Atmel Stereo Amplifier ATR7040 User Manual

Features  
Frequency Range 5 GHz to 6 GHz  
Pout 25 dBm at 5.8 GHz  
Gain Typically 30 dB  
Pin Typically 0 dBm  
VCC 2.7V to 3.8V  
Power Consumption in Power-down Mode Typically < 1 µA  
Package: QFN16 3 mm × 3 mm  
5.8 GHz WDCT  
Power Amplifier  
Benefits  
Biasing Control Extends Battery Time  
Simple Input and Output Matching  
Only One Single Supply Required  
No High-side Switching Transistor Required  
ATR7040  
1. Description  
1.1  
Process  
This 5-GHz power amplifier (PA) is designed using Atmel’s Silicon-Germanium (SiGe)  
process and provides high efficiency.  
1.2  
Circuitry  
The PA, ATR7040, consists of a three-stage amplifier with a typical output power of  
25 dBm. The output stage was implemented using an open-collector structure. Power  
up, power down, and output level are controlled at bias control pin 6 (Vctl).  
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ATR7040  
2. Pin Configuration  
Figure 2-1. Pinning QFN16  
16 15 14 13  
NC  
RFOUT/VCC3  
RFOUT/VCC3  
NC  
12 NC  
11 NC  
1
2
3
4
ATR7040  
10 RFIN  
GND on the  
PADDLE  
9
NC  
5
6
7
8
Table 2-1.  
Pin Description  
Pin  
Symbol  
NC  
Function  
Not connected(1)  
1
2
RFOUT  
RFOUT  
NC  
RF output and supply voltage for output amplifier stage  
RF output and supply voltage for output amplifier stage  
Not connected(1)  
3
4
5
NC  
Not connected(1)  
6
VCC2  
VCC1  
NC  
Supply voltage for second amplifier stage  
Supply voltage for first amplifier stage  
Not connected(1)  
7
8
9
NC  
Not connected(1)  
10  
RFIN  
NC  
RF input  
Not connected(1)  
11  
12  
NC  
Not connected(1)  
13  
VCTL  
GND  
VCC_CTL  
NC  
Control voltage for power ramping  
Ground  
14  
15  
Supply voltage for biasing control block  
Not connected(1)  
16  
PADDLE  
Ground  
Note:  
1. Pin can be connected to paddle for increased GND area  
3
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3. Absolute Maximum Ratings  
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating  
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this  
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.  
Parameters  
Symbol  
VCC  
Icc  
Value  
Unit  
V
Supply voltage  
5
400  
Supply current  
mA  
°C  
Junction temperature  
Storage temperature  
Input RF power  
Control voltage  
Tj  
150  
TStg  
Pin  
–40 to +125  
10  
°C  
dBm  
V
Vctl  
2.5  
Note:  
The part may not survive all maximums applied simultaneously.  
Electrostatic sensitive device.  
Observe precautions for handling.  
4. Thermal Resistance  
Parameters  
Symbol  
Value  
Unit  
Junction ambient package QFN16, 3 × 3,  
slug soldered on PCB  
RthJA  
40  
K/W  
5. Operating Range  
Parameters  
Symbol  
VCC  
Value  
Unit  
V
Supply voltage  
2.7 to 3.8  
Operating frequency range  
Ambient temperature range  
fin  
5100 to 5900  
–25 to +75  
MHz  
°C  
Tamb  
4
ATR7040  
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ATR7040  
6. Electrical Characteristics  
Operating conditions: VCC = 3.6V, Vctl = 1.5V, input frequency = 5.8 GHz, input power 0 dBm, pulsed mode, duty cycle 10%, ton = 1 ms,  
Tamb = 25°C, unless otherwise specified.  
No.  
Parameters  
Test Conditions  
Pin  
Symbol  
Min.  
5100  
2.7  
Typ.  
Max.  
5900  
3.8  
Unit  
Depends on external  
circuitry  
1.0  
Frequency range  
MHz  
1.1  
1.2  
1.3  
1.4  
Supply voltage  
Vcc  
Pin  
Psat  
Pd  
3.6  
0
V
dBm  
dBm  
dB  
V
Input power  
Saturated power output  
Output power deviation  
25  
–2  
+2  
1.7  
0.2  
PA operating mode  
Power-down mode  
PA on  
Vctl  
Vctl  
Ictl  
1.0  
1.5  
Control voltage range  
V
1.6  
1.7  
1.8  
Control input current  
Input return loss  
Isolation  
5
90  
–7  
35  
µA  
dB  
dB  
With external matching  
Vctl 0.2V  
10  
–6  
ISOr  
PAE  
Icc  
33  
At power saturation,  
Pin = 0 dBm  
1.9  
Power added efficiency  
35  
250  
1
%
mA  
µA  
%
1.10 Current consumption  
For 25 dBm output power  
Current consumption in  
1.11  
Vctl 0.2V  
Icc  
power-down mode  
1.12 Duty cycle of operation  
At saturated output power  
100  
7. Application Circuit  
Figure 7-1. Application Circuit  
VCC  
C6  
slug  
8
7
6
5
L1  
9
4
3
RFIN  
TRL1  
10  
11  
12  
C3  
RFOUT  
TRL2  
2
1
C1  
C2  
13 14 15 16  
VCTL  
VCC  
5
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8. Diagrams  
Figure 8-1. Output Power, Efficiency and Supply Currents Versus Input Frequency  
Pin = 0 dBm, Vcc = 3.6V, Vctl = 1.4V  
40  
35  
30  
25  
20  
15  
400  
350  
300  
250  
200  
150  
10 0  
50  
PAE (%)  
Iges (mA)  
Pout (dBm)  
10  
0
5600  
5650  
5700  
5750  
5800  
5850  
5900  
5950  
6000  
Frequency (MHz)  
Figure 8-2. Output Power, Gain, Efficiency and Supply Currents Versus Input Power  
Freq = 5800 MHz, Vcc = 3.6V, Vctl = 1.4V  
40  
30  
20  
10  
400  
350  
300  
250  
200  
150  
10 0  
50  
Gain (dB)  
PAE (%)  
0
-10  
-20  
-30  
Iges (mA)  
Pout (dBm)  
0
-20  
-15  
-10  
-5  
0
5
Pin (dBm)  
Figure 8-3. Output Power, Efficiency and Supply Currents Versus Operating Voltage  
Freq = 5800 MHz, Pin = 0 dBm, Vctl = 1.5V  
40  
35  
30  
25  
20  
15  
450  
400  
350  
300  
250  
200  
150  
10 0  
50  
PAE (%)  
Iges (mA)  
Pout (dBm)  
10  
0
2.5  
3.0  
3.5  
4.0  
Vcc (V)  
6
ATR7040  
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ATR7040  
9. Ordering Information  
Extended Type Number  
Package  
Remarks  
ATR7040-PVPG  
QFN16, 3 × 3  
QFN16, 3 × 3  
Taped and reeled, MOQ 2000, Pb-free  
Taped and reeled, MOQ 8000, Pb-free  
ATR7040-PVQG  
10. Package Information  
Package: QFN 16 - 3x3  
Exposed pad 1.7x1.7  
(acc. JEDEC OUTLINE No. MO-220)  
Dimensions in mm  
3
0.9 0.1  
+0  
1.7  
Not indicated tolerances 0.05  
0.05  
-0.05  
16  
1
13  
8
16  
5
12  
9
1
technical drawings  
according to DIN  
specifications  
4
4
0.5 nom.  
1.5  
Drawing-No.: 6.543-5115.01-4  
Issue: 1; 07.03.05  
Assembly Chip PAC  
7
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