USB2601/USB2602
4th Generation USB 2.0 Flash
Media Controller with
Integrated Card Power FETs &
HS Hub
Datasheet
PRODUCT FEATURES
—
768 Bytes of internal SRAM for general purpose
scratchpad or program execution while re-flashing
external ROM
Hub Controller
„
Provides Three USB 2.0 Downstream Ports via
internal USB 2.0 Hub
—
—
—
—
Double Buffered Bulk Endpoint
—
Multi Transaction Translator for FS/LS devices attached
Bi-directional 512 Byte Buffer for Bulk Endpoint
64 Byte RX Control Endpoint Buffer
64 Byte TX Control Endpoint Buffer
Flash Media Controller
Complete System Solution for interfacing
„
„
Internal Program Memory Interface
—
TM
TM
1
SmartMedia
(SM) or xD Picture Card
(xD) ,
64K Byte Internal Code Space
TM
Memory Stick
(HSMS), Memory Stick PRO (MSPRO), MS Duo
Secure Digital (SD), Mini-Secure Digital (Mini-SD),
(MS), High Speed Memory Stick
„
„
„
On Board 24MHz Crystal Driver Circuit
TM
,
Can be clocked by an external 24MHz source
TM
On-Chip 1.8V Regulator for Low Power Core
Operation
TransFlash (SD), MultiMediaCard
Reduced Size MultiMediaCard (RS-MMC), NAND
Flash, Compact Flash (CF) and CF Ultra I & II,
and CF form-factor ATA hard drives to USB 2.0 bus
(MMC),
TM
TM
„
„
Internal PLL for 480MHz USB 2.0 Sampling,
Configurable MCU clock
—
Supports USB Bulk Only Mass Storage Compliant
11 GPIOs for special function use: LED indicators,
button inputs, power control to memory devices, etc.
—
Bootable BIOS
„
Support for simultaneous operation of all above
devices. (only one at a time of each of the following
groups supported: CF or ATA drive, SM or XD or
NAND, SD or MMC)
Inputs capable of generating interrupts with either edge
sensitivity
„
Configuration of Hub and Flash Media features
controlled either by internal defaults or via single
external EEPROM. User configurable features:
„
„
„
„
„
„
„
On-Chip 4-Bit High Speed Memory Stick and MS
PRO Hardware Circuitry
—
—
—
—
—
—
—
—
—
Full or Partial Card compliance checking
LUN configuration and assignment
Write Protect Polarity
Cover Switch operation for xD compliance
Inquiry Command operation
SD Write Protect operation
Older CF card support
Force USB 1.1 reporting
Internal or External Power FET operation
On-Chip firmware reads and writes High Speed
Memory Stick and MS PRO
1-bit ECC correction performed in hardware for
maximum efficiency
Hardware support for SD Security Command
Extensions
3.3 Volt I/O with 5V input tolerance on VBUS, Port
Power and Over-Current Sense pins
„
„
„
Compatible with Microsoft WinXP, WinME, Win2K
SP3&4, Apple OS10 and Linux Multi-LUN Mass
Storage Class Drivers
On-chip power FETs for supplying flash media card
power with minimum board components
Win2K, Win98/98SE and Apple OS8.6 and OS9
Multi-LUN Mass Storage Class Drivers are available
from SMSC
8051 8 bit microprocessor
—
—
Provides low speed control functions
30 MHz execution speed at 4 cycles per instruction
average
128 Pin TQFP Package (1.0mm height, 14mm
x14mm footprint); lead-free RoHS compliant package
also available
—
12K Bytes of internal SRAM for general purpose
scratchpad
1.xD Picture Card not applicable to USB2601
SMSC USB2601/USB2602
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4th Generation USB 2.0 Flash Media Controller with Integrated Card Power FETs & HS Hub
Datasheet
Table of Contents
Chapter 1 General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Chapter 2 Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Chapter 3 Pin Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Chapter 4 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Chapter 5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Chapter 6 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
PIN Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Buffer Type Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Chapter 7 DC Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Maximum Guaranteed Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Chapter 8 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Package Thermal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Chapter 9 GPIO Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
SMSC USB2601/USB2602
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List of Figures
Figure 4.1 USB2601/USB2602 128-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 5.1 USB2601/USB2602 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 7.1 Supply Rise Time Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 8.1 USB2601/USB2602 128-Pin TQFP Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
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List of Tables
Table 3.1 USB2601/USB2602 128-Pin TQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 3.2 USB2601/USB2602 128-Pin TQFP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 6.1 USB2601/USB2602 Buffer Type Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 8.1 USB2601/USB2602 128-Pin TQFP Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 8.2 128-Pin TQFP Package Thermal Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 9.1 GPIO Usage (ROM Rev -01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
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Chapter 1 General Description
The USB2601/USB2602 is an Integrated “combo” High-Speed USB hub and Flash Media Controller.
The Flash media controller permanently resides on Port 1 of the Integrated USB hub.
1.1
High-Speed Hub
The integrated SMSC Hub is fully compliant with the USB 2.0 Specification and will attach to a USB
host as a Full-Speed Hub or as a Full-/High-Speed Hub. The Hub supports Low-Speed, Full-Speed,
and High-Speed (if operating as a High-Speed Hub) downstream devices on all of the enabled
downstream ports.
A dedicated Transaction Translator (TT) is available for each downstream facing port. This architecture
ensures maximum USB throughput for each connected device when operating with mixed-speed
peripherals.
The Hub works with an external USB power distribution switch device to control V
downstream ports, and to limit current and sense over-current conditions.
switching to
BUS
All required resistors on the USB ports are integrated into the Hub. This includes all series termination
resistors on D+ and D– pins and all required pull-down and pull-up resistors on D+ and D– pins. The
over-current sense inputs for the downstream facing ports have internal pull-up resistors.
Throughout this document the upstream facing port of the hub will be referred to as the upstream port,
and the downstream facing ports will be called the downstream ports.
Three externally available ports are available for general USB device connectivity.
1.2
Flash Media Controller
The Bulk Only Mass Storage Class Peripheral Controller intended for supporting CompactFlash (CF
and CF Ultra I/II) in True IDE Mode only, SmartMedia (SM) and xD cards, Memory Stick (MS), Memory
Stick DUO (MSDUO) and Memory Stick Pro (MSPRO), Secure Digital (SD), and MultiMediaCard
(MMC) flash memory devices. It provides a single chip solution for the most popular flash memory
cards in the market.
The device consists of buffers, Fast 8051 microprocessor with expanded scratchpad, and program
SRAM, and CF, MS, SM and SD controllers. The SD controller supports both SD and MMC devices.
SM controller supports both SM and xD cards.
12K bytes of scratchpad SRAM and 768 Bytes of program SRAM are also provided.
Eleven GPIO pins are provided for indicators, external serial EEPROM for OEM ID and system
configuration information, and other special functions.
Internal power FETs are provided to directly supply power to the xD/SM, MMC/SD and MS/MSPro
cards.
The internal ROM program is capable of implementing any combination of single or multi-LUN
CF/SD/MMC/SM/MS reader functions with individual card power control and activity indication. SMSC
also provides licenses** for Win98 and Win2K drivers and setup utilities. Note: Please check with
SMSC for precise features and capabilities for the current ROM code release.
*Note: In order to develop, make, use, or sell readers and/or other products using or incorporating any of the SMSC devices made
the subject of this document or to use related SMSC software programs, technical information and licenses under patent and other
intellectual property rights from or through various persons or entities, including without limitation media standard companies,
forums, and associations, and other patent holders may be required. These media standard companies, forums, and associations
include without limitation the following: Sony Corporation (Memory Stick, Memory Stick Pro); SD3 LLC (Secure Digital); MultiMedia
Card Association (MultiMediaCard); the SSFDC Forum (SmartMedia); the Compact Flash Association (Compact Flash); and Fuji
Photo Film Co., Ltd., Olympus Optical Co., Ltd., and Toshiba Corporation (xD-Picture Card). SMSC does not make such licenses
or technical information available; does not promise or represent that any such licenses or technical information will actually be
obtainable from or through the various persons or entities (including the media standard companies, forums, and associations), or
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with respect to the terms under which they may be made available; and is not responsible for the accuracy or sufficiency of, or
otherwise with respect to, any such technical information.
SMSC's obligations (if any) under the Terms of Sale Agreement, or any other agreement with any customer, or otherwise, with
respect to infringement, including without limitation any obligations to defend or settle claims, to reimburse for costs, or to pay
damages, shall not apply to any of the devices made the subject of this document or any software programs related to any of such
devices, or to any combinations involving any of them, with respect to infringement or claimed infringement of any existing or future
patents related to solid state disk or other flash memory technology or applications ("Solid State Disk Patents"). By making any
purchase of any of the devices made the subject of this document, the customer represents, warrants, and agrees that it has
obtained all necessary licenses under then-existing Solid State Disk Patents for the manufacture, use and sale of solid state disk
and other flash memory products and that the customer will timely obtain at no cost or expense to SMSC all necessary licenses
under Solid State Disk Patents; that the manufacture and testing by or for SMSC of the units of any of the devices made the subject
of this document which may be sold to the customer, and any sale by SMSC of such units to the customer, are valid exercises of
the customer's rights and licenses under such Solid State Disk Patents; that SMSC shall have no obligation for royalties or otherwise
under any Solid State Disk Patents by reason of any such manufacture, use, or sale of such units; and that SMSC shall have no
obligation for any costs or expenses related to the customer's obtaining or having obtained rights or licenses under any Solid State
Disk Patents.
SMSC MAKES NO WARRANTIES, EXPRESS, IMPLIED, OR STATUTORY, IN REGARD TO INFRINGEMENT OR OTHER
VIOLATION OF INTELLECTUAL PROPERTY RIGHTS. SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES
AGAINST INFRINGEMENT AND THE LIKE.
No license is granted by SMSC expressly, by implication, by estoppel or otherwise, under any patent, trademark, copyright, mask
work right, trade secret, or other intellectual property right.
**To obtain this software program the appropriate SMSC Software License Agreement must be executed and in effect. Forms of
these Software License Agreements may be obtained by contacting SMSC.
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Chapter 2 Acronyms
SM: SmartMedia
SMC: SmartMedia Controller
FM: Flash Media
FMC: Flash Media Controller
CF: CompactFlash
CFC: CompactFlash Controller
SD: Secure Digital
SDC: Secure Digital Controller
MMC: MultiMediaCard
MS: Memory Stick
MSC: Memory Stick Controller
TPC: Transport Protocol Code.
ECC: Error Checking and Correcting
CRC: Cyclic Redundancy Checking
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Chapter 3 Pin Table
3.1
128-Pin TQFP Package
Table 3.1 USB2601/USB2602 128-Pin TQFP Package
UPSTREAM USB 2.0 INTERFACE (3 PINS)
USBUP_DM VBUS_DET
3-PORT USB 2.0 INTERFACE (16 PINS)
USBUP_DP
USBDN_DP2
USBDN_DP4
PRTPWR4
GR2_N
USBDN_DM2
USBDN_DM4
OCS2_N
USBDN_DP3
PRTPWR2
OCS3_N
USBDN_DM3
PRTPWR3
OCS4_N
GR3_N
GR4_N
PRTPWR_POL
CompactFlash INTERFACE (28 Pins)
CF_D0
CF_D4
CF_D1
CF_D5
CF_D2
CF_D6
CF_D3
CF_D7
CF_D8
CF_D9
CF_D10
CF_D14
CF_IRQ
CF_nCS1
CF_nCD1
CF_D11
CF_D12
CF_nIOR
CF_IORDY
CF_SA1
CF_D13
CF_nIOW
CF_nCS0
CF_SA2
CF_D15
CF_nRESET
CF_SA0
CF_nCD2
SmartMedia INTERFACE (17 Pins)
SM_D0
SM_D4
SM_D1
SM_D5
SM_D2
SM_D3
SM_D7
SM_D6
SM_nRE
SM_nCE
SM_ALE
SM_nWP
SM_nWPS
SM_CLE
SM_nB/R
SM_nWE
SM_nCD
Memory Stick INTERFACE (7 Pins)
MS_BS
MS_D1
MS_SDIO/MS_D0
MS_D2
MS_SCLK
MS_INS
MS_D3
SD INTERFACE (7 Pins)
SD_CMD
SD_DAT2
SD_CLK
SD_DAT0
SD_nWP
SD_DAT1
SD_DAT3
SMSC USB2601/USB2602
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Table 3.1 USB2601/USB2602 128-Pin TQFP Package
MISC (23 Pins)
GPIO1
GPIO6
GPIO2
GPIO7
GPIO4
GPIO5
GPIO9
GPIO8/CRD_PWR0
GPIO12
GPIO10/CRD_PWR1
GPIO14
GPIO11/CRD_PWR2
GPIO15
GPIO13
RESET_N
XTAL2
TEST
ATEST
RBIAS
XTAL1/CLKIN
SEL_CLKDRV
CLK_SEL0
CLK_SEL1
ANALOG POWER (5 Pins)
(3)VDDA33
(5)VDD33
VDD33PLL
VDD18PLL
DIGITAL, POWER & GROUND (22 Pins)
(11)VSS (3)VDD18
(3)NC
Total 128
3.2
128-Pin List Table
Table 3.2 USB2601/USB2602 128-Pin TQFP
PI
N
#
NAME
M
A
PI
N #
NAME
MA PIN
#
NAME
MA
PIN
#
NAME
MA
1
PRTPWR_
POL
-
33
VDD18
-
65
CF_D7
8
97
SD_nWP
-
2
3
4
5
6
PRTPWR2
OCS2_N
12
-
34
35
36
37
38
VSS
VSS
-
-
66
67
68
69
70
CF_D15
CF_nCS0
CF_nCS1
CF_nIOR
CF_nIOW
8
8
8
8
8
98
99
SD_DAT1
SD_DAT0
SD_CLK
VDD33
8
8
8
-
PRTPWR3
OCS3_N
12
-
SM_nWPS
SM_CLE
SM_nCE
-
100
101
102
8
8
PRTPWR4
12
GPIO11/
CRD_PWR2
-
7
8
9
OCS4_N
VDDA33
-
-
39
40
41
SM_ALE
SM_nRE
SM_nWE
8
8
8
71
72
73
CF_IRQ
CF_nRESET
CF_IORDY
8
8
8
103
104
105
SD_CMD
SD_DAT3
SD_DAT2
8
8
8
USBDN_D
P3
--
10
USBDN_D
M3
-
42
SM_nB/R
VDD33
-
74
CF_SA2
8
106
GPIO4
8
11
12
VSS
-
-
43
44
-
-
75
76
CF_SA1
CF_SA0
8
8
107
108
GPIO5
VSS
8
-
USBDN_D
M4
GPIO10/
CRD_PWR1
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Table 3.2 USB2601/USB2602 128-Pin TQFP (continued)
PI
N
#
NAME
M
A
PI
N #
NAME
MA PIN
#
NAME
MA
PIN
#
NAME
MA
13
USBDN_D
P4
-
45
SM_nWP
8
77
CF_D0
8
109
VSS
-
14
15
16
17
VDDA33
VDD33
GR2_N
GR3_N
-
-
46
47
48
49
SM_D0
SM_D1
SM_D7
SM_D2
8
8
8
8
78
79
80
81
CF_D1
CF_D8
CF_D2
CF_D9
8
8
8
8
110
111
112
113
USBUP_DM
USBUP_DP
VDDA33
-
-
-
-
8
8
USBDN_DP
2
18
GR4_N
8
50
SM_D6
8
82
CF_D10
8
114
USBDN_DM
2
-
19
20
GPIO6
8
8
51
52
SM_D3
SM_D5
8
8
83
84
CF_nCD2
VSS
-
-
115
116
VSS
-
MS_BS
VBUS_
DET
12
21
22
MS_D1
8
8
53
54
SM_D4
8
-
85
86
VSS
-
-
117
118
VSS
-
-
MS_SDIO/
MS_D0
SM_nCD
VDD18
RESET_N
23
24
25
26
MS_D2
MS_INS
MS_D3
8
-
55
56
57
58
GPIO9
CF_nCD1
CF_D3
8
-
87
88
89
90
VDD33
GPIO1
GPIO2
GPIO7
-
119
120
121
122
VDD18
TEST
VSS
-
-
-
-
8
8
8
8
8
8
8
MS_
SCLK
CF_D11
XTAL2
27 SEL_CLKD
RV
-
-
59
60
CF_D4
8
8
91
92
VDD33
-
-
123
124
XTAL1/
CLKIN
-
-
28
CLK_SEL1
CF_D12
GPIO8/
VDD18PLL
CRD_PWR0
29
30
31
32
CLK_SEL0
-
-
-
-
61
62
63
64
CF_D5
CF_D13
CF_D6
8
8
8
8
93
94
95
96
GPIO12
GPIO13
GPIO14
GPIO15
8
8
8
8
125
126
127
128
VDD33PLL
ATEST
RBIAS
VSS
-
-
-
-
NC
NC
NC
CF_D14
Notes:
„
„
RBIAS is connected to the Analog Ground plane VSS via a resistor.
When the internal 1.8V regulators are enabled, VDD18 (Pin 86) & VDD18PLL (Pin 124), MUST
have a 10uf +/- 20%, (equivalent series resistance (ESR) <0.1ohm) bypass capacitor to VSS.
These capacitors must be as close to the pins as possible.
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Chapter 4 Pin Configuration
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Chapter 5 Block Diagram
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Figure 5.1 USB2601/USB2602 Block Diagram
SMSC USB2601/USB2602
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Chapter 6 Pin Descriptions
This section provides a detailed description of each signal. The signals are arranged in functional
groups according to their associated interface.
The “n” or “_N” symbol in the signal name indicates that the active, or asserted state occurs when the
signal is at a low voltage level. When “n” is not present before the signal name (or “_N” after the signal
name), the signal is asserted when at the high voltage level.
The terms assertion and negation are used exclusively. This is done to avoid confusion when working
with a mixture of “active low” and “active high” signal. The term assert, or assertion indicates that a
signal is active, independent of whether that level is represented by a high or low voltage. The term
negate, or negation indicates that a signal is inactive.
6.1
PIN Descriptions
BUFFER
TYPE
NAME
SYMBOL
DESCRIPTION
UPSTREAM USB INTERFACE
USB Bus Data
USBUP_DM
USBUP_DP
IO-U
These pins connect to the Upstream USB bus data
signals.
Detect Upstream
VBUS Power
VBUS_DET
I/O12
Detects state of Upstream VBUS power. The SMSC
Hub monitors VBUS_DET to determine when to assert
the internal D+ pull-up resistor (signalling a connect
event).
When designing a detachable hub, this pin must be
connected to the VBUS power pin of the USB port that
is upstream of the hub.
For self-powered applications with a permanently
attached host, this pin must be pulled-up to either 3.3V
or 5.0V (typically VDD33).
3-PORT USB INTERFACE
USB Bus Data
USBDN_DM
[4:2]
IO-U
These pins connect to the Downstream USB bus data
signals.
USBDN_DP
[4:2]
USB Power Enable
PRTPWR[4:2]
PRTPWR_POL
I/O12
Enables power to USB peripheral devices
(downstream).
The active signal level of the PRTPWR[4:2] pins is
determined by the Power Polarity Strapping function of
the PRTPWR_POL pin.
Port Power Polarity
Strapping
I/O12
Port Power Polarity strapping determination for the
active signal polarity of the PRTPWR[4:2] pins.
While RESET_N is asserted, the logic state of this pin
will (though the use of internal combinatorial logic)
determine the active state of the PRTPWR[4:2] pins in
order to ensure that downstream port power is not
inadvertently enabled to inactive ports during a
hardware reset.
‘1’ = PRTPWR[4:2] pins have an active ‘high’ polarity
‘0’ = PRTPWR[4:2] pins have an active ‘low’ polarity
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BUFFER
TYPE
NAME
SYMBOL
DESCRIPTION
Over Current Sense
OCS[4:2]_N
IPU
Input from external current monitor indicating an over-
current condition. {Note: Contains internal pull-up to
3.3V supply}
Green LED
GR[4:2]_N
I/O8
Green indicator LED for ports 2, 3 and 4. Will be active
low when LED support is enabled via EEPROM or
SMBus.
CompactFlash (In True IDE mode) INTERFACE
CF Chip Select 1
CF Chip Select 0
CF_nCS1
O8PU
O8PU
O8
This pin is the active low chip select 1 signal for the CF
ATA device
CF_nCS0
CF_SA2
CF_SA1
CF_SA0
CF_IRQ
This pin is the active low chip select 0 signal for the task
file registers of CF ATA device in the True IDE mode.
CF Register
Address 2
This pin is the register select address bit 2 for the CF
ATA device.
CF Register
Address 1
O8
This pin is the register select address bit 1 for the CF
ATA device
CF Register
Address 0
O8
This pin is the register select address bit 0 for the CF
ATA device.
CF Interrupt
IPD
This is the active high interrupt request signal from the
CF device.
CF Data [15:8]
CF_D[15:8]
I/O8PD
The bi-directional data signals CF_D15-CF_D8 in True
IDE mode data transfer.
In the True IDE Mode, all of task file register operation
occur on the CF_D[7:0], while the data transfer is on
CF_D[15:0].
The bi-directional data signal has an internal weak pull-
down resistor.
CF Data [7:0]
CF_D[7:0]
I/O8PD
The bi-directional data signals CF_D7-CF_D0 in the
True IDE mode data transfer.
In the True IDE Mode, all of task file register operation
occur on the CF_D[7:0], while the data transfer is on
CF_D[15:0].
The bi-directional data signal has an internal weak pull-
down resistor.
IO Ready
CF_IORDY
CF_nCD2
IPU
IPU
This pin is active high input signal.
This pin has an internally controlled weak pull-up
resistor.
CF
This card detection pin is connected to the ground on
the CF device, when the CF device is inserted.
Card Detection2
This pin has an internally controlled weak pull-up
resistor.
CF
CF_nCD1
IPU
O8
This card detection pin is connected to ground on the
CF device, when the CF device is inserted.
Card Detection1
This pin has an internally controlled weak pull-up
resistor.
CF
CF_nRESET
This pin is an active low hardware reset signal to CF
device.
Hardware Reset
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BUFFER
TYPE
NAME
SYMBOL
DESCRIPTION
CF
IO Read
CF_nIOR
O8
This pin is an active low read strobe signal for CF
device.
CF
CF_nIOW
SM_nWP
O8
This pin is an active low write strobe signal for CF
device.
IO Write Strobe
SmartMedia INTERFACE
SM
Write Protect
O8PD
O8PD
O8PD
I/O8PD
08PU
This pin is an active low write protect signal for the SM
device.
This pin has a weak pull-down resistor that is
permanently enabled
SM
SM_ALE
SM_CLE
SM_D[7:0]
SM_nRE
This pin is an active high Address Latch Enable signal
for the SM device.
Address Strobe
This pin has a weak pull-down resistor that is
permanently enabled
SM
This pin is an active high Command Latch Enable signal
for the SM device.
Command Strobe
This pin has a weak pull-down resistor that is
permanently enabled
SM
Data[7:0]
These pins are the bi-directional data signal SM_D7-
SM_D0.
The bi-directional data signal has an internal weak pull-
down resistor.
SM
Read Enable
This pin is an active low read strobe signal for SM
device.
When using the internal FET, this pin has an internal
weak pull-up resistor that is tied to the output of the
internal Power FET.
08
If an external FET is used (Internal FET is disabled),
then the internal pull-up is not available (external pull-
ups must be used, and should be connected to the
applicable Card Power Supply).
SM
Write Enable
SM_nWE
O8PU
This pin is an active low write strobe signal for SM
device.
When using the internal FET, this pin has an internal
weak pull-up resistor that is tied to the output of the
internal Power FET.
08
IPU
I
If an external FET is used (Internal FET is disabled),
then the internal pull-up is not available (external pull-
ups must be used, and should be connected to the
applicable Card Power Supply).
SM
SM_nWPS
SM_nB/R
A write-protect seal is detected, when this pin is low.
Write Protect Switch
This pin has an internally controlled weak pull-up
resistor.
SM
This pin is connected to the BSY/RDY pin of the SM
device.
Busy or Data Ready
An external pull-up resistor is required on this signal.
The pull-up resistor must be pulled up to the same
power source that powers the SM/NAND flash device.
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BUFFER
TYPE
NAME
SYMBOL
DESCRIPTION
SM
Chip Enable
SM_nCE
O8PU
This pin is the active low chip enable signal to the SM
device.
When using the internal FET, this pin has an internal
weak pull-up resistor that is tied to the output of the
internal Power FET.
08
If an external FET is used (Internal FET is disabled),
then the internal pull-up is not available (external pull-
ups must be used, and should be connected to the
applicable Card Power Supply).
SM
SM_nCD
MS_BS
IPU
This is the card detection signal from SM device to
indicate if the device is inserted.
Card Detection
This pin has an internally controlled weak pull-up
resistor.
MEMORY STICK INTERFACE
MS
O8
This pin is connected to the BS pin of the MS device.
Bus State
It is used to control the Bus States 0, 1, 2 and 3 (BS0,
BS1, BS2 and BS3) of the MS device.
MS
System
Data In/Out
MS_SDIO/MS_
D0
I/O8PD
This pin is a bi-directional data signal for the MS device.
Most significant bit (MSB) of each byte is transmitted
first by either MSC or MS device.
The bi-directional data signal has an internal weak pull-
down resistor.
MS
MS_D1
MS_D[3:2]
MS_INS
I/O8PD
I/O8PD
IPU
This pin is a bi-directional data signal for the MS device.
System Data In/Out
This pin has internally controlled weak pull-up and pull-
down resistors for various operational modes.
MS
System
Data In/Out
This pin is a bi-directional data signal for the MS device.
The bi-directional data signal has an internal weak pull-
down resistor.
MS
This pin is the card detection signal from the MS device
to indicate, if the device is inserted.
Card Insertion
This pin has an internally controlled weak pull-up
resistor.
MS
System CLK
MS_SCLK
O8
This pin is an output clock signal to the MS device.
The clock frequency is software configurable.
SD INTERFACE
SD
Data [3:0]
SD_DAT[3:0]
SD_CLK
I/O8PU
These are bi-directional data signals.
These pins have internally controlled weak pull-up
resistors.
SD Clock
O8
This is an output clock signal to SD/MMC device.
The clock frequency is software configurable.
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BUFFER
TYPE
NAME
SYMBOL
DESCRIPTION
SD Command
SD_CMD
I/O8PU
This is a bi-directional signal that connects to the CMD
signal of SD/MMC device.
This pin has an internally controlled weak pull-up
resistor.
SD
SD_nWP
IPD
This pin is an input signal with an internal weak pull-
down.
Write Protected
This pin has an internally controlled weak pull-down
resistor.
MISC
General Purpose
I/O
GPIO1
GPIO2
GPIO4
GPIO5
GPIO6
I/O8
I/O8
I/O8
I/O8
IPU
This pin may be used either as input, edge sensitive
interrupt input, or output.
General Purpose
I/O
This pin may be used either as input, edge sensitive
interrupt input, or output.
General Purpose
I/O
This pin may be used either as input, edge sensitive
interrupt input, or output.
General Purpose
I/O
This pin may be used either as input, edge sensitive
interrupt input, or output.
GPIO6
This pin has an internal weak pull-up resistor that is
enabled or disabled by the state of RESET_N.
The pull-up is enabled when RESET_N is active.
The pull-up is disabled, when the RESET_N is inactive
(some clock cycles later, after the rising edge of
RESET_N).
The state of this pin is latched internally on the rising
edge of RESET_N to determine if internal or external
program memory is used.
The state latched is stored in ROMEN bit of GPIO_IN1
register.
I/O8
After the rising edge of RESET_N, this pin may be used
as GPIO6.
When this pin is left unconnected or pulled high by a
weak pull-up resistor, the USB2601/USB2602 uses the
internal ROM for program execution.
This pin may be used either as input, edge sensitive
interrupt input, or output.
General Purpose
I/O
GPIO7
I/O8
I/O8
This pin may be used either as input, edge sensitive
interrupt input, or output.
General Purpose
GPIO8/
CRD_PWR0
GPIO: This pin may be used either as input, edge
sensitive interrupt input, or output.
I/O
Or
CRD_PWR: Card Power drive of 3.3V @ 100mA.
Card Power
General Purpose
I/O
GPIO9
I/O8
I/O8
This pin may be used either as input, edge sensitive
interrupt input, or output.
General Purpose
GPIO10/
CRD_PWR1
GPIO: This pin may be used either as input, edge
sensitive interrupt input, or output.
I/O
Or
CRD_PWR: Card Power drive of 3.3V @ 100mA.
Card Power
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BUFFER
TYPE
NAME
SYMBOL
DESCRIPTION
General Purpose
GPIO11/
CRD_PWR2
I/O8
GPIO: These pins may be used either as input, edge
sensitive interrupt input, or output.
I/O
Or
CRD_PWR: Card Power drive of 3.3V @ 200mA.
These pins may be used either as input, or output.
Card Power
General Purpose
I/O
GPIO[15:12]
RESET_N
TEST
I/O8
IS
RESET input
This active low signal is used by the system to reset the
chip. The active low pulse should be at least 1μs wide.
TEST Input
IPD
I
Used for testing the IC. User must treat either as a no-
connect, or connect to the ground.
USB Transceiver
Bias
RBIAS
A 12.0kΩ, ± 1.0% resistor is attached from VSS to this
pin, in order to set the transceiver’s internal bias
currents.
Analog Test
ATEST
AIO
This signal is used for testing the analog section of the
chip and should be connected to VDDA33 for normal
operation.
Crystal
Input/External Clock
Input
XTAL1/
CLKIN
ICLKx
24MHz Crystal or external clock input.
This pin can be connected to one terminal of the crystal
or can be connected to an external 24MHz clock when
a crystal is not used.
Note:
The ‘SEL_CLKDRV and CLK_SEL[1:0]’ pins
will be sampled while RESET_N is asserted,
and the value will be latched upon RESET_N
negation. This will determine the clock source
and value.
Crystal Output
XTAL2
OCLKx
I/O8PD
24MHz Crystal
This is the other terminal of the crystal, or left open
when an external clock source is used to drive
XTAL1/CLKIN. It may not be used to drive any external
circuitry other than the crystal circuit.
Select Clock Drive
SEL_CLKDRV
SEL_CLKDRV. During RESET_N assertion, this pin will
select the operating clock mode (crystal or externally
driven clock source), and a weak pull-down resistor is
enabled. When RESET_N is negated, the value will be
internally latched and the internal pull-down will be
disabled.
‘0’ = Crystal operation (24MHz)
‘1’ = Externally driven clock source (24MHz)
Clock Select
CLK_SEL[1:0]
I/O8PD
SEL[1:0]. During RESET_N assertion, these pins will
select the operating frequency of the external clock, and
the corresponding weak pull-down resistors are
enabled. When RESET_N is negated, the value on
these pins will be internal latched and the internal pull-
downs will be disabled.
SEL[1:0] = ‘00’. 24MHz
SEL[1:0] = ‘01’. RESERVED
SEL[1:0] = ‘10’. RESERVED
SEL[1:0] = ‘11’. RESERVED
ANALOG POWER
1.8V PLL Power
3.3V PLL Power
VDD18PLL
VDD33PLL
1.8V Output from the internal 1.8V PLL regulator
3.3V Input to the internal 1.8V PLL regulator.
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BUFFER
TYPE
NAME
SYMBOL
DESCRIPTION
3.3v Analog PHY Power
3.3V Analog Power
VDDA33
DIGITAL POWER, GROUNDS, and NO CONNECTS
1.8V Digital Core
Power
VDD18
VDD33
+1.8V Core power
All VDD18 pins must be connected together on the
circuit board.
3.3v Power & &
Voltage Regulator
Input
3.3V Power & Regulator Input.
Pin 87 supplies 3.3V power to the internal 1.8V
regulator.
Ground
VSS
NC
Ground Reference
No Connect
No Connect. No trace or signal should be
routed/attached to these pins.
Notes:
„
Hot-insertion capable card connectors are required for all flash media. It is required for SD
connector to have Write Protect switch. This allows the chip to detect MMC card.
„
nMCE is normally asserted except when the 8051 is in standby mode.
6.2
Buffer Type Descriptions
Table 6.1 USB2601/USB2602 Buffer Type Descriptions
BUFFER
DESCRIPTION
I
Input
IPU
Input with internal weak pull-up resistor.
IPD
Input with internal weak pull-down resistor.
IS
Input with Schmitt trigger
I/O8
I/O8PU
I/O8PD
Input/Output buffer with 8mA sink and 8mA source.
Input/Output buffer with 8mA sink and 8mA source, with an internal weak pull-up resistor.
Input/Output buffer with 8mA sink and 8mA source, with an internal weak pull-down
resistor.
I/O12
O8
Input/Output, 12mA
Output buffer with 8mA sink and 8mA source.
Output buffer with 8mA sink and 8mA source, with an internal weak pull-up resistor.
Output buffer with 8mA sink and 8mA source, with an internal weak pull-down resistor.
XTAL clock input
O8PU
O8PD
ICLKx
OCLKx
I/O-U
AIO
XTAL clock output
Analog Input/Output Defined in USB specification
Analog Input/Output
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Chapter 7 DC Parameters
7.1
Maximum Guaranteed Ratings
o
o
Operating Temperature Range*...........................................................................................0 C to +70 C
o
o
Storage Temperature Range.............................................................................................-55 to +150 C
o
Lead Temperature Range (soldering, 10 seconds)...................................................................... +325 C
Positive Voltage on GPIO3, with respect to Ground......................................................................... 5.5V
Positive Voltage on any signal pin, with respect to Ground ............................................................. 4.6V
Positive Voltage on XTAL1, with respect to Ground......................................................................... 4.0V
Negative Voltage on GPIO8, 10 & 11, with respect to Ground (see Note 7.2)...............................-0.5V
Negative Voltage on any pin, with respect to Ground .....................................................................-0.5V
Maximum V
V
.............................................................................................................. +2.5V
DD18, DD18PLL
Maximum V
V
................................................................................................................. +4.6V
DD33, DDA33
*Stresses above the specified parameters could cause permanent damage to the device. This is a
stress rating only and functional operation of the device at any other condition above those indicated
in the operation sections of this specification is not implied.
Note 7.1 When powering this device from laboratory or system power supplies, it is important that
the Absolute Maximum Ratings not be exceeded or device failure can result. Some power
supplies exhibit voltage spikes on their outputs when the AC power is switched on or off.
In addition, voltage transients on the AC power line may appear on the DC output. When
this possibility exists, it is suggested that a clamp circuit be used.
Note 7.2 When internal power FET operation of these pins is enabled, these pins may be
simultaneously shorted to ground or any voltage up to 3.63V indefinitely, without damage
to the device as long as V
and V
are less than 3.63V and T is less than 70°C.
DD33
DDA33
A
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7.2
Operating Conditions
PARAMETER
SYMBOL
MIN
MAX
70
UNITS
COMMENTS
Operating Temperature
1.8V supply voltage
T
0
°C
V
*Ambient temperature in still air.
A
V
V
1.62
3.0
0
1.98
3.6
DD18,
DD18PLL
3.3V supply voltage
3.3V supply rise time
Voltage on XTAL1
V
V
V
DD33,
DDA33
t
400
μs
V
RT
-0.3
V
DDA33
Voltage
VDD33
tRT
3.3V
100%
90%
10%
VSS
t90%
Time
t10%
Figure 7.1 Supply Rise Time Model
Note 7.3 When powering the device, the maximum power supply ramp time should be set at a rate
faster than 400 micro seconds. This speed is important to ensure that the device resets
properly. Measure rise time at 10% and 90%.
7.3
DC Electrical Characteristics
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
COMMENTS
I,IPU & IPD Type Input Buffer
Low Input Level
High Input Level
Pull Down
V
0.8
V
V
TTL Levels
ILI
V
2.0
IHI
PD
PU
72
58
μA
μA
Pull Up
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PARAMETER
IS Type Input Buffer
Low Input Level
SYMBOL
MIN
TYP
MAX
UNITS
COMMENTS
V
0.8
V
V
TTL Levels
ILI
High Input Level
V
2.0
IHI
Hysteresis
V
500
mV
HYSI
ICLK Input Buffer
Low Input Level
High Input Level
V
0.4
V
V
ILCK
V
2.2
IHCK
Input Leakage
(All I and IS buffers)
Low Input Leakage
High Input Leakage
I
-10
-10
+10
+10
μA
V
V
= 0
= V
IL
IN
I
mA
IH
IN
DD33
O8. O8PU & 08PD Type
Buffer
Low Output Level
V
0.4
V
V
I
V
= 8 mA @
OL
OL
= 3.3V
DD33
High Output Level
V
V
I
= -8mA @
OH
OH
DD33
- 0.4
V
= 3.3V
DD33
Output Leakage
Pull Down
Pull Up
I
-10
+10
μA
μA
μA
V
= 0 to V
IN DD33
OL
PD
72
58
PU
I/O8, I/O8PU & I/O8PD Type
Buffer
Low Output Level
V
0.4
V
V
I
V
= 8 mA @
OL
OL
OH
OL
= 3.3V
DD33
High Output Level
V
V
-0.4
I
V
= -8 mA @
OH
DD33
= 3.3V
DD33
Output Leakage
Pull Down
I
-10
+10
µA
µA
µA
V
= 0 to V
IN DD33
PD
PU
72
58
Pull Up
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4th Generation USB 2.0 Flash Media Controller with Integrated Card Power FETs & HS Hub
Datasheet
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
COMMENTS
I/O12 Type Buffer
Low Output Level
High Output Level
Output Leakage
V
0.4
V
V
OL
I
V
= 12mA @
OL
V
2.4
OH
OL
= 3.3V
DD33
I
+10
uA
I
= -4mA @
OH
V
= 3.3V
DD33
V
= 0 to V
IN
DD33
(Note 1)
IO-U
Integrated Power FET for
GPIO8 & GPIO10
Output Current
I
100
mA
mA
Ω
GPIO8, or 10;
OUT
Vdrop
= 0.23V
FET
Short Circuit Current Limit
On Resistance
I
140
2.1
GPIO8, or 10;
Vout = 0V
SC
FET
R
t
GPIO8, or 10;
= 70mA
DSON
I
FET
Output Voltage Rise Time
800
μs
GPIO8, or 10;
= 10μF
DSON
C
LOAD
Integrated Power FET for
GPIO11
Output Current
I
200
mA
mA
Ω
GPIO11;
Vdrop
OUT
= 0.46V
FET
Short Circuit Current Limit
On Resistance
I
181
2.1
GPIO11;
Vout
SC
= 0V
FET
R
t
GPIO11;
= 70mA
DSON
I
FET
Output Voltage Rise Time
800
μs
GPIO11;
= 10μF
DSON
C
LOAD
Supply Current Hub, Card
Reader, Unconfigured
I
I
90
83
mA
mA
CCINIT
CCINIT
High-Speed Host
Full-Speed Host
Revision 1.6 (06-20-08)
SMSC USB2601/USB2602
DATA2S4HEET
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4th Generation USB 2.0 Flash Media Controller with Integrated Card Power FETs & HS Hub
Datasheet
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
COMMENTS
Supply Current
Configured
Total from all
supplies
(High-Speed Host)
302
mA
3 Ext Ports @HS
Card Reader Active
Supply Current
Configured
Total from all
supplies
(High-Speed Host)
242
mA
1 Ext Port @HS
Card Reader Active
Supply Current
Configured
Total from all
supplies
(Full-Speed Host)
200
mA
1 Ext Port @ FS/LS
Card Reader Active
I
298
91
μA
Supply Current
Suspend
Total from all
supplies.
CSBY
I
μA
Supply Current
Reset
Total from all
supplies.
RST
Note 7.4 Output leakage is measured with the current pins in high impedance.
Note 7.5 See Appendix A for USB DC electrical characteristics.
Note 7.6 The Maximum power dissipation parameters of the package should not be exceeded
Note 7.7 The assignment of each Integrated Card Power FET to a designated Card Connector is
controlled by both firmware and the specific board implementation. Firmware will default to
SMSC USB2601/USB2602
Revision 1.6 (06-20-08)
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4th Generation USB 2.0 Flash Media Controller with Integrated Card Power FETs & HS Hub
Datasheet
7.4
Capacitance
T
= 25°C; fc = 1MHz; V
V
= 1.8V
A
DD18, DD18PLL
LIMITS
TYP
PARAMETER
SYMBOL
MIN
MAX
UNIT
TEST CONDITION
Clock Input Capacitance
C
20
pF
All pins except USB pins
(and pins under test tied to
AC ground)
IN
Input Capacitance
Output Capacitance
C
10
20
pF
pF
IN
C
OUT
Revision 1.6 (06-20-08)
SMSC USB2601/USB2602
DATA2S6HEET
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4th Generation USB 2.0 Flash Media Controller with Integrated Card Power FETs & HS Hub
Datasheet
Chapter 8 Package Information
8.1
Package Outline
Figure 8.1 USB2601/USB2602 128-Pin TQFP Package Outline
Table 8.1 USB2601/USB2602 128-Pin TQFP Package Parameters
MIN
NOMINAL
MAX
REMARKS
A
~
~
1.20
0.15
1.05
16.20
14.20
16.20
14.20
0.20
0.75
~
Overall Package Height
Standoff
A1
A2
D
0.05
0.95
15.80
13.80
15.80
13.80
0.09
0.45
~
~
~
Body Thickness
X Span
~
D1
E
~
X body Size
~
Y Span
E1
H
~
Y body Size
~
Lead Frame Thickness
Lead Foot Length
Lead Length
L
0.60
L1
e
1.00
0.40 Basic
Lead Pitch
o
o
q
0
~
0.18
~
7
Lead Foot Angle
Lead Width
W
R1
R2
ccc
0.13
0.08
0.08
~
0.23
~
Lead Shoulder Radius
Lead Foot Radius
Coplanarity
~
0.20
0.08
~
Notes:
1. Controlling Unit: millimeter.
2. Tolerance on the true position of the leads is ± 0.035 mm maximum.
Package body dimensions D1 and E1 do not include the mold protrusion.
3. Maximum mold protrusion is 0.25 mm.
4. Dimension for foot length L measured at the gauge plane 0.25 mm above the seating plane.
5. Details of pin 1 identifier are optional but must be located within the zone indicated.
SMSC USB2601/USB2602
Revision 1.6 (06-20-08)
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4th Generation USB 2.0 Flash Media Controller with Integrated Card Power FETs & HS Hub
Datasheet
8.2
Package Thermal Specifications
Table 8.2 128-Pin TQFP Package Thermal Parameters
PARAMETER
SYMBOL
VALUE
UNIT
COMMENTS
From the die to the ambient air
o
Thermal Resistance
ΘJA
ΘJT
53.1
0.3
C/W
C/W
o
Junction-to-Top-of-Package
Revision 1.6 (06-20-08)
SMSC USB2601/USB2602
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4th Generation USB 2.0 Flash Media Controller with Integrated Card Power FETs & HS Hub
Datasheet
Chapter 9 GPIO Usage
Table 9.1 GPIO Usage (ROM Rev -01)
ACTIVE
NAME
LEVEL
SYMBOL
DESCRIPTION AND NOTE
GPIO1
H
Flash Media Activity LED/
xD_Door
Indicates media activity. Media or USB
cable must not be removed with LED lit.
Also may be used for xD Door
functionality.
GPIO2
GPIO3
GPIO4
H
H
H
EE_CS
Serial EE PROM chip select.
USB V bus detect.
V_BUS
EE_DIN/EE_DOUT/xDID
Serial EE PROM input/output and xD
Identify.
GPIO5
GPIO6
GPIO7
GPIO8
H
H
H
L
HS_IND/SD_CD
A16/ROMEN
HS Indicator LED or SD Card Detect
Switch input.
A16 address line connect for DFU or
debug LED indicator optional.
EE_CLK/
UNCONF_LED
Serial EE PROM clock output or
Unconfigured LED.
MS_PWR_CTRL/
CRD_PWR0
Memory Stick Card Power Control, or
Internal Power FET0.
GPIO9
L
L
CF_PWR_CTRL
CompactFlash Card Power Control.
GPIO10
SM_PWR_CTRL/
CRD_PWR1
SmartMedia Card Power Control, or
Internal Power FET1.
GPIO11
GPIO12
L
SD/MMC_PWR_CTRL/
CRD_PWR2
SD/MMC Card Power Control, or
Internal Power FET2.
H
MS_ACT_IND/
Media Activity
Memory Stick Activity Indicator, or
Media Activity LED.
GPIO13
GPIO14
GPIO15
H
H
H
CF_ACT_IND
CompactFlash Activity Indicator.
SmartMedia Activity Indicator.
SD/MMC Activity Indicator.
SM_ACT_IND
SD/MMC_ACT_IND
SMSC USB2601/USB2602
Revision 1.6 (06-20-08)
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