Pico Computing
Pico E-15
Hardware Technical
Reference
Release: 1.01
For Hardware Revision: D
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3
Product Overview:
The Pico family of products are revolutionary FPGA based embedded acceleration platforms.
With performance that often exceeds modern microcomputers, a shockingly small form factor,
and nominal power consumption that is less than one watt, the Pico family of products take
computing to a whole new level.
The Pico E-15 is based on the high-performance Virtex-4 FPGA chip. This device has the
performance and power consumption of a custom chip (ASIC), but is completely
reconfigurable! The E-15 features four high speed converters and direct video capture.
Advanced users will enjoy the open source development kits which allow absolute control over
the hardware. For those who desire a more high level approach to firmware, Viva provides a
graphical development model. Impulse C™ support is also included for rapid firmware
development in the C programming language. Board support packages are available for
operating systems such as Linux, µC/OS, Green Hills Integrity OS™ and VX Works.
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Pico E-15 Quick Reference Datasheet
FEATURES
♦ High-performance Virtex-4 FX-20, 40 or 60
♦ 256MB RAM
MECHANICAL
Temperature Range: 0°C to +70°C
PC Card Type II Form-Factor
Stainless steel case
♦ 64MB Flash ROM
♦ Dual 12-Bit 125 MSPS A/D converters
♦ Dual 14-Bit 210 MSPS D/A converters
♦ Integrated composite video capture
♦ CardBus (PCI) Interface
♦ Open source
♦ Standalone operation
♦ Reconfigurable, high-speed digital bus
POWER
Sleep: 0.001W
Nominal: 1.2W
Absolute Maximum: 7.0W
Supply Voltage: 3.3V
FPGA FEATURES
♦ Embedded PowerPC™ P405 processor
♦ Integrated DSP logic
♦ Integrated RAM
APPLICATIONS
♦ Software defined radio
♦ Video processing / compression
♦ Accelerated scientific computing
♦ Digital signal processing
♦ Impulse C™ development platform
♦ Viva development platform
♦ Embedded systems
♦ Encryption / decryption
♦ Supercomputing / cluster computing
IO Connectivity
♦ 10/100/1000 Ethernet
♦ RS-232 Asynchronous Serial
♦ JTAG
♦ SVIDEO/Composite In
♦ Dual High Speed Analog to Digital
♦ Dual High Speed Digital to Analog
♦ GPIO
*Operation below -0°C requires throttled RAM timing
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Standard Part Numbers
Standard Part Number
FX-20
FX-40
FX-60
E15FX20-256/64/JEGSAADDV10C
E15FX40-256/64/JEGSAADDV10C
E15FX60-256/64/JEGSAADDV10C
A Military version is available which includes:
ꢀ BGA underfill
ꢀ Conformal coating
ꢀ Extended temperature range
The Military version is available by special order only, and is subject to minimum quantity
requirements.
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System Architecture
At the core of the Pico E-15 is a Virtex-4 FPGA. The FPGA can be dynamically configured to
perform any number of specialized tasks such as: protocol processing, encryption, or complex
mathematical functions. Embedded systems benefit from the integrated PowerPC™ processor.
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Pico E-15 Electrical Specification
Minimum
Nominal
3.3V
1.2W
Maximum
3.35V
7.0W
DC Input Voltage
Power Consumption
DC Input Current
3.25V
0.001W
0.0003A
0.36A
2.1A
Recommended Temperature Range
FPGA Over Temperature Shutdown
Maximum Storage Temperature Range
Relative Humidity (Non-Condensing)
0°C
10°C
70-80°C
27°C
70°C
-50°C
0%
90°C
95%
Overpower Considerations:
The Pico E-15 FX60 is designed desktop computers, and is not recommended for use in
laptops. Because of the large gate count of the FX60, it can easily exceed the PCCARD
maximum current consumption specification of 1A. The FX-60 features built in over-
temperature shutdown to protect both the card and the host system.
The Pico E-15 FX60 should be used with an external heat sink and an extender card.
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Field Programmable Gate Array
The core of the Pico E-15 is a high performance Virtex-4 FPGA. Included in the FPGA are the
FPGA Fabric, an optional PowerPC ™ processor, ultra high-speed DSP slices and RAM.
FPGA Fabric:
The “Fabric” of an FPGA comprises an array of logic elements that can be connected in
virtually unlimited patterns. These patterns of logic elements can be used to perform basic
mathematical functions such as addition and subtraction, or can be grouped together to
perform complex functions like Fast Fourier Transforms. Logic elements can even be
connected to create a custom soft processor.
The advantage of the FPGA is that the internal logic can be optimized for a specific
application. FPGAs are also able to execute operations in parallel, not being limited by
sequential execution like a traditional processor. FPGA operations can be executed in a
parallel, pipelined or even an asynchronous manner. The FPGA allows incredible application
speed with very low power consumption. Your imagination is really the limit.
DSP Slice:
Embedded within the FPGA are special areas that are designed to facilitate high speed “digital
signal processing.” These areas are called DSP slices. The DSP slice can be configured in a
variety of different ways. For example, one DSP slice can be configured to be one tap of an
FIR filter. DSP slices are fully pipelined and feature incredible speed. When configured for FIR
filtering the DSP slice has a guaranteed performance of 500MHz with a latency of one cycle.
An 18x18 multiply and accumulate also runs at 250MHz with a latency of two cycles. Smaller
data widths allow higher clock speeds.
FPGA Resources:
Free FPGA Cores
Encryption Cores
Virtex-4 Website
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PowerPC™ Processor
PPC405x3 Processor Introduction:
FPGAs are renowned for their ability to process parallel logic, but they typically have a hard
time emulating a high performance processor. To get the best of both worlds the Virtex-4™
features an embedded Power PC Processor. Since the processor shares the same die as the
FPGA it seamlessly interfaces with the FPGA fabric.
A new feature of the Virtex-4 FPGA is the addition of an auxiliary processor interface. The APU
is the highest speed interface between the PowerPC™ processor and the FPGA fabric. Up to
four custom instructions may be implemented in the FPGA, which are accessible from the
PowerPC™.
Board support packages are currently available for
code is available open source under the GPL.
µC/OS and Linux. Board support source
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CPLD TurboLoader
A CPLD (Complex Programmable Logic Device) is a smaller version of an FPGA (described
above) with permanent Flash storage built in. The Pico E-15 contains one CPLD that loads
and reconfigures the FPGA. The Pico firmware guide describes how to access the CPLD
TurboLoader.
The Flash ROM’s address bus can be controlled by either the TurboLoader or the FPGA (but
not both). During power-up or reboot, the TurboLoader is in control of the Flash ROM Address
bus. At all other times the FPGA is in control of the address bus.
CPLD Resources:
Xilinx CPLD Website
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Flash Memory
The Pico E-15 comes equipped with at least 64MB of Flash ROM. The Flash ROM is divided
into 512 sectors that can be erased independently. Most of the space on the ROM is reserved
for the user.
The Flash ROM’s address bus can be controlled by either the TurboLoader or the FPGA (but
not both). During power-up or reboot, the TurboLoader is in control of the Flash ROM Address
bus. At all other times the FPGA is in control of the address bus.
The Flash ROM has a simple, open file system which allows the user to store FPGA images,
ELF binary files, or other data. The primary image is used to boot the FPGA initially, and the
backup image is only invoked if the primary image fails to load correctly. Executable files are in
ELF format and are loaded by a loader within the secondary image. The primary image will
either load the secondary image or pause for the PC to access and manage the file system.
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DDR2 SDRAM Memory
The Pico E-15 comes equipped with 256MB of DDR2 SDRAM memory. There are two 1024Mb
chips, each with a separate 16 bit data path to the host to form one 32 bit bank. From 0°C to
+85°C, the ram can run at up to 333 MHz. For operation at temperatures below 0°C, special
firmware with throttled ram timings is required. Please note that the RAM will not function
below 125 MHz.
RAM
MSBs
Virtex-4 FPGA
RAM
LSBs
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RAM Timing and Parameter Information
Parameter
Value
EDK Value
EDK Value
133 MHz
333 MHz
Registered
Clock Pairs
Memory Banks
IDELAY Controllers
Differential DQs
Open Row Management
On Die Termination
ECC Support
TMRD
TWR
TWTR
TRAS
TRC
TRFC
TRCD
TRRD
TRP
TREFI
TFAW
No
1
1
2
Yes
No
Disabled
No
2 Clocks
15 nS
7.5 nS
45 nS
60 nS
127.5 nS
15 nS
10 nS
15 nS
7.8 uS
37.5
5 Clocks
32 Bits
13 Bits
10 Bits
3
0
0
1
1
2
1
0
0
0
1
1
2
1
0
0
0
6000
1500
3
45000
60000
12750
15000
10000
15000
7800000
37500
5
32
13
10
3
15000
15000
1
45000
60000
12750
15000
10000
15000
7800000
37500
5
32
13
10
3
CAS Latency
Data Width
Address Width
Column Width
Bank Address Width
Clock Period*
*Minimum RAM Speed is 125MHz
5 nS
7500
3000
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14
Temperature Sensor
The Pico E-15 contains one temperature sensor that directly senses the die temperature of the
Virex-4 FPGA. The digital interface of the remote temperature sensing chip is connected to the
Cypress PSoC. If an overtemperature condition occurs, the PSoC will shutdown the FPGA
until the temperature has dropped sufficiently below the shutdown threshold.
The setpoints of the temperature shutdown circuit can be reprogrammed via the PSoC debug
cable.
Electrical Specifications
Temperature Sensing Range
Resolution
Minimum
Nominal
Maximum
-55°C
125°C
0.0625°C
+/- 1.0°C
Accuracy
+/- 2.4°C
+/- 0.0°C
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Sleep Controller
The Pico E-15 contains one Cypress PSoC which is used to generate a clock for the
bootloader and control the power state.
The E-15 can be placed in a state where it draws almost no power, then wakes up
automatically after a set amount of time.
The sleep controller can be activated by the FPGA, or the external peripheral interface
connector.
The protocol for entering sleep state is simple. Simply pulse FPGA_POWERCTL_C for as
many seconds as your wish to sleep, then lower the FPGA_POWERCTL_D signal.
The Pico E-15 will awake from sleep if any of the following conditions are true:
-Power is first applied
-The sleep timer has run out
-POWERCTL_D is low and POWERCTL_C is high
The Pico E-15 will enter sleep mode if any of the following conditions are true:
-An overtemperature condition is detected
-The FPGA_POWERCTL_D pin is low
-The POWERCTL_C pin is low
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16
Tri-Mode Ethernet Interface
The Pico E-15 features the Marvell Alaska series 88E1111 tri-mode Ethernet transceiver.
Combined with the on-FPGA MAC (Middle access controller) a complete Ethernet solution is
offered. Communication between the MAC and PHY takes place over an industry standard
MII/GMII interface.
The Ethernet transceiver features 10/100/1000 full/half duplex operation. It will automatically
configure the physical interface on the fly for crossover or straight through operation. The PHY
can even automatically correct for common wiring mistakes. The PHY has a built in Time
Domain Reflectometer which can diagnose cable problems and pinpoint their distance away
from the transceiver.
The Ethernet interface on the Pico is magnetic-less allowing high speed, low power digital
interconnect directly to Ethernet backplanes. DO NOT directly connect the Ethernet interface
to a hub or switch without a magnetic isolation module.
The Marvell 88E1111 is the only user-accessible chip on the Pico E-15 that requires an NDA
for access to the datasheets. If you are interested in some of the advanced features not
supported by the native driver, contact Pico Computing for assistance in obtaining an NDA
from Marvell. Users are advised not to contact Marvell directly.
Ethernet Resources:
Marvell 88E1111 Webpage
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Digital Peripheral Interface
The Pico E-15 features 2 GPIO lines which are used for external peripheral support. The GPIO
lines are always enabled.
All GPIO signals have user selectable pull-up, pull-down, keeper or HI-Z termination. Drive
strength is also user selectable between 2 and 24mA. All GPIOs can be configured for input,
output and bi-directional mode.
GPIO 1 has a 50 ohm resistor in series with the output to allow connectivity with low voltage
devices which may clamp a 3.3V signal.
Electrical Specifications
High Voltage
Minimum
2.0V
Nominal
3.3V
Maximum
3.45V
Low Voltage
-0.2V
0V
0.8
Input Impedance (Pulldowns Disabled)
Drive Strength (Selectable)
HI-Z
2 mA
24 mA
2 KV
ESD Withstand Voltage (Human Body Model)
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High Speed Analog to Digital Converters
The Pico E-15 features 2 high speed analog to digital converters. The converters are optimized
for high-frequency, high-performance, low-power, low-noise operation. The converters have
integrated DC blocking capacitors, and thus, cannot be used on very low frequency signals.
The ADC should be driven by a source with an impedance of 50 ohms.
To ensure accuracy at high speeds, the low-jitter 125 MHz reference clock must be used. The
converters may be tuned to different applications. For example: a lower termination impedance
may be traded for more sensitivity. A wider high frequency input range may be traded for less
high frequency noise rejection. Contact Pico Computing with your application requirements.
The data returning from the ADCs must be sampled on the rising edge of the appropriate clock
return pin. Even when the ADCs are clocked from the same source, they will be running out of
sync because of the duty cycle stabilizer (which provides greater resolution). The Pico E-15
can be special ordered with the duty cycle stabilizer perminately disabled.
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Electrical Specifications
Differential AC Input Voltage
Termination Resistance
Input Frequency Range
Bandwidth
Minimum
0 Vpp
45 (VHF)
1 KHz*
Nominal
1 Vpp
50 (AC)
1-50 MHz
125 MHz
Maximum
1.8 Vpp
115(DC)
125 MHz
225 MHz
Dielectric Surge Withstand Voltage
Withstand Voltage
-14 VDC
-4 VDC
0 VDC
0 VDC
14 VDC
4 VDC
Clock Frequency
Resolution
125 MHz
0.013V
125 MHz
12 Bits
0.007V
Sensativity
0.087V
*Lower frequencies are possible with degraded performance.
ADC Front-End Equivalent Circuit
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ADC Low Frequency Input Impedance
ADC High Frequency Input Impedance*
*Low pass filter range is customizable via special order
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21
High Speed Digital to Analog Converters
The Pico E-15 features 2 high speed analog to digital converters. The converters are optimized
for high-frequency, high-performance, low-power, low-noise operation. The converters have
integrated DC blocking capacitors, and can not be used on low frequency signals. The DAC
should be terminated into a 50 ohm load.
To ensure accuracy at high speeds, the low-jitter 125 MHz reference clock must be used. The
DAC supports a clock frequency of up to 210 MHz.
Electrical Specifications
Minimum
Nominal
0.225 Vpp
1.8 Vpp
50
Maximum
0.45 Vpp
1.8 Vpp
Differential AC Output Voltage (50 Ohm Load) 0 Vpp
Differential AC Output Voltage (Hi-Z)
Internal Termination Impedance
Output Frequency Range (50 Ohm Load)
Bandwidth
0 Vpp
5 KHz
105 MHz
Noise Floor
Dielectric Withstand Voltage (Output to GND) -15V
0V
15V
Clock Frequency
Resolution
125 MHz
14 Bits
210 MHz
DAC Front-End Equivalent Circuit
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DAC Low Frequency Maximum Amplitude (50 Ohm Load)
DAC High Frequency Maximum Amplitude (50 Ohm Load)
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23
Video Digitizer
The Pico E-15 contains one ultra low-power video digitizer. The video digitizer accepts both
SVIDEO and Composite video inputs and can decode NTSC, PAL and SECAM video
standards. When using composite video, the video digitzer can switch from between two
channels. The TVP5150 has an integrated I2C control interface.
Video Digitizer External Connections (SVIDEO Mode):
VIDEO_IN_Y
VIDEO_IN_C
VIDEO_IN_GND
Video Luminence
Video Chrominence
Analog Video Ground
Video Digitizer External Connections (COMPOSITE Mode):
VIDEO_IN_Y
VIDEO_IN_C
VIDEO_IN_GND
Composite Video Channel #1*
Composite Video Channel #2*
Analog Video Ground
*Unused channels must be connected to Analog Video Ground
Electrical Specifications
Resolution
Minimum
Nominal
9 Bits
Maximum
Impedance
75 Ohms
Maximum AC Amplitude
Maximum DC Offset
1.5 Vp
75V
-75V
0
Video Digitizer Resources:
TVP5150AM1 Homepage
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24
CardBus / Digital Bus Interface
The Pico E-15 can run as a standalone product or be connected to a host using the CardBus
connector. By default, the Pico E-15 ships with firmware that is ready for use as a CardBus
device.
The CardBus interface is a subset of PCI. The data path is 32 bits wide and is synchronous.
The wiring of the CardBus interface supports both completion and mastering of the bus.
When the Pico E-15 is not connected to a CardBus host, the digital bus can be reconfigured to
connect with a wide variety of high speed digital busses and peripherals. With proper external
termination, speeds of over 100 MHz are possible. The external digital bus can only interface
with 3.3V logic.
Those who are interested in alternate interfaces should contact Pico Computing. The CardBus
interface source code and support is available.
Electrical Specifications (DC)
Positive Supply Input Voltage (Vcc)
Low Level Input Voltage
Minimum
3.25V
-0.2V
Nominal
3.3V
0V
Maximum
3.35V
0.7V
High Level Input Voltage
2.0V
3.3V
3.35V
Recommended Drive Strength
Input Impedance
Internal Bus Voltage
8mA
HI-Z
3.3V
PCMCIA Interface Resources:
PCMCIA Website
PCI SIG Website
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25
JTAG Debug Interface
The Pico E-15 is equipped with a JTAG diagnostic port which allows real-time debugging of
hardware, firmware and software.
Some JTAG programs require the length of the instruction register (IR). The IR length is listed
below for all devices in the JTAG chain. The FPGA IR length changes depending on how
many PowerPCs are internally connected to the JTAG chain in the FPGA.
Device
FPGA
Instruction register bit length
6,10 or 14 (Depends on PPC Configuration)
TurboLoader
Ethernet PHY
8
8
FPGA
TDI
TDO
Turbo Loader
Ethernet
IR= 8
PowerPC
IR= 10
IR= 8
The Primary Image in the Flash ROM contains an embedded JTAG diagnostic port. This
allows a user in Windows or Linux to debug software without an external JTAG cable. The
internal JTAG diagnostic loopback looks just like a Parallel Port JTAG diagnostic cable when
used with the Pico E-15 driver.
The external JTAG interface uses 1.8V logic.
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26
PSoC Debug Interface
The Pico E-15 has a low power PSoC microcontroller (also known as the sleep controller)
which controls the power to the rest of the board. The PSoC also generates a 24 MHz clock for
the TurboLoader. The PSoC features an in-circuit programming interface, although it is
unlinkey that a user will ever need to debug or modify the PSoC firmware.
To program the PSoC the following parts are required:
Description
ISSP Programming Cable
PSoC ICE CUBE
Manufacturer
Pico Computing
Cypress
Part Number
E15-PSoC
CY3215-DK
Distributor
Pico Computing
Digikey
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27
Appendix A – Peripheral I/O Connector Information
Connector Information
Description
Brand
Part Number
Mating Connector
Hirose
NX-32TA-CV1(50)
*Connectors are always in stock at Pico Computing
Peripheral I/O Connector Pinout
1
2
3
4
5
6
7
8
9
VIDEO_GND
VIDEO_IN_C
VIDEO_IN_Y
TMS
Analog Video Ground
0V DC – Ground [VIDEO]
NTSC / CAM / PAL Video
NTSC / CAM / PAL Video
LVCMOS-1.8
LVCMOS-1.8
LVCMOS-1.8
Analog Video Input (Chrominance)
Analog Video Input (Luminance)
JTAG Mode Select
JTAG Clock
JTAG Data In
JTAG Data Out
Differential Analog In #1 +
Differential Analog In #1 -
Ethernet DA-
TCK
TDI
TDO
ANALOG_IN_1+
ANALOG_IN_1-
LVCMOS-1.8
1.8V Pk-Pk 50 Ohm Analog
1.8V Pk-Pk 50 Ohm Analog
IEEE 802.3
IEEE 802.3
IEEE 802.3
10 ETHER_OUT_DA-
11 ETHER_OUT_DA+
12 ETHER_OUT_DD-
Ethernet DA+
Ethernet DD-
13 ETHER_OUT_DD+ Ethernet DD+
14 ETHER_OUT_DC- Ethernet DC-
15 ETHER_OUT_DC+ Ethernet DC+
IEEE 802.3
IEEE 802.3
IEEE 802.3
16 ETHER_OUT_DB-
17 ETHER_OUT_DB+
18 POWERCTL_R
19 ANALOG_IN_2-
20 ANALOG_IN_2+
21 2.5V
Ethernet DB-
Ethernet DB+
PSoC Debug Interface Reset
Differential Analog In #2 -
Differential Analog In #2 +
2.5V 250mA Max
IEEE 802.3
IEEE 802.3
LVTTL-3.3
1.8V Pk-Pk 50 Ohm Analog
1.8V Pk-Pk 50 Ohm Analog
2.5V DC
22 DIAG_EN_n
23 1.8V
Diagnostic Enable
1.8V 250mA Max
LVCMOS-1.8
1.8V DC
24 POWERCTL_C
25 POWERCTL_D
26 GPIO_1
27 GPIO_2
28 GND
29 ANALOG_OUT_2+
30 ANALOG_OUT_2-
31 ANALOG_OUT_1+
32 ANALOG_OUT_1-
PSoC Debug Clock
LVTTL-3.3
LVTTL-3.3
LVTTL-3.3
LVTTL-3.3
0V DC – Ground [DIGITAL]
1.8V Pk-Pk 50 Ohm Analog
1.8V Pk-Pk 50 Ohm Analog
1.8V Pk-Pk 50 Ohm Analog
1.8V Pk-Pk 50 Ohm Analog
PSoC Debug Data / WAKEUP
General Purpose IO #1
General Putpose IO #2
Digital Ground
Differential Analog Out #2 +
Differential Analog Out #2 -
Differential Analog Out #1 +
Differential Analog Out #1 -
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Peripheral Connector Drawing
Figure 5
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29
Appendix B – CardBus Connector Information
Connector Information
Description
Brand
Part Number
CardBus Socket
FCI
71299-050CALF
The CardBus Socket is typically in stock at Mouser Electronics. (http://www.mouser.com)
The function and direction of the pins on the CardBus interface can be easily changed to suit
the needs of a custom interface. Series termination on the E-15 is zero ohms, but a larger
value can be used if it is required for your application.
Pico E-15 Hardware Reference
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30
CardBus Interface Schematic
Pico E-15 Hardware Reference
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31
CardBus Connector Pinout
1
GND
Digital Ground
2
PCI_CAD0
Data / Address 0
Data / Address 1
Data / Address 3
Data / Address 5
Data / Address 7
Byte Enable 0
3
PCI_CAD1
4
PCI_CAD3
5
PCI_CAD5
6
PCI_CAD7
7
P\C\I\_\C\C\B\E\0\
PCI_CAD9
8
Data / Address 9
Data / Address 11
Data / Address 12
Data / Address 14
Byte Enable 1
9
PCI_CAD11
PCI_CAD12
PCI_CAD14
P\C\I\_\C\C\B\E\1\
PCI_CPAR
P\C\I\_\C\P\E\R\R\
P\C\I\_\C\G\N\T\
P\C\I\_\C\I\N\T\
3.3V
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
Parity Even
Parity Error
Access Grant
Interrupt Request
3.3V Digital Supply
No Connection
33 MHz
VPP
PCI_CCLK
P\C\I\_\C\I\R\D\Y\
P\C\I\_\C\C\B\E\2\
PCI_CAD18
PCI_CAD20
PCI_CAD21
PCI_CAD22
PCI_CAD23
PCI_CAD24
PCI_CAD25
PCI_CAD26
PCI_CAD27
PCI_CAD29
PCI_RFU2
Initiator Ready
Byte Enable 2
Data / Address 18
Data / Address 20
Data / Address 21
Data / Address 22
Data / Address 23
Data / Address 24
Data / Address 25
Data / Address 26
Data / Address 27
Data / Address 29
Reserved
PCI_CLKRUN
GND
Clock Request
Digital Ground
GND
Digital Ground
PCI_DETECT
PCI_CAD2
CardBus Detect Shorted to 46
Data / Address 2
Data / Address 4
Data / Address 6
Reserved
PCI_CAD4
PCI_CAD6
PCI_RFU0
PCI_CAD8
Data / Address 8
Data / Address 10
CardBus Detect Shorted to 36
Data / Address 13
Data / Address 15
Data / Address 16
Reserved
PCI_CAD10
PCI_DETECT
PCI_CAD13
PCI_CAD15
PCI_CAD16
PCI_RFU1
P\C\I\_\C\B\L\O\C\K\
Bus Lock
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32
49
50
51
52
53
54
55
56
58
59
60
61
62
63
64
65
66
67
68
P\C\I\_\C\S\T\O\P\
P\C\I\_C\D\E\V\S\E\L\
3.3V
Transfer Halt
Device Select
3.3V Digital Supply
No Connection
Target Ready
Frame
VPP
P\C\I\_\C\T\R\D\Y\
P\C\I\_\C\F\R\A\M\E\
PCI_CAD17
Data / Address 17
Data / Address 19
Reset
PCI_CAD19
P\C\I\_\C\R\S\T\
P\C\I\_\C\S\E\R\R\
P\C\I\_\C\R\E\Q\
P\C\I\_\C\C\B\E\3\
PCI_CAUDIO
PCI_CSTSCHG
PCI_CAD28
System Error
Access Request
Byte Enable 3
Audio
Status Change Interrupt
Data / Address 28
Data / Address 30
Data / Address 31
Digital Ground
Digital Ground
PCI_CAD30
PCI_CAD31
GND
GND
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33
Appendix C – FPGA Pinout
FPGA Pinout
Net
Pin
K8
Description
Differential Clock In+
Differential Clock In-
Clock Return
Data In #0
Dir
I/O Standard
DIFF HSTL II
DIFF HSTL II
LVTTL
Term
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Drive
ADC_1_CLK_IN+
ADC_1_CLK_IN-
ADC_1_CLK_RTURN
ADC_1_D0
O
K7
O
D6
I
G7
E5
I
LVTTL
ADC_1_D1
Data In #1
I
LVTTL
ADC_1_D2
E7
Data In #2
I
LVTTL
ADC_1_D3
F7
Data In #3
I
LVTTL
ADC_1_D4
F8
Data In #4
I
LVTTL
ADC_1_D5
C9
Data In #5
I
LVTTL
ADC_1_D6
D9
Data In #6
I
LVTTL
ADC_1_D7
C12
G9
A14
G10
H7
Data In #7
I
LVTTL
ADC_1_D8
Data In #8
I
LVTTL
ADC_1_D9
Data In #9
I
LVTTL
ADC_1_D10
ADC_1_D11
ADC_1_OVERLOAD
ADC_1_POWER
ADC_2_CLK_IN+
ADC_2_CLK_IN-
ADC_2_CLK_RTURN
ADC_2_D0
Data In #10
Data In #11
Over-Voltage Detect
Power Control
Differential Clock In+
Differential Clock In-
Clock Return
Data In #0
I
LVTTL
I
LVTTL
H8
I
LVTTL
L9
I
LVTTL
J9
O
DIFF HSTL II
DIFF HSTL II
LVTTL
K10
H4
O
I
B14
F10
K6
I
LVTTL
ADC_2_D1
Data In #1
I
LVTTL
ADC_2_D2
Data In #2
I
LVTTL
ADC_2_D3
L7
Data In #3
I
LVTTL
ADC_2_D4
D15
E15
F15
F14
H9
Data In #4
I
LVTTL
ADC_2_D5
Data In #5
I
LVTTL
ADC_2_D6
Data In #6
I
LVTTL
ADC_2_D7
Data In #7
I
LVTTL
ADC_2_D8
Data In #8
I
LVTTL
ADC_2_D9
L10
C6
Data In #9
I
LVTTL
ADC_2_D10
ADC_2_D11
ADC_2_OVERLOAD
ADC_2_POWER
C\B\L\O\C\K\
C\C\B\E\0\
Data In #10
Data In #11
Over-Voltage Detect
Power Control
Bus Lock
I
LVTTL
G11
D14
L5
I
LVTTL
I
LVTTL
I
LVTTL
H6
I/O
I/O
I/O
I/O
I/O
I
PCI33_3
PCI33_3
PCI33_3
PCI33_3
PCI33_3
PCI33_3
PCI33_3
PCI33_3
2mA
2mA
2mA
2mA
2mA
AF13
J5
Byte Enable 0
Byte Enable 1
Byte Enable 2
Byte Enable 3
Device Select
Frame
C\C\B\E\1\
C\C\B\E\2\
D5
C\C\B\E\3\
C11
E3
C\D\E\V\S\E\L\
C\F\R\A\M\E\
C\G\N\T\
C3
I/O
I
2mA
G5
Access Grant
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C\I\N\T\
C\I\R\D\Y\
C\P\E\R\R\
C\R\E\Q\
C\R\S\T\
C\S\E\R\R\
C\S\T\O\P\
C\T\R\D\Y\
CAD0
F4
Interrupt Request
Initiator Ready
Parity Error
O
PCI33_3
PCI33_3
PCI33_3
PCI33_3
PCI33_3
PCI33_3
PCI33_3
PCI33_3
PCI33_3
PCI33_3
PCI33_3
PCI33_3
PCI33_3
PCI33_3
PCI33_3
PCI33_3
PCI33_3
PCI33_3
PCI33_3
PCI33_3
PCI33_3
PCI33_3
PCI33_3
PCI33_3
PCI33_3
PCI33_3
PCI33_3
PCI33_3
PCI33_3
PCI33_3
PCI33_3
PCI33_3
PCI33_3
PCI33_3
PCI33_3
PCI33_3
PCI33_3
PCI33_3
PCI33_3
PCI33_3
PCI33_3
PCI33_3
PCI33_3
PCI33_3
PCI33_3
DIFF HSTL II
DIFF HSTL II
LVTTL
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
2mA
2mA
2mA
2mA
D4
H3
A10
A8
A9
F3
I/O
I/O
O
Access Request
Reset
I
System Error
Stop Request
Target Ready
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
2mA
2mA
2mA
2mA
2mA
2mA
2mA
2mA
2mA
2mA
2mA
2mA
2mA
2mA
2mA
2mA
2mA
2mA
2mA
2mA
2mA
2mA
2mA
2mA
2mA
2mA
2mA
2mA
2mA
2mA
2mA
2mA
2mA
2mA
2mA
2mA
D3
AD15 Data / Address #0
AE15 Data / Address #1
CAD1
CAD2
AF15
AF14
Data / Address #2
Data / Address #3
CAD3
CAD4
AD14 Data / Address #4
AC14 Data / Address #5
AA13 Data / Address #6
AB12 Data / Address #7
AC13 Data / Address #8
AD13 Data / Address #9
AC12 Data / Address #10
AA12 Data / Address #11
AB14 Data / Address #12
AA14 Data / Address #13
CAD5
CAD6
CAD7
CAD8
CAD9
CAD10
CAD11
CAD12
CAD13
CAD14
M6
M5
K3
Data / Address #14
Data / Address #15
Data / Address #16
Data / Address #17
Data / Address #18
Data / Address #19
Data / Address #20
Data / Address #21
Data / Address #22
Data / Address #23
Data / Address #24
Data / Address #25
Data / Address #26
Data / Address #27
Data / Address #28
Data / Address #29
Data / Address #30
Data / Address #31
Audio
CAD15
CAD16
CAD17
C4
CAD18
C7
CAD19
B6
CAD20
A7
CAD21
B7
CAD22
B9
CAD23
B10
B11
A12
B12
A13
C8
CAD24
CAD25
CAD26
CAD27
CAD28
CAD29
C13
E10
D10
E8
CAD30
CAD31
CAUDIO
CCLK
E11
E13
J4
CardBus 33 MHz Clock
Clock Request
I
CCLKRUN
CPAR
O
2mA
2mA
2mA
Parity Even
I/O
O
CSTSCHG
DAC_1_CLK_IN+
DAC_1_CLK_IN-
DAC_1_D0
DAC_1_D1
DAC_1_D2
D8
Status Change Interrupt
Differential Clock In +
Differential Clock In -
Data Out #0
AC4
AC3
W5
W4
Y3
O
O
O
4mA
4mA
4mA
Data Out #1
O
LVTTL
Data Out #2
O
LVTTL
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DAC_1_D3
AA4
AA3
AD4
AB4
AD3
AB7
AD8
AB6
AD6
AB5
AD5
AC8
AC7
AC6
AD9
Data Out #3
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
LVTTL
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Pullup
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
4mA
4mA
4mA
4mA
4mA
4mA
4mA
4mA
4mA
4mA
4mA
4mA
DAC_1_D4
Data Out #4
LVTTL
DAC_1_D5
Data Out #5
LVTTL
DAC_1_D6
Data Out #6
LVTTL
DAC_1_D7
Data Out #7
LVTTL
DAC_1_D8
Data Out #8
LVTTL
DAC_1_D9
Data Out #9
LVTTL
DAC_1_D10
DAC_1_D11
DAC_1_D12
DAC_1_D13
DAC_1_POWER
DAC_2_CLK_IN+
DAC_2_CLK_IN-
DAC_2_D0
Data Out #10
Data Out #11
Data Out #12
Data Out #13
Power Control (Inverted)
Differential Clock In +
Differential Clock In -
Data Out #0
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
DIFF HSTL II
DIFF HSTL II
LVTTL
4mA
4mA
4mA
4mA
4mA
4mA
4mA
4mA
4mA
4mA
4mA
4mA
4mA
4mA
4mA
DAC_2_D1
AD10 Data Out #1
AC9 Data Out #2
LVTTL
DAC_2_D2
LVTTL
DAC_2_D3
AD11 Data Out #3
AC11 Data Out #4
AB10 Data Out #5
AA10 Data Out #6
LVTTL
DAC_2_D4
LVTTL
DAC_2_D5
LVTTL
DAC_2_D6
LVTTL
DAC_2_D7
AA9
Y8
Data Out #7
Data Out #8
Data Out #9
LVTTL
DAC_2_D8
LVTTL
DAC_2_D9
AA8
LVTTL
DAC_2_D10
DAC_2_D11
DAC_2_D12
DAC_2_D13
DAC_2_POWER
ETHER_CLK_TERM
ETHER_CLK_TERM
ETHER_COL
ETHER_CRS
ETHER_GTX_TERM
ETHER_IRQ
ETHER_MDC
ETHER_MDIO
ETHER_RESET
ETHER_RX0
ETHER_RX1
ETHER_RX2
ETHER_RX3
ETHER_RX4
ETHER_RX5
ETHER_RX6
ETHER_RX7
ETHER_RX_CLK
ETHER_RX_DV
ETHER_RX_ER
ETHER_TX0
AB11 Data Out #10
LVTTL
W9
Data Out #11
Data Out #12
Data Out #13
Power Control (Inverted)
125 MHz Clock
125 MHz Clock
Colision Detect
Carrier Sense
Gigabit TX Clock
Interrupt Request
Management Clock
Management Data
Reset
LVTTL
AB9
AA7
Y5
LVTTL
LVTTL
LVTTL
H14
K13
F19
G17
A17
E22
F22
G22
F23
D18
B16
A15
B15
F24
D16
C16
F18
K22
C17
C18
B17
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
I
I
I
O
OD
O
I/O
O
I
4mA
4mA
4mA
4mA
RX Data #0
RX Data #1
I
RX Data #2
I
RX Data #3
I
RX Data #4
I
RX Data #5
I
RX Data #6
I
RX Data #7
I
RX Clock
I
RX Data Valid
RX Error
I
I
TX Data #0
O
4mA
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ETHER_TX1
ETHER_TX2
ETHER_TX3
ETHER_TX4
ETHER_TX5
ETHER_TX6
ETHER_TX7
ETHER_TX_CLK
ETHER_TX_CTL
ETHER_TX_ER
F\L\A\S\H\_\B\Y\T\E\
F\L\A\S\H\_\C\E\
F\L\A\S\H\_\O\E\
F\L\A\S\H\_\W\E\
FLASH_A0
F20
E21
C23
C21
D21
D23
E23
D19
C19
E17
TX Data #1
TX Data #2
TX Data #3
TX Data #4
TX Data #5
TX Data #6
TX Data #7
TX Clock
O
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
4mA
4mA
4mA
4mA
4mA
4mA
4mA
4mA
4mA
4mA
4mA
4mA
4mA
4mA
4mA
4mA
O
O
O
O
O
O
O
TX Control (Enable)
TX Error
O
O
AC17 16 / 8 Bit Mode Select
O
J16
Chip Enable
O
H13
Output Enable
O
AD19 Write Enable
O
U17
U15
V11
Address # 0
Address # 1
Address # 2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
FLASH_A1
FLASH_A2
4mA
4mA
FLASH_A3
AC18 Address # 3
4mA
4mA
4mA
4mA
4mA
4mA
4mA
FLASH_A4
Y11
V16
W11
Address # 4
Address # 5
Address # 6
FLASH_A5
FLASH_A6
FLASH_A7
AD18 Address # 7
AB19 Address # 8
AD20 Address # 9
AB20 Address # 10
FLASH_A8
FLASH_A9
FLASH_A10
FLASH_A11
FLASH_A12
FLASH_A13
FLASH_A14
FLASH_A15
FLASH_A16
FLASH_A17
FLASH_A18
FLASH_A19
FLASH_A20
FLASH_A21
FLASH_A22
FLASH_A23
FLASH_A24
FLASH_D0
Y15
Address # 11
4mA
4mA
4mA
4mA
4mA
4mA
4mA
4mA
4mA
4mA
4mA
4mA
4mA
4mA
4mA
4mA
4mA
4mA
4mA
4mA
4mA
4mA
4mA
4mA
4mA
AC22 Address # 12
AB21 Address # 13
AA15 Address # 14
AA17 Address # 15
AD16 Address # 16
Y12
Address # 17
AA20 Address # 18
Y16
U16
W16
Address # 19
Address # 20
Address # 21
AD23 Address # 22
AB15 Address # 23
AB16 Address # 24
V12
V13
V14
U14
W13
Y13
W14
W15
T17
J14
Data #0
Data #1
Data #2
Data #3
Data #4
Data #5
Data #6
Data #7
Data #8
Data #9
Data #10
FLASH_D1
FLASH_D2
FLASH_D3
FLASH_D4
FLASH_D5
FLASH_D6
FLASH_D7
FLASH_D8
FLASH_D9
FLASH_D10
K12
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FLASH_D11
FLASH_D12
FLASH_D13
FLASH_D14
FLASH_D15
FLASH_READY
GPIO_1
H12
K11
J11
H11
Data #11
Data #12
Data #13
Data #14
I/O
I/O
I/O
I/O
I/O
I
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVTTL
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
4mA
4mA
4mA
4mA
4mA
4mA
AA19 Data #15 / Address -1
AC19 Ready
T4
General Purpose I/O #1
I/O
I/O
O
12mA
12mA
4mA
GPIO_2
T3
General Purpose I/O #2
LVTTL
JTAG_LOOP_TCK
JTAG_LOOP_TDI
JTAG_LOOP_TDO
JTAG_LOOP_TMS
LOAD
H16
J15
G16
G15
Internal JTAG Loopback Clock
Internal JTAG Loopback Data In
Internal JTAG Loopback Data Out
Internal JTAG Loopback Mode Select
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVTTL
O
4mA
I
O
4mA
AB17 TurboLoader Reload Request
O
Pulldown 2mA
Float
LOOP_1
U4
V4
V3
W3
Timing Loopback #1
Timing Loopback #1
Timing Loopback #2
Timing Loopback #2
I
LOOP_1
O
LVTTL
Float
Float
Float
4mA
LOOP_2
I
LVTTL
LOOP_2
O
LVTTL
4mA
PEEKABOO
POWERCTL_FPGA_C
POWERCTL_FPGA_D
RAM_A0
AA18 TurboLoader Peekaboo Request
O
LVCMOS18
LVTTL
Pulldown 2mA
G12
F13
V23
N22
L18
K23
T24
K21
L19
J19
K18
P24
K20
R23
T23
T22
T20
J23
V24
U20
R20
R21
U21
PSoC Serial Interface Clock
PSoC Serial Interface Data
Address #0
O
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
4mA
I/O
O
LVTTL
4mA
SSTL18 II
SSTL18 II
SSTL18 II
SSTL18 II
SSTL18 II
SSTL18 II
SSTL18 II
SSTL18 II
SSTL18 II
SSTL18 II
SSTL18 II
SSTL18 II
SSTL18 II
SSTL18 II
SSTL18 II
SSTL18 II
SSTL18 II
SSTL18 II
DIFF SSTL18 II
DIFF SSTL18 II
SSTL18 II
SSTL18 II
SSTL18 II
SSTL18 II
SSTL18 II
SSTL18 II
SSTL18 II
SSTL18 II
SSTL18 II
SSTL18 II
12mA
12mA
12mA
12mA
12mA
12mA
12mA
12mA
12mA
12mA
12mA
12mA
12mA
12mA
12mA
12mA
12mA
12mA
RAM_A1
Address #1
O
RAM_A2
Address #2
O
RAM_A3
Address #3
O
RAM_A4
Address #4
O
RAM_A5
Address #5
O
RAM_A6
Address #6
O
RAM_A7
Address #7
O
RAM_A8
Address #8
O
RAM_A9
Address #9
O
RAM_A10
Address #10
O
RAM_A11
Address #11
O
RAM_A12
Address #12
O
RAM_BA0
Bank Address #0
Bank Address #1
Bank Address #2
Column Address Select
Chip Select
O
RAM_BA1
O
RAM_BA2
O
RAM_C\A\S\
RAM_C\S\
O
O
RAM_CK_N
RAM_CK_P
RAM_CKE
RAM_DM0_7
RAM_DM8_15
RAM_DM16-23
RAM_DM24-31
RAM_DQ0
RAM_DQ1
RAM_DQ2
RAM_DQ3
RAM_DQ4
Clock -
O
Clock +
O
Clock Enable
O
12mA
12mA
12mA
12mA
12mA
12mA
12mA
12mA
12mA
12mA
AA23 Data Mask 0
O
W18
H22
G24
Y23
W21
V21
W23
V22
Data Mask 1
O
Data Mask 2
O
Data Mask 3
O
Bidirectional Data #0
Bidirectional Data #1
Bidirectional Data #2
Bidirectional Data #3
Bidirectional Data #4
I/O
I/O
I/O
I/O
I/O
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RAM_DQ5
RAM_DQ6
RAM_DQ7
RAM_DQ8
RAM_DQ9
RAM_DQ10
RAM_DQ11
RAM_DQ12
RAM_DQ13
RAM_DQ14
RAM_DQ15
RAM_DQ16
RAM_DQ17
RAM_DQ18
RAM_DQ19
RAM_DQ20
RAM_DQ21
RAM_DQ22
RAM_DQ23
RAM_DQ24
RAM_DQ25
RAM_DQ26
RAM_DQ27
RAM_DQ28
RAM_DQ29
RAM_DQ30
RAM_DQ31
RAM_DQS0_N
RAM_DQS0_P
RAM_DQS1_N
RAM_DQS1_P
RAM_DQS2_N
RAM_DQS2_P
RAM_DQS3_N
RAM_DQS3_P
RAM_R\A\S\
RAM_W\E\
RFU0
W24
Y22
Bidirectional Data #5
Bidirectional Data #6
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
SSTL18 II
SSTL18 II
SSTL18 II
SSTL18 II
SSTL18 II
SSTL18 II
SSTL18 II
SSTL18 II
SSTL18 II
SSTL18 II
SSTL18 II
SSTL18 II
SSTL18 II
SSTL18 II
SSTL18 II
SSTL18 II
SSTL18 II
SSTL18 II
SSTL18 II
SSTL18 II
SSTL18 II
SSTL18 II
SSTL18 II
SSTL18 II
SSTL18 II
SSTL18 II
SSTL18 II
DIFF SSTL18 II
DIFF SSTL18 II
DIFF SSTL18 II
DIFF SSTL18 II
DIFF SSTL18 II
DIFF SSTL18 II
DIFF SSTL18 II
DIFF SSTL18 II
SSTL18 II
SSTL18 II
PCI33_3
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
12mA
12mA
12mA
12mA
12mA
12mA
12mA
12mA
12mA
12mA
12mA
12mA
12mA
12mA
12mA
12mA
12mA
12mA
12mA
12mA
12mA
12mA
12mA
12mA
12mA
12mA
12mA
AA24 Bidirectional Data #7
AC23 Bidirectional Data #8
Y20
Bidirectional Data #9
Bidirectional Data #10
Bidirectional Data #11
W20
W19
AA22 Bidirectional Data #12
AB22 Bidirectional Data #13
Y17
Bidirectional Data #14
AD24 Bidirectional Data #15
L23
H17
M22
M24
G20
N24
G21
N23
J21
Bidirectional Data #16
Bidirectional Data #17
Bidirectional Data #18
Bidirectional Data #19
Bidirectional Data #20
Bidirectional Data #21
Bidirectional Data #22
Bidirectional Data #23
Bidirectional Data #24
Bidirectional Data #25
Bidirectional Data #26
Bidirectional Data #27
Bidirectional Data #28
Bidirectional Data #29
Bidirectional Data #30
Bidirectional Data #31
G19
H23
F17
H19
L24
H24
J24
AD21 Bidirectional Data Strobe 0 -
AC21 Bidirectional Data Strobe 0 +
AC24 Bidirectional Data Strobe 1 -
AB24 Bidirectional Data Strobe 1 +
C24
D24
D20
E20
U19
U24
Bidirectional Data Strobe 2 -
Bidirectional Data Strobe 2 +
Bidirectional Data Strobe 3 -
Bidirectional Data Strobe 3 +
Row Address Select
12mA
12mA
2mA
Write Enable
O
AE13 CardBus RFU 0 / RESERVED
O
RFU1
J3
CardBus RFU 1 / RESERVED
CardBus RFU 2 / RESERVED
Active Video Indicator
Clock
O
PCI33_3
2mA
RFU2
D13
L4
O
PCI33_3
2mA
VDC_AVID
VDC_CLOCK
VDC_D0
I
LVTTL
W10
R3
P5
V8
R5
Y7
U6
U5
P4
I
LVTTL
YCbCr 4:4:2 #0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
LVTTL
4mA
4mA
4mA
4mA
4mA
4mA
4mA
4mA
VDC_D1
YCbCr 4:4:2 #1
LVTTL
VDC_D2
YCbCr 4:4:2 #2
LVTTL
VDC_D3
YCbCr 4:4:2 #3
LVTTL
VDC_D4
YCbCr 4:4:2 #4
LVTTL
VDC_D5
YCbCr 4:4:2 #5
LVTTL
VDC_D6
YCbCr 4:4:2 #6
LVTTL
VDC_D7
YCbCr 4:4:2 #7
LVTTL
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VDC_FID
P3
L3
Odd / Even Field Indicator
Horizontal Sync
Interrupt Request
Power Control
Reset
I
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
Float
Float
Float
Float
Float
Float
Float
Float
VDC_HSYNC
VDC_INTREQ
VDC_POWER
VDC_RESET
VDC_SCA
I
M4
N4
W8
T9
T8
N3
I/O
O
O
I/O
O
I
4mA
2mA
2mA
4mA
4mA
I2C Serial Data
I2C Serial Clock
Vertical Sync
VDC_SCL
VDC_VSYNC
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Appendix D – CPLD Pinout
CPLD Pinout
Net
Pin
13
35
28
17
1
30
15
12
10
7
Description
Dir
I
O
O
O
Standard Term
Drive
CLOCK_24
F\L\A\S\H\_\B\Y\T\E\
F\L\A\S\H\_\C\E\
F\L\A\S\H\_\O\E\
F\L\A\S\H\_\W\E\
F\P\G\A\_\P\R\O\G\
FLASH_A0
FLASH_A1
FLASH_A2
FLASH_A3
FLASH_A4
Free Running 24 MHz Clock from PSoC
8 Bit Mode Select
Chip Enable
Output Enable
Write Enable
FPGA Asynchronous Erase
Address 0
Address 1
Address 2
Address 3
Address 4
Address 5
Address 6
Address 7
Address 8
Address 9
Address 10
Address 11
Address 12
Address 13
Address 14
Address 15
Address 16
Address 17
Address 18
Address 19
Address 20
Address 21
Address 22
Address 23
Address 24
Address -1*
FPGA Configuration Clock
FPGA Configuration Done
FPGA Ready to Configure
FPGA Reload Request
FPGA Image Address Request
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
Float
Slow
Slow
Slow
Slow
Slow
Slow
Slow
Slow
Slow
Slow
Slow
Slow
Slow
Slow
Slow
Slow
Slow
Slow
Slow
Slow
Slow
Slow
Slow
Slow
Slow
Slow
Slow
Slow
Slow
Slow
Slow
Slow
O
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
8
11
9
FLASH_A5
FLASH_A6
FLASH_A7
FLASH_A8
5
47
48
32
33
45
46
44
37
39
6
FLASH_A9
FLASH_A10
FLASH_A11
FLASH_A12
FLASH_A13
FLASH_A14
FLASH_A15
FLASH_A16
FLASH_A17
FLASH_A18
FLASH_A19
FLASH_A20
FLASH_A21
FLASH_A22
FLASH_A23
FLASH_A24
FLASH_D15
FPGA_CCLK
FPGA_DONE
FPGA_INIT
LOAD
4
24
14
2
43
34
38
36
25
27
26
20
18
I
I
I
I
Float
Float
Float
Float
PEEKABOO
*Pin D15 turns into Address -1 when the Flash ROM is in 8 bit mode.
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Appendix E – PSoC Pinout
PSoC Pinout
3\.\3\V\_\E\N\
23 3.3V Master Power Enable
17 24 MHz TurboLoader Clock Out
PSoC External Debug Clock
10 PSoC External Debug Data
19 PSoC -> FPGA Clock
22 PSoC -> FPGA Data
14 PSoC External Debug Reset
24 Temperature Sensor Chip Select
O
O
CLOCK_24_HV
POWERCTL_C
POWERCTL_D
POWERCTL_FPGA_C
POWERCTL_FPGA_D
POWERCTL_R
TEMP_SENSE_C\S\
TEMP_SENSE_SCK
TEMP_SENSE_SD
7
I/O
I/O
I/O
I/O
I
O
O
I/O
4
5
Temperature Sensor Clock
Temperature Sensor Data
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42
Appendix F – Standard Part Number Listing
Standard Part Number Listing
Device
Part Number
Website
FPGA
XC4VFX20-10FG672C
XC4VFX40-10FG672C
XC4VFX60-10FG672C
XC2C64A-7QFG48I
EDE116ABSE-6E-E
S29GL512N11FAIV010
88E1111-BAB-I1000
AD9233BCPZ-125
AD9744ACPZRL7
TVP5150AM1PBS
MAX6627MTA+
CPLD
RAM
ROM
Ethernet
ADC
DAC
VDC
Temp Sensor
Sleep Controller
CY8C21323-24LFXI
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Appendix G – Errata
The following section lists all known errata:
All versions:
Permanent damage will result if the Pico E-15 is left un-configured and powered on for more
than 10 minutes. This should not be a problem since the Pico E-15 automatically loads an
FPGA image upon power-on.
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Appendix H – FPGA Performance Enhancements
Overview:
Like most silicon devices, the FPGA on the Pico E-15 can be overclocked if proper cooling
techniques are employed. Care must be taken to avoid thermal runaway.
Thermal Runaway:
As the die temperature of the FPGA increases, it draws more power. This extra power gets
turned into heat. If thermal equilibrium is not reached with proper cooling, the FPGA will
overheat. The E-15 is protected against catestropic overtemperature conditions via the
integrated temperature sensor, although the limits should not routinely be pushed. The
maximum FPGA core temperature is 150°C. Note that chips surrounding the FPGA can be
damaged by temperatures above 70°C.
Heat Sink Placement:
The heat sink of the FPGA is internally connected via thermal grease to the case of the
CardBus card on the bottom side (no markings). Placing a large heat sink on the outside of the
case can allow higher performance.
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Revision History
1.00.01
Initial public release
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Legal Notices
FCC Class A
This equipment has been tested and found to comply with the limits for a Class A digital device,
pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable protection against
harmful interference when the equipment is operated in a commercial environment. This equipment
generates, uses, and can radiate radio frequency energy and, if not installed and used in accordance with
the instruction manual, may cause harmful interference to radio communications. Operation of this
equipment in a residential area is likely to cause harmful interference in which case the user is required
to correct the interference at their own expense.
CE Class A
This Class A digital apparatus meets all requirements of the Canadian Interference-Causing Equipment
Regulations.
Pico Computing products are not authorized for use in life-critical applications, or where device failure could
cause injury or disruption of service.
“Xilinx System Generator for DSP” is a registered trademark of Xilinx, INC.
“Xilinx” and associated artwork are registered trademarks of Xilinx, INC.
“Virtex” and associated artwork are registered trademarks of Xilinx, INC.
“Virtex-4” and associated artwork are registered trademarks of Xilinx, INC.
“CoolRunner-II” and associated artwork are registered trademarks of Xilinx, INC.
“MATLAB” is a registered trademark of The MathWorks, INC.
“Simulink” is a registered trademark of The MathWorks, INC.
“PowerPC” and associated artwork are registered trademarks of International Business Machines Corporation.
“MirrorBit” and associated artwork are registered trademarks of Advanced Microdevices, INC.
“AMD” and associated artwork are registered trademarks of Advanced Micro Devices, INC.
“Spansion” and associated artwork are registered trademarks of Spansion, LLC.
“SAMSUNG” and associated artwork are registered trademarks of SAMSUNG Electronics Co. LTD.
“Texas Instruments” and the Texas Instruments logo are registered trademarks of Texas Instruments, INC.
“Linear Technology” and the Linear Technology logo are registered trademarks of Linear Technology Corporation.
“Impulse C” is a registered trademark of Impulse Accelerated Technologies, INC.
“Impulse Accelerated Technologies” and associated artwork are registered trademarks of Impulse Accelerated Technologies, INC.
“µC/OS” is a product of Micrimm.
The “PCMCIA” and “CardBus” standards are governed by the Personal Computer Memory Card International Association.
The “Compact Flash” standard is governed by the Compact Flash Association.
“Viva” is a registered trademark of Star Bridge Systems, Inc.
“Cypress” and associated artwork are registered trademarks of Cypress Semiconductor Corporation
“Maxim” and associated artwork are registered trademarks of Texas Instruments, INC.
This manual is © 2007 Pico Computing, Inc.
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