Philips CD Player SC28L91 User Manual

INTEGRATED CIRCUITS  
SC28L91  
3.3 V or 5.0 V Universal Asynchronous  
Receiver/Transmitter (UART)  
Product data sheet  
2004 Oct 21  
Supersedes data of 2000 Sep 22  
Philips  
Semiconductors  
Download from Www.Somanuals.com. All Manuals Search And Download.  
Philips Semiconductors  
Product data sheet  
3.3 V or 5.0 V Universal Asynchronous  
Receiver/Transmitter (UART)  
SC28L91  
ORDERING INORMATION  
Industrial  
V
CC  
= +3.3 V ± 10 %, +5 V ± 10 %  
Description  
T
= –40 °C to +85 °C  
Drawing Number  
SOT187-2  
amb  
44-Pin Plastic Leaded Chip Carrier (PLCC)  
44-Pin Plastic Quad Flat Pack (PQFP)  
SC28L91A1A  
SC28L91A1B  
SOT307-2  
3
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Philips Semiconductors  
Product data sheet  
3.3 V or 5.0 V Universal Asynchronous  
Receiver/Transmitter (UART)  
SC28L91  
PIN CONFIGURATION DIAGRAM  
80XXX PIN CONFIGURATION  
44  
34  
6
40  
1
7
39  
1
33  
23  
PLCC  
PQFP  
11  
29  
17  
18  
28  
12  
Pin Function  
22  
Pin Function  
Pin Function  
Pin Function  
Pin Function  
Pin Function  
1
2
A3  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
GND  
GND  
INTRN  
D6  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
x2  
1
2
NC  
A0  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
OP5  
OP7  
D1  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
OP2  
OP0  
TxDA  
NC  
IP0  
RESET  
CEN  
IP2  
3
WRN  
RDN  
3
IP3  
A1  
4
4
D3  
5
V
D4  
IP6  
CC  
5
IP1  
A2  
D5  
RxDA  
X1/CLK  
X2  
6
No Connection  
D2  
IP5  
6
D7  
7
OP1  
OP3  
OP5  
OP7  
I/M  
D0  
IP4  
7
A3  
V
SS  
8
NC  
V
V
CC  
8
IP0  
WRN  
RDN  
NC  
RESET  
CEN  
IP2  
9
OP6  
OP4  
OP2  
OP0  
TxDA  
RxDA  
x1/clk  
CC  
9
INTRN  
D6  
10  
11  
12  
13  
14  
15  
A0  
IP3  
A1  
IP1  
A2  
10  
11  
12  
13  
14  
15  
V
D4  
IP6  
CC  
D1  
I/M  
D2  
IP5  
D3  
No Connection  
OP1  
D0  
IP4  
D5  
OP6  
OP4  
V
CC  
D7  
OP3  
SD00699  
SD00698  
Note: Pins marked “No Connection” must NOT be connected.  
4
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Philips Semiconductors  
Product data sheet  
3.3 V or 5.0 V Universal Asynchronous  
Receiver/Transmitter (UART)  
SC28L91  
PIN CONFIGURATION DIAGRAM  
68XXX PIN CONFIGURATION  
44  
34  
6
40  
1
7
39  
1
33  
23  
PLCC  
PQFP  
11  
29  
17  
18  
28  
12  
Pin Function  
22  
Pin Function  
Pin Function  
Pin Function  
Pin Function  
Pin Function  
1
2
A3  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
GND  
GND  
INTRN  
D6  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
x2  
1
2
NC  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
OP5  
OP7  
D1  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
OP2  
IP0  
RESETN  
CEN  
IP2  
A0  
OP0  
3
R/WN  
DACKN  
3
IP3  
TxDA  
NC  
4
4
A1  
D3  
5
V
D4  
IACKN  
IP5  
CC  
5
IP1  
D5  
RxDA  
X1/CLK  
X2  
6
No Connection  
D2  
6
A2  
D7  
7
OP1  
OP3  
OP5  
OP7  
I/M  
D0  
IP4  
7
A3  
V
SS  
8
NC  
V
V
CC  
8
IP0  
NC  
RESETN  
CEN  
IP2  
9
OP6  
OP4  
OP2  
OP0  
TxDA  
RxDA  
x1/clk  
CC  
9
R/WN  
DACKN  
INTRN  
D6  
10  
11  
12  
13  
14  
15  
A0  
IP3  
A1  
IP1  
A2  
10  
11  
12  
13  
14  
15  
V
D4  
IACKN  
IP5  
CC  
D1  
I/M  
D2  
D3  
No Connection  
OP1  
D0  
IP4  
D5  
OP6  
OP4  
V
CC  
D7  
OP3  
SD00701  
SD00700  
Note: Pins marked “No Connection” must NOT be connected.  
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Product data sheet  
3.3 V or 5.0 V Universal Asynchronous  
Receiver/Transmitter (UART)  
SC28L91  
8
DATA CHANNEL  
D0–D7  
RDN  
BUS BUFFER  
16 BYTE TRANSMIT  
FIFO  
TxDA  
RxDA  
TRANSMIT  
SHIFT REGISTER  
OPERATION CONTROL  
16 BYTE RECEIVE  
FIFO  
WRN  
CEN  
ADDRESS  
DECODE  
WATCH DOG TIMER  
4
A0–A3  
RESET  
RECEIVE SHIFT  
REGISTER  
R/W CONTROL  
MRA0, 1, 2  
CRA  
SRA  
INTERRUPT CONTROL  
IMR  
INTRN  
ISR  
GP  
INPUT PORT  
CHANGE OF  
STATE  
DETECTORS (4)  
TIMING  
7
IP0-IP6  
BAUD RATE  
GENERATOR  
IPCR  
ACR  
CLOCK  
SELECTORS  
COUNTER/  
TIMER  
OUTPUT PORT  
FUNCTION  
SELECT LOGIC  
8
OP0-OP7  
X1/CLK  
X2  
XTAL OSC  
OPCR  
OPR  
CSR  
ACR  
CTL  
CTU  
V
V
CC  
SS  
SD00702  
Figure 1. Block Diagram (80XXX mode)  
6
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Philips Semiconductors  
Product data sheet  
3.3 V or 5.0 V Universal Asynchronous  
Receiver/Transmitter (UART)  
SC28L91  
8
DATA CHANNEL  
D0–D7  
BUS BUFFER  
16 BYTE TRANSMIT  
FIFO  
TxDA  
RxDA  
TRANSMIT  
SHIFT REGISTER  
OPERATION CONTROL  
R/WN  
16 BYTE RECEIVE  
FIFO  
IACKN  
CEN  
ADDRESS  
DECODE  
WATCH DOG TIMER  
4
A0–A3  
RESETN  
RECEIVE SHIFT  
REGISTER  
R/W CONTROL  
MRA0, 1, 2  
CRA  
SRA  
INTERRUPT CONTROL  
IMR  
INTRN  
ISR  
IVR  
DACKN  
INPUT PORT  
CHANGE OF  
STATE  
DETECTORS (4)  
TIMING  
6
IP0-IP5  
BAUD RATE  
GENERATOR  
IPCR  
ACR  
CLOCK  
SELECTORS  
COUNTER/  
TIMER  
OUTPUT PORT  
FUNCTION  
SELECT LOGIC  
8
OP0-OP7  
X1/CLK  
X2  
XTAL OSC  
OPCR  
OPR  
CSR  
ACR  
CTL  
CTU  
V
V
CC  
SS  
SD00703  
Figure 2. Block Diagram (68XXX mode)  
7
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Philips Semiconductors  
Product data sheet  
3.3 V or 5.0 V Universal Asynchronous  
Receiver/Transmitter (UART)  
SC28L91  
PIN CONFIGURATION FOR 80XXX BUS INTERFACE (INTEL )  
Pin  
type  
Symbol  
I/M  
Name and function  
I
Bus Configuration: When high or not connected configures the bus interface to the Conditions shown in this table.  
D0–D7  
I/O  
Data Bus: Bi-directional 3-State data bus used to transfer commands, data and status between the UART and the  
CPU. D0 is the least significant bit.  
CEN  
I
Chip Enable: Active-Low input signal. When Low, data transfers between the CPU and the UART are enabled on  
D0–D7 as controlled by the WRN, RDN and A0–A3 inputs. When High, places the D0–D7 lines in the 3-State condi-  
tion.  
WRN  
RDN  
I
I
Write Strobe: When Low and CEN is also Low, the contents of the data bus is loaded into the addressed register. The  
transfer occurs on the rising edge of the signal.  
Read Strobe: When Low and CEN is also Low, causes the contents of the addressed register to be presented on the  
data bus. The read cycle begins on the falling edge of RDN.  
A0–A3  
I
I
Address Inputs: Select the UART internal registers and ports for read/write operations.  
RESET  
Reset: A High level clears internal registers (SR, IMR, ISR, OPR, OPCR), puts OP0–OP7 in the High state, stops the  
counter/timer, and puts the Channel in the inactive state, with the TxD outputs in the mark (High) state. Sets MR point-  
er to MR1. See Figure 4  
INTRN  
X1/CLK  
X2  
O
I
Interrupt Request: Active-Low, open-drain, output which signals the CPU that one or more of the eight maskable in-  
terrupting conditions are true. This pin requires a pull-up device.  
Crystal 1: Crystal or external clock input. A crystal or clock of the specified limits must be supplied at all times. When a  
crystal is used, a capacitor must be connected from this pin to ground (see Figure 11).  
O
Crystal 2: Connection for other side of the crystal. When a crystal is used, a capacitor must be connected from this pin  
to ground (see Figure 11). If X1/CLK is driven from an external source, this pin must be left open.  
RxD  
TxD  
I
Receiver Serial Data Input: The least significant bit is received first. “Mark” is High; “space” is Low.  
O
Transmitter Serial Data Output: The least significant bit is transmitted first. This output is held in the “mark” condition  
when the transmitter is disabled, idle or operating in local loop back mode. “Mark” is High; “space” is Low.  
OP0  
O
Output 0: General-purpose output or request to send (RTSN, active-Low). Can be deactivated automatically on re-  
ceive or transmit.  
OP1  
OP2  
OP3  
OP4  
OP5  
OP6  
OP7  
IP0  
O
O
O
O
O
O
O
I
Output 1: General-purpose output.  
Output 2: General-purpose output, or transmitter 1X or 16X clock output, or receiver 1X clock output.  
Output 3: General-purpose output.  
Output 4: General-purpose output or open-drain, active-Low, Rx interrupt ISR[1] output. DMA Control  
Output 5: General-purpose output  
Output 6: General-purpose output or open-drain, active-Low, Tx interrupt ISR[0] output. DMA Control  
Output 7: General-purpose output.  
Input 0: General-purpose input or clear to send active-Low input (CTSN). Has Change of State Dector.  
Input 1: General-purpose input. Has Change of State Dector.  
IP1  
I
IP2  
I
Input 2: General-purpose input or counter/timer external clock input. Has Change of State Dector.  
IP3  
I
Input 3: General-purpose input or transmitter external clock input (TxC). When the external clock is used by the trans-  
mitter, the transmitted data is clocked on the falling edge of the clock. Has Change of State Dector.  
IP4  
I
Input 4: General-purpose input or receiver external clock input (RxC). When the external clock is used by the receiver,  
the received data is sampled on the rising edge of the clock.  
IP5  
IP6  
I
Input 5: General-purpose input  
Input 6: General-purpose input  
Power Supply: +3.3 V or +5 V supply input ± 10 %  
Ground  
I
V
CC  
Pwr  
Pwr  
GND  
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Philips Semiconductors  
Product data sheet  
3.3 V or 5.0 V Universal Asynchronous  
Receiver/Transmitter (UART)  
SC28L91  
PIN CONFIGURATION FOR 68XXX BUS INTERFACE (MOTOROLA )  
Pin  
type  
Symbol  
I/M  
Name and function  
I
Bus Configuration: When low configures the bus interface to the Conditions shown in this table.  
D0–D7  
I/O  
Data Bus: Bi-directional 3-State data bus used to transfer commands, data and status between the UART and the  
CPU. D0 is the least significant bit.  
CEN  
I
Chip Enable: Active-Low input signal. When Low, data transfers between the CPU and the UART are enabled on  
D0–D7 as controlled by the R/WN and A0–A3 inputs. When High, places the D0–D7 lines in the 3-State condition.  
R/WN  
I
I
Read/Write: Input Signal. When CEN is low R/WN high input indicates a read cycle; when low indicates a write cycle.  
IACKN  
Interrupt Acknowledge: Active low input indicating an interrupt acknowledge cycle. Usually asserted by the CPU in  
response to an interrupt request. When asserted places the interrupt vector on the bus and asserts DACKN.  
DACKN  
O
Data Transfer Acknowledge: A3-State active-low output asserted in a write, read, or interrupt acknowledge cycle to  
indicate proper transfer of data between the CPU and the UART.  
A0–A3  
I
I
Address Inputs: Select the UART internal registers and ports for read/write operations.  
RESETN  
Reset: A low level clears internal registers (SRA, SRB, IMR, ISR, OPR, OPCR), puts OP0–OP7 in the High state,  
stops the counter/timer, and puts the Channel in the inactive state, with the TxD outputs in the mark (High) state. Sets  
MR pointer to MR1. See Figure 4  
INTRN  
X1/CLK  
X2  
O
I
Interrupt Request: Active-Low, open-drain, output which signals the CPU that one or more of the eight maskable  
interrupting conditions are true. This pin requires a pullup.  
Crystal 1: Crystal or external clock input. A crystal or clock of the specified limits must be supplied at all times. When  
a crystal is used, a capacitor must be connected from this pin to ground (see Figure 11).  
O
Crystal 2: Connection for other side of the crystal. When a crystal is used, a capacitor must be connected from this  
pin to ground (see Figure 11). If X1/CLK is driven from an external source, this pin must be left open.  
RxD  
TxD  
I
Receiver Serial Data Input: The least significant bit is received first. “Mark” is High, “space” is Low.  
O
Transmitter Serial Data Output: The least significant bit is transmitted first. This output is held in the ‘mark’ condition  
when the transmitter is disabled, idle, or when operating in local loop back mode. ‘Mark’ is High; ‘space’ is Low.  
OP0  
O
Output 0: General purpose output or request to send (RTSAN, active-Low). Can be deactivated automatically on  
receive or transmit.  
OP1  
OP2  
OP3  
OP4  
OP5  
OP6  
OP7  
IP0  
O
O
O
O
O
O
O
I
Output 1: General-purpose output.  
Output 2: General purpose output or transmitter 1X or 16X clock output, or receiver 1X clock output.  
Output 3: General purpose output.  
Output 4: General purpose output or open-drain, active-Low, RxA interrupt ISR [1] output. DMA Control  
Output 5: General-purpose output.  
Output 6: General purpose output or open-drain, active-Low, TxA interrupt ISR[0] output. DMA Control  
Output 7: General-purpose output.  
Input 0: General purpose input or clear to send active-Low input (CTSAN). Has Change of State Dector.  
Input 1: General purpose input. Has Change of State Dector.  
IP1  
I
IP2  
I
Input 2: General-purpose input or counter/timer external clock input. Has Change of State Dector.  
IP3  
I
Input 3: General purpose input or transmitter external clock input (TxC). When the external clock is used by the trans-  
mitter, the transmitted data is clocked on the falling edge of the clock. Has Change of State Dector.  
IP4  
I
Input 4: General purpose input or receiver external clock input (RxC). When the external clock is used by the receiver,  
the received data is sampled on the rising edge of the clock.  
IP5  
I
Input 5: General purpose input.  
Power Supply: +3.3 or +5V supply input ±10%  
Ground  
V
CC  
Pwr  
Pwr  
GND  
9
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Philips Semiconductors  
Product data sheet  
3.3 V or 5.0 V Universal Asynchronous  
Receiver/Transmitter (UART)  
SC28L91  
1
ABSOLUTE MAXIMUM RATINGS  
Symbol  
Parameter  
Rating  
Unit  
°C  
2
T
amb  
Operating ambient temperature range  
Note 4  
T
Storage temperature range  
–65 to +150  
–0.5 to +7.0  
°C  
stg  
3
V
V
P
P
Voltage from V to GND  
V
CC  
CC  
3
Voltage from any pin to GND  
–0.5 to V +0.5  
V
S
CC  
Package power dissipation (PLCC44)  
Package power dissipation (PQFP44)  
2.4  
1.78  
19  
W
D
W
D
Derating factor above 25 °C (PLCC44)  
mW/°C  
mW/°C  
Derating factor above 25 °C (PQFP44)  
14  
NOTES:  
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and  
functional operation of the device at these or any other condition above those indicated in the operation section of this specification is not  
implied.  
2. For operating at elevated temperatures, the device must be derated based on +150°C maximum junction temperature.  
3. This product includes circuitry specifically designed for the protection of its internal devices from damaging effects of excessive static  
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima.  
4. Parameters are valid over specified temperature and voltage range.  
1, 2, 3  
DC ELECTRICAL CHARACTERISTICS  
V
= 5 V ± 10 %, T  
= –40 °C to +85 °C, unless otherwise specified.  
CC  
amb  
Symbol  
Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
V
V
V
V
V
Input low voltage  
0.8  
IL  
Input high voltage (except X1/CLK)  
Input high voltage (X1/CLK)  
Output low voltage  
2.4  
1.5  
2.4  
0.2  
V
IH  
IH  
OL  
0.8V  
V
CC  
0.4  
V
I
I
= 2.4 mA  
= –400 µA  
= 0 V to V  
OL  
4
V
I
Output high voltage (except OD outputs)  
V
CC  
– 0.5  
V
OH  
OH  
X1/CLK input current - power down  
X1/CLK input low current - operating  
X1/CLK input high current - operating  
Input leakage current:  
0.5  
0.05  
0.5  
0
µA  
µA  
µA  
V
V
V
IX1PD  
IN  
IN  
IN  
CC  
I
I
= 0 V  
= V  
–130  
0
ILX1  
130  
IHX1  
CC  
All except input port pins  
V
IN  
V
IN  
V
IN  
V
IN  
V
IN  
V
IN  
= 0 V to V  
= 0 V to V  
–0.5  
–8  
0.05  
0.05  
+0.5  
+0.5  
0.5  
µA  
µA  
µA  
µA  
µA  
µA  
I
CC  
I
5
Input port pins  
CC  
I
I
I
I
Output off current high, 3-State data bus  
Output off current low, 3-State data bus  
= V  
OZH  
OZL  
ODL  
ODH  
CC  
= 0 V  
= 0 V  
–0.5  
–0.5  
Open-drain output low current in off-state  
Open-drain output high current in off-state  
= V  
0.5  
CC  
6
Power supply current  
Operating mode  
CMOS input levels  
CMOS input levels  
7
25  
5
mA  
I
CC  
Power down mode  
1  
mA  
NOTES:  
1. Parameters are valid over specified temperature and voltage range.  
2. All voltage measurements are referenced to ground (GND). For testing, all inputs swing between 0.4 V and 3.0 V with a transition time of  
5 ns maximum. For X1/CLK, this swing is between 0.4 V and 0.8V . All time measurements are referenced at input voltages of 0.8 V and  
CC  
2.0 V and output voltages of 0.8 V and 2.0 V, as appropriate.  
3. Typical values are at +25 °C, typical supply voltages, and typical processing parameters.  
4. Test conditions for outputs: C = 125 pF, except open drain outputs. Test conditions for open drain outputs: C = 125 pF,  
L
L
constant current source = 2.6 mA.  
5. Input port pins have active pull-up transistors that will source a typical 2 µA from V when the input pins are at V  
.
SS  
CC  
Input port pins at V source 0.0 µA.  
CC  
6. All outputs are disconnected. Inputs are switching between CMOS levels of V – 0.2 V and V + 0.2 V.  
CC  
SS  
10  
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2004 Oct 21  
Philips Semiconductors  
Product data sheet  
3.3 V or 5.0 V Universal Asynchronous  
Receiver/Transmitter (UART)  
SC28L91  
1, 2, 3  
DC ELECTRICAL CHARACTERISTICS  
V
= 3.3 V ± 10 %, T  
= –40 °C to +85 °C, unless otherwise specified.  
CC  
amb  
Symbol  
Parameter  
Conditions  
Min  
Typ  
0.65  
1.7  
Max  
Unit  
V
V
V
V
Input low voltage  
Input high voltage  
Output low voltage  
0.2*V  
IL  
CC  
0.8*V  
V
IH  
OL  
CC  
0.2  
0.4  
V
I
I
= 2.4 mA  
= –400 µA  
= 0 V to V  
OL  
4
V
I
Output high voltage (except OD outputs)  
V
CC  
– 0.5  
V
CC  
– 0.2  
V
OH  
OH  
X1/CLK input current - power down  
X1/CLK input low current - operating  
X1/CLK input high current - operating  
Input leakage current:  
–0.5  
–80  
0
0.05  
+0.5  
0
µA  
µA  
µA  
V
V
V
IX1PD  
IN  
IN  
IN  
CC  
I
I
= 0 V  
= V  
ILX1  
80  
IHX1  
CC  
All except input port pins  
V
IN  
V
IN  
V
IN  
V
IN  
V
IN  
V
IN  
= 0 V to V  
= 0 V to V  
–0.5  
–8  
0.05  
0.5  
+0.5  
+0.5  
0.5  
µA  
µA  
µA  
µA  
µA  
µA  
I
CC  
I
5
Input port pins  
CC  
I
I
I
I
Output off current high, 3-State data bus  
Output off current low, 3-State data bus  
= V  
OZH  
OZL  
ODL  
ODH  
CC  
= 0 V  
= 0 V  
–0.5  
–0.5  
Open-drain output low current in off-state  
Open-drain output high current in off-state  
= V  
0.5  
CC  
6
Power supply current  
Operating mode  
CMOS input levels  
CMOS input levels  
5
mA  
I
CC  
Power down mode  
1  
5.0  
mA  
NOTES:  
1. Parameters are valid over specified temperature and voltage range.  
2. All voltage measurements are referenced to ground (GND). For testing, all inputs swing between 0.4 V and 3.0 V with a transition time of  
5 ns maximum. For X1/CLK, this swing is between 0.4 V and 0.8*V . All time measurements are referenced at input voltages of 0.8 V and  
CC  
2.0 V and output voltages of 0.8 V and 2.0 V, as appropriate.  
3. Typical values are at +25 °C, typical supply voltages, and typical processing parameters.  
4. Test conditions for outputs: C = 125 pF, except open drain outputs. Test conditions for open drain outputs: C = 125 pF,  
L
L
constant current source = 2.6 mA.  
5. Input port pins have active pull-up transistors that will source a typical 2 µA from V when the input pins are at V  
.
SS  
CC  
Input port pins at V source 0.0 µA.  
CC  
6. All outputs are disconnected. Inputs are switching between CMOS levels of V – 0.2 V and V + 0.2 V.  
CC  
SS  
11  
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2004 Oct 21  
Philips Semiconductors  
Product data sheet  
3.3 V or 5.0 V Universal Asynchronous  
Receiver/Transmitter (UART)  
SC28L91  
1, 2, 3, 4  
AC CHARACTERISTICS (5 VOLT)  
V
= 5.0 V ± 10 %, T  
= –40 °C to +85 °C, unless otherwise specified.  
CC  
amb  
Symbol  
Reset Timing (See Figure 4)  
Reset pulse width  
Parameter  
Min  
Typ  
Max  
Unit  
t
100  
18  
ns  
RES  
5
Bus Timing (See Figure 5)  
t
t
t
t
t
t
t
t
t
t
t
t
A0–A3 setup time to RDN, WRN Low  
10  
20  
0
6
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
*AS  
*AH  
*CS  
*CH  
*RW  
*DD  
*DA  
*DF  
*DI  
A0–A3 hold time from RDN, WRN low  
12  
CEN setup time to RDN, WRN low  
CEN Hold time from RDN. WRN low  
0
WRN, RDN pulse width (Low time)  
15  
8
Data valid after RDN low (125pF load. See Figure 3 for smaller loads.)  
40  
55  
20  
6
RDN low to data bus active  
0
Data bus floating after RDN or CEN high  
7
RDN or CEN high to data bus invalid  
0
Data bus setup time before WRN or CEN high (write cycle)  
Data hold time after WRN high  
25  
0
*DS  
*DH  
*RWD  
–12  
5, 7  
High time between read and/or write cycles  
17  
5
Port Timing (See Figure 9)  
t
t
t
Port in setup time before RDN low (Read IP ports cycle)  
Port in hold time after RDN high  
0
0
–20  
–20  
40  
ns  
ns  
ns  
*PS  
*PH  
*PD  
OP port valid after WRN or CEN high (OPR write cycle)  
60  
Interrupt Timing (See Figure 10)  
INTRN (or OP3–OP7 when used as interrupts) negated from:  
t
*IR  
Read RxFIFO (RxRDY/FFULL interrupt)  
Write TxFIFO (TxRDY interrupt)  
40  
40  
40  
40  
40  
40  
60  
60  
60  
60  
60  
60  
ns  
ns  
ns  
ns  
ns  
ns  
Reset Command (delta break change interrupt)  
Stop C/T command (Counter/timer interrupt  
Read IPCR (delta input port change interrupt)  
Write IMR (Clear of change interrupt mask bit(s))  
Clock Timing (See Figure 11)  
t
f
f
f
t
f
X1/CLK high or low time  
30  
0.1  
30  
0
20  
ns  
*CLK  
*CLK  
*CTC  
*CTC  
*RX  
8
X1/CLK frequency (for higher speeds contact factory)  
3.686 8.0  
MHz  
ns  
C/T Clk (IP2) high or low time (C/T external clock input)  
10  
8.0  
10  
16  
1
8
C/T Clk (IP2) frequency (for higher speeds contact factory)  
MHz  
ns  
RxC high or low time (16X)  
30  
0
RxC Frequency (16X)(for higher speeds contact factory)  
MHz  
MHz  
ns  
*RX  
8, 9  
RxC Frequency (1x)  
0
t
f
TxC High or low time (16X)  
30  
10  
16  
1
*TX  
TxC frequency (16X) (for higher speeds contact factory)  
MHz  
MHz  
*TX  
8, 9  
TxC frequency (1X)  
0
Transmitter Timing, external clock (See Figure 12)  
t
TxD output delay from TxC low (TxC input pin)  
40  
6
60  
30  
ns  
ns  
*TXD  
*TCS  
t
Output delay from TxC output pin low to TxD data output  
12  
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Philips Semiconductors  
Product data sheet  
3.3 V or 5.0 V Universal Asynchronous  
Receiver/Transmitter (UART)  
SC28L91  
Symbol  
Parameter  
Min  
Typ  
Max  
Unit  
Receiver Timing, external clock (See Figure 13)  
t
t
RxD data setup time to RxC high  
RxD data hold time from RxC high  
50  
50  
40  
40  
ns  
ns  
*RXS  
*RXH  
10  
68000 or Motorola bus timing (See Figures 6, 7, 8)  
10  
t
t
t
t
DACKN Low (read cycle) from X1 High  
15  
15  
8
35  
35  
10  
ns  
ns  
ns  
ns  
DCR  
DCW  
DAT  
DACKN Low (write cycle) from X1 High  
DACKN High impedance from CEN or IACKN High  
CEN or IACKN setup time to X1 High for minimum DACKN cycle  
16  
CSC  
NOTES:  
1. Parameters are valid over specified temperature and voltage range.  
2. All voltage measurements are referenced to ground (GND). For testing, all inputs swing between 0.4 V and 3.0 V with a transition time of  
5 ns maximum. For X1/CLK this swing is between 0.4 V and 0.8*V . All time measurements are referenced at input voltages of 0.8 V and  
CC  
2.0 V and output voltages of 0.8 V and 2.0 V, as appropriate.  
3. Test conditions for outputs: CL = 125 pF, except open drain outputs. Test conditions for open drain outputs: C = 125 pF,  
L
constant current source = 2.6 mA.  
4. Typical values are the average values at +25 °C and 5 V.  
5. Timing is illustrated and referenced to the WRN and RDN Inputs. Also, CEN may be the “strobing” input. CEN and RDN (also CEN and  
WRN) are ORed internally. The signal asserted last initiates the cycle and the signal negated first terminates the cycle.  
6. Guaranteed by characterization of sample units.  
7. If CEN is used as the “strobing” input, the parameter defines the minimum High times between one CEN and the next. The RDN signal must  
be negated for t  
to guarantee that any status register changes are valid.  
RWD  
8. Minimum frequencies are not tested but are guaranteed by design.  
9. Clocks for 1X mode should maintain a 60/40 duty cycle or better.  
10.Minimum DACKN time is t  
= t  
+ t  
+ two positive edges of the X1 clock. For faster bus cycles, the 80XXX bus timing may be used  
DCR  
DSC  
DCR  
while in the 68XXX mode. It is not necessary to wait for DACKN to insure the proper operation of the SC28C91. In all cases the data will be  
written to the SC28L91 on the falling edge of DACKN or the rise of CEN. The fall of CEN initializes the bus cycle. The rise of CEN ends the  
bus cycle. DACKN low or CEN high completes the write cycle.  
60  
V
= 3.3 V @ +25 °C  
CC  
55  
50  
45  
40  
35  
30  
25  
20  
15  
10  
5
5.0 V @ +25 °C  
T
dd  
(ns)  
12 pF  
30 pF  
100 pF  
100  
125 pF  
230 pF  
0
0
20  
40  
60  
80  
120  
pF  
140  
160  
180  
200  
220  
240  
SD00684  
NOTES:  
Bus cycle times:  
(80XXX mode): t + t  
= 70 ns @ 5V, 40 ns @ 3.3 V + rise and fall time of control signals  
DD  
RWD  
(68XXX mode) = t  
+ t  
+ 1 cycle of the X1 clock @ 5 V + rise and fall time of control signals  
CSC  
DAT  
Figure 3. Port Timing vs. Capacitive Loading at typical conditions  
13  
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Product data sheet  
3.3 V or 5.0 V Universal Asynchronous  
Receiver/Transmitter (UART)  
SC28L91  
1, 2, 3, 4  
AC CHARACTERISTICS (3.3 VOLT)  
V
= 3.3 V ± 10 %, T  
= –40 °C to +85 °C, unless otherwise specified.  
CC  
amb  
Symbol  
Reset Timing (See Figure 4)  
Reset pulse width  
Parameter  
Min  
Typ  
20  
6
Max  
Unit  
t
100  
ns  
RES  
5
Bus Timing (See Figure 5)  
t
t
t
t
t
t
t
t
t
t
t
t
A0–A3 setup time to RDN, WRN Low  
10  
33  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
*AS  
*AH  
*CS  
*CH  
*RW  
*DD  
*DA  
*DF  
*DI  
A0–A3 hold time from RDN, WRN low  
CEN setup time to RDN, WRN low  
CEN Hold time from RDN. WRN low  
0
WRN, RDN pulse width (Low time)  
20  
10  
46  
Data valid after RDN low (125pF load. See Figure 3 for smaller loads.)  
75  
20  
6
RDN low to data bus active  
0
Data bus floating after RDN or CEN high  
15  
7
RDN or CEN high to data bus invalid  
0
Data bus setup time before WRN or CEN high (write cycle)  
Data hold time after WRN high  
43  
0
*DS  
*DH  
*RWD  
–15  
5, 7  
High time between read and/or write cycles  
27  
5
Port Timing (See Figure 9)  
t
t
t
Port in setup time before RDN low (Read IP ports cycle)  
Port in hold time after RDN high  
0
0
–20  
–20  
50  
ns  
ns  
ns  
*PS  
*PH  
*PD  
OP port valid after WRN or CEN high (OPR write cycle)  
75  
Interrupt Timing (See Figure 10)  
INTRN (or OP3–OP7 when used as interrupts) negated from:  
t
*IR  
Read RxFIFO (RxRDY/FFULL interrupt)  
Write TxFIFO (TxRDY interrupt)  
40  
40  
40  
40  
40  
40  
79  
79  
79  
79  
79  
79  
ns  
ns  
ns  
ns  
ns  
ns  
Reset Command (delta break change interrupt)  
Stop C/T command (Counter/timer interrupt)  
Read IPCR (delta input port change interrupt)  
Write IMR (Clear of change interrupt mask bit(s))  
Clock Timing (See Figure 11)  
t
f
f
f
t
f
X1/CLK high or low time  
35  
0.1  
30  
0
25  
ns  
*CLK  
*CLK  
*CTC  
*CTC  
*RX  
8
X1/CLK frequency (for higher speeds contact factory)  
3.686  
15  
8
8
MHz  
ns  
C/T Clk (IP2) high or low time (C/T external clock input)  
8
C/T Clk (IP2) frequency (for higher speeds contact factory)  
MHz  
ns  
RxC high or low time (16X)  
30  
0
10  
15  
RxC Frequency (16X) (for higher speeds contact factory)  
16  
1
MHz  
MHz  
ns  
*RX  
8, 9  
RxC Frequency (1x)  
0
t
f
TxC High or low time (16X)  
30  
*TX  
TxC frequency (16X) (for higher speeds contact factory)  
16  
1
MHz  
MHz  
*TX  
8, 9  
TxC frequency (1X)  
0
Transmitter Timing, external clock (See Figure 12)  
t
TxD output delay from TxC low (TxC input pin)  
40  
8
78  
30  
ns  
ns  
*TXD  
*TCS  
t
Output delay from TxC output pin low to TxD data output  
14  
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Philips Semiconductors  
Product data sheet  
3.3 V or 5.0 V Universal Asynchronous  
Receiver/Transmitter (UART)  
SC28L91  
Symbol  
Parameter  
Min  
Typ  
Max  
Unit  
Receiver Timing, external clock (See Figure 13)  
t
t
RxD data setup time to RxC high  
RxD data hold time from RxC high  
50  
50  
10  
10  
ns  
ns  
*RXS  
*RXH  
10  
68000 or Motorola bus timing (See Figures 6, 7, 8)  
10  
t
t
t
t
DACKN Low (read cycle) from X1 High  
18  
18  
10  
10  
57  
57  
15  
ns  
ns  
ns  
ns  
DCR  
DCW  
DAT  
DACKN Low (write cycle) from X1 High  
DACKN High impedance from CEN or IACKN High  
CEN or IACKN setup time to X1 High for minimum DACKN cycle  
30  
CSC  
NOTES:  
1. Parameters are valid over specified temperature and voltage range.  
2. All voltage measurements are referenced to ground (GND). For testing, all inputs swing between 0.4 V and 3.0 V with a transition time of  
5 ns maximum. For X1/CLK this swing is between 0.4 V and 0.8*V . All time measurements are referenced at input voltages of 0.8 V and  
CC  
2.0 V and output voltages of 0.8 V and 2.0 V, as appropriate.  
3. Test conditions for outputs: CL = 125 pF, except open drain outputs. Test conditions for open drain outputs: C = 125 pF,  
L
constant current source = 2.6 mA.  
4. Typical values are the average values at +25 °C and 3.3 V.  
5. Timing is illustrated and referenced to the WRN and RDN Inputs. Also, CEN may be the “strobing” input. CEN and RDN (also CEN and  
WRN) are ORed internally. The signal asserted last initiates the cycle and the signal negated first terminates the cycle.  
6. Guaranteed by characterization of sample units.  
7. If CEN is used as the “strobing” input, the parameter defines the minimum High times between one CEN and the next. The RDN signal must  
be negated for t  
to guarantee that any status register changes are valid.  
RWD  
8. Minimum frequencies are not tested but are guaranteed by design.  
9. Clocks for 1X mode should maintain a 60/40 duty cycle or better.  
10.Minimum DACKN time is t  
= t  
+ t  
+ two positive edges of the X1 clock. For faster bus cycles, the 80XXX bus timing may be used  
DCR  
DSC  
DCR  
while in the 68XXX mode. It is not necessary to wait for DACKN to insure the proper operation of the SC28C91. In all cases the data will be  
written to the SC28L91 on the falling edge of DACKN or the rise of CEN. The fall of CEN initializes the bus cycle. The rise of CEN ends the  
bus cycle. DACKN low or CEN high completes the write cycle.  
15  
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Philips Semiconductors  
Product data sheet  
3.3 V or 5.0 V Universal Asynchronous  
Receiver/Transmitter (UART)  
SC28L91  
Block Diagram  
TIMING CIRCUITS  
Crystal Clock  
The SC28L91 UART consists of the following seven major sections:  
data bus buffer, operation control, interrupt control, timing, Rx and  
Tx FIFO Buffers, input port and output port control. Refer to the  
Block Diagram.  
The timing block consists of a crystal oscillator, a baud rate  
generator, a programmable 16-bit counter/timer, and four clock  
selectors. The crystal oscillator operates directly from a crystal  
connected across the X1/CLK and X2 inputs. If an external clock of  
the appropriate frequency is available, it may be connected to  
X1/CLK. The clock serves as the basic timing reference for the Baud  
Rate Generator (BRG), the counter/timer, and other internal circuits.  
A clock signal within the limits specified in the specifications section  
of this data sheet must always be supplied to the UART. If an  
external clock is used instead of a crystal, X1 should be driven using  
a configuration similar to the one in Figure 11. X2 should be open or  
driving a nominal gate load. Nominal crystal rate is 3.6864 MHz.  
Rates up to 8 MHz may be used.  
Data Bus Buffer  
The data bus buffer provides the interface between the external and  
internal data buses. It is controlled by the operation control block to  
allow read and write operations to take place between the controlling  
CPU and the UART.  
Operation Control  
The operation control logic receives operation commands from the  
CPU and generates appropriate signals to internal sections to  
control device operation. It contains address decoding and read and  
write circuits to permit communications with the microprocessor via  
the data bus.  
BRG  
The baud rate generator operates from the oscillator or external  
clock input and is capable of generating 28 commonly used data  
communications baud rates ranging from 50 to 38.4 K baud.  
Programming bit 0 of MR0 to a “1” gives additional baud rates of  
57.6 kB, 115.2 kB and 230.4 kB (500 kHz with X1 at 8.0 MHz).  
These will be in the 16X mode. A 3.6864 MHz crystal or external  
clock must be used to get the standard baud rates. The clock  
outputs from the BRG are at 16X the actual baud rate. The  
counter/timer can be used as a timer to produce a 16X clock for any  
other baud rate by counting down the crystal clock or an external  
clock. The four clock selectors allow the independent selection, for  
the receiver and transmitter, of any of these baud rates or external  
timing signal.  
Interrupt Control  
A single active-Low interrupt output (INTRN) is provided which is  
activated upon the occurrence of any of eight internal events.  
Associated with the interrupt system are the Interrupt Mask Register  
(IMR) and the Interrupt Status Register (ISR). The IMR can be  
programmed to select only certain conditions to cause INTRN to be  
asserted. The ISR can be read by the CPU to determine all currently  
active interrupting conditions. Outputs OP3–OP7 can be  
programmed to provide discrete interrupt outputs for the transmitter,  
receiver, and counter/timer. Programming the OP3 to OP7 pins as  
interrupts causes their output buffers to change to an open drain  
active low configuration. The OP pins may be used for DMA and  
modem control as well. (See output port notes).  
Counter/Timer  
FIFO Configuration  
The counter timer is a 16-bit programmable divider that operates in  
one of three modes: counter, timer, and time out. In the timer mode it  
generates a square wave. In the counter mode it generates a time  
delay. In the time out mode it monitors the time between received  
characters. The C/T uses the numbers loaded into the  
Counter/Timer Lower Register (CTLR) and the Counter/Timer Upper  
Register (CTUR) as its divisor.  
Each receiver and transmitter has a 16 byte FIFO. These FIFOs  
may be configured to operate at a fill capacity of either 8 or 16 bytes.  
This feature may be used if it is desired to operate the 28L91 in  
close compliance to 26C92 software. The 8-byte/16-byte mode is  
controlled by the MR0[3] bit. A 0 value for this bit sets the 8-bit mode  
( the default); a 1 sets the 16-byte mode.  
The FIFO fill interrupt level automatically follow the programming of  
the MR0[3] bit. See Tables 3 and 4.  
The counter/timer clock source and mode of operation (counter or  
timer) is selected by the Auxiliary Control Register bits 6 to 4  
(ACR[6:4]). The output of the counter/timer may be used for a baud  
rate and/or may be output to the OP pins for some external function  
that may be totally unrelated to data transmission. The counter/timer  
also sets the counter/timer ready bit in the Interrupt Status Register  
(ISR) when its output transitions from 1 to 0. A register read address  
(see Table 1) is reserved to issue a start counter/timer command  
and a second register read address is reserved to issue a stop  
command. The value of D[7:0] is ignored. The START command  
always loads the contents of CTUR, CTLR to the counting registers.  
The STOP command always resets the ISR[3] bit in the interrupt  
status register.  
68XXX mode  
When the I/M pin is connected to V (ground), the operation of the  
SS  
SC28L91 switches to the bus interface compatible with the Motorola  
bus interfaces. Several of the pins change their function as follows:  
IP6 becomes IACKN input  
RDN becomes DACKN  
WRN becomes R/WN  
The interrupt vector is enabled and the interrupt vector will be placed  
on the data bus when IACKN is asserted low. The interrupt vector  
register is located at address 0xC. The contents of this register are  
set to 0x0F on the application of RESETN.  
Timer Mode  
In the timer mode a symmetrical square wave is generated whose  
half period is equal in time to division of the selected counter/timer  
clock frequency by the 16-bit number loaded in the CTLR CTUR.  
Thus, the frequency of the counter/timer output will be equal to the  
counter/timer clock frequency divided by twice the value of the  
CTUR CTLR. While in the timer mode the ISR bit 3 (ISR[3]) will be  
set each time the counter/timer transitions from 1 to 0. (High to low)  
The generation of DACKN uses two positive edges of the X1 clock  
as the DACKN delay from the falling edge of CEN. If the CEN is  
withdrawn before two edges of the X1 clock occur, the  
generation of DACKN is terminated. Systems not strictly requiring  
DACKN may use the 68XXX mode with the bus timing of the 80XXX  
mode greatly decreasing the bus cycle time.  
16  
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Philips Semiconductors  
Product data sheet  
3.3 V or 5.0 V Universal Asynchronous  
Receiver/Transmitter (UART)  
SC28L91  
This continues regardless of issuance of the stop counter command.  
ISR[3] is reset by the stop counter command.  
ISR [3], and the interrupt. Invoking the ‘Set Timeout Mode On’  
command, CRx = 0xAn, will also clear the counter ready bit and stop  
the counter until the next character is received. The counter timer is  
controlled with six commands: Start/Stop C/T, Read/Write  
Counter/Timer lower register and Read/Write Counter/Timer upper  
register. These commands have slight differences depending on the  
mode of operation. Please see the detail of the commands under the  
CTLR CTUR Register descriptions.  
NOTE: Reading of the CTU and CTL registers in the timer mode is  
not meaningful. When the C/T is used to generate a baud rate and  
the C/T is selected through the CSR then the receiver and/or  
transmitter will be operating in the 16x mode. Calculation for the  
number ‘n’ to program the counter timer upper and lower registers is  
shown below.  
Time Out Mode Caution  
cńt clock rate  
When operating in the special time out mode it is possible to  
generate what appears to be a “false interrupt”, i.e. an interrupt  
without a cause. This may result when a time-out interrupt occurs  
and then, BEFORE the interrupt is serviced, another character is  
received, i.e., the data stream has started again. (The interrupt  
latency is longer than the pause in the data stream.) In this case,  
when a new character has been receiver, the counter/timer will be  
restarted by the receiver, thereby withdrawing its interrupt. If, at this  
time, the interrupt service begins for the previously seen interrupt, a  
read of the ISR will show the “Counter Ready” bit not set. If nothing  
else is interrupting, this read of the ISR will return a x’00 character.  
This action may present the appearance of a spurious interrupt.  
N +  
2 * 16 * Baud rate  
Often this division will result in a non-integer number; 26.3 for  
example. One can only program integer numbers to a digital divider.  
Therefore 26 would be chosen. This gives a baud rate error of  
0.3/26.3 which is 1.14%; well within the ability of the asynchronous  
mode of operation.  
Counter Mode  
In the counter mode the counter/timer counts the value of the CTLR  
CTUR down to zero and then sets the ISR[3] bit and sets the  
counter/timer output from 1 to 0. It then rolls over to 65,365 and  
continues counting with no further observable effect. Reading the  
C/T in the counter mode outputs the present state of the C/T. If the  
C/T is not stopped, a read of the C/T may result in changing data on  
the data bus.  
Communications  
The communications channel of the SC28L91 comprises a  
full-duplex asynchronous receiver/transmitter (UART). The operating  
frequency for the receiver and transmitter can be selected  
independently from the baud rate generator, the counter/timer, or  
from an external input. The transmitter accepts parallel data from the  
CPU, converts it to a serial bit stream, inserts the appropriate start,  
stop, and optional parity bits and outputs a composite serial stream  
of data on the TxD output pin. The receiver accepts serial data on  
the RxD pin, converts this serial input to parallel format, checks for  
start bit, stop bit, parity bit (if any), or break condition and sends an  
assembled character to the CPU via the receive FIFO. Three status  
bits (Break Received, Framing and Parity Errors) are also FIFOed  
with the data character.  
Timeout Mode  
The timeout mode uses the received data stream to control the  
counter. The time-out mode forces the C/T into the timer mode.  
Each time a received character is transferred from the shift register  
to the RxFIFO, the counter is restarted. If a new character is not  
received before the counter reaches zero count, the counter ready  
bit is set, and an interrupt can be generated. This mode can be used  
to indicate when data has been left in the Rx FIFO for more than the  
programmed time limit. If the receiver has been programmed to  
interrupt the CPU when the receive FIFO is full, and the message  
ends before the FIFO is full, the CPU will not be interrupted for the  
remaining characters in the RxFIFO.  
Input Port  
The inputs to this unlatched 7-bit (6-bit for 68xxx mode) port can be  
read by the CPU by performing a read operation at address 0xD. A  
High input results in a logic 1 while a Low input results in a logic 0.  
D7 will always read as a logic 1. The pins of this port can also serve  
as auxiliary inputs to certain portions of the UART logic, modem and  
DMA.  
By programming the C/T such that it would time out in just over one  
character time, the above situation could be avoided. The processor  
would be interrupted any time the data stream had stopped for more  
than one character time. NOTE: This is very similar to the watch dog  
timer of MR0. The difference is in the programmability of the delay  
timer and that this indicates that the data stream has stopped. The  
watchdog timer is more of an indicator that data is in the FIFO is not  
enough to cause an interrupt. The watchdog is restarted by either a  
receiver load to the RxFIFO or a system read from it.  
Four change-of-state detectors are provided which are associated  
with inputs IP3, IP2, IP1 and IP0. A High-to-Low or Low-to-High  
transition of these inputs, lasting longer than 25–50 µs, will set the  
corresponding bit in the input port change register. The bits are  
cleared when the register is read by the CPU. Any change-of-state  
can also be programmed to generate an interrupt to the CPU.  
This mode is enabled by writing the appropriate command to the  
command register. Writing an ‘0xAn’ to CR will invoke the timeout  
mode for that channel. Writing a ‘Cx’ to CR will disable the timeout  
mode. The timeout mode disables the regular START/STOP counter  
commands and puts the C/T into counter mode under the control of  
the received data stream. Each time a received character is  
transferred from the shift register to the RxFIFO, the C/T is stopped  
after one C/T clock, reloaded with the value in CTUR and CTLR and  
then restarted on the next C/T clock. If the C/T is allowed to end the  
count before a new character has been received, the counter ready  
Bit, ISR[3], will be set. If IMR[3] is set, this will generate an interrupt.  
Since receiving a character restarts the C/T, the receipt of a  
The input port change of state detection circuitry uses a 38.4 kHz  
sampling clock derived from one of the baud rate generator taps.  
This results in a sampling period of slightly more than 25 µs (this  
assumes that the clock input is 3.6864 MHz). The detection circuitry,  
in order to guarantee that a true change in level has occurred,  
requires two successive samples at the new logic level be observed.  
As a consequence, the minimum duration of the signal change is  
25 µs if the transition occurs “coincident with the first sample pulse”.  
The 50 µs time refers to the situation in which the change-of-state is  
character after the C/T has timed out will clear the counter ready bit,  
17  
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Philips Semiconductors  
Product data sheet  
3.3 V or 5.0 V Universal Asynchronous  
Receiver/Transmitter (UART)  
SC28L91  
“just missed” and the first change-of-state is not detected until 25 µs  
If CTS option is enabled (MR2[4] = 1), the CTS input at IP0 or IP1  
must be Low in order for the character to be transmitted. The  
transmitter will check the state of the CTS input at the beginning of  
the character transmitted. If it is found to be High, the transmitter will  
delay the transmission of any following characters until the CTS has  
returned to the low state. CTS going high during the serialization of  
a character will not affect that character.  
later.  
Output Port  
The output ports are controlled from six places: the OPCR, OPR,  
MR, Command, SOPR and ROPR registers. The OPCR register  
controls the source of the data for the output ports OP2 through  
OP7. The data source for output ports OP0 and OP1 is controlled by  
the MR and CR registers. When the OPR is the source of the data  
for the output ports, the data at the ports is inverted from that in the  
OPR register. The content of the OPR register is controlled by the  
“Set Output Port Bits Command” and the “Reset Output Bits  
Command”. These commands are at E and F, respectively. When  
these commands are used, action takes place only at the bit  
locations where ones exist. For example, a one in bit location 5 of  
the data word used with the “Set Output Port bits” command will  
result in OPR[5] being set to one. The OP5 would then be set to  
The transmitter can also control the RTSN outputs, OP0 or OP1 via  
MR2[5]. When this mode of operation is set, the meaning of the OP0  
or OP1 signals will usually be ‘end of message’. See description of  
the MR2[5] bit for more detail. This feature may be used to  
automatically “turn around” a transceiver in simplex systems.  
Receiver  
The SC28L91 is conditioned to receive data when enabled through  
the command register. The receiver looks for a High-to-Low  
(mark-to-space) transition of the start bit on the RxD input pin. If a  
transition is detected, the state of the RxD pin is sampled the 16X  
clock for 7–1/2 clocks (16X clock mode) or at the next rising edge of  
the bit time clock (1X clock mode). If RxD is sampled high, the start  
bit is invalid and the search for a valid start bit begins again. If RxD  
is still Low, a valid start bit is assumed and the receiver continues to  
sample the input at one-bit time intervals at the theoretical center of  
the bit. When the proper number of data bits and parity bit (if any)  
have been assembled, and one/half stop bit has been detected the  
byte is loaded to the RxFIFO. The least significant bit is received  
first. The data is then transferred to the Receive FIFO and the  
RxRDY bit in the SR is set to a 1. This condition can be  
programmed to generate an interrupt at OP4 or OP5 and INTRN. If  
the character length is less than 8 bits, the most significant unused  
bits in the RxFIFO are set to zero.  
zero (V ). Similarly, a one in bit position 5 of the data word  
SS  
associated with the “Reset Output Ports Bits” command would set  
OPR[5] to zero and, hence, the pin OP5 to a one (V ).  
DD  
These pins along with the IP pins and their change of state detectors  
are often used for modem and DMA control.  
OPERATION  
Transmitter  
The SC28L91 is conditioned to transmit data when the transmitter is  
enabled through the command register. The SC28L91 indicates to  
the CPU that it is ready to accept a character by setting the TxRDY  
bit in the status register. This condition can be programmed to  
generate an interrupt request at OP6 or OP7 and INTRN. When the  
transmitter is initially enabled the TxRDY and TxEMPT bits will be  
set in the status register. When a character is loaded to the transmit  
FIFO the TxEMPT bit will be reset. The TxEMPT will not set until: 1)  
the transmit FIFO is empty and the transmit shift register has  
finished transmitting the stop bit of the last character written to the  
transmit FIFO, or 2) the transmitter is disabled and then re-enabled.  
The TxRDY bit is set whenever the transmitter is enabled and the  
TxFIFO is not full. Data is transferred from the holding register to  
transmit shift register when it is idle or has completed transmission  
of the previous character. Characters cannot be loaded into the  
TxFIFO while the transmitter is disabled.  
After the stop bit is detected, the receiver will immediately look for  
the next start bit. However if a framing error occurs (a non-zero  
character was received without a stop bit) and then RxD remains  
low one/half bit time the receiver operates as if a new start bit was  
detected. It then continues to assemble the next character.  
The parity error, framing error, and overrun error (if any) are strobed  
into the SR from the next byte to be read from the Rx FIFO.  
If a break condition is detected (RxD is Low for the entire character  
including the stop bit), a character consisting of all zeros will be  
loaded into the RxFIFO and the received break bit in the SR is set to  
1. The RxD input must return to high for two (2) clock edges of the  
X1 crystal clock for the receiver to recognize the end of the break  
condition and begin the search for a start bit.  
The transmitter converts the parallel data from the CPU to a serial  
bit stream on the TxD output pin. It automatically sends a start bit  
followed by the programmed number of data bits, an optional parity  
bit, and the programmed number of stop bits. The least significant  
bit is sent first. Following the transmission of the stop bits, if a new  
character is not available in the TxFIFO, the TxD output remains  
High and the TxEMT bit in the Status Register (SR) will be set to 1.  
Transmission resumes and the TxEMT bit is cleared when the CPU  
loads a new character into the TxFIFO.  
This will usually require a high time of one X1 clock period or 3 X1  
edges since the clock of the controller is not synchronous to the X1  
clock.  
Transmitter Reset and Disable  
Note the difference between transmitter disable and reset. A  
transmitter reset stops transmitter action immediately, clears the  
transmitter FIFO and returns the idle state. A transmitter disable  
withdraws the transmitter interrupts but allows the transmitter to  
continue operation until all bytes in its FIFO and shift register have  
been transmitted including the final stop bits. It then returns to its  
idle state.  
If the transmitter is disabled it continues operating until the character  
currently being transmitted and any characters in the TxFIFO,  
including parity and stop bits, have been transmitted. New data  
cannot be loaded to the TxFIFO when the transmitter is disabled.  
When the transmitter is reset it stops sending data immediately.  
Receiver FIFO  
The transmitter can be forced to send a break (a continuous low  
condition) by issuing a START BREAK command via the CR  
register. The break is terminated by a STOP BREAK command or a  
transmitter reset.  
The RxFIFO consists of a First-In-First-Out (FIFO) stack with a  
capacity of 8 or 16 characters. Data is loaded from the receive shift  
register into the topmost empty position of the FIFO. The RxRDY bit  
18  
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Philips Semiconductors  
Product data sheet  
3.3 V or 5.0 V Universal Asynchronous  
Receiver/Transmitter (UART)  
SC28L91  
in the status register is set whenever one or more characters are  
available to be read, and a FFULL status bit is set if all 8 or 16 stack  
positions are filled with data. Either of these bits can be selected to  
cause an interrupt. A read of the RxFIFO outputs the data at the top  
of the FIFO. After the read cycle, the data FIFO and its associated  
status bits (see below) are ‘popped’ thus emptying a FIFO position  
for new data.  
read. This situation may occur at the end of a transmission when the  
last few characters received are not sufficient to cause an interrupt.  
This counter times out after 64 bit times. It is reset each time a  
character is transferred from the receiver shift register to the  
RxFIFO or a read of the RxFIFO is executed.  
Receiver Time-out Mode  
In addition to the watch dog timer described in the receiver section,  
the counter/timer may be used for a similar function. Its 16-bit  
programmability allows much greater precision of time out intervals.  
A disabled receiver with data in its FIFO may generate an interrupt  
(see “Receiver Status Bits”, below). Its status bits remain active and  
its watchdog, if enabled, will continue to operate.  
The time-out mode uses the received data stream to control the  
counter. Each time a received character is transferred from the shift  
register to the RxFIFO, the counter is restarted. If a new character is  
not received before the counter reaches zero count, the counter  
ready bit is set, and an interrupt can be generated. This mode can  
be used to indicate when data has been left in the RxFIFO for more  
than the programmed time limit. Otherwise, if the receiver has been  
programmed to interrupt the CPU when the receive FIFO is full, and  
the message ends before the FIFO is full, the CPU may not know  
there is data left in the FIFO. The CTU and CTL value would be  
programmed for just over one character time, so that the CPU would  
be interrupted as soon as it has stopped receiving continuous data.  
This mode can also be used to indicate when the serial line has  
been marking for longer than the programmed time limit. In this  
case, the CPU has read all of the characters from the FIFO, but the  
last character received has started the count. If there is no new data  
during the programmed time interval, the counter ready bit will get  
set, and an interrupt can be generated.  
Receiver Status Bits  
In addition to the data word, three status bits (parity error, framing  
error, and received break) are also appended to the data character  
in the FIFO. The overrun error, MR1[5], and the change of break  
(ISR[2]) are not FIFOed.  
The status of the Rx FIFO may be provided in two ways, as  
programmed by the error mode control bit in the mode register  
(MR1[5]). In the ‘character’ mode, status is provided on a  
character-by-character basis; the status applies only to the  
character at the top of the FIFO. In the ‘block’ mode, the status  
provided in the SR for these three bits is the logical-OR of the status  
for all characters coming to the top of the FIFO since the last ‘reset  
error’ from the command register was issued. In either mode  
reading the SR does not affect the FIFO. The FIFO is ‘popped’ only  
when the RxFIFO is read. Therefore the status register should be  
read prior to reading the FIFO.  
If the FIFO is full when a new character is received, that character is  
held in the receive shift register until a FIFO position is available. If  
an additional character is received while this state exits, the  
contents of the FIFO are not affected; the character previously in the  
shift register is lost and the overrun error status bit (SR[4]) will be  
set-upon receipt of the start bit of the new (overrunning) character.  
The time-out mode is enabled by writing the appropriate command  
to the command register. Writing an 0xAn to CR will invoke the  
time-out mode for that channel. Writing a ‘Cx’ to CR will disable the  
time-out mode. The time-out mode should only be used by one  
channel at once, since it uses the C/T. CTU and CTL must be  
loaded with a value greater than the normal receive character  
period. The time-out mode disables the regular START/STOP  
Counter commands and puts the C/T into counter mode under the  
control of the received data stream. Each time a received character  
is transferred from the shift register to the RxFIFO, the C/T is  
stopped after 1 C/T clock, reloaded with the value in CTU and CTL  
and then restarted on the next C/T clock. If the C/T is allowed to end  
the count before a new character has been received, the counter  
ready bit, ISR[3], will be set. If IMR[3] is set, this will generate an  
interrupt. Receiving a character after the C/T has timed out will clear  
the counter ready bit, ISR[3], and the interrupt. Invoking the ‘Set  
Time-out Mode On’ command, CRx = ‘Ax’, will also clear the counter  
ready bit and stop the counter until the next character is received.  
The receiver can control the deactivation of RTS. If programmed to  
operate in this mode, the RTSN output will be negated when a valid  
start bit was received and the FIFO is full. When a FIFO position  
becomes available, the RTSN output will be re-asserted (set low)  
automatically. This feature can be used to prevent an overrun, in the  
receiver, by connecting the RTSN output to the CTSN input of the  
transmitting device.  
If the receiver is disabled, the FIFO characters can be read.  
However, no additional characters can be received until the receiver  
is enabled again. If the receiver is reset, the FIFO and all of the  
receiver status, and the corresponding output ports and interrupt are  
reset. No additional characters can be received until the receiver is  
enabled again.  
Watchdog and Time Out Mode Differences  
The watchdog timer is restarted each time a character is read from  
or written to the Rx FIFO. It is an indicator that data is in the FIFO  
that has not been read. If the Rx FIFO is empty no action occurs. In  
the time out mode the C/T is stopped and restarted each time a  
character is written to the Rx FIFO. From this point of view the time  
out of the C/T is an indication that the data stream has stopped.  
After the time out mode is invoked the timer will not start until the  
first character is written to the Rx FIFO.  
Receiver Reset and Disable  
Receiver disable stops the receiver immediately—data being  
assembled in the receiver shift register is lost. Data and status in the  
FIFO is preserved and may be read. A re-enable of the receiver  
after a disable will cause the receiver to begin assembling  
characters at the next start bit detected.  
A receiver reset will discard the present shift register date, reset the  
receiver ready bit (RxRDY), clear the status of the byte at the top of  
the FIFO and re-align the FIFO read/write pointers.  
Time Out Mode Caution  
When operating in the special time out mode, it is possible to  
generate what appears to be a “false interrupt”, i.e. an interrupt  
without a cause. This may result when a time-out interrupt occurs  
and then, BEFORE the interrupt is serviced, another character is  
received, i.e., the data stream has started again. (The interrupt  
Watchdog  
A ‘watchdog timer’ is associated with the receiver. Its interrupt is  
enabled by MR0[7]. The purpose of this timer is to alert the control  
processor that characters are in the RxFIFO which have not been  
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Philips Semiconductors  
Product data sheet  
3.3 V or 5.0 V Universal Asynchronous  
Receiver/Transmitter (UART)  
SC28L91  
latency is longer than the pause in the data stream.) In this case,  
when a new character has been received, the counter/timer will be  
restarted by the receiver, thereby withdrawing its interrupt. If, at this  
time, the interrupt service begins for the previously seen interrupt, a  
read of the ISR will show the “Counter Ready” bit not set. If nothing  
else is interrupting, this read of the ISR will return a x’00 character.  
character if the received A/D bit is a zero (data tag). If enabled, all  
received characters are transferred to the CPU via the RxFIFO. In  
either case, the data bits are loaded into the data FIFO while the  
A/D bit is loaded into the status FIFO position normally used for  
parity error (SR[5] ). Framing error, overrun error, and break detect  
operate normally whether or not the receiver is enabled.  
Multi-drop Mode (9-bit or Wake-Up)  
The UART is equipped with a wake up mode for multi-drop  
applications. This mode is selected by programming bits MR1[4:3]or  
to ‘11’. In this mode of operation, a ‘master’ station transmits an  
address character followed by data characters for the addressed  
‘slave’ station. The slave station(s) whose receiver(s) that are  
normally disabled, examine the received data stream and ‘wakeup’  
the CPU (by setting RxRDY) only upon receipt of an address  
character. The CPU compares the received address to its station  
address and enables the receiver if it wishes to receive the  
subsequent data characters. Upon receipt of another address  
character, the CPU may disable the receiver to initiate the process  
again.  
PROGRAMMING  
The operation of the UART is programmed by writing control words  
into the appropriate registers. Operational feedback is provided via  
status registers which can be read by the CPU. The addressing of  
the registers is described in Table 1.  
The contents of certain control registers are initialized to zero on  
RESET. Care should be exercised if the contents of a register are  
changed during operation, since certain changes may cause  
operational problems.  
For example, changing the number of bits per character while the  
transmitter is active may cause the transmission of an incorrect  
character. In general, the contents of the MR, the CSR, and the  
OPCR should only be changed while the receiver(s) and  
transmitter(s) are not enabled, and certain changes to the ACR  
should only be made while the C/T is stopped.  
A transmitted character consists of a start bit, the programmed  
number of data bits, and Address/Data (A/D) bit, and the  
programmed number of stop bits. The polarity of the transmitted A/D  
bit is selected by the CPU by programming bit MR1[2]. MR1[2]= 0  
transmits a zero in the A/D bit position, which identifies the  
corresponding data bits as data. MR1[2] = 1 transmits a one in the  
A/D bit position, which identifies the corresponding data bits as an  
address. The CPU should program the mode register prior to  
loading the corresponding data bits into the TxFIFO.  
The channel has 3 mode registers (MR0, 1, 2) which control the  
basic configuration of the channel. Access to these registers is  
controlled by independent MR address pointers. These pointers are  
set to 0 or 1 by MR control commands in the command register  
“Miscellaneous Commands”. Each time the MR registers are  
accessed the MR pointer increments, stopping at MR2. It remains  
pointing to MR2 until set to 0 or 1 via the miscellaneous commands  
of the command register. The pointer is set to 1 on reset for  
compatibility with previous Philips Semiconductors UART software.  
MR1[2] = 1 transmits a one in the A/D bit position, which identifies  
the corresponding data bits as an address. The CPU should  
program the mode register prior to loading the corresponding data  
bits into the TxFIFO.  
Refer to Table 2 for register bit descriptions. The reserved registers  
at addresses 0x02 and 0x0A should never be read during normal  
operation since they are reserved for internal diagnostics.  
In this mode, the receiver continuously looks at the received data  
stream, whether it is enabled or disabled. If disabled, it sets the  
RxRDY status bit and loads the character into the RxFIFO if the  
received A/D bit is a one (address tag), but discards the received  
Table 1. SC28L91 register addressing  
Address Bits  
A[3:0]  
READ (RDN = 0)  
WRITE (WRN = 0)  
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
0
1
1
0
1
0
1
0
1
0
1
0
0
1
0
1
Mode Register(MR0, MR1, MR2)  
Status Register(SR)  
Mode Register(MR0, MR1, MR2)  
Clock Select Register(CSR)  
Command Register(CR)  
Reserved  
Rx Holding Register(RxFIFO)  
Input Port Change Register (IPCR)  
Interrupt Status Register (ISR)  
Counter/Timer Upper (CTU)  
Counter/Timer Lower (CTL)  
Tx Holding Register(RxFIFO)  
Aux. Control Register (ACR)  
Interrupt Mask Register (IMR)  
C/T Upper Preset Register (CTPU)  
C/T Lower Preset Register (CTPL)  
Interrupt vector (68K mode), Misc. register in Intel mode  
IVR Motorola mode, Misc. register (Intel mode)  
Input Port (IPR)  
Interrupt vector (68K mode), Misc. register in Intel mode  
IVR Motorola mode, Misc. register (Intel mode)  
Output Port Configuration Register (OPCR)  
Set Output Port Bits Command (SOPR)  
Start Counter Command  
Stop Counter Command  
Reset output Port Bits Command (ROPR)  
NOTE:  
1. The three MR registers are accessed via the MR Pointer and Commands 0x1n and 0xBn (where n = represents receiver and transmitter enable bits)  
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Philips Semiconductors  
Product data sheet  
3.3 V or 5.0 V Universal Asynchronous  
Receiver/Transmitter (UART)  
SC28L91  
Register Acronyms and Read / Write Capability  
(R/W = Read/Write, R = Read only, W = Write only)  
Interrupt Mask Register  
Counter Timer Upper Value  
Counter Timer Lower Value  
Counter Timer Preset Upper  
Counter Timer Preset Lower  
Input Port Register  
Output Configuration Register  
Set Output Port  
Reset Output Port  
IMR  
CTU  
CTL  
CTPU  
CTPL  
IPR  
OPCR  
Bits  
W
R
R
W
W
R
W
W
W
R/W  
Mode Register  
Status Register  
MRn  
SR  
R/W  
R
W
W
R
W
R
W
R
Clock Select  
Command Register  
Receiver FIFO  
CSR  
CR  
RxFIFO  
RxFIFO  
IPCR  
ACR  
ISR  
Transmitter FIFO  
Input Port Change Register  
Auxiliary Control Register  
Interrupt Status Register  
Bits  
IVR/GP  
Interrupt vector or GP register  
Table 2. Condensed Register bit formats  
Adr Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
TEST 2  
Bit 0  
Name  
MR0  
0
WATCH  
RxINT BIT 2  
TxINT [1:0]  
FIFO SIZE  
BAUD RATE  
EXTENDED  
II  
BAUD RATE  
EXTENDED 1  
DOG  
MR1  
MR2  
0
0
RxRTS  
Control  
RxINT BIT 1  
Error Mode  
Parity Mode  
Parity Type  
Bits per Character  
Channel Mode  
TxRTS  
Control  
CTSN Enable Stop Bit Length  
Tx  
CSR  
SR  
1
1
Receiver Clock, Select Code  
Transmitter Clock select code,  
Received  
Break  
Framing  
Error  
Parity Error  
Overrun Error TxEMT  
TxRDY  
RxFULL  
RxRDY  
CR  
2
3
3
4
4
5
Channel Command codes  
Read 8 bits from Rx FIFO  
Write 8 bits to Tx FIFO  
Disable Tx  
Enable Tx  
Disable Rx  
Enable Rx  
RxFIFO  
TxFIFO  
IPCR  
ACR  
Delta IP3  
Delta IP2  
Delta IP1  
Delta IP0  
State of IP3  
Enable IP3  
State of IP2  
Enable IP2  
State of IP1  
Enable IP1  
RxRDY  
State of IP0  
Enable IP0  
TxRDY  
Baud Group Counter Timer mode and clock select  
ISR  
Change  
Ignore in ISR Reads  
Counter  
Ready  
Change  
Break  
Input Port  
IMR  
5
Change  
Input Port  
Set to 0  
Set to 0  
Set to 0  
Counter  
Ready  
Change  
Break  
RxRDY  
TxRDY  
CTU  
6
6
7
7
D
D
Read 8 MSb of the BRG Timer divisor.  
Write 8 MSb of the BRG Timer divisor.  
Read 8 LSb of the BRG Timer divisor.  
Write 8 LSb of the BRG Timer divisor.  
CTPU  
CTL  
CTPL  
IPR  
State of IP  
State of IP 6  
State of IP 5  
State of IP 4  
State of IP 3  
State of IP 2  
State of IP1  
State of IP 0  
OPCR  
Configure  
OP7  
Configure  
OP6  
Configure  
OP5  
Configure  
OP4  
Configure OP3  
Configure OP2  
Strt C/T  
SOPR  
E
E
F
F
Read Address E to start Counter Timer  
Set OP 7 Set OP 6 Set OP 5  
Read Address F to stop counter Timer  
Reset OP 7 Reset OP 6 Reset OP 5  
Set OP 4  
Set OP 3  
Set OP 2  
Set OP 1  
Set OP 0  
Stp C/T  
ROPR  
Reset OP 4  
Reset OP 3  
Reset OP 2  
Reset OP 1  
Reset OP 0  
21  
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Philips Semiconductors  
Product data sheet  
3.3 V or 5.0 V Universal Asynchronous  
Receiver/Transmitter (UART)  
SC28L91  
REGISTER DESCRIPTIONS MODE REGISTERS  
MR0 – Mode Register 0  
Mode Register 0. MR0 is accessed by setting the MR pointer to 0 via the command register command B.  
Addr  
MR0  
Bit 7  
Rx  
WATCHDOG  
BIT 6  
RxINT BIT 2  
BITS 5:4  
TxINT (1:0)  
BIT 3  
FIFO SIZE  
BIT 2  
BAUD RATE  
EXTENDED II  
BIT 1  
TEST 2  
BIT 0  
BAUD RATE  
EXTENDED 1  
0x00  
0x08  
0 = Disable  
1 = Enable  
See Tables in  
MR0 descrip-  
tion  
See Table 4  
0 = 8 byte FIFO  
1 = 16 byte FIFO  
0 = Normal  
1 = Extend II  
Set to 0  
0 = Normal  
1 = Extend  
MR0[7]—Watchdog Control  
MR0[5:4]—Tx interrupt fill level.  
This bit controls the receiver watchdog timer. 0 = disable,  
1 = enable. When enabled, the watch dog timer will generate a  
receiver interrupt if the receiver FIFO has not been accessed within  
64 bit times of the receiver 1X clock. This is used to alert the control  
processor that data is in the RxFIFO that has not been read. This  
situation may occur when the byte count of the last part of a  
message is not large enough to generate an interrupt.  
Table 4. Transmitter FIFO  
Interrupt fill level MR0(3) = 0 (8 bytes)  
MR0[5:4]  
Interrupt Condition  
00  
01  
10  
11  
8 bytes empty (Tx EMPTY)  
4 or more bytes empty  
6 or more bytes empty  
MR0[6]—Rx Interrupt bit 2  
Bit 2 of receiver FIFO interrupt level. This bit along with Bit 6 of MR1  
sets the fill level of the FIFO that generates the receiver interrupt.  
1 or more bytes empty (Tx RDY)  
Table 4a. Transmitter FIFO  
MR0[6], MR1[6] Rx Interrupt bits  
Interrupt fill level MR0(3) = 1 (16 bytes)  
Note that this control is split between MR0 and MR1. This is for  
backward compatibility to legacy software of the SC2692 and  
SCN2681 dual UART devices.  
MR0[5:4]  
Interrupt Condition  
00  
01  
10  
11  
16 bytes empty (Tx EMPTY)  
8 or more bytes empty  
Table 3. Receiver FIFO  
Interrupt fill level (MR0(3) = 0 (8 bytes)  
12 or more bytes empty  
1 or more bytes empty (Tx RDY)  
MR0[6] MR1[6]  
Interrupt Condition  
00  
01  
10  
11  
1 or more bytes in FIFO (Rx RDY)  
6 or more bytes in FIFO  
4 or more bytes in FIFO  
8 bytes in FIFO (Rx FULL)  
For the transmitter these bits control the number of FIFO positions  
empty when the transmitter will attempt to interrupt. After the reset  
the transmit FIFO has 8 bytes empty. It will then attempt to interrupt  
as soon as the transmitter is enabled. The default setting of the MR0  
bits [5:4] condition the transmitter to attempt to interrupt only when it  
is completely empty. As soon as one–byte is loaded, it is no longer  
empty and hence will withdraw its interrupt request.  
Table 3a. Receiver FIFO  
Interrupt fill level(MR0(3)=1 (16 bytes)  
MR0[6] MR1[6]  
Interrupt Condition  
MR0[3]—FIFO size  
Selects the FIFO depth at 8 or 16 bytes. See Tables 3 and 4  
00  
01  
10  
11  
1 or more bytes in FIFO (Rx RDY)  
8 or more bytes in FIFO  
MR0[2:0]—Baud Rate Group Selection  
These bits are used to select one of the six–baud rate groups.  
12 or more bytes in FIFO  
16 bytes in FIFO (Rx FULL)  
See Table 5 for the group organization.  
000 Normal mode  
001 Extended mode I  
100 Extended mode II  
For the receiver these bits control the number of FIFO positions  
filled when the receiver will attempt to interrupt. After the reset the  
receiver FIFO is empty. The default setting of these bits cause the  
receiver to attempt to interrupt when it has one or more bytes in it.  
Other combinations of MR2[2:0] should not be used.  
22  
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Philips Semiconductors  
Product data sheet  
3.3 V or 5.0 V Universal Asynchronous  
Receiver/Transmitter (UART)  
SC28L91  
MR1 – Mode Register 1  
Addr  
MR1  
BIT 7  
BIT 6  
BIT 5  
BIT 4  
BIT 3  
BIT 2  
BIT 1  
BITS PER  
BIT 0  
Rx CONTROLS  
RTS  
RxINT  
BIT 1  
ERROR  
MODE  
PARITY MODE  
PARITY TYPE  
CHARACTER  
0x00  
0 = No  
1 = Yes  
0 = RxRDY  
1 = FFULL  
0 = Char  
1 = Block  
00 = With Parity  
01 = Force Parity  
10 = No Parity  
0 = Even  
1 = Odd  
00 = 5  
01 = 6  
10 = 7  
11 = 8  
11 = Multi-drop Mode  
NOTE:  
In block error mode, block error conditions must be cleared by using the error reset command (command 4x) or a receiver reset.  
MR1 is accessed when the MR pointer points to MR1. The pointer is  
set to MR1 by RESET or by a ‘set pointer’ command applied via CR  
command 0x10. After reading or writing MR1, the pointer will point to  
MR2 and will not move from MR2 on subsequent MR reads or  
writes.  
provided on a character-by-character basis; the status applies only  
to the character at the top of the FIFO. In the ‘block’ mode, the  
status provided in the SR for these bits is the accumulation  
(logical-OR) of the status for all characters coming to the top of the  
FIFO since the last ‘reset error’ command was issued.  
MR1[7]— Receiver Request–to–Send Control (Flow Control)  
This bit controls the deactivation of the RTSN output (OP0) by the  
receiver. This output is normally asserted by setting OPR[0] and  
negated by resetting OPR[0]. Proper automatic operation of flow  
control requires OPR[0] to be set to logical 1.  
MR1[4:3|— Parity Mode Select  
If ‘with parity’ or ‘force parity’ is selected a parity bit is added to the  
transmitted character and the receiver performs a parity check on  
incoming data MR1[4:3] = 11 selects operation in the special  
multi–drop mode described in the Operation section.  
MR1[7] = 1 causes RTSN to be negated (OP0 is driven to a ‘1’  
[V ]) upon receipt of a valid start bit if the FIFO is full. This is the  
CC  
MR1[2]— Parity Type Select  
This bit selects the parity type (odd or even) if the ‘with parity’ mode  
is programmed by MR1[4:3], and the polarity of the forced parity bit  
if the ‘force parity’ mode is programmed. It has no effect if the ‘no  
parity’ mode is programmed. In the special multi-drop mode it  
selects the polarity of the A/D bit.  
beginning of the reception of the ninth byte. If the FIFO is not read  
before the start of the tenth or 17th byte, an overrun condition will  
occur and the tenth or 17th or 17th byte will be lost. However, the bit  
in OPR[0] is not reset and RTSN will be asserted again when an  
empty FIFO position is available. This feature can be used for flow  
control to prevent overrun in the receiver by using the RTSN output  
signal to control the CTSN input of the transmitting device.  
MR1[1:0]— Bits Per Character Select  
This field selects the number of data bits per character to be  
transmitted and received. The character length does not include the  
start, parity, and stop bits.  
MR1[6]—Rx Interrupt Bit 1  
Bit 1 of the receiver interrupt control. See description under MR0[6].  
MR1[5]— Error Mode Select  
This bit selects the operating mode of the three FIFOed status bits  
(FE, PE, and received break) for. In the ‘character’ mode, status is  
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Philips Semiconductors  
Product data sheet  
3.3 V or 5.0 V Universal Asynchronous  
Receiver/Transmitter (UART)  
SC28L91  
MR2 – Mode Register 2  
MR2 is accessed when the MR pointer points to MR2, which occurs after any access to MR1. Accesses to MR2 do not change the pointer.  
ADDR  
MR  
BIT 7  
BIT 6  
BIT 5  
BIT 4  
BIT 3  
BIT 2  
BIT 1  
BIT 0  
CHANNEL MODE  
Tx CONTROLS  
RTS  
CTS  
ENABLE Tx  
STOP BIT LENGTH  
NOTE: Add 0.5 to binary codes 0–7 for 5 bit character lengths.  
0x00  
00 = Normal  
0 = 0.563  
1 = 0.625  
2 = 0.688  
3 = 0.750  
4 = 0.813  
5 = 0.875  
6 = 0.938  
7 = 1.000  
8 = 1.563  
9 = 1.625  
A = 1.688  
B = 1.750  
C = 1.813  
D = 1.875  
E = 1.938  
F = 2.000  
01 = Auto-Echo  
10 = Local loop  
11 = Remote loop  
0 = No  
0 = No  
1 = Yes  
1 = Yes  
NOTE:  
Add 0.5 to values shown for 0–7 if channel is programmed for 5 bits/char.  
MR2[7:6]— Mode Select  
4. The received parity is not checked and is not regenerated for  
transmission, i.e., transmitted parity is as received.  
The channel of the UART can operate in one of four modes.  
MR2[7:6] = 00 is the normal mode, with the transmitter and receiver  
operating independently.  
5. The receiver must be enabled.  
6. Character framing is not checked, and the stop bits are  
retransmitted as received.  
MR2[7:6] = 01 places the channel in the automatic echo mode,  
which automatically retransmits the received data. The following  
conditions are true while in automatic echo mode:  
7. A received break is echoed as received until the next valid start  
bit is detected.  
1. Received data is reclocked and retransmitted on the TxD output.  
2. The receive clock is used for the transmitter.  
The user must exercise care when switching into and out of the  
various modes. The selected mode will be activated immediately  
upon mode selection, even if this occurs in the middle of a received  
or transmitted character. Likewise, if a mode is deselected the  
device will switch out of the mode immediately.  
3. The receiver must be enabled, but the transmitter needs not be  
enabled.  
4. The TxRDY and TxEMT status bits are inactive.  
5. The received parity is checked, but is not regenerated for  
transmission, i.e. transmitted parity bit is as received.  
An exception to this occurs when switching out of auto echo or  
remote loop back modes. If the de-selection occurs just after the  
receiver has sampled the stop bit (indicated in auto echo by  
assertion of RxRDY) and the transmitter is enabled, then the  
transmitter will remain in auto echo mode until the stop bit(s) have  
been re-transmitted.  
6. Character framing is checked, but the stop bits are retransmitted  
as received.  
7. A received break is echoed as received until the next valid start  
bit is detected.  
In most situations the above is rendered transparent by other  
system considerations. However recall that the stop bit sequence  
may be very long compared to bus cycles. If rapid reconfiguration of  
the transmitter is desired in the above conditions the controlling  
system should wait for the TxEMT bit to set or issue a Tx software  
reset before reconfiguration begins.  
8. CPU to receiver communication continues normally, but the CPU  
to transmitter link is disabled.  
MR2[7:6] = 10 selects local loop back diagnostic mode. In this  
mode:  
1. The transmitter output is internally connected to the receiver  
input.  
MR2[5]— Transmitter Request–to–Send Control  
This bit controls the deactivation of the RTSN output (OP0) by the  
transmitter. This output is normally asserted by setting OPR[0] and  
negated by resetting OPR[0]. MR2[5] = 1 caused OPR[0] to be  
reset automatically one bit time after the characters in the transmit  
shift register and in the TxFIFO, if any, are completely transmitted  
including the programmed number of stop bits, if the transmitter is  
not enabled.  
2. The transmit clock is used for the receiver.  
3. The TxD output is held High.  
4. The RxD input is ignored.  
5. The transmitter must be enabled, but the receiver need not be  
enabled.  
6. CPU to transmitter and receiver communications continue  
normally.  
This feature can be used to automatically terminate the transmission  
of a message as follows (“line turnaround”):  
1. Program auto–reset mode: MR2[5] = 1.  
MR2[7:6] = 11 selects remote loop back diagnostic mode. In this  
2. Enable transmitter.  
3. Asset RTSN: OPR[0] = 1.  
4. Send message.  
mode:  
1. Received data is reclocked and retransmitted on the TxD  
out–put.  
2. The receive clock is used for the transmitter.  
5. Disable transmitter after the last character is loaded into the  
TxFIFO.  
3. Received data is not sent to the local CPU, and the error status  
conditions are inactive.  
24  
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Philips Semiconductors  
Product data sheet  
3.3 V or 5.0 V Universal Asynchronous  
Receiver/Transmitter (UART)  
SC28L91  
6. The last character will be transmitted and OPR[0] will be reset  
one bit time after the last stop bit, causing RTSN to be negated.  
MR2[3:0]— Stop Bit Length Select  
This field programs the length of the stop bit appended to the  
transmitted character. Stop bit lengths of 9/16 to 1 and 1–9/16 to 2  
bits, in increments of 1/16 bit, can be programmed for character  
lengths of 6, 7, and 8 bits. For a character lengths of 5 bits, 1–1/16  
to 2 stop bits can be programmed in increments of 1/16 bit. In all  
cases, the receiver only checks for a ‘mark’ condition at the center  
of the stop bit position (one half-bit time after the last data bit, or  
after the parity bit if enabled is sampled).  
MR2[4]— Clear-to-Send Control  
If this bit is 0, CTSN has no effect on the transmitter. If this bit is a 1,  
the transmitter checks the state of CTSN (IP0) the time it is ready to  
send a character. If IP0 is asserted (Low), the character is  
transmitted. If it is negated (High), the TxD output remains in the  
marking state and the transmission is delayed until CTSN goes low.  
Changes in CTSN while a character is being transmitted do not  
affect the transmission of that character..  
If an external 1X clock is used for the transmitter, then MR2[3] = 0  
selects one stop bit and MR2[3] = 1 selects two stop bits to be  
transmitted.  
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Philips Semiconductors  
Product data sheet  
3.3 V or 5.0 V Universal Asynchronous  
Receiver/Transmitter (UART)  
SC28L91  
CSR CLOCK SELECT REGISTER  
Addr  
CSR  
0x01  
CSR (7:4)  
CSR (3:0)  
RECEIVER CLOCK SELECT  
See Text and table 5  
TRANSMITTER CLOCK SELECT  
See Text and table 5  
Table 5. Baud rate (base on a 3.6864MHz crystal clock)  
MR0[0] = 0 (Normal Mode)  
MR0[0] = 1 (Extended Mode I)  
MR0[2] = 1 (Extended Mode II)  
CSRA[7:4]  
0000  
0001  
0010  
0011  
ACR[7] = 0  
50  
ACR[7] = 1  
75  
ACR[7] = 0  
300  
ACR[7] = 1  
450  
ACR[7] = 0  
4,800  
ACR[7] = 1  
7,200  
110  
110  
110  
110  
880  
880  
134.5  
200  
134.5  
150  
134.5  
1200  
134.5  
900  
1,076  
1,076  
19.2K  
28.8K  
57.6K  
115.2K  
1,050  
14.4K  
28.8K  
57.6K  
115.2K  
2,000  
0100  
0101  
0110  
300  
300  
1800  
1800  
600  
600  
3600  
3600  
1,200  
1,050  
2,400  
4,800  
7,200  
9,600  
38.4K  
Timer  
IP4–16X  
IP4–1X  
1,200  
2,000  
2,400  
4,800  
1,800  
9,600  
19.2K  
Timer  
IP4–16X  
IP4–1X  
7200  
7,200  
2,000  
14.4K  
28.8K  
1,800  
57.6K  
115.2K  
Timer  
IP4–16X  
IP4–1X  
0111  
1,050  
14.4K  
28.8K  
7,200  
57.6K  
230.4K  
Timer  
IP4–16X  
IP4–1X  
1000  
1001  
1010  
1011  
57.6K  
4,800  
57.6K  
4,800  
57.6K  
9,600  
14.4K  
9,600  
1100  
38.4K  
Timer  
19.2K  
Timer  
1101  
1110  
IP4–16X  
IP4–1X  
IP4–16X  
IP4–1X  
1111  
NOTE:  
1. The receiver clock is always a 16X clock except for CSR[7:4] = 1111. CSR[3:0]— Transmitter Clock Select. This field selects the baud rate  
clock for the transmitter.  
The field definition is as shown in Table 5, except as follows:  
CSR[3:0]  
1110  
1111  
IP3 –16X  
IP3 –1X  
The transmitter clock is always a 16X clock except for CSR[3:0] = 1111.  
Table 6. Bit rate generator characteristics for Crystal or Clock = 3.6864MHz  
NORMAL RATE (BAUD)  
ACTUAL 16X CLOCK (KHz)  
ERROR (%)  
50  
0.8  
0
75  
1.2  
0
110  
134.5  
150  
1.759  
2.153  
2.4  
–0.069  
0.059  
0
200  
3.2  
0
300  
4.8  
0
600  
9.6  
0
1050  
1200  
1800  
2000  
2400  
4800  
7200  
9600  
19.2K  
38.4K  
16.756  
19.2  
28.8  
32.056  
38.4  
76.8  
115.2  
153.6  
307.2  
614.4  
–0.260  
0
0
0.175  
0
0
0
0
0
0
NOTE:  
Duty cycle of 16X clock is 50% 1%  
26  
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Philips Semiconductors  
Product data sheet  
3.3 V or 5.0 V Universal Asynchronous  
Receiver/Transmitter (UART)  
SC28L91  
CR—Command Register  
CR is a register used to supply commands to the UART. Multiple  
commands can be specified in a single write to CR as long as the  
commands are non–conflicting, e.g., the ‘enable transmitter’ and  
‘reset transmitter’ commands cannot be specified in a single  
command word.  
CR COMMAND REGISTER  
Addr  
CR  
Bit 7  
BIT 6  
BIT 5  
BIT 4  
BIT 3  
BIT 2  
BIT 1  
BIT 0  
MISCELLANEOUS COMMANDS  
Disable Tx  
Enable Tx  
Disable Rx  
Enable Rx  
0x02  
See Text of Channel Command Register  
1 = Yes  
0 = No  
1 = Yes  
0 = No  
1 = Yes  
0 = No  
1 = Yes  
0 = No  
NOTES:  
Access to the miscellaneous commands should be separated by 3 X1 clock edges. A disabled transmitter cannot be loaded.  
CR[7:4]—Miscellaneous Commands  
1011  
1100  
Set MR pointer to ‘0’  
Execution of the commands in the upper four bits of this register  
must be separated by 3 X1 clock edges. Other reads or writes  
(including writes to the lower four bits) may be inserted to achieve  
this separation.  
Disable Timeout Mode. This command returns control  
of the C/T to the regular START/STOP counter com-  
mands. It does not stop the counter, or clear any pend-  
ing interrupts. After disabling the timeout mode, a ‘Stop  
Counter’ command should be issued to force a reset of  
the ISR[3] bit  
CR[7:4]—Commands  
1101  
1110  
Not used.  
0000  
0001  
No command.  
Reset MR pointer. Causes the MR pointer to point to  
MR1.  
Power Down Mode On. In this mode, the UART oscilla-  
tor is stopped and all functions requiring this clock are  
suspended. The execution of commands other than  
disable power down mode (1111) requires a X1/CLK.  
While in the power down mode, do not issue any com-  
mands to the CR except the disable power down mode  
command. The contents of all registers will be saved  
while in this mode. It is recommended that the transmit-  
ter and receiver be disabled prior to placing the UART  
into power down mode.  
0010  
Reset receiver. Resets the receiver as if a hardware  
reset had been applied. The receiver is disabled and  
the FIFO is flushed.  
0011  
0100  
Reset transmitter. Resets the transmitter as if a hard-  
ware reset had been applied.  
Reset error status. Clears the Received Break, Parity  
Error, and Overrun Error bits in the status register  
(SR[7:4]). Used in character mode to clear OE status  
(although Received Break, PE and FE bits will also be  
cleared) and in block mode to clear all error status after  
a block of data has been received.  
1111  
Disable Power Down Mode. This command restarts the  
oscillator. After invoking this command, wait for the os-  
cillator to start up before writing further commands to  
the CR.  
0101  
0110  
Reset break change interrupt. Causes the break detect  
change bit in the interrupt status register (ISR[2]) to be  
cleared to zero  
CR[3]—Disable Transmitter  
This command terminates transmitter operation and reset the  
TxRDY and TxEMT status bits. However, if a character is being  
transmitted or if a character is in the TxFIFO when the transmitter is  
disabled, the transmission of the character(s) is completed before  
assuming the inactive state.  
Start break. Forces the TxD output Low (spacing). If the  
transmitter is empty the start of the break condition will  
be delayed up to two bit times. If the transmitter is ac-  
tive the break begins when transmission of the charac-  
ter is completed. If a character is in the TxFIFO, the  
start of the break will be delayed until that character, or  
any other loaded subsequently are transmitted. The  
transmitter must be enabled for this command to be  
accepted.  
CR[2]—Enable Transmitter  
Enables operation of the transmitter. The TxRDY and TxEMT status  
bits will be asserted if the transmitter is idle.  
0111  
Stop break. The TxD line will go High (marking) within  
two bit times. TxD will remain High for one bit time be-  
fore the next character, if any, is transmitted.  
CR[1]—Disable Receiver  
This command terminates operation of the receiver immediately—a  
character being received will be lost. The command has no effect on  
the receiver status bits or any other control registers. If the special  
multi-drop mode is programmed, the receiver operates even if it is  
disabled. See Operation section.  
1000  
1001  
1010  
Assert RTSN. Causes the RTSN output to be asserted  
(Low).  
Negate RTSN. Causes the RTSN output to be negated  
(High)  
Set Timeout Mode On. The receiver in this channel will  
restart the C/T as the receive character is transferred  
from the shift register to the RxFIFO. The C/T is placed  
in the counter mode, the START/STOP counter com-  
mands are disabled, the counter is stopped, and the  
Counter Ready Bit, ISR[3], is reset. (See also Watch-  
dog timer description in the receiver section.)  
CR[0]—Enable Receiver  
Enables operation of the receiver. If not in the special wakeup mode,  
this also forces the receiver into the search for start–bit state.  
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Philips Semiconductors  
Product data sheet  
3.3 V or 5.0 V Universal Asynchronous  
Receiver/Transmitter (UART)  
SC28L91  
SR Status Register  
Addr  
SR  
Bit 7  
BIT 6  
BIT 5  
BIT 4  
BIT 3  
BIT 2  
BIT 1  
BIT 0  
RECEIVED  
BREAK  
FRAMING  
ERROR  
PARITY  
ERROR  
OVERRUN  
ERROR  
TxEMT  
TxRDY  
FFULL  
RxRDY  
1
1
1
0x01  
0 = No  
0 = No  
0 = No  
0 = No  
0 = No  
0 = No  
0 = No  
0 = No  
1 = Yes  
1 = Yes  
1 = Yes  
1 = Yes  
1 = Yes  
1 = Yes  
1 = Yes  
1 = Yes  
1. These status bits are appended to the corresponding data character in the receive FIFO. A read of the status provides these bits [7:5] from  
the top of the FIFO together with bits [4:0]. These bits are cleared by a “reset error status” command. In character mode they are discarded  
when the corresponding data character is read from the FIFO. In block error mode, the error–reset command (command 4x or receiver  
reset) must used to clear block error conditions.  
SR[7]— Received Break  
This bit indicates that an all zero character of the programmed  
length has been received without a stop bit. Only a single FIFO  
position is occupied when a break is received: further entries to the  
FIFO are inhibited until the RxD line returns to the marking state for  
at least one-half a bit time two successive edges of the internal or  
external 1X clock. This will usually require a high time of one X1  
clock period or 3 X1 edges since the clock of the controller is  
not synchronous to the X1 clock.  
This bit is cleared by a ‘reset error status’ command.  
SR[3]— Transmitter Empty (TxEMT)  
This bit will be set when the transmitter under runs, i.e., both the  
TxEMT and TxRDY bits are set. This bit and TxRDY are set when  
the transmitter is first enabled and at any time it is re-enabled after  
either (a) reset, or (b) the transmitter has assumed the disabled  
state. It is always set after transmission of the last stop bit of a  
character if no character is in the THR awaiting transmission.  
When this bit is set, the ‘change in break’ bit in the ISR (ISR[2]) is  
set. ISR[2] is also set when the end of the break condition, as  
defined above, is detected.  
It is reset when the THR is loaded by the CPU, a pending  
transmitter disable is executed, the transmitter is reset, or the  
transmitter is disabled while in the under run condition.  
The break detect circuitry can detect breaks that originate in the  
middle of a received character. However, if a break begins in the  
middle of a character, it must persist until at least the end of the next  
character time in order for it to be detected.  
SR[2]— Transmitter Ready (TxRDY)  
This bit, when set, indicates that the transmit FIFO is not full and  
ready to be loaded with another character. This bit is cleared when  
the transmit FIFO is loaded by the CPU and there are (after this  
load) no more empty locations in the FIFO. It is set when a  
character is transferred to the transmit shift register. TxRDY is reset  
when the transmitter is disabled and is set when the transmitter is  
first enabled. Characters loaded to the TxFIFO while this bit is 0 will  
be lost. This bit has different meaning from ISR[0].  
This bit is reset by command 4 (0100) written to the command  
register or by receiver reset.  
SR[6]— Framing Error  
This bit, when set, indicates that a stop bit was not detected (not a  
logical 1) when the corresponding data character in the FIFO was  
received. The stop bit check is made in the middle of the first stop bit  
position.  
SR[1]— FIFO Full (FFULL)  
This bit is set when a character is transferred from the receive shift  
register to the receive FIFO and the transfer causes the FIFO to  
become full, i.e., all eight (or 16) FIFO positions are occupied. It is  
reset when the CPU reads the receive FIFO. If a character is waiting  
in the receive shift register because the FIFO is full, FFULL will not  
be reset when the CPU reads the receive FIFO. This bit has  
different meaning from IRS when MR1 6 is programmed to a ‘1’.  
SR[5]— Parity Error  
This bit is set when the ‘with parity’ or ‘force parity’ mode is  
programmed and the corresponding character in the FIFO was  
received with incorrect parity.  
In the special multi-drop mode the parity error bit stores the receive  
A/D (Address/Data) bit.  
SR[0]— Receiver Ready (RxRDY)  
SR[4]— Overrun Error  
This bit indicates that a character has been received and is waiting  
in the FIFO to be read by the CPU. It is set when the character is  
transferred from the receive shift register to the FIFO and reset  
when the CPU reads the receive FIFO, only if (after this read) there  
are no more characters in the FIFO – the Rx FIFO becomes empty.  
This bit, when set, indicates that one or more characters in the  
received data stream have been lost. It is set upon receipt of a new  
character when the FIFO is full and a character is already in the  
receive shift register waiting for an empty FIFO position. When this  
occurs, the character in the receive shift register (and its break  
detect, parity error and framing error status, if any) is lost.  
28  
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Philips Semiconductors  
Product data sheet  
3.3 V or 5.0 V Universal Asynchronous  
Receiver/Transmitter (UART)  
SC28L91  
OPCR Output Port Configuration Register  
Addr  
OPCR  
0x0D  
Bit 7  
BIT 6  
BIT 5  
OP5  
BIT 4  
OP4  
BIT 3  
OP3  
BIT 2  
OP2  
BIT 1  
OP1  
BIT 0  
OP0  
OP7  
OP6  
0 = OPR[7]  
1 = Reserved 1 = TxRDY  
0 = OPR[6]  
0 = OPR[5]  
1 = Reserved  
0 = OPR[4]  
1 = RxRDY/FFULL  
00 = OPR[3]  
00 = OPR[2]  
01 = TxC(16X)  
10 = TxC(1X)  
11 = RxC(1X)  
01 = C/T OUTPUT  
10 = Reserved  
11 = Reserved  
OPCR[7]—OP7 Output Select  
This bit programs the OP7 output to provide one of the following:  
OPCR[3:2]—OP3 Output Select  
This bit programs the OP3 output to provide one of the following:  
0
1
The complement of OPR[7].  
reserved  
00 The complement of OPR[3].  
01 The counter/timer output, in which case OP3 acts as an  
open-drain output. In the timer mode, this output is a square  
wave at the programmed frequency. In the counter mode,  
the output remains High until terminal count is reached, at  
which time it goes Low. The output returns to the High state  
when the counter is stopped by a stop counter command.  
Note that this output is not masked by the contents of the  
IMR.  
OPCR[6]—OP6 Output Select  
This bit programs the OP6 output to provide one of the following:  
0
1
The complement of OPR[6].  
The transmitter interrupt output which is the complement of  
ISR[0]. When in this mode OP6 acts as an open-drain out-  
put. Note that this output is not masked by the contents of  
the IMR.  
10 Reserved  
11 Reserved  
OPCR[5]—OP5 Output Select  
This bit programs the OP5 output to provide one of the following:  
OPCR[1:0]—OP2 Output Select  
This field programs the OP2 output to provide one of the following:  
0
1
The complement of OPR[5].  
Reserved  
00 The complement of OPR[2].  
01 The 16X clock for the transmitter. This is the clock selected  
by CSR[3:0], and will be a 1X clock if CSR[3:0] = 1111.  
OPCR[4]—OP4 Output Select  
10 The 1X clock for the transmitter, which is the clock that shifts  
the transmitted data. If data is not being transmitted, a free  
running 1X clock is output.  
This field programs the OP4 output to provide one of the following:  
0
1
The complement of OPR[4].  
The receiver interrupt output which is the complement of  
ISR[1]. When in this mode OP4 acts as an open-drain out-  
put. Note that this output is not masked by the contents of  
the IMR.  
11 The 1X clock for the receiver, which is the clock that samples  
the received data. If data is not being received, a free run-  
ning 1X clock is output.  
SOPR—Set the Output Port Bits (OPR)  
SOPR[7:0]—Ones in the byte written to this register will cause the corresponding bit positions in the OPR to set to 1. Zeros have no effect. This  
allows software to set individual bits with our keeping a copy of the OPR bit configuration.  
Addr  
SOPR  
0x0E  
Bit 7  
OP 7  
BIT 6  
OP 6  
BIT 5  
OP 5  
BIT 4  
OP 4  
BIT 3  
OP 3  
BIT 2  
OP 2  
BIT 1  
OP 1  
BIT 0  
OP 0  
1 = set bit  
1 = set bit  
1 = set bit  
1 = set bit  
1 = set bit  
1 = set bit  
1 = set bit  
1 = set bit  
0 = no change  
0 = no change  
0 = no change  
0 = no change  
0 = no change  
0 = no change  
0 = no change  
0 = no change  
ROPR—Reset Output Port Bits (OPR)  
ROPR[7:0]—Ones in the byte written to the ROPR will cause the corresponding bit positions in the OPR to set to 0. Zeros have no effect. This  
allows software to reset individual bits with our keeping a copy of the OPR bit configuration.  
Addr  
ROPR  
0x0F  
Bit 7  
OP 7  
BIT 6  
OP 6  
BIT 5  
OP 5  
BIT 4  
OP 4  
BIT 3  
OP 3  
BIT 2  
OP 2  
BIT 1  
OP 1  
BIT 0  
OP 0  
1 = reset bit  
1 = reset bit  
1 = reset bit  
1 = reset bit  
1 = reset bit  
1 = reset bit  
1 = reset bit  
1 = reset bit  
0 = no change  
0 = no change  
0 = no change  
0 = no change  
0 = no change  
0 = no change  
0 = no change  
0 = no change  
29  
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Philips Semiconductors  
Product data sheet  
3.3 V or 5.0 V Universal Asynchronous  
Receiver/Transmitter (UART)  
SC28L91  
OPR Output Port Register  
The output pins (OP pins) drive the compliment of the data in this register as controlled by SOPR and ROPR.  
Addr  
N/A  
Bit 7  
OP 7  
BIT 6  
OP 6  
BIT 5  
OP 5  
BIT 4  
OP 4  
BIT 3  
OP 3  
BIT 2  
OP 2  
BIT 1  
OP 1  
BIT 0  
OP 0  
N/A  
0 = Pin High 0 = Pin High  
1 = Pin Low 1 = Pin Low  
0 = Pin High  
1 = Pin Low  
0 = Pin High  
1 = Pin Low  
0 = Pin High  
1 = Pin Low  
0 = Pin High  
1 = Pin Low  
0 = Pin High  
1 = Pin Low  
0 = Pin High  
1 = Pin Low  
ACR Auxiliary Control Register  
Addr  
ACR  
Bit 7  
BIT 6  
BIT 5  
BIT 4  
BIT 3  
BIT 2  
BIT 1  
BIT 0  
BRG SET  
Select  
Counter Timer Mode  
Mode and clock sour select  
Delta IP3 int Delta IP3 int Delta IP3 int Delta IP3 int  
enable  
enable  
enable  
enable  
0x04  
0 = set 1  
1 = set 2  
See table 7  
0 = off  
1 = enabled  
0 = off  
1 = enabled  
0 = off  
1 = enabled  
0 = off  
1 = enabled  
ACR—Auxiliary Control Register  
ACR[7]—Baud Rate Generator Set Select  
This bit selects one of two sets of baud rates to be generated by the  
BRG (see Table 5).  
Table 7. ACR 6:4 field definition  
ACR  
6:4  
MODE  
CLOCK SOURCE  
The selected set of rates is available for use by the receiver and  
transmitter as described in CSR. Baud rate generator characteristics  
are given in Table 6.  
000  
001  
010  
011  
100  
101  
110  
111  
Counter  
Counter  
External (IP2)  
TxC – 1X clock of transmitter  
reserved  
ACR[6:4]—Counter/Timer Mode And Clock Source Select  
This field selects the operating mode of the counter/timer and its  
clock source as shown in Table 7  
Counter  
Timer  
Timer  
Timer  
Timer  
Crystal or X1/CLK clock divided by 16  
External (IP2)  
External (IP2) divided by 16  
Crystal or external clock (X1/CLK)  
ACR[3:0]—IP3, IP2, IP1, IP0 Change-of-State Interrupt Enable  
This field selects which bits of the input port change register (IPCR)  
cause the input change bit in the interrupt status register (ISR [7]) to  
be set. If a bit is in the ‘on’ state the setting of the corresponding bit  
in the IPCR will also result in the setting of ISR [7], which results in  
the generation of an interrupt output if IMR [7] = 1. If a bit is in the  
‘off’ state, the setting of that bit in the IPCR has no effect on ISR [7].  
Crystal or external clock (X1/CLK) divided  
by 16  
NOTE:  
1. The timer mode generates a square wave  
IPCR Input Port change Register  
Addr  
IPCR  
0x04  
Bit 7  
BIT 6  
BIT 5  
BIT 4  
BIT 3  
IP 3  
BIT 2  
IP 2  
BIT 1  
IP 1  
BIT 0  
IP 0  
Delta IP3  
Delta IP3  
Delta IP3  
Delta IP3  
0 = no change 0 = no change 0 = no change 0 = no change 0 = low  
1 = change 1 = change 1 = change 1 = change 1 = High  
0 = low  
0 = low  
0 = low  
1 = High  
1 = High  
1 = High  
IPCR[7:4]—IP3, IP2, IP1, IP0 Change-of-State  
These bits are set when a change-of-state, as defined in the input  
port section of this data sheet, occurs at the respective input pins.  
They are cleared when the IPCR is read by the CPU. A read of the  
IPCR also clears ISR [7], the input change bit in the interrupt status  
register. The setting of these bits can be programmed to generate  
an interrupt to the CPU.  
IPCR[3:0]—IP3, IP2, IP1, IP0 Change-of-State  
These bits provide the current state of the respective inputs. The  
information is unlatched and reflects the state of the input pins at the  
time the IPCR is read.  
30  
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Philips Semiconductors  
Product data sheet  
3.3 V or 5.0 V Universal Asynchronous  
Receiver/Transmitter (UART)  
SC28L91  
corresponding bit in the IMR is a zero, the state of the bit in the ISR  
has no effect on the INTRN output. Note that the IMR does not mask  
the reading of the ISR – the true status will be provided regardless  
of the contents of the IMR. The contents of this register are  
initialized to 0x00’ when the UART is reset.  
ISR—Interrupt Status Register  
This register provides the status of all potential interrupt sources.  
The contents of this register are masked by the Interrupt Mask  
Register (IMR). If a bit in the ISR is a ‘1’ and the corresponding bit in  
the IMR is also a ‘1’, the INTRN output will be asserted (Low). If the  
ISR Interrupt Status Register  
Addr  
ISR  
Bit 7  
Bits[6:4]  
BIT 3  
BIT 2  
BIT 1  
BIT 0  
INPUT PORT  
CHANGE  
Ignore in ISR reads.  
Reserved for future function  
Counter  
Ready  
Delta  
Break  
RxRDY/  
FFULL  
TxRDY  
0x05  
0 = not active  
1 = active  
0 = not active 0 = not active 0 = not active 0 = not active  
1 = active  
1 = active  
1 = active  
1 = active  
ISR[7]—Input Port Change Status  
ISR[1]—Rx Interrupt  
This bit is a ‘1’ when a change–of–state has occurred at the IP0,  
IP1, IP2, or IP3 inputs and that event has been selected to cause an  
interrupt by the programming of ACR[3:0]. The bit is cleared when  
the CPU reads the IPCR.  
This bit indicates that the receiver is interrupting according to the fill  
level programmed by the MR0 and MR1 registers. This bit has a  
different meaning than the receiver ready/full bit in the status  
register.  
ISR[6:4]—Not used, Ignore in ISR read.  
ISR[0]—Tx Interrupt  
This bit indicates that the transmitter is interrupting according to the  
interrupt level programmed in the MR0[5:4] bits. This bit has a  
different meaning than the TxRDY bit in the status register.  
ISR[3]—Counter Ready.  
In the counter mode, this bit is set when the counter reaches  
terminal count and is reset when the counter is stopped by a stop  
counter command.  
IMR—Interrupt Mask Register  
The programming of this register selects which bits in the ISR  
causes an interrupt output. If a bit in the ISR is a ‘1’ and the  
corresponding bit in the IMR is also a ‘1’ the INTRN output will be  
asserted. If the corresponding bit in the IMR is a zero, the state of  
the bit in the ISR has no effect on the INTRN output. Note that the  
IMR does not mask the programmable interrupt outputs OP3–OP7  
or the reading of the ISR.  
In the timer mode, this bit is set once the cycle of the generated  
square wave (every other time that the counter/timer reaches zero  
count). The bit is reset by a stop counter command. The command,  
however, does not stop the counter/timer.  
ISR[2]— Change in Break  
This bit, when set, indicates that the receiver has detected the  
beginning or the end of a received break. It is reset when the CPU  
issues a ‘reset break change interrupt’ command.  
IMR Interrupt Mask Register  
Addr  
IMR  
Bit 7  
BIT 6  
BIT 5  
BIT 4  
BIT 3  
BIT 2  
BIT 1  
BIT 0  
INPUT PORT  
CHANGE  
Reserved  
Reserved  
Reserved  
Counter  
Ready  
Delta  
Break  
RxRDY/  
FFULL  
TxRDY  
0x05  
0 = not enabled Set to 0  
1 = enabled  
Set to 0  
Set to 0  
0 = not enabled 0 = not enabled 0 = not enabled 0 = not enabled  
1 = enabled  
1 = enabled  
1 = enabled  
1 = enabled  
IVR/GP– Interrupt Vector Register (68k mode) or General–purpose register (80XXX mode)  
IVR/GP  
Bit 7  
BIT 6  
BIT 5  
BIT 4  
BIT 3  
BIT 2  
BIT 1  
BIT 0  
0x0C  
Interrupt Vector Register (68XXX mode) or General–purpose register (80XXX mode)  
This register stores the Interrupt Vector. It is initialized to 0x0F on  
hardware reset and is usually changed from this value during  
initialization of the SC28L91 for the 68K Mode. The contents of this  
register will be placed on the data bus when IACKN is asserted low  
or a read of address 0xC is performed.  
When not operating in the 68XXX mode, this register may be used  
as a general-purpose one-byte storage register. A convenient use  
may the storing a “shadow” of the contents of another SC28L91  
register (IMR, for example).  
31  
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Philips Semiconductors  
Product data sheet  
3.3 V or 5.0 V Universal Asynchronous  
Receiver/Transmitter (UART)  
SC28L91  
CTPU and CTPL – Counter/Timer Registers  
CTPU Counter Timer Preset Upper  
CTPU  
Bit 7  
BIT 6  
BIT 5  
BIT 4  
BIT 3  
BIT 2  
BIT 2  
BIT 1  
BIT 1  
BIT 0  
BIT 0  
0x06  
The lower eight (8) bits for the 16 bit counter timer preset register  
CTPL Counter –Timer Preset Low  
CTPL  
Bit 7  
BIT 6  
BIT 5  
BIT 4  
BIT 3  
0x07  
The Upper eight (8) bits for the 16 bit counter timer preset register  
The CTPU and CTPL hold the eight MSbs and eight Labs,  
respectively, of the value to be used by the counter/timer in either  
the counter or timer modes of operation. The minimum value which  
may be loaded into the CTPU/CTPL registers is H‘0002’. Note that  
these registers are write-only and cannot be read by the CPU.  
counter are read. However, note that a subsequent start counter  
command will cause the counter to begin a new count cycle using  
the values in CTPU and CTPL.  
When the C/T clock divided by 16 is selected, the maximum divisor  
becomes 1,048,575.  
In the timer mode, the C/T generates a square wave whose period is  
twice the value (in C/T clock periods) of the CTPU and CTPL. The  
waveform so generated is often used for a data clock. The formula  
for calculating the divisor n to load to the CTPU and CTPL for a  
particular 1X data clock is shown below.  
Output Port Notes  
The output ports are controlled from four places: the OPCR register,  
the OPR register, the MR registers and the command register  
(except the 2681 and 68681) The OPCR register controls the source  
of the data for the output ports OP2 through OP7. The data source  
for output ports OP0 and OP1 is controlled by the MR and CR  
registers. When the OPR is the source of the data for the output  
ports, the data at the ports is inverted from that in the OPR register.  
n = (C/T Clock Frequency) divided by (2 x 16 x Baud rate desired)  
Often this division will result in a non-integer number; 26.3, for  
example. One can only program integer numbers in a digital divider.  
Therefore 26 would be chosen. This gives a baud rate error of  
0.3/26.3 which is 1.14%; well within the ability asynchronous mode  
of operation.  
The content of the OPR register is controlled by the “Set Output Port  
Bits Command” and the “Reset Output Bits Command”. These  
commands are at E and F, respectively. When these commands are  
used, action takes place only at the bit locations where ones exist.  
For example, a one in bit location 5 of the data word used with the  
“Set Output Port Bits” command will result in OPR[5] being set to  
one. The OP5 would then be set to zero (V SS ). Similarly, a one in  
bit position 5 of the data word associated with the “Reset Output  
Ports Bits” command would set OPR[5] to zero and, hence, the pin  
The C/T will not be running until it receives an initial ‘Start Counter’  
command (read at address A3–A0 = 1110). After this, while in timer  
mode, the C/T will run continuously. Receipt of a start counter  
command (read with A3–A0 = 1110) causes the counter to terminate  
the current timing cycle and to begin a new cycle using the values in  
CTPU and CTPL. If the value in CTPU and CTPL is changed, the  
current half-period will not be affected, but subsequent half periods  
will be affected.  
OP5 to a one (V ).  
DD  
The CTS, RTS, CTS Enable Tx signals  
The counter ready status bit (ISR[3]) is set once each cycle of the  
square wave. The bit is reset by a stop counter command (read with  
A3–A0 = 0xF). The command however, does not stop the C/T. The  
generated square wave is output on OP3 if it is programmed to be  
the C/T output. In the counter mode, the value C/T loaded into  
CTPU and CTPL by the CPU is counted down to 0. Counting begins  
upon receipt of a start counter command. Upon reaching terminal  
count 0x0000, the counter ready interrupt bit (ISR[3]) is set. The  
counter continues counting past the terminal count until stopped by  
the CPU. If OP3 is programmed to be the output of the C/T, the  
output remains high until terminal count is reached, at which time it  
goes low. The output returns to the High state and ISR[3] is cleared  
when the counter is stopped by a stop counter command. The CPU  
may change the values of CTPU and CTPL at any time, but the new  
count becomes effective only on the next start counter commands. If  
new values have not been loaded, the previous count values are  
preserved and used for the next count cycle.  
CTS (Clear To Send) is usually meant to be a signal to the  
transmitter meaning that it may transmit data to the receiver. The  
CTS input is on pin IP0 for Tx. The CTS signal is active low; thus, it  
is called CTSN for TxRTS is usually meant to be a signal from the  
receiver indicating that the receiver is ready to receive data. It is  
also active low and is, thus, called RTSN for Rx. RTSN is on pin  
OP0. A receiver’s RTS output will usually be connected to the CTS  
input of the associated transmitter. Therefore, one could say that  
RTS and CTS are different ends of the same wire!  
MR2[4] is the bit that allows the transmitter to be controlled by the  
CTS pin (IP0 or IP1). When this bit is set to one AND the CTS input  
is driven high, the transmitter will stop sending data at the end of the  
present character being serialized. It is usually the RTS output of the  
receiver that will be connected to the transmitter’s CTS input. The  
receiver will set RTS high when the receiver FIFO is full AND the  
start bit of the ninth or 17th character is sensed. Transmission then  
stops with nine or 17 valid characters in the receiver. When MR2[4]  
is set to one, CTSN must be at zero for the transmitter to operate. If  
MR2[4] is set to zero, the IP pin will have no effect on the operation  
of the transmitter. MR1[7] is the bit that allows the receiver to control  
OP0. When OP0 (or OP1) is controlled by the receiver, the meaning  
of that pin will be.  
In the counter mode, the current value of the upper and lower 8 bits  
of the counter (CTU, CTL) may be read by the CPU. It is  
recommended that the counter be stopped when reading to prevent  
potential problems which may occur if a carry from the lower 8 bits  
to the upper 8 bits occurs between the times that both halves of the  
32  
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Philips Semiconductors  
Product data sheet  
3.3 V or 5.0 V Universal Asynchronous  
Receiver/Transmitter (UART)  
SC28L91  
RESETN  
RESETN  
t
RES  
t
RES  
80XXX Mode  
68XXX Mode  
SD00696  
Figure 4. Reset Timing  
A0–A3  
CEN  
t
t
AS  
t
AH  
t
CS  
CH  
t
t
RWD  
RW  
RDN  
t
t
DF  
DD  
NOT  
VALID  
D0–D7  
(READ)  
FLOAT  
VALID  
FLOAT  
t
RWD  
WDN  
t
DS  
t
DH  
D0–D7  
(WRITE)  
VALID  
SD00087  
NOTE:  
Bus action in the 80XXX mode terminates on the rise of CEN, WRN, or RDN which ever one occurs first.  
Figure 5. Bus Timing (80XXX mode)  
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Philips Semiconductors  
Product data sheet  
3.3 V or 5.0 V Universal Asynchronous  
Receiver/Transmitter (UART)  
SC28L91  
t
CSC  
X1/CLK  
t
AS  
A1–A4  
t
CS  
t
CH  
RWN  
t
RWD  
t
CSN  
AH  
t
t
DF  
DD  
NOT  
VALID  
D0–D7  
DATA VALID  
t
DA  
DTACKN  
t
DAH  
t
DCR  
t
DAT  
NOTE: DACKN low requires two rising edges of X1 clock after CSN is low.  
SD00687  
Figure 6. Bus Timing (Read Cycle) (68XXX mode)  
t
CSC  
X1/CLK  
t
AS  
A1–A4  
RWN  
t
t
CH  
CS  
t
RWD  
t
CSN  
AH  
D0–D7  
t
DH  
t
DS  
DTACKN  
t
t
DAH  
DCW  
t
DAT  
NOTE: DACKN low requires two rising edges of X1 clock after CSN is low.  
SD00688  
Figure 7. Bus Timing (Write Cycle) (68XXX mode)  
NOTE:  
For Figures 6 and 7 WRN changing within the time of CEN low may cause short read or write pulses that could upset internal pointers and  
registers. Bus action terminates on the rise of CEN or the fall of DACKN, which ever occurs first.  
34  
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Philips Semiconductors  
Product data sheet  
3.3 V or 5.0 V Universal Asynchronous  
Receiver/Transmitter (UART)  
SC28L91  
t
CSC  
X1/CLK  
INTRN  
IACKN  
t
t
DF  
DD  
D0–D7  
t
CSD  
t
DAL  
DTACKN  
t
t
DCR  
DAH  
t
DAT  
NOTE: DACKN low requires two rising edges of X1 clock after CSN is low.  
SD00149  
Figure 8. Interrupt Cycle Timing (68XXX mode)  
RDN  
t
t
PH  
PS  
IP0–IP6  
(a) INPUT PINS  
WRN  
t
PD  
OP0–OP7  
OLD DATA  
NEW DATA  
(b) OUTPUT PINS  
SD00135  
Figure 9. Port Timing  
35  
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Philips Semiconductors  
Product data sheet  
3.3 V or 5.0 V Universal Asynchronous  
Receiver/Transmitter (UART)  
SC28L91  
V
M
WRN  
t
IR  
1
INTERRUPT  
V
+0.5V  
OL  
OUTPUT  
V
OL  
V
M
RDN  
t
IR  
1
INTERRUPT  
V
+0.5V  
OL  
OUTPUT  
V
OL  
NOTES:  
1. INTRN or OP3-OP7 when used as interrupt outputs.  
2. The test for open-drain outputs is intended to guarantee switching of the output transistor. Measurement of this response is referenced from the midpoint of the switching  
signal, V , to a point 0.5V above V . This point represents noise margin that assures true switching has occurred. Beyond this level, the effects of external circuitry and  
M
OL  
test environment are pronounced and can greatly affect the resultant measurement.  
SD00136  
Figure 10. Interrupt Timing (80xxx mode)  
t
t
t
t
V
CLK  
CTC  
Rx  
CC  
NOTE:  
RESISTOR REQUIRED  
FOR TTL INPUT.  
470Ω  
Tx  
X1/CLK  
CTCLK  
RxC  
CLK  
X1  
TxC  
t
t
t
t
CLK  
CTC  
Rx  
X2*  
*NOTE: X2 MUST BE LEFT OPEN.  
SC28L91  
Tx  
3pF  
PARASITIC CAPACITANCE  
X1  
2pF  
C1  
50kΩ  
to  
100kΩ  
C2  
4pF  
X2  
TO UART  
CIRCUIT  
3.6864MHz  
3pF  
PARASITIC CAPACITANCE  
C1 = C2 24pF FOR C = 20pF  
L
C1 and C2 should be chosen according to the crystal manufacturer’s specification.  
C1 and C2 values will include any parasitic capacitance of the wiring and X1 X2 pins.  
Gain at 3.6864MHz: 9 to 13 dB  
Package capacitance approximately 4pF.  
SD00704  
Figure 11. Clock Timing  
36  
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Product data sheet  
3.3 V or 5.0 V Universal Asynchronous  
Receiver/Transmitter (UART)  
SC28L91  
1 BIT TIME  
(1 OR 16 CLOCKS)  
TxC  
(INPUT)  
t
TXD  
TxD  
t
TCS  
TxC  
(1X OUTPUT)  
SD00138  
Figure 12. Transmitter External Clocks  
RxC  
(1X INPUT)  
t
t
RXH  
RXS  
RxD  
SD00139  
Figure 13. Receiver External Clock  
TxD  
D1  
D2  
D3  
BREAK  
D4  
D6  
TRANSMITTER  
ENABLED  
TxRDY  
(SR2)  
WRN  
D1  
D8  
D9  
START  
BREAK  
D10  
STOP  
BREAK  
D11 WILL  
NOT BE  
D12  
WRITTEN TO  
THE TxFIFO  
1
CTSN  
(IP0)  
2
RTSN  
(OP0)  
OPR(0) = 1  
OPR(0) = 1  
NOTES:  
1. Timing shown for MR2[4] = 1.  
2. Timing shown for MR2[5] = 1.  
SD00155  
Figure 14. Transmitter Timing  
37  
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Product data sheet  
3.3 V or 5.0 V Universal Asynchronous  
Receiver/Transmitter (UART)  
SC28L91  
D1  
D2  
D8  
D9  
D10  
D11  
D12  
D13  
RxD  
D12, D13 WILL BE LOST  
DUE TO RECEIVER DISABLE.  
RECEIVER  
ENABLED  
RxRDY  
(SR0)  
FFULL  
(SR1)  
RxRDY/  
FFULL  
2
(OP5)  
RDN  
STATUS DATA  
STATUS DATA STATUS DATA STATUS DATA  
D11 WILL BE LOST  
DUE TO OVERRUN  
D1  
D2  
D3  
D10  
OVERRUN  
(SR4)  
RESET BY COMMAND  
1
RTS  
(OP0)  
OPR[0] = 1  
NOTES:  
1. Timing shown for MR1[7] = 1.  
2. Shown for OPCR[4] = 1 and MR[6] = 0.  
SD00156  
Figure 15. Receiver Timing  
MASTER STATION  
TxD  
BIT 9  
BIT 9  
BIT 9  
1
ADD#1  
1
D0  
0
ADD#2  
TRANSMITTER  
ENABLED  
TxRDY  
(SR2)  
WRN  
MR1[4:3] = 11  
MR1[2] = 1  
ADD#1 MR1[2] = 0 D0  
MR1[2] = 1 ADD#2  
PERIPHERAL STATION  
BIT 9  
BIT 9  
1
BIT 9  
0
BIT 9  
BIT 9  
0
0
ADD#1  
D0  
ADD#2  
1
RxD  
RECEIVER  
ENABLED  
RxRDY  
(SR0)  
RDN/WRN  
MR1[4:3] = 11  
ADD#1  
STATUS DATA  
STATUS DATA  
ADD#2  
D0  
SD00096  
Figure 16. Wake-Up Mode  
38  
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Product data sheet  
3.3 V or 5.0 V Universal Asynchronous  
Receiver/Transmitter (UART)  
SC28L91  
I = 2.4mA  
INTRN  
DACKN  
+5V  
125pF  
I = 2.4mA V return to V for a 0 level  
OL  
CC  
I = 400µA V  
return to V for a 1 level  
SS  
OH  
D0–D7  
TxDA/B  
OP0–OP7  
125pF  
SD00690  
Figure 17. Test Conditions on Outputs  
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Philips Semiconductors  
Product data sheet  
3.3 V or 5.0 V Universal Asynchronous  
Receiver/Transmitter (UART)  
SC28L91  
PLCC44: plastic leaded chip carrier; 44 leads  
SOT187-2  
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Philips Semiconductors  
Product data sheet  
3.3 V or 5.0 V Universal Asynchronous  
Receiver/Transmitter (UART)  
SC28L91  
QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm  
SOT307-2  
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Philips Semiconductors  
Product data sheet  
3.3 V or 5.0 V Universal Asynchronous  
Receiver/Transmitter (UART)  
SC28L91  
REVISION HISTORY  
Rev  
Date  
Description  
_3  
20041021  
Product data (9397 750 13124). Supersedes Product specification of 2000 Sep 22 (9397 750 07549).  
Modifications:  
AC electrical characteristics (5 V) table:  
t  
t  
t  
t  
(min.) changed from “15 ns” to “17 ns”.  
(max.) changed from “20 ns” to “35 ns”.  
(max.) changed from “20 ns” to “35 ns”.  
(min.) changed from “10 ns” to “16 ns”.  
RWD  
DCR  
DCW  
CSC  
AC electrical characteristics (3.3 V) table:  
t (min.) changed from “25 ns” to “33 ns”.  
AH  
t (min.) changed from “25 ns” to “43 ns”.  
DS  
t  
(min.) changed from “20 ns” to “27 ns”.  
RWD  
t (max.) changed from “70 ns” to “75 ns”.  
PD  
t  
t  
t  
t  
t  
t  
(max.) changed from “60 ns” to “79 ns”.  
(min.) changed from “30 ns” to “35 ns”.  
(max.) changed from “60 ns” to “78 ns”.  
IRH  
CLK  
TXD  
DCR  
DCW  
CSC  
(max.) changed from “25 ns” to “57 ns”.  
(max.) changed from “25 ns” to “57 ns”.  
(min.) changed from “15 ns” to “30 ns”.  
_2  
20000922  
Product specification (9397 750 07549). ECN 853-2219 24638 of 22 September 2000.  
Supersedes data of 2000 Apr 03.  
42  
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Product data sheet  
3.3 V or 5.0 V Universal Asynchronous  
Receiver/Transmitter (UART)  
SC28L91  
Data sheet status  
Product  
status  
Definitions  
[1]  
Level  
Data sheet status  
[2] [3]  
I
Objective data sheet  
Development  
This data sheet contains data from the objective specification for product development.  
Philips Semiconductors reserves the right to change the specification in any manner without notice.  
II  
Preliminary data sheet  
Product data sheet  
Qualification  
Production  
This data sheet contains data from the preliminary specification. Supplementary data will be published  
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in  
order to improve the design and supply the best possible product.  
III  
This data sheet contains data from the product specification. Philips Semiconductors reserves the  
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant  
changes will be communicated via a Customer Product/Process Change Notification (CPCN).  
[1] Please consult the most recently issued data sheet before initiating or completing a design.  
[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL  
[3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.  
Definitions  
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see  
the relevant data sheet or data handbook.  
LimitingvaluesdefinitionLimiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting  
values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given  
in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.  
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no  
representation or warranty that such applications will be suitable for the specified use without further testing or modification.  
Disclaimers  
Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be  
expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree  
to fully indemnify Philips Semiconductors for any damages resulting from such application.  
Right to make changes — Philips Semiconductors reserves the right to make changes in the products—including circuits, standard cells, and/or software—described  
or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated  
viaaCustomerProduct/ProcessChangeNotification(CPCN).PhilipsSemiconductorsassumesnoresponsibilityorliabilityfortheuseofanyoftheseproducts,conveys  
nolicenseortitleunderanypatent, copyright, ormaskworkrighttotheseproducts, andmakesnorepresentationsorwarrantiesthattheseproductsarefreefrompatent,  
copyright, or mask work right infringement, unless otherwise specified.  
Koninklijke Philips Electronics N.V. 2004  
Contact information  
All rights reserved. Printed in U.S.A.  
For additional information please visit  
Fax: +31 40 27 24825  
Date of release: 10-04  
9397 750 13124  
For sales offices addresses send e-mail to:  
Document order number:  
Philips  
Semiconductors  
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