Omron Video Game Controller C20K User Manual
Cat. No. W146-E1-5  
SYSMAC  
C20K/C28K/C40K/C60K  
Programmable Controllers  
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K-type  
Programmable Controllers  
OPERATION MANUAL  
Revised July 1999  
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Notice:  
OMRON products are manufactured for use according to proper procedures by a qualified operator  
and only for the purposes described in this manual.  
The following conventions are used to indicate and classify precautions in this manual. Always heed  
the information provided with them. Failure to heed precautions can result in injury to people or dam-  
age to property.  
DANGER  
Indicates an imminently hazardous situation which, if not avoided, will result in death or  
serious injury.  
!
!
!
WARNING  
Caution  
Indicates a potentially hazardous situation which, if not avoided, could result in death or  
serious injury.  
Indicates a potentially hazardous situation which, if not avoided, may result in minor or  
moderate injury, or property damage.  
OMRON Product References  
All OMRON products are capitalized in this manual. The word “Unit” is also capitalized when it refers  
to an OMRON product, regardless of whether or not it appears in the proper name of the product.  
The abbreviation “Ch,” which appears in some displays and on some OMRON products, often means  
“word” and is abbreviated “Wd” in documentation in this sense.  
The abbreviation “PC” means Programmable Controller and is not used as an abbreviation for any-  
thing else.  
Visual Aids  
The following headings appear in the left column of the manual to help you locate different types of  
information.  
Note Indicates information of particular interest for efficient and convenient operation  
of the product.  
1, 2, 3... 1. Indicates lists of one sort or another, such as procedures, checklists, etc.  
OMRON, 1992  
All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted, in any  
form, or by any means, mechanical, electronic, photocopying, recording, or otherwise, without the prior written permis-  
sion of OMRON.  
No patent liability is assumed with respect to the use of the information contained herein. Moreover, because OMRON is  
constantly striving to improve its high-quality products, the information contained in this manual is subject to change  
without notice. Every precaution has been taken in the preparation of this manual. Nevertheless, OMRON assumes no  
responsibility for errors or omissions. Neither is any liability assumed for damages resulting from the use of the informa-  
tion contained in this publication.  
ii  
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About this Manual:  
The OMRON K-type Programmable Controllers offer an effective way to automate processing, man-  
ufacturing, assembly, packaging, and many other processes to save time and money. Distributed con-  
trol systems can also be designed to allow centralized monitoring and supervision of several separate  
controlled systems. Monitoring and supervising can be done through a host computer, connecting the  
controlled system to a data bank. It is thus possible to have adjustments in system operation made  
automatically to compensate for requirement changes.  
The K-type Units can utilize a number of additional Units including dedicated Special I/O Units that  
can be used for specific tasks and Link Units that can be used to build more highly integrated sys-  
tems.  
The K-types are equipped with large programming instruction sets, data areas, and other features to  
control processing directly. Programming utilizes ladder-diagram programming methods, which are  
described in detail for those unfamiliar with them.  
This manual describes the characteristics and abilities of the K-types programming operations, in-  
structions, and other aspects of operation and preparation that demand attention. Before attempting  
to operate the PC, thoroughly familiarize yourself with the information contained herein. Hardware  
information is provided in detail in the Installation Guide. A table of other manuals that can be used in  
combination with this manual is provided at the end of Section 1 Introduction.  
Section 1 Introduction explains the background and some of the basic terms used in ladder-diagram  
programming. It also provides an overview of the process of programming and operating a PC and  
explains basic terminology used with OMRON PCs. Descriptions of peripheral devices used with the  
K-types and a table of other manuals available to use with this manual for special PC applications are  
also provided.  
Section 2 Hardware Considerations explains basic aspects of the overall PC configuration and de-  
scribes the indicators that are referred to in other sections of this manual.  
Section 3 Memory Areas takes a look at the way memory is divided and allocated and explains the  
information provided there to aid in programming. It also explains how I/O is managed in memory and  
how bits in memory correspond to specific I/O points.  
Section 4 Programming explains the basics of writing and inputting the ladder-diagram program,  
looking at the elements that make up the ‘ladder’ part of a ladder-diagram program and explaining  
how execution of this program is controlled and the methods required to input it input the PC. Sec-  
tion 5 Instruction Set then goes on to describe individually all of the instructions used in program-  
ming, while Section 6 Program Execution Timing explains the scanning process used to execute  
the program and tells how to coordinate inputs and outputs so that they occur at the proper times.  
Section 7 Debugging and Execution provides the Programming Console procedures used to debug  
the program and to monitor and control system operation.  
Finally, Section 8 Troubleshooting provides information on system error indications and other  
means of reducing system down time. Information in this section is also necessary when debugging a  
program.  
The Appendices provide tables of standard OMRON products available for the K-types, reference  
tables of instructions and Programming Console operations, and other information helpful in PC op-  
eration.  
! WARNING Failure to read and understand the information provided in this manual may result in  
personal injury or death, damage to the product, or product failure. Please read each  
section in its entirety and be sure you understand the information provided in the section  
and related sections before attempting any of the procedures or operations given.  
iii  
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TABLE OF CONTENTS  
PRECAUTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
ix  
x
x
x
x
1
2
3
4
5
Intended Audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
General Precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Safety Precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Operating Environment Precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Application Precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
xi  
SECTION 1 – Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
1-1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
1-2 Relay Circuits: The Roots of PC Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
1-3 PC Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
1-4 OMRON Product Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
1-5 Overview of PC Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
1-6 Peripheral Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
1-7 Available Manuals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
1
2
2
3
3
4
5
6
SECTION 2 – Hardware Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . .  
2-1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
2-2 Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
2-3 PC Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
7
8
8
8
SECTION 3 – Memory Areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
3-1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
3-2 Data Area Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
3-3 Internal Relay (IR) Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
3-4 Special Relay (SR) Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
9
10  
10  
12  
21  
21  
21  
21  
21  
22  
22  
22  
22  
22  
23  
3-4-1  
3-4-2  
3-4-3  
3-4-4  
3-4-5  
3-4-6  
3-4-7  
3-4-8  
3-4-9  
Battery Alarm Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Cycle Time Error Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
High-speed Drum Counter Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Clock Pulse Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Error Flag (ER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Step Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Always OFF, Always ON Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
First Cycle Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Arithmetic Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
3-5 Data Memory (DM) Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
3-6 Holding Relay (HR) Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
3-7 Timer/Counter (TC) Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
3-8 Temporary Relay (TR) Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
23  
23  
24  
SECTION 4 – Writing and Inputting the Program . . . . . . . . . . . . . . . . . . .  
4-1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
4-2 Instruction Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
4-3 The Ladder Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
25  
26  
26  
27  
28  
28  
30  
32  
32  
32  
39  
39  
43  
4-3-1  
4-3-2  
4-3-3  
4-3-4  
4-3-5  
4-3-6  
4-3-7  
4-3-8  
4-3-9  
Basic Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Mnemonic Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Ladder Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
OUT and OUT NOT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
The END Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Logic Block Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Coding Multiple Right-hand Instructions . . . . . . . . . . . . . . . . . . . . . .  
Branching Instruction Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Jumps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
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Table of contents  
4-4 The Programming Console . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
44  
44  
45  
4-4-1  
4-4-2  
The Keyboard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
PC Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
4-5 Preparation for Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
46  
47  
47  
49  
49  
50  
51  
53  
54  
55  
57  
4-5-1  
4-5-2  
4-5-3  
Entering the Password . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Clearing Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Clearing Error Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
4-6 Inputting, Modifying, and Checking the Program . . . . . . . . . . . . . . . . . . . . . . . .  
4-6-1  
4-6-2  
4-6-3  
4-6-4  
4-6-5  
4-6-6  
Setting and Reading from Program Memory Address . . . . . . . . . . . .  
Inputting or Overwriting Programs . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Checking the Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Displaying the Cycle Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Program Searches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Inserting and Deleting Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . .  
4-7 Controlling Bit Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
59  
59  
60  
60  
61  
63  
4-7-1  
4-7-2  
4-7-3  
DIFFERENTIATE UP and DIFFERENTIATE DOWN . . . . . . . . . . .  
KEEP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Self-maintaining Bits (Seal) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
4-8 Work Bits (Internal Relays) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
4-9 Programming Precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
4-10 Program Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
65  
SECTION 5 – Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
5-1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
5-2 Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
5-3 Instruction Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
5-4 Data Areas, Definer Values, and Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
67  
68  
68  
68  
69  
69  
73  
73  
74  
75  
75  
5-4-1  
Coding Other Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
5-5 Ladder Diagram Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
5-5-1  
5-5-2  
LOAD, LOAD NOT, AND, AND NOT, OR, and OR NOT . . . . . . . .  
AND LOAD and OR LOAD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
5-6 Bit Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
5-6-1  
5-6-2  
OUTPUT and OUTPUT NOT – OUT and OUT NOT . . . . . . . . . . . .  
DIFFERENTIATE UP and DIFFERENTIATE DOWN –  
DIFU(13) and DIFD(14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
75  
77  
78  
80  
81  
81  
5-6-3  
KEEP – KEEP(11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
5-7 INTERLOCK and INTERLOCK CLEAR – IL(02) and ILC(03) . . . . . . . . . . . .  
5-8 JUMP and JUMP END – JMP(04) and JME(05) . . . . . . . . . . . . . . . . . . . . . . . . .  
5-9 END – END(01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
5-10 NO OPERATION – NOP(00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
5-11 Timer and Counter Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
82  
5-11-1  
5-11-2  
5-11-3  
5-11-4  
5-11-5  
5-11-6  
5-11-7  
TIMER – TIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
HIGH-SPEED TIMER – TIMH(15) . . . . . . . . . . . . . . . . . . . . . . . . . .  
Analog Timer Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
COUNTER – CNT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
REVERSIBLE COUNTER – CNTR(12) . . . . . . . . . . . . . . . . . . . . . .  
HIGH-SPEED DRUM COUNTER – HDM(61) . . . . . . . . . . . . . . . . .  
REVERSIBLE DRUM COUNTER – RDM(60) . . . . . . . . . . . . . . . . .  
83  
86  
87  
90  
93  
94  
103  
106  
106  
109  
110  
111  
111  
112  
112  
5-12 Data Shifting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
5-12-1  
5-12-2  
5-12-3  
SHIFT REGISTER – SFT(10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
REVERSIBLE SHIFT REGISTER – SFTR(84) . . . . . . . . . . . . . . . . .  
WORD SHIFT – WSFT(16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
5-13 Data Movement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
5-13-1  
5-13-2  
MOVE – MOV(21) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
MOVE NOT – MVN(22) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
5-14 DATA COMPARE – CMP(20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
5-15 Data Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
115  
115  
5-15-1  
BCD-TO- BINARY – BIN(23) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
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Table of contents  
5-15-2  
5-15-3  
5-15-4  
BINARY-TO-BCD – BCD(24) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
4-TO-16 DECODER – MLPX(76) . . . . . . . . . . . . . . . . . . . . . . . . . . .  
16-TO-4 ENCODER – DMPX(77) . . . . . . . . . . . . . . . . . . . . . . . . . . .  
115  
116  
118  
120  
120  
122  
123  
124  
125  
125  
126  
5-16 BCD Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
5-16-1  
5-16-2  
5-16-3  
5-16-4  
5-16-5  
5-16-6  
BCD ADD – ADD(30) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
BCD SUBTRACT – SUB(31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
BCD MULTIPLY – MUL(32) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
BCD DIVIDE – DIV(33) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
SET CARRY – STC(40) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
CLEAR CARRY – CLC(41) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
5-17 Subroutines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
5-17-1  
SUBROUTINE DEFINE and SUBROUTINE RETURN  
SBN(92)/RET(93) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
SUBROUTINE ENTRY – SBS(91) . . . . . . . . . . . . . . . . . . . . . . . . . .  
126  
126  
128  
128  
135  
135  
135  
136  
5-17-2  
5-18 Step Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
5-18-1 STEP DEFINE and STEP START – STEP(08)/SNXT(09) . . . . . . . .  
5-19 Special Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
5-19-1  
5-19-2  
5-19-3  
I/O REFRESH – IORF(97) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
END WAIT – ENDW(62) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
NOTATION INSERT – NETW(63) . . . . . . . . . . . . . . . . . . . . . . . . . .  
SECTION 6 – Program Execution Timing . . . . . . . . . . . . . . . . . . . . . . . . . .  
6-1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
6-2 Cycle Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
6-3 Calculating Cycle Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
137  
138  
139  
141  
141  
142  
143  
6-3-1  
6-3-2  
Single PC Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
PC with Additional Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
6-4 Instruction Execution Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
6-5 I/O Response Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
145  
SECTION 7 – Program Debugging and Execution . . . . . . . . . . . . . . . . . . .  
7-1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
7-2 Debugging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
7-3 Monitoring Operation and Modifying Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
147  
148  
148  
149  
150  
153  
155  
156  
157  
158  
159  
7-3-1  
7-3-2  
7-3-3  
7-3-4  
Bit/Digit Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Force Set/Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Hexadecimal/BCD Data Modification . . . . . . . . . . . . . . . . . . . . . . . .  
Changing Timer/Counter SV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
7-4 Program Backup and Restore Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
7-4-1  
7-4-2  
Saving Program Memory Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Restoring or Comparing Program Memory Data . . . . . . . . . . . . . . . .  
SECTION 8 – Troubleshooting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
8-1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
8-2 Reading and Clearing Errors and Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
8-3 Error Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
8-4 Error Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
161  
162  
162  
162  
164  
Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
A – Standard Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
B – Programming Instructions and Execution Times . . . . . . . . . . . . . . . . . . . . . . . . . . .  
C – Programming Console Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
D – Error and Arithmetic Flag Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
E – Binary–Hexadecimal–Decimal Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
F – Word Assignment Recording Sheets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
G – Program Coding Sheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
165  
165  
171  
183  
189  
191  
193  
199  
Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
201  
215  
vii  
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PRECAUTIONS  
This section provides general precautions for using the K-type Programmable Controllers (PCs) and related devices.  
The information contained in this section is important for the safe and reliable application of Programmable Control-  
lers. You must read this section and understand the information contained before attempting to set up or operate a PC  
system.  
1
2
3
4
5
Intended Audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
General Precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Safety Precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Operating Environment Precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Application Precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
x
x
x
x
xi  
ix  
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Application Precautions  
5
1
Intended Audience  
This manual is intended for the following personnel, who must also have knowl-  
edge of electrical systems (an electrical engineer or the equivalent).  
• Personnel in charge of installing FA systems.  
• Personnel in charge of designing FA systems.  
• Personnel in charge of managing FA systems and facilities.  
2
General Precautions  
The user must operate the product according to the performance specifications  
described in the operation manuals.  
Before using the product under conditions which are not described in the manual  
or applying the product to nuclear control systems, railroad systems, aviation  
systems, vehicles, combustion systems, medical equipment, amusement ma-  
chines, safety equipment, and other systems, machines, and equipment that  
may have a serious influence on lives and property if used improperly, consult  
your OMRON representative.  
Make sure that the ratings and performance characteristics of the product are  
sufficient for the systems, machines, and equipment, and be sure to provide the  
systems, machines, and equipment with double safety mechanisms.  
This manual provides information for programming and operating the Unit. Be  
sure to read this manual before attempting to use the Unit and keep this manual  
close at hand for reference during operation.  
WARNING It is extremely important that a PC and all PC Units be used for the specified  
purpose and under the specified conditions, especially in applications that can  
directly or indirectly affect human life. You must consult with your OMRON  
representative before applying a PC System to the above-mentioned  
applications.  
!
3
Safety Precautions  
WARNING Do not attempt to take any Unit apart while the power is being supplied. Doing so  
!
!
!
may result in electric shock.  
WARNING Do not touch any of the terminals or terminal blocks while the power is being  
supplied. Doing so may result in electric shock.  
WARNING Do not attempt to disassemble, repair, or modify any Units. Any attempt to do so  
may result in malfunction, fire, or electric shock.  
4
Operating Environment Precautions  
Caution Do not operate the control system in the following locations:  
!
• Locations subject to direct sunlight.  
• Locations subject to temperatures or humidity outside the range specified in  
the specifications.  
• Locations subject to condensation as the result of severe changes in tempera-  
ture.  
x
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Application Precautions  
5
• Locations subject to corrosive or flammable gases.  
• Locations subject to dust (especially iron dust) or salts.  
• Locations subject to exposure to water, oil, or chemicals.  
• Locations subject to shock or vibration.  
Caution Take appropriate and sufficient countermeasures when installing systems in the  
!
!
following locations:  
• Locations subject to static electricity or other forms of noise.  
• Locations subject to strong electromagnetic fields.  
• Locations subject to possible exposure to radioactivity.  
• Locations close to power supplies.  
Caution The operating environment of the PC System can have a large effect on the lon-  
gevity and reliability of the system. Improper operating environments can lead to  
malfunction, failure, and other unforeseeable problems with the PC System. Be  
sure that the operating environment is within the specified conditions at installa-  
tion and remains within the specified conditions during the life of the system.  
5
Application Precautions  
Observe the following precautions when using the PC System.  
WARNING Always heed these precautions. Failure to abide by the following precautions  
!
could lead to serious or possibly fatal injury.  
• Always ground the system to 100 Ω or less when installing the Units. Not con-  
necting to a ground of 100 Ω or less may result in electric shock.  
• Always turn OFF the power supply to the PC before attempting any of the fol-  
lowing. Not turning OFF the power supply may result in malfunction or electric  
shock.  
• Mounting or dismounting I/O Units, CPU Units, Memory Cassettes, or any  
other Units.  
• Assembling the Units.  
• Setting DIP switches or rotary switches.  
• Connecting cables or wiring the system.  
• Connecting or disconnecting the connectors.  
Caution Failure to abide by the following precautions could lead to faulty operation of the  
PC or the system, or could damage the PC or PC Units. Always heed these pre-  
cautions.  
!
• Fail-safe measures must be taken by the customer to ensure safety in the  
event of incorrect, missing, or abnormal signals caused by broken signal lines,  
momentary power interruptions, or other causes.  
• Interlock circuits, limit circuits, and similar safety measures in external circuits  
(i.e., not in the Programmable Controller) must be provided by the customer.  
• Always use the power supply voltages specified in the operation manuals. An  
incorrect voltage may result in malfunction or burning.  
• Take appropriate measures to ensure that the specified power with the rated  
voltage and frequency is supplied. Be particularly careful in places where the  
power supply is unstable. An incorrect power supply may result in malfunction.  
• Install external breakers and take other safety measures against short-circuit-  
ing in external wiring. Insufficient safety measures against short-circuiting may  
result in burning.  
xi  
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Application Precautions  
5
• Do not apply voltages to the Input Units in excess of the rated input voltage.  
Excess voltages may result in burning.  
• Do not apply voltages or connect loads to the Output Units in excess of the  
maximum switching capacity. Excess voltages or loads may result in burning.  
• Disconnect the functional ground terminal when performing withstand voltage  
tests. Not disconnecting the functional ground terminal may result in burning.  
• Be sure that all the mounting screws, terminal screws, and cable connector  
screws are tightened to the torque specified in the relevant manuals. Incorrect  
tightening torque may result in malfunction.  
• Leave the label attached to the Unit when wiring. Removing the label may re-  
sult in malfunction if foreign matter enters the Unit.  
• Remove the label after the completion of wiring to ensure proper heat dissipa-  
tion. Leaving the label attached may result in malfunction.  
• Use crimp terminals for wiring. Do not connect bare stranded wires directly to  
terminals. Connection of bare stranded wires may result in burning.  
• Wire all connections correctly.  
• Double-check all wiring and switch settings before turning ON the power sup-  
ply. Incorrect wiring may result in burning.  
• Be sure that the terminal blocks, Memory Units, expansion cables, and other  
items with locking devices are properly locked into place. Improper locking  
may result in malfunction.  
• Check the user program for proper execution before actually running it on the  
Unit. Not checking the program may result in an unexpected operation.  
• Confirm that no adverse effect will occur in the system before attempting any of  
the following. Not doing so may result in an unexpected operation.  
• Changing the operating mode of the PC.  
• Force-setting/force-resetting any bit in memory.  
• Changing the present value of any word or any set value in memory.  
• Resume operation only after transferring to the new CPU Unit the contents of  
the DM Area, HR Area, and other data required for resuming operation. Not  
doing so may result in an unexpected operation.  
• Do not pull on the cables or bend the cables beyond their natural limit. Doing  
either of these may break the cables.  
• Do not place objects on top of the cables or other wiring lines. Doing so may  
break the cables.  
• When replacing parts, be sure to confirm that the rating of a new part is correct.  
Not doing so may result in malfunction or burning.  
• Before touching a Unit, be sure to first touch a grounded metallic object in order  
to discharge any static built-up. Not doing so may result in malfunction or dam-  
age.  
• Install the Units properly as specified in the operation manuals. Improper  
installation of the Units may result in malfunction.  
xii  
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SECTION 1  
Background  
1-1  
1-2  
1-3  
1-4  
1-5  
1-6  
1-7  
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
2
2
3
3
4
5
6
Relay Circuits: The Roots of PC Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
PC Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
OMRON Product Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Overview of PC Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Peripheral Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Available Manuals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
1
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Relay Circuits: The Roots of PC Logic  
Section 1-2  
1-1  
Introduction  
A Programmable Controller (PC) is basically a central processing unit (CPU)  
containing a program and connected to input and output (I/O) devices (I/O  
Devices). The program controls the PC so that when an input signal from an  
input device turns ON, the appropriate response is made. The response nor-  
mally involves turning ON an output signal to some sort of output device. The  
input devices could be photoelectric sensors, pushbuttons on control panels,  
limit switches, or any other device that can produce a signal that can be input  
into the PC. The output devices could be solenoids, switches activating indi-  
cator lamps, relays turning on motors, or any other devices that can be acti-  
vated by signals output from the PC.  
For example, a sensor detecting a product passing by turns ON an input to  
the PC. The PC responds by turning ON an output that activates a pusher  
that pushes the product onto another conveyor for further processing. An-  
other sensor, positioned higher than the first, turns ON a different input to  
indicate that the product is too tall. The PC responds by turning on another  
pusher positioned before the pusher mentioned above to push the too-tall  
product into a rejection box.  
Although this example involves only two inputs and two outputs, it is typical of  
the type of control operation that PCs can achieve. Actually even this exam-  
ple is much more complex than it may at first appear because of the timing  
that would be required, i.e., “How does the PC know when to activate each  
pusher?” Much more complicated operations, however, are also possible.  
The problem is how to get the desired control signals from available inputs at  
appropriate times.  
Desired control sequences are input to the K-type PCs using a form of PC  
logic called ladder-diagram programming. This manual is written to explain  
ladder-diagram programming and to prepare the reader to program and oper-  
ate the K-type PCs.  
1-2  
Relay Circuits: The Roots of PC Logic  
PCs historically originate in relay-based control systems. And although the  
integrated circuits and internal logic of the PC have taken the place of the  
discrete relays, timers, counters, and other such devices, actual PC opera-  
tion proceeds as if those discrete devices were still in place. PC control, how-  
ever, also provides computer capabilities and consistency to achieve a great  
deal more flexibility and reliability than is possible with relays.  
The symbols and other control concepts used to describe PC operation also  
come from relay-based control and form the basis of the ladder-diagram pro-  
gramming method. Most of the terms used to describe these symbols and  
concepts, however, originated as computer terminology.  
Relay vs. PC Terminology  
The terminology used throughout this manual is somewhat different from re-  
lay terminology, but the concepts are the same. The following table shows  
the relationship between relay terms and the PC terms used for OMRON  
PCs.  
Relay term  
contact  
PC equivalent  
input or condition  
coil  
output or work bit  
NO relay  
NC relay  
normally open condition  
normally closed condition  
2
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OMRON Product Terminology  
Section 1-4  
Actually there is not a total equivalence between these terms, because the  
term condition is used only to describe ladder diagram programs in general  
and is specifically equivalent to one of certain basic instructions. The terms  
input and output are not used in programming per se, except in reference to  
I/O bits that are assigned to input and output signals coming into and leaving  
the PC. Normally open conditions and normally closed conditions are ex-  
plained in 4-3 The Ladder Diagram.  
1-3  
PC Terminology  
Although also provided in the Glossary at the back of this manual, the follow-  
ing terms are crucial to understanding PC operation and are thus explained  
here as well.  
PC  
When we refer to the PC, we are generally talking about the CPU and all of  
the Units directly controlled by it through the program. This does not include  
the I/O devices connected to PC inputs and outputs.  
If you are not familiar with the terms used above to describe a PC, refer to  
Section 2 Hardware Considerations for explanations.  
Inputs and Outputs  
A device connected to the PC that sends a signal to the PC is called an input  
device; the signal it sends is called an input signal. A signal enters the PC  
through terminals or through pins on a connector on a Unit. The place where  
a signal enters the PC is called an input point. This input point is allocated a  
location in memory that reflects its status, i.e., either ON or OFF. This mem-  
ory location is called an input bit. The CPU in its normal processing cycle  
monitors the status of all input points and turns ON and OFF corresponding  
input bits accordingly.  
There are also output bits in memory that are allocated to output points on  
Units through which output signals are sent to output devices, i.e., an out-  
put bit is turned ON to send a signal to an output device through an output  
point. The CPU periodically turns output points ON and OFF according to the  
status of the output bits.  
These terms are used when describing different aspects of PC operation.  
When programming, one is concerned with what information is held in mem-  
ory, and so I/O bits are referred to. When describing the Units that connect  
the PC to the controlled system and the places on these Units where signals  
enter and leave the PC, I/O points are referred to. When wiring these I/O  
points, the physical counterparts of the I/O points, either terminals or connec-  
tor pins, are referred to. When describing the signals that enter or leave the  
system, reference is made to input signals and output signals, or sometimes  
just inputs and outputs.  
Controlled System and  
Control System  
The Control System includes the PC and all I/O devices it uses to control an  
external system. A sensor that provides information to achieve control is an  
input device that is clearly part of the Control System. The controlled system  
is the external system that is being controlled by the PC program through  
these I/O devices. I/O devices can sometimes be considered part of the con-  
trolled system, e.g., a motor used to drive a conveyor belt.  
1-4  
OMRON Product Terminology  
OMRON products are divided into several functional groups that have ge-  
neric names. Appendix A Standard Models list products by these groups.  
The term Unit is used to refer to all OMRON PC products, depending on the  
context.  
The largest group of OMRON products is I/O Units. I/O Units come in a vari-  
ety of point quantities and specifications.  
3
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Overview of PC Operation  
Section 1-5  
Special I/O Units are dedicated Units that are designed to meet specific  
needs. These include Analog Timer Units and Analog I/O Units.  
Link Units are used to create Link Systems that link more than one PC or  
link a single PC to remote I/O points. Link Units include I/O Link Units that  
are used to connect K-type PCs to Remote I/O Systems controlled by a larg-  
er PC (e.g. C1000H) and Host Link Units.  
Other product groups include Programming Devices and Peripheral De-  
vices.  
1-5  
Overview of PC Operation  
The following are the basic steps involved in programming and operating a  
K-type PC. Assuming you have already purchased one or more of these  
PCs, you must have a reasonable idea of the required information for steps  
one and two, which are discussed briefly below. This manual is written to ex-  
plain steps three through six, eight, and nine. The section(s) of this manual  
that provide relevant information are listed with each of these steps.  
1, 2, 3... 1. Determine what the controlled system must do, in what order, and at  
what times.  
2. Determine what Units will be required. Refer to the Installation Guide. If  
a Link System is required, refer to the required System Manual(s).  
3. On paper, assign all input and output devices to I/O points on Units and  
determine which I/O bits will be allocated to each. If the PC includes  
Special I/O Units or Link Systems, refer to the individual Operation  
Manuals or System Manuals for details on I/O bit allocation. (Section 3  
Memory Areas)  
4. Using relay ladder symbols, write a program that represents the se-  
quence of required operations and their inter-relationships. Be sure to  
also program appropriate responses for all possible emergency situ-  
ations. (Section 4 Writing and Inputting the Program, Section 5 Instruc-  
tion Set, and Section 6 Program Execution Timing)  
5. Input the program and all required operating parameters into the PC.  
(Section 4 Writing and Inputting the Program)  
6. Debug the program, first to eliminate any syntax errors and then to elim-  
inate execution errors. (Section 4 Writing and Inputting the Program,  
Section 7 Program Debugging and Execution, and Section 8  
Troubleshooting)  
7. Wire the PC to the controlled system. This step can actually be started  
as soon as step 3 has been completed. Refer to the Installation Guide  
and to Operation Manuals and System Manuals for details on individual  
Units.  
8. Test the program in an actual control situation and fine tune it if required.  
(Section 7 Program Debugging and Execution and Section 8  
Troubleshooting)  
9. Record two copies of the finished program on masters and store them  
safely in different locations. (Section 7 Program Debugging and Execu-  
tion)  
Control System Design  
Designing the Control System is the first step in automating any process. A  
PC can be programmed and operated only after the overall Control System is  
fully understood. Designing the Control System requires a thorough under-  
standing of the system that is to be controlled. The first step in designing a  
Control System is thus determining the requirements of the controlled sys-  
tem.  
4
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Peripheral Devices  
Section 1-6  
Input/Output Requirements The first thing that must be assessed is the number of input and output points  
that the controlled system will require. This is done by identifying each device  
that is to send an input signal to the PC or which is to receive an output sig-  
nal from the PC. Keep in mind that the number of I/O points available de-  
pends on the configuration of the PC. Refer to 3-3 Internal Relay (IR) Area  
for details on I/O capacity and assigning I/O bits to I/O points.  
Sequence, Timing, and  
Relationships  
Next, determine the sequence in which control operations are to occur and  
the relative timing of the operations. Identify the physical relationships be-  
tween the I/O devices as well as the kinds of responses that should occur  
between them.  
For instance, a photoelectric switch might be functionally tied to a motor by  
way of a counter within the PC. When the PC receives an input from a start  
switch, it could start the motor. The PC could then stop the motor when the  
counter has received five input signals from the photoelectric switch.  
Each of the related tasks must be similarly determined, throughout the entire  
control operation.  
Unit Requirements  
The actual Units that will be mounted must be determined according to the  
requirements of the I/O devices. This will include actual hardware specifica-  
tions, such as voltage and current levels, as well as functional considera-  
tions, such as those that require Special I/O Units or Link Systems. In many  
cases, Special I/O Units or Link Systems can greatly reduce the program-  
ming burden. Details on these Units and Link Systems are available in indi-  
vidual Operation Manuals and System Manuals.  
Once the entire Control System has been designed, the task of program-  
ming, debugging, and operation as described in the remaining sections of  
this manual can begin.  
1-6  
Peripheral Devices  
The following peripheral devices can be used in programming, either to input/  
debug/monitor the PC program or to interface the PC to external devices to  
output the program or memory area data. Model numbers for all devices  
listed below are provided in Appendix A Standard Models. OMRON product  
names have been placed in bold when introduced in the following descrip-  
tions.  
Programming Console  
A Programming Console is the simplest form of programming device for OM-  
RON PCs. Although a Programming Console Adapter is sometimes re-  
quired, all Programming Consoles are connected directly to the CPU without  
requiring a separate interface. The Programming Console also functions as  
an interface to output programs to a standard cassette tape recorder.  
Various types of Programming Console are available, including both  
CPU-mounting and Handheld models. Programming Console operations are  
described later in this manual.  
Graphic Programming  
Console: GPC  
A Peripheral Interface Unit is required to interface the GPC to the PC.  
The GPC also functions as an interface to output programs directly to a stan-  
dard cassette tape recorder. A PROM Writer, Floppy Disk Interface Unit, or  
Printer Interface Unit can be directly mounted to the GPC to output pro-  
grams directly to an EPROM chip, floppy disk drive, or printing device.  
Ladder Support Software:  
LSS  
LSS is designed to run on IBM AT/XT compatibles to enable nearly all of the  
operations available on the GPC. It also offers extensive documentation ca-  
pabilities.  
5
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Available Manuals  
Section 1-7  
A Host Link Unit is required to interface a computer running LSS to the PC.  
Using an Optical Host Link Unit also enables the use of optical fiber cable to  
connect the FIT to the PC. Wired Host Link Units are available when desired.  
(Although FIT does not have optical connectors, conversion to optical fiber  
cable is possible by using Converting Link Adapters.)  
Factory Intelligent Terminal: The FIT is an OMRON computer with specially designed software that allows  
FIT  
you to perform all of the operations that are available with the GPC or LSS.  
Programs can also be output directly to an EPROM chip, floppy disk drive, or  
printing device without any additional interface units. The FIT has an EPROM  
writer and two 3.5” floppy disk drives built in.  
A Peripheral Interface Unit or Host Link Unit is required to interface the  
FIT to the PC. Using an Optical Host Link Unit also enables the use of optical  
fiber cable to connect the FIT to the PC. Wired Host Link Units are available  
when desired. (Although FIT does not have optical connectors, conversion to  
optical fiber cable is possible by using Converting Link Adapters.)  
PROM Writer  
Other than its applications described above, the PROM Writer can be  
mounted to the PC’s CPU to write programs to EPROM chips.  
Floppy Disk Interface Unit  
Other than its applications described above, the Floppy Disk Interface Unit  
can be mounted to the PC’s CPU to interface a floppy disk drive and write  
programs onto floppy disks.  
Printer Interface Unit  
Other than its applications described above, the Printer Interface Unit can be  
mounted to the PC’s CPU to interface a printer or X-Y plotter to print out pro-  
grams in either mnemonic or ladder-diagram form.  
1-7  
Available Manuals  
The following table lists other manuals that may be required to program and/  
or operate the K-type PCs. Operation Manuals and/or Operation Guides are  
also provided with individual Units and are required for wiring and other  
specifications.  
Name  
Cat. No.  
W147  
W173  
W84  
Contents  
Installation Guide  
Hardware specifications  
Data Access Console Operation Guide  
GPC Operation Manual  
Procedures for monitoring and manipulating data.  
Programming procedures for the GPC (Graphics  
Programming Console)  
FIT Operation Manual  
LSS Operation Manual  
W150  
W237  
Programming procedures for using the FIT (Factory Intelligent  
Terminal  
Programming procedures for using LSS (Ladder Support  
Software)  
Printer Interface Unit Operation Guide  
PROM Writer Operation Guide  
W107  
W155  
W119  
W136  
Procedures for interfacing a PC to a printer  
Procedures for writing programs to EPROM chips  
Procedures for interfacing a PC to a floppy disk drive  
Floppy Disk Interface Unit Operation Guide  
Optical Remote I/O System Manual  
Information on building an Optical Remote I/O System to  
enable remote I/O capability  
Host Link System Manual  
W143  
W122  
Information on building a Host Link System to manage PCs  
from a ‘host’ computer  
K-type Analog I/O Units Operation Guide  
Hardware and software information on using Analog I/O Units  
with the K-type PCs.  
6
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SECTION 2  
Hardware Considerations  
2-1  
2-2  
2-3  
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
PC Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
8
8
8
7
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PC Configuration  
Section 2-3  
2-1  
Introduction  
This section provides information on hardware aspects of K-type PCs that  
are relevant to programming and software operation. These include indica-  
tors on the CPU and basic PC configuration. This information is covered in  
detail in the Installation Guide.  
2-2  
Indicators  
CPU indicators provide visual information on the general operation of the PC.  
Using the flags and other error indicators provided in the memory data areas,  
although not a substitute for proper error programming, provides ready con-  
firmation of proper operation.  
CPU Indicators  
CPU indicators are located on the front right hand side of the PC adjacent to  
the I/O expansion slot and are described in the following table.  
Indicator  
POWER  
Function  
Lights when power is supplied to the CPU.  
Lights when the CPU is operating normally.  
RUN  
ERR  
Lights when an error is discovered in system error diagnosis  
operations. When this indicator lights, the RUN indicator will go  
off, CPU operation will be stopped, and all outputs from the PC  
will be turned OFF.  
ALARM  
Lights when an error is discovered in system error diagnosis  
operations. PC operation will continue.  
2-3  
PC Configuration  
The system must contain a K-type CPU and may additionally contain an Ex-  
pansion I/O Unit, Special I/O Units and/or I/O Link Units.  
The Expansion I/O Units are not a required part of the basic system and are  
used to increase the number of I/O points available. Special I/O Units and I/O  
Link Units are used to reduce programming complexity.  
8
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SECTION 3  
Memory Areas  
3-1  
3-2  
3-3  
3-4  
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
10  
10  
12  
21  
21  
21  
21  
21  
22  
22  
22  
22  
22  
23  
23  
23  
24  
Data Area Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Internal Relay (IR) Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Special Relay (SR) Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
3-4-1  
3-4-2  
3-4-3  
3-4-4  
3-4-5  
3-4-6  
3-4-7  
3-4-8  
3-4-9  
Battery Alarm Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Cycle Time Error Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
High-speed Drum Counter Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Clock Pulse Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Error Flag (ER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Step Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Always OFF, Always ON Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
First Cycle Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Arithmetic Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
3-5  
3-6  
3-7  
3-8  
Data Memory (DM) Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Holding Relay (HR) Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Timer/Counter (TC) Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Temporary Relay (TR) Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
9
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Data Area Structure  
Section 3-2  
3-1  
Introduction  
Various types of data are required to achieve effective and correct control. To  
facilitate managing this data, the PC is provided with various memory areas  
for data, each of which performs a different function. The areas generally ac-  
cessible by the user for use in programming are classified as data areas.  
The other memory area is the Program Memory, where the user’s program is  
actually stored.  
This section describes these areas individually and provides information that  
will be necessary to use them. The name, acronym, range, and function of  
each area are summarized in the following table. All but the last one of these  
are data areas. All memory areas are normally referred to by their acronyms.  
Area  
Acronym  
Range  
Function  
Internal Relay  
area  
IR  
Words: 00 to 18 (bits 00 to 07)  
Used to manage I/O points, control other bits,  
timers, and counters, to temporarily store data.  
Bits:  
0000 to 1807  
Special Relay  
area  
SR  
Words: 18 (bits 08 to 15) and  
19 (bits 00 to 07)  
Contains system clocks, flags, control bits, and  
status information.  
Bits:  
1808 to 1907  
Data Memory  
area  
DM  
HR  
TC  
DM 00 to DM 63  
(words only)  
Used for internal data storage and manipulation.  
Holding Relay  
area  
Words: HR 0 to HR 9  
Used to store data and to retain the data values  
when the power to the PC is turned off.  
Bits:  
HR 000 to HR 915  
Timer/Counter  
area  
TC 00 to TC 47 (TC numbers are Used to define timers and counters and to access  
used to access other information) completion flags, PV, and SV for them.  
Temporary Relay TR  
area  
TR 00 to TR 07 (bits only)  
Used to temporarily store execution conditions.  
Program Memory UM  
UM: 1,194 words.  
Contains the program executed by the CPU.  
Work Bits and Words  
When some bits and words in certain data areas are not used for their in-  
tended purpose, they can be used in programming as required to control  
other bits. Words and bits available for use in this fashion are called work bits  
and work words. Most, but not all, unused bits can be used as work bits.  
Those that can be are specified by area in the remainder of this section. Ac-  
tual application of work bits and work words is described in Section 4 Writing  
and Inputting the Program.  
Flags and Control Bits  
Some data areas contain flags and/or control bits. Flags are bits that are  
automatically turned ON and OFF to indicate status of one form or another.  
Although some flags can be turned ON and OFF by the user, most flags can  
be read only; they cannot be controlled directly.  
Control bits are bits turned ON and OFF by the user to control specific as-  
pects of operation. Any bit given a name using the word bit rather than the  
word flag is a control bit, e.g., Restart Bits are control bits.  
3-2  
Data Area Structure  
When designating a data area, the acronym for the area is always required  
for any but the IR and SR areas. Although the acronyms for the IR and SR  
areas are often given for clarity, they are not required and not input when  
programming. Any data area designation without an acronym is assumed to  
be in either the IR and SR area. Because IR and SR addresses run consecu-  
tively, the word or bit addresses are sufficient to differentiate these two areas.  
An actual data location within any data area but the TC area is designated by  
its address. The address designates the bit and/or word within the area  
where the desired data is located. The TR area consists of individual bits  
10  
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Data Area Structure  
Section 3-2  
used to store execution conditions at branching points in ladder diagrams.  
The use of TR bits is described in Section 4 Writing and Inputting the Pro-  
gram. The TC area consists of TC numbers, each of which is used for a spe-  
cific timer or counter defined in the program. Refer to 3-7 Timer/Counter (TC)  
Area for more details on TC numbers and to 5-11 Timer and Counter Instruc-  
tions for information on actual application.  
The rest of the data areas (i.e., the IR, SR, HR and DM areas) consist of  
words, each of which consists of 16 bits numbered 00 through 15 from right  
to left. IR words 00 and 01 are shown below with bit numbers. Here, the con-  
tent of each word is shown as all zeros. Bit 00 is called the rightmost bit; bit  
15, the leftmost bit.  
Bit number  
IR word 00  
IR word 01  
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Note The term least significant is often used for rightmost; the term most signifi-  
cant, for leftmost. These terms have not been used in this manual because a  
single word is often split into two or more parts, with each part used for differ-  
ent parameters or operands, sometimes even with bits in another word.  
When this is done, the rightmost bits in a word may actually be the most sig-  
nificant bits, i.e., the leftmost bits, of a value with other bits, i.e., the least sig-  
nificant bits, contained in another word.  
The DM area is accessible by word only; you cannot designate an individual  
bit within a DM word. Data in the IR, SR and HR areas is accessible either by  
bit or by word, depending on the instruction in which the data is being used.  
To designate one of these areas by word, all that is necessary is the acronym  
(if required) and the one or two-digit word address. To designate an area by  
bit, the word address is combined with the bit number as a single three- or  
four-digit address. The examples in the following table should make this  
clear. The two rightmost digits of a bit designation must indicate a bit be-  
tween 00 and 15.  
The same TC number can be used to designate either a word containing the  
present value (PV) of the timer or counter or a bit that functions as the com-  
pletion flag for the timer or counter. This is explained in more detail in 3-7  
Timer/Counter (TC) Area.  
Area  
Word designation  
Bit designation  
0015 (leftmost bit in word 00)  
1900 (rightmost bit in word 19)  
Not possible  
IR  
00  
19  
SR  
DM  
TC  
DM 10  
TC 46 (designates PV)  
TC 46 (designates completion flag)  
Data Structure  
Word data input as decimal values is stored in binary-coded decimal (BCD)  
code; word data input as hexadecimal is stored in binary form. Because each  
word contains 16 bits, each four bits of a word represents one digit: either a  
hexadecimal digit equivalent numerically to the binary bits or decimal. One  
word of data thus contains four digits, which are numbered from right to left.  
These digit numbers and the corresponding bit numbers for one word are  
shown below.  
Digit number  
3
2
1
0
Bit number  
Contents  
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
11  
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Internal Relay (IR) Area  
Section 3-3  
When referring to the entire word, the digit numbered 0 is called the right-  
most digit; the one numbered 3, the leftmost digit.  
When inputting data into data areas, it must be input in the proper form for  
the intended purpose. This is no problem when designating individual bits,  
which are merely turned ON (equivalent to a binary value of 1) or OFF (a bi-  
nary value of 0). When inputting word data, however, it is important to input it  
either as decimal or as hexadecimal, depending on what is called for by the  
instruction it is to be used for. Section 5 Instruction Set specifies when a par-  
ticular form of data is required for an instruction.  
Converting Different Forms Binary and hexadecimal can be easily converted back and forth because  
of Data  
each four bits of a binary number is numerically equivalent to one digit of a  
hexadecimal number. The binary number 0101111101011111 is converted to  
hexadecimal by considering each set of four bits in order from the right. Bi-  
nary 1111 is hexadecimal F; binary 0101 is hexadecimal 5. The hexadecimal  
equivalent would thus be 5F5F, or 24,415 in decimal (16 x 5 + 16 x 15 + 16  
x 5 + 15).  
3
2
Decimal and BCD can also be easily converted back and forth. In this case,  
each BCD digit (i.e., each four BCD bits) is numerically equivalent of the cor-  
responding decimal digit. The BCD bits 0101011101010111 are converted to  
decimal by considering each four bits from the right. Binary 0101 is decimal  
5; binary 0111 is decimal 7. The decimal equivalent would thus be 5,757.  
Note that this is not the same numeric value as the hexadecimal equivalent  
of 0101011101010111, which would be 5,757 hexadecimal, or 22,359 in deci-  
3
2
mal (16 x 5 + 16 x 7 + 16 x 5 + 7).  
Because the numeric equivalent of each four BCD binary bits must be  
equivalent to a decimal value, any four bit combination numerically greater  
then 9 cannot be used, e.g., 1011 is not allowed because it is numerically  
equivalent to 11, which cannot be expressed as a single digit in decimal nota-  
tion. The binary bits 1011 are of course allowed in hexadecimal and they are  
equivalent to the hexadecimal digit C.  
There are instructions provided to convert data in either direction between  
BCD and hexadecimal. Refer to 5-15 Data Conversion for details. Tables of  
binary equivalents to hexadecimal and BCD digits are provided in the appen-  
dices for reference.  
Decimal Points  
Decimal points are used in timers only. The least significant digit represents  
tenths of a second. All arithmetic instructions operate on integers only.  
3-3  
Internal Relay (IR) Area  
The IR area is used both to control I/O points and as work bits to manipulate  
and store data internally. It is accessible both by bit and by word. Those  
words that can be used to control I/O points are called I/O words. Bits in I/O  
words are called I/O bits.  
The number of I/O words varies between the K-type PCs. As shown, the IR  
area is comprised of three main sections. These are input words, output  
words and work words (work bits). Work bits are used in programming to ma-  
nipulate data and control other bits. IR area work bits are reset when power  
is interrupted or PC operation is stopped.  
12  
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Internal Relay (IR) Area  
Section 3-3  
The maximum number of available I/O bits is 16 (bits/word) times the number  
of I/O words. I/O bits are assigned to input or output points as described in  
Word Allocations.  
I/O Words  
If a Unit brings inputs into the PC, the bit assigned to it is an input bit; if the  
Unit sends an output from the PC, the bit is an output bit. To turn on an out-  
put, the output bit assigned to it must be turned ON. When an input turns on,  
the input bit assigned to it also turns ON. These facts can be used in the pro-  
gram to access input status and control output status through I/O bits.  
I/O bits that are not assigned to I/O points can be used as work bits, unless  
otherwise specified in Word Allocations.  
Input Bit Usage  
Input bits can directly input external signals to the PC and can be used in any  
order in programming. Each input bit can also be used in as many instruc-  
tions as required to achieve effective and proper control. They cannot be  
used in instructions that control bit status, e.g., the OUTPUT, DIFFERENTI-  
ATION UP, and KEEP instructions.  
Output Bit Usage  
Output bits are used to output program execution results and can be used in  
any order in programming. Because outputs are refreshed only once during  
each cycle (i.e. once each time the program is executed), any output bit can  
be used in only one instruction that controls its status, including OUT, OUT  
NOT, KEEP(11), DIFU(13), DIFD(14), and SFT(10). If an output bit is used in  
more than one such instruction, only the status determined by the last in-  
struction will actually be output from the PC. See 5-12-1 SHIFT REGISTER -  
SFT(10) for an example of an output bit controlled by two instructions.  
Word Allocations  
The maximum number of words available for I/O within the IR area is 10,  
numbered 00 through 09. The remaining words (10 through 18) are to be  
used for work bits. (Note that with word 18, only the bits 00 through 07 are  
available for work bits although some of the remaining bits are required for  
special purposes when RDM is used).  
The actual number of bits that can be used as I/O bits is determined by the  
model of the CPU and the PC configuration. There are different models of  
Expansion I/O Units and Special I/O Units and I/O Link Units which can be  
connected to any of the CPUs. Each CPU model provides a particular num-  
ber of I/O bits and each Expansion I/O Unit, Special I/O Unit or I/O Link Unit  
provides a particular number of I/O bits. Configuration charts for the possible  
combinations of CPUs and Units are included later in this section. Refer to  
those to determine the actual available I/O bits.  
Within CPUs the I/O input words are always even numbered and the output  
words are always odd numbered. The general rule when connecting Expan-  
sion I/O Units to CPUs is that the first available word for the Expansion I/O  
Unit (whether input or output or a combination) is one more than the last I/O  
word of the CPU. If the Expansion I/O Unit is only either input or output (and  
not both) then the I/O words provided by the Expansion I/O Unit are allocated  
consecutively and the remaining words up to word 09 may be used for work  
bits. If the Expansion I/O Unit provides both input and output words then the  
words are allocated alternatively (input words always having even numbers)  
until all I/O words provided by the Expansion I/O Unit are allocated. The re-  
maining words up to word 09 may then be used for work bits. Note that when  
a portion of an input word is not allocated to an input point then that portion  
may be used for work bits.  
13  
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Internal Relay (IR) Area  
Section 3-3  
I/O Bits Available in CPUs  
The following table shows which bits can be used as I/O bits in each of the  
K-type CPUs. Bits in the shaded areas can be used as work bits but not as  
output bits.  
Model  
Input bits  
Output bits  
Word 00  
Word 01  
00  
01  
02  
03  
04  
05  
06  
07  
08  
09  
10  
11  
00  
01  
02  
03  
04  
05  
06  
07  
08  
09  
10  
11  
12  
13  
14  
15  
C20K  
Cannot  
be  
used.  
Word 00  
Word 01  
00  
01  
02  
03  
04  
05  
06  
07  
08  
09  
10  
11  
12  
13  
14  
15  
00  
01  
02  
03  
04  
05  
06  
07  
08  
09  
10  
11  
12  
13  
14  
15  
C28K  
Word 00  
Word 02  
00  
Word 01  
Word 03  
00  
00  
01  
02  
03  
04  
05  
06  
07  
08  
09  
10  
11  
12  
13  
14  
15  
00  
01  
02  
03  
04  
05  
06  
07  
08  
09  
10  
11  
12  
13  
14  
15  
08  
09  
10  
11  
12  
13  
14  
15  
01  
02  
03  
04  
05  
06  
07  
01  
02  
03  
04  
05  
06  
07  
Cannot  
be  
used.  
C40K  
C60K  
Word 00  
Word 02  
Word 01  
Word 03  
00  
01  
02  
03  
04  
05  
06  
07  
08  
09  
10  
11  
12  
13  
14  
15  
00  
01  
02  
03  
04  
05  
06  
07  
08  
09  
10  
11  
12  
13  
14  
15  
00  
01  
02  
03  
04  
05  
06  
07  
08  
09  
10  
11  
12  
13  
14  
15  
00  
01  
02  
03  
04  
05  
06  
07  
08  
09  
10  
11  
12  
13  
14  
15  
indicates words that cannot be used for I/O,  
but can be used as work bits.  
14  
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Internal Relay (IR) Area  
Section 3-3  
I/O Bits Available in  
Expansion I/O Units  
The following table shows which bits can be used as I/O bits in each of the  
Expansion I/O Units. Bits in the shaded areas can be used as work bits but  
not as output bits. The word addresses depend on the CPU that the Expan-  
sion I/O Unit is coupled to. In all cases the first Expansion I/O Unit address  
for input and output words is one more than the last CPU address for input  
and output words. For example, the last CPU word address for a C40K CPU  
is 03 and hence the first input or output word address for any of the Expan-  
sion I/O Units coupled to a C40K CPU will be 04. In the tables below “n” is  
the last CPU word allocated as an input or output word.  
There are several models for some of the Units listed below. A blank space  
(_) in the model number indicates that any of the applicable model numbers  
could be inserted here.  
Model  
C20P  
Input bits  
Output bits  
Model  
Input bits  
Output bits  
Word (n+1)  
Word (n + 1)  
Word (n + 2)  
00  
01  
02  
03  
04  
05  
06  
07  
08  
09  
10  
11  
00  
01  
02  
03  
04  
05  
06  
07  
08  
09  
10  
11  
12  
13  
14  
15  
00  
01  
02  
03  
04  
05  
06  
07  
08  
09  
10  
11  
12  
13  
14  
15  
C16P  
-Ij-j  
Cannot  
be  
used.  
Word (n+1)  
Word (n + 2)  
Word (n + 1)  
00  
01  
02  
03  
04  
05  
06  
07  
08  
09  
10  
11  
12  
13  
14  
15  
00  
08  
09  
10  
11  
12  
13  
14  
15  
00  
01  
02  
03  
04  
05  
06  
07  
08  
09  
10  
11  
12  
13  
14  
15  
01  
02  
03  
04  
05  
06  
07  
C28P  
C40P  
C60P  
C16P  
-Oj-j  
Word (n + 3)  
00  
Word (n + 2)  
Word (n + 4)  
Word (n + 1)  
00  
Word (n+1)  
00  
01  
02  
03  
04  
05  
06  
07  
08  
09  
10  
11  
12  
13  
14  
15  
00  
08  
09  
10  
11  
12  
13  
14  
15  
00  
01  
02  
03  
04  
05  
06  
07  
08  
09  
10  
11  
12  
13  
14  
15  
01  
02  
03  
04  
05  
06  
07  
01  
02  
03  
04  
05  
06  
07  
01  
02  
03  
Cannot  
be  
used.  
C4K-Ij  
C4K-Oj  
C4K-TM  
Cannot  
be used  
Word (n + 3)  
Word (n + 2)  
Word (n + 4)  
Word (n + 1)  
Word (n+1)  
00  
08  
09  
10  
11  
12  
13  
14  
15  
00  
08  
09  
10  
11  
12  
13  
14  
15  
00  
08  
09  
10  
11  
12  
13  
14  
15  
00  
01  
02  
03  
04  
05  
06  
07  
08  
09  
10  
11  
12  
13  
14  
15  
00  
08  
09  
10  
11  
12  
13  
14  
15  
01  
02  
03  
04  
05  
06  
07  
01  
02  
03  
04  
05  
06  
07  
01  
02  
03  
04  
05  
06  
07  
01  
02  
03  
04  
05  
06  
07  
Word (n + 1)  
00  
Word (n + 2)  
00  
08  
09  
10  
11  
12  
13  
14  
15  
01  
02  
03  
01  
02  
03  
04  
05  
06  
07  
indicates words that cannot be used for I/O,  
but can be used as work bits.  
Cannot  
be used  
15  
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Internal Relay (IR) Area  
Section 3-3  
PC Configuration  
A K-type PC can be configured with a CPU Unit and one or more of the fol-  
lowing Units: Expansion I/O Units, Analog Timer Units, or an I/O Link Unit. All  
of these Units are connected in series with the CPU Unit at one end. An I/O  
Link Unit, if included, must be on the other end (meaning only one I/O Link  
Unit can be used) and an Analog Timer Unit cannot be used. The rest of the  
Units can be in any order desired.  
There is also a restriction in the number of Units which can be included. To  
compute the number of Units for this restriction, add up all of the Units count-  
ing the C40K CPU Unit, C60K CPU Unit, C40K Expansion I/O Unit and C60K  
Expansion I/O Unit as two Units each and any other Units as one Unit each.  
This total must be no more than five.  
The following table shows some of the combinations that can be used to  
achieve specific numbers of I/O points. The numbers in the table indicate the  
number of Units of that size to be used as either the CPU or Expansion I/O  
Unit; any one of the Units can be the CPU Unit. This table does not include  
the C4P or C16P Expansion I/O Units, the Analog Timer Unit, or the I/O Link  
Unit, which can be used for greater system versatility or special applications.  
Refer to the remaining tables in this section for other combinations.  
I/O points  
Count as 2  
each  
Count as 1  
each  
I/O points  
Count as 2  
each  
Count as 1  
each  
Total In Out C60j C40j C28j C20j  
Total In Out C60j C40j C28j C20j  
(32/28) (24/16) (16/12) (12/8)  
(32/28) (24/16) (16/12) (12/8)  
100  
60 40  
---  
---  
---  
---  
1
---  
1
---  
---  
---  
3
5
3
20  
28  
40  
12  
8
---  
---  
---  
---  
---  
1
1
16 12  
24 16  
---  
2
1
---  
---  
---  
1
---  
---  
2
104  
108  
60 44  
60 48  
64 44  
---  
---  
---  
1
1
---  
1
1
48  
56  
60  
28 20  
32 24  
---  
---  
---  
---  
1
2
1
---  
---  
---  
---  
1
1
4
---  
1
2
32 28  
36 24  
1
---  
---  
1
---  
---  
---  
---  
3
2
1
---  
---  
---  
3
---  
---  
112  
116  
64 48  
64 52  
68 48  
---  
---  
---  
1
4
1
2
68  
40 28  
---  
---  
---  
1
1
1
2
---  
---  
2
2
---  
2
1
76  
80  
44 32  
48 32  
---  
---  
2
1
120  
64 56  
68 52  
---  
---  
1
---  
---  
---  
3
---  
3
---  
---  
---  
1
---  
1
---  
---  
---  
---  
4
2
1
1
1
2
---  
2
124  
128  
72 52  
72 56  
---  
---  
1
---  
1
2
---  
3
---  
2
84  
88  
48 36  
---  
---  
3
---  
---  
1
1
1
1
---  
1
48 40  
52 36  
1
---  
---  
1
1
1
1
---  
3
132  
136  
140  
76 56  
76 60  
76 64  
80 60  
80 64  
80 68  
---  
1
---  
---  
---  
---  
---  
---  
4
---  
---  
1
2
1
96  
56 40  
56 44  
2
---  
5
1
---  
---  
---  
1
2
2
2
---  
1
---  
---  
---  
---  
144  
148  
3
100  
1
1
---  
1
---  
---  
2
2
1
---  
16  
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Internal Relay (IR) Area  
Section 3-3  
The tables on the following pages show the possible configurations for a  
K-type PC. Although the tables branch to show the various possibilities at  
any one point, there can be no branching in the actual PC connections. You  
can choose either branch at any point and go as far as required, i.e., you can  
break off at any point to create a smaller PC System.When implementing a  
system there is a physical restriction on the total cable length allowable. The  
sum of the lengths of all cables in the system must be limited to less than 1.2  
meters.  
The tables also show which words will be input words and which words will  
be output words. All of these are determined by the position of the Unit in the  
configuration except for the C4P and C16P Expansion I/O Units, in which  
case the model of the Unit determines whether the words are input or output.  
The symbols used in the table represent the following:  
C20K/C28K  
C20K or C28K CPU Unit  
Input  
Output  
C40K/C60K  
Output Input  
C40K or C60K CPU Unit  
Input  
Output  
C4K/C16P  
In/Output  
C4P or C16P Expansion I/O Unit  
C20P/C28P/TU/LU,  
C20P Expansion I/O Unit, C28K Expansion I/O Unit,  
Analog Timer Unit, or I/O Link Unit  
Input  
Output  
C40P/C60P  
C40P or C60P Expansion I/O Unit  
Input  
Output  
Input  
Output  
17  
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Internal Relay (IR) Area  
Section 3-3  
IR 00  
IR 01  
IR 02  
IR 03  
IR 04  
IR 05  
IR 06  
IR 07  
IR 08  
IR 09  
C20K/C28K  
Input Output  
C4K/C16P C4K/C16P C4K/C16P C4K/C16P  
In/Output In/Output In/Output In/Output  
C20P/C28P/TU/LU  
Input  
Output  
C20P/C28P/TU/LU  
C4K/C16P  
In/Output  
Input  
Output  
C20P/C28P/TU/LU  
Input  
Output  
C40P/C60P  
Output Input  
Input  
Output  
C20P/C28P/TU/LU  
Input Output  
C4K/C16P C4K/C16P  
In/Output In/Output  
C20P/C28P/TU/LU  
Input  
Output  
C20P/C28P/TU/LU  
C4K/C16P  
In/Output  
Input  
Output  
C20P/C28P/TU/LU  
Input  
Output  
C40P/C60P  
Input  
Output  
Output  
Input  
Output  
C40P/C60P  
Output Input  
C4K/C16P  
In/Output  
Input  
C20P/C28P/TU/LU  
Input Output  
C20P/C28P/TU/LU  
Input Output  
C4K/C16P C4K/C16P C4K/C16P  
In/Output In/Output In/Output  
C20P/C28P/TU/LU  
Input  
Output  
C20P/C28P/TU/LU  
C4K/C16P  
In/Output  
Input  
Input  
Output  
C20P/C28P/TU/LU  
Input  
Output  
C40P/C60P  
Output Input  
Output  
18  
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Internal Relay (IR) Area  
Section 3-3  
IR 00  
IR 01  
IR 02  
IR 03  
IR 04  
IR 05  
IR 06  
IR 07  
IR 08  
IR 09  
C20K/C28K  
C20P/C28P/TU/LU  
Input Output  
C20P/C28P/TU/LU  
Input Output  
C4K/C16P C4K/C16P  
In/Output In/Output  
Input  
Output  
C20P/C28P/TU/LU  
Input Output  
C20P/C28P/TU/LU  
C4K/C16P  
In/Output  
Input  
Output  
C20P/C28P/TU/LU  
Input  
Output  
C40P/C60P  
Input  
Output  
Output  
Input  
Output  
C40P/C60P  
Output Input  
C4K/C16P  
In/Output  
Input  
C20P/C28P/TU/LU  
Input Output  
C40P/C60P  
Output Input  
C4K/C16P C4K/C16P  
In/Output In/Output  
Input  
Output  
C20P/C28P/TU/LU  
Input  
Output  
C20P/C28P/TU/LU  
C4K/C16P  
In/Output  
Input  
Input  
Output  
C20P/C28P/TU/LU  
Input  
Output  
C40P/C60P  
Output Input  
Output  
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Internal Relay (IR) Area  
Section 3-3  
IR 00  
Input  
IR 01  
IR 02  
Input  
IR 03  
IR 04  
IR 05  
IR 06  
IR 07  
IR 08  
IR 09  
C40K/C60K  
C4K/C16P C4K/C16P C4K/C16P  
In/Output In/Output In/Output  
Output  
Output  
C20P/C28P/TU/LU  
Input  
Output  
C4K/C16P  
In/Output  
C20P/C28P/TU/LU  
Input  
Output  
C20P/C28P/TU/LU  
Input  
Output  
C40P/C60P  
Output Input  
Input  
Output  
C20P/C28P/TU/LU  
Input Output  
C4K/C16P C4K/C16P  
In/Output In/Output  
C20P/C28P/TU/LU  
Input Output  
C20P/C28P/TU/LU  
Input Output  
C4K/C16P  
In/Output  
C40K/C60K  
Output Input  
C20P/C28P/TU/LU  
Input Output  
C20P/C28P/TU/LU  
C20P/C28P/TU/LU  
Input  
Output  
Input  
Output  
Input  
Output  
C40P/C60P  
Input  
Output  
Output  
Input  
Output  
C40P/C60P  
Output Input  
C4K/C16P  
In/Output  
Input  
C20P/C28P/TU/LU  
Input Output  
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Special Relay (SR) Area  
Section 3-4  
3-4  
Special Relay (SR) Area  
The SR area contains flags and control bits used for monitoring system op-  
eration, accessing clock pulses, and signalling errors. SR area word ad-  
dresses range from 18 through 19; bit addresses, from 1804 through 1907.  
The following table lists the functions of SR area flags and control bits. Most  
of these bits are described in more detail following the table.  
Unless otherwise stated, flags are OFF until the specified condition arises,  
when they are turned ON. Bits 1903 to 1907 are turned OFF when END is  
executed at the end of each program cycle, and thus cannot be monitored on  
the Programming Console. Other control bits are OFF until set by the user.  
Word  
Bit  
Function  
18  
04  
05  
06  
07  
08  
09  
10  
11  
12  
13  
14  
15  
00  
01  
02  
03  
04  
05  
06  
07  
RDM(60) Reset Bit  
RDM(60) Count Input Bit  
RDM(60) Up/Down Selection Bit  
HDM(61) Reset Bit  
Battery Alarm flag  
Cycle Time Error flag  
High Speed Counter Reset  
Step flag  
Always OFF flag  
Always ON flag  
Always OFF flag  
First Cycle flag  
19  
0.1-second Clock Pulse  
0.2-second Clock Pulse  
1-second Clock Pulse  
Error (ER) flag  
Carry (CY) flag  
Greater Than (GR) flag  
Equals (EQ) flag  
Less Than (LE) flag  
3-4-1  
3-4-2  
Battery Alarm Flag  
SR bit 1808 turns ON if the voltage of the CPU backup battery drops. A volt-  
age drop can be indicated by connecting the output of this bit to an external  
indicating device such as a LED. This bit can be used in programming to acti-  
vate an external warning for a low battery.  
Cycle Time Error Flag  
SR bit 1809 turns ON if the cycle time exceeds 100 ms. This bit is turned ON  
when the cycle time is between 100 and 130 ms. The PC will still operate but  
timing may become inaccurate. The PC will stop operating if the execution  
time exceeds 130 ms.  
3-4-3  
3-4-4  
High-speed Drum Counter Reset  
SR bit 1810 turns ON for one cycle time when the hard reset signal (input  
0001) is turned ON.  
Clock Pulse Bits  
Three clock pulses are available to control program timing. Each clock pulse  
bit is ON for the first half of the rated pulse time, then OFF for the second  
half. In other words, each clock pulse has a duty factor of 50%.  
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Special Relay (SR) Area  
Section 3-4  
These clock pulse bits are often used with counter instructions to create tim-  
ers. Refer to 5-11 Timer and Counter Instructions for an example of this.  
Pulse width  
Bit  
0.1 s  
1900  
0.2 s  
1901  
1.0 s  
1902  
Bit 1900  
0.1-s clock pulse  
Bit 1901  
0.2-s clock pulse  
.05 s  
.05 s  
0.1 s  
0.1 s  
0.1 s  
0.2 s  
Bit 1902  
1.0-s clock pulse  
0.5 s  
0.5 s  
1.0 s  
Caution Because the 0.1-second clock pulse bit has an ON time of 50 ms, the CPU may  
!
not be able to accurately read the pulses if program execution time is too long.  
3-4-5  
Error Flag (ER)  
SR bit 1903 turns ON when the results of an arithmetic operation is not out-  
put in BCD or the value of the BIN data processed by the BIN to BCD or BCD  
to BIN conversion instruction exceeds 9999. When the ER flag is ON the cur-  
rent instruction is not executed.  
3-4-6  
3-4-7  
Step Flag  
SR bit 1811 turns ON for one cycle when single-step execution is started with  
the STEP instruction.  
Always OFF, Always ON Flags  
SR bits 1812 and 1814 are always OFF and 1813 is always ON. By connect-  
ing these bits to external indicating devices such as a LED they can be used  
to monitor the PC’s operating status.  
3-4-8  
3-4-9  
First Cycle Flag  
SR bit 1815 turns ON when program execution starts and turns OFF after  
one cycle.  
Arithmetic Flags  
The following flags are used in data shifting, arithmetic calculation, and com-  
parison instructions. They are generally referred to only by their two-letter  
abbreviations. Refer to 5-12 Data Shifting, 5-14 DATA COMPARE - CMP(20)  
and 5-16 BCD Calculations for details.  
Caution These flags are all reset when END is executed, and therefore cannot be moni-  
!
tored from a Programming Device.  
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Timer/Counter (TC) Area  
Section 3-7  
Carry Flag, CY  
SR bit 1904 turns ON when there is a carry in the result of an arithmetic op-  
eration. The content of CY is also used in some arithmetic operations, e.g., it  
is added or subtracted along with other operands. This flag can be set and  
cleared from the program using the SET CARRY and CLEAR CARRY in-  
structions. Use CLC before any instruction using CY unless the current con-  
tent of CY is required.  
Greater Than Flag, GR  
SR bit 1905 turns ON when the result of a comparison shows the second of  
two 4-digit operands to be greater than the first.  
SR bit 1906 turns ON when the result of a comparison shows two operands  
to be equal or when the result of an arithmetic operation is zero.  
Equal Flag, EQ  
Less Than Flag, LE  
SR bit 1907 turns ON when the result of a comparison shows the second of  
two 4-digit operands to be less than the first.  
Note Remember that the previous four flags, CY, GR, EQ, and LE, are cleared by  
the END instruction.  
3-5  
Data Memory (DM) Area  
The DM area is used for internal data storage and manipulation and is acces-  
sible only by word. Addresses range from DM 00 through DM 63.  
Although composed of 16 bits just like any other word in memory, DM words  
cannot be specified by bit for use in instructions with bit-size operands, such  
as LD, OUT, AND, and OR.  
When the RDM (REVERSIBLE DRUM COUNTER) is used the DM area  
words 00 to 31 are used as the area where the upper and lower limits of the  
counter are preset and as such these words cannot be used for any other  
purposes.  
When the HDM (HIGH-SPEED DRUM COUNTER) is used the DM area  
words 32 to 63 are used as the area where the upper and lower limits of the  
counter are preset and as such these words cannot be used for any other  
purposes.  
The DM area retains status during power interruptions.  
3-6  
3-7  
Holding Relay (HR) Area  
The HR area is used to store and manipulate various kinds of data and can  
be accessed either by word or by bit. Word addresses range from HR 0  
through HR 9; bit addresses, from HR 000 through HR 915. HR bits can be  
used in any order required and can be programmed as often as required.  
The HR area retains status when the system operating mode is changed, or  
when power is interrupted.  
Timer/Counter (TC) Area  
The TC area is used to create and program timers and counters and holds  
the completion flags, set values (SV), and present values (PV) for all timers  
and counters. All of these are accessed through TC numbers ranging from  
TC 00 through TC 47. Each TC number is defined as either a timer or  
counter using one of the following instructions: TIM, TIMH, CNT or CNTR. No  
prefix is required when using a TC number in a timer or counter instruction.  
23  
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Temporary Relay (TR) Area  
Section 3-8  
Once a TC number has been defined using one of these instructions, it can-  
not be redefined elsewhere in the program using the same or a different in-  
struction. If the same TC number is defined in more than one of these in-  
structions or in the same instruction twice, an error will be generated during  
the program check. There are no restrictions on the order in which TC num-  
bers can be used.  
Once defined, a TC number can be designated as an operand in one or more  
instructions other than those listed above. When defined as a timer, a TC  
number designated as an operand takes a TIM prefix. The TIM prefix is used  
regardless of the timer instruction that was used to define the timer. Once  
defined as a counter, the TC number designated as an operand takes a CNT  
prefix. The CNT is also used regardless of the counter instruction that was  
used to define the counter.  
TC numbers can be designated for operands that require bit data or for oper-  
ands that require word data. When designated as an operand that requires  
bit data, the TC number accesses the completion flag of the timer or counter.  
When designated as an operand that requires word data, the TC number ac-  
cesses a memory location that holds the PV of the timer or counter.  
TC numbers are also used to access the SV of timers and counters from a  
Programming Device. The procedures for doing so from the Programming  
Console are provided in 7-3 Monitoring Operation and Modifying Data.  
The TC area retains the SVs of both timers and counters during power inter-  
ruptions. The PVs of timers are reset when PC operation is begun and when  
reset in interlocked program sections. Refer to 5-7 INTERLOCK AND INTER-  
LOCK CLEAR - IL(02) and ILC(03) for details on timer and counter operation  
in interlocked program sections. The PVs of counters are not reset at these  
times.  
Note that in programming “TIM 00” is used to designate three things: the  
TIMER instruction defined with TC number 00, the completion flag for this  
timer, and the PV of this timer. The meaning in context should be clear, i.e.,  
the first is always an instruction, the second is always a bit, and the third is  
always a word. The same is true of all other TC numbers prefixed with TIM or  
CNT. In explanations of ladder diagrams, the completion flag and PV ac-  
cessed through a TC number are generally called the completion flag or the  
PV of the instruction (e.g., the completion flag of TIM 00 is the completion  
flag accessed through TC number 00, which has been defined using TIM).  
When the RDM (REVERSIBLE DRUM COUNTER) is used, TC 46 is used as  
the present value storage area of the counter and thus cannot be used for  
any other purpose.  
When the HDM (HIGH-SPEED DRUM COUNTER) is used, TC 47 is used as  
the present value storage area of the counter and thus cannot be used for  
any other purpose.  
3-8  
Temporary Relay (TR) Area  
The TR area provides eight bits that are used only with the LD and OUT in-  
structions to enable certain types of branching ladder diagram programming.  
The use of TR bits is described in Section 4 Writing and Inputting the Pro-  
gram.  
TR addresses range from TR 0 though TR 7. Each of these bits can be used  
as many times as required and in any order required as long as the same TR  
bit is not used twice in the same instruction block.  
24  
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SECTION 4  
Writing and Inputting the Program  
4-1  
4-2  
4-3  
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Instruction Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
The Ladder Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
26  
26  
27  
28  
28  
30  
32  
32  
32  
39  
39  
43  
44  
44  
45  
46  
47  
47  
49  
49  
50  
51  
53  
54  
55  
57  
59  
59  
60  
60  
61  
63  
65  
4-3-1  
4-3-2  
4-3-3  
4-3-4  
4-3-5  
4-3-6  
4-3-7  
4-3-8  
4-3-9  
Basic Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Mnemonic Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Ladder Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
OUT and OUT NOT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
The END Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Logic Block Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Coding Multiple Right-hand Instructions . . . . . . . . . . . . . . . . . . . . . . .  
Branching Instruction Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Jumps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
4-4  
4-5  
The Programming Console . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
4-4-1  
4-4-2  
The Keyboard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
PC Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Preparation for Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
4-5-1  
4-5-2  
4-5-3  
Entering the Password . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Clearing Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Clearing Error Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
4-6  
4-7  
Inputting, Modifying, and Checking the Program . . . . . . . . . . . . . . . . . . . . . . . . .  
4-6-1  
4-6-2  
4-6-3  
4-6-4  
4-6-5  
4-6-6  
Setting and Reading from Program Memory Address . . . . . . . . . . . . .  
Inputting or Overwriting Programs . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Checking the Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Displaying the Cycle Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Program Searches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Inserting and Deleting Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Controlling Bit Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
4-7-1  
4-7-2  
4-7-3  
DIFFERENTIATE UP and DIFFERENTIATE DOWN . . . . . . . . . . . .  
KEEP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Self-maintaining Bits (Seal) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
4-8  
4-9  
Work Bits (Internal Relays) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Programming Precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
4-10 Program Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
25  
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Instruction Terminology  
Section 4-2  
4-1  
Introduction  
This section explains how to convert ladder diagrams to mnemonic code and  
input them into the PC. It then describes the basic steps and concepts in-  
volved in programming and introduces the instructions used to build the basic  
structure of the ladder diagram and control its execution. The entire set of  
instructions used in programming is described in Section 5 Instruction Set.  
There are several basic steps involved in writing a program.  
1, 2, 3... 1. Obtain a list of all I/O devices and the I/O points that have been as-  
signed to them and prepare a table that shows the I/O bit allocated to  
each I/O device.  
2. If the PC has any Units, i.e. Analog Timer Units, Host Link Units , and  
I/O Link Units that are allocated words in data areas other than the IR  
area or are allocated IR words in which the function of each bit is speci-  
fied by the Unit, prepare similar tables to show what words are used for  
which Units and what function is served by each bit within the words.  
3. Determine what words are available for work bits and prepare a table in  
which you can allocate these as you use them.  
4. Also prepare tables of TC numbers and jump numbers so that you can  
allocate these as you use them. Remember, the function of a TC num-  
ber can be defined only once within the program; jump numbers 01  
through 08 can be used only once each. (TC numbers are described in  
5-11 Timer and Counter Instructions; jump numbers are described later  
in this section.)  
5. Draw the ladder diagram.  
6. Input the program into the CPU. When using the Programming Console,  
this will involve converting the program to mnemonic form.  
7. Check the program for syntax errors and correct these.  
8. Execute the program to check for execution errors and correct these.  
9. After the entire Control System has been installed and is ready for use,  
execute the program and fine tune it if required.  
The basics of writing the ladder diagram and inputting it into memory are de-  
scribed in the rest of this section. Debugging and monitoring operation of the  
program are described in Section 7 Program Debugging and Execution. Sec-  
tion 8 Troubleshooting also provides information required for debugging.  
This section provides the procedures for inputting and debugging a program  
and monitoring and controlling the PC through a Programming Console. The  
Programming Console is the most commonly used Programming Device for  
the K-type PCs. It is compact and available both in handheld models or  
CPU-mounted models. Refer to Appendix A Standard Models for model num-  
bers and other details.  
If you are using a GPC, FIT, or a computer running LSS, refer to the Opera-  
tion Manual for corresponding procedures on these.  
4-2  
Instruction Terminology  
There are basically two types of instructions used in ladder diagram program-  
ming: instructions that correspond to conditions on the ladder diagram and  
are used in instruction form only when converting a program to mnemonic  
code and instructions that are used on the right side of the ladder diagram  
and are executed according to the conditions on the instruction lines leading  
to them.  
26  
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The Ladder Diagram  
Section 4-3  
Most instructions have at least one or more operands associated with them.  
Operands indicate or provide the data on which an instruction is to be per-  
formed. These are sometimes input as the actual numeric values, but are  
usually the addresses of data area words or bits that contain the data to be  
used. For instance, a MOVE instruction that has IR 00 designated as the  
source operand will move the contents of IR 00 to some other location. The  
other location is also designated as an operand. A bit whose address is des-  
ignated as an operand is called an operand bit; a word whose address is  
designated as an operand is called an operand word.  
Other terms used in describing instructions are introduced in Section 5 In-  
struction Set.  
4-3  
The Ladder Diagram  
A ladder diagram consists of one line running down the left side with lines  
branching off to the right. The line on the left is called the bus bar; the  
branching lines, instruction lines or rungs. Along the instruction lines are  
placed conditions that lead to other instructions on the right side. The logical  
combinations of these conditions determine when and how the instructions at  
the right are executed. A simple ladder diagram is shown below.  
0000 0315  
0001  
1208  
HR 109  
1203  
1200  
1201  
Instruction  
0501  
0502  
0503  
0504  
0100 0002  
0010  
0003 HR 510  
0007 TC 01  
0515  
0403  
0405  
Instruction  
1001  
1005  
1002  
0011  
1007  
As shown in the diagram above, instruction lines can branch apart and they  
can join back together. The vertical pairs of lines are called conditions. Con-  
ditions without diagonal lines through them are called normally open condi-  
tions and correspond to a LOAD, AND, or OR instruction. The conditions with  
diagonal lines through them are called normally closed conditions and corre-  
spond to a LOAD NOT, AND NOT, or OR NOT instruction. The number  
above each condition indicates the operand bit for the instruction. It is the  
status of the bit associated with each condition that determine the execution  
condition for following instructions. The function of each of the instructions  
that correspond to a condition is described below. Before we consider these,  
however, there are some basic terms that must be explained.  
Note When displaying ladder diagrams with a GPC, a FIT, or LSS, a second bus  
bar will be shown on the right side of the ladder diagram and will be con-  
nected to all instructions on the right side. This does not change the ladder  
diagram program in any functional sense. No conditions can be placed be-  
tween the instructions on the right side and the right bus bar, i.e., all instruc-  
tions on the right must be connected directly to the right bus bar. Refer to the  
GPC, FIT, or LSS Operation Manual for details.  
27  
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The Ladder Diagram  
Section 4-3  
4-3-1  
Basic Terms  
Normally Open and  
Normally Closed  
Conditions  
Each condition in a ladder diagram is either ON or OFF depending on the  
status of the operand bit that has been assigned to it. A normally open condi-  
tion is ON if the operand bit is ON; OFF if the operand bit is OFF. An normally  
closed condition is ON if the operand bit is OFF; OFF if the operand bit is  
ON. Generally speaking, you use a normally open condition when you want  
something to happen when a bit is ON and an normally closed condition  
when you want something to happen when a bit is OFF.  
0000  
Instruction is executed  
Instruction  
when IR 0000 is ON.  
Normally open condition  
0000  
Instruction is executed  
Instruction  
when IR 0000 is OFF.  
Normally closed condition  
Execution Conditions  
In ladder diagram programming, the logical combination of ON and OFF con-  
ditions before an instruction determines the compound condition under which  
the instruction is executed. This condition, which is either ON or OFF, is  
called the execution condition for the instruction. All instructions except for  
LOAD instructions have execution conditions.  
Operand Bits  
The operands designated for any of the ladder instructions can be any bit in  
the IR, SR, HR or TC area. This means that the conditions in a ladder dia-  
gram can be determined by I/O bits, flags, work bits, timers/counters, etc.  
LOAD and OUTPUT instructions can also use TR area bits, but they do so  
only in special applications.  
Logic Blocks  
What conditions correspond to what instructions is determined by the rela-  
tionship between the conditions established by the instruction lines that con-  
nect them. Any group of conditions that go together to create a logic result is  
called a logic block. Although ladder diagrams can be written without actually  
analyzing individual logic blocks, understanding logic blocks is necessary for  
efficient programming and is essential when programs are to be input in mne-  
monic code.  
4-3-2  
Mnemonic Code  
The ladder diagram cannot be directly input into the PC via a Programming  
Console; a GPC, a FIT, or LSS is required. To input from a Programming  
Console, it is necessary to convert the ladder diagram to mnemonic code.  
The mnemonic code provides exactly the same information as the ladder dia-  
gram, but in a form that can be typed directly into the PC. Actually you can  
program directly in mnemonic code, although it in not recommended for be-  
ginners or for complex programs. Also, regardless of the Programming De-  
vice used, the program is stored in memory in mnemonic form, making it im-  
portant to understand mnemonic code.  
Because of the importance of the Programming Console as a peripheral de-  
vice and because of the importance of mnemonic code in complete under-  
standing of a program, we will introduce and describe the mnemonic code  
along with the ladder diagram. Remember, you will not need to use the mne-  
monic code if you are inputting via a GPC, a FIT, or LSS (although you can  
use it with these devices too, if you prefer).  
28  
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The Ladder Diagram  
Section 4-3  
Program Memory Structure The program is input into addresses in Program Memory. Addresses in Pro-  
gram Memory are slightly different to those in other memory areas because  
each address does not necessarily hold the same amount of data. Rather,  
each address holds one instruction and all of the definers and operands (de-  
scribed in more detail later) required for that instruction. Because some in-  
structions require no operands, while others require up to three operands,  
Program Memory addresses can be from one to four words long.  
Program Memory addresses start at 0000 and run until the capacity of Pro-  
gram Memory has been exhausted. The first word at each address defines  
the instruction. Any definers used by the instruction are also contained in the  
first word. Also, if an instruction requires only a single bit operand (with no  
definer), the bit operand is also programmed on the same line as the instruc-  
tion. The rest of the words required by an instruction contain the operands  
that specify what data is to be used. When converting to mnemonic code, all  
but ladder diagram instructions are written in the same form, one word to a  
line, just as they appear in the ladder diagram symbols. An example of mne-  
monic code is shown below. The instructions used in it are described later in  
the manual.  
Address Instruction  
Operands  
HR 001  
0000  
0001  
0002  
0003  
0004  
0005  
0006  
LD  
AND  
0001  
0002  
0200  
0201  
0102  
OR  
LD NOT  
AND  
AND LD  
MOV(21)  
00  
00  
DM  
0007  
CMP(20)  
DM  
HR  
00  
0
0008  
0009  
0010  
LD  
0205  
0101  
OUT  
MOV(21)  
DM  
DM  
00  
05  
0011  
0012  
0013  
DIFU(13)  
AND  
0002  
0005  
0103  
OUT  
The address and instruction columns of the mnemonic code table are filled in  
for the instruction word only. For all other lines, the left two columns are left  
blank. If the instruction requires no definer or bit operand, the operand col-  
umn is left blank for first line. It is a good idea to cross through any blank  
data column spaces (for all instruction words that do not require data) so that  
the data column can be quickly cycled to see if any addresses have been left  
out.  
When programming, addresses are automatically displayed and do not have  
to be input unless for some reason a different location is desired for the in-  
struction. When converting to mnemonic code, it is best to start at Program  
Memory address 0000 unless there is a specific reason for starting else-  
where.  
29  
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The Ladder Diagram  
Section 4-3  
4-3-3  
Ladder Instructions  
The ladder instructions are those that correspond to the conditions on the  
ladder diagram. Ladder instructions, either independently or in combination  
with the logic block instructions described next, form the execution conditions  
upon which all other instructions are executed.  
LOAD and LOAD NOT  
The first condition that starts any logic block within a ladder diagram corre-  
sponds to a LOAD or LOAD NOT instruction.  
0000  
Address Instruction  
Operands  
0000  
A LOAD instruction.  
0000  
0001  
0002  
0003  
LD  
Instruction  
LD NOT  
Instruction  
0000  
0000  
A LOAD NOT instruction.  
When this is the only condition on the instruction line, the execution condition  
for the instruction at the right is ON when the condition is ON. For the LOAD  
instruction (i.e., a normally open condition), the execution condition would be  
ON when IR 0000 was ON; for the LOAD NOT instruction (i.e., an normally  
closed condition), it would be ON when IR 0000 was OFF.  
AND and AND NOT  
When two or more conditions lie in series on the same instruction line, the  
first one corresponds to a LOAD or LOAD NOT instruction; the rest of the  
conditions, to AND or AND NOT instructions. The following example shows  
three conditions which correspond in order from the left to a LOAD, an AND  
NOT, and an AND instruction.  
0000  
0100  
HR 000  
Address Instruction  
Operands  
0000  
Instruction  
0000  
0001  
0002  
0003  
LD  
AND NOT  
AND  
0100  
000  
HR  
Instruction  
The instruction at the right would have an ON execution condition only when  
all three conditions are ON, i.e., when IR 0000 was ON, IR 0100 was OFF,  
and HR 000 was ON.  
Actually, AND instructions can be considered individually in series, each of  
which would take the logical AND between the execution condition (i.e., the  
sum of all conditions up to that point) and the status of the AND instruction’s  
operand bit. If both of these were ON, an ON execution condition would be  
produced for the next instruction. The execution condition for the first AND  
instruction in a series would be the first condition on the instruction line.  
Each AND NOT instruction in a series would take the logical AND between  
its execution condition and the inverse of its operand bit.  
30  
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The Ladder Diagram  
Section 4-3  
OR and OR NOT  
When two or more conditions lie on separate instruction lines running in par-  
allel and then joining together, the first condition corresponds to a LOAD or  
LOAD NOT instruction; the rest of the conditions correspond to OR or OR  
NOT instructions. The following example shows three conditions which corre-  
spond in order from the top to a LOAD NOT, an OR NOT, and an OR instruc-  
tion.  
0000  
0100  
Address Instruction  
Operands  
0000  
Instruction  
0000  
0001  
0002  
0003  
LD  
OR NOT  
OR  
0100  
000  
HR  
HR 000  
Instruction  
The instruction at the right would have an ON execution condition when any  
one of the three conditions was ON, i.e., when IR 0000 was OFF, when IR  
0100 was OFF, or when HR 000 was ON.  
OR and OR NOT instructions can also be considered individually, each tak-  
ing the logical OR between its execution condition and the status of the OR  
instruction’s operand bit. If either one of these were ON, an ON execution  
condition would be produced for the next instruction.  
Combining AND and OR  
Instructions  
When AND and OR instructions are combined in more complicated dia-  
grams, they can sometimes be considered individually, with each instruction  
performing a logic operation on the execution condition and the status of the  
operand bit. The following is one example.  
0000  
0200  
0001  
0002  
0003  
Address Instruction  
Operands  
0000  
Instruction  
0000  
0001  
0002  
0003  
0004  
0005  
LD  
AND  
0001  
0200  
0002  
0003  
OR  
AND  
AND NOT  
Instruction  
Here, an AND is taken between the status of 0000 and that of 0001 to deter-  
mine the execution condition for an OR with the status of 0200. The result of  
this operation determines the execution condition for an AND with the status  
of 0002, which in turn determines the execution condition for an AND with the  
inverse of the status of 0003. In more complicated diagrams, however, it is  
necessary to consider logic blocks before an execution condition can be de-  
termined for the final instruction, and that’s where AND LOAD and OR LOAD  
instructions are used.  
31  
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The Ladder Diagram  
Section 4-3  
4-3-4  
OUT and OUT NOT  
The OUT and OUT NOT instructions are used to control the status of the  
designated operand bit according to the execution condition. With the OUT  
instruction, the operand bit will be turned ON as long as the execution condi-  
tion is ON and will be turned OFF as long as the execution condition is OFF.  
With the OUT NOT instruction, the operand bit will be turned ON as long as  
the execution condition is OFF and turned OFF as long as the execution con-  
dition is ON. These appear as follows:  
0000  
0001  
Address Instruction  
Operands  
0000  
0100  
0100  
0000  
0001  
LD  
OUT  
Address Instruction  
Operands  
0101  
0000  
0001  
LD  
0001  
0101  
OUT NOT  
In the above examples, bit 0100 will be ON as long as 0000 is ON and bit  
0101 will be OFF as long as 0001 is ON. Here, 0000 and 0001 would be in-  
put bits and 0100 and 0101 output bits assigned to the Units controlled by  
the PC, i.e., the signals coming in through the input points assigned 0000  
and 0001 are controlling the output points assigned 0100 and 0101, respec-  
tively.  
The length of time that a bit is ON or OFF can be controlled by combining the  
OUT or OUT NOT instruction with timer instructions. Refer to Examples un-  
der 5-11-1 TIMER - TIM for details.  
4-3-5  
The END Instruction  
The last instruction in any program must be the END instruction. When the  
CPU cycles the program, it executes all instructions up to the first END in-  
struction before returning to the beginning of the program and beginning exe-  
cution again. Although an END instruction can be placed at any point in a  
program, which is sometimes done when debugging, no instructions past the  
first END instruction will be executed until it is removed.  
0000  
0001  
Instruction  
END(01)  
Program execution  
ends here.  
Address Instruction  
Operands  
0000  
0500  
0501  
0502  
0503  
LD  
AND NOT  
Instruction  
END(01)  
0001  
---  
If there is no END instruction anywhere in the program, the program will not  
be executed at all.  
4-3-6  
Logic Block Instructions  
Logic block instructions do not correspond to specific conditions on the lad-  
der diagram; rather, they describe relationships between logic blocks. The  
AND LOAD instruction logically ANDs the execution conditions produced by  
two logic blocks. The OR LOAD instruction logically ORs the execution condi-  
tions produced by two logic blocks.  
32  
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The Ladder Diagram  
Section 4-3  
AND LOAD  
Although simple in appearance, the diagram below requires an AND LOAD  
instruction.  
0000  
0001  
0002  
Address Instruction  
Operands  
0000  
Instruction  
0000  
0001  
0002  
0003  
0004  
LD  
0003  
OR  
0001  
0002  
0003  
---  
LD  
OR NOT  
AND LD  
The two logic blocks are indicated by dotted lines. Studying this example  
shows that an ON execution condition would be produced when both 1)  
either of the conditions in the left logic block was ON (i.e., when either 0000  
or 0001 was ON) and 2) either of the conditions in the right logic block was  
ON (i.e., when either 0002 was ON or 0003 was OFF).  
Analyzing the diagram in terms of instructions, the condition at 0000 would  
be a LOAD instruction and the condition below it would be an OR instruction  
between the status of 0000 and that of 0001. The condition at 0002 would be  
another LOAD instruction and the condition below this would be an OR NOT  
instruction, i.e., an OR between the status or 0002 and the inverse of the  
status of 0003. To arrive at the execution condition for the instruction at the  
right, the logical AND of the execution conditions resulting from these two  
blocks would have to be taken. AND LOAD allows us to do this. AND LOAD  
always takes an AND between the current execution condition and the last  
unused execution condition. An unused execution condition is produced by  
using the LOAD or LOAD NOT instruction for any but the first condition on an  
instruction line.  
OR LOAD  
Although we’ll not describe it in detail, the following diagram would require an  
OR LOAD instruction between the top logic block and the bottom logic block.  
An ON execution condition would be produced for the instruction at the right  
either when 0000 was ON and 0001 was OFF or when 0002 and 0003 were  
both ON.  
0000  
0002  
0001  
Address Instruction  
Operands  
0000  
Instruction  
0000  
0001  
0002  
0003  
0004  
LD  
AND NOT  
LD  
0001  
0002  
0003  
---  
0003  
AND  
OR LD  
Naturally, some diagrams will require both AND LOAD and OR LOAD instruc-  
tions.  
Logic Block Instructions in To code diagrams with logic block instructions in series, the diagram must be  
Series  
divided into logic blocks. Each block is coded using a LOAD instruction to  
code the first condition, and then AND LOAD or OR LOAD is used to logically  
combine the blocks. With both AND LOAD and OR LOAD there are two ways  
to achieve this. One is to code the logic block instruction after the first two  
blocks and then after each additional block. The other is to code all of the  
blocks to be combined, starting each block with LOAD or LOAD NOT, and  
then to code the logic block instructions which combine them. In this case,  
the instructions for the last pair of blocks should be combined first, and then  
each preceding block should be combined, working progressively back to the  
first block. Although either of these methods will produce exactly the same  
result, the second method, that of coding all logic block instructions together,  
can be used only if eight or fewer blocks are being combined, i.e., if seven or  
fewer logic block instructions are required.  
33  
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The Ladder Diagram  
Section 4-3  
The following diagram requires AND LOAD to be converted to mnemonic  
code because three pairs of parallel conditions lie in series. The two means  
of coding the programs are also shown.  
0000  
0002  
0004  
0100  
0001  
0003  
0005  
Address Instruction  
Operands  
Address Instruction  
Operands  
0000  
0001  
0002  
0003  
0004  
0005  
0006  
0007  
0008  
LD  
0000  
0000  
0001  
0002  
0003  
0004  
0005  
0006  
0007  
0008  
LD  
0000  
0001  
0002  
0003  
0004  
0005  
---  
OR NOT  
LD NOT  
OR  
0001  
0002  
0003  
---  
OR NOT  
LD NOT  
OR  
AND LD  
LD  
LD  
0004  
0005  
---  
OR  
OR  
AND LD  
AND LD  
OUT  
AND LD  
OUT  
---  
0100  
0100  
Again, with the method on the right, a maximum of eight blocks can be com-  
bined. There is no limit to the number of blocks that can be combined with  
the first method.  
The following diagram requires OR LOAD instructions to be converted to  
mnemonic code because three pairs of conditions in series lie in parallel to  
each other.  
0000 0001  
0101  
0002 0003  
0040 0005  
The first of each pair of conditions is converted to LOAD with the assigned bit  
operand and then ANDed with the other condition. The first two blocks can  
be coded first, followed by OR LOAD, the last block, and another OR LOAD,  
or the three blocks can be coded first followed by two OR LOADs. The mne-  
monic code for both methods is shown below.  
Address Instruction  
Operands  
0000  
Address Instruction  
Operands  
0000  
0000  
0001  
0002  
0003  
0004  
0005  
0006  
0007  
0008  
LD  
0000  
0001  
0002  
0003  
0004  
0005  
0006  
0007  
0008  
LD  
AND NOT  
LD NOT  
AND NOT  
OR LD  
LD  
0001  
0002  
0003  
---  
AND NOT  
LD NOT  
AND NOT  
LD  
0001  
0002  
0003  
0004  
0005  
---  
0004  
0005  
---  
AND  
AND  
OR LD  
OR LD  
OUT  
OR LD  
OUT  
---  
0101  
0101  
Again, with the method on the right, a maximum of eight blocks can be com-  
bined. There is no limit to the number of blocks that can be combined with  
the first method.  
34  
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The Ladder Diagram  
Section 4-3  
Combining AND LD and  
OR LD  
Both of the coding methods described above can also be used when using  
both AND LD and OR LD, as long as the number of blocks being combined  
does not exceed eight.  
The following diagram contains only two logic blocks as shown. It is not nec-  
essary to break block b down further, because it can coded directly using  
only AND and OR.  
0000 0001  
0002 0003  
0201  
Address Instruction  
Operands  
0000  
0101  
0000  
0001  
0002  
0003  
0004  
0005  
0006  
0007  
LD  
AND NOT  
LD  
0001  
0002  
0003  
0201  
0004  
---  
AND  
OR  
0004  
OR  
Block  
a
Block  
b
AND LD  
OUT  
0101  
Although the following diagram is similar to the one above, block b in the dia-  
gram below cannot be coded without being broken down into two blocks  
combined with OR LD. In this example, the three blocks have been coded  
first and then OR LD has been used to combine the last two blocks followed  
by AND LD to combine the execution condition produced by the OR LD with  
the execution condition of block a.  
When coding the logic block instructions together at the end of the logic  
blocks they are combining, they must, as shown below, be coded in reverse  
order, i.e., the logic block instruction for the last two blocks is coded first, fol-  
lowed by the one to combine the execution condition resulting from the first  
logic block instruction and the execution condition of the logic block third from  
the end, and on back to the first logic block that is being combined.  
Block  
b1  
Address Instruction  
Operands  
0000  
0000  
0001  
0002  
0003  
0004  
0005  
0006  
0007  
0008  
LD NOT  
AND  
0000 0001  
0002 0003  
0102  
0001  
0002  
0003  
0004  
0202  
---  
LD  
0004 0202  
AND NOT  
LD NOT  
AND  
Block  
b2  
OR LD  
AND LD  
OUT  
---  
Block  
a
Block  
b
0102  
Complicated Diagrams  
When determining what logic block instructions will be required to code a dia-  
gram, it is sometimes necessary to break the diagram into large blocks and  
then continue breaking the large blocks down until logic blocks that can be  
coded without logic block instructions have been formed. These blocks are  
then coded, combining the small blocks first, and then combining the larger  
blocks. AND LD and OR LD is used to combine either, i.e., AND LD or OR  
LD always combines the last two execution conditions that existed, regard-  
less of whether the execution conditions resulted from a single condition,  
from logic blocks, or from previous logic block instructions.  
When working with complicated diagrams, blocks will ultimately be coded  
starting at the top left and moving down before moving across. This will gen-  
erally mean that, when there might be a choice, OR LD will be coded before  
AND LD.  
35  
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The Ladder Diagram  
Section 4-3  
The following diagram must be broken down into two blocks and each of  
these then broken into two blocks before it can be coded. As shown below,  
blocks a and b require an AND LD. Before AND LD can be used, however,  
OR LD must be used to combine the top and bottom blocks on both sides,  
i.e., to combine a1 and a2; b1 and b2.  
Block  
a1  
Block  
b1  
0000 0001  
0004 0005  
0103  
0002 0003  
0006 0007  
Block  
a2  
Block  
b2  
Block  
a
Block  
b
Address Instruction  
Operands  
0000  
0000  
0001  
0002  
0003  
0004  
0005  
0006  
0007  
0008  
0009  
0010  
0011  
LD  
AND NOT  
LD NOT  
AND  
0001  
0002  
0003  
---  
OR LD  
LD  
Blocks a1 and a2  
0004  
0005  
0006  
0007  
---  
AND  
LD  
AND  
OR LD  
AND LD  
OUT  
Blocks b1 and b2  
Blocks a and b  
---  
0103  
This type of diagram can be coded easily if each block is worked with in or-  
der first top to bottom and then left to right. In the following diagram, blocks a  
and b would be combined with AND LD as shown above, and then block c  
would be coded and a second AND LD would be used to combine it with the  
execution condition from the first AND LD, and so on through to block n.  
00  
Block  
a
Block  
b
Block  
c
Block  
n
36  
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The Ladder Diagram  
Section 4-3  
The following diagram requires first an OR LD and an AND LD to code the  
top of the three blocks, and then two more OR LDs to complete the mne-  
monic code.  
0000  
0001  
Address Instruction  
Operands  
0000  
0105  
0000  
0001  
0002  
0003  
0004  
0005  
0006  
0007  
0008  
0009  
0010  
0011  
0012  
LD  
0002  
0003  
LD  
0001  
0002  
0003  
---  
LD  
0004  
0006  
0005  
AND NOT  
OR LD  
AND LD  
LD NOT  
AND  
0007  
---  
0004  
0005  
---  
OR LD  
LD NOT  
AND  
0006  
0007  
---  
OR LD  
OUT  
0105  
Although the program will execute as written, this diagram could be redrawn  
as shown below to eliminate the need for the first OR LD and the AND LD,  
simplifying the program and saving memory space.  
0002  
0001  
0003  
0000  
Address Instruction  
Operands  
0002  
0105  
0000  
0001  
0002  
0003  
0004  
0005  
0006  
0007  
0008  
0009  
0010  
LD  
AND NOT  
OR  
0003  
0001  
0000  
0004  
0005  
---  
0004  
0006  
0005  
0007  
AND  
LD NOT  
AND  
OR LD  
LD NOT  
AND  
0006  
0007  
---  
OR LD  
OUT  
0105  
The following diagram requires five blocks, which here are coded in order  
before using OR LD and AND LD to combine them starting from the last two  
blocks and working forward. The OR LD at address 0008 combines blocks d  
and e, the following AND LD combines the resulting execution condition with  
that of block c, etc.  
0000  
0001  
0002  
Address Instruction  
Operands  
0000  
0105  
0000  
0001  
0002  
0003  
0004  
0005  
0006  
0007  
0008  
0009  
0010  
0011  
0012  
LD  
Block b  
LD  
0001  
0002  
0003  
0004  
0005  
0006  
0007  
---  
Block a  
AND  
LD  
Block c  
0004  
Block d  
0005  
AND  
LD  
0003  
LD  
AND  
OR LD  
AND LD  
OR LD  
AND LD  
OUT  
0006  
0007  
Blocks d and e  
---  
Block e  
Block c with result of above  
---  
Block b with result of above  
Block a with result of above  
---  
0105  
37  
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The Ladder Diagram  
Section 4-3  
Again, this diagram can be redrawn as follows to simplify program structure  
and coding and to save memory space.  
0006  
0005  
0007  
0001  
0003  
0004  
0000  
Address Instruction  
Operands  
0006  
0105  
0000  
0001  
0002  
0003  
0004  
0005  
0006  
0007  
0008  
0009  
LD  
AND  
OR  
0007  
0005  
0003  
0004  
0001  
0002  
---  
0002  
AND  
AND  
LD  
AND  
OR LD  
AND  
OUT  
0000  
0105  
Our last example may at first appear very complicated but can be coded us-  
ing only two logic block instructions. The diagram appears as follows:  
Block a  
0000  
0100  
0500  
0001  
0101  
0002  
0003  
0004  
0006  
0005  
0105  
Block b  
Block c  
The first logic block instruction is used to combine the execution conditions  
resulting from blocks a and b, and the second one is used to combine the  
execution condition of block c with the execution condition resulting from the  
normally closed condition assigned 0003. The rest of the diagram can be  
coded with ladder instructions. The logical flow for this and the resulting code  
are shown below.  
Block a  
Block b  
0000  
0001  
0100  
0101  
LD  
AND  
0000  
0001  
LD  
AND  
0100  
0101  
OR LD  
Block c  
0004 0005  
0500  
Address Instruction  
Operands  
0000  
0000  
0001  
0002  
0003  
0004  
0005  
0006  
0007  
0008  
0009  
0010  
0011  
0012  
LD  
LD  
AND  
0004  
0005  
OR  
0500  
0003  
AND  
LD  
0001  
0100  
0101  
---  
0002  
0006  
AND  
OR LD  
OR  
AND  
AND NOT 0003  
0002  
OR  
0006  
0500  
0002  
0003  
0004  
0005  
0006  
---  
AND  
AND NOT  
LD  
AND LD  
AND  
OR  
0105  
AND LD  
OUT  
0105  
38  
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The Ladder Diagram  
Section 4-3  
4-3-7  
Coding Multiple Right-hand Instructions  
If there is more than one right-hand instruction executed with the same exe-  
cution condition, they are coded consecutively following the last condition on  
the instruction line. In the following example, the last instruction line contains  
one more condition that corresponds to an AND.  
0000  
0001  
0003  
Address Instruction  
Operands  
0000  
HR  
001  
0000  
0001  
0002  
0003  
0004  
0005  
0006  
0007  
0008  
LD  
OR  
0001  
0002  
000  
OR  
0107  
0106  
OR  
HR  
HR  
HR  
0002  
AND  
OUT  
OUT  
AND  
OUT  
0003  
001  
HR 002  
HR 000  
0107  
002  
0106  
4-3-8  
Branching Instruction Lines  
When an instruction line branches into two or more lines, it is sometimes  
necessary to use either interlocks or TR bits to maintain the execution condi-  
tion that existed at a branching point. This is because instruction lines are  
executed across to a terminal instruction on the right before returning to  
branching points to execute instructions on the branch lines. If the execution  
condition has changed during this time, the previous execution condition is  
lost and proper execution will not be possible without some means of pre-  
serving the previous condition. The following diagrams illustrate this. In both  
diagrams, instruction 1 is executed before returning to the branching point  
and moving on to the branch line leading to instruction 2.  
Branching  
point  
Address Instruction  
Operands  
0000  
0000  
Instruction 1  
Instruction 2  
0000  
0001  
0002  
0003  
LD  
Instruction 1  
AND  
0002  
0002  
Instruction 2  
Diagram A: OK  
Branching  
point  
0000  
0001  
0002  
Address Instruction  
Operands  
Instruction 1  
Instruction 2  
0000  
0001  
0002  
0003  
0004  
LD  
0000  
0001  
AND  
Instruction 1  
AND  
Diagram B: Needs Correction  
0002  
Instruction 2  
If, as shown in diagram A, the execution condition that existed at the branch-  
ing point is not changed before returning to the branch line (instructions at  
the far right do not change the execution condition), then the branch line will  
be executed correctly and no special programming measure is required.  
If, as shown in diagram B, a condition exists between the branching point  
and the last instruction on the top instruction line, the execution condition at  
the branching point and the execution condition at the end of the top line will  
sometimes be different, making it impossible to ensure correct execution of  
the branch line. The system remembers only the current execution condition  
(i.e., the logical sum for an entire line) and does not remember partial logical  
sums at points within a line.  
39  
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The Ladder Diagram  
Section 4-3  
There are two means of programming branching programs to preserve the  
execution conditions. One is to use TR bits; the other, to use interlocks  
(IL(02)/ILC(03)).  
TR Bits  
The TR area provides eight bits, TR 0 through TR 7, that can be used to tem-  
porarily preserve execution conditions. If a TR bit is used as the operand of  
the OUTPUT instruction placed at a branching point, the current execution  
condition will be stored at the designated TR bit. Storing execution conditions  
is a special application of the OUTPUT instruction. When returning to the  
branching point, the same TR bit is then used as the operand of the LOAD  
instruction to restore the execution condition that existed when the branching  
point was first reached in program execution.  
The above diagram B can be written as shown below to ensure correct exe-  
cution.  
Address Instruction  
Operands  
0000  
TR 0  
0000  
0001  
0002  
0000  
0001  
0002  
0003  
0004  
0005  
0006  
LD  
Instruction 1  
Instruction 2  
OUT  
TR  
0
AND  
0001  
Instruction 1  
LD  
Diagram B: Corrected Using a TR bit  
TR  
0
AND  
0002  
Instruction 2  
In terms of actual instructions the above diagram would be as follows: The  
status of 0000 is loaded (a LOAD instruction) to establish the initial execution  
condition. This execution condition is then output using an OUTPUT instruc-  
tion to TR 0 to store the execution condition at the branching point. The exe-  
cution condition is then ANDed with the status of 0001 and instruction 1 is  
executed accordingly. The execution condition that was stored at the branch-  
ing point is then loaded back in (a LOAD instruction with TR 0 as the oper-  
and) and instruction 2 is executed accordingly.  
The following example shows an application using two TR bits.  
Address Instruction  
Operands  
0000  
TR 0  
TR 1  
0000  
0001  
0002  
0003  
0000  
0001  
0002  
0003  
0004  
0005  
0006  
0007  
0008  
0009  
0010  
0011  
0012  
0013  
0014  
LD  
Instruction 1  
Instruction 2  
Instruction 3  
Instruction 4  
OUT  
AND  
OUT  
AND  
OUT  
LD  
TR  
0
0001  
1
TR  
0004  
0005  
0002  
0500  
1
TR  
TR  
TR  
AND  
OUT  
LD  
0003  
0501  
0
AND  
OUT  
LD  
0004  
0502  
0
AND NOT  
OUT  
0005  
0503  
In this example, TR 0 and TR 1 are used to store the execution conditions at  
the branching points. After executing instruction 1, the execution condition  
stored in TR 1 is loaded for an AND with the status 0003. The execution con-  
dition stored in TR 0 is loaded twice, the first time for an AND with the status  
of 0004 and the second time for an AND with the inverse of the status of  
0005.  
40  
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The Ladder Diagram  
Section 4-3  
TR bits can be used as many times as required as long as the same TR bit is  
not used more than once in the same instruction block. Here, a new instruc-  
tion block is begun each time execution returns to the bus bar. If more than  
eight branching points requiring that the execution condition be saved are  
necessary in a single instruction block, interlocks, which are described next,  
must be used.  
When drawing a ladder diagram, be careful not to use TR bits unless neces-  
sary. Often the number of instructions required for a program can be reduced  
and ease of understanding a program increased by redrawing a diagram that  
would otherwise required TR bits. With both of the following pairs of dia-  
grams, the versions on the top require fewer instructions and do not require  
TR bits. The first example achieves this by merely reorganizing the parts of  
the instruction block; the second, by separating the second OUTPUT instruc-  
tion and using another LOAD instruction to create the proper execution con-  
dition for it.  
TR 0  
0000  
0001  
Instruction 1  
Instruction 2  
0000  
Instruction 2  
Instruction 1  
0001  
0000  
0001  
0003  
Instruction 1  
Instruction 2  
Instruction 1  
Instruction 2  
TR 0  
0002  
0004  
0001  
0002  
0003  
0000  
0001  
0004  
Note TR bits are only used when programming using mnemonic code and are not  
necessary when inputting ladder diagrams directly, as is possible from a  
GPC. The above limitations on the number of branching points requiring TR  
bits and considerations on methods to reduce the number of programming  
instructions still hold.  
41  
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The Ladder Diagram  
Section 4-3  
Interlocks  
The problem of storing execution conditions at branching points can also be  
handled by using the INTERLOCK (IL(02)) and INTERLOCK CLEAR  
(ILC(03)) instructions. The branching point and all the conditions leading to it  
are placed on a separate line followed by all of the lines from the branching  
point. Each branch line is thus established as an new instruction line, with the  
first condition on each branch line corresponding to a LOAD or LOAD NOT  
instruction. If the execution condition for the INTERLOCK instruction is OFF,  
all instructions on the right side of the branch lines leading from the branch-  
ing point receive an OFF execution condition through the first INTERLOCK  
CLEAR instruction. The effect that this has on particular instructions is de-  
scribed in 5-7 INTERLOCK and INTERLOCK CLEAR - IL(02) and ILC(03).  
Diagram B from the initial example can also be corrected with an interlock.  
As shown below, this requires two more instruction lines for the interlock in-  
structions.  
0000  
0001  
0002  
Address Instruction  
Operands  
0000  
IL(02)  
0000  
0001  
0002  
0003  
0004  
0005  
0006  
LD  
Instruction 1  
Instruction 2  
IL(02)  
---  
LD  
0001  
Instruction 1  
LD  
0002  
---  
ILC(03)  
Instruction 2  
ILC(03)  
Diagram B: Corrected with an Interlock  
If 0000 is ON in the revised version of diagram B, above, the status of 0001  
and that of 0002 would determine the execution conditions for instructions 1  
and 2, respectively, on independent instruction lines. Because here 0000 is  
ON, this would produce the same results as ANDing the status of each of  
these bits, as would occur if the interlock was not used, i.e., the INTERLOCK  
and INTERLOCK CLEAR instructions would not affect execution. If 0000 is  
OFF, the INTERLOCK instruction would produce an OFF execution condition  
for instructions 1 and 2 and then execution would continue with the instruc-  
tion line following the INTERLOCK CLEAR instruction.  
As shown in the following diagram, more than one INTERLOCK instruction  
can be used within one instruction block; each is effective through the next  
INTERLOCK CLEAR instruction.  
Address Instruction  
Operands  
0000  
0000  
0001  
0002  
IL(02)  
0000  
0001  
0002  
0003  
0004  
0005  
0006  
0007  
0008  
0009  
0010  
0011  
0012  
0013  
LD  
IL(02)  
---  
Instruction 1  
LD  
0001  
Instruction 1  
LD  
0002  
---  
IL(02)  
IL(02)  
0003  
0005  
0006  
0004  
LD  
0003  
0004  
Instruction 2  
Instruction 3  
Instruction 4  
AND NOT  
Instruction 2  
LD  
0005  
0006  
---  
Instruction 3  
LD  
Instruction 4  
ILC(03)  
ILC(03)  
42  
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The Ladder Diagram  
Section 4-3  
If 0000 in the above diagram was OFF (i.e., if the execution condition for the  
first INTERLOCK instruction was OFF), instructions 1 through 4 would be  
executed with OFF execution conditions and execution would move to the  
instruction following the INTERLOCK CLEAR instruction. If 0000 was ON, the  
status of 0001 would be loaded to form the execution condition for instruction  
1 and then the status of 0002 would be loaded to form the first execution  
status for that instruction line, i.e., the execution condition for the second IN-  
TERLOCK instruction. If 0002 was OFF, instructions 2 through 4 would be  
executed with OFF execution conditions. If 0002 was ON, 0003, 0005, and  
0006 would be executed as written.  
4-3-9  
Jumps  
A specific section of a program can be skipped according to a designated  
execution condition. Although this is similar to what happens when the exe-  
cution condition for an INTERLOCK instruction is OFF, with jumps, the oper-  
ands for all instructions maintain status. Jumps can therefore be used to con-  
trol devices that require a sustained output, e.g., pneumatics and hydraulics,  
whereas interlocks can be used to control devices that do not required a sus-  
tained output, e.g., electronic instruments.  
Jumps are created using the JUMP (JMP(04)) and JUMP END (JME(05))  
instructions. If the execution condition for a JUMP instruction is ON, the pro-  
gram is executed normally as if the jump did not exist. If the execution condi-  
tion for the JUMP instruction is OFF, program execution moves immediately  
to a JUMP END instruction without changing the status of anything between  
the JUMP and JUMP END instruction. Actually there are two types of jumps.  
All JUMP and JUMP END instructions are assigned jump numbers ranging  
between 00 and 08. The jump number used determines the type of jump.  
A jump can be defined using jump numbers 01 through 08 only once, i.e.,  
each of these numbers can be used once in a JUMP instruction and once in  
a JUMP END instruction. When a JUMP instruction assigned one of these  
numbers is executed, execution moves immediately to the JUMP END in-  
struction that has the same number as if all of the instruction between them  
did not exist. Diagram B from the TR bit and interlock example could be  
redrawn as shown below using a jump. Although 01 has been used as the  
jump number, any number between 01 and 08 could be used as long as it  
has not already been used in a different part of the program.  
0000  
0001  
0002  
Address Instruction  
Operands  
0000  
JMP(04) 01  
Instruction 1  
Instruction 2  
0000  
0001  
0002  
0003  
0004  
0005  
0006  
LD  
JMP(04)  
LD  
01  
0001  
Instruction 1  
LD  
0002  
01  
JME(05) 01  
Instruction 2  
JME(05)  
Diagram B: Corrected with a Jump  
This version of diagram B would have a shorter execution time when 0000  
was OFF than any of the other versions.  
The other type of jump is created with a jump number of 00. As many jumps  
as desired can be created using jump number 00 and JUMP instructions us-  
ing 00 can be used consecutively without a JUMP END using 00 between  
them. In the extreme, only one JUMP END 00 instruction is required for all  
JUMP 00 instructions. When 00 is used as the jump number for a JUMP in-  
struction, program execution moves to the instruction following the next  
43  
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The Programming Console  
Section 4-4  
JUMP END instruction with a jump number of 00. Although, as in all jumps,  
no status is changed and no instructions are executed between the JUMP 00  
and JUMP END 00 instructions, the program must search for the next JUMP  
END 00 instruction, producing a slightly longer execution time.  
Execution of programs containing multiple JUMP 00 instructions for one  
JUMP END 00 instruction resembles that of similar interlocked sections. The  
following diagram is the same as that used for the interlock example above,  
except redrawn with jumps. This diagram, however, would not execute the  
same, as has already be described, i.e., interlocks would reset certain parts  
of the interlocked section but jumps would not affect any status between the  
JUMP and JUMP END instructions.  
Address Instruction  
Operands  
0000  
0000  
0001  
0002  
JMP(04) 00  
Instruction 1  
0000  
0001  
0002  
0003  
0004  
0005  
0006  
0007  
0008  
0009  
0010  
0011  
0012  
0013  
LD  
JMP(04)  
LD  
00  
0001  
Instruction 1  
LD  
0002  
00  
JMP(04) 00  
JMP(04)  
LD  
0003  
0005  
0006  
0004  
0003  
0004  
Instruction 2  
Instruction 3  
Instruction 4  
AND NOT  
Instruction 2  
LD  
0005  
0006  
00  
Instruction 3  
LD  
Instruction 4  
JME(05)  
JME(05) 00  
Jump diagrams can also be drawn as branching instruction lines if desired  
and would look exactly like their interlock equivalents. The non-branching  
form, which is the form displayed on the GPC, will be used in this manual.  
4-4  
The Programming Console  
Depending on the model of Programming Console used, it is either con-  
nected to the CPU via a Programming Console Adapter and Connecting Ca-  
ble or it is mounted directly to the CPU.  
4-4-1  
The Keyboard  
The keyboard of the Programming Console is functionally divided by key  
color into the following four areas:  
White Numeric Keys  
The ten white keys are used to input numeric program data such as program  
addresses, data area addresses, and operand values. The numeric keys are  
also used in combination with the function key (FUN) to enter instructions  
with function codes.  
Red CLR Key  
The CLR key clears the display and cancels current Programming Console  
operations. It is also used when you key in the password at the beginning of  
programming operations. Any Programming Console operation can be can-  
celled by pressing the CLR key, although the CLR key may have to be  
pressed two or three times to cancel the operation and clear the display.  
Yellow Operation Keys  
The yellow keys are used for writing and correcting programs. Detailed ex-  
planations of their functions are given later in this section.  
44  
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The Programming Console  
Section 4-4  
Gray Instruction and Data  
Area Keys  
Except for the SHIFT key on the upper right, the gray keys are used to input  
instructions and designate data area prefixes when inputting or changing a  
program. The SHIFT key is similar to the shift key of a typewriter, and is used  
to alter the function of the next key pressed. (It is not necessary to hold the  
SHIFT key down; just press it once and then press the key to be used with  
it.)  
The gray keys other than the SHIFT key have either the mnemonic name of  
the instruction or the abbreviation of the data area written on them. The func-  
tions of these keys are described below.  
Pressed before the function code when in-  
putting an instruction via its function code.  
Pressed before designating an address in  
the TR area.  
Pressed to enter SFT (the Shift Register  
instruction).  
Pressed before designating an address in  
the LR area. Cannot be used with the K-type  
PCs.  
Input after a ladder instruction to designate  
an normally closed condition.  
Pressed before designating an address in  
the HR area.  
Pressed to enter AND (the AND instruc-  
tion) or used with NOT to enter AND NOT.  
Pressed before designating an address in  
the DM area.  
Pressed to enter OR (the OR instruction)  
or used with NOT to enter OR NOT.  
Pressed before designating an indirect DM  
address. Cannot be used with the K-type  
PCs.  
Pressed to enter CNT (the Counter instruc-  
tion) or to designate a TC number that has  
already been defined as a counter.  
Pressed before designating a word address.  
Pressed to enter LD (the Load instruction)  
or used with NOT to enter LD NOT. Also  
pressed to indicate an input bit.  
Pressed before designating an operand as a  
constant.  
Pressed to enter OUT (the Output instruc-  
tion) or used with NOT to enter OUT NOT.  
Also pressed to indicate an output bit.  
Pressed before designating a bit address.  
Pressed to enter TIM (the Timer instruc-  
tion) or to designate a TC number that has  
already been defined as a timer.  
4-4-2  
PC Modes  
The Programming Console is equipped with a switch to control the PC mode.  
To select one of three operating modes—RUN, MONITOR, or PROGRAM—  
use the mode switch. The mode that you select will determine PC operation  
as well as the procedures that are possible from the Programming Console.  
RUN mode is the mode used for normal program execution. When the switch  
is set to RUN and the START input on the CPU Power Supply Unit is ON, the  
CPU will begin executing the program according to the program written in its  
Program Memory. Although monitoring PC operation from the Programming  
Console is possible in RUN mode, no data in any of the memory areas can  
be input or changed.  
MONITOR mode allows you to visually monitor in-progress program execu-  
tion while controlling I/O status, changing PV (present values) or SV (set val-  
ues), etc. In MONITOR mode, I/O processing is handled in the same way as  
in RUN mode. MONITOR mode is generally used for trial system operation  
and final program adjustments.  
45  
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Preparation for Operation  
Section 4-5  
In PROGRAM mode, the PC does not execute the program. PROGRAM  
mode is for creating and changing programs, clearing memory areas, and  
registering and changing the I/O table. A special Debug operation is also  
available within PROGRAM mode that enables checking a program for cor-  
rect execution before trial operation of the system.  
DANGER  
Do not leave the Programming Console connected to the PC by an extension  
cable when in RUN mode. Noise entering via the extension cable can affect the  
program in the PC and thus the controlled system.  
!
Mode Changes  
When the PC is turned on, the mode it is in will depend on what Peripheral  
Device, if any, is connected or mounted to the CPU.  
• No Peripheral Device Connected  
When power is applied to the PC without a Peripheral Device connected,  
the PC is automatically set to RUN mode. Program execution is then con-  
trolled through the CPU Power Supply Unit’s START terminal.  
• Programming Console Connected  
If the Programming Console is connected to the PC when PC power is ap-  
plied, the PC is set to the mode set on the Programming Console’s mode  
switch.  
• Other Peripheral Connected  
If a Peripheral Interface Unit, PROM Writer, Printer Interface Unit, or a  
Floppy Disk Interface Unit is attached to the PC when PC power is turned  
on, the PC is automatically set to PROGRAM mode.  
If the PC power supply is already turned on when a peripheral device is at-  
tached to the PC, the PC will stay in the same mode it was in before the pe-  
ripheral device was attached. The mode can be changed with the mode  
switch on the Programming Console once the password has been entered. If  
it is necessary to have the PC in PROGRAM mode, (for the PROM Writer,  
Floppy Disk Interface Unit, etc.), be sure to select this mode before connect-  
ing the peripheral device, or alternatively, apply power to the PC after the pe-  
ripheral device is connected.  
The mode will also not change when a Peripheral Device is removed from  
the PC after PC power is turned on.  
DANGER  
Always confirm that the Programming Console is in PROGRAM mode when  
turning on the PC with a Programming Console connected unless another mode  
is desired for a specific purpose. If the Programming Console is in RUN mode  
when PC power is turned on, any program in Program Memory will be executed,  
possibly causing any PC-controlled system to begin operation. Also be sure that  
starting operation is safe and appropriate whenever turning on the PC without a  
device mounted to the CPU when the START input on the CPU Power Supply  
Unit is ON.  
!
4-5  
Preparation for Operation  
This section describes the procedures required to begin Programming Con-  
sole operation. These include password entry, clearing memory, and error  
message clearing.  
The following sequence of operations must be performed before beginning  
initial program input.  
1, 2, 3... 1. Confirm that all wiring for the PC has been installed and checked prop-  
erly.  
2. Confirm that a RAM Unit is mounted as the Memory Unit and that the  
write-protect switch is OFF.  
46  
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Preparation for Operation  
Section 4-5  
3. Connect the Programming Console to the PC. Make sure that the Pro-  
gramming Console is securely connected or mounted to the CPU; im-  
proper connection may inhibit operation.  
4. Set the mode switch to PROGRAM mode.  
5. Turn on PC power.  
6. Enter the password.  
7. Clear memory.  
Each of these operations from entering the password on is described in detail  
in the following subsections. All operations should be done in PROGRAM  
mode unless otherwise noted.  
4-5-1  
Entering the Password  
To gain access to the PC’s programming functions, you must first enter the  
password. The password prevents unauthorized access to the program.  
The PC prompts you for a password when PC power is turned on or, if PC  
power is already on, after the Programming Console has been connected to  
the PC. To gain access to the system when the “Password!” message ap-  
pears, press CLR and then MONTR. Then press CLR to clear the display.  
If the Programming Console is connected to the PC when PC power is al-  
ready on, the first display below will indicate the mode the PC was in before  
the Programming Console was connected. Be sure that the PC is in PRO-  
GRAM mode before you enter the password. When the password is en-  
tered, the PC will shift to the mode set on the mode switch, causing PC op-  
eration to begin if the mode is set to RUN or MONITOR. You can change the  
mode to RUN or MONITOR with the mode switch after entering the pass-  
word.  
<PROGRAM>  
PASSWORD  
<PROGRAM>  
Indicates the mode set by the mode selector switch.  
4-5-2  
Clearing Memory  
Using the Memory Clear operation it is possible to clear all or part of the Pro-  
gram Memory, and the IR, HR, DM and TC areas. Unless otherwise speci-  
fied, the clear operation will clear all memory areas above provided that the  
Memory Unit attached to the PC is a RAM Unit or an EEPROM Unit and the  
write-protect switch is OFF. If the write-protect switch is ON, or the Memory  
Unit is an EPROM Unit, Program Memory cannot be cleared.  
Before beginning to programming for the first time or when installing a new  
program, all areas should normally be cleared. Before clearing memory,  
check to see if a program is already loaded that you need. If you need the  
program, clear only the memory areas that you do not need, and be sure to  
check the existing program with the program check key sequence before us-  
ing it. The check sequence is provided later in this section. Further debug-  
ging methods are provided in Section 7 Program Debugging and Execution.  
To clear all memory areas, press CLR until all zeros are displayed and then  
the top line of the following sequence. The branch lines in the sequence are  
used when clearing only part of the memory areas, which is described below.  
Memory can be cleared in PROGRAM mode only.  
47  
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Preparation for Operation  
Section 4-5  
Key Sequence  
All Clear  
The following procedure is used to clear memory completely.  
0000  
0000  
0000  
0000MEMORY CLR?  
HR CNT DM  
0000MEMORY CLR  
END HR CNT DM  
Partial Clear  
It is possible to retain the data in specified areas and/or part of the Program  
Memory. To retain the data in the HR and TC, and/or DM areas, press the  
appropriate key after entering REC/RESET. The CNT key is used for the en-  
tire TC area. The display will show those areas that will be cleared.  
It is also possible to retain a portion of the Program Memory from the begin-  
ning to a specified address. After designating the data areas to be retained,  
specify the first Program Memory address to be cleared. For example, to  
leave addresses 0000 to 0122 untouched, but to clear addresses from 0123  
to the end of Program Memory, input 0123.  
48  
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Inputting, Modifying, and Checking the Program  
Section 4-6  
For example, to leave the TC area uncleared and retaining Program Memory  
addresses 0000 through 0122, input as follows:  
0000  
0000  
0000  
0000MEMORY CLR?  
HR CNT DM  
0000MEMORY CLR?  
HR DM  
0123MEMORY CLR?  
HR DM  
0000MEMORY CLR  
END HR DM  
4-5-3  
Clearing Error Messages  
Any error messages recorded in memory should also be cleared. It is as-  
sumed here that the causes of any of the errors for which error messages  
appear have already been taken care of. If the beeper sounds when an at-  
tempt is made to clear an error message, eliminate the cause of the error,  
and then clear the error message (refer to Section 8 Troubleshooting).  
To display any recorded error messages, press CLR, FUN, and then  
MONTR. The first message will appear. Pressing MONTR again will clear the  
present message and display the next error message. Continue pressing  
MONTR until all messages have been cleared.  
Although error messages can be accessed in any mode, they can be cleared  
only in PROGRAM mode.  
Key Sequence  
4-6  
Inputting, Modifying, and Checking the Program  
Once a program is written in mnemonic code, it can be input directly into the  
PC from a Programming Console. Mnemonic code is keyed into Program  
Memory addresses from the Programming Console. Checking the program  
involves a syntax check to see that the program has been written according  
to syntax rules before trial execution and finally correction under actual con-  
ditions can begin.  
The operations required to input a program are explained below. Operations  
to modify programs that already exist in memory are also provided in this  
section, as well as the procedure to obtain the current cycle time.  
49  
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Inputting, Modifying, and Checking the Program  
Section 4-6  
Before starting to input a program, check to see whether there is a program  
already loaded. If there is a program already loaded that you do not need,  
clear it first using the program memory clear key sequence, then input the  
new program. If you need the previous program, be sure to check it with the  
program check key sequence and correct it as required. Further debugging  
methods are provided in Section 7 Program Debugging and Execution.  
4-6-1  
Setting and Reading from Program Memory Address  
When inputting a program for the first time, it is generally input from Program  
Memory address 0000. As this address appears when the display is cleared,  
it is not necessary to input it.  
When inputting a program starting from other than 0000 or to read or modify  
a program that already exists in memory, the desired address must be desig-  
nated. To designate an address, press CLR and then input the desired ad-  
dress. Leading zeros of the address need not be input, i.e., when specifying  
an address such as 0053 you need to enter only 53. The contents of the des-  
ignated address will not be displayed until the down key is pressed.  
Once the down key has been pressed to display the contents of the desig-  
nated address, the up and down keys can be used to scroll through Program  
Memory. Each time one of these keys is pressed, the next or previous word  
in Program Memory will be displayed.  
If Program Memory is read in RUN or MONITOR mode, the ON/OFF status  
of any bit displayed will also be shown.  
Key Sequence  
Example  
If the following mnemonic code has already been input into Program Memory,  
the key inputs below would produce the displays shown.  
Address Instruction  
Operands  
0000  
0000  
0200  
0201  
0202  
LD  
AND  
TIM  
0001  
00  
0200  
#
0123  
0100  
0203  
LD  
0200READ OFF  
LD  
0000  
0201READ ON  
AND 0001  
0202READ OFF  
TIM 00  
0202TIM DATA  
#0123  
0203READ ON  
LD  
0100  
50  
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Inputting, Modifying, and Checking the Program  
Section 4-6  
4-6-2  
Inputting or Overwriting Programs  
Programs can be input or overwritten only in PROGRAM mode.  
The same procedure is used to either input a program for the first time or to  
overwrite a program that already exists. In either case, the current contents  
of Program Memory are overwritten, i.e., if there is no previous program, the  
NOP(00) instruction, which will be written at every address, will be overwrit-  
ten.  
To input a program, just follow the mnemonic code that was produced from  
the ladder diagram, making sure that the proper address is set before start-  
ing. Once the proper address is displayed, input the first instruction word,  
press WRITE, and then input any operands required, pressing WRITE after  
each, i.e., WRITE is pressed at the end of each line of the mnemonic code.  
When WRITE is pressed, the designated instruction will be input and the next  
display will appear. If the instruction requires two or more words, the next  
display will indicate the next operand required and provide a default value for  
it. If the instruction requires only one word, the next address will be dis-  
played. Continue inputting each line of the mnemonic code until the entire  
program has been input.  
When inputting numeric values for operands, it is not necessary to input lead-  
ing zeros. Leading zeros are required only when inputting function codes  
(see below). When designating operands, be sure to designate the data area  
for all but IR and SR addresses by pressing the corresponding data area key  
or to designate a constant by pressing CONT/#. CONT/# is not required for  
counter or timer SV (see below). TC numbers as bit operands (i.e., comple-  
tion flags) are designated by pressing either TIM or CNT before the address,  
depending on whether the TC number has been used to define a timer or a  
counter.  
Inputting SV for Counters  
and Timers  
The SV (set value) for a timer or counter is generally input as a constant, al-  
though inputting the address of a word that holds the SV is also possible.  
When inputting an SV as a constant, CONT/# is not required; just input the  
numeric value and press WRITE. To designate a word, press CLR and then  
input the word address as described above.  
Designating Instructions  
The most basic instructions are input using the Programming Console keys  
provided for them. All other instructions are input using function codes.  
These function codes are always written after the instruction’s mnemonic. If  
no function code is given, there should be a Programming Console key for  
that instruction.  
To input an instruction word using a function code, set the address, press  
FUN, input the function code including any leading zero, input any bit oper-  
ands or definers required on the instruction line, and then press WRITE.  
Caution Enter function codes with care.  
!
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Inputting, Modifying, and Checking the Program  
Section 4-6  
Example  
The following ladder diagram can be input using the key inputs shown below.  
Displays will appear as indicated.  
Address Instruction  
Operands  
0002  
0000  
0200  
0200  
0201  
LD  
TIM  
00  
0123  
01  
#
#
0202  
TIMH(15)  
0500  
0200  
LD  
0002  
0201READ  
NOP (00)  
0201  
TIM  
00  
0201 TIM DATA  
#0000  
0201 TIM  
#0123  
0202READ  
NOP (00)  
0202  
FUN (??)  
0202  
TIMH (15) 01  
0202 TIMH DATA  
#0000  
0202 TIMH  
#0500  
0203READ  
NOP (00)  
Error Messages  
The following error messages may appear when inputting a program. Correct  
the error as indicated and continue with the input operation. The asterisks in  
the displays shown below will be replaced with numeric data, normally an  
address, in the actual display.  
Message  
Cause and correction  
****REPL ROM  
An attempt was made to write to ROM or to write-protected RAM. Be sure a RAM Unit is mounted  
and that its write-protect switch is set to OFF.  
****PROG OVER  
****ADDR OVER  
****SETDATA ERR  
****I/O NO. ERR  
The instruction at the last address in memory is not NOP(00). Erase all unnecessary instructions  
at the end of the program or use a larger Memory Unit.  
An address was set that is larger than the highest memory in Program Memory. Input a smaller  
address  
Data has been input in the wrong format or beyond defined limits, e.g., a hexadecimal value has  
been input for BCD. Reinput the data.  
A data area address has been designated that exceeds the limit of the data area, e.g., an  
address is too large. Confirm the requirements for the instruction and reinput the address.  
52  
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Inputting, Modifying, and Checking the Program  
Section 4-6  
4-6-3  
Checking the Program  
Once a program has been input, it should be checked for syntax to be sure  
that no programming rules have been violated. This check should also be  
performed if the program has been changed in any way that might create a  
syntax error.  
To check the program, input the key sequence shown below. If an error is  
discovered, the check will stop and a display indicating the error will appear.  
Press SRCH to continue the check. If an error is not found, the program will  
be checked through the first END(01), with a display indicating when each 64  
instructions have been checked (e.g., display #1 below).  
CLR can be pressed to cancel the check after it has been started, and a dis-  
play like display #2, in the example, will appear. When the check has reached  
the first END, a display like display #3 will appear.  
A syntax check can be performed on a program only in PROGRAM mode.  
Key Sequence  
Error Messages  
The following table provides the error types, displays, and explanations of all  
syntax errors. The address where the error was generated will also be dis-  
played.  
Many of the following errors are for instructions that have not been intro-  
duced yet. Refer to 4-7 Controlling Bit Status or to Section 5 Instruction Set  
for details on these.  
Message  
?????  
Meaning and appropriate response  
The program has been destroyed. Reinput the program.  
NO END INSTR  
CIRCUIT ERR  
There is no END(01) in the program. Write END(01) at the final address in the program.  
The number of logic blocks and logic block instructions does not agree, i.e., either LD or LD NOT  
has been used to start a logic block whose execution condition has not been used by another  
instruction or a logic block instruction has been used that does not have the required number of  
logic blocks (i.e., unused execution conditions). Check your program.  
IL-ILC ERR  
IL(02) and ILC(03) are not used in pairs. Correct the program so that each IL(02) has a unique  
ILC(03). Although this error message will appear if more than one IL(02) is used with the same  
ILC(03), the program will be executed as written. Make sure your program is written as desired  
before proceeding.  
JMP-JME ERR  
COIL DUPL  
JMP(04) and JME(05) are not used in pairs. Match each JMP(04) to a JME(05).  
The same bit is being controlled (i.e., turned ON and/or OFF) by more than one instruction (e.g.,  
OUT, OUT NOT, DIFU(13), DIFD(14), KEEP(11), SFT(10)). Although this is allowed for certain  
instructions, check instruction requirements to confirm that the program is correct or rewrite the  
program so that each bit is controlled by only one instruction.  
DIF OVER  
More than 48 DIFU and DIFDs are used in the program. Reduce the number of DIFU(13) and  
DIFD(14) used to 48 or less.  
LOCN ERR  
JME UNDEFD  
JMP UNDEFD  
DUPL  
The instruction currently displayed is in the wrong area. Correct the program.  
The corresponding JME for a given JMP does not exist. Correct the program.  
The corresponding JMP for a given JME does not exist. Correct the program.  
The number of the currently displayed instruction has already been programmed. Correct the  
program.  
SBN-RET ERR  
SBN UNDEFD  
Incorrect usage of the displayed instruction (SBN or RET). Incorrect SBN usage is caused by  
more than one SBN having the same subroutine number. Correct the program.  
The subroutine called by SBS does not exist. Correct the program.  
53  
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Inputting, Modifying, and Checking the Program  
Section 4-6  
Message  
Meaning and appropriate response  
SBS UNDEFD  
A defined subroutine is not called by the main program. When this message is displayed because  
of interrupt routine definition, there is no problem. In all other cases, correct the program.  
STEP OVER  
SNXT OVER  
STEP ERR  
STEP is used for more than 16 program sections. Correct the program to decrease the number of  
sections to 16 or less. When the GPC is used the message “CPU WAITG” is displayed.  
More than 48 SNTXs are used in the program. Correct the program to decrease the number to 48  
or less.  
STEP and SNXT are not correctly used. Correct the program.  
Example  
The following examples shows some of the displays that can appear as a  
result of a program check.  
0000  
0064PROG CHK  
Display #1  
Halts program check  
0128PROG CHKEND  
Display  
#2  
Check continues until END(01)  
1150PROG CHK  
END (01)  
Display  
#3  
When errors are found  
0178CIRCUIT ERR  
OUT  
0200  
0196COIL DUPL  
OUT 0500  
0200IL-ILC ERR  
ILC (03)  
1193NO ENDINSTR  
END  
4-6-4  
Displaying the Cycle Time  
Once the program has been cleared of syntax errors, the cycle time should  
be checked. This is possible only in RUN or MONITOR mode while the pro-  
gram is being executed. See Section 6 Program Execution Timing for details  
on the cycle time.  
To display the current average cycle time, press CLR then MONTR. The time  
displayed by this operation is an average cycle time. The differences in dis-  
played values depend on the execution conditions that exist when MONTR is  
pressed.  
Note Cycle time is displayed as scan time.  
54  
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Inputting, Modifying, and Checking the Program  
Section 4-6  
Example  
0000  
0000SCAN TIME  
AVG 054.1MS  
0000SCAN TIME  
AVG 053.9MS  
4-6-5  
Program Searches  
The program can be searched for occurrences of any designated instruction  
or data area bit address used in an instruction. Searches can be performed  
from any currently displayed address or from a cleared display.  
To designate a bit address, press SHIFT, press CONT/#, then input the ad-  
dress, including any data area designation required, and press SRCH. To  
designate an instruction, input the instruction just as when inputting the pro-  
gram and press SRCH. Once an occurrence of an instruction or bit address  
has been found, any additional occurrences of the same instruction or bit can  
be found by pressing SRCH again. SRCHG will be displayed while a search  
is in progress.  
When the first word of a multiword instruction is displayed for a search opera-  
tion, the other words of the instruction can be displayed by pressing the down  
key before continuing the search.  
If Program Memory is read in RUN or MONITOR mode, the ON/OFF status  
of any bit displayed will also be shown.  
Key Sequence  
55  
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Inputting, Modifying, and Checking the Program  
Section 4-6  
Example: Instruction Search  
0000  
0000  
LD  
0000  
0200SRCH  
LD  
0000  
0202  
LD  
0000  
1082SRCH  
END (01)  
0000  
0100  
0100  
TIM  
01  
01  
0203SRCH  
TIM  
0203 TIM DATA  
#0123  
Example: Bit Search  
0000  
0000  
CONT  
0005  
0200CONT SRCH  
LD 0005  
0203CONT SRCH  
AND 0005  
1078CONT SRCH  
END (01)  
56  
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Inputting, Modifying, and Checking the Program  
Section 4-6  
4-6-6  
Inserting and Deleting Instructions  
In PROGRAM mode, any instruction that is currently displayed can be de-  
leted or another instruction can be inserted before it. These are not possible  
in RUN or MONITOR modes.  
To insert an instruction, display the instruction before which you want the new  
instruction to be placed, input the instruction word in the same way as when  
inputting a program initially, and then press INS and the down key. If other  
words are required for the instruction, input these in the same way as when  
inputting a program initially.  
To delete an instruction, display the instruction word of the instruction to be  
deleted and then press DEL and the up key. All the words for the designated  
instruction will be deleted.  
Caution Be careful not to inadvertently delete instructions; there is no way to recover  
!
them without reinputting them completely.  
Key Sequence  
When an instruction is inserted or deleted, all addresses in Program Memory  
following the operation are adjusted automatically so that there are no blank  
addresses and no unaddressed instructions.  
Example  
The following mnemonic code shows the changes that are achieved in a pro-  
gram through the key sequences and displays shown below.  
Original Program  
Address Instruction  
Operands  
0100  
0000  
0001  
0002  
0003  
0004  
0005  
0006  
0007  
0008  
LD  
AND  
0101  
0201  
0102  
---  
LD  
AND NOT  
OR LD  
AND  
0103  
0104  
0201  
---  
AND NOT  
OUT  
END(01)  
Before Deletion:  
Before Insertion:  
0104  
0100  
0101  
0103  
0105  
0100  
0201  
0101  
0102  
0103  
0104  
0201  
0201  
0201  
0102  
Delete  
0105  
END(01)  
END(01)  
57  
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Inputting, Modifying, and Checking the Program  
Section 4-6  
The following key inputs and displays show the procedure for achieving the  
program changes shown above.  
Inserting an Instruction  
0000  
Find the address prior  
to the insertion point  
0000  
OUT  
0000  
0000  
OUT  
Program After Insertion  
0201  
Address Instruction  
Operands  
0100  
0207SRCH  
0000  
0001  
0002  
0003  
0004  
0005  
0006  
0007  
0008  
0009  
LD  
OUT  
0201  
AND  
0101  
0201  
0102  
---  
LD  
0206READ  
AND NOT 0104  
AND NOT  
OR LD  
AND  
0103  
0105  
0104  
0201  
---  
0206  
AND  
AND  
0000  
0105  
AND NOT  
OUT  
0206  
AND  
END(01)  
0206INSERT?  
AND  
0105  
0207INSERT END  
AND NOT 0104  
Insert the  
instruction  
0206READ  
AND  
0105  
58  
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Controlling Bit Status  
Section 4-7  
Deleting an Instruction  
0000  
Find the instruction  
that requires deletion.  
0000  
OUT  
0000  
0201  
Program After Deletion  
Address Instruction  
0000  
OUT  
Operands  
0000  
0001  
0002  
0003  
0004  
0005  
0006  
0007  
0008  
LD  
0100  
0101  
0201  
0102  
---  
AND NOT  
LD  
0208SRCH  
OUT  
0201  
AND NOT  
OR LD  
AND  
0207READ  
AND NOT 0104  
0103  
0105  
0104  
0201  
AND  
AND NOT  
OUT  
0207 DELETE?  
AND NOT 0104  
0207DELETE END  
Confirm that this is the  
instruction to be deleted.  
OUT  
0201  
0206READ  
AND 0105  
4-7  
Controlling Bit Status  
There are five instructions that can be used generally to control individual bit  
status. These are the OUTPUT or OUT, OUTPUT NOT or OUT NOT, DIF-  
FERENTIATE UP, DIFFERENTIATE DOWN, and KEEP instructions. All of  
these instruction appear as the last instruction in an instruction line and take  
a bit address for an operand. Although details are provided in 5-6 Bit Control  
Instructions, these instructions are described here because of their impor-  
tance in most programs. Although these instructions are used to turn ON and  
OFF output bits in the IR area (i.e., to send or stop output signals to external  
devices), they are also used to control the status of other bits in the IR area  
or in other data areas.  
4-7-1  
DIFFERENTIATE UP and DIFFERENTIATE DOWN  
DIFFERENTIATE UP (DIFU(13)) and DIFFERENTIATE DOWN (DIFD(14))  
instructions are used to turn the operand bit ON for one cycle at a time. The  
DIFFERENTIATE UP turns ON the operand bit for one cycle after the execu-  
tion condition when it goes from OFF to ON; the DIFFERENTIATE DOWN  
instruction turns ON the operand bit for one cycle after the execution condi-  
tion when it goes from ON to OFF.  
0000  
0001  
Address Instruction  
Operands  
0000  
0500  
DIFU(13) 0500  
DIFD(14) 0501  
0000  
0001  
LD  
DIFU(13)  
Address Instruction  
Operands  
0000  
0001  
LD  
0001  
0501  
DIFD(14)  
59  
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Controlling Bit Status  
Section 4-7  
Here, 0500 will be turned ON for one cycle after 0000 goes ON. The next  
time DIFU(13) 0500 is executed, 0500 will be turned OFF, regardless of the  
status of 0000. With the DIFFERENTIATE DOWN instruction, 0501 will be  
turned ON for one cycle after 0001 goes OFF (0501 will be kept OFF until  
then) and will be turned ON the next time DIFD(14) is executed.  
4-7-2  
KEEP  
The KEEP instruction is used to maintain the status of the operand bit based  
on two execution conditions. To do this, the KEEP instruction is connected to  
two instruction lines. When the execution condition at the end of the first in-  
struction line is ON, the operand bit of the KEEP instruction is turned ON.  
When the execution condition at the end of the second instruction line is ON,  
the operand bit of the KEEP instruction is turned OFF. The operand bit for the  
KEEP instruction will maintain its ON or OFF status even if it is located in an  
interlocked section of the diagram and the execution condition for the INTER-  
LOCK instruction is ON.  
In the following example, HR 000 will be turned ON when 0002 is ON and  
0003 is OFF. HR 000 will then remain ON until either 0004 or 0005 turns ON.  
0002  
0003  
Address Instruction  
Operands  
0002  
S:set  
0000  
0001  
0002  
0003  
0004  
LD  
KEEP(11)  
HR 000  
AND NOT  
LD  
0003  
0004  
0005  
000  
0004  
0005  
R: reset  
OR  
KEEP(11)  
HR  
4-7-3  
Self-maintaining Bits (Seal)  
Although the KEEP instruction can be used to create self maintaining bits, it  
is sometimes necessary to create self maintaining bits in another way so that  
they can be turned OFF when in an interlocked section of a program.  
To create a self maintaining bit, the operand bit of an OUTPUT instruction is  
used as a condition for the same OUTPUT instruction in an OR setup so that  
the operand bit of the OUTPUT instruction will remain ON or OFF until  
changes in other bits occur. At least one other condition is used just before  
the OUTPUT instruction to function as a reset. Without this reset, there would  
be no way to control the operand bit of the OUTPUT instruction.  
The above diagram for the KEEP instruction can be rewritten as shown be-  
low. The only difference in these diagrams would be their operation in an in-  
terlocked program section when the execution condition for the INTERLOCK  
instruction was ON. Here, just as in the same diagram using the KEEP in-  
struction, two reset bits are used, i.e., HR 000 is turned OFF by turning ON  
both 0004 and 0005.  
0002  
0003  
0004  
Address Instruction  
Operands  
0002  
HR 000  
0000  
0001  
0002  
0003  
0004  
0005  
LD  
0005  
AND NOT  
OR  
0003  
000  
HR  
HR  
HR 000  
AND NOT  
OR NOT  
OUT  
0004  
0005  
000  
60  
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Work Bits (Internal Relays)  
Section 4-8  
4-8  
Work Bits (Internal Relays)  
In programming, combining conditions to directly produce execution condi-  
tions is often extremely difficult. These difficulties are easily overcome, how-  
ever, by using certain bits to trigger other instructions indirectly. Such pro-  
gramming is achieved by using work bits. Sometimes entire words are re-  
quired for these purposes. These words are referred to as work words.  
Work bits are not transferred to or from the PC. They are bits selected by the  
programmer to facilitate programming as described above. I/O bits and other  
dedicated bits cannot be used as works bits. All bits in the IR area that are  
not allocated as I/O bits, and certain unused bits in the AR area, are avail-  
able for use as work bits. Be careful to keep an accurate record of how and  
where you use work bits. This helps in program planning and writing, and  
also aids in debugging operations.  
Work Bit Applications  
Examples given later in this subsection show two of the most common ways  
to employ work bits. These should act as a guide to the almost limitless num-  
ber of ways in which the work bits can be used. Whenever difficulties arise in  
programming a control action, consideration should be given to work bits and  
how they might be used to simplify programming.  
Work bits are often used with the OUTPUT, OUTPUT NOT, DIFFERENTIATE  
UP, DIFFERENTIATE DOWN, and KEEP instructions. The work bit is used  
first as the operand for one of these instructions so that later it can be used  
as a condition that will determine how other instructions will be executed.  
Work bits can also be used with other instructions, e.g., with the SHIFT REG-  
ISTER instruction (SFT(10)). An example of the use of work words and bits  
with the SHIFT REGISTER instruction is provided in 5-12-1 SHIFT REGIS-  
TER - SFT(10).  
Although they are not always specifically referred to as work bits, many of the  
bits used in the examples in Section 5 Instruction Set use work bits. Under-  
standing the use of these bits is essential to effective programming.  
61  
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Work Bits (Internal Relays)  
Section 4-8  
Reducing Complex  
Conditions  
Work bits can be used to simplify programming when a certain combination  
of conditions is repeatedly used in combination with other conditions. In the  
following example, IR 0000, IR 0001, IR 0002, and IR 0003 are combined in  
a logic block that stores the resulting execution condition as the status of IR  
0112. IR 0112 is then combined with various other conditions to determine  
output conditions for IR 0100, IR 0101, and IR 0102, i.e., to turn the outputs  
allocated to these bits ON or OFF.  
Address Instruction  
Operands  
0000  
0000  
0002  
0003  
0001  
0112  
0000  
0001  
0002  
0003  
0004  
0005  
0006  
0007  
0008  
0009  
0010  
0011  
0012  
0013  
0014  
0015  
0016  
LD  
AND NOT  
OR  
0001  
0002  
0003  
0112  
0112  
0004  
0005  
0100  
0112  
0004  
0005  
0101  
0112  
0006  
0007  
0102  
OR NOT  
OUT  
LD  
AND  
AND NOT  
OUT  
0112  
0112  
0004  
0005  
0005  
0100  
0101  
LD  
OR NOT  
AND  
OUT  
LD NOT  
OR  
0004  
0112  
OR  
OUT  
0102  
0006  
0007  
62  
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Programming Precautions  
Section 4-9  
Differentiated Conditions  
Work bits can also be used if differential treatment is necessary for some, but  
not all, of the conditions required for execution of an instruction. In this exam-  
ple, IR 0100 must be left on continuously as long as IR 0001 is ON and both  
IR 0002 and IR 0003 are OFF, or as long as IR 0004 is ON and IR 0005 is  
OFF. It must be turned ON for only one cycle each time IR 0000 turns ON  
(unless one of the preceding conditions is keeping it ON continuously).  
This action is easily programmed by using IR 0112 as a work bit as the oper-  
and of the DIFFERENTIATE UP instruction (DIFU(13)). When IR 0000 turns  
ON, IR 0112 will be turned ON for one cycle and then be turned OFF the next  
cycle by DIFU(13). Assuming the other conditions controlling IR 0100 are not  
keeping it ON, the work bit IR 0112 will turn IR 0100 ON for one cycle only.  
0000  
Address Instruction  
Operands  
0000  
DIFU(13) 0112  
0100  
0000  
0001  
0002  
0003  
0004  
0005  
0006  
0007  
0008  
0009  
0010  
LD  
DIFU(13)  
LD  
0112  
0112  
0001  
0002  
0003  
---  
0112  
0001  
0002  
0003  
LD  
AND NOT  
AND NOT  
OR LD  
LD  
0004  
0005  
0004  
0005  
---  
AND NOT  
OR LD  
OUT  
0100  
4-9  
Programming Precautions  
The number of conditions that can be used in series or parallel is unlimited.  
Therefore, use as many conditions as required to draw a clear diagram. Al-  
though very complicated diagrams can be drawn with instruction lines almost  
forming mazes, there must not be any conditions on instruction lines running  
vertically between two other instruction lines. Diagram A shown below, for  
example, is not possible, and should be redrawn as diagram B.  
0000  
0002  
0003  
Instruction 1  
Instruction 2  
0004  
0001  
Diagram A  
0001  
0004  
0004  
0002  
0003  
Address Instruction  
Operands  
0001  
Instruction 1  
Instruction 2  
0000  
0001  
0002  
0003  
0004  
0005  
0006  
0007  
0008  
0009  
LD  
0000  
0000  
AND  
0004  
0000  
0002  
OR  
AND  
Instruction 1  
LD  
0001  
0000  
0004  
0001  
0003  
AND  
Diagram B  
OR  
AND NOT  
Instruction 2  
The number of times any particular bit can be assigned to conditions is not  
limited, so use them as many times as required to simplify your program.  
63  
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Programming Precautions  
Section 4-9  
Often, complicated programs are the result of attempts to reduce the number  
of times a bit is used.  
Every instruction line must also have at least one condition on it to determine  
the execution condition for the instruction at the right. Again, diagram A , be-  
low, must be redrawn as diagram B. If an instruction must always be exe-  
cuted (e.g., if an output must always be kept ON while the program is being  
executed), the Always ON Flag (1813) in the SR area can be used.  
Instruction  
Diagram A  
Address Instruction  
Operands  
1813  
1813  
Instruction  
0000  
0001  
LD  
Instruction  
Diagram B  
There are, however, a few exceptions to this rule, including the INTERLOCK  
CLEAR, JUMP END, and STEP Instructions. Each of these instructions is  
used as the second of a pair of instructions and is controlled by the execution  
condition of the first of the pair. Conditions should not be placed on the in-  
struction lines leading to these instructions. Refer to Section 5 Instruction Set  
for details.  
When drawing ladder diagrams, it is important to keep in mind the number of  
instructions that will be required to input it. In diagram A, below, an OR Load  
instruction will be required to combine the top and bottom instruction lines.  
This can be avoided by redrawing as shown in diagram B so that no AND  
LOAD or OR LOAD instructions are required. Refer to 5-5-2 AND LOAD and  
OR LOAD for more details and 4-6 Inputting, Modifying and Checking the  
Program for further examples.  
Address Instruction  
Operands  
0000  
0000  
0207  
0000  
0001  
0002  
0003  
0004  
LD  
LD  
0001  
0207  
---  
0001 0207  
AND  
OR LD  
OUT  
0207  
Diagram A:  
Address Instruction  
Operands  
0001 0207  
0000  
0207  
0000  
0001  
0002  
0003  
LD  
0001  
0207  
0000  
0207  
AND  
OR  
OUT  
Diagram B:  
64  
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Program Execution  
Section 4-10  
4-10 Program Execution  
When program execution is started, the CPU cycles the program from top to  
bottom, checking all conditions and executing all instructions accordingly as it  
moves down the bus bar. It is important that instructions be placed in the  
proper order so that, for example, the desired data is moved to a word before  
that word is used as the operand for an instruction. Remember that an in-  
struction line is completed to the terminal instruction at the right before exe-  
cuting any instruction lines branching from the first instruction line to other  
terminal instructions at the right.  
Program execution is only one of the tasks carried out by the CPU as part of  
the cycle time. Refer to Section 6 Program Execution Timing for details.  
65  
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SECTION 5  
Instruction Set  
5-1  
5-2  
5-3  
5-4  
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
68  
68  
68  
69  
69  
73  
73  
74  
75  
75  
Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Instruction Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Data Areas, Definer Values, and Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
5-4-1  
Coding Other Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
5-5  
5-6  
Ladder Diagram Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
5-5-1  
5-5-2  
LOAD, LOAD NOT, AND, AND NOT, OR, and OR NOT . . . . . . . .  
AND LOAD and OR LOAD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Bit Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
5-6-1  
5-6-2  
OUTPUT and OUTPUT NOT – OUT and OUT NOT . . . . . . . . . . . . .  
DIFFERENTIATE UP and DIFFERENTIATE DOWN –  
DIFU(13) and DIFD(14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
KEEP – KEEP(11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
75  
77  
5-6-3  
5-7  
5-8  
5-9  
INTERLOCK and INTERLOCK CLEAR – IL(02) and ILC(03) . . . . . . . . . . . . .  
JUMP and JUMP END – JMP(04) and JME(05) . . . . . . . . . . . . . . . . . . . . . . . . . .  
END – END(01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
78  
80  
81  
5-10 NO OPERATION – NOP(00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
81  
5-11 Timer and Counter Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
82  
5-11-1  
5-11-2  
5-11-3  
5-11-4  
5-11-5  
5-11-6  
5-11-7  
TIMER – TIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
HIGH-SPEED TIMER – TIMH(15) . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Analog Timer Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
COUNTER – CNT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
REVERSIBLE COUNTER – CNTR(12) . . . . . . . . . . . . . . . . . . . . . . .  
HIGH-SPEED DRUM COUNTER – HDM(61) . . . . . . . . . . . . . . . . .  
REVERSIBLE DRUM COUNTER – RDM(60) . . . . . . . . . . . . . . . . .  
83  
86  
87  
90  
93  
94  
103  
106  
106  
109  
110  
111  
111  
112  
112  
115  
115  
115  
116  
118  
120  
120  
122  
123  
124  
125  
125  
126  
5-12 Data Shifting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
5-12-1  
5-12-2  
5-12-3  
SHIFT REGISTER – SFT(10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
REVERSIBLE SHIFT REGISTER – SFTR(84) . . . . . . . . . . . . . . . . .  
WORD SHIFT – WSFT(16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
5-13 Data Movement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
5-13-1  
5-13-2  
MOVE – MOV(21) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
MOVE NOT – MVN(22) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
5-14 DATA COMPARE – CMP(20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
5-15 Data Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
5-15-1  
5-15-2  
5-15-3  
5-15-4  
BCD-TO- BINARY – BIN(23) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
BINARY-TO-BCD – BCD(24) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
4-TO-16 DECODER – MLPX(76) . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
16-TO-4 ENCODER – DMPX(77) . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
5-16 BCD Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
5-16-1  
5-16-2  
5-16-3  
5-16-4  
5-16-5  
5-16-6  
BCD ADD – ADD(30) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
BCD SUBTRACT – SUB(31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
BCD MULTIPLY – MUL(32) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
BCD DIVIDE – DIV(33) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
SET CARRY – STC(40) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
CLEAR CARRY – CLC(41) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
5-17 Subroutines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
5-17-1  
SUBROUTINE DEFINE and SUBROUTINE RETURN  
SBN(92)/RET(93) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
SUBROUTINE ENTRY – SBS(91) . . . . . . . . . . . . . . . . . . . . . . . . . . .  
126  
126  
128  
128  
135  
135  
135  
136  
5-17-2  
5-18 Step Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
5-18-1 STEP DEFINE and STEP START – STEP(08)/SNXT(09) . . . . . . . . .  
5-19 Special Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
5-19-1  
5-19-2  
5-19-3  
I/O REFRESH – IORF(97) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
END WAIT – ENDW(62) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
NOTATION INSERT – NETW(63) . . . . . . . . . . . . . . . . . . . . . . . . . . .  
67  
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Instruction Format  
Section 5-3  
5-1  
Introduction  
The K-type PCs have large programming instruction sets that allow for easy  
programming of complicated control processes. This section explains each  
instruction individually and provides the ladder diagram symbol, data areas,  
and flags used with each. Basic application examples are also provided as  
required in describing the instructions.  
The many instructions provided by the K-type PCs are described in following  
subsections by instruction group. These groups include Ladder Diagram In-  
structions, Bit Control Instructions, Timer and Counter Instructions, Data  
Shifting, Data Movement, Data Comparison, Data Conversion, BCD Calcula-  
tions, Subroutines, Step Instructions, and Special Instructions.  
Some instructions, such as timer and counter instructions, are used to control  
execution of other instructions, e.g., a TIM completion flag might be used to  
turn ON a bit when the time period set for the timer has expired. Although  
these other instructions are often used to control output bits through the  
OUTPUT instruction, they can be used to control execution of other instruc-  
tions as well. The OUTPUT instructions used in examples in this manual can  
therefore generally be replaced by other instructions to modify the program  
for specific applications other than controlling output bits directly.  
5-2  
Notation  
In the remainder of this manual, all instructions will be referred to by their  
mnemonics. For example, the OUTPUT instruction will be called OUT; the  
AND NOT instruction, AND NOT. If you’re not sure of what instruction a mne-  
monic is used for, refer to Appendix B Programming Instructions and Execu-  
tion Times.  
If an instruction is assigned a function code, it will be given in parentheses  
after the mnemonic. These function codes, which are 2-digit decimal num-  
bers, are used to input most instructions into the CPU. A table of instructions  
listed in order of function codes is also provided in Appendix B Programming  
Instructions and Execution Times.  
5-3  
Instruction Format  
Most instructions have at least one or more operands associated with them.  
Operands indicate or provide the data on which an instruction is to be per-  
formed. These are sometimes input as the actual numeric values (i.e., as  
constants), but are usually the addresses of data area words or bits that con-  
tain the data to be used. A bit whose address is designated as an operand is  
called an operand bit; a word whose address is designated as an operand is  
called an operand word. In some instructions, the word address designated  
in an instruction indicates the first of multiple words containing the desired  
data.  
Each instruction requires one or more words in Program Memory. The first  
word is the instruction word, which specifies the instruction and contains any  
definers (described below) or operand bits required by the instruction. Other  
operands required by the instruction are contained in following words, one  
operand per word. Some instructions require up to four words.  
A definer is an operand associated with an instruction and contained in the  
same word as the instruction itself. These operands define the instruction  
rather than telling what data it is to be used. Examples of definers are TC  
numbers, which are used in timer and counter instructions to create timer  
and counters, and jump numbers, which define which JUMP instruction is  
68  
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Data Areas, Definer Values, and Flags  
Section 5-4  
paired with which JUMP END instruction. Bit operands are also contained in  
the same word as the instruction itself, although these are not considered  
definers.  
5-4  
Data Areas, Definer Values, and Flags  
Each instruction is introduced with the ladder diagram symbol(s), the data  
areas that can be used with any operand(s), and the values that can be used  
for definers. With the data areas is also specified the operand names and the  
type of data required for each operand (i.e., word or bit and, for words, hexa-  
decimal or BCD).  
Not all addresses in a specified data area are necessarily allowed in an oper-  
and, e.g., if an operand requires two words, the last word in a data area can-  
not be designated because all words for a single operand must be in the  
same data area. Unless a limit is specified, any bit/word in the area can be  
used. Specific limitations for operands and definers are specified in a Limita-  
tions subsection. Refer to Section 3 Memory Areas for addressing conven-  
tions and the addresses of flags and control bits.  
Caution The IR and SR areas are considered as separate areas and both are not neces-  
sarily allowed for an operand just because one of them is. The border between  
the IR and SR area can, however, be crossed for a single operand, i.e., the last  
bit in the IR area may be specified for an operand that requires more than one  
word as long as the SR area is also allowed for that operand.  
!
The Flags subsection lists flags that are affected by execution of the instruc-  
tion. These flags include the following SR area flags.  
Abbreviation  
ER  
Name  
Instruction Execution Error flag  
Carry flag  
Bit  
1903  
1904  
1906  
1905  
1907  
CY  
EQ  
GR  
LE  
Equals flag  
Greater Than flag  
Less Than flag  
ER is the flag most often used for monitoring an instruction’s execution.  
When ER goes ON, it indicates that an error has occurred in attempting to  
execute the current instruction. The Flags subsection of each instruction lists  
possible reasons for ER being ON. ER will turn ON for any instruction if oper-  
ands are not input within established parameters. Instructions are not exe-  
cuted when ER is ON. A table of instructions and the flags they affect is pro-  
vided in Appendix D Error and Arithmetic Flag Operation.  
Designating Constants  
Although data area addresses are most often given as operands, many oper-  
ands can be input and all definers are input as constants. The range in which  
a number can be specified for a given definer or operand depends on the  
particular instruction that uses it. Constants must also be input in the form  
required by the instruction, i.e., in BCD or in hexadecimal.  
5-4-1  
Coding Other Instructions  
When combining other right-hand instructions with ladder diagram instruc-  
tions, they would appear in the same place as the OUTs used in the example  
in the preceding section. Many of these instructions, however, require more  
than one word to code.  
69  
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Data Areas, Definer Values, and Flags  
Section 5-4  
The first word of any instruction defines the instruction and provides any de-  
finers and sometimes bit operands required by the instruction. All other oper-  
ands (i.e., operand words) are placed in words after the instruction word, one  
operand to a word, in the same order as these appear in the ladder symbol  
for the instruction. Although the SV for TIM and CNT are written to the left of  
the symbol on the same line as the instruction, these are the only instructions  
for which one line in the ladder symbol must be coded as two words (i.e., two  
lines) in the mnemonic code. Also the TC number for TIMH(15) is placed on  
a second line even though it is part of the instruction word. For all other in-  
structions, each line of the ladder diagram will go into one word of mnemonic  
code.  
The address and instruction columns of the mnemonic code table are filled in  
for the instruction word only. For all other words, the left two columns are left  
blank. If the instruction word requires no definer or bit operand, the data col-  
umn for it is left blank. It is a good idea to cross though the blank data col-  
umn for all instruction words not requiring data so that the data column can  
be quickly scanned to see if any addresses have been left out.  
If an IR or SR address is used in the data column, the left side of the column  
is left blank. If any other data area is used, the data area abbreviation is  
placed on the left side and the address is place on the right side. If a con-  
stant is to be input, the number symbol (#) is placed on the left side of the  
data column and the number to be input is placed on the right side. Any num-  
bers input as definers in the instruction word do not require the number sym-  
bol on the right side. Remember, TR bits, once defined as a timer or counter,  
take a TIM (timer) or CNT (counter) prefix.  
When coding an instruction that has a function code, be sure to write in the  
function code, which will be necessary when inputting the instruction.  
The following diagram and corresponding mnemonic code illustrate the  
points described above.  
Address Instruction  
Operands  
0000  
0000  
0003  
0001  
DIFU(13) 1500  
0000  
0001  
0002  
0003  
0004  
0005  
0006  
0007  
0008  
0009  
0010  
0011  
LD  
0002  
AND  
0001  
0002  
1500  
0003  
0200  
0006  
0007  
1505  
OR  
DIFU(13)  
LD  
0200  
1505  
1500  
ADD(30)  
#0001  
0004  
HR 0  
AND NOT  
LD  
0006 0007  
AND NOT  
AND NOT  
OR LD  
AND  
1500  
00005  
ADD(30)  
TIM 00  
# 0150  
#
0001  
0004  
0
HR  
TIM 00  
0012  
0013  
LD  
0005  
00  
MOV(21)  
HR 0  
TIM  
#
0150  
00  
HR 2  
0014  
0015  
LD  
TIM  
MOV(21)  
HR  
HR  
HR  
0
2
HR 015  
0100  
0016  
0017  
LD  
015  
0100  
OUT NOT  
70  
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Data Areas, Definer Values, and Flags  
Section 5-4  
Multiple Instruction Lines  
If a right-hand instruction requires multiple instruction lines, all of the lines for  
the instruction are coded before the right-hand instruction. Each of the lines  
for the instruction are coded starting with LD or LD NOT to form ‘logic blocks’  
that are combined by the right-hand instruction. An example of this for  
CNTR(12) is shown below.  
Address Instruction  
Operands  
0000  
0000  
0200  
0001  
I
0000  
0001  
0002  
0003  
0004  
0005  
0006  
0007  
0008  
0009  
0010  
LD  
CNTR(12)  
02  
0002  
AND  
0001  
0002  
0200  
0203  
0201  
0202  
1501  
P
R
LD  
0203  
1501  
1500  
LD  
#5000  
AND NOT  
LD  
0201 0202  
HR 015  
AND NOT  
AND NOT  
OR LD  
AND  
0100  
1500  
CNTR(12)  
02  
5000  
015  
#
0011  
0012  
LD  
HR  
OUT NOT  
0100  
TR Bits  
TR bits in a program are used to output (OUT) the execution condition at the  
branching point and then to load back (LD) the execution condition when it is  
required after returning to the branch lines. Within any one instruction block,  
OUT cannot be used with the same TR address. The same TR address can,  
however, be used with LD as many times as required. The following example  
shows an instruction block using two TR bits. TR 1 is used in LD once; TR 0,  
twice.  
Address Instruction  
Operands  
0000  
TR  
0
TR  
1
0000  
0001  
0002  
0003  
0004  
0005  
0006  
0007  
0008  
0009  
0010  
0011  
0012  
0013  
0014  
LD  
0000  
0001  
0002  
0003  
0100  
0101  
0102  
0103  
OUT  
AND  
OUT  
AND  
OUT  
LD  
TR  
0
0001  
1
TR  
0002  
0100  
1
0004  
0005  
TR  
TR  
TR  
AND  
OUT  
LD  
0003  
0101  
0
AND  
OUT  
LD  
0004  
0102  
0
AND NOT  
OUT  
0005  
0103  
71  
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Data Areas, Definer Values, and Flags  
Section 5-4  
If the condition assigned 0004 was not in the diagram, the second LD using  
TR 0 would not be necessary because OUT with 0102 and the AND NOT  
with 0005 both require the same execution condition, i.e., the execution con-  
dition stored in TR 0. The diagram and mnemonic code for this program are  
shown below.  
Address Instruction  
Operands  
0000  
TR  
0
TR  
1
0000  
0001  
0002  
0003  
0004  
0005  
0006  
0007  
0008  
0009  
0010  
0011  
0012  
LD  
0000  
0001  
0002  
0003  
0100  
0101  
0102  
0103  
OUT  
AND  
OUT  
AND  
OUT  
LD  
TR  
0
0001  
1
TR  
0002  
0100  
1
TR  
TR  
AND  
OUT  
LD  
0003  
0101  
0
0005  
OUT  
AND NOT  
OUT  
0102  
0005  
0103  
Interlocks  
When coding IL(02) and ILC(03), the mnemonic code will be the same re-  
gardless of whether the instruction is drawn as branching instruction lines or  
whether IL(02) is placed on its own instruction line. If drawn as branching  
instruction lines, each branch line is coded as if it were connected to the bus  
bar, i.e., the first condition on each branch line corresponds to a LD or LD  
NOT instruction.  
IL(02)  
Address Instruction  
Operands  
0000  
0000  
0001  
0100  
0101  
0000  
0001  
0002  
0003  
0004  
0005  
0006  
0007  
0008  
0009  
0010  
0011  
0012  
0013  
LD  
IL(02)  
LD  
0001  
0100  
0002  
IL(02)  
0002  
0003  
0005  
0006  
0004  
OUT  
LD  
IL(02)  
LD  
0003  
0004  
0101  
0005  
0102  
0006  
0103  
0102  
AND NOT  
OUT  
LD  
0103  
OUT  
LD  
ILC(03)  
OUT  
ILC(03)  
72  
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Ladder Diagram Instructions  
Section 5-5  
5-5  
Ladder Diagram Instructions  
Ladder diagram instructions include ladder instructions and logic block in-  
structions. Ladder instructions correspond to the conditions on the ladder  
diagram. Logic block instructions are used to relate more complex parts of  
the diagram that cannot be programmed with ladder instructions alone.  
5-5-1  
LOAD, LOAD NOT, AND, AND NOT, OR, and OR NOT  
LOAD – LD  
Ladder Symbol  
Operand Data Areas  
B: Bit  
B
IR, SR, HR, TC, TR  
LOAD NOT – LD NOT  
Ladder Symbol  
Operand Data Areas  
B: Bit  
B
IR, SR, HR, TC, TR  
AND – AND  
Ladder Symbol  
Operand Data Areas  
B: Bit  
B
IR, SR, HR, TC, TR  
AND NOT – AND NOT  
Ladder Symbol  
Operand Data Areas  
B: Bit  
B
IR, SR, HR, TC, TR  
OR – OR  
Ladder Symbol  
Operand Data Areas  
B: Bit  
B
IR, SR, HR, TC, TR  
OR NOT – OR NOT  
Ladder Symbol  
Operand Data Areas  
B: Bit  
B
IR, SR, HR, TC, TR  
Limitations  
There is no limit in the number of any of these instructions or in the order in  
which they must be used as long as the memory capacity of the PC is not  
exceeded.  
73  
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Ladder Diagram Instructions  
Section 5-5  
Description  
These six basic instructions correspond to the conditions on a ladder dia-  
gram. As described in Section 4 Writing and Inputting the Program, the  
status of the bits assigned to each instruction determines the execution con-  
ditions for all other instructions. Each of these instructions can be used as  
many times and a bit address can be used in as many of these instructions  
as required.  
The status of the bit operand (B) assigned to LD or LD NOT determines the  
first execution condition. AND takes the logical AND between the execution  
condition and the status of its bit operand; AND NOT, the logical AND be-  
tween the execution condition and the inverse of the status of its bit operand.  
OR takes the logical OR between the execution condition and the status of its  
bit operand; OR NOT, the logical OR between the execution condition and  
the inverse of the status of its bit operand. The ladder symbol for loading TR  
bits is different from that shown above. Refer to Section 4 Writing and Input-  
ting the Program.  
Flags  
There are no flags affected by these instructions.  
5-5-2  
AND LOAD and OR LOAD  
AND LOAD – AND LD  
0000  
0001  
0002  
0003  
Ladder Symbol  
OR LOAD – OR LD  
0000  
0001  
Ladder Symbol  
0002  
0003  
Description  
When the above instructions are combined into blocks that cannot be logi-  
cally combined using only OR and AND operations, AND LD and OR LD are  
used. Whereas AND and OR operations logically combine a bit status and an  
execution condition, AND LD and OR LD logically combine two execution  
conditions, the current one and the last unused one.  
AND LD and OR LD instruction are not necessary to draw ladder diagrams,  
nor are they necessary when inputting ladder diagrams directly, as is possi-  
ble from the GPC. They are required, however, to convert the program to and  
input it in mnemonic form.  
In order to reduce the number of programming instruction required, a basic  
understanding of logic block instructions is required.  
Flags  
There are no flags affected by these instructions.  
74  
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Bit Control Instructions  
Section 5-6  
5-6  
Bit Control Instructions  
There are five instructions that can be used generally to control individual bit  
status. These are OUT, OUT NOT, DIFU(13), DIFD(14), and KEEP(11).  
These instructions are used to turn bits ON and OFF in different ways.  
5-6-1  
OUTPUT and OUTPUT NOT – OUT and OUT NOT  
OUTPUT – OUT  
Ladder Symbol  
Ladder Symbol  
Operand Data Areas  
B: Bit  
B
B
IR, HR, TR  
OUTPUT NOT –  
OUT NOT  
Operand Data Areas  
B: Bit  
IR, HR, TR  
Limitations  
Description  
Any output bit can be used in only one instruction that controls its status. See  
3-3 Internal Relay (IR) Area for details.  
OUT and OUT NOT are used to control the status of the designated bit ac-  
cording to the execution condition.  
OUT turns ON the designated bit for a ON execution condition, and turns  
OFF the designated bit for an OFF execution condition. OUT with a TR bit  
appears at a branching point rather than at the end of an instruction line.  
OUT NOT turns ON the designated bit for a OFF execution condition, and  
turns OFF the designated bit for an ON execution condition.  
OUT and OUT NOT can be used to control execution by turning ON and OFF  
bits that are assigned to conditions on the ladder diagram, thus determining  
execution conditions for other instructions. This is particularly helpful when a  
complex set of conditions can be used to control the status of a single work  
bit, and then that work bit can be used to control other instructions.  
The length of time that a bit is ON or OFF can be controlled by combining the  
OUT or OUT NOT with TIM. Refer to Examples under 5-11-1 TIMER – TIM  
for details.  
Flags  
There are no flags affected by these instructions.  
5-6-2  
DIFFERENTIATE UP and DIFFERENTIATE DOWN –  
DIFU(13) and DIFD(14)  
Ladder Symbol  
Operand Data Areas  
B: Bit  
DIFU(13) B  
IR, HR  
Ladder Symbol  
Operand Data Areas  
B: Bit  
DIFD(14) B  
IR, HR  
75  
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Bit Control Instructions  
Section 5-6  
Limitations  
Any output bit can be used in only one instruction that controls its status. See  
3-3 Internal Relay (IR) Area for details.  
Description  
DIFU(13) and DIFD(14) are used to turn the designated bit ON for one cycle  
only.  
Whenever executed, DIFU(13) compares its current execution with the previ-  
ous execution condition. If the previous execution condition was OFF and  
and current one is ON, DIFU(13) will turn ON the designated bit. If the previ-  
ous execution condition was ON and the current execution condition is either  
ON or OFF, DIFU(13) will turn the designated bit OFF or do nothing (i.e., if  
the designated bit is already OFF). The designated bit will thus never be ON  
for longer than one cycle assuming it is executed each cycle (see Precau-  
tions, below).  
Whenever executed, DIFD(14) compares its current execution with the previ-  
ous execution condition. If the previous execution condition was ON and the  
current one is OFF, DIFD(14) will turn ON the designated bit. If the previous  
execution condition was OFF and the current execution condition is either  
ON or OFF, DIFD(14) will turn the designated bit OFF or do nothing (i.e., if  
the designated bit is already OFF). The designated bit will thus never be ON  
for longer than one cycle.  
These instructions are used when a single-cycle execution of a particular in-  
struction is desired. Examples of these are shown below.  
DIFU(13) and DIFD(14) operation can be tricky when used in programming  
between IL and ILC, between JMP and JME, or in subroutines. Refer to 5-7  
INTERLOCK and INTERLOCK CLEAR – IL(02) and ILC(03) and 5-8 JUMP  
and JUMP END – JMP(04)/JME(05) for details. A total of 48  
DIFU(13)/DIFD(14) can be used in a program. If more than 48 are used in a  
program only the first 48 will be executed and all others will be ignored.  
DIFU(13)/DIFD(14) are useful when used in conjunction with CMP(20) or  
MOV(21), see Example below.  
Flags  
There are no flags affected by these instructions.  
Example  
In diagram A, below, CMP(20) will compare the contents of the two operand  
words (HR 1 and DM 00) whenever it is executed with an ON execution con-  
dition and set the arithmetic flags (GR, EQ, and LE) accordingly. If the execu-  
tion condition remains ON, flag status may be changed each cycle if the con-  
tents of one or both operands change. Diagram B, however, shows how  
DIFU(13) can be used to ensure that CMP(20) is executed only once each  
time the desired execution condition goes ON.  
0000  
Address Instruction  
Operands  
0000  
CMP(20)  
HR 1  
0000  
0001  
LD  
CMP(20)  
DM 00  
Diagram A  
HR  
DM  
1
00  
0000  
1000  
DIFU(13) 1000  
Address Instruction  
Operands  
0000  
0001  
0002  
0003  
LD  
0000  
1000  
1000  
CMP(20)  
HR 1  
DIFU(13)  
LD  
DM 00  
Diagram B  
CMP(20)  
HR  
DM  
1
00  
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Bit Control Instructions  
Section 5-6  
5-6-3  
KEEP – KEEP(11)  
Ladder Symbol  
Operand Data Areas  
S
KEEP(11)  
B: Bit  
B
IR, HR  
R
Description  
KEEP(11) is used to maintain the status of the designated bit based on two  
execution conditions. These execution conditions are labeled S and R. S is  
the set input; R, the reset input. KEEP(11) operates like a latching relay that  
is set by S and reset by R.  
When S turns ON, the designated bit will go ON and stay ON until reset, re-  
gardless of whether S stays ON or goes OFF. When R turns ON, the desig-  
nated bit will go OFF and stay OFF until reset, regardless of whether R stays  
ON or goes OFF. The relationship between execution conditions and  
KEEP(11) bit status is shown below.  
S execution condition  
R execution condition  
Status of B  
Notice that KEEP(11) operates like a self-maintaining bit. The following two  
diagrams would function identically, though the one using KEEP(11) requires  
one less instruction to program and would maintain status even in an inter-  
locked program section.  
0002 0003  
0500  
Address Instruction  
Operands  
0002  
0500  
0000  
0001  
0002  
0003  
LD  
OR  
0500  
0003  
0500  
AND NOT  
OUT  
0002  
0003  
S
R
Address Instruction  
Operands  
KEEP(11)  
0000  
0001  
0002  
LD  
0002  
0003  
0500  
0500  
LD  
KEEP(11)  
Flags  
There are no flags affected by this instruction.  
77  
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INTERLOCK and INTERLOCK CLEAR – IL(02) and ILC(03)  
Section 5-7  
Precautions  
Never use an input bit in an normally closed condition on the reset (R) for  
KEEP(11) when the input device uses an AC power supply. The delay in  
shutting down the PC’s DC power supply (relative to the AC power supply to  
the input device) can cause the designated bit of KEEP(11) to be reset. This  
situation is shown below.  
Input Unit  
A
S
KEEP(11)  
NEVER  
HR 000  
A
R
Bits used in KEEP are not reset in interlocks. Refer to the 5-7 INTERLOCK  
and INTERLOCK CLEAR – IL(02) and ILC(03) for details.  
Example  
If a HR bit is used, bit status will be retained even during a power interrup-  
tion. KEEP(11) can thus be used to program bits that will maintain status af-  
ter restarting the PC following a power interruption. An example of this that  
can be used to produce a warning display following a system shutdown for  
an emergency situation is shown below. Bits 0002, 0003, and 0004 would be  
turned ON to indicate some type of system error. Bit 0005 would be turned  
ON to reset the warning display. HR 000, which is turned ON for any of the  
three bits which indicates emergency situation, is used to turn ON the warn-  
ing indicator through 0500.  
0002  
0003  
Address Instruction  
Operands  
0002  
S
0000  
0001  
0002  
0003  
0004  
0005  
0006  
LD  
KEEP(11)  
HR 000  
OR  
0003  
0004  
0005  
000  
Indicates  
emergency  
situation  
OR  
LD  
0004  
KEEP(11)  
LD  
HR  
HR  
000  
Reset input  
0005  
OUT  
0500  
R
HR 000  
Activates  
warning  
display  
0500  
KEEP(11) can also be combined with TIM to produce delays in turning bits  
ON and OFF. Refer to 5-11-1 TIMER – TIM for details.  
5-7  
INTERLOCK and INTERLOCK CLEAR – IL(02) and ILC(03)  
Ladder Symbol  
IL(02)  
Ladder Symbol  
ILC(03)  
Description  
IL(02) is always used in conjunction with ILC(03) to create interlocks. Inter-  
locks are used to enable branching in the same way as can be achieved with  
TR bits, but treatment of instructions between IL(02) and ILC(03) differs from  
that with TR bits when the execution condition for IL(02) is OFF. If the execu-  
tion condition of IL(02) is ON, the program will be executed as written, with  
an ON execution condition used to start each instruction line from the point  
where IL(02) is located through ILC(03).  
78  
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INTERLOCK and INTERLOCK CLEAR – IL(02) and ILC(03)  
Section 5-7  
If the execution condition for IL(02) condition is OFF, the interlocked section  
between IL(02) and ILC(03) will be treated as shown in the following table:  
Instruction  
OUT and OUT NOT  
Treatment  
Designated bit turned OFF.  
Reset.  
TIM and TIMH(15)  
CNT, CNTR(12)  
KEEP(11)  
PV maintained.  
Bit status maintained.  
Not executed (see below).  
Not executed.  
DIFU(13) and DIFD(14)  
All others  
IL(02) and ILC(03) do not necessarily have to be used in pairs. IL(02) can be  
used several times in a row, with each IL(02) creating an interlocked section  
through the next ILC(03). ILC(03) cannot be used unless there is at least one  
IL(02) between it and any previous ILC(03).  
DIFU(13) and DIFD(14) in  
Interlocks  
Changes in the execution condition for a DIFU(13) or DIFD(14) are not re-  
corded if the DIFU(13) or DIFD(14) is in an interlocked section and the exe-  
cution condition for the IL(02) is OFF. When DIFU(13) or DIFD(14) is ex-  
ecuted in an interlocked section immediately after the execution condition for  
the IL(02) has gone ON, the execution condition for the DIFU(13) or  
DIFD(14) will be compared to the execution condition that existed before the  
interlock became effective (i.e., before the interlock condition for IL(02) went  
OFF). The ladder diagram and bit status changes for this are shown below.  
The interlock is in effect while 0000 is OFF. Notice that 1000 is not turned ON  
at the point labeled A even though 0001 has turned OFF and then back ON.  
0000  
0001  
Address Instruction  
Operands  
0000  
IL(02)  
DIFU(13) 1000  
ILC(03)  
0000  
0001  
0002  
0003  
0004  
LD  
IL(02)  
LD  
0001  
1000  
DIFU(13)  
ILC(03)  
A
ON  
OFF  
0000  
ON  
0001  
1000  
OFF  
ON  
OFF  
Precautions  
There must be an ILC(03) following any one or more IL(02).  
Although as many IL(02) as necessary can be used with one ILC(03),  
ILC(03) cannot be used consecutively without at least one IL(02) in between,  
i.e., nesting is not possible. Whenever a ILC(03) is executed, all interlocks  
are cleared.  
When more than one IL(02) is used with a single ILC(03), an error message  
will appear when the program check is performed, but execution will proceed  
normally.  
Flags  
There are no flags affected by these instructions.  
79  
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JUMP and JUMP END – JMP(04) and JME(05)  
Section 5-8  
Example  
The following diagram shows IL(02) being used twice with one ILC(03).  
Address Instruction  
Operands  
0000  
0001  
0002  
IL(02)  
0000  
0001  
0002  
0003  
LD  
0000  
IL(02)  
LD  
TIM 11  
0001  
11  
#0015  
1.5 s  
TIM  
#
0015  
0002  
IL(02)  
0004  
0005  
0006  
0007  
0008  
0009  
LD  
0003  
0100  
0004  
IL(02)  
LD  
CP  
R
CNT 01  
IR 10  
0003  
0004  
0100  
01  
AND NOT  
LD  
CNT  
0005  
10  
0502  
0010  
0011  
0012  
LD  
0005  
0502  
OUT  
ILC(03)  
ILC(03)  
When the execution condition for the first IL(02) is OFF, TIM 11 will be reset  
to 1.5 s, CNT 01 will not be changed, and 0502 will be turned OFF. When the  
execution condition for the first IL(02) is ON and the execution condition for  
the second IL(02) is OFF, TIM 11 will be executed according to the status of  
0001, CNT 01 will not be changed, and 0502 will be turned OFF. When the  
execution conditions for both the IL(02) are ON, the program will execute as  
written.  
5-8  
JUMP and JUMP END – JMP(04) and JME(05)  
Ladder Symbols  
Definer Values  
N: Jump number  
JMP(04) N  
# (00 to 08)  
Ladder Symbols  
Definer Values  
N: Jump number  
JME(05) N  
# (00 to 08)  
Limitations  
Description  
Jump numbers 01 through 08 may be used only once in JMP(04) and once in  
JME(05), i.e., each can be used to define one jump only. Jump number 00  
can be used as many times as desired.  
JMP(04) is always used in conjunction with JME(05) to create jumps, i.e., to  
skip from one point in a ladder diagram to another point. JMP(04) defines the  
point from which the jump will be made; JME(05) defines the destination of  
the jump. When the execution condition for JMP(04) in ON, no jump is made  
and the program is executed as written. When the execution condition for  
JMP(04) is OFF, a jump is made to the JME(05) with the same jump number  
and the instruction following JME(05) is executed next.  
If the jump number for JMP(04) is between 01 and 08, jumps, when made,  
will go immediately to JME(05) without executing any instructions in between.  
The status of timers, counters, bits used in OUT, bits used in OUT NOT, and  
all other status controlled by the instructions between JMP(04) and JMP(05)  
80  
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NO OPERATION – NOP(00)  
Section 5-10  
will not be changed. Each of these jump numbers can be used to define one  
jump. Because all of instructions between JMP(04) and JME(05) are skipped,  
jump numbers 01 through 08 can be used to reduce cycle time.  
If the jump number for JMP(04) is 00, the CPU will look for the next JME(05)  
with a Jump number of 00. To do so, it must search through the program,  
causing a longer cycle time than for other jumps (i.e., longer when the execu-  
tion condition is OFF). The status of timers, counters, bits used in OUT, bits  
used in OUT NOT, and all other status controlled by the instructions between  
JMP(04) 00 and JMP(05) 00 will not be changed. Jump number 00 can be  
used as many times as desired. A jump from JMP(04) 00 will always go to  
the next JME(05) 00 in the program. It is thus possible to use JMP(04) 00  
consecutively and match them all with the same JME(05) 00. It makes no  
sense, however, to used JME(05) 00 consecutively, because all jumps made  
to them will end at the first JME(05) 00.  
Although DIFU(13) and DIFD(14) are designed to turn ON the designated bit  
for one cycle, they will not necessarily do so when written between JMP(04)  
and JMP (05). Once either DIFU(13) or DIFD(14) has turned ON a bit, it will  
remain ON until the next time DIFU(13) or DIFD(14) is executed again. In  
normal programming, this means the next cycle. In a jump, it means the next  
time the jump from JMP(04) to JME(05) is not made, i.e., if a bit is turned ON  
by DIFU(13) or DIFD(14) and then a jump is made that skips the DIFU(13) or  
DIFD(14), the designated bit will remain ON until the next time the execution  
condition for the JMP(04) controlling the jump is ON.  
DIFU(13) and DIFD(14)  
in Jumps  
Precautions  
Flags  
When JMP(04) and JME(05) are not used in pairs, an error message will ap-  
pear when the program check is performed. Although this message also ap-  
pears if JMP(04) 00 and JME(05) 00 are not used in pairs, the program will  
execute properly as written.  
There are no flags affected by these instructions.  
5-9  
END – END(01)  
Ladder Symbol  
END(01)  
Description  
END(01) is required as the last instruction in any program. No instruction  
written after END(01) will be executed. END(01) can be placed anywhere in  
the program to execute all instructions up to that point, as is sometimes done  
to debug a program, but it must be removed to execute the remainder of the  
program.  
If there is no END(01) in the program, no instructions will be executed and  
the error message “NO END INST” will appear.  
Flags  
END(01) turns OFF ER, CY, GR, EQ, and LE.  
5-10 NO OPERATION – NOP(00)  
Description  
NOP(00) is not generally required in programming and there is no ladder  
symbol for it. When NOP(00) is found in a program, nothing is executed and  
the next instruction is moved to. When memory is cleared prior to program-  
ming, NOP(00) is written at all addresses. NOP(00) can be input through the  
00 function code.  
Flags  
There are no flags affected by NOP(00).  
81  
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Timer and Counter Instructions  
Section 5-11  
5-11 Timer and Counter Instructions  
TIM and TIMH are decrementing ON-delay timer instructions which require a  
TC number and a set value (SV).  
CNT is a decrementing counter instruction and CNTR is a reversible counter  
instruction. Both require a TC number and a SV. Both are also connected to  
multiple instruction lines which serve as an input signal(s) and a reset.  
HDM(61) is used to create a 2-kHz high-speed drum counter; RDM(60) is  
used to create a reversible drum counter. RDM(60) cannot be used to create  
a high-speed counter. If you require a high-speed counter, use HDM(61).  
Any one TC number cannot be defined twice, i.e., once it has been used as  
the definer in any of the timer or counter instructions it cannot be used again.  
Once defined, TC numbers can be used as many times as required as oper-  
ands in instructions other than timer and counter instructions.  
TC numbers run from 00 through 47. No prefix is required when using a TC  
number as a definer in a timer or counter instruction. Once defined as a tim-  
er, a TC number can be prefixed with TIM for use as an operand in certain  
instructions. The TIM prefix is used regardless of the timer instruction that  
was used to define the timer. Once defined as a counter, a TC number can  
be prefixed with CNT for use as an operand in certain instructions. The CNT  
is also used regardless of the counter instruction that was used to define the  
counter.  
TC numbers can be designated for operands that require bit data or for oper-  
ands that require word data. When designated as an operand that requires  
bit data, the TC number accesses a bit that functions as a “completion flag”  
that indicates when the time/count has expired, i.e., the bit, which is normally  
OFF, will turn ON when the designated SV has expired. When designated as  
an operand that requires word data, the TC number accesses a memory lo-  
cation that holds the present value (PV) of the timer or counter. The PV of a  
timer or counter can thus be used as an operand in CMP(20) or any other  
instruction for which the TC area is allowed by designating the TC number  
used to define that timer or counter to access the memory location that holds  
the PV.  
Note that “TIM 00” is used to designate the Timer instruction defined with TC  
number 00, to designate the completion flag for this timer, and to designate  
the PV of this timer. The meaning of the term in context should be clear, i.e.,  
the first is always an instruction, the second is always a bit operand, and the  
third is always a word operand. The same is true of all other TC numbers  
prefixed with TIM or CNT. In explanations of ladder diagrams, the completion  
flag and PV accessed through a TC number are generally called the comple-  
tion flag or the PV of the instruction (e.g., the completion flag of TIM 00 is the  
completion flag of TC number 00, which has been defined using TIM).  
An SV can be input as a constant or as a word address in a data area. If an  
IR area word assigned to an Input Unit is designated as the word address,  
the Input Unit can be wired so that the SV can be set externally through  
thumbwheel switches or similar devices. Timers and counter wired in this  
way can be set externally only during RUN or MONITOR mode. All SVs, in-  
cluding those set externally, must be in BCD.  
82  
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Timer and Counter Instructions  
Section 5-11  
5-11-1 TIMER – TIM  
Definer Values  
N: TC number  
Ladder Symbol  
# (00 through 47)  
TIM N  
Operand Data Areas  
SV  
SV: Set value (word, BCD)  
IR, HR, #  
Limitations  
SV may be between 000.0 and 999.9 seconds. The decimal point of SV is  
not input.  
Each TC number can be used as the definer in only one timer or counter in-  
struction.  
TC 00 through TC 47 should not be used in TIM if they are required for  
TIMH(15). Refer to 5-11-2 HIGH-SPEED TIMER – TIMH(15) for details.  
Description  
A timer is activated when its execution condition goes ON and is reset (to  
SV) when the execution condition goes OFF. Once activated, TIM measures  
in units of 0.1 second from the SV. TIM accuracy is +0.0/-0.1 second.  
If the execution condition remains ON long enough for TIM to time down to  
zero, the completion flag for the TC number used will turn ON and will remain  
ON until TIM is reset (i.e., until its execution condition goes OFF).  
The following figure illustrates the relationship between the execution condi-  
tion for TIM and the completion flag assigned to it.  
ON  
Execution condition  
OFF  
ON  
Completion flag  
OFF  
SV  
SV  
Precautions  
Timers in interlocked program sections are reset when the execution condi-  
tion for IL(02) is OFF. Power interruptions also reset timers. If a timer that is  
not reset under these conditions is desired, SR area clock pulse bits can be  
counted to produce timers using CNT. Refer to 5-11-4 COUNTER – CNT for  
details.  
Program execution will continue even if a non-BCD SV is used, but timing will  
not be accurate.  
Flags  
ER:  
SV is not in BCD.  
83  
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Timer and Counter Instructions  
Section 5-11  
All of the following examples use OUT in diagrams that would generally be  
used to control output bits in the IR area. There is no reason, however, why  
these diagrams cannot be modified to control execution of other instructions.  
Examples  
Example 1:  
Basic Application  
The following example shows two timers, one set with a constant and one set  
via input word 01. Here, 0200 will be turned ON 15 seconds after 0000 goes  
ON and stays ON for at least 15 seconds. When 0000 goes OFF, the timer  
will be reset and 0200 will be turned OFF. When 0001 goes ON, TIM 01 is  
started from the SV provided through IR word 01. Bit 0201 is also turned ON  
when 0001 goes ON. When the SV in 01 has expired, 0201 is turned OFF.  
This bit will also be turned OFF when TIM 01 is reset, regardless of whether  
or not SV has expired.  
0000  
Address Instruction  
Operands  
0000  
TIM 00  
#0150  
0000  
0001  
LD  
TIM  
00  
0150  
00  
TIM 00  
0001  
#
0200  
0002  
0003  
0004  
0005  
LD  
TIM  
OUT  
LD  
0200  
0001  
01  
TIM 01  
TIM  
01  
01  
TIM 01  
0006  
0007  
AND NOT  
OUT  
TIM  
01  
0201  
0201  
Example 2:  
Extended Timers  
Timers operating longer than 999.9 seconds can be formed in two ways. One  
is by programming consecutive timers, with the completion flag of each timer  
used to activate the next timer. A simple example with two 900.0-second  
(15-minute) timers combined to functionally form a 30-minute timer.  
0000  
Address Instruction  
Operands  
0000  
TIM 01  
#9000  
0000  
0001  
LD  
900.0 s  
900.0 s  
TIM  
01  
9000  
01  
TIM 01  
#
TIM 02  
#9000  
0002  
0003  
LD  
TIM  
TIM  
02  
TIM 02  
#
9000  
02  
0200  
0004  
0005  
LD  
TIM  
OUT  
0200  
In this example, 0200 will be turned ON 30 minutes after 0000 goes ON.  
TIM can also be combined with CNT or CNT can be used to count SR area  
clock pulse bits to produce longer timers. An example is provided in 5-11-4  
COUNTER – CNT.  
Example 3:  
ON/OFF Delays  
TIM can be combined with KEEP(11) to delay turning a bit ON and OFF in  
reference to a desired execution condition. KEEP(11) is described in 5-6-3  
KEEP – KEEP(11).  
To create delays, the completion flags for two timers are used to determine  
the execution conditions for setting and resetting the bit designated for  
KEEP(11). The bit whose manipulation is to be delayed is used in KEEP(11).  
Turning ON and OFF the bit designated for KEEP(11) is thus delayed by the  
SV for the two timers. The two SV could naturally be the same if desired.  
84  
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Timer and Counter Instructions  
Section 5-11  
In the following example, 0500 would be turned ON 5.0 seconds after 0000  
goes ON and then turned OFF 3.0 seconds after 0000 goes OFF. It is neces-  
sary to use both 0500 and 0000 to determine the execution condition for TIM  
02; 0000 in an normally closed condition is necessary to reset TIM 02 when  
0000 goes ON and 0500 is necessary to activate TIM 02 when 0000 goes  
OFF, setting 0500 by resetting TIM 01.  
0000  
Address Instruction  
Operands  
0000  
TIM 01  
#0050  
0000  
0001  
LD  
5.0 s  
3.0 s  
TIM  
01  
0050  
0500  
0000  
02  
0500 0000  
#
TIM 02  
#0030  
0002  
0003  
0004  
LD  
AND NOT  
TIM  
TIM 01  
S
R
#
0030  
01  
KEEP(11)  
0500  
0005  
0006  
0007  
LD  
TIM  
TIM  
LD  
02  
TIM 02  
KEEP(11)  
0500  
0000  
0500  
5.0 s  
3.0 s  
Example 4:  
One-shot Bits  
The length of time that a bit is kept ON or OFF can be controlled by combin-  
ing TIM with OUT or OUT NOT. The following diagram demonstrates how  
this is possible. In this example, 0204 would remain ON for 1.5 seconds after  
0000 goes ON regardless of the time 0000 stays ON. This is achieved by  
using 1000, activated by 0000, to turn ON 0204. When TIM 01 comes ON  
(i.e., when the SV of TIM 01 has expired), 0204 will be turned OFF through  
TIM 01 (i.e., TIM 01 will turn ON for an normally closed condition, creating an  
OFF execution condition for OUT 0204). TIM 01 will also turn OFF 1000 the  
next cycle, resetting the one-shot.  
1000  
0000  
1000  
TIM 01  
Address Instruction  
Operands  
1000  
1000  
0000  
0001  
0002  
0003  
0004  
0005  
LD  
AND NOT  
OR  
TIM  
01  
0000  
1000  
1000  
01  
OUT  
LD  
TIM 01  
TIM  
#0015  
1.5 s  
#
0015  
1000  
01  
0006  
0007  
0008  
LD  
1000 TIM 01  
0204  
AND NOT  
OUT  
TIM  
0204  
0000  
0204  
1.5 s  
1.5 s  
85  
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Timer and Counter Instructions  
Section 5-11  
Example 5:  
Flicker Bits  
Bits can be programmed to turn ON and OFF at a regular interval while a  
designated execution condition is ON by using TIM twice. One TIM functions  
to turn ON and OFF a specified bit, i.e., the completion flag of this TIM turns  
the specified bit ON and OFF. The other TIM functions to control the opera-  
tion of the first TIM, i.e., when the first TIM’s completion flag goes ON, the  
second TIM is started and when the second TIM’s completion flag goes ON,  
the first TIM is started.  
TIM 02  
0000  
Address Instruction  
Operands  
0000  
TIM 01  
#0010  
0000  
0001  
0002  
LD  
1.0 s  
1.5 s  
AND  
TIM  
TIM  
02  
01  
TIM 01  
TIM 02  
#0015  
#
0010  
01  
0003  
0004  
LD  
TIM  
TIM 01  
TIM  
02  
0205  
#
0015  
01  
0005  
0006  
LD  
TIM  
OUT  
0205  
0000  
0205  
1.0 s  
1.5 s 1.0 s 1.5 s  
An easier but more limited method of creating a flicker bit is to AND one of  
the SR area clock pulse bits with the execution condition that is to be ON  
when the flicker bit is operating. Although this method does not use TIM, it is  
included here for comparison. This method is more limited because the ON  
and OFF times must be the same and they depend on the clock pulse bits  
available in the SR area.  
5-11-2 HIGH-SPEED TIMER – TIMH(15)  
Definer Values  
N: TC number  
Ladder Symbol  
# (00 though 47 )  
TIMH(15) N  
SV  
Operand Data Areas  
SV: Set value (word, BCD)  
IR, HR, #  
Limitations  
Description  
SV may be between 00.02 and 99.99 seconds. (Actually settings of 00.00  
and 00.01 are allowed, but 00.00 is meaningless and 00.01 is not reliable.)  
The decimal point of SV is not input.  
Each TC number can be used as the definer in only one timer or counter in-  
struction.  
A cycle time of greater than 10 ms will affect the accuracy of the timer.  
TIMH(15) operates the same as TIM except that TIMH measures in units of  
0.01 second.  
Refer to 5-11-1 TIMER – TIM for operational details and examples. All as-  
pects except for the above considerations are the same.  
86  
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Timer and Counter Instructions  
Section 5-11  
Precautions  
Timers in interlocked program sections are reset when the execution condi-  
tion for IL(02) is OFF. Power interruptions also reset timers. If a timer that is  
not reset under these conditions is desired, SR area clock pulse bits can be  
counted to produce timers using CNT. Refer to 5-11-4 COUNTER – CNT for  
details.  
Program execution will continue even if a non-BCD SV is used, but timing will  
not be accurate.  
Flags  
ER:  
SV is not in BCD.  
5-11-3 Analog Timer Unit  
The Analog Timer Unit uses two I/O words to provide four timers (T to T ).  
0
3
Each of the four timers may be set to a specific timer value (SV) within one of  
four ranges. The SV for each timer may be set using either a variable resistor  
on the Analog Timer Unit or from an external variable resistor.  
Each timer is allocated five bits within the IR words allocated to the Analog  
Timer Units. The function of these is shown below. The words shown in the  
table are as seen from the CPU, i.e., the input word goes from the Analog  
Timer Unit to the CPU, the output word, from the CPU to the Analog Timer  
Unit. The CPU receives the Time Expired flag from the Unit and sends the  
Start control bit Pause control bit and Range bits to the Unit.  
Bit  
Input word  
T Time Expired flag  
Output word  
T Start control bit  
00  
01  
02  
03  
04  
05  
0
0
T Time Expired flag  
T Start control bit  
1
1
T Time Expired flag  
2
T Start control bit  
2
T Time Expired flag  
3
T Start control bit  
3
T Pause control bit  
0
T Pause control bit  
1
06  
07  
08  
09  
10  
11  
12  
13  
14  
15  
T Pause control bit  
2
T Pause control bit  
3
T Range bits  
0
Cannot be used.  
T Range bits  
1
T Range bits  
2
T Range bits  
3
There is a SET indicator and a time expired indicator on the Analog Timer  
Unit for each timer. These indicators are lit when the corresponding timer’s  
Start control bit or Time Expired flag is ON.  
When the Start control bit is turned ON, the timer begins operation and the  
SET indicator is lit.  
When the time set with the internal or external adjustment has expired, the  
corresponding Time Expired flag is set. The time up indicator also lights.  
If the Pause control bit for a timer is turned ON from the PC, the timer will  
cease timing and the present value (PV) will be retained. Timing will resume  
when the Pause control bit is turned OFF. If the Start control bit is turned  
OFF before the set value (SV) of the timer has expired, the Time Expired flag  
will not be turned ON.  
87  
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Timer and Counter Instructions  
Section 5-11  
Timer ranges are set in the output words as shown in the following table.  
Timer  
Output  
word bit  
0.1 to 1s  
OFF  
1 to 10s  
ON  
10 to 60s  
OFF  
1 to 10m  
ON  
T
T
T
T
08  
0
1
2
3
09  
10  
11  
12  
13  
14  
15  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
OFF  
ON  
ON  
ON  
ON  
ON  
ON  
ON  
ON  
ON  
OFF  
ON  
OFF  
ON  
OFF  
ON  
OFF  
ON  
OFF  
OFF  
ON  
Example  
Setup  
This example uses an Analog Timer Unit connected to a C28K CPU. Word  
allocations are shown in the following table.  
Unit  
Input word  
Output word  
CPU  
Analog Timer Unit  
00  
02  
01  
03  
All four time’s are used. Times for two of them are adjusted on the variable  
resistors provided on the Analog Timer Unit. The other two times are ad-  
justed using external resistors. These adjustments are made as follows. Re-  
fer to the Analog Timer Unit Installation Guide for hardware details.  
Timer  
SV  
Range  
0.1 to 1 s  
Resistor adjustment  
6/10th turn clockwise  
3/10th turn clockwise  
2/10th turn clockwise  
8/10th turn clockwise  
T
T
T
T
Approx. 0.6 s  
Approx. 3 s  
0
1
2
3
1 to 10 s  
Approx. 2.6 s  
Approx. 8 min  
10 to 60 s  
1 to 10 min  
Programming  
The following program sections are used to set up the required data and pro-  
duce outputs from the four timers. The first section moves E400 into IR 06 to  
set the desired ranges (see table above). The second program section  
achieves the following operation.  
1, 2, 3... 1. IR 0500 is turned ON approximately 0.6 seconds after IR 0002 turns ON  
as the result of the action of T .  
0
2. IR 0501 is turned ON approximately 3 seconds after IR 0003 turns ON  
as the result of the action of T .  
1
3. IR 0502 is turned ON approximately 20 seconds after IR 0004 turns ON  
as the result of the action of T .  
2
4. IR 0503 is turned ON approximately 8 minutes after IR 0004 turns ON  
as the result of the action of T .  
3
88  
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Timer and Counter Instructions  
Section 5-11  
5. T and T are made inoperative if IR 0015 is turned ON.  
2
3
First Cycle Flag  
1815  
Address Instruction  
Operands  
MOV(21)  
#0400  
06  
0000  
0001  
LD  
1815  
MOV(21)  
#
0400  
06  
Content of IR O6 after MOV(21)  
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00  
1
1
1
0
0
1
0
0
0
0
0
0
0
0
0
0
Range settings  
0015  
Address Instruction  
Operands  
0015  
0606  
0607  
0000  
0001  
0002  
0003  
0004  
0005  
0006  
0007  
0008  
0009  
0010  
0011  
0012  
0013  
0014  
0015  
0016  
0017  
LD  
Used to inhibit operation of T and T .  
OUT  
OUT  
LD  
0606  
0607  
0002  
0600  
0100  
0500  
0003  
0601  
0101  
0501  
0004  
0602  
0603  
0102  
0502  
0103  
0503  
2
3
OUT  
LD  
T
Start Control Bit  
0
0002  
T started.  
0
0600  
OUT  
LD  
T
Time Expired  
0
OUT  
LD  
Flag  
0100  
0003  
0500 turned ON when time for T expires.  
0500  
0
OUT  
LD  
T
Start Control Bit  
1
OUT  
OUT  
LD  
T started.  
1
0601  
0501  
OUT  
LD  
T
Flag  
Time Expired  
1
0101  
0501 turned ON when time for T expires.  
1
OUT  
T
T
Start Control Bit  
2
3
0004  
0602  
Start Control Bit  
T and T started.  
2
3
0603  
T
Time Expired  
0102  
2
Flag  
0502 turned ON when time for T expires.  
0502  
2
T
Time Expired  
0103  
3
Flag  
0502 turned ON when time for T expires.  
0503  
3
89  
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Timer and Counter Instructions  
Section 5-11  
5-11-4 COUNTER – CNT  
Definer Values  
N: TC number  
Ladder Symbol  
# (00 through 47)  
CP  
R
CNT N  
SV  
Operand Data Areas  
SV: Set value (word, BCD)  
IR, HR, #  
Limitations  
Description  
Each TC number can be used as the definer in only one timer or counter in-  
struction.  
CNT is used to count down from SV when the execution condition on the  
count pulse, CP, goes from OFF to ON, i.e., the present value (PV) will be  
decremented by one whenever CNT is executed with an ON execution condi-  
tion for CP and the execution condition was OFF for the last execution. If the  
execution condition has not changed or has changed from ON to OFF, the  
PV of CNT will not be changed. Counter is turned ON when the PV reaches  
zero and will remain ON until the counter is reset.  
CNT is reset with a reset input, R. When R goes from OFF to ON, the PV is  
reset to SV. The PV will not be decremented while R is ON. Counting down  
from SV will begin again when R goes OFF. The PV for CNT will not be reset  
in interlocked program sections or for power interruptions.  
Changes in execution conditions, the completion flag, and the PV are illus-  
trated below. PV line height is meant to indicate changes in the PV only.  
ON  
Execution condition  
on count pulse (CP)  
OFF  
ON  
Execution condition  
on reset (R)  
OFF  
ON  
Completion flag  
OFF  
SV  
SV  
PV  
0002  
SV - 1  
0001  
SV - 2  
0000  
Precautions  
Flags  
Program execution will continue even if a non-BCD SV is used, but the SV  
will not be correct.  
ER:  
SV is not in BCD.  
90  
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Timer and Counter Instructions  
Section 5-11  
Example 1:  
Basic Application  
In the following example, the PV will be decremented whenever both 0000  
and 0001 are ON provided that 0002 is OFF and either 0000 or 0001 was  
OFF the last time CNT 04 was executed. When 150 pulses have been  
counted down (i.e., when PV reaches zero), 0205 will be turned ON.  
0000  
0002  
0001  
Address Instruction  
Operands  
0000  
CP  
R
CNT 04  
#0150  
0000  
0001  
0002  
0003  
LD  
AND  
LD  
0001  
0002  
04  
CNT 04  
CNT  
0205  
#
0150  
04  
0004  
0005  
LD  
CNT  
OUT  
0205  
Here, 0000 can be used to control when CNT is operative and 0001 can be  
used as the bit whose OFF to ON changes are being counted.  
The above CNT can be modified to restart from SV each time power is  
turned ON to the PC. This is done by using the First Cycle flag in the SR area  
(1815) to reset CNT as shown below.  
0000  
0001  
Address Instruction  
Operands  
0000  
CP  
R
CNT 04  
#0150  
0000  
0001  
0002  
0003  
0004  
LD  
0002  
1815  
AND  
LD  
0001  
0002  
1815  
04  
OR  
CNT  
CNT 04  
#
0150  
04  
0205  
0005  
0006  
LD  
CNT  
OUT  
0205  
Example 2:  
Extended Counter  
Counters that can count past 9,999 can be programmed by using one CNT to  
count the number of times another CNT has reached zero from SV.  
In the following example, 0000 is used to control when CNT 01 operates and  
CNT 01, when 0000 is ON, counts down the number of OFF to ON changes  
in 0001. CNT 01 is reset by its completion flag, i.e., it starts counting again as  
soon as its PV reaches zero. CNT 02 counts the number of times the com-  
pletion flag for CNT 01 goes ON. Bit 0002 serves as a reset for the entire  
extended counter, resetting both CNT 01 and CNT 02 when it is OFF. The  
completion flag for CNT 02 is also used to reset CNT 01 to inhibit CNT 01  
operation once PV for CNT 02 has been reached until the entire extended  
counter is reset via 0002.  
91  
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Timer and Counter Instructions  
Section 5-11  
Because in this example the SV for CNT 01 is 100 and the SV for CNT 02 is  
200, the completion flag for CNT 02 turns ON when 100 x 200 or 20,000 OFF  
to ON changes have been counted in 0001. This would result in 0203 being  
turned ON.  
0000 0001  
0002  
CP  
Address Instruction  
Operands  
0000  
CNT 01  
#0100  
0000  
0001  
0002  
0003  
0004  
0005  
LD  
AND  
LD NOT  
OR  
0001  
0002  
01  
R
CNT  
CNT  
CNT 01  
CNT 02  
CNT 01  
0002  
OR  
02  
CNT  
01  
#
0100  
01  
0006  
0007  
0008  
LD  
CNT  
LD NOT  
CNT  
0002  
02  
CP  
R
CNT 02  
#0200  
#
0200  
02  
0009  
0010  
LD  
CNT  
OUT  
0203  
CNT 02  
0203  
CNT can be used in sequence as many times as required to produce count-  
ers capable of counting down even higher values.  
Example 3:  
Extended Timers  
CNT can be used to create extended timers in two ways: by combining TIM  
with CNT and by counting SR area clock pulse bits.  
In the following example, CNT 02 counts the number of times TIM 01  
reaches zero from its SV. The completion flag for TIM 01 is used to reset TIM  
01 so that is runs continuously and CNT 02 counts the number of times the  
completion flag for TIM 01 goes ON (CNT 02 would be executed once each  
time between when the completion flag for TIM 01 goes ON and TIM 01 is  
reset by its completion flag). TIM 01 is also reset by the completion flag for  
CNT 02 so that the extended timer would not start again until CNT 02 was  
reset by 0001, which serves as the reset for the entire extended timer.  
As the SV for TIM 01 is 5.0 seconds and the SV for CNT 02 is 100, the com-  
pletion flag for CNT 02 turns ON when 5 seconds x 100 times, or 8 minutes  
and 20 seconds have expired. This would result in 0201 being turned ON.  
0000 TIM 01  
CNT 02  
Address Instruction  
Operands  
0000  
TIM 01  
#0050  
0000  
0001  
0002  
0003  
LD  
AND NOT  
AND NOT  
TIM  
TIM  
01  
02  
TIM 01  
0001  
CP  
R
CNT  
CNT 02  
#0100  
01  
#
0050  
01  
0004  
0005  
0006  
LD  
TIM  
LD  
0001  
02  
CNT 02  
CNT  
0200  
#
0100  
02  
0007  
0008  
LD  
CNT  
OUT  
0200  
In the following example, CNT 01 counts the number of times the 1-second  
clock pulse bit (1902) goes from OFF to ON. Here again, 0000 is used to  
control when CNT is operating.  
92  
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Timer and Counter Instructions  
Section 5-11  
As the SV for CNT 01 is 700, the completion flag for CNT 02 turns ON when  
1 second x 700 times, or 10 minutes and 40 seconds have expired. This  
would result in 0202 being turned ON.  
0000 1902  
0001  
CP  
Address Instruction  
Operands  
0000  
CNT 01  
#0700  
0000  
0001  
0002  
0003  
LD  
AND  
LD NOT  
CNT  
1902  
0001  
01  
R
CNT 01  
0202  
#
0700  
01  
0004  
0005  
LD  
CNT  
OUT  
0202  
Caution The shorter clock pulses may not produce accurate timers because their short  
ON times may not be read accurately for longer cycle times. In particular the  
0.02-second and 0.1-second clock pulses should not be used to create timers  
with CNT.  
!
5-11-5 REVERSIBLE COUNTER – CNTR(12)  
Definer Values  
N: TC number  
Ladder Symbol  
# (00 through 47)  
II  
CNTR(12)  
N
DI  
R
Operand Data Areas  
SV  
SV: Set value (word, BCD)  
IR, HR, #  
Limitations  
Description  
Each TC number can be used as the definer in only one timer or counter in-  
struction.  
The CNTR(12) is a reversible, up-down circular counter, i.e., it is used to  
count between zero and SV according to changes in two execution condi-  
tions, those in the increment input (II) and those in the decrement input (DI).  
The present value (PV) will be incremented by one whenever CNTR(12) is  
executed with an ON execution condition for II and the execution condition  
was OFF for II for the last execution. The present value (PV) will be decre-  
mented by one whenever CNTR(12) is executed with an ON execution condi-  
tion for DI and the execution condition was OFF for DI for the last execution.  
If OFF to ON changes have occurred in both II and DI since the last execu-  
tion, the PV will not be changed.  
If the execution conditions have not changed or has changed from ON to  
OFF for both II and DI, the PV of CNT will not be changed.  
When decremented from 0000, the present value is set to SV and the com-  
pletion flag is turned ON until the PV is decremented again. When incre-  
mented past the SV, the PV is set to 0000 and the completion flag is turned  
ON until the PV is incremented again.  
93  
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Timer and Counter Instructions  
Section 5-11  
CNTR(12) is reset with a reset input, R. When R goes from OFF to ON, the  
PV is reset to zero. The PV will not be incremented or decremented while R  
is ON. Counting will begin again when R goes OFF. The PV for CNTR(12)  
will not be reset in interlocked program sections or for power interruptions.  
Changes in II and DI execution conditions, the completion flag, and the PV  
are illustrated below starting from part way through CNTR(12) operation (i.e.,  
when reset, counting begins from zero). PV line height is meant to indicate  
changes in the PV only.  
ON  
Execution condition  
on increment (II)  
OFF  
ON  
Execution condition  
on decrement (DI)  
OFF  
ON  
Completion flag  
OFF  
SV  
SV  
PV  
SV - 1  
SV - 1  
0001  
SV - 2  
SV - 2  
0000  
0000  
Precautions  
Flags  
Program execution will continue even if a non-BCD SV is used, but the SV  
will not be correct.  
ER:  
SV is not in BCD.  
5-11-6 HIGH-SPEED DRUM COUNTER – HDM(61)  
Definer Values  
N: TC number  
Ladder Symbol  
Must be 47  
HDM(61) N  
R
Operand Data Areas  
R: Result word  
IR, HR, DM  
Limitations  
If any of the lower limits for the DM ranges are set to “0000,” the correspond-  
ing output bits are turned ON when the high-speed counter is reset.  
If the time it takes to count through some range is less than the cycle time of  
the CPU, the high-speed counter may count past between cycles and thus  
the output bit for this range may not be turned ON.  
Counting  
Time  
Lower Limit  
Upper Limit  
The count signal must be at least 250 µs (2 kHz) wide and have a duty factor  
of 1:1, as shown below.  
Input  
0000  
250 µS 250 µS  
94  
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Timer and Counter Instructions  
Section 5-11  
In the hard reset mode, the reset signal must have an ON time of at least  
250 µs.  
Input  
0001  
250 µs max.  
Description  
General  
The high-speed counter counts the signals input from an external device con-  
nected to input 0000 and, when the high-speed counter instruction is ex-  
ecuted, compares the current value with a set of ranges which have been  
preset in DM words 32 through 63. If the current value is within any of the  
preset ranges, the corresponding bit of a specified result word is turned ON.  
The bit in the result word remains ON until the current value is no longer  
within the specified range.  
An internal buffer is incremented whenever bit 0000 goes from OFF to ON.  
When the high-speed counter instruction is executed, the value in the count-  
er buffer is transferred to counter 47 which serves as the count value storage  
area.  
When using the high-speed counter, the following bits are reserved and can-  
not be used for any other purpose:  
• Input 0000 (count input)  
• Input 0001 (hard reset)  
• SR bit 1807 (soft reset)  
• TC 47 (present count value)  
• DM 32 to 63 (upper and lower limits)  
Note If a power failure occurs, the count value of the high speed counter immedi-  
ately before the power failure is retained.  
The high-speed counter is programmed differently depending on how it is to  
be reset. Two resetting modes are possible: hard-reset and soft-reset. The  
hard reset is made effective or ineffective with the DIP switch in the CPU.  
Hard Reset  
To use the hard reset, turn pins 7 and 8 ON. In this mode, input 0001 is the  
reset input. When it is turned ON, the present value in the high-speed count-  
er buffer is reset to “0000.” When the reset is ON, the count signal from input  
0000 is not accepted. When programmed with the hard reset, the high-speed  
counter would appear as below.  
0002  
Address Instruction  
Operands  
0002  
HDM(61) 47  
10  
0000  
0001  
LD  
HDM(61)  
47  
10  
95  
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Timer and Counter Instructions  
Section 5-11  
Soft Reset  
SR bit 1807 is the soft reset. When it is turned ON, the present value in the  
high-speed counter buffer is reset to “0000.” As for the hard reset, when the  
soft reset is ON, the count signal from input 0000 is not accepted. When pro-  
grammed with the soft reset, the high-speed counter would appear as below.  
Note that when the soft reset is used, the timing at which the counter buffer is  
reset may be delayed due to the cycle time of the CPU.  
0003  
0002  
Address Instruction  
Operands  
0003  
1807  
00000  
00001  
00002  
00003  
LD  
OUT  
LD  
1807  
0002  
47  
HDM(61) 47  
10  
HDM(61)  
10  
If required, both the hard reset and the soft reset can be used together.  
Upper and Lower Limit  
Setting  
The following table shows the upper and lower limits that need to be set in  
DM 32 through DM 63. In this table, “S” denotes the present value of counter  
47 and R is the results word.  
Lower  
limit  
Upper  
limit  
Present value of the counter  
Bit of R  
that turns  
ON  
DM 32  
DM 33  
00  
01  
02  
03  
04  
05  
06  
07  
08  
09  
10  
11  
12  
13  
14  
15  
Value of DM 32 ≤ S ≤ value of DM 33  
Value of DM 34 ≤ S ≤ value of DM 35  
Value of DM 36 ≤ S ≤ value of DM 37  
Value of DM 38 ≤ S ≤ value of DM 39  
Value of DM 40 ≤ S ≤ value of DM 41  
Value of DM 42 ≤ S ≤ value of DM 43  
Value of DM 44 ≤ S ≤ value of DM 45  
Value of DM 46 ≤ S ≤ value of DM 47  
Value of DM 48 ≤ S ≤ value of DM 49  
Value of DM 50 ≤ S ≤ value of DM 51  
Value of DM 52 ≤ S ≤ value of DM 53  
Value of DM 54 ≤ S ≤ value of DM 55  
Value of DM 56 ≤ S ≤ value of DM 57  
Value of DM 58 ≤ S ≤ value of DM 59  
Value of DM 60 ≤ S ≤ value of DM 61  
Value of DM 62 ≤ S ≤ value of DM 63  
DM 34  
DM 36  
DM 38  
DM 40  
DM 42  
DM 44  
DM 46  
DM 48  
DM 50  
DM 52  
DM 54  
DM 56  
DM 58  
DM 60  
DM 62  
DM 35  
DM 37  
DM 39  
DM 41  
DM 43  
DM 45  
DM 47  
DM 49  
DM 51  
DM 53  
DM 55  
DM 57  
DM 59  
DM 61  
DM 63  
96  
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Timer and Counter Instructions  
Section 5-11  
The values must be four-digit BCD in the range 0000 to 9999. Note that fail-  
ure to enter BCD values will not activate the ERR flag. Always set a lower  
limit which is less than the corresponding upper limit. MOV is useful in setting  
limits. The following ladder diagram shows the use of MOV for setting limits  
and the associated timing diagram shows the state of the relevant bits of the  
result word (IR 05) as the counter is incremented.  
1813 (normally ON)  
MOV(21)  
#0200  
DM 32  
MOV(21)  
#1500  
DM 33  
Transfers  
preset  
value to  
DM 32 to  
35  
MOV(21)  
#0600  
DM 34  
MOV(21)  
#2000  
DM 35  
Address Instruction  
Operands  
1813  
0000  
0001  
LD  
0002 (start input)  
MOV(21)  
HDM(61) 47  
05  
#
0200  
32  
DM  
Corresponding  
result word is 05  
0002  
0003  
0004  
MOV(21)  
MOV(21)  
MOV(21)  
#
1500  
33  
DM  
Start input 0002  
Count input 0000  
#
0600  
34  
DM  
#
2000  
35  
200  
1500  
DM  
Output 0500  
Output 0501  
0005  
0006  
LD  
0002  
47  
600  
2000  
HDM(61)  
05  
Response Speed  
Precautions  
The maximum response speed of the high-speed counter hardware is 2 kHz.  
Note however that the start signal, reset signal (in the case of soft reset), and  
corresponding outputs are all processed by software. Because of this, re-  
sponse may be delayed by the cycle time.  
When programming the high-speed counter with the GPC, “00” is displayed  
on each of the three lines below the instruction code (HDM(61)). Do not alter  
the second and third lines; if they are not “00,” an error occurs when an at-  
tempt is made to transfer the program from the GPC to the PC.  
Do not program the high-speed counter between JMP and JME. The  
high-speed counter can be programmed between IL and ILC. However, the  
hard reset signal remains active, causing the corresponding output(s) to turn  
ON or OFF, even when the IL condition is OFF.  
97  
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Timer and Counter Instructions  
Section 5-11  
Examples  
Extending the Counter  
The high-speed counter normally provides 16 output bits. If more than 16 are  
required, the high-speed counter may be programmed more than once. In  
the following program example, the high-speed counter is used twice to pro-  
vide 32 output bits.  
1813 (normally ON)  
Address Instruction  
Operands  
1813  
MOV(21)  
“S1”  
0000  
0001  
LD  
MOV(21)  
DM 32  
“S1”  
32  
DM  
DM  
DM  
HR  
Transfers limit values  
S1 to S32 to DM.  
Output thru HR 0  
0002  
0003  
MOV(21)  
MOV(21)  
MOV(21)  
“S2”  
“S2”  
33  
DM 33  
“S32”  
35  
0004  
0005  
LD  
0002  
47  
MOV(21)  
“S32”  
HDM(61)  
0
DM 35  
0006  
0007  
LD  
1813  
MOV(21)  
0002  
“S33”  
32  
HDM(61) 47  
HR 0  
DM  
DM  
DM  
HR  
A
0008  
0009  
MOV(21)  
MOV(21)  
“S34”  
33  
1813 (normally ON)  
MOV(21)  
“S33”  
“S64”  
35  
DM 32  
0010  
0011  
LD  
0002  
47  
HDM(61)  
Transfers limit values  
S33 to S64 to DM.  
Output thru HR 1  
1
MOV(21)  
“S34”  
DM 33  
MOV(21)  
“S64”  
DM 35  
0002  
HDM(61) 47  
HR 1  
B
In this program, each bit in the specified words, HR 0 and HR 1 are turned  
ON under the following conditions (where S is the present count value of the  
high-speed counter stored as the data of CNT 47):  
Where S1 ≤ S ≤ S2,  
Where S3 ≤ S ≤ S4,  
HR 000 is ON.  
HR 001 is ON.  
Where S31 ≤ S ≤ S32, HR 015 is ON.  
Where S33 ≤ S ≤ S34, HR 100 is ON.  
Where S63 ≤ S ≤ S64, HR 115 is ON.  
98  
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Timer and Counter Instructions  
Section 5-11  
Note that in the program just mentioned, the present value in the counter  
buffer is transferred to counter number 47 at points A and B. In this case, if  
S31 (=1,000) < S < S32 (=2,000) and S33 (=2,000) < S < S34 (=3,000), and  
if the present count value of the first high-speed counter (at point A) is 1,999  
and that of the second counter (at point B) is 2,003, HR 015 and HR100 may  
be simultaneously turned ON. If it is necessary to avoid this, set the values of  
S32 and S33 so that there is a value difference equivalent to the time lag  
from points A to B. For example, set the value of S32 to 2,000 and that of  
S33 to 2,010.  
More than 16 output bits may be obtained using CMP.  
1813 (normally ON)  
Address Instruction  
Operands  
1813  
CMP(20)  
CNT 47  
#6850  
0000  
0001  
LD  
CMP(20)  
CNT  
#
47  
6850  
1905  
0600  
1905 (GR)  
0600  
0002  
0003  
AND  
OUT  
In the above program, output 0600 is turned ON when the following condition  
is satisfied, where S is the present count value of the high-speed counter:  
6,850 < S ≤ 9,999.  
1813 (normally ON)  
Address Instruction  
Operands  
1813  
CMP(20)  
CNT 47  
#0300  
0000  
0001  
LD  
CMP(20)  
CNT  
#
47  
0300  
1905  
1000  
1813  
1905 (GR)  
1000  
0002  
0003  
0004  
0005  
AND  
OUT  
LD  
CMP(20)  
CNT  
#
47  
2300  
1907  
1001  
1000  
1001  
0601  
1813 (normally ON)  
CMP(20)  
CNT 47  
#2300  
0006  
0007  
0008  
0009  
0010  
AND  
OUT  
LD  
AND  
OUT  
1907 (LE)  
1001  
0601  
1000 1001  
In the above program, output 0601 is turned ON when the following condition  
is satisfied, where S is the present count value of the high-speed counter:  
300 < S < 2,300.  
Cascade Connection  
(Counting Past 9,999)  
The number of digits of the upper and lower limits of the high-speed counter  
can be increased from four to eight by using the high-speed counter together  
with CNTR and CMP.  
99  
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Timer and Counter Instructions  
Section 5-11  
The high-speed counter is a ring counter and thus when its present count  
value is incremented from 9999 to 0000, the completion flag of CNT 47 is  
turned ON for one cycle. By using this flag as an input to the UP input of the  
reversible counter (i.e., cascade connection) you can increase the number of  
digits to eight. Although an ordinary counter can be cascade-connected to  
the high-speed counter, programming is easier with CNTR since an ordinary  
counter is decrementing.  
1813 (normally ON)  
Address Instruction  
Operands  
1813  
MOV(21)  
#0000  
0000  
0001  
LD  
MOV(21)  
DM 32  
#
0000  
32  
DM  
0002  
MOV(21)  
MOV(21)  
#5000  
#
5000  
33  
DM  
DM 33  
0003  
0004  
LD  
0002  
47  
HDM(61)  
0002 (start input)  
HDM(61) 47  
HR 0  
HR  
0
0005  
0006  
0007  
0008  
LD  
CNT  
47  
CNT 47  
LD  
1814  
1810  
II  
LD  
CNTR(12)  
46  
CNTR(12)  
1814 (normally OFF)  
1810 (turns On for 1 cycle upon hard reset)  
1813 (normally ON)  
DI  
R
46  
9999  
1813  
#9999  
#
0009  
0010  
LD  
CMP(20)  
CNT  
#
46  
0002  
1906  
000  
CMP(20)  
CNT 46  
#0002  
0011  
0012  
0013  
AND  
AND  
OUT  
HR  
0500  
1906 (EQ) HR 000  
0500  
In the above program example, output 0500 is turned ON when the following  
condition is satisfied (where S is the present count value of the high-speed  
counter):  
20,000 ≤ S ≤ 25,000.  
Note In hard reset mode, program SR 1810, which turns ON for one cycle time  
upon input of the hard reset signal, to CNTR as the reset input. Unless CNTR  
and CMP are programmed immediately after the high-speed counter, the cor-  
rect corresponding outputs may not be produced.  
Packaging Machine  
The high-speed counter is very useful in the following application. Here,  
packages are being carried on a conveyor belt at random intervals. Some of  
them are spaced far apart and others are clustered together, making it im-  
possible to accurately detect and count them with photoelectric switches  
alone.  
By presetting the number of pulses generated when a single package is de-  
tected and by counting those pulses, the number of packages can be accu-  
rately counted, regardless of whether the packages are spaced or clustered.  
100  
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Timer and Counter Instructions  
Section 5-11  
The following diagram shows the packaging system and the corresponding  
timing chart.  
Reflective photoelectric  
switch PH1 (0002)  
Motor 2 (M2)  
Rear limit switch for  
Rotary encoder E6A  
pusher LS1 (0003)  
(0000)  
Fixed stopper  
Pusher  
Front limit switch for  
pusher LS2 (0004)  
Packages  
Upper limit switch for stopper LS3 (0005)  
Moving stopper  
Motor 1 (M1)  
Lower limit switch for stopper LS4 (0006)  
PH1  
(0002)  
E6A  
(0000)  
M1 rise  
(0100)  
LS4  
(0006)  
LS3  
(0005)  
M2  
forward  
(0102)  
LS2  
(0004)  
LS1  
(0003)  
M2  
backward  
(0103)  
M1 fall  
(0101)  
In this example, “x” is the number of pulses per package. To detect four pack-  
ages therefore, 4x must be set as the preset value of the high-speed counter.  
101  
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Timer and Counter Instructions  
Section 5-11  
Here is the program example for the application.  
1813 (normally ON)  
MOV(21)  
#0905  
DM 32  
MOV(21)  
#1150  
DM 33  
Transfer limit values  
MOV(21)  
#1450  
DM 34  
MOV(21)  
#1550  
DM 35  
1815  
0005  
0002  
Resets counter  
upon power  
application or at  
stopper  
1807  
operation  
Counts pulses  
from encoder  
only when PH1  
is ON  
HDM(61) 47  
HR 0  
HR 000  
HR 001  
0100  
0011  
0006  
0005  
0100  
Normally counts 4  
packages. When  
input 0011 is ON,  
counts 6 packages.  
Pushes stopper up  
at count-up to stop  
following packages  
0011  
0003  
0102  
0005  
0102  
0004  
0103  
0100  
0004  
0102  
Pushes  
packages  
out  
0003  
Returns pusher  
to original  
position after  
operation  
0103  
0003  
1000  
DIFU(13) 1000  
0101  
0005  
0006  
Pushes stopper  
down and  
continues  
operating when  
pusher returns  
to original  
0101  
position  
102  
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Timer and Counter Instructions  
Section 5-11  
Address Instruction  
Operands  
1813  
Address Instruction  
Operands  
0000  
0001  
LD  
0014  
0015  
0016  
0017  
0018  
0019  
0020  
0021  
0022  
0023  
0024  
0025  
0026  
0027  
0028  
0029  
0030  
0031  
0032  
0033  
0034  
0035  
0036  
OR LD  
AND  
MOV(21)  
0006  
#
0905  
32  
OR  
0100  
0005  
0100  
0005  
0003  
0102  
0100  
0004  
0102  
0004  
0102  
0103  
0003  
0103  
0003  
1000  
1000  
0005  
0101  
0006  
0101  
DM  
AND NOT  
OUT  
0002  
0003  
0004  
MOV(21)  
MOV(21)  
MOV(21)  
#
1150  
33  
LD  
DM  
AND  
OR  
#
1450  
34  
AND NOT  
AND NOT  
OUT  
DM  
#
1550  
35  
LD  
DM  
AND NOT  
OR  
0005  
0006  
0007  
0008  
0009  
LD  
1815  
0005  
1807  
0002  
47  
OR  
AND NOT  
OUT  
OUT  
LD  
LD  
HDM(61)  
DIFU(13)  
LD  
HR  
HR  
0
0010  
0011  
0012  
0013  
LD  
000  
0011  
001  
0011  
AND  
AND NOT  
LD  
OR  
HR  
AND NOT  
OUT  
AND  
5-11-7 REVERSIBLE DRUM COUNTER – RDM(60)  
Definer Values  
N: TC number  
Ladder Symbol  
Must be 46  
RDM(60) N  
R
Operand Data Areas  
R: Result word  
IR, HR, DM  
Limitations  
Description  
If any of the lower limits for the DM ranges are set to “0000,” the correspond-  
ing output bits are turned ON when the counter is reset.  
The reversible drum counter is a ring counter with a counting range of 0000  
to 9999. It requires three input signals to operate: a count input, reset input,  
and UP/DOWN selection input. For these inputs, SR bits 1804 to 1806 are  
reserved and cannot be used for any other purpose while the RDM(60) is  
being used.  
Operation is enabled when RDM(60) is executed with an ON execution con-  
dition. RDM(60) increments when the UP/DOWN selection input (1806) is  
OFF. When this input is ON, RDM(60) decrements. Incrementing or decre-  
menting occurs on the rising edge of the count input signal. When RDM(60)  
is executed by the CPU, the value in the counter buffer is transferred to CNT  
46.  
103  
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Timer and Counter Instructions  
Section 5-11  
The transferred count value is then compared with the upper and lower limits  
of a set of ranges which have been preset in DM 00 through DM 31. If the  
current value is within any of the preset ranges, the corresponding bit of the  
results word, R, is turned ON. The bit in the result word will remain ON until  
the current value is no longer within the specified range.  
When the reset input (1804) goes ON, the present value is cleared to 0000,  
even if the start input is OFF, and all bits in R are set.  
Note RDM(60) cannot be used to create a high-speed counter. If you require a  
high-speed counter, use HDM(61).  
Dedicated Bits  
When using the counter, the following bits are reserved and cannot be used  
for any other purpose:  
• SR bit 1804 (reset input)  
• SR bit 1805 (count input)  
• SR bit 1806 (UP/DOWN selection input)  
• TC 46 (present count value)  
• DM 00 to 31 (upper and lower limits)  
Note If a power failure occurs, the count value of the counter immediately before  
the power failure is retained.  
Upper and Lower Limit  
Setting  
The following table shows the upper and lower limits that need to be set in  
DM 00 through DM 31. In this table, S is the present value of counter 46 and  
R is the result word.  
Lower limit  
Upper limit  
DM 01  
Present value of the counter  
Bit of R that  
turns ON  
DM 00  
DM 02  
DM 04  
DM 06  
DM 08  
DM 10  
DM 12  
DM 14  
DM 16  
DM 18  
DM 20  
DM 22  
DM 24  
DM 26  
DM 28  
DM 30  
00  
Value of DM 00 ≤ S ≤ value of DM 01  
Value of DM 02 ≤ S ≤ value of DM 03  
Value of DM 04 ≤ S ≤ value of DM 05  
Value of DM 06 ≤ S ≤ value of DM 07  
Value of DM 08 ≤ S ≤ value of DM 09  
Value of DM 10 ≤ S ≤ value of DM 11  
Value of DM 12 ≤ S ≤ value of DM 13  
Value of DM 14 ≤ S ≤ value of DM 15  
Value of DM 16 ≤ S ≤ value of DM 17  
Value of DM 18 ≤ S ≤ value of DM 19  
Value of DM 20 ≤ S ≤ value of DM 21  
Value of DM 22 ≤ S ≤ value of DM 23  
Value of DM 24 ≤ S ≤ value of DM 25  
Value of DM 26 ≤ S ≤ value of DM 27  
Value of DM 28 ≤ S ≤ value of DM 29  
Value of DM 30 ≤ S ≤ value of DM 31  
DM 03  
DM 05  
DM 07  
DM 09  
DM 11  
DM 13  
DM 15  
DM 17  
DM 19  
DM 21  
DM 23  
DM 25  
DM 27  
DM 29  
DM 31  
01  
02  
03  
04  
05  
06  
07  
08  
09  
10  
11  
12  
13  
14  
15  
104  
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Timer and Counter Instructions  
Section 5-11  
The values must be four-digit BCD in the range 0000 through 9999. Failure  
to enter BCD values will not activate the ERR flag. Always set a lower limit  
which is less than the corresponding upper limit. MOV(21) is useful in setting  
limits. The following ladder diagram shows the use of MOV(21) for setting  
limits.  
1813 (normally ON)  
MOV(21)  
#0200  
DM 00  
MOV(21)  
#1500  
DM 01  
Transfers  
preset value  
to DM 00 to  
03.  
MOV(21)  
#0600  
DM 02  
MOV(21)  
#2000  
DM 03  
0002 (start input)  
Counts  
RDM(60) 46  
inputs on  
IR 1805.  
05  
Corresponding  
result word is 05  
Address Instruction  
Operands  
1813  
Address Instruction  
Operands  
0000  
0001  
LD  
0004  
MOV(21)  
MOV(21)  
#
2000  
03  
#
0200  
00  
DM  
DM  
0005  
0006  
LD  
0002  
46  
0002  
0003  
MOV(21)  
MOV(21)  
RDM(60)  
#
1500  
01  
05  
DM  
#
0600  
02  
DM  
105  
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Data Shifting  
Section 5-12  
Timing Example  
The following timing example uses HR 0 as the results word.  
Present value  
0000 0001 0002 0003 0004 0005 0004 0003 0002 0001 0000 9999 9998 9997 00000000 0000  
Start input 0002  
Count input (1805)  
Reset input (1804)  
UP/DOWN selection (1806)  
HR 000  
Limits: 0001 to 0002  
HR 001  
Limits: 0002 to 0004  
HR 015  
Limits: 9980 to 9999  
5-12 Data Shifting  
This section describes the instructions that are used to create and manipu-  
late shift registers. SFT(10) creates a single- or multiple-word register that  
shift in a second execution condition when executed with an ON execution  
condition. SFTR(84) creates a reversible shift register that is controlled  
through the bits in a control word. WSFT(16) creates a multiple-word register  
that shifts by word.  
5-12-1 SHIFT REGISTER – SFT(10)  
Ladder Symbol  
Operand Data Areas  
I
St : Starting word  
IR, HR  
SFT(10)  
P
St  
E : End word  
IR, HR  
R
E
Limitations  
E must be less than or equal to St, and St and E must be in the same data  
area.  
If a bit address in one of the words used in a shift register is also used in an  
instruction that controls individual bit status (e.g., OUT, KEEP(11)), an error  
(“COIL DUPL”) will be generated when program syntax is checked on the  
Programming Console or another Programming Device. The program, how-  
ever, will be executed as written. See Example 2: Controlling Bits in Shift  
Registers for a programming example that does this.  
106  
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Data Shifting  
Section 5-12  
Description  
SFT(10) shifts an execution condition into a shift register. SFT(10) is con-  
trolled by three execution conditions, I, P, and R. If SFT(10) is executed and  
1) execution condition P is ON and was OFF the last execution and 2) R is  
OFF, then execution condition I is shifted into the rightmost bit of a shift regis-  
ter defined between St and E, i.e., if I is ON, a 1 is shifted into the register; if I  
is OFF, a 0 is shifted in. When I is shifted into the register, all bits previously  
in the register are shifted to the left and the leftmost bit of the register is lost.  
E
St + 1, St + 2, ...  
St  
Lost  
data  
Execution  
condition I  
The execution condition on P functions like a differentiated instruction, i.e., I  
will be shifted into the register only when P is ON and was OFF the last time  
SFT(10) was executed. If execution condition P has not changed or has gone  
from ON to OFF, the shift register will remain unaffected.  
St designates the rightmost word of the shift register; E designates the left-  
most. The shift register includes both of these words and all words between  
them. The same word may be designated for St and E to create a 16-bit (i.e.,  
1-word) shift register.  
When execution condition R goes ON, all bits in the shift register will be  
turned OFF (i.e., set to 0) and the shift register will not operate until R goes  
OFF again.  
Flags  
There are no flags affected by SFT(10).  
Example 1:  
Basic Application  
The following example uses the 1-second clock pulse bit (1902) to so that the  
execution condition produced by 0005 is shifted into a 3-word register be-  
tween 10 and 12 every second.  
0005  
1902  
0006  
Address Instruction  
Operands  
0005  
I
SFT(10)  
10  
0000  
0001  
0002  
0003  
LD  
P
R
LD  
1902  
0006  
LD  
12  
SFT(10)  
10  
12  
Example 2:  
Controlling Bits in Shift  
Registers  
The following program is used to control the status of the 17th bit of a shift  
register running from IR 00 through IR 01 (i.e. bit 00 of IR 01). When the 17th  
bit is to be set, 0204 is turned ON. This causes the jump for JMP(04) 00 not  
to be made for that one cycle and IR 0100 (the 17th bit) will be turned ON.  
107  
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Data Shifting  
Section 5-12  
When 1280 is OFF (all times but the first cycle after 0204 has changed from  
OFF to ON), the jump is taken and the status of 0100 will not be changed.  
0200  
0202  
0203  
0204  
1280  
1280  
0201  
I
Address Instruction  
Operands  
0200  
0000  
0001  
0002  
0003  
0004  
LD  
SFT(10)  
00  
AND  
LD  
0201  
0202  
0203  
P
R
LD  
01  
SFT(10)  
00  
01  
DIFU(13) 1280  
JMP(04) 00  
0005  
0006  
0007  
0008  
0009  
0010  
0011  
LD  
0204  
1280  
1280  
00  
DIFU(13)  
LD  
JMP(04)  
LD  
1280  
0100  
00  
0100  
OUT  
JME(05)  
JME(05) 00  
When a bit that is part of a shift register is used in OUT (or any other instruc-  
tion that controls bit status), a syntax error will be generated during the pro-  
gram check, but the program will execute properly (i.e., as written).  
Example 3:  
Control Action  
The following program controls the conveyor line shown below so that faulty  
products detected at the sensor are pushed down a chute. To do this, the  
execution condition determined by inputs from the first sensor (0001) are  
stored in a shift register: ON for good products; OFF for faulty ones. Con-  
veyor speed has been adjusted so that HR 003 of the shift register can be  
used to activate a pusher (0500) when a faulty product reaches it, i.e., when  
HR 003 turns ON, 0500 is turned ON to activate the pusher.  
108  
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Data Shifting  
Section 5-12  
The program is set up so that a rotary encoder (0000) controls execution of  
SFT(10) through a DIFU(13), the rotary encoder is set up to turn ON and  
OFF each time a product passes the first sensor. Another sensor (0002) is  
used to detect faulty products in the chute so that the pusher output and HR  
003 of the shift register can be reset as required.  
Sensor  
(0001)  
Pusher  
(0500)  
Sensor  
(0002)  
Rotary Encoder  
(0000)  
Chute  
0001  
0000  
0003  
I
Instruction  
Operands  
0001  
Address  
SFT(10)  
HR 0  
P
R
0000  
0001  
0002  
0003  
LD  
LD  
0000  
0003  
HR 1  
LD  
SFT(10)  
HR  
HR  
HR  
0
1
HR 003  
0002  
0500  
0004  
0005  
0006  
0007  
0008  
LD  
003  
0500  
0002  
0500  
003  
OUT  
LD  
0500  
OUT NOT  
OUT NOT  
HR  
HR 003  
5-12-2 REVERSIBLE SHIFT REGISTER – SFTR(84)  
Operand Data Areas  
C : Control word  
IR, DM, HR  
Ladder Symbols  
SFTR(84)  
St : Starting word  
IR, DM, HR  
C
St  
E
E : End word  
IR, DM, HR  
Limitations  
St and E must be in the same data area and St must be less than or equal to  
E.  
109  
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Data Shifting  
Section 5-12  
Description  
SFTR(84) is used to create a single- or multiple-word shift register that can  
be shifted to either the right or the left. To create a single-word shift register,  
designate the same word for St and E. The control word provides the shift  
direction, the status to be input into the register, the shift pulse, and the reset  
input. The control word is allocated as follows:  
15 14 13 12  
Not used.  
Shift direction  
1 (ON): Left  
0 ()FF:  
Right  
Status to input into register  
Shift pulse bit  
Reset  
The data in the shift register will be shifted one bit in the direction indicated  
by bit 12, shifting one bit out to CY and the status of bit 13 into the other end  
whenever SFTR(84) is executed with an ON execution condition as long as  
the reset bit is OFF and as long as bit 14 is ON. If SFTR(84) is executed with  
an OFF execution condition or if SFTR(84) is executed with bit 14 OFF, the  
shift register will remain unchanged. If SFTR(84) is executed with an ON ex-  
ecution condition and the reset bit (bit 15) is OFF, the entire shift register and  
CY will be set to zero.  
Flags  
ER:  
CY  
St and E are not in the same data area or St is greater than E.  
Indirectly addressed DM word is non-existent. (Content of *DM word  
is not BCD, or the DM area boundary has been exceeded.)  
Receives the status of bit 00 of St or bit 15 of E depending on the  
shift direction.  
Caution If the execution condition for SFTR(84) is ON and bit 14 is ON, the status of bit 13  
will be shifted into the register every cycle. Use DIFU(13) or DIFD(14) when it is  
necessary to ensure that the shift is made only once each time the execution  
condition comes ON.  
!
5-12-3 WORD SHIFT – WSFT(16)  
Ladder Symbols  
Operand Data Areas  
St : Start word  
IR, DM, HR  
E : End word  
IR, DM, HR  
WSFT(16)  
St  
E
Limitations  
St and E must be in the same data area and St must be less than E.  
110  
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Data Movement  
Section 5-13  
Description  
When the execution condition is OFF, WSFT(16) is not executed and the  
next instruction is moved to. When the execution condition is ON, 0000 is  
moved into St, the content of St is moved to St + 1, the content of St + 1 is  
moved to St + 2, etc., and the content of E is lost.  
E
St + 1  
St  
F
0
4
C
2
2
3
1
4
5
2
9
1
0
0
0
2
0
9
0
Lost  
0000  
E
St + 1  
St  
3
5
0
2
Flags  
ER:  
St and E are not in the same data area.  
Indirectly addressed DM word is non-existent. (Content of *DM word  
is not BCD, or the DM area boundary has been exceeded.)  
5-13 Data Movement  
This section describes the instructions used for moving data between differ-  
ent addresses in data areas. These movements can be programmed within  
the same data area or between different data areas. Data movement is es-  
sential for utilizing all of the data areas of the PC. All of these instructions  
change only the content of the words to which data is being moved, i.e., the  
content of source words is the same before and after execution of any of the  
move instructions.  
5-13-1 MOVE – MOV(21)  
Ladder Symbol  
Operand Data Areas  
S : Source word  
MOV(21)  
IR, SR, DM, HR, TC, #  
D : Destination word  
IR, DM, HR  
S
D
Description  
When the execution condition is OFF, MOV(21) is not executed and the next  
instruction is moved to. When the execution condition is ON, MOV(21) trans-  
fers the content of S (specified word or four-digit hexadecimal constant) to D.  
Source word  
Destination word  
Bit status  
not changed.  
Precautions  
Flags  
TC numbers cannot be designated as D to change the PV of the timer or  
counter.  
EQ:  
ON when all zeros are transferred to D.  
111  
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DATA COMPARE – CMP(20)  
Section 5-14  
5-13-2 MOVE NOT – MVN(22)  
Ladder Symbol  
Operand Data Areas  
S : Source word  
IR, SR, DM, HR, TC, #  
D : Destination word  
IR, DM, HR  
MVN(22)  
S
D
Description  
When the execution condition is OFF, MVN(22) is not executed and the next  
instruction is moved to. When the execution condition is ON, MOV(21) trans-  
fers the inverted content of S (specified word or four-digit hexadecimal con-  
stant) to D, i.e., for each ON bit in S, the corresponding bit in D is turned  
OFF, and for each OFF bit in S, the corresponding bit in D is turned ON.  
Source word  
Destination word  
Bit status  
inverted.  
Precautions  
TC numbers cannot be designated as D to change the PV of the timer or  
counter.  
EQ:  
ON when all zeros are transferred to D.  
5-14 DATA COMPARE – CMP(20)  
This section describes the instruction used for comparing data. CMP(20) is  
used to compare the contents of two words.  
Ladder Symbols  
Operand Data Areas  
Cp1 : First compare word  
IR, SR, DM, HR, TC, #  
CMP(20)  
Cp1  
Cp2 : Second compare word  
IR, SR, DM, HR, TC, #  
Cp2  
Limitations  
Description  
When comparing a value to the PV of a timer or counter, the value must be  
four-digit BCD.  
When the execution condition is OFF, CMP(20) is not executed and the next  
instruction is moved to. When the execution condition is ON, CMP(20) com-  
pares Cp1 and Cp2 and outputs the result to the GR, EQ, and LE flags in the  
SR area.  
Precautions  
Placing other instructions between CMP(20) and accessing the EQ, LE, and  
GR flags may change the status of these flags. Be sure to access them be-  
fore the desired status is changed.  
EQ:  
LE:  
GR:  
ON if Cp1 equals Cp2.  
ON if Cp1 is less than Cp2.  
ON if Cp1 is greater than Cp2.  
112  
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DATA COMPARE – CMP(20)  
Section 5-14  
Example 1:  
Saving CMP(20) Results  
The following example shows how to save the comparison result immedi-  
ately. If the content of HR 8 is greater than that of 9, 0200 is turned ON; if the  
two contents are equal, 0201 is turned ON; if content of HR 8 is less than  
that of HR 9, 0202 is turned ON. In some applications, only one of the three  
OUTs would be necessary, making the use of TR 0 unnecessary. With this  
type of programming, 0200, 0201, and 0202 are changed only then CMP(20)  
is executed.  
TR  
0
0000  
CMP(20)  
HR 8  
HR 9  
1905  
0200  
Greater Than  
1906  
1907  
0201  
0202  
Equal  
Less Than  
Address Instruction  
Operands  
Address Instruction  
Operands  
0000  
0001  
0002  
LD  
0000  
0005  
0006  
0007  
0008  
0009  
0010  
0011  
OUT  
LD  
0200  
OUT  
TR  
0
TR  
0
1906  
0201  
0
CMP(20)  
AND  
OUT  
LD  
HR  
HR  
TR  
8
9
TR  
0003  
0004  
LD  
0
AND  
OUT  
1907  
0202  
AND  
1905  
Example 2:  
Obtaining Indications  
during Timer Operation  
The following example uses TIM, CMP(20), and the LE flag (1907) to pro-  
duce outputs at particular times in the timer’s countdown. The timer is started  
by turning ON 0000. When 0000 is OFF, the TIM (10) is reset and the second  
two CMP(20)s are not executed (i.e., executed with OFF execution condi-  
tions). Output 0200 is output after 100 seconds; output 0201, after 200 sec-  
onds; output 0202, after 300 seconds; and output 0204, after 500 seconds.  
113  
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DATA COMPARE – CMP(20)  
Section 5-14  
The branching structure of this diagram is important so that 0200, 0201, and  
0202 are controlled properly as the timer counts down. Because all of the  
comparisons here are to the timer’s PV, the other operand for each CMP(20)  
must be in 4-digit BCD.  
0000  
TIM 10  
0500 s.  
CMP(20)  
TIM 10  
#4000  
1907  
Output at  
100 s.  
0200  
0200  
CMP(20)  
TIM 10  
#3000  
1907  
Output at  
200 s.  
0201  
0201  
CMP(20)  
TIM 10  
#2000  
1907  
Output at  
0202  
300 s.  
TIM 10  
Output at  
500 s.  
0204  
Address Instruction  
Operands  
0000  
Address Instruction  
Operands  
0000  
0001  
LD  
0007  
0008  
0009  
0010  
AND  
1907  
0201  
0201  
TIM  
10  
OUT  
#
0500  
LD  
0002  
CMP(20)  
CMP(20)  
TIM  
#
10  
4000  
1907  
0200  
0200  
TIM  
10  
2000  
1907  
0202  
10  
#
0003  
0004  
0005  
0006  
AND  
0011  
0012  
0013  
0014  
AND  
OUT  
LD  
OUT  
LD  
TIM  
CMP(20)  
OUT  
0204  
TIM  
#
10  
3000  
114  
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Data Conversion  
Section 5-15  
5-15 Data Conversion  
The conversion instructions convert word data that is in one format into an-  
other format and output the converted data to specified result word(s). Con-  
versions are available to convert between binary (hexadecimal) and BCD  
and between multiplexed and non-multiplexed data. All of these instructions  
change only the content of the words to which converted data is being  
moved, i.e., the content of source words is the same before and after execu-  
tion of any of the conversion instructions.  
5-15-1 BCD-TO- BINARY – BIN(23)  
Ladder Symbol  
Operand Data Areas  
S : Source word (BCD)  
IR, SR, DM, HR, TC  
R : Result word  
BIN(23)  
S
R
IR, DM, HR  
Description  
Flags  
BIN(23) can be used to convert BCD to binary so that displays on the Pro-  
gramming Console or any other programming device will appear in hexadeci-  
mal rather than decimal. It can also be used to convert to binary to perform  
binary arithmetic operations rather than BCD arithmetic operations, e.g.,  
when BCD and binary values must be added.  
ER:  
The content S is not BCD  
EQ:  
ON when 0000 is placed in R.  
5-15-2 BINARY-TO-BCD – BCD(24)  
Ladder Symbol  
Operand Data Areas  
S : Source word (binary)  
IR, SR, DM, HR, TC  
R : Result word  
BCD(24)  
S
R
IR, DM, HR  
Limitations  
Description  
If the content of S exceeds 270F, the converted result would exceed 9999  
and BCD(24) will not be executed. When the instruction is not executed, the  
content of R remains unchanged.  
BCD(24) converts the binary (hexadecimal) content of S into the numerically  
equivalent BCD bits, and outputs the BCD bits to R. Only the content of R is  
changed; the content of S is left unchanged.  
BCD(24) can be used to convert binary to BCD so that displays on the Pro-  
gramming Console or any other programming device will appear in decimal  
rather than hexadecimal. It can also be used to convert to BCD to perform  
BCD arithmetic operations rather than binary arithmetic operations, e.g.,  
when BCD and binary values must be added.  
Flags  
ER:  
S is greater than 270F.  
EQ:  
ON when 0000 is placed in R.  
115  
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Data Conversion  
Section 5-15  
5-15-3 4-TO-16 DECODER – MLPX(76)  
Operand Data Areas  
S : Source word  
IR, SR, DM, HR, TC  
Di : Digit designator  
IR, DM, HR, TC, #  
R : First result word  
IR, DM, HR  
Ladder Symbol  
MLPX(76)  
S
Di  
R
Limitations  
Description  
The rightmost two digits of Di must each be between D and 3.  
All result words must be in the same data area.  
When the execution condition is OFF, MLPX(76) is not executed and the next  
instruction is moved to. When the execution condition is ON, MLPX(76) con-  
verts up to four, four-bit hexadecimal digits from S into decimal values from 0  
to 15, each of which is used to indicate a bit position. The bit whose number  
corresponds to each converted value is then turned ON in a result word. If  
more than one digit is specified, then one bit will be turned ON in each of  
consecutive words beginning with R. (See examples, below.)  
The following is an example of a one-digit decode operation from digit num-  
ber 1 of S, i.e., here Di would be 0001.  
S
C
Bit C (i.e., bit number 12) turned ON.  
R
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
The first digit and the number of digits to be converted are designated in Di. If  
more digits are designated than remain in S (counting from the designated  
first digit), the remaining digits will be taken starting back at the beginning of  
S. The final word required to store the converted result (R plus the number of  
digits to be converted) must be in the same data area as R, e.g., if two digits  
are converted, the last word address in a data area cannot be designated; if  
three digits are converted, the last two words in a data area cannot be desig-  
nated.  
Digit Designator  
The digits of Di are set as shown below.  
Digit numbers: 0 1 2 3  
Specifies the first digit to be converted (0 to 3)  
Number of digits to be converted (0 to 3)  
0: 1 digits  
1: 2 digits  
2: 3 digits  
3: 4 digits  
Not used.  
116  
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Data Conversion  
Section 5-15  
Some example Di values and the digit-to-word conversions that they produce  
are shown below.  
Di : 0010  
Di : 0030  
S
S
R
R
0
1
2
3
0
1
2
3
R + 1  
R + 1  
R + 2  
R + 3  
Di : 0031  
Di : 0023  
S
S
R
R
0
1
2
3
0
1
2
3
R + 1  
R + 2  
R + 1  
R + 2  
R + 3  
Flags  
ER:  
Undefined digit designator, or R plus number of digits exceeds a data  
area.  
Example  
The following program converts three digits of data from DM 20 to bit posi-  
tions and turns ON the corresponding bits in three consecutive words starting  
with HR 1.  
0000  
Address Instruction  
Operands  
0000  
MLPX(76)  
DM 20  
#0021  
0000  
0001  
LD  
MLPX(76)  
DM  
#
20  
0021  
1
HR 1  
HR  
S: DM 20  
R: HR 1  
R+1: HR 2  
R+2: HR 3  
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
DM 00  
DM 01  
DM 02  
DM 03  
DM 04  
DM 05  
DM 06  
DM 07  
DM 08  
DM 09  
DM 10  
DM 11  
DM 12  
DM 13  
DM 14  
DM 15  
2
HR 100  
HR 101  
HR 102  
HR 103  
HR 104  
HR 105  
HR 106  
HR 107  
HR 108  
HR 109  
HR 110  
HR 111  
HR 112  
HR 113  
HR 114  
HR 115  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
HR 200  
HR 201  
HR 202  
HR 203  
HR 204  
HR 205  
HR 206  
HR 207  
HR 208  
HR 209  
HR 210  
HR 211  
HR 212  
HR 213  
HR 214  
HR 215  
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
HR 300  
HR 301  
HR 302  
HR 303  
HR 304  
HR 305  
HR 306  
HR 307  
HR 308  
HR 309  
HR 310  
HR 311  
HR 312  
HR 313  
HR 314  
HR 315  
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Not  
Converted  
1
1
1
1
0
1
1
0
0
0
0
0
15  
6
1
2
3
0
117  
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Data Conversion  
Section 5-15  
5-15-4 16-TO-4 ENCODER – DMPX(77)  
Operand Data Areas  
S : First source word  
IR, SR, DM, HR, TC  
R : Result word  
Ladder Symbol  
DMPX(77)  
S
R
IR, DM, HR  
Di : Digit designator  
IR, DM, HR, TC, #  
Di  
Limitations  
Description  
The rightmost two digits of Di must each be between 0 and 3. All source  
words must be in the same data area.  
When the execution condition is OFF, DMPX(77) is not executed and the  
next instruction is moved to. When the execution condition is ON, DMPX(77)  
determines the position of the highest ON bit in S, encodes it into single-digit  
hexadecimal value corresponding to the bit number of the highest ON bit  
number, then transfers the hexadecimal value to the specified digit in R. The  
digits to receive the results are specified in Di, which also specifies the num-  
ber of digits to be encoded.  
The following is an example of a one-digit encode operation to digit number 1  
of R, i.e., here Di would be 0001.  
S
0
0
0
1
0
0
0
1
0
0
0
1
0
1
1
0
C transferred to indicate bit number 12 as  
the highest ON bit.  
R
C
Up to four digits from four consecutive source words starting with S may be  
encoded and the digits written to R in order from the designated first digit. If  
more digits are designated than remain in R (counting from the designated  
first digit), the remaining digits will be placed at digits starting back at the be-  
ginning of R.  
The final word to be converted (S plus the number of digits to be converted)  
must be in the same data area as SB.  
Digit Designator  
The digits of Di are set as shown below.  
Digit Numbers: 0 1 2 3  
Specifies the first digit to receive converted data (0 to 3).  
Number of words to be converted (0 to 3)  
0: 1 word  
1: 2 words  
2: 3 words  
3: 4 words  
Not used.  
118  
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Data Conversion  
Section 5-15  
Some example Di values and the word-to-digit conversions that they produce  
are shown below.  
Di : 0011  
Di : 0030  
R
0
1
2
3
R
0
1
2
3
S
S
S + 1  
S + 1  
S + 2  
S + 3  
Di : 0013  
Di : 0032  
R
0
1
2
3
R
0
S
S
1
2
3
S + 1  
S + 2  
S + 3  
S + 1  
Flags  
ER:  
Undefined digit designator, or S plus number of digits exceeds a data  
area.  
Content of a source word is 0000.  
Example  
When 0000 is ON, the following diagram encodes IR words 10 and 11 to the  
first two digits of HR 2 and then encodes DM 10 and 11 to the last two digits  
of HR 2. Although the status of each source word bit is not shown, it is as-  
sumed that the bit with status 1 (ON) shown is the highest bit that is ON in  
the word.  
0000  
Address Instruction  
Operands  
0000  
DMPX(77)  
10  
0000  
0001  
LD  
DMPX(77)  
HR 2  
10  
2
#0010  
HR  
#
0010  
DMPX(77)  
DM10  
0002  
DMPX(77)  
DM  
HR  
#
10  
2
HR 2  
#0012  
0012  
IR 010  
IR 011  
1100  
:
1000  
:
1011  
1012  
:
1
0
1109  
1110  
:
1
0
:
:
HR  
1015  
0
1115  
0
2
B
9
1
8
Digit 0  
Digit 1  
Digit 2  
Digit 3  
DM 10  
DM 11  
DM1000  
:
DM1100  
:
DM1001  
DM1002  
:
1
0
DM1108  
DM1109  
:
1
0
:
:
DM1015  
0
DM1115  
0
119  
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BCD Calculations  
Section 5-16  
5-16 BCD Calculations  
The BCD calculation instructions perform mathematic operations on BCD  
data.  
These instructions change only the content of the words in which results are  
placed, i.e., the contents of source words are the same before and after exe-  
cution of any of the BCD calculation instructions.  
STC(40) and CLC(41), which set and clear the carry flag, are included in this  
group because most of the BCD operations make use of the carry flag (CY)  
in their results. Binary arithmetic and shift operations also use CY.  
The addition and subtraction instructions use CY in the calculation as well as  
in the result. Be sure to clear CY if its previous status is not required in the  
calculation, and to use the result placed in CY, if required, before it is  
changed by execution of any other instruction.  
5-16-1 BCD ADD – ADD(30)  
Operand Data Areas  
Au : Augend word (BCD)  
IR, SR, DM, HR, TC, #  
Ad : Addend word (BCD)  
IR, SR, DM, HR, TC, #  
R : Result word  
Ladder Symbol  
ADD(30)  
Au  
Ad  
R
IR, DM, HR  
Description  
When the execution condition is OFF, ADD(30) is not executed and the next  
instruction is moved to. When the execution condition is ON, ADD(30) adds  
the contents of Au, Ad, and CY, and places the result in R. CY will be set if  
the result is greater than 9999. Au and Ad should not be designated as con-  
stants. This instruction will be executed every cycle as long as the execution  
condition remains ON. If the instruction is to be executed only once for a giv-  
en ON execution condition then it must be used in conjunction with DIFU(13)  
or DIFD(14).  
Au + Ad + CY  
CY  
R
Flags  
ER:  
CY:  
EQ:  
Au and/or Ad is not BCD.  
ON when there is a carry in the result.  
ON when the result is 0.  
120  
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BCD Calculations  
Section 5-16  
Example  
If 0002 is ON, the following diagram clears CY with CLC(41), adds the con-  
tent of IR 02 to a constant (6103), places the result in DM 01, and then  
moves either all zeros or 0001 into DM 02 depending on the status of CY  
(1904). This ensures that any carry from the last digit is preserved in R + 1 so  
that the entire result can be later handled as eight-digit data.  
Address Instruction  
Operands  
0002  
TR 0  
0002  
0000  
0001  
0002  
0003  
LD  
CLC(41)  
OUT  
TR  
0
CLC(41)  
AND(30)  
ADD(30)  
02  
02  
6103  
01  
#
#6103  
DM 01  
DM  
0004  
0005  
AND  
1904  
1904  
1904  
MOV(21)  
MOV(21)  
#0001  
#
0001  
02  
DM  
TR  
DM 02  
0006  
0007  
0008  
LD  
0
AND NOT  
MOV(21)  
1904  
MOV(21)  
#0000  
#
0000  
02  
DM 02  
DM  
Consecutive ADD(30)s can be used to perform eight-digit BCD addition. By  
using two ADD(30)s and combining the augend and the addend words of one  
ADD(30) with those of the other, two 8-digit values can be added. The result  
may or may not be 9 digits depending on whether a carry is generated.  
0002  
Address Instruction  
Operands  
0002  
DIFU(13) 1000  
0000  
0001  
0003  
0004  
0005  
0006  
LD  
TR 0  
1000  
DIFU(13)  
LD  
1000  
1000  
0
CLC(41)  
OUT  
TR  
CLC(41)  
AND(30)  
ADD(30)  
DM 00  
DM 02  
DM 04  
DM  
DM  
DM  
00  
02  
04  
0007  
AND(30)  
DM  
DM  
DM  
01  
03  
ADD(30)  
DM 01  
DM 03  
DM 05  
05  
0008  
0009  
AND  
1904  
MOV(21)  
1904  
1904  
#
0001  
06  
MOV(21)  
#0001  
DM  
TR  
0010  
0011  
0012  
LD  
0
DM 06  
AND NOT  
MOV(21)  
1904  
MOV(21)  
#0000  
#
0000  
06  
DM  
DM 06  
In the above program the 8 digit augend consists of two words: DM 00 and  
DM 01, with DM 01 being used for the 4 left digits and 00 for the 4 right dig-  
its. Similarly the 8-digit addend consist of DM 02 and 03. Three words are  
used to hold the results of the addition: DM 04, DM 05, and DM 06. In this  
121  
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BCD Calculations  
Section 5-16  
case DM 05 and DM 04 are used to represent the intermediate 4 digits and  
the 4 right digits respectively. DM 06 represents the leftmost digit, the 9th dig-  
it.  
If a carry is generated, SR 1904 (CY) is turned ON and the constant 0001 is  
transferred to DM 06. If a carry is not generated SR 1904 remains OFF and  
the constant 0000 is transferred to DM 06.  
5-16-2 BCD SUBTRACT – SUB(31)  
Operand Data Areas  
Mi : Minuend word (BCD)  
IR, SR, DM, HR, TC, #  
Su : Subtrahend word (BCD)  
IR, SR, DM, HR, TC, #  
R : Result word  
Ladder Symbol  
SUB(31)  
Mi  
Su  
R
IR, DM, HR  
Description  
When the execution condition is OFF, SUB(31) is not executed and the next  
instruction is moved to. When the execution condition is ON, SUB(31) sub-  
tracts the contents of Su and CY from Mi and places the result in R. If the  
result is negative, CY is set and the 10’s complement of the actual result is  
placed in R. To convert the 10’s complement to the true result, subtract the  
content of R from zero (see example below). This instruction will be executed  
every cycle as long as the execution condition remains ON. If the instruction  
is to be executed only once then it must be used in conjunction with  
DIFU(13) or DIFD(14).  
Mi – Su – CY  
CY  
R
Flags  
ER:  
CY:  
EQ:  
Mi and/or Su is not BCD.  
ON when the result is negative, i.e., when Mi is less than Su plus CY.  
ON when the result is 0.  
Caution Be sure to clear the carry flag with CLC(41) before executing SUB(31) if its previ-  
ous status is not required, and check the status of CY after doing a subtraction  
with SUB(31). If CY is ON as a result of executing SUB(31) (i.e., if the result is  
negative), the result is output as the 10’s complement of the true answer. To con-  
vert the output result to the true value, subtract the value in R from 0.  
!
Example  
When 0002 is ON, the following diagram clears CY, subtracts the contents of  
DM 01 and CY from the content of IR 10 and places the result in HR 2.  
If CY is set by executing SUB(31), the result in HR 2 is subtracted from zero  
(note that CLC(41) is again required to obtain an accurate result), the result  
is placed back in HR 2, and HR 300 is turned ON to indicate a negative re-  
sult.  
122  
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BCD Calculations  
Section 5-16  
If CY is not set by executing SUB(31), the result is positive, the second sub-  
traction is not performed and HR 300 is not turned ON. HR 300 is pro-  
grammed as a self-maintaining bit so that a change in the status of CY will  
not turn it OFF when the program is recycled.  
TR 0  
0002  
CLC(41)  
SUB(31)  
First  
subtraction  
10  
DM 01  
HR 2  
1904  
CLC(41)  
SUB(31)  
Second  
subtraction  
#0000  
HR 2  
Address Instruction  
Operands  
0002  
HR 2  
0000  
0001  
0002  
0003  
LD  
1904  
HR 300  
OUT  
TR  
0
CLC(41)  
@SUB(31)  
HR 300  
Turned ON to indicate  
negative result.  
10  
01  
DM  
HR  
2
0004  
0005  
0006  
AND  
1904  
CLC(41)  
@SUB(31)  
#
0000  
2
HR  
HR  
TR  
2
0007  
0008  
0009  
0010  
LD  
0
AND  
OR  
1904  
300  
300  
HR  
HR  
OUT  
5-16-3 BCD MULTIPLY – MUL(32)  
Operand Data Areas  
Md : Multiplicand word (BCD)  
IR, DM, HR, TC, #  
Ladder Symbol  
MUL(32)  
Mr : Multiplier word (BCD)  
IR, DM, HR, TC, #  
Md  
Mr  
R
R : First result word (BCD)  
IR, DM, HR  
Limitations  
R and R + 1 must be in the same data area.  
123  
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BCD Calculations  
Section 5-16  
Description  
When the execution condition is OFF, MUL(32) is not executed and the next  
instruction is moved to. When the execution condition is ON, the contents of  
Md and Mr are multiplied and the rightmost four digits of the result are placed  
in R; the leftmost four digits, in R + 1.  
Md word  
X
Mr word  
R +1 word  
R word  
Flags  
ER:  
Md or Mr is not in BCD.  
Indirectly addressed DM word is non-existent. (Content of *DM word  
is not BCD, or the DM area boundary has been exceeded.)  
EQ:  
ON when the result is 0.  
Example  
When IR 0000 is ON with the following program, the contents of IR 13 and  
DM 05 are multiplied and the result is placed in HR 7 and HR 8. Example  
data and calculations are shown below the program.  
Address Instruction  
Operands  
0000  
0000  
0000  
0001  
LD  
MUL(32)  
13  
MUL(32)  
13  
05  
7
DM 05  
HR 7  
DM  
HR  
MD : IR 13  
3
0
3
3
5
6
5
0
X
MR : DM 05  
0
2
R+1 : HR 8  
R : HR 7  
9
0
0
0
8
0
5-16-4 BCD DIVIDE – DIV(33)  
Operand Data Areas  
Dd : Dividend word (BCD)  
IR, SR, DM, HR, TC, #  
Dr : Divisor word (BCD)  
IR, SR, DM, HR, TC, #  
R : First result word (BCD)  
IR, DM, HR  
Ladder Symbol  
DIV(33)  
Dd  
Dr  
R
Limitations  
R and R + 1 must be in the same data area.  
124  
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BCD Calculations  
Section 5-16  
Description  
When the execution condition is OFF, DIV(33) is not executed and the next  
instruction is moved to. When the execution condition is ON, the content of  
Dd is divided by the content of Dr and the result is placed in R and R + 1: the  
quotient in R and the remainder in R + 1.  
Quotient  
R word  
Remainder  
R + 1 word  
÷
Dr word  
Dd word  
Flags  
ER:  
Dd or Dr is not in BCD.  
Indirectly addressed DM word is non-existent. (Content of *DM word  
is not BCD, or the DM area boundary has been exceeded.)  
EQ:  
ON when the result is 0.  
Example  
When IR 0000 is ON with the following program, the content of IR 20 is di-  
vided by the content of HR 9 and the result is placed in DM 17 and DM 18.  
Example data and calculations are shown below the program.  
Address Instruction  
Operands  
0000  
0000  
0000  
0001  
LD  
DIV(33)  
20  
DIV(33)  
20  
9
HR 9  
DM 17  
HR  
DM  
17  
Quotient  
Remainder  
R : DM 17  
R + 1 : DM 18  
1
1
5
0
0
0
0
2
÷
Dd : IR 20  
Dd : IR 20  
3
4
5
2
0
0
0
3
5-16-5 SET CARRY – STC(40)  
Set carry is used to set (turn ON) the CY (SR bit 1904) to “1.”  
0002  
Address Instruction  
Operands  
0002  
STC(40)  
0000  
0001  
LD  
STC(40)  
5-16-6 CLEAR CARRY – CLC(41)  
Clear carry is used to reset (turn OFF) the CY (SR bit 1904) to “0.”  
0002  
Address Instruction  
Operands  
0002  
CLC(41)  
0000  
0001  
LD  
CLC(41)  
125  
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Subroutines  
Section 5-17  
5-17 Subroutines  
Subroutines can be used for one of two different purposes: either to separate  
off sections of large control tasks so that they can be handled as smaller  
ones and to enable you to reuse a given set of instructions at different places  
within one program or as a part of different programs. When the main pro-  
gram calls a subroutine, control is transferred to the subroutine and the in-  
structions in the subroutine are executed. The instructions within a subrou-  
tine are written in the same way as main program code. When all the instruc-  
tions in the subroutine have been executed, control returns to the main pro-  
gram.  
5-17-1 SUBROUTINE DEFINE and SUBROUTINE RETURN  
SBN(92)/RET(93)  
Ladder Symbol  
Definer Data Areas  
N: Subroutine number  
SBN(92) N  
# (00 to 15)  
Ladder Symbol  
RET(93)  
Limitations  
Description  
Each subroutine number can be used in SBN(92) once only, i.e., up to 16  
subroutines may be programmed.  
SBN(92) is used to mark the beginning of a subroutine program; RET(93) is  
used to mark the end. Each subroutine is identified with a subroutine number,  
N, that is programmed as a definer for SBN(92). This same subroutine num-  
ber is used in any SBS(91) that calls the subroutine (see next section). No  
subroutine number is required with RET(93).  
All subroutines must be programmed at the end of the main program. When  
one or more subroutines have been programmed, the main program will be  
executed up to the first SBN(92) before returning to address 0000 for the  
next cycle. Subroutines will not be executed unless called by SBS(91).  
END(01) must be placed at the end of the last subroutine program, i.e., after  
the last RET(93). It is not required at any other point in the program.  
Flags  
There are no flags directly affected by these instructions.  
5-17-2 SUBROUTINE ENTRY – SBS(91)  
Ladder Symbol  
Definer Data Areas  
N: Subroutine number  
SBS(91) N  
# (00 to 15)  
Description  
To execute a subroutine, it must be called from the main by programming  
SBS(91) with the number of the desired subroutine. When SBS(91) is exe-  
cuted (i.e., when the execution condition for it is ON), the instructions be-  
tween the SBN(92) with the same subroutine number and the first RET(93)  
after it are executed before execution returns to the instruction following the  
SBS(91) that made the call.  
126  
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Subroutines  
Section 5-17  
SBS(91) may be used as many times as desired in the program (i.e., the  
same subroutine may be called from different places in the program).  
SBS(91) may also be placed into a subroutine to shift program execution  
from one subroutine to another, i.e., subroutines may be nested. When the  
second subroutine has been completed (i.e., RET(93) has been reached),  
the first subroutine is returned to and completed before returning to the main  
program. Nesting is possible to up to eight levels. A subroutine cannot call  
itself, e.g., SBS(91) 00 cannot be programmed within the subroutine defined  
with SBN(92).  
The following diagram illustrates program execution flow for various execu-  
tion conditions for two SBS(91). In actual execution, the PC actually executes  
a sequential program, with the subroutines inserted in at the required loca-  
tions.  
A
SBS(91)  
B
00  
01  
OFF execution conditions for 00 and 01  
A
B
C
Main  
program  
SBS(91)  
ON execution condition for 00  
A
D
B
C
C
SBN(92)  
D
00  
01  
ON execution condition for 01  
A
B
E
C
RET(93)  
SBN(92)  
ON execution conditions for 00 and 01  
Subroutines  
A
D
B
E
C
E
RET  
END(01)  
Flags  
ER:  
A subroutine does not exist for the specified subroutine number.  
A subroutine has called itself.  
Subroutines have been nested to more than eight levels.  
Caution SBS(91) will not be executed and the subroutine will not be called when ER is  
!
ON.  
127  
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Step Instructions  
Section 5-18  
5-18 Step Instructions  
The step instructions STEP(08) and SNXT(09) are used in conjunction to set  
up breakpoints between sections in large programs so that the sections can  
be executed as units and reset upon completion. A step of program will usu-  
ally be defined to correspond with an actual process in the application. (Refer  
to the application examples later in this section.) A section is like normal pro-  
gramming code except that certain instruction (e.g. IL(02)/ILC(03), JMP(04)/  
JME(05)) may not be included.  
5-18-1 STEP DEFINE and STEP START – STEP(08)/SNXT(09)  
Ladder Symbols  
Definer Data Areas  
B: Control bit  
STEP(08) B  
STEP(08)  
IR, HR  
Ladder Symbol  
Definer Data Areas  
B: Control bit  
SNXT(09) B  
IR, HR  
Description  
STEP(08) is used with a control bit in the IR or HR area to define the begin-  
ning of a section of the program called a step. STEP(08) does not require an  
execution condition, i.e., its execution is controlled through the control bit. To  
start execution of the step, SNXT(09) is used with the same control bit as the  
STEP(08) that defines the beginning of the step. If SNXT(09) is executed  
with an ON execution condition, the step with the same control bit is exe-  
cuted. If the execution condition is OFF, the step is not executed. The  
SNXT(09) must be written into the program before the step it starts. It can be  
used at different locations before the step to control the step according to two  
different execution conditions (see example 2, below). Any step in the pro-  
gram that has not been started with SNTX(09) will not be executed.  
Once SNXT(09) is used in the program, step execution will continue until  
STEP(08) is executed without a control bit. STEP(08) without a control bit  
must be preceded by SNXT(09) with a dummy control bit. The dummy con-  
trol bit may be any unused IR or HR bit. It cannot be a control bit used in a  
STEP(08). All control bits used to produce steps, however, must be from the  
same word and must be used consecutively, and therefore a maximum of 16  
steps can be programmed.  
Execution of a step is completed either by execution of the next SNXT(09) or  
by turning OFF the control bit for the step (see example 3 below). When the  
step is completed, all of the IR and HR bits in the step are turned OFF and all  
timers in the step are reset to their SV. Counters, shift registers, and bits  
used in KEEP(11) maintain status.  
More than one step can be programmed in series. Each step must start with  
STEP(08) and generally ends with SNXT(09) (see example 3, below, for an  
exception). When steps are programmed in series, three types of execution  
are possible: sequential, branching, or parallel. The execution conditions for  
and positioning of SNXT(09) determine how the steps are executed. The  
three examples given below demonstrate these three types of step execu-  
tion.  
128  
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Step Instructions  
Section 5-18  
Precautions  
Interlocks, jumps, SBN(92), and END(01) must not be used within step pro-  
grams.  
Bits used as control bits must not be used anywhere else in the program un-  
less they are used to control the step (see example 3, below).  
If IR bits are used for control bits, their status will be lost during any power  
interruption. If it is necessary to maintain status to resume execution at the  
same step, HR bits must be used.  
Flags  
1811: Step Start flag; turns ON for one cycle when STEP(08) is executed  
and can be used to reset counters in steps as shown below if neces-  
sary.  
0000  
Start  
SNXT(09) 1000  
1000  
STEP(08) 1000  
0100  
CP  
CNT 01  
1811  
1811  
#0003  
R
1 cycle  
Address Instruction  
Operands  
0000  
0001  
0002  
0003  
0004  
0005  
LD  
0000  
1000  
1000  
0100  
1811  
01  
SNXT(09)  
STEP(08)  
LD  
LD  
CNT  
#
0003  
129  
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Step Instructions  
Section 5-18  
Examples  
The following three examples demonstrate the three types of execution con-  
trol possible with step programming. Example 1 demonstrates sequential  
execution; example 2, branching execution; and example 3, parallel execu-  
tion.  
Example 1: Sequential  
Execution  
The following process requires that three processes, loading, part installa-  
tion, and inspection/discharge, be executed in sequence with each process  
being reset before continuing on to the next process. Various sensors (SW1,  
SW2, SW3, and SW4) are positioned to signal when processes are to start  
and end.  
SW 1  
SW 4  
SW 2  
SW 3  
Loading  
Part installation  
Inspection/discharge  
The following diagram demonstrates the flow of processing and the switches  
that are used for execution control.  
SW1  
Process A  
Loading  
SW2  
Process B  
Part Installation  
SW3  
Process C  
Inspection/discharge  
SW4  
130  
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Step Instructions  
Section 5-18  
The program for this process, shown below, utilizes the most basic type of  
step programming: each step is completed by a unique SNXT(09) that starts  
the next step. Each step starts when the switch that indicates the previous  
step has been completed turns ON.  
0001 (SW1)  
0002 (SW2)  
0003 (SW3)  
0004 (SW4)  
Process A  
started.  
SNXT(09) 1000  
Address Instruction  
Operands  
0001  
0000  
0001  
0002  
LD  
STEP(08) 1000  
SNXT(09)  
STEP(08)  
1000  
1000  
Process A  
Process A  
reset.  
SNXT(09) 1001  
STEP(08) 1001  
Address Instruction  
Operands  
0100  
0101  
0102  
LD  
0002  
1001  
1001  
Process B  
started.  
SNXT(09)  
STEP(08)  
Process B  
Process  
B reset.  
SNXT(09) 1002  
STEP(08) 1002  
Address Instruction  
Operands  
0200  
0201  
0202  
LD  
0003  
1002  
1002  
Process C  
started.  
SNXT(09)  
STEP(08)  
Process C  
Process C  
reset.  
SNXT(09) 1003  
STEP(08)  
Address Instruction  
Operands  
0300  
0301  
0302  
LD  
0004  
1003  
1003  
SNXT(09)  
STEP(08)  
Example 2: Branching  
Execution  
The following process requires that a product is processed in one of two  
ways, depending on its weight, before it is printed. The printing process is the  
same regardless of which of the first processes is used. Various sensors are  
positioned to signal when processes are to start and end.  
Printer  
SW A2  
SW A1  
SW D  
Process A  
Process B  
SW B1  
SW B2  
Weight scale  
Process C  
131  
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Step Instructions  
Section 5-18  
The following diagram demonstrates the flow of processing and the switches  
that are used for execution control. Here, either process A or process B is  
used depending on the status of SW A1 and SW B1.  
SW B1  
SW B2  
SW A1  
SW A2  
Process A  
Process B  
Process C  
SW D  
End  
The program for this process, shown below, starts with two SNXT(09) that  
start processes A and B. Because of the way 0001 (SWA1) and 0002 (SB  
B1) are programmed, only one of these will be executed to start either proc-  
ess A or process B. Both of the steps for these processes end with a  
SNXT(09) that starts the step for process C.  
0001 (SW A1) 0002 (SW B2)  
SNXT(09) 1400  
Address Instruction  
Operands  
0001  
0000  
0001  
0002  
0003  
0004  
0005  
0006  
LD  
0001 (SW A1)  
0003 (SW A2)  
0004 (SW B2)  
0005 (SW D)  
0002 (SW B2)  
AND NOT  
SNXT(09)  
LD NOT  
AND  
0002  
1400  
0001  
0002  
1401  
1400  
SNXT(09) 1401  
STEP(08) 1400  
Process A  
started.  
SNXT(09)  
STEP(08)  
Process A  
SNXT(09) 1402  
STEP(08) 1401  
Process A  
reset.  
Address Instruction  
Operands  
0100  
0101  
0102  
LD  
0003  
1402  
1401  
Process  
C started.  
SNXT(09)  
STEP(08)  
Process B  
Process B  
reset.  
SNXT(09) 1402  
STEP(08) 1402  
Address Instruction  
Operands  
0200  
0201  
0202  
LD  
0004  
1402  
1402  
Process  
C started.  
SNXT(09)  
STEP(08)  
Process C  
Process C  
reset.  
SNXT(09) 1403  
STEP(08)  
Address Instruction  
Operands  
0300  
0301  
0302  
LD  
0005  
1403  
SNXT(09)  
STEP(08)  
132  
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Step Instructions  
Section 5-18  
Example 3: Parallel  
Execution  
The following process requires that two parts of a product pass simultane-  
ously through two processes each before they are joined together in a fifth  
process. Various sensors are positioned to signal when processes are to  
start and end.  
SW1  
SW3  
SW5  
SW7  
Process A  
Process B  
Process E  
Process D  
Process C  
SW4  
SW2  
SW6  
The following diagram demonstrates the flow of processing and the switches  
that are used for execution control. Here, process A and process C are  
started together. When process A finishes, process B starts; when process C  
finishes, process D starts. When both processes B and D have finished,  
process E starts.  
SW 1 and SW2 both ON  
Process A  
Process B  
Process C  
Process D  
SW4  
SW3  
SW5 and SW6 both ON  
Process E  
SW7  
End  
The program for this operation, shown below, starts with two SNXT(09) that  
start processes A and C. These instructions branch from the same instruction  
line and are always executed together, starting steps for both A and C. When  
the steps for both A and C have finished, the steps for process B and D be-  
gin immediately.  
When both process B and process D have finished (i.e., when SW5 and SW6  
turn ON), processes B and D are reset together by the SNXT(09) at the end  
of the programming for process B. Although there is no SNXT(09) at the end  
of process D, the control bit for it is turned OFF by executing SNXT(09) 1002.  
This is because the OUT to IR 1101 is in the step reset by SNXT(09) 1002.  
133  
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Step Instructions  
Section 5-18  
Thus, process B is reset directly and process B is set indirectly before exe-  
cuting the step for process E.  
Address Instruction  
Operands  
0001  
0001 (SW1 and SW2))  
Process A  
started.  
0000  
0001  
0002  
0003  
LD  
SNXT(09) 1000  
SNXT(09)  
SNXT(09)  
STEP(08)  
1000  
1002  
1000  
Process C  
started.  
SNXT(09) 1002  
STEP(08) 1000  
Process A  
0002 (SW3)  
SNXT(09) 1001  
STEP(08) 1001  
Process A  
reset.  
Address Instruction  
Operands  
0100  
0101  
0102  
LD  
0002  
1001  
1001  
Process B  
started.  
SNXT(09)  
STEP(08)  
Process B  
1003  
Used to  
turn off  
process D.  
Address Instruction  
Operands  
1003  
SNXT(09) 1004  
STEP(08) 1002  
0200  
0201  
0202  
0203  
0204  
LD  
1003  
1003  
0004  
1004  
1002  
0004 (SW5 and SW6)  
OUT  
Process E  
started.  
AND  
SNXT(09)  
STEP(08)  
Process C  
0003 (SW4)  
SNXT(09) 1003  
STEP(08) 1003  
Process C  
reset.  
Process D  
started.  
Address Instruction  
Operands  
0300  
0301  
0302  
LD  
0003  
1003  
1003  
SNXT(09)  
STEP(08)  
Process D  
STEP(08) 1004  
Address Instruction  
0401 STEP(08)  
Operands  
1004  
Process E  
0005 (SW7)  
Process E  
reset.  
SNXT(09) 1005  
STEP(08)  
Address Instruction  
Operands  
0500  
0501  
0502  
LD  
0005  
1005  
SNXT(09)  
STEP(08)  
134  
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Special Instructions  
Section 5-19  
5-19 Special Instructions  
The following instructions provide for special purposes: refreshing I/O bits  
during program execution, designating minimum cycle time, and inserting  
comments into a program.  
5-19-1 I/O REFRESH – IORF(97)  
Ladder Symbol  
Operand Data Areas  
St : Starting word  
IR (00 through 09)  
E : End word  
IORF(97)  
St  
E
IR (00 through 09)  
Limitations  
Description  
IORF can be used for refreshing I/O words allocated on the CPU or an Ex-  
pansion I/O Rack only. It cannot be used for other I/O words. St must be less  
than or equal to E.  
When the execution condition is OFF, IORF(97) is not executed and the next  
instruction is moved to. When the execution condition is ON, all words be-  
tween St and E will be refreshed. This will be in addition to the normal I/O  
refresh performed during the PC’s cycle.  
Execution Time  
Flags  
The execution time for IORF(97), T  
, is computed as follows:  
IORF  
T
= 40 µs + (74 µs x number of words refreshed)  
IORF  
There are no flags affected by this instruction.  
5-19-2 END WAIT – ENDW(62)  
Ladder Symbol  
Operand Data Areas  
Ml : Multiplier (BCD)  
ENDW(62)  
Ml  
#
Description  
ENDW(62) can be used to specify a minimum cycle time for the PC. When  
the execution condition is OFF, ENDW(62) is not executed and the next in-  
struction is moved to. When the execution condition is ON, the CPU will wait  
at the end of program execution until the cycle time reaches 100 µs X Ml be-  
ginning the next cycle. If program execution requires less that the minimum  
time set, a wait will be inserted immediately after execution of END(01).  
If the minimum cycle time set with ENDW(62) is exceeded by normal pro-  
gram execution, the cycle will continue as normal. If more than one  
ENDW(62) is written into the program, only the last one will be effective.  
The accuracy of TIMH(15) may be affected if Ml is greater than 10. The accu-  
racy of TIM and the response speed of the Programming Console may be  
affected if Ml is set to greater than 1,000.  
The cycle time set with ENDW(62) is accurate to plus or minus 0.05 ms.  
There are no flags affected by this instruction.  
Flags  
135  
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Special Instructions  
Section 5-19  
5-19-3  
NOTATION INSERT – NETW(63)  
Ladder Symbol  
Operand Data Areas  
C1 : Comment 1 (Hex)  
NETW(63)  
#
C1  
C2  
C2 : Comment 2 (Hex)  
#
Description  
Flags  
NETW(63) is not executed regardless of its execution condition. It is provided  
so that the programmer can leave comments in the program. The operands  
may be any hexadecimal value from 0000 through FFFF.  
There are no flags affected by this instruction.  
136  
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SECTION 6  
Program Execution Timing  
6-1  
6-2  
6-3  
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Cycle Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Calculating Cycle Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
138  
139  
141  
141  
142  
143  
145  
6-3-1  
6-3-2  
Single PC Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
PC with Additional Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
6-4  
6-5  
Instruction Execution Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
I/O Response Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
137  
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Introduction  
Section 6-1  
6-1  
Introduction  
When writing and debugging a program, the timing of various operations  
must be considered. Not only is the time required to execute the program  
and perform other CPU operations important, but also the timing of each sig-  
nal coming into and leaving the PC must be such that the desired control ac-  
tion is achieved at the right time.  
The major factors in determining program timing are the cycle time and the  
I/O response time. One cycle of CPU operation is called a cycle; the time  
required for one cycle is called the cycle time. The time required to produce a  
control output signal following reception of an input signal is called the I/O  
response time. This section explains the cycle and shows how to calculate  
the cycle time and I/O response time.  
138  
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Cycle Time  
Section 6-2  
6-2  
Cycle Time  
To aid in PC operation, the average cycle time can be displayed on the Pro-  
gramming Console or any other Programming Device. Understanding the  
operations that occur during the cycle and the elements that affect cycle time  
is essential to effective programming and PC operations.  
The overall flow of CPU operation is as shown in the following flowchart.  
Power application  
Clears IR area and  
resets all timers  
Checks I/O Unit  
connections  
Resets watchdog  
timer  
Checks hardware and  
Program Memory  
NO  
Check OK?  
Sets error flags and  
lights indicator  
YES  
Services Peripheral  
Devices  
ERROR or ALARM  
ERROR  
ALARM  
Resets watchdog timer  
Executes program  
Resets watchdog timer  
Input and output  
refreshing  
139  
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Cycle Time  
Section 6-2  
The first three operations immediately after power application are performed  
once each time the PC is turned on. The then on the operations shown  
above are performed in cyclic fashion, with each cycle forming one cycle.  
The cycle time is the time that is required for the CPU to complete one of  
these cycles. This cycle includes four types of operation.  
1, 2, 3... 1. Overseeing  
2. Input/Output refreshing  
3. Peripheral Device servicing  
4. Instruction execution  
Cycle time = Overseeing time + Input/output refreshing + Peripheral  
Device servicing time + Instruction execution time  
1
2
Overseeing  
Watchdog timer set and program memory  
and I/O bus checked.  
1.6 ms (Fixed)  
Peripheral Device  
servicing  
Commands from Program Devices and  
Interface Units processed.  
T = ( 1 + 3 + 4 ) x 0.05.  
T <= 1, execution time = 1 ms.  
T > 1, round off in units of 0.5 ms  
(e.g.,1.65 ms rounds to 1.5 ms)  
No peripherals connected = 0 ms.  
3
4
Instruction  
execution  
Instructions executed.  
Total of execution time for each instruction.  
Varies with program size, the instructions  
used, and execution conditions. Refer to  
6-4 Instruction Execution Times for details.  
Input refreshing  
Output refreshing  
Reading data input from input terminals  
and writing the results of instruction  
execution to output terminals.  
0.51 ms + 0.03 ms times N where N =  
number of input and output words – 2.  
The cycle time can be obtained by adding the four cycle time components  
identified above. An adequately short cycle time is important to ensure effi-  
cient, error-free operation.  
Watchdog Timer and Long  
Cycle Times  
Within the PC, the watchdog timer measures the cycle time and compares it  
to a set value. If the cycle time exceeds the set value of the watchdog timer,  
an error is generated and the CPU stops.  
Even if the cycle time does not exceed the set value of the watchdog timer, a  
long cycle time can adversely affect the accuracy of system operations as  
shown in the following table.  
Cycle time (ms)  
10 or greater  
Possible adverse affects  
TIMH(15) becomes inaccurate.  
100 or greater  
0.1-second clock pulse generator SR 1900 may  
malfunction.  
Between  
ALARM indicator on the CPU lights and SR 1809 turns ON.  
100 and 130  
130 or greater  
ERROR indicator on the CPU lights and the system halts.  
140  
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Calculating Cycle Time  
Section 6-3  
6-3  
Calculating Cycle Time  
The PC configuration, the program, and program execution conditions must  
be taken into consideration when calculating the cycle time. This means tak-  
ing into account such things as the number of I/O points, the programming  
instructions used, and whether or not Peripheral Devices are employed. This  
subsection shows some basic cycle time calculation examples.  
6-3-1  
Single PC Unit  
Configuration: A single C20K CPU.  
Program: 300 addresses.  
Instructions Used: LD and OUT.  
Calculations  
The equation for the cycle time from above is as follows:  
Cycle time = Overseeing time  
+ Input/output refreshing  
+ Peripheral device servicing time  
+ Instruction execution time  
The overseeing time is fixed at 1.6 ms.  
The input/output refresh time would be as follows: 0.51 ms + ( 0.03 ms x N ).  
As the C20K is provided with only one input and one output word the value of  
the constant N is 0 (i.e. N = 2 – 2 = 0) and so the time required is 0.51 ms + (  
0.03 ms x 0 ) = 0.51 ms.  
The execution time can be calculated by obtaining the average instruction  
execution time and multiplying this by the number of addresses used in the  
program. As only LD and OUT are used in this program and they have ex-  
ecution times of 12 µs and 17.5 µs respectively, the average instruction ex-  
ecution time is:  
12 µs + 17.5 µs  
= 14.75 µs  
2
The total execution time is equal to this average instruction execution time  
multiplied by the number of program addresses.  
Total execution time = 300 addresses x 14.75 µs = 4.43 ms  
The peripheral device servicing time is calculated by adding the other three  
time values and multiplying the result by a factor of 0.05. This value is only  
required in configurations where a peripheral device is connected to the PC.  
The result is calculated as an example. As there are no peripheral devices  
used in this example the following results will be ignored in the final calcula-  
tion.  
Peripheral device servicing = (1.6 ms + 0.51 ms + 4.43 ms) x 0.05 = 0.3 ms  
As this is less than 1 ms it must be rounded up to 1 ms. Had it been over 1  
ms it would then need to be rounded down to the nearest 0.5 ms.  
141  
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Calculating Cycle Time  
Section 6-3  
The cycle time is the total of all these calculations.  
1.6 ms + 0.51 ms + 4.43 ms = 6.54 ms  
If a peripheral device had been present it would have been:  
1.6 ms + 0.51 ms + 4.43 ms + 1 ms = 7.54 ms  
Process  
Formula  
Peripheral device servicing (ms)  
With  
Without  
1. Overseeing  
Fixed  
1.6  
1.6  
2. Input/output refreshing  
3. Peripheral device servicing  
4. Instruction execution  
Total  
0.29 + 0.07 * (1–1)  
((1) + (3) + (4)) * 0.05 = 0.3 < 1  
14.75 * 300  
0.51  
1.00  
4.43  
7.54  
0.51  
0.00  
4.43  
6.54  
(1) + (2) + (3) + (4)  
6-3-2  
PC with Additional Units  
Configuration: A C40K CPU, a C40P Expansion I/O Unit, an I/O Link Unit.  
Program: 1150 addresses.  
Average instruction execution time: 30 µs.  
Calculations  
The equation for the cycle time from above is as follows:  
Cycle time = Overseeing time  
+ Input/output refreshing  
+ Peripheral device servicing time  
+ Instruction execution time  
The overseeing time is fixed at 1.6 ms.  
The input/output refresh time would be as follows: 0.51 ms + (0.03 ms x N ).  
As the C40K is provided with only one input and one output word and the  
C40P Expansion unit contains input and output words the value of the con-  
stant N is 8. (i.e., N = 10 – 2 = 8) and so the time required is 0.51 ms + (0.03  
ms x 8) = 0.75 ms.  
The total execution time can be calculated by obtaining the average instruc-  
tion execution time and multiplying this by the number of addresses used in  
the program. As given above the average instruction execution time is 30 µs.  
Total execution time = 1150 addresses x 30 µs = 34.50 ms  
The peripheral device servicing time is calculated by adding the other three  
time values and multiplying the result by a factor of 0.05. This value is only  
required in configurations where a peripheral device is connected to the PC.  
The result is calculated as an example. As there are no peripheral devices  
used in this example the following results will be ignored in the final calcula-  
tion.  
Peripheral device servicing = (1.6 ms + 0.75 ms + 34.50 ms) x 0.05 =  
1.84 ms which is rounded down to 1.50 ms.  
142  
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Instruction Execution Times  
Section 6-4  
The cycle time is the total of all these calculations.  
1.6 ms + 0.75 ms + 34.50 ms = 36.85 ms  
If a peripheral device had been present it would have been:  
1.6 ms + 0.75 ms + 34.50 ms + 1.50 ms = 38.35 ms  
Process  
Formula  
Peripheral device servicing (ms)  
With  
Without  
1. Overseeing  
Fixed  
1.6  
1.6  
2. Input/output refreshing  
3. Peripheral device servicing  
4. Instruction execution  
Total  
0.29 + 0.07 * (1–1)  
((1) + (2) + (4)) * 0.05 = 1.8 >1  
30 * 1150  
0.75  
1.50  
34.50  
38.35  
0.75  
0.00  
34.50  
36.85  
(1) + (2) + (3) + (4)  
6-4  
Instruction Execution Times  
This following table lists the execution times for all instructions that are avail-  
able for the K-types. The maximum and minimum execution times and the  
conditions which cause them are given where relevant.  
Execution times for most instructions depend on whether they are executed  
with an ON or an OFF execution condition. The OFF execution time for an  
instruction can also vary depending on the circumstances, i.e., whether it is  
in an interlocked program section and the execution condition for IL is OFF,  
whether it is between JMP(04) 00 and JME(05) 00 and the execution condi-  
tion for JMP(04) 00 is OFF, or whether it is reset by an OFF execution condi-  
tion. “R,” “IL,” and “JMP” are used to indicate these three times.  
Execution times are expressed in microseconds except where noted.  
Function Instruction  
code  
Execution  
time(µs)  
Conditions  
---  
LD  
12  
Always  
Always  
Always  
Always  
Always  
Always  
Always  
Always  
LD NOT  
AND  
12  
11.5  
11.5  
11.5  
11.5  
4
AND NOT  
OR  
OR NOT  
AND LD  
OR LD  
OUT  
4
17  
When outputting logical “1” (ON)  
When outputting logical “0” (OFF)  
When outputting logical “1” (ON)  
When outputting logical “0” (OFF)  
When timing  
17.5  
19  
OUT NOT  
TIM  
17.5  
95  
95.5 to 186.5 When reset  
CNT  
80.5  
When counting  
91.5 TO 184  
When reset  
00  
01  
02  
03  
04  
05  
08  
NOP  
END  
IL  
2
Always  
—
Refer to Cycle Time Calculation Example.  
2.5  
Always  
Always  
Always  
Always  
Always  
ILC  
3
JMP  
JME  
STEP  
94  
38  
60 to 127  
143  
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Instruction Execution Times  
Section 6-4  
Function Instruction  
code  
Execution  
time(µs)  
Conditions  
09  
10  
SNXT  
SFT  
100  
Always  
102  
When shifting 1 word  
When shifting 13 words  
248  
90 to 254  
19  
When reset (1 to 13 words)  
When set  
11  
12  
13  
14  
15  
16  
20  
21  
22  
23  
24  
30  
31  
KEEP  
CNTR  
DIFU  
DIFD  
TIMH  
WSFT  
CMP  
MOV  
MVN  
BIN  
20  
When reset  
95  
When counting DOWN  
190.5  
60.5  
56.5  
59  
When counting UP (word specified)  
When input = 1  
When input = 0  
When input = 1  
62.5  
94.5  
97 to 187.5  
97  
When input = 0  
When timing  
When reset  
When shifting DM by 1 word  
When shifting DM by 64 words  
When comparing a constant with word data  
When comparing a TIM/CNT with word data  
When transferring a constant to a word  
When transferring a TIM/CNT to a word  
When inverting & transferring a constant to a word  
When inverting & transferring a TIM/CNT to a word  
When converting & transferring a TIM/CNT to a word  
When converting & transferring a word to a word  
When converting & transferring DM to DM  
When converting & transferring data in other areas  
When adding two words  
825.5  
121.5  
212  
109  
196  
108.5  
196  
115  
193.5  
194  
BCD  
ADD  
SUB  
202.5  
233  
352  
When adding a TIM/CNT to a constant  
When subtracting a word from a word  
When subtracting a constant from a TIM/CNT  
When multiplying a DM word by a DM word  
When dividing a DM word by a DM word  
Always  
237.5  
356.5  
655  
32  
33  
40  
41  
60  
61  
62  
63  
76  
MUL  
DIV  
572  
STC  
16  
CLC  
16  
Always  
RDM  
HDM  
ENDW  
NETW  
MLPX  
695  
At reset  
734  
Always  
197  
With DM word  
58  
Always  
212.5  
288  
Word, 1 digit (constant) —> word  
Word, 4 digits (constant) —> word  
TIM/CNT, 1 digit (TIM/CNT) —> word  
TIM/CNT, 4 digits (TIM/CNT) —> word  
Word, 1 digit (constant) —> word  
Word, 4 digits (constant) —> word  
TIM/CNT, 1 digit (TIM/CNT) —> word  
TIM/CNT, 4 digits (TIM/CNT) —> word  
When shifting one word  
355  
431  
77  
DMPX  
298.5  
658.5  
456  
1,080  
145  
743  
When shifting 64 DM words  
144  
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I/O Response Time  
Section 6-5  
Function Instruction  
code  
Execution  
time(µs)  
Conditions  
84  
SFTR  
136 to 668  
When resetting 1 to 64 DM words  
44  
42  
75  
26  
49  
108  
NOP  
IL  
91  
92  
93  
97  
SBS  
SBN  
RET  
IORF  
Always  
Always  
Always  
When refreshing 1 word  
6-5  
I/O Response Time  
The I/O response time is the time it takes for the PC to output a control signal  
after it has received an input signal. How long it takes to respond depends on  
the cycle time and when the CPU receives the input signal relative to the in-  
put refresh period. The I/O response times for a PC not in a Link System are  
discussed below. For response times for PCs with Link Systems, refer to the  
relevant System Manual.  
The minimum and maximum I/O response time calculations described below  
are for the following, where 0000 is the input bit that receives the signal and  
0200 is the output bit corresponding to the desired output point.  
0000  
0200  
Minimum I/O Response  
Time  
The PC responds most quickly when it receives an input signal just prior to  
the input refresh period in the cycle. Once the input bit corresponding to the  
signal has been turned ON, the program will have to be executed once to  
turn ON the output bit for the desired output signal and then the input refresh  
and overseeing operations would have to be repeated before the output from  
the output bit was refreshed. The I/O response time in this case is thus found  
by adding the input ON-delay time, the cycle time, the I/O refresh time, the  
overseeing time, and the output ON-delay time. This situation is illustrated  
below.  
Overseeing  
CPU reads  
input signal  
Cycle time  
Cycle time  
Cycle  
I/O refresh  
Input  
signal  
CPU writes  
output signal  
Input ON delay  
Output ON delay  
Output  
signal  
I/O response time  
Minimum I/O response time = Input ON delay + Cycle time + I/O refresh time  
+ Overseeing time + Output ON delay  
145  
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I/O Response Time  
Section 6-5  
Maximum I/O Response  
Time  
The PC takes longest to respond when it receives the input signal just after  
the input refresh phase of the cycle. In this case the CPU does not recognize  
the input signal until the end of the next cycle. The maximum response time  
is thus one cycle longer than the minimum I/O response time, except that the  
input refresh time would not need to be added in because the input comes  
just after it rather than before it.  
Overseeing  
Cycle  
Cycle time  
Cycle time  
I/O refresh  
Input  
signal  
CPU reads  
input signal  
CPU writes  
output signal  
Input ON delay  
Output ON delay  
Output  
signal  
I/O response time  
Maximum I/O response time = input ON delay + (cycle time x 2) + overseeing  
time + output ON delay  
Calculation Example  
The data in the following table would produce the minimum and maximum  
cycle times shown calculated below.  
Input ON-delay  
Cycle time  
1.5 ms  
20 ms  
Input refresh time  
Overseeing time  
Output ON-delay  
0.23 ms  
3.0 ms  
15 ms  
Minimum I/O response time = 1.5 + 20 + 0.23 + 3.0 +15 = 39.73 ms  
Maximum I/O response time = 1.5 + (20 x 2) + 3.0 +15 = 59.5 ms  
146  
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SECTION 7  
Program Debugging and Execution  
7-1  
7-2  
7-3  
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Debugging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Monitoring Operation and Modifying Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
148  
148  
149  
150  
153  
155  
156  
157  
158  
159  
7-3-1  
7-3-2  
7-3-3  
7-3-4  
Bit/Digit Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Force Set/Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Hexadecimal/BCD Data Modification . . . . . . . . . . . . . . . . . . . . . . . . .  
Changing Timer/Counter SV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
7-4  
Program Backup and Restore Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
7-4-1  
7-4-2  
Saving Program Memory Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Restoring or Comparing Program Memory Data . . . . . . . . . . . . . . . . .  
147  
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Debugging  
Section 7-2  
7-1  
Introduction  
This section provides the procedures for inputting and debugging a program  
and monitoring and controlling the PC through a Programming Console. The  
Programming Console is the most commonly used Programming Device for  
the K-type PCs. It is compact and available both in hand-held models or  
CPU-mounted models. Refer to Appendix A Standard Models for model num-  
bers and other details.  
If you are using a GPC, FIT, or a computer running LSS, refer to the Opera-  
tion Manual for corresponding procedures on these. If you are going to use a  
GPC, FIT, or a computer running LSS, but want to input in mnemonic code  
rather than in ladder diagram form, refer to 4-3-2 Mnemonic Code.  
7-2  
Debugging  
After inputting a program and correcting it for syntax errors, it must be exe-  
cuted and all execution errors must be eliminated. Execution errors include  
an excessively long cycle time, errors in settings for various Units in the PC,  
and inappropriate control actions, i.e., the program not doing what it is de-  
signed to do.  
When necessary, the program can first be executed isolated from the actual  
control system and wired to artificial inputs and outputs to check for certain  
types of errors before actual trial operation with the controlled system.  
Displaying and Clearing  
Error Messages  
When an error occurs during program execution, it can be displayed for iden-  
tification by pressing CLR, FUN, and then MONTR. If an error message is  
displayed, the MONTR key can be press to access any other error messages  
that are stored by the system in memory. If MONTR is pressed in PROGRAM  
mode, the error message will be cleared from memory; be sure to write down  
the error message when required before pressing MONTR. OK will be dis-  
played when the last message has been cleared.  
If a beeper sounds and the error cannot be cleared by pressing MONTR, the  
cause of the error still exists and must be eliminated before the error mes-  
sage can be cleared. If this happens, take the appropriate corrective action to  
eliminate the error. Refer to Section 8 Troubleshooting for all details on all  
error messages. The sequence in which error messages are displayed de-  
pends on the priority levels of the errors. The messages for fatal errors (i.e.,  
those that stop PC operation) are displayed before non-fatal ones.  
Although error messages can be displayed in any mode, they can be cleared  
only in PROGRAM mode. There is no way to restart the PC following a fatal  
error without first clearing the error message in PROGRAM mode.  
Key Sequence  
148  
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Monitoring Operation and Modifying Data  
Section 7-3  
Example  
The following displays show some of the messages that may appear. Refer  
to Section 8 Troubleshooting for an inclusive list of error messages, mean-  
ings, and appropriate responses.  
Note Cycle time is displayed as scan time.  
0000  
0000  
FUN (??)  
0000ERR CHK  
OK  
MEMORY ERR  
NO END INST  
I/O BUS ERR  
Fatal  
errors  
BATT LOW  
Non-fatal  
errors  
SCAN TIME OVER  
All errors  
have been  
cleared  
0000ERR CHK  
OK  
7-3  
Monitoring Operation and Modifying Data  
The simplest form of operation monitoring is to display the address whose  
operand bit status is to be monitored using the Program Read or one of the  
search operations. As long as the operation is performed in RUN or MONI-  
TOR mode, the status of any bit displayed will be indicated.  
This section provides other procedures for monitoring data as well as proce-  
dures for modifying data that already exists in a data area. Data that can be  
modified includes the PV (present value) and SV (set value) for any timer or  
counter.  
All monitor operations in this section can be performed in RUN, MONITOR,  
or PROGRAM mode and can be cancelled by pressing the CLR key.  
All data modification operations except for timer/counter SV changes are per-  
formed after first performing one of the monitor operations. Data modification  
is possible in either MONITOR or PROGRAM mode, but cannot be per-  
formed in RUN mode.  
149  
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Monitoring Operation and Modifying Data  
Section 7-3  
7-3-1  
Bit/Digit Monitor  
The status of any bit or word in any data area can be monitored using the  
following operation. Although the operation is possible in any mode, ON/OFF  
status displays will be provided for bits only in MONITOR or RUN mode.  
The Bit/Digit Monitor operation can be entered either from a cleared display  
by designating the first bit or word to be monitored or it can be entered from  
any address in the program by displaying the bit or word address whose  
status is to be monitored and pressing MONTR.  
When a bit is monitored, it’s ON/OFF status will be displayed (in MONITOR  
or RUN mode); when a word address is designated other than a timer or  
counter, the digit contents of the word will be displayed; and when a timer or  
counter number is designated, the PV of the timer will be displayed and a  
small box will appear if the timer or counter’s completion flag is ON. The  
status of TR bits and SR flags cleared when END(01) is executed (e.g., the  
arithmetic flags) cannot be monitored.  
Up to six memory addresses, either bits, words, or a combination of both,  
can be monitored at once, although only three of these are displayed at any  
one time. To monitor more than one address, return to the start of the proce-  
dure and continue designating addresses. Monitoring of all designated ad-  
dresses will be maintained unless more than six addresses are designated. If  
more than six addresses are designated, the leftmost address of those being  
monitored will be cancelled.  
To display addresses that are being monitored but are not presently on the  
Programming Console display, press MONTR without designating another  
address. The addresses being monitored will be shifted to the right. As  
MONTR is pressed, the addresses being monitored will continue shifting to  
the right until the rightmost address is shifted back onto the display from the  
left.  
During a monitor operation the up and down keys can be pressed to incre-  
ment and decrement the leftmost address on the display and CLR can be  
pressed to cancel monitoring the leftmost address on the display. If the last  
address is cancelled, the monitor operation will be cancelled. The monitor  
operation can also be cancelled regardless of the number of addresses being  
monitored by pressing SHIFT and then CLR.  
LD and OUT can be used only to designate the first address to be displayed;  
they cannot be used when an address is already being monitored.  
150  
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Monitoring Operation and Modifying Data  
Section 7-3  
Key Sequence  
Examples  
The following examples show various applications of this monitor operation.  
Program Read then Monitor  
0100  
0100READ  
TIM  
00  
T00  
1234  
T00  
!0000  
Indicates Completion flag is ON  
Monitor operation  
is cancelled  
0100  
TIM  
01  
151  
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Monitoring Operation and Modifying Data  
Section 7-3  
Bit Monitor  
0000  
0000  
LD  
0001  
0001  
ON  
0000  
CONT  
0001  
Word Monitor  
0000  
0000  
CHANNEL  
00  
0000  
CHANNEL HR  
1
cH1  
FFFF  
cH0  
0000  
152  
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Monitoring Operation and Modifying Data  
Section 7-3  
Multiple Address Monitoring  
0000  
0000  
TIM  
00  
T00  
0100  
0000 T00  
0100  
0001 T00  
0100  
0001 T00  
OFF 0100  
D00 0001 T00  
OFF 0100  
D00 0001 T00  
10FF OFF 0100  
T00 D00 0001  
0100 10FF OFF  
D00 0001  
10FF^ OFF  
Cancels monitoring of  
leftmost address  
0001  
OFF  
0000  
CONT  
0001  
0000  
Cancels Monitor  
operation  
CHANNEL DM 00  
7-3-2  
Force Set/Reset  
When the Bit/Digit Monitor operation is being performed and a bit, timer, or  
counter address is leftmost on the display, PLAY/SET can be pressed to turn  
ON the bit, start the timer, or increment the counter and REC/RESET can be  
pressed to turn OFF the bit or reset the timer or counter. Timers will not oper-  
ate in PROGRAM mode. SR bits cannot be turned ON and OFF with this op-  
eration.  
Bit status will remain ON or OFF for only one scan after pressing the key; it  
will then return to its original status. When timers or counters are reset in  
MONITOR mode, they will start after one scan.  
This operation can be used in MONITOR mode to check wiring of outputs  
from the PC prior to actual program execution. This operation cannot be  
used in RUN mode.  
153  
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Monitoring Operation and Modifying Data  
Section 7-3  
Key Sequence  
Example  
The following example shows how either bits or timers can be controlled with  
the Force Set/Reset operation. The displays shown below are for the follow-  
ing program section.  
0002  
TIM 00  
SV  
0003  
TIM 00  
0501  
0501  
Address Instruction  
Operands  
0002  
0200  
0201  
LD  
TIM  
00  
0123  
00  
#
0202  
0203  
0204  
0205  
LD  
TIM  
OR  
0501  
0003  
0501  
AND NOT  
OUT  
154  
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Monitoring Operation and Modifying Data  
Section 7-3  
The following displays show what happens when TIM 00 is set with 0100  
OFF (i.e., 0500 is turned ON) and what happens when TIM 00 is reset with  
0100 ON (i.e., timer starts operation, turning OFF 0500, which is turned back  
ON when the timer has finished counting down the SV).  
0000  
0000  
OUT  
0500  
0501  
0000  
OUT  
0501  
OFF  
0501  
ON  
0501  
OFF  
T00 0501  
OFF  
T00 0501  
0123 OFF  
T00 0501  
!0000 ON  
Returns to the  
original condition  
after a scan  
Indicates  
that the  
time is up  
T00 0501  
0123 OFF  
T00 0501  
!0000 ON  
T00 0501  
0123 OFF  
The timer  
commences after  
the first scan  
T00 0501  
0122 OFF  
OUT 0501 is ON  
after the timer has  
reached its SV  
T00 0501  
!0000 ON  
7-3-3  
Hexadecimal/BCD Data Modification  
When the Bit/Digit Monitor operation is being performed and a BCD or hexa-  
decimal value is leftmost on the display, CHG can be input to change the  
value. SR words cannot be changed.  
If a timer or counter is leftmost on the display, the PV will be displayed and  
will be the value changed. See 7-3-4 Changing Timer/Counter SV for the pro-  
cedure to change SV. PV can be changed in MONITOR mode and only when  
the timer or counter is operating.  
155  
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Monitoring Operation and Modifying Data  
Section 7-3  
To change contents of the leftmost word address, press CHG, input the de-  
sired value, and press WRITE.  
Key Sequence  
Example  
The following example shows the effects of changing the PV of a timer.  
This example is in MONITOR mode  
0000  
0000  
TIM  
00  
T00  
0122  
Timing  
0000PRES VAL?  
T00 0119 ????  
PV changed  
Timing  
Timing  
Timing  
0000PRES VAL?  
T00 0100 0200  
T00  
0199  
7-3-4  
Changing Timer/Counter SV  
The SV of a timer or counter can be changed by inputting a new value nu-  
merically when in MONITOR mode. The SV can be changed while the pro-  
gram is being executed.  
To change the SV, first display the address of the timer or counter whose SV  
is to be changed, press the down key, and then press CHG. The new value  
can then be input numerically and WRITE pressed to change the SV.  
When changing the SV of timers or counters while operation is stopped, use  
PROGRAM mode and follow the procedure outlined in 4-6-2 Inputting or  
Overwriting Programs.  
This operation can be used to change a SV from designation as a constant to  
a word address designation or from a word address to a constant designa-  
tion.  
156  
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Program Backup and Restore Operations  
Section 7-4  
Key Sequence  
Example  
The following example shows inputting a new constant and changing from a  
constant to a word designation.  
Inputting New SV  
0000  
0000  
TIM  
00  
00  
0201SRCH  
TIM  
0201 TIM DATA  
#0123  
0201 TIM DATA  
T00 #0123 #????  
0201 TIM DATA  
T00 #0123 #0124  
0201 TIM DATA  
#0124  
0201 DATA?  
T00 #0123 c???  
0201 DATA?  
T00 #0123 c 10  
0201 TIM DATA  
10  
7-4  
Program Backup and Restore Operations  
Program Memory (UM) can be backed-up on a standard commercially avail-  
able cassette tape recorder. Any kind of dependable magnetic tape of ade-  
quate length will suffice. To save a 16K-word program, the tape must be 30  
minutes long. Always allow about 5 seconds of blank tape leader before the  
taped data begins. Store only one program on a single side of a tape; there is  
no way to identify separate programs stored on the same side of the tape. If  
a program is longer than will fit on one side, it can be split onto two sides.  
Be sure to label the contents of all cassette tapes clearly.  
Use patch cords to connect the cassette recorder earphone (or LINE-OUT)  
jack to the Programming Console EAR jack and the cassette recorder micro-  
phone (or LINE-IN) jack to the Programming Console MIC jack. Set the cas-  
sette recorder volume and tone controls to maximum levels.  
157  
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Program Backup and Restore Operations  
Section 7-4  
The PC must be in PROGRAM mode for all cassette tape operations.  
While the operation is in progress, the cursor will blink and the block count  
will be incremented on the display.  
Cassette tape operations may be halted at any time by pressing the CLR key.  
Error Messages  
The following error messages may appear during cassette tape operations.  
Message  
Meaning and appropriate response  
0000 ERR *******  
FILE NO.********  
File number on cassette and designated file number are  
not the same. Repeat the operation using the correct file  
number.  
**** MT VER ERR  
**** MT ERR  
Cassette tape contents differs from that in the PC. Check  
content of tape and/or the PC.  
Cassette tape is faulty. Replace it with another.  
7-4-1  
Saving Program Memory Data  
This operation is used to copy the content of Program Memory to a cassette  
tape. The procedure is as follows:  
1, 2, 3...  
Press EXT.  
Input a file number for the data that is to be saved.  
Start cassette tape recording.  
Within 5 seconds, press the SHIFT and REC/RESET keys.  
Program saving continues until END(01) or the final address is reached.  
Cancel by pressing the CLR key.  
Key Sequence  
158  
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Program Backup and Restore Operations  
Section 7-4  
Example  
0000  
0000MT  
FILE NO!00000000  
0000MT  
FILE NO!00000012  
Start recording  
Continue within 5 seconds  
Blinking  
0000MT RECORD ~  
FILE NO!00000012  
Recording in progress  
0075MT RECORD ~  
FILE NO!00000012  
When it comes to END  
0145MT RECORD ~  
END (01)  
Stop recording with CLR  
0145MT DISCONTD  
END (01) (0100)  
Saved up to stop address  
1193RECORD END  
END (01) (0497)  
7-4-2  
Restoring or Comparing Program Memory Data  
This operation is used to restore Program Memory data from a cassette tape  
or to compare Program Memory data with the contents on a cassette tape.  
The procedure is as follows:  
1, 2, 3...  
Press EXT.  
Specify the number of the file to be restored or compared.  
Start playing the cassette tape.  
Within 5 seconds, press SHIFT and PLAY/SET to restore data or VER to  
compare data.  
Program restoration or comparison continues until the final address or  
END(01) is reached or until the tape is finished. Cancel by pressing the CLR  
key.  
To restore or compare program data recorded on two sides of a tape or on  
two or more tapes, begin restoring or comparing from the lowest address.  
159  
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Program Backup and Restore Operations  
Section 7-4  
Key Sequence  
Example  
0000  
0000MT  
FILE NO!00000000  
0000MT  
FILE NO!00000012  
0000MT PLAY  
~
0034MT PLAY  
~
FILE NO!00000012  
FILE NO!00000012  
Restoring in progress  
Comparison in progress  
0242MT PLAY  
~
0242MT PLAY  
~
FILE NO!00000012  
FILE NO!00000012  
END reached  
END reached  
0480MT RECORD ~  
END (01)  
0486MT RECORD ~  
END (01)  
Restored up to END  
Stop comparison using CLR  
1193MT DISCONTD  
END (01) (0100)  
0480MT DISCONTD  
END (01)  
Compared up to end of tape  
Stop restoring using CLR  
0145 RECORD END  
END (01) (0100)  
0578 RECORD END  
END (01)  
160  
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SECTION 8  
Troubleshooting  
8-1  
8-2  
8-3  
8-4  
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
162  
162  
162  
164  
Reading and Clearing Errors and Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Error Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Error Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
161  
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Error Messages  
Section 8-3  
8-1  
Introduction  
The K-type PCs provide self-diagnostic functions to identify many types of  
abnormal system conditions. These functions minimize downtime and enable  
quick, smooth error correction.  
This section provides information on hardware and software errors that occur  
during PC operation. Program input and program syntax errors are described  
in Section 4 Writing and Inputting the Program. Although described in Section  
3 Memory Areas, flags and other error information provided in SR areas are  
listed in 8-4 Error Flags.  
There are two indicators on the front of the CPU that provide visual indication  
of an abnormality in the PC. The error indicator (ERR) indicates fatal errors  
(i.e., ones that will stop PC operation); the alarm indicator (ALARM) indicates  
nonfatal ones. These indicators are shown in 2-2 Indicators.  
DANGER  
The PC will turn ON the error indicator (ERR), stop program execution, and turn  
OFF all outputs from the PC for most hardware errors, or certain fatal software  
errors. PC operation will continue for all other errors. It is the user’s responsibility  
to take adequate measures to ensure that a hazardous situation will not result  
from automatic system shutdown for fatal errors and to ensure that proper  
actions are taken for errors for which the system is not automatically shut down.  
System flags and other system and/or user-programmed error indications can  
be used to program proper actions.  
!
8-2  
Reading and Clearing Errors and Messages  
System error messages can be displayed on the Programming Console or  
any other Programming Device.  
On the Programming Console, press the CLR, FUN, and MONTR keys. If  
there are multiple error messages stored by the system, the MONTR key can  
be pressed again to access the next message. If the system is in PROGRAM  
mode, pressing the MONTR key will clear the error message, so be sure to  
write down all message errors as you read them out. (It is not possible to  
clear an error or a message while in RUN or MONITOR mode; the PC must  
be in PROGRAM mode.) When all messages have been cleared, “ERR CHK  
OK” will be displayed.  
Details on accessing error messages from the Programming Console are  
provided in 7-3 Monitoring Operation and Modifying Data. Procedures for the  
GPC, LSS, and FIT are provided in the relevant Operation Manual.  
8-3  
Error Messages  
There are basically two types of errors for which messages are displayed:  
non-fatal operating errors, and fatal operating errors.  
The type of error can be quickly determined from the indicators on the CPU,  
as described below for the two types of errors. If the status of an indicator is  
not mentioned, it makes no difference whether it is lit or not.  
After eliminating the cause of an error, clear the error message from memory  
before resuming operation.  
162  
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Error Messages  
Section 8-3  
Non-fatal Operating Errors The following error messages appear for errors that occur after program exe-  
cution has been started. PC operation and program execution will continue  
after one or more of these error have occurred. The POWER, RUN, and  
ALARM indicators will be lit and the ERR indicator will not be lit for any of  
these errors. The RUN output will be ON.  
Error and message  
Cycle time overrun  
Probable cause  
Possible correction  
Watchdog timer has exceeded 100  
ms.  
Program cycle time is longer then  
desirable. Reduce cycle time if  
possible.  
SCAN TIME OVER  
Backup battery is missing or it’s  
voltage has dropped.  
Check battery and replace if  
necessary.  
Battery error  
BATT LOW  
Fatal Operating Errors  
The following error messages appear for errors that occur after program exe-  
cution has been started. PC operation and program execution will stop and  
all outputs from the PC will be turned OFF when any of the following errors  
occur. All CPU indicators will not be lit for the power interruption error. For all  
other fatal operating errors, the POWER, and ERR indicators will be lit and  
the RUN indicator will not be lit. The RUN output will be OFF.  
Error and message  
Probable cause  
Possible correction  
Power has been interrupted for at  
least 10 ms.  
Check power supply voltage and  
power lines. Try to power-up again.  
Power interruption  
No message  
Watchdog timer has exceeded  
maximum setting (default setting: 130 and check program. Reduce cycle  
Restart system in PROGRAM mode  
CPU error  
ms).  
time or reset watchdog timer if longer  
time required. (Consider effects of  
longer cycle time before resetting).  
No message  
Memory Unit is incorrectly mounted or Check Memory Unit to make sure it is  
Memory error  
missing or parity error has occurred.  
mounted and backed up properly.  
Perform a Program Check Operation  
to locate cause of error. If error not  
correctable, try inputting program  
again.  
MEMORY ERR  
END(01) is not written anywhere in  
program.  
Write END(01) at the final address of  
the program.  
No END(01) instruction  
NO END INST  
Error has occurred in the bus line  
between the CPU and Units.  
Check the CPU Left/Right selector  
switch on the Expansion I/O Unit.  
Check cable connections between the  
Units and Racks.  
I/O bus error  
I/O BUS ERR  
163  
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Error Flags  
Section 8-4  
8-4  
Error Flags  
The following table lists the flags and other information provided in the SR  
area that can be used in troubleshooting. Details are provided in 3-4 Special  
Relay (SR) Area.  
SR Area  
Address  
Function  
1808  
1809  
1903  
Battery Alarm Flag  
Cycle Time Error Flag  
Instruction Execution Error (ER) Flag  
Other Error Messages  
A number of other error messages are detailed within this manual. Errors in  
program input and debugging can be examined in 4-6-2 Inputting and Over-  
writing Programs and 4-6-3 Checking the Program and errors in cassette  
tape operation are detailed in 7-4 Program Backup and Restore Operations.  
164  
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Appendix A  
Standard Models  
There are four K-type C-series CPUs. A CPU can be combined with any of six types of Expansion I/O Unit  
and/or an Analog Timer, Analog I/O Unit, or I/O Link Unit.  
Analog Timer Unit  
CPUs  
Expansion I/O Units  
C4K-TM  
C20K-Cjj-j  
C4K-Ij/Ojj  
C20P  
To order  
C4K-CN502  
(included with Unit)  
cable sepa-  
rately, specify  
C4K-CN502  
Analog I/O Units  
C16P-Ij-j/Oj-j  
C28K-Cjj-j  
C1K-AD/DA  
C28P  
C16P  
5 cm or 40 cm  
One included  
with each Ex-  
pansion I/O  
Unit.  
Cable (70 cm)  
C20P-CN711  
(ordered separately)  
C20P-Ejj-j  
C40K-Cjj-j  
C4K-AD  
C20P  
C4K - AD  
C40P  
C60K-Cjj-j  
C28P-Ejj-j  
C28P  
C60P  
C40P-Ejj-j  
I/O Link Unit  
C40P  
C20-LK011/LK011-P  
C60P-Ejj-j  
C60P  
165  
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Standard Models  
Appendix A  
CPUs  
Name  
Power supply  
Inputs  
Outputs  
Relay w/socket  
Model number  
Standards  
C20K  
100 to 240 VAC  
24 VDC, 12 pts  
8 pts  
C20K-CDR-A  
C20K-CDT1-A  
C20K-CDS1-A  
C20K-CAR-A  
C20K-CAS1-A  
U, C  
Transistor, 1 A  
Triac, 1 A  
U, C  
U, C  
24 VDC, 2 pts  
Relay w/socket  
Triac, 1A  
U, C, N, L  
U, C  
100 to 120 VAC,  
10 pts  
24 VDC  
24 VDC, 12 pts  
Relay w/socket  
Transistor, 1 A  
Relay w/socket  
Transistor, 1 A  
Triac, 1 A  
C20K-CDR-D  
C20K-CDT1-D  
U, C  
U
C28K  
100 to 240 VAC  
24 VDC, 16 pts  
12 pts C28K-CDR-A  
C28K-CDT1-A  
C28K-CDS1-A  
C28K-CAR-A  
U, C  
U, C  
U, C  
U, C  
U, C  
24 VDC, 2 pts  
Relay w/socket  
Triac, 1A  
100 to 120 VAC,  
14 pts  
C28K-CAS1-A  
24 VDC  
24 VDC, 16 pts  
Relay w/socket  
Transistor, 1 A  
Relay w/socket  
Transistor, 1 A  
Triac, 1 A  
C40K-CDR-D  
C28K-CDT1-D  
16 pts C40K-CDR-A  
C40K-CDT1-A  
C40K-CDS1-A  
C40K-CAR-A  
U, C  
U, C  
U, C  
U, C  
U, C  
U, C  
U, C  
U, C  
U, C  
U, C  
U, C  
U, C  
U, C  
U, C  
U, C  
---  
C40K  
100 to 240 VAC  
24 VDC, 16 pts  
24 VDC, 2 pts  
100 VAC, 22 pts  
24 VDC, 24 pts  
Relay w/socket  
Triac, 1 A  
C40K-CAS1-A  
C40K-CDR-D  
24 VDC  
Relay w/socket  
Transistor, 1 A  
Relay w/socket  
Transistor, 1 A  
Triac, 1 A  
C40K-CDT1-D  
28 pts C60K-CDR-A  
C60K-CDT1-A  
C60K-CDS1-A  
C60K-CAR-A  
C60K  
100 to 240 VAC  
24 VDC, 32 pts  
24 VDC, 2 pts  
100 VAC, 30 pts  
24 VDC, 32 pts  
Relay w/socket  
Triac, 1 A  
C60K-CAS1-A  
C60K-CDR-D  
24 VDC  
Relay w/socket  
Transistor, 1 A  
C60K-CDT1-D  
• U: UL, C: CSA, N: NK, L: LLOYD  
See Omron sales representatives concerning operating conditions under which UL, CSA, and NK standards were met (Aug. 1991).  
166  
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Standard Models  
Appendix A  
I/O Units  
Name  
Power Supply  
---  
Inputs  
Outputs  
Model number  
C4K-ID  
C4K-IA  
Standards  
C4K I/O Unit  
24 VDC, 4 pts  
100 to 120 VAC, ---  
4 pts  
---  
U, C  
U, C  
---  
Relay w/socket  
Transistor, 1 A  
Triac, 1A  
4 pts  
C4K-OR2  
C4K-OT2  
C4K-OS2  
C16P-ID-A  
U, C  
U, C  
U, C  
U, C  
U, C  
U, C  
U, C  
U, C  
U, C  
C16P I/O Unit 100 to 240 VAC 24 VDC, 16 pts  
---  
---  
Relay w/socket  
Transistor, 1 A  
Triac, 1A  
16 pts C16P-OR-A  
C16P-OT1-A  
C16P-OS1-A  
C16P-ID  
---  
24 VDC, 16 pts  
100 to 120 VAC, ---  
16 pts  
---  
C16P-IA  
24 VDC  
---  
Relay w/socket  
16 pts C16P-OR-D  
C16P-OT1-D  
U, C  
U
Transistor, 1 A  
Relay w/socket  
Transistor, 1 A  
Triac, 1A  
C20P I/O Unit 100 to 240 VAC 24 VDC, 12 pts  
8 pts  
C20P-EDR-A  
C20P-EDT1-A  
C20P-EDS1-A  
C20P-EAR-A  
C20P-EAS1-A  
C20P-EDR-D  
C20P-EDT1-D  
U, C, N, L  
U, C, N, L  
U, C, N, L  
U, C, N, L  
U, C, N, L  
U, C, N, L  
U, C, N, L  
U, C, N, L  
U, C, N, L  
U, C, N, L  
U, C, N, L  
U, C, N, L  
U, C, N, L  
U, C, N, L  
U, C, N, L  
U, C, N, L  
U, C, N, L  
U, C, N, L  
U, C, N, L  
U, C, N, L  
U, C, N, L  
U, C  
100 to 120 VAC, Relay w/socket  
12 pts  
24 VDC, 12 pts  
Triac, 1A  
24 VDC  
Relay w/socket  
Transistor, 1 A  
Relay w/socket  
Transistor, 1 A  
Triac, 1A  
C28P I/O Unit 100 to 240 VAC 24 VDC, 16 pts  
12 pts C28P-EDR-A  
C28P-EDT1-A  
C28P-EDS1-A  
C28P-EAR-A  
100 to 120 VAC, Relay w/socket  
16 pts  
24 VDC, 16 pts  
Triac, 1A  
C28P-EAS1-A  
C28P-EDR-D  
24 VDC  
Relay w/socket  
Transistor, 1 A  
Relay w/socket  
Transistor, 1 A  
Triac, 1A  
C28P-EDT1-D  
16 pts C40P-EDR-A  
C40P-EDT1-A  
C40P-EDS1-A  
C40P-EAR-A  
C40P I/O Unit 100 to 240 VAC 24 VDC, 24 pts  
100 to 120 VAC, Relay w/socket  
24 pts  
24 VDC, 24 pts  
Triac, 1A  
C40P-EAS1-A  
C40P-EDR-D  
24 VDC  
Relay w/socket  
Transistor, 1 A  
Relay w/socket  
Transistor, 1 A  
Triac, 1A  
C40P-EDT1-D  
28 pts C60P-EDR-A  
C60P-EDT1-A  
C60P-EDS1-A  
C60P-EAR-A  
C60P I/O Unit 100 to 240 VAC 24 VDC, 32 pts  
---  
U, C  
U, C  
U, C  
U, C  
---  
100 VAC, 32 pts Relay w/socket  
Triac, 1A  
24 VDC, 32 pts  
C60P-EAS1-A  
C60P-EDR-D  
C60P-EDT1-D  
24 VDC  
Relay w/socket  
Transistor, 1 A  
167  
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Standard Models  
Appendix A  
Special Units  
Name  
Specifications  
Model number  
C4K-TM  
Standards  
Analog Timer Unit  
Settings: 0.1 s to 10 min (one cable, C4K-CN502,  
included)  
U, C  
Analog Timer External  
Connector  
2-m cable and connector  
C4K-CN223  
---  
Analog Input Unit  
1 input; input ranges: 4 to 20 mA, 1 to 5 V  
4 inputs; input ranges: 4 to 20 mA, 1 to 5 V  
1 output; output ranges: 4 to 20 mA, 1 to 5 V  
C1K-AD  
U, C  
U, C  
U, C  
---  
C4K-AD  
Analog Output Unit  
Host Link Unit  
C1K-DA  
RS-232C  
RS-422  
APF/PCF  
PCF  
C20/C20K/C28K/C40K/C60K  
3G2C7-LK201-EV1  
3G2C7-LK202-EV1  
C20-LK011-P  
C20-LK011  
---  
I/O Link Unit  
U, C  
U, C  
---  
I/O Connecting Cable  
For horizontal mounting; cable length: 5 cm  
(for maintenance)  
C20P-CN501  
For vertical mounting; cable length: 40 cm  
(for maintenance)  
C20P-CN411  
---  
I/O Connecting Cable  
For horizontal mounting; connects Cable length: 5 cm C4K-CN502  
---  
---  
to C4K I/O, Analog Timer, or Ana- Cable length: 50  
cm  
C4K-CN512  
log I/O Units (for maintenance)  
Cable length: 1 m  
C4K-CN122  
C20P-CN711  
---  
---  
I/O Link Connecting  
Cable  
Cable length: 70 cm; for I/O Link Units only  
EPROM  
Battery Set  
Relay  
2764  
ROM-H  
L
Built into CPU (same for all C-Series PCs)  
24-VDC contact relay  
24-VDC transistor relay  
24-VDC triac relay  
3G2A9-BAT08  
G6B-1174P-FD-US  
---  
U, C  
G3SD-Z01P-PD-US  
G3S-201PL-PD-US  
U, C  
U, C  
• U: UL, C: CSA, N: NK, L: LLOYD  
See Omron sales representatives concerning operating conditions under which UL, CSA, and NK standards were met (Aug. 1991).  
168  
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Standard Models  
Appendix A  
Mounting Rail and Accessories  
Name  
Specifications  
Model number  
PFP-50N  
Standards  
DIN Track  
Length: 50 cm  
Length: 1 m  
Not usable with  
C60K  
PFP-100N  
PFP-100N2  
PFP-M  
---  
End Plate  
Spacer  
---  
---  
PFP-S  
Factory Intelligent Terminal (FIT)  
Name  
Specifications  
Model number  
Standards  
FIT  
1. FIT Computer  
2. SYSMATE Ladder Pack (2 system disks, 1 data disk)  
3. MS-DOS  
FIT10-SET11-E  
---  
4. GPC Communications Adapter (C500-IF001)  
5. Peripheral Connecting Cable (3G2A2-CN221)  
6. Power Cord and 3-pin/2-pin plug  
7. Carrying Case  
Graphic Programming Console (GPC)  
Name  
Specifications  
Model number  
Standards  
GPC (LCD display)  
W/battery; power supply: 32 kw, 100 VAC;  
w/comments; System Memory Cassette ordered  
separately.  
3G2C5-GPC03-E  
W/battery; power supply: 32 kw, 200 VAC;  
w/comments; System Memory Cassette ordered  
separately.  
3G2C5-GPC04-E  
GPC Carrying Case  
W/side pocket for accessories  
C500-CS001  
For K-Type PCs  
W/comments  
3G2C5-MP304-EV3  
GPC System Memory  
Cassette  
---  
Cassette Interface Unit  
Used to load programs in V8, M1R, M5R, POR, or S6  
cassettes into the GPC and print them out through a  
Printer Interface Unit.  
3G2A5-CMT01-E  
169  
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Standard Models  
Appendix A  
Peripheral Devices  
Name  
Specifications  
Vertical, with backlight  
Horizontal, with backlight  
Model number  
3G2A5-PRO13-E  
3G2A6-PRO15-E  
C200H-PR027-E  
Standards  
U, C  
Programming Console  
---  
Hand-Held, with backlight. The Programming Console  
Adapter AP003 and connecting cable CN222/CN422  
are necessary. They are sold separately.  
U, C  
Programming Console  
Mounting Bracket  
Used to attach Hand-held Programming Console to a  
panel.  
C200H-ATT01  
---  
Programming Console  
Connecting Cables  
For C20K/C28K/C40K/C60K  
1 m  
3G2C7-CN122  
3G2C7-CN512  
C200H-CN222  
C200H-CN422  
3G2A5-AP001-E  
---  
50 cm  
---  
For Hand-held Programming Console 2 m  
4 m  
U, C  
U, C  
---  
Programming Console  
Adapter  
Attached to PC when connecting Programming  
Console via cable (for 3G2A5-PRO13-E or  
3G2A6-PRO15-E).  
Required to use Hand-held Programming Console.  
3G2A5-AP003  
3G2A5-BP001  
---  
---  
Programming Console  
Base  
Attached to Programming Console when connecting  
Programming Console via cable.  
Cassette Recorder  
Connecting Cable  
Used to connect Programming Console, GPC, or  
Cassette Deck Interface Unit to a cassette deck;  
length: 1 m.  
SCYPOR-PLG01  
---  
PROM Writer  
Used for all K-type PCs.  
C500-PRW06  
---  
---  
Printer Interface Unit  
Interface for X-Y plotter or printer; System Memory  
Cassette ordered separately.  
3G2A5-PRT01-E  
Memory Rack  
K-type PCs w/comment printing function  
K-type PCs  
C500-MP102-EV3  
C20-MP009-EV3  
SCY-CN201  
Printer Connecting Cable 2 m (also used for X-Y plotter)  
---  
---  
Floppy Disk Interface  
Unit  
C20K/C28K/C40K/C60K. GPC required; with comment 3G2C5-FDI03-E  
file; able to connect to NEC floppy disk controller  
Peripheral Interface Unit To connect GPC or FIT to K-type PCs  
3G2C7-IP002-V2  
Connecting Cable  
Used to connect FIT or GPC to  
Peripheral Interface Unit and to  
connect Programming Console  
Adapter and Programming Console  
2 m  
5 m  
10 m  
20 m  
3G2A2-CN221  
3G2A5-CN523  
3G2A5-CN131  
3G2A5-CN231  
---  
Base.  
30 m  
40 m  
50 m  
3G2A5-CN331  
3G2A5-CN431  
3G2A5-CN531  
• U: UL, C: CSA, N: NK  
See Omron sales representatives concerning operating conditions under which UL, CSA, and NK standards were met (Aug. 1988).  
170  
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Appendix B  
Programming Instructions and Execution Times  
Function code  
Name  
Mnemonic  
Page  
-
LOAD  
LD  
73  
-
LOAD NOT  
AND  
LD NOT  
AND  
73  
-
73  
-
AND NOT  
OR  
AND NOT  
OR  
73  
-
73  
-
OR NOT  
AND LOAD  
OR LOAD  
OUTPUT  
OUTPUT NOT  
TIMER  
OR NOT  
AND LD  
OR LD  
OUT  
73  
-
74  
-
74  
-
75  
-
OUT NOT  
TIM  
75  
-
83  
-
COUNTER  
CNT  
90  
00  
01  
02  
03  
04  
05  
08  
09  
10  
11  
12  
13  
14  
15  
16  
20  
21  
22  
23  
24  
30  
31  
32  
33  
40  
41  
60  
NO OPERATION  
END  
NOP  
END  
81  
81  
INTERLOCK  
IL  
78  
INTERLOCK CLEAR  
JUMP  
ILC  
78  
JMP  
80  
JUMP END  
JME  
80  
STEP DEFINE  
STEP START  
STEP  
SNXT  
SFT  
128  
128  
106  
77  
SHIFT REGISTER  
KEEP  
KEEP  
CNTR  
DIFU  
DIFD  
TIMH  
WSFT  
CMP  
MOV  
MVN  
BIN  
REVERSIBLE COUNTER  
DIFFERENTIATE UP  
DIFFERENTIATE DOWN  
HIGH-SPEED TIMER  
WORD SHIFT  
COMPARE  
93  
75  
75  
86  
110  
112  
111  
112  
115  
115  
120  
122  
123  
124  
125  
125  
103  
MOVE  
MOVE NOT  
BCD-TO-BINARY  
BINARY-TO-BCD  
BCD ADD  
BCD  
ADD  
BCD SUBTRACT  
BCD MULTIPLY  
BCD DIVIDE  
SUB  
MUL  
DIV  
SET CARRY  
STC  
CLEAR CARRY  
REVERSIBLE DRUM COUNTER  
CLC  
RDM  
171  
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Programming Instructions and Execution Times  
Appendix B  
Function code  
Name  
HIGH-SPEED DRUM COUNTER  
END WAIT  
Mnemonic  
Page  
61  
62  
63  
76  
77  
84  
91  
92  
93  
97  
HDM  
ENDW  
NETW  
MLPX  
DMPX  
SFTR  
SBS  
94  
135  
136  
116  
118  
109  
126  
126  
126  
135  
NOTATION INSERT  
4-TO-16 DECODER  
16-TO-4 ENCODER  
REVERSIBLE SHIFT REGISTER  
SUBROUTINE ENTER  
SUBROUTINE DEFINE  
RETURN  
SBN  
RET  
I/O REFRESH  
IORF  
Instruction Execution Times  
This following table lists the execution times for all instructions that are available for the K-types. The maxi-  
mum and minimum execution times and the conditions which cause them are given where relevant.  
Execution times for most instructions depend on whether they are executed with an ON or an OFF execution  
condition. The OFF execution time for an instruction can also vary depending on the circumstances, i.e.,  
whether it is in an interlocked program section and the execution condition for IL is OFF, whether it is between  
JMP(04) 00 and JME(05) 00 and the execution condition for JMP(04) 00 is OFF, or whether it is reset by an  
OFF execution condition. “R,” “IL,” and “JMP” are used to indicate these three times.  
Execution times are expressed in microseconds except where noted.  
Function Instruction  
code  
Execution  
time(µs)  
Conditions  
---  
LD  
12  
Always  
LD NOT  
AND  
12  
Always  
11.5  
11.5  
11.5  
11.5  
4
Always  
AND NOT  
OR  
Always  
Always  
OR NOT  
AND LD  
OR LD  
OUT  
Always  
Always  
4
Always  
17  
When outputting logical “1” (ON)  
17.5  
19  
When outputting logical “0” (OFF)  
When outputting logical “1” (ON)  
When outputting logical “0” (OFF)  
OUT NOT  
17.5  
172  
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Programming Instructions and Execution Times  
Appendix B  
Function Instruction  
code  
Execution  
time(µs)  
Conditions  
---  
TIM  
95  
When timing  
95.5 to 186.5 When reset  
CNT  
80.5  
91.5 TO 184  
2
When counting  
When reset  
Always  
00  
01  
02  
03  
04  
05  
08  
09  
10  
NOP  
END  
IL  
—
Refer to Cycle Time Calculation Example.  
Always  
2.5  
ILC  
3
Always  
JMP  
JME  
STEP  
SNXT  
SFT  
94  
Always  
38  
Always  
60 to 127  
100  
Always  
Always  
102  
When shifting 1 word  
248  
When shifting 13 words  
90 to 254  
19  
When reset (1 to 13 words)  
When set  
11  
12  
13  
14  
15  
16  
20  
21  
22  
23  
24  
30  
31  
32  
KEEP  
CNTR  
DIFU  
DIFD  
TIMH  
WSFT  
CMP  
MOV  
MVN  
BIN  
20  
When reset  
95  
When counting DOWN  
190.5  
60.5  
56.5  
59  
When counting UP (word specified)  
When input = 1  
When input = 0  
When input = 1  
62.5  
94.5  
97 to 187.5  
97  
When input = 0  
When timing  
When reset  
When shifting DM by 1 word  
When shifting DM by 64 words  
When comparing a constant with word data  
When comparing a TIM/CNT with word data  
When transferring a constant to a word  
When transferring a TIM/CNT to a word  
When inverting & transferring a constant to a word  
When inverting & transferring a TIM/CNT to a word  
When converting & transferring a TIM/CNT to a word  
When converting & transferring a word to a word  
When converting & transferring DM to DM  
When converting & transferring data in other areas  
When adding two words  
825.5  
121.5  
212  
109  
196  
108.5  
196  
115  
193.5  
194  
BCD  
ADD  
SUB  
202.5  
233  
352  
When adding a TIM/CNT to a constant  
When subtracting a word from a word  
When subtracting a constant from a TIM/CNT  
When multiplying a DM word by a DM word  
237.5  
356.5  
655  
MUL  
173  
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Programming Instructions and Execution Times  
Appendix B  
Function Instruction  
code  
Execution  
time(µs)  
Conditions  
33  
40  
41  
60  
61  
62  
63  
76  
DIV  
572  
When dividing a DM word by a DM word  
STC  
16  
Always  
CLC  
16  
Always  
RDM  
HDM  
ENDW  
NETW  
MLPX  
695  
734  
197  
58  
At reset  
Always  
With DM word  
Always  
212.5  
288  
355  
431  
298.5  
658.5  
456  
1,080  
145  
743  
136 to 668  
44  
Word, 1 digit (constant) —> word  
Word, 4 digits (constant) —> word  
TIM/CNT, 1 digit (TIM/CNT) —> word  
TIM/CNT, 4 digits (TIM/CNT) —> word  
Word, 1 digit (constant) —> word  
Word, 4 digits (constant) —> word  
TIM/CNT, 1 digit (TIM/CNT) —> word  
TIM/CNT, 4 digits (TIM/CNT) —> word  
When shifting one word  
When shifting 64 DM words  
When resetting 1 to 64 DM words  
NOP  
77  
DMPX  
84  
SFTR  
42  
IL  
91  
92  
93  
97  
SBS  
SBN  
RET  
IORF  
75  
Always  
26  
Always  
49  
Always  
108  
When refreshing 1 word  
174  
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Programming Instructions and Execution Times  
Appendix B  
Ladder Diagram Instructions  
Name  
Symbol  
Function  
Operands  
Mnemonic  
LOAD  
LD  
Used to start instruction block with status B:  
of designated bit.  
IR  
SR  
HR  
TC  
TR  
LD  
B
LOAD NOT  
LD NOT  
Used to start instruction block with in-  
verse of designated bit.  
B:  
IR  
SR  
HR  
TC  
TR  
LD NOT  
B
AND  
AND  
Logically ANDs status of designated bit  
with execution condition.  
B:  
IR  
SR  
HR  
TC  
TR  
AND  
B
AND NOT  
AND NOT  
Logically ANDs inverse of designated bit B:  
with execution condition.  
IR  
SR  
HR  
TC  
TR  
AND NOT  
B
OR  
OR  
Logically ORs status of designated bit  
with execution condition.  
B:  
IR  
SR  
HR  
TC  
TR  
OR  
B
OR NOT  
OR NOT  
Logically ORs inverse of designated bit  
with execution condition.  
B:  
IR  
SR  
HR  
TC  
TR  
OR NOT  
B
AND LOAD  
AND LD  
Logically ANDs results of preceding  
blocks.  
None  
None  
AND LD  
-
OR LOAD  
OR LD  
Logically ORs results of preceding  
blocks.  
OR LD  
-
Refer to table at beginning of Appendix B for page references.  
175  
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Programming Instructions and Execution Times  
Appendix B  
Name  
Mnemonic  
Function  
Symbol  
Operands  
OUTPUT  
OUT  
Turns ON designated bit.  
B:  
IR  
HR  
TR  
B
OUT  
B
OUTPUT NOT  
OUT NOT  
Turns OFF designated bit.  
B:  
IR  
HR  
TR  
B
OUT NOT  
B
TIMER  
TIM  
ON-delay (decrementing) timer opera-  
tion. Set value: 999.9 s; accuracy:  
+0.0/-0.1 s. Same TC bit cannot be as-  
signed to more than one timer/counter.  
The TC bit is input as a constant.  
N:  
TC  
SV:  
IR  
HR  
#
TIM N  
SV  
TIM  
N
SV  
COUNTER  
CNT  
A decrementing counter. SV: 0 to 9999;  
CP: count pulse; R: reset input. The TC  
bit is input as a constant.  
N:  
TC  
SV:  
IR  
HR  
#
CNT  
N
SV  
CNT  
N
SV  
Refer to table at beginning of Appendix B for page references.  
176  
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Programming Instructions and Execution Times  
Appendix B  
Special Instructions  
Name  
Symbol  
Function  
Operands  
Mnemonic  
NO OPERATION  
NOP (00)  
Nothing is executed and next instruc-  
tion is moved to.  
None  
None  
None  
None  
END  
END(01)  
Required at the end of the program.  
END(01)  
INTERLOCK  
IL(02)  
INTERLOCK  
If interlock condition is OFF, all outputs  
are turned OFF and all timer PVs reset  
between this IL(02) and the next  
IL(02)  
CLEAR  
ILC(03)  
ILC(03). Other instructions are treated  
as NOP; counter PV are maintained.  
ILC(03)  
JUMP  
Cause all instructions between  
None  
JMP(04)  
JUMP END  
JME(05)  
JMP(04) and the corresponding  
JME(05) to be ignored. Corresponding  
JME is next one in program; only 8  
JMP-JME pairs allowed per program.  
JMP(04)  
JME(05)  
STEP DEFINE  
STEP(08)  
Is used in the definition of program  
sections. STEP N marks the beginning  
of the section identified by N. STEP  
without an operand indicates the end  
of a series of program sections.  
N:  
HR  
STEP(08) N  
STEP(08)  
STEP START  
SNXT(09)  
SNXT resets the timers and clears the  
data areas used in the previous pro-  
gram section. SNTX must also be  
present at the end of a series of pro-  
gram sections.  
N:  
HR  
SNXT(09) N  
SHIFT REGISTER  
SFT(10)  
Creates a bit shift register from the  
starting word (St) through the ending  
word (E). I: input bit; P: shift pulse; R:  
reset input. St must be less than or  
equal to E and Bg and E must be in the  
same data area.  
St/E:  
IR  
HR  
I
SFT(10)  
P
R
St  
E
15  
00  
15  
00  
IN  
St  
E
KEEP  
KEEP(11)  
Defines a bit (B) as a latch controlled  
by set (S) and reset (R) inputs.  
B:  
S
R
IR  
HR  
KEEP(11)  
B
REVERSIBLE  
COUNTER  
CNTR (12)  
Increases or decreases PV by one  
whenever the increment input (II) or  
decrement input (DI) signal goes from  
OFF to ON. SV: 0 to 9999; R: reset in-  
put. Must not access the same TC bit  
as another timer/counter. The TC bit is  
input as a constant.  
N:  
TC  
SV:  
IR  
HR  
#
II  
CNTR  
N
SV  
DI  
R
Refer to table at beginning of Appendix B for page references.  
177  
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Programming Instructions and Execution Times  
Appendix B  
Name  
Mnemonic  
Symbol  
Function  
Operands  
DIFFERENTIATE  
UP  
DIFU(13)  
DIFFERENTIATE  
DOWN  
DIFD(14)  
DIFU turns ON the designated bit (B)  
for one cycle on the rising edge of the  
input signal; DIFD turns ON the bit for  
one cycle on the trailing edge. The  
maximum number of DIFU/DIFDs is  
48.  
B:  
IR  
DIFU(13)  
DIFD(14)  
B
B
HR  
HIGH-SPEED  
TIMER  
TIMH(15)  
A high-speed ON-delay (decrementing)  
timer. SV: 0.02 to 99.99 s. Must not be  
assigned the same TC bit as another  
timer/counter. The TC bit is input as a  
constant.  
N:  
TC  
SV:  
IR  
HR  
#
TIMH(15) N  
SV  
WORD SHIFT  
WSFT(16)  
Shifts data between the start and end  
words in word units.  
St/E:  
IR  
HR  
DM  
WSFT(16)  
St  
E
COMPARE  
CMP(20)  
Compares two sets of four-digit hexa-  
decimal data (Cp1 and Cp2) and out-  
puts result to GR, EQ, and LE.  
Cp1/Cp2:  
IR  
CMP(20)  
Cp1  
Cp2  
SR  
HR  
TC  
DM  
#
MOVE  
MOV(21)  
Transfers source data (S) (word or  
four-digit constant) to destination word  
(D).  
S:  
D:  
IR  
IR  
MOV(21)  
SR  
HR  
TC  
DM  
#
HR  
DM  
S
D
MOVE NOT  
MVN(22)  
Inverts source data (S) (word or  
four-digit constant) and then transfers it  
to destination word(D).  
S:  
D:  
IR  
IR  
MVN(22)  
SR  
HR  
TC  
DM  
#
HR  
DM  
S
D
BCD-TO-BINARY  
BIN(23)  
Converts four-digit, BCD data in source  
word (S) into 16-bit binary data, and  
outputs converted data to result word  
(R).  
S:  
R:  
IR  
IR  
BIN(23)  
SR  
HR  
TC  
DM  
HR  
DM  
S
R
S
R
(BCD)  
(BIN)  
0
1
2
3
0
1
2
3
x16  
x16  
x16  
x16  
x10  
x10  
x10  
x10  
Refer to table at beginning of Appendix B for page references.  
178  
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Programming Instructions and Execution Times  
Appendix B  
Name  
Mnemonic  
Symbol  
Function  
Operands  
BINARY-TO-BCD  
BCD(24)  
Converts binary data in source word (S)  
into BCD, and outputs converted data to  
result word (R).  
S:  
R:  
IR  
IR  
BCD(24)  
SR  
HR  
DM  
HR  
DM  
S
R
S
R
(BIN)  
(BCD)  
0
0
1
x16  
x16  
x16  
x16  
x10  
x10  
1
2
3
2
x10  
x10  
3
BCD ADD  
ADD(30)  
Adds two four-digit BCD values (Au  
and Ad) and content of CY, and out-  
puts result to specified result word (R).  
Au/Ad R:  
IR  
IR  
ADD(30)  
SR  
HR  
TC  
DM  
#
HR  
DM  
Au  
Ad  
R
Au + Ad + CY  
CY  
R
BCD SUBTRACT  
SUB(31)  
Subtracts both four-digit BCD subtra-  
hend (Su) and content of CY from  
four-digit BCD minuend (Mi) and out-  
puts result to specified result word (R).  
Mi/Su: R:  
IR  
IR  
SUB(31)  
SR  
HR  
TC  
DM  
#
HR  
DM  
Mi  
Su  
R
Mi - Su  
CY  
CY  
R
BCD MULTIPLY  
MUL(32)  
Multiplies a words data or a four-digit  
BCD value(Md) and another words  
data (Mr) and outputs the result to a  
specified result word (R).  
Md/Mr R:  
IR  
IR  
MUL(32)  
SR  
HR  
TC  
DM  
#
HR  
DM  
Md  
Mr  
R
Md X Mr  
R
R + 1  
BCD DIVIDE  
DIV(33)  
Divides a words data or a four-digit  
BCD dividend (Dd) and another words  
data (Dr) and outputs result to speci-  
fied result word (R).  
Dd/Dr: R:  
IR  
IR  
DIV(33)  
SR  
HR  
TC  
DM  
#
HR  
DM  
Dd  
Dr  
R
R
R + 1  
SET CARRY  
STC(40)  
Sets carry flag (i.e., turns CY ON).  
None  
None  
D:  
STC(40)  
CLC(41)  
CLEAR CARRY  
CLC(41)  
CLC clears carry flag (i.e, turns CY  
OFF).  
REVERSIBLE  
DRUM COUNTER  
RDM(60)  
High-speed UP-DOWN counter opera-  
tion.  
RDM(60)  
D
IR  
HR  
DM  
HIGH-SPEED  
DRUM COUNTER  
HDM(61)  
A 2-kHz counter with both software  
and hardware resets.  
D:  
IR  
HR  
DM  
HDM(61)  
D
Refer to table at beginning of Appendix B for page references.  
179  
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Programming Instructions and Execution Times  
Appendix B  
Name  
Mnemonic  
Symbol  
Function  
Operands  
END WAIT  
ENDW(62)  
Used to force a cycle time longer than  
normal causing the CPU to wait.  
N:  
IR  
HR  
TC  
DM  
#
ENDW(62)  
N
NOTATION  
INSERT  
NETW(63)  
Used to leave comments in the pro-  
gram.  
#
NETW(63)  
C1  
C2  
4-TO-16  
DECODER  
MLPX(76)  
Converts up to four hexadecimal digits  
in source word (S) into decimal values  
from 0 to 15 and turns ON, in result  
word(s) (R), bit(s) corresponding to  
converted value. Digits designated in  
Di digits (rightmost digit: first digit to be  
converted; next digit to left: number of  
digits to be converted minus 1).  
S:  
Di:  
IR  
HR  
TC  
DM  
#
R:  
IR  
IR  
MLPX(76)  
SR  
HR  
TC  
DM  
HR  
DM  
S
Di  
R
3
S
3
2
1
0
0 to F  
Di  
16-TO-4  
ENCODER  
DMPX(77)  
Determines position of highest ON bit in  
source word(s) (starting word: S) and  
turns ON corresponding bit(s) in result  
word (R). Digit designations made with Di  
digits (rightmost digit: first digit to receive  
converted value; next digit to left: number  
of words to be converted minus 1).  
S:  
R:  
Di:  
IR  
HR  
TC  
DM  
#
IR  
IR  
SR  
HR  
TC  
DM  
HR  
DM  
DMPX(77)  
S
R
Di  
15  
0
S
R
0
3
.
3
2
1
0
0 to F  
REVERSIBLE  
SHIFT REGISTER  
SFT(84)  
Shifts data in a specified word or series  
of words one bit to either the left or the  
right.  
St/E: C:  
SFTR(84)  
IR  
IR  
C
St  
E
HR  
DM  
HR  
DM  
SUBROUTINE  
ENTER  
SBS(91)  
Transfers control of a program over to  
a subroutine N.  
N:  
00 to 15  
SBS(91) N  
SBN(92) N  
SUBROUTINE  
DEFINE  
SBN(92)  
Indicates the beginning of a subroutine  
definition.  
N:  
00 to 15  
Refer to table at beginning of Appendix B for page references.  
180  
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Programming Instructions and Execution Times  
Appendix B  
Name  
Mnemonic  
Symbol  
Function  
Operands  
RETURN  
RET(93)  
Indicates the end of a subroutine defi-  
nition.  
None  
RET(93)  
I/O REFRESH  
IORF(97)  
Refreshes I/O words between a speci-  
fied range. Refreshes words in word  
units.  
St/E:  
00 to 09  
IORF(97)  
St  
E
Refer to table at beginning of Appendix B for page references.  
181  
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Appendix C  
Programming Console Operations  
Function  
Name  
Page  
Data Clear  
Used to erase data, either selectively or totally, from the Program Memory and 47  
the IR, AR, HR, DM, and TC areas.  
Address Designation  
Program Search  
Displays the specified address.  
50  
55  
57  
Searches a program for the specified data address or instruction.  
Instruction Insert  
Instruction Delete  
Allows a new instruction to be inserted before the displayed instruction, or  
deletes the displayed instruction (respectively).  
Program Check  
Checks the completed program for syntax errors (up to three levels in H-type  
PCs).  
53  
Error Message Read  
Bit/Word Monitor  
Displays error messages in sequence, starting with the most severe messages. 148  
Displays the specified address whose operand is to be monitored. In RUN or  
MONTR mode it will show the status of the operand for any bit or word in any  
data area.  
150  
Forced Set/Reset  
Set: Used to turn ON bits or timers, or to increment counters currently  
displayed on the left of the screen.  
153  
Reset: Used to turn OFF bits, or to reset timers or counters.  
Hex/BCD Data Change  
Used to change the value of the leftmost BCD or hexadecimal word displayed  
during a Bit/Word Monitor operation.  
155  
156  
SV Change  
SV Reset  
Alters the SV of a timer or counter either by incrementing or decrementing the  
value, or by overwriting the original value with a new one.  
Program Memory Save  
Program Memory Restore  
Program Memory Compare  
Saves Program Memory to tape.  
Reads Program Memory from tape.  
158  
159  
159  
Compares Program Memory data on tape with that in the Program Memory  
area.  
System Operations  
Operation/Description  
Modes*  
Key sequence  
Data Clear  
P
All Clear  
REC  
PLAY  
SET  
NOT  
MONTR  
Unless otherwise specified, this  
operation will clear all erasable  
memory in Program Memory and  
IR, HR, AR, DM, and TC areas. To  
clear EPROM memory the write  
enable switch must be ON (i.e.,  
enabled). The branch lines shown  
are used only when performing a  
partial memory clear, with each of  
the memory areas entered being  
retained. Specifying an address will  
result in the Program Memory after  
and including that address being  
deleted. All memory up to that  
address will be retained.  
CLR  
RESET  
Partial  
Clear  
[Address]  
HR  
Retained if  
pressed  
CNT  
DM  
*Modes in which the given instruction is applicable: R = RUN, M = MONITOR, P = PROGRAM  
183  
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Programming Console Operations  
Appendix C  
Programming Operations  
Operation/Description  
Address Designation  
Modes*  
Key sequence  
R P M  
Displays the specified address. Can  
be used to start programming from  
a non-zero address or to access an  
address for editing. Leading zeros  
need not be entered. The contents  
of the address will not be displayed  
until the down key is pressed. The  
up and down keys can then be used  
to scroll through the Program  
Memory.  
CLR  
[Address]  
Program Search  
R P M  
SRCH  
[Instruction]  
SRCH  
Allows the program to be searched  
for occurrences of any designated  
instruction or data area address. To  
designate a bit address, press  
SHIFT, CONT/#, and then input the  
address. Then press SRCH.  
Pressing SRCH again will find the  
next occurrence. In RUN or  
MONITOR mode, the ON/OFF  
status of each monitored bit will also  
be displayed. Applicable data areas  
vary according to the PC being  
used.  
CLR  
CLR  
CONT  
SHIFT  
#
[Address]  
HR  
SRCH  
SRCH  
TIM  
CNT  
Instruction Insert and  
Instruction Delete  
P
At the desired position  
in program:  
[Enter new  
instruction]  
INS  
Insert  
The displayed instruction can be  
deleted, or another instruction can  
be inserted before it. Care should  
be taken to avoid inadvertent  
deletions as there is no way of  
recovering the instructions other  
than to re-enter them. When an  
instruction is deleted all subsequent  
instruction addresses are  
Instruction  
currently  
displayed  
DEL  
Delete  
automatically adjusted so that there  
are no empty addresses, or  
instructions without addresses.  
Program Check  
P
SRCH  
Press SRCH to find  
next error.  
SRCH  
CLR  
Once a program has been entered,  
it should be checked for errors. The  
address where the error was  
generated will be displayed.  
Cancel  
CLR  
*Modes in which the given instruction is applicable: R = RUN, M = MONITOR, P = PROGRAM  
Debugging Operations  
Operation/Description  
Error Message Read  
Displays error messages in  
Modes*  
Key sequence  
R P M  
FUN  
MONTR  
MONTR  
CLR  
sequence with most severe  
messages displayed first. Press  
monitor to access remaining  
messages. In PROGRAM mode,  
pressing MONTR clears the  
displayed message from memory  
and the next message is displayed.  
*Modes in which the given instruction is applicable: R = RUN, M = MONITOR, P = PROGRAM  
184  
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Programming Console Operations  
Appendix C  
Monitoring and Data Changing Operations  
Operation/Description  
Modes*  
Key sequence  
Bit/Word Monitor  
R P M  
Up to six memory addresses,  
containing either words or bits, or a  
combination of the two, can be  
monitored at once. Only three can  
be displayed at any one time. If  
operated in RUN or MONITOR  
mode, the status of monitored bits  
will also be displayed.  
CONT  
#
[Address]  
SHIFT  
CLR  
HR  
MONTR  
LD  
The operation can be started from a  
cleared display by entering the  
address of the first word or bit to be  
monitored and pressing MONTR, or  
from any address in the program by  
displaying the address of the bit or  
word to be monitored and pressing  
MONTR.  
OUT  
Clears the left-  
most address  
from the screen.  
MONTR  
CLR  
TIM  
CNT  
DM  
When a timer or counter is  
monitored, its PV will be displayed  
and a box is displayed in the bottom  
left hand corner if the Completion  
Flag is ON.  
Cancel  
Applicable data areas vary  
according to the PC being used.  
Forced Set/Reset  
P M  
Bit/Word monitor in progress. Bit or  
Timer/Counter currently monitored  
appears on left of the screen.  
PLAY  
SET  
If a bit, timer, or counter address is  
leftmost on the screen during a  
Bit/Word Monitor operation,  
pressing PLAY/SET will turn ON the  
bit, start the timer, or increment the  
counter. Pressing REC/RESET will  
turn OFF the bit, or reset the timer  
or counter. These force-sets and  
force-resets are effective for one  
cycle.  
REC  
RESET  
Timers will not operate in  
PROGRAM mode. SR bits are not  
affected by this operation.  
Hex/BCD Data Change  
P M  
Bit/Word monitor in progress.  
Currently monitored word ap-  
pears on the left of the screen.  
CHG  
[New data]  
WRITE  
Used to edit the leftmost BCD or  
hexadecimal value displayed during  
a Bit/Word Monitor operation. If a  
timer or counter is leftmost on the  
display, the PV will be the value  
displayed and affected by this  
operation. It can only be changed in  
MONITOR mode and only while the  
timer or counter is operating. SR  
words cannot be changed using this  
operation.  
185  
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Programming Console Operations  
Appendix C  
Operation/Description  
SV Change,  
SV Reset  
Modes*  
Key sequence  
P M  
M
Timer/Counter  
currently displayed  
[New SV]  
WRITE  
CHG  
There are three ways of modifying  
the SVs for timers and counters.  
One method is to enter a new value.  
CH  
[Word]  
SHIFT  
WRITE  
*
The second is to increment or  
decrement the existing SV. In  
MONITOR mode the SV can be  
changed while the program is being  
executed. Incrementing and  
decrementing can only be carried  
out if the SV has been entered as a  
constant.  
The third method is to change the  
value properties from that of a  
constant to a word address, or vice  
versa. Note that the display clears  
after pressing the CHG key and the  
subsequent keystrokes determine  
whether the new data will be  
entered as a word address  
(pressing SHIFT CH/* plus Word  
address) or a constant (entering  
data only).  
*Modes in which the given instruction is applicable: R = RUN, M = MONITOR, P = PROGRAM  
186  
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Programming Console Operations  
Appendix C  
Cassette Tape Operations  
Operation/Description  
Modes*  
Key sequence  
5 second leader tape**  
Program Memory Save  
P
Copies data from the Program  
Memory to tape. The file no.  
specified in the instructions provides  
an identifying address for the  
information within the tape. Each file  
number should be used only once  
per tape. If only a part of the  
REC  
Start tape recorder in  
the appropriate mode.  
SHIFT  
EXT  
[File no.]  
CLR  
RESET  
Program Memory is to be stored,  
the appropriate start and stop  
addresses must be entered. Each  
C60 tape can store approximately  
16K words on each side of the tape.  
When the start address is entered,  
the maximum stop address is set as  
the default. Do not set a stop  
address greater than this one. If you  
wish to record past this address the  
additional information will need to be  
recorded either on the flip side of  
the tape or on a separate tape. After  
starting the tape recorder, wait  
about 5 seconds before pressing  
SHIFT REC/RESET. This is to allow  
the leader tape to pass before the  
data transmission starts.  
5 second leader tape**  
Program Memory Restore  
P
To read Program Memory data  
which has been recorded on a  
cassette tape, the keystrokes are as  
given here. The file number must be  
the same as the one entered when  
the data was recorded. The read  
operation will proceed from the  
specified start address up to the end  
of the tape, unless halted by a CLR  
command. The instruction must be  
completed before the required data  
is reached on the tape, i.e., usually  
before the leader tape finishes.  
PLAY  
SET  
Start tape recorder  
playback.  
SHIFT  
EXT  
[File no.]  
CLR  
5 second leader tape**  
Program Memory Compare  
The procedure to compare Program  
Memory data stored on a tape with  
that in the PC’s Program Memory  
area is the same as that for reading  
it (see above), except that after  
starting the tape playback, VER  
should be pressed instead of SHIFT  
and PLAY/SET.  
P
Start tape recorder  
playback.  
VER  
EXT  
[File no.]  
CLR  
*Modes in which the given instruction is applicable: R = RUN, M = MONITOR, P = PROGRAM  
**These times take the cassette leader tape into consideration according to the following:  
a) When recording to tape, the leader tape needs to be allowed to pass before the data transmission to the tape player starts.  
b) When restoring from tape or comparing data, the Programming Console needs to be ready to receive data before the data is transfered  
from the tape.  
187  
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Appendix D  
Error and Arithmetic Flag Operation  
The following table shows which instructions affect the ER, CY, GT, LT and EQ flags. In general, ER indicates  
that operand data is not within requirements. CY indicates arithmetic or data shift results. GT indicates that a  
compared value is larger than some standard, LT that it is smaller; and EQ, that it is the same. EQ also indi-  
cates a result of zero for arithmetic operations. Refer to subsections of Section 5 Instruction Set for details.  
Vertical arrows in the table indicate the flags that are turned ON and OFF according to the result of the in-  
struction.  
Although TIM, CNT, and CNTR are executed when ER is ON, other instructions with a vertical arrow under  
the Er column are not executed if ER is ON. All of the other flags in the following table will also not operate  
when ER is ON.  
Instructions not shown do not affect any of the flags in the table.  
Instructions  
END(01)  
SR 1907 (LE)  
OFF  
SR 1906 (EQ)  
OFF  
SR 1905 (GR)  
OFF  
SR 1904 (CY)  
OFF  
SR 1903 (ER)  
OFF  
TIM  
TIMH(15)  
CNT  
CNTR(12)  
WSFT(16)  
CMP(20)  
MOV(21)  
MVN(22)  
BIN(23)  
BCD(24)  
ADD(30)  
SUB(31)  
MUL(32)  
DIV(33)  
STC(40)  
CLC(41)  
MLPX(76)  
DMPX(77)  
SFTR(84)  
SBS(91)  
ON  
ON  
OFF  
OFF  
Note:  
means that the flag is affected by the result of instruction execution.  
189  
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Appendix E  
Binary–Hexadecimal–Decimal Table  
Decimal  
BCD  
00000000  
Hex  
Binary  
00000000  
00  
01  
02  
03  
04  
05  
06  
07  
08  
09  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
00  
01  
02  
03  
04  
05  
06  
07  
08  
09  
0A  
0B  
0C  
0D  
0E  
0F  
10  
11  
00000001  
00000010  
00000011  
00000100  
00000101  
00000110  
00000111  
00001000  
00001001  
00010000  
00010001  
00010010  
00010011  
00010100  
00010101  
00010110  
00010111  
00011000  
00011001  
00100000  
00100001  
00100010  
00100011  
00100100  
00100101  
00100110  
00100111  
00101000  
00101001  
00110000  
00110001  
00110010  
00000001  
00000010  
00000011  
00000100  
00000101  
00000110  
00000111  
00001000  
00001001  
00001010  
00001011  
00001100  
00001101  
00001110  
00001111  
00010000  
00010001  
00010010  
00010011  
00010100  
00010101  
00010110  
00010111  
00011000  
00011001  
00011010  
00011011  
00011100  
00011101  
00011110  
00011111  
00100000  
12  
13  
14  
15  
16  
17  
18  
19  
1A  
1B  
1C  
1D  
1E  
1F  
20  
191  
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Appendix F  
Word Assignment Recording Sheets  
This appendix contains sheets that can be copied by the programmer to record I/O bit allocations and terminal  
assignments on the Racks, as well as details of work bits, data storage areas, timers, and counters.  
193  
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I/O Bits  
Word Assignment Recording Sheets  
Appendix F  
Page:  
Programmer:  
Program:  
Date:  
Word:  
Bit  
Unit:  
Word:  
Unit:  
Field device  
Notes  
Bit  
00  
01  
02  
03  
04  
05  
06  
07  
08  
09  
10  
11  
12  
13  
14  
15  
Field device  
Notes  
00  
01  
02  
03  
04  
05  
06  
07  
08  
09  
10  
11  
12  
13  
14  
15  
Word:  
Bit  
Unit:  
Word:  
Bit  
Unit:  
Field device  
Notes  
Field device  
Notes  
00  
01  
02  
03  
04  
05  
06  
07  
08  
09  
10  
11  
12  
13  
14  
15  
00  
01  
02  
03  
04  
05  
06  
07  
08  
09  
10  
11  
12  
13  
14  
15  
194  
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Work Bits  
Word Assignment Recording Sheets  
Appendix F  
Page:  
Programmer:  
Program:  
Date:  
Area:  
Bit  
Word:  
Area:  
Word:  
Usage  
Notes  
Bit  
00  
01  
02  
03  
04  
05  
06  
07  
08  
09  
10  
11  
12  
13  
14  
15  
Usage  
Notes  
00  
01  
02  
03  
04  
05  
06  
07  
08  
09  
10  
11  
12  
13  
14  
15  
Area:  
Bit  
Word:  
Area:  
Bit  
Word:  
Usage  
Notes  
Usage  
Notes  
00  
01  
02  
03  
04  
05  
06  
07  
08  
09  
10  
11  
12  
13  
14  
15  
00  
01  
02  
03  
04  
05  
06  
07  
08  
09  
10  
11  
12  
13  
14  
15  
195  
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Data Storage  
Word Assignment Recording Sheets  
Appendix F  
Programmer:  
Program:  
Date:  
Page:  
Word  
Contents  
Notes  
Word  
Contents  
Notes  
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Timers and Counters  
Word Assignment Recording Sheets  
Appendix F  
Programmer:  
Program:  
Date:  
Page:  
T or C  
T or C  
TC address  
Set value  
Notes  
TC address  
Set value  
Notes  
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Appendix G  
Program Coding Sheet  
The following page can be copied for use in coding ladder diagram programs. It is designed for flexibility, al-  
lowing the user to input all required addresses and instructions.  
When coding programs, be sure to specify all function codes for instructions and data areas (or # for constant)  
for operands. These will be necessary when inputting programs though a Programming Console or other Pe-  
ripheral Device.  
199  
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Program Coding Sheets  
Appendix G  
Programmer:  
Program:  
Date:  
Page:  
Address Instruction  
Operand(s)  
Address Instruction  
Operand(s)  
Address Instruction  
Operand(s)  
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Glossary  
address  
The location in memory where data is stored. For data areas, an address  
consists of a two-letter data area designation and a number that designate  
the word and/or bit location. For the UM area, an address designates the in-  
struction location (UM area); for the FM area, the block location (FM area),  
etc.  
allocation  
The process by which the PC assigns certain bits or words in memory for  
various functions. This includes pairing I/O bits to I/O points on Units.  
Analog Timer Unit  
AND  
A dedicated timer that interfaces through analog signal externally and digital  
signals internally.  
A logic operation whereby the result is true if and only if both premises are  
true. In ladder-diagram programming the premises are usually ON/OFF  
states of bits or the logical combination of such states called execution condi-  
tions.  
BCD  
Short for binary-coded decimal.  
BCD calculation  
An arithmetic calculation that uses numbers expressed in binary-coded deci-  
mal.  
binary  
A number system where all numbers are expressed to the base 2. Although  
in a PC all data is ultimately stored in binary form, binary is used to refer to  
data that is numerically equivalent to the binary value. It is not used to refer  
to binary-coded decimal. Each four binary bits is equivalent to one hexadeci-  
mal digit.  
binary-coded decimal  
bit  
A system used to represent numbers so that each four binary bits is numeri-  
cally equivalent to one decimal digit.  
The smallest unit of storage in a PC. The status of a bit is either ON or OFF.  
Four bits equal one digit; sixteen bits, one word. Different bits are allocated to  
special purposes, such as holding the status input from external devices,  
while other bits are available for general use in programming.  
bit address  
The location in memory where a bit of data is stored. A bit address must  
specify (sometimes by default) the data area and word that is being ad-  
dressed as well as the number of the bit.  
bit designator  
bit number  
An operand that is used to designate the bit or bits of a word to be used by  
an instruction.  
A number that indicates the location of a bit within a word. Bit 00 is the right-  
most (least significant) bit; bit 15 is the leftmost (most significant) bit.  
buffer  
A temporary storage space for data in a computerized device.  
bus bar  
The line leading down the left and sometimes right side of a ladder diagram.  
Instruction execution follows down the bus bar, which is the starting point for  
all instruction lines.  
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Glossary  
call  
A process by which instruction execution shifts from the main program to a  
subroutine. The subroutine may be called by an instruction or by an interrupt.  
carry flag  
A flag that is used with arithmetic operations to hold a carry from an addition  
or multiplication operation or to indicate that the result is negative in a sub-  
traction operation. The carry flag is also used with certain types of shift oper-  
ation.  
clock pulse  
clock pulse bit  
condition  
A pulse available at a certain bit in memory for use in timing operations. Vari-  
ous clock pulses are available with different pulse widths.  
A bit in memory that supplies a pulse that can be used to time operations.  
Various clock pulse bit are available with different pulse widths.  
An ‘instruction’ placed along an instruction line to determine how terminal  
instruction on the right side are to be executed. Each condition is assigned to  
a bit in memory that determines its status. The status of the bit assigned to  
each condition determines, in turn, the execution condition for each instruc-  
tion up to a terminal instruction on the right side of the ladder diagram.  
constant  
An operand for which the actual numeric value is input directly and in place  
of a data memory address would hold the value to be used.  
control bit  
A bit in a memory area that is set either from the program or from a Program-  
ming Device to achieve a specific purpose, e.g., a Restart bit is turned ON  
and OFF to restart a Unit.  
Control System  
All of the hardware and software components used to control other devices.  
A Control System includes the PC System, the PC programs, and all I/O de-  
vices that are used to control or obtain feedback from the controlled system.  
controlled system  
control signal  
counter  
The devices that are being controlled by a PC System.  
A signal sent from the PC to affect the operation of the controlled system.  
Either a dedicated number of digits or words in memory used to count the  
number of times a specific process has occurred or a location in memory ac-  
cessed through a TC bit and used to count the number of times the status of  
a bit or an execution condition has changed from OFF to ON.  
CPU  
An acronym for central processing unit. In a PC System, the CPU executes  
the program, processes I/O signals, communicates with external devices,  
etc.  
CPU Unit  
cycle  
The CPU Unit contains the CPU and provides a certain number of I/O points.  
The process used to execute a ladder-diagram program. The program is ex-  
amined sequentially from start to finish and each instruction is executed in  
turn based on execution conditions.  
cycle time  
data area  
The time required for a single cycle of the ladder-diagram program.  
An area in the PC’s memory that is designed to hold a specific type of data,  
e.g., the SR area is designed to hold flags and control bits. Memory areas  
that hold programs are not considered data areas.  
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Glossary  
data area boundary  
debug  
The highest address available in a data area. When designating an operand  
that requires multiple words, it is necessary that the highest address in the  
data area is not exceeded.  
A process by which a draft program is corrected until it operates as intended.  
Debugging includes both removal of syntax errors as well as fine-tuning of  
timing and coordination of control operations.  
decimal  
A number system where all numbers are expressed to the base 10. Although  
in a PC all data is ultimately stored in binary form, four binary bits are often  
used to represent one decimal digit, a system called binary-coded decimal.  
decrement  
default  
Decreasing a numeric value by 1.  
A value assumed and automatically set by the PC when a specific value is  
not input by the user.  
definer  
A number used as an operand for an instruction but that serves to define the  
instruction itself rather that the data on which the instruction is to operate.  
Definers include jump numbers, subroutine numbers, etc.  
delay  
In tracing, a value that specifies where tracing to begin in relationship to the  
trigger. A delay can be either positive or negative, i.e., can designate an off-  
set on either side of the trigger.  
destination  
differentiation instruction  
The location where data of some sort in an instruction is to be placed as op-  
posed to the location from which data is to be taken for use in the instruction.  
The location from which data is to be taken is called the source.  
An instruction used to ensure that the operand bit is never turned ON for  
more than one cycle after the execution condition goes either from OFF to  
ON for a Differentiate Up instruction or from ON to OFF for a Differentiate  
Down instruction.  
digit  
A unit of storage in memory that consists of four bits.  
digit designator  
An operand that is used to designate the digit or digits of a word to be used  
by an instruction.  
distributed control  
An automation concept in which control of each portion of an automated sys-  
tem is located near the devices actually being controlled, i.e., control is de-  
centralized and ‘distributed’ over the system. Distributed control is a concept  
basic to PC Systems.  
DM area  
A data area used to hold word data. A word in the DM area cannot be ac-  
cessed by bit.  
download  
The process of transferring a program or data from a higher-level computer  
to a lower-level computer or PC.  
electrical noise  
error code  
Electrical ‘static’ that can disturb electronic communications. The ‘snow’ that  
can appear on a TV screen is an example of the effects of electrical noise.  
A numeric code output to indicate the existence of and something about the  
nature of an error. Some error codes are generated by the system; other are  
defined in the program by the operator.  
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Glossary  
exection condition  
The ON or OFF status under which an instruction is executed. The execution  
condition is determined by the logical combination of conditions on the same  
instruction line and up to the instruction being executed.  
execution time  
The time required for the CPU to execute either an individual instruction or  
an entire program.  
Expansion I/O Unit  
extended counter  
extented timer  
An Expansion I/O Unit is connected to increase the number of I/O points  
available.  
A counter created in a program that count higher that any of the standard  
counters provided by the individual instructions.  
A timer created in a program that times longer that any of the standard timers  
provided by the individual instructions.  
Factory Intelligent Terminal A Programming Device provided with advanced programming and debugging  
capabilities to facilitate PC operation. The Factory Intelligent Terminal also  
provides various interfaces for external devices, such as floppy disk drives.  
fatal error  
An error that will stop PC operation and require correction before operation  
can be continued.  
FIT  
Short for Factory Intelligent Terminal.  
flag  
A dedicated bit in memory that is set by the system to indicate some type of  
operating status. Some flags, such as the carry flag, can also be set by the  
operator or program.  
flicker bit  
A bit that is programmed to turn ON and OFF at a specific interval.  
force reset  
The process of artificially turning OFF a bit from a Programming Device. Bits  
are usually turned OFF as a result of program execution.  
force set  
The process of artificially turning ON a bit from a Programming Device. Bits  
are usually turned ON as a result of program execution.  
function code  
GPC  
A two-digit number used to input an instruction into the PC.  
Short for Graphic Programming Console.  
Graphic Programming  
Console  
A Programming Device provided with advanced programming and debugging  
capabilities to facilitate PC operation. A Graphic Programming Console is  
provided with a large display onto which ladder-diagram programs can be  
written directly in ladder-diagram symbols for input into the PC without con-  
version to mnemonic form.  
hardware error  
hexadecimal  
An error originating in the hardware structure of the PC, as opposed to a soft-  
ware error, which ordinates in software (i.e., programs).  
A number system where all numbers are expressed to the base 16. Although  
in a PC all data is ultimately stored in binary form, displays on and inputs  
through Programming Devices are often expressed in hexadecimal to facili-  
tate operation. Each four binary bits is numerically equivalent to one hexade-  
cimal digit.  
204  
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Glossary  
Host Link System  
One or more host computers connected to one or more PCs through Host  
Link Units so that the host computer can be used to transfer data to and re-  
ceive data from the PC(s). Host Link Systems enable centralized manage-  
ment and control of a PC System.  
Host Link Unit  
host computer  
An interface used to connect a PC to a host computer in a Host Link System.  
A computer that is used to transfer data or programs to or receive data or  
programs from a PC in a Host Link System. The host computer is used for  
data management and overall system control. Host computers are generally  
small personal or business computers.  
HR area  
A data area used to store and manipulate data and to preserve data when  
power to the PC is turned OFF.  
I/O capacity  
The number of inputs and outputs that a PC is able to handle. This number  
ranges from around one-hundred for smaller PCs to two-thousand for the  
largest ones.  
I/O devices  
I/O Link  
The devices to which terminals on I/O Units, Special I/O Units, etc., are con-  
nected. I/O devices may be either part of the Control System, if they function  
to help control other devices, or they may be part of the controlled system.  
Created in an Optical Remote I/O System to enable input/output of one or  
two IR words directly between PCs. The words are input/output between the  
PC controlling the Master and a PC connected to the Remote I/O System  
through an I/O Link Unit or an I/O Link Rack.  
I/O Link Unit  
I/O point  
A Unit used with certain PCs to create an I/O Link in an Optical Remote I/O  
System.  
The place at which an input signal enters the PC System or an output signal  
leaves the PC System. In physical terms, an I/O point corresponds to termi-  
nals or connector pins on a Unit; in terms of programming, an I/O point corre-  
sponds to an I/O bit in the IR area.  
I/O response time  
I/O Unit  
The time required for an output signal to be sent from the PC in response to  
and input signal received from an external device.  
The most basic type of Unit mounted to a backplane to create a Rack. I/O  
Units include Input Units and Output Units, each of which is available in a  
range of specifications. I/O Units do not include Special I/O Units, Link Units,  
etc.  
I/O word  
A word in the IR area that is allocated to a Unit in the PC System.  
Increasing a numeric value by 1.  
increment  
initialization error  
An error that occurs either in hardware or software before the PC System  
has actually begun operation, i.e., during initialization.  
initialize  
input  
Part of the startup process whereby some memory areas are cleared, system  
setup is checked, and default values are set.  
The signal coming from an external device into the PC. Input often is used  
abstractly or collectively to refer to incoming signals.  
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Glossary  
input bit  
A bit in the IR area that is allocated to hold the status of an input.  
An external device that sends signal(s) into the PC System.  
input device  
input point  
The point at which an input enters the PC System. An input point physically  
corresponds to terminals or connector pin(s).  
input signal  
instruction  
A change in the status of a connection entering the PC. Generally an input  
signal is said to exist when, for example, a connection point goes from low to  
high voltage or from a nonconductive to a conductive state.  
A direction given in the program that tells the PC an action to be carried out  
and the data to be used in carrying out the action. Instructions can simply  
turn a bit ON or OFF, or they can perform much more complex actions, such  
as converting and/or transferring large blocks of data.  
instruction block  
A group of instructions that is logically related in a ladder-diagram program.  
Although any logically related group of instructions could be called an instruc-  
tion block, the term is generally used to refer to blocks of instructions called  
logic blocks that require logic block instructions to relate them to other in-  
structions or logic blocks.  
instruction execution time  
instruction line  
The time required to execution an instruction. The execution time for any one  
instruction can vary with the execution condition for the instruction and the  
operands used in it.  
A group of conditions that lie together on the same horizontal line of a ladder  
diagram. Instruction lines can branch apart or join together to form instruction  
blocks.  
interface  
An interface is the conceptual boundary between systems or devices and  
usually involves changes in the way the communicated data is represented.  
Interface devices perform operations as changing the coding, format, or  
speed of the data.  
interlock  
IR area  
jump  
A programming method used to treat a number of instructions as a group so  
that the entire group can be reset together when individual execution is not  
required. An interlocked program section is executed normally for an ON ex-  
ecution condition and partially reset for an OFF execution condition.  
A data area whose principal function is to hold the status of inputs coming  
into the system and outputs that are to be set out of the system. Bits and  
words in the IR are that are used this way are called I/O bits and I/O words.  
The remaining bits in the IR area are work bits.  
A type of programming where execution moves directly from one point in a  
program to a separate point in the program without sequentially executing  
the instruction in between. Jumps are usually conditional on an execution  
condition.  
jump number  
A definer used with a jump that defines the points from which and to which a  
jump is to be made.  
ladder diagram (program)  
A form of program arising out of relay-based control systems that uses cir-  
cuit-type diagrams to represent the logic flow of programming instructions.  
The appearance of the program suggests a ladder, and thus the name.  
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Glossary  
ladder diagram symbol  
ladder instruction  
A symbol used in a ladder-diagram program.  
An instruction that represents the ‘rung’ portion of a ladder-diagram program.  
The other instructions in a ladder diagram fall along the right side of the dia-  
gram and are called terminal instructions.  
leftmost (bit/word)  
link  
The highest numbered bits of a group of bits, generally of an entire word, or  
the highest numbered words of a group of words. These bits/words are often  
called most significant bits/words.  
A hardware or software connection formed between two Units. “Link” can  
refer either to a part of the physical connection between two Units or a soft-  
ware connection created to data existing at another location (I/O Links).  
load  
The processes of copying data either from an external device or from a stor-  
age area to an active portion of the system such as a display buffer. Also, an  
output device connected to the PC is called a load.  
logic block  
logic block instruction  
A group of instructions that is logically related in a ladder-diagram program  
and that requires logic block instructions to relate it to other instructions or  
logic blocks.  
An instruction used to locally combine the execution condition resulting from  
a logic block with a current execution condition. The current execution condi-  
tion could be the result of a single condition or of another logic block. AND  
Load and OR Load are the two logic block instructions.  
LR area  
A data area that is used in a PC Link System so that data can be transferred  
between two or more PCs. If a PC Link System is not used, the LR area is  
available for use as work bits.  
Master  
Short for Remote I/O Master Unit.  
main program  
memory area  
mnemonic code  
All of a program except for the subroutines.  
Any of the areas in the PC used to hold data or programs.  
A form of a ladder-diagram program that consists of a sequential list of the  
instructions without using a ladder diagram. Mnemonic code is required to  
input a program into a PC when using a Programming Console.  
MONITOR mode  
A mode of PC operation in which normal program execution is possible but in  
which modification of data held in memory is still possible. Used for monitor-  
ing or debugging the PC.  
NC input  
An input that is normally closed, i.e., the input signal is considered to be  
present when the circuit connected to the input opens.  
nest  
Programming one jump within another jump, programming a call to a subrou-  
tine from within another subroutine, etc.  
NO input  
An input that is normally open, i.e., the input signal is considered to be pres-  
ent when the circuit connected to the input closes.  
noise interference  
Disturbances in signals caused by electrical noise.  
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Glossary  
nonfatal error  
A hardware or software error that produces a warning but does not stop the  
PC from operating.  
normally closed condition  
A condition that produces an ON execution condition when the bit assigned  
to it is OFF, and an OFF execution condition when the bit assigned to it is  
ON.  
normally open condition  
NOT  
A condition that produces an ON execution condition when the bit assigned  
to it is ON and an OFF execution condition when the bit assigned to it is OFF.  
A logic operation which inverts the status of the operand. For example, AND  
NOT indicates an AND with the opposite of the actual status of the operand  
bit.  
OFF  
The status of an input or output when a signal is said not to be present. The  
OFF state is generally low voltage or non-conductivity, but can be defined as  
the opposite of either.  
OFF delay  
The delay produced between the time turning OFF a signal is initiated (e.g.,  
by an input device or PC) and the time the signal reaches a state readable as  
an OFF signal (i.e., as no signal) by a receiving party (e.g., output device or  
PC).  
ON  
The status of an input or output when a signal is said to be present. The ON  
state is generally high voltage or conductivity, but can be defined as the op-  
posite of either.  
ON delay  
The delay produced between the time a signal is initiated (e.g., by an input  
device or PC) and the the time the signal reaches a state readable as an ON  
signal by a receiving party (e.g., output device or PC).  
one-shot bit  
operand  
A bit that is turned ON or OFF for a specified interval of time longer than one  
cycle.  
A bit(s) or word(s) designated as the data to be used for an instruction. An  
operand can be input as a constant expressing the actual numeric value to  
be used or as an address to express the location in memory of the data to be  
used.  
operand bit  
A bit designated as an operand for an instruction.  
A word designated as an operand for an instruction.  
operand word  
operating error  
An error that occurs during actual PC operation as opposed to an initializa-  
tion error, which occurs before actual operations can begin.  
Optical Slave Rack  
OR  
A Slave Rack connected through an Optical Remote I/O Slave Unit.  
A logic operation whereby the result is true if either one or both of the prem-  
ises is true. In ladder-diagram programming the premises are usually ON/  
OFF states of bits or the logical combination of such states called execution  
conditions.  
output  
The signal sent from the PC to an external device. Output often is used ab-  
stractly or collectively to refer to outgoing signals.  
208  
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Glossary  
output bit  
A bit in the IR area that is allocated to hold the status to be sent to an output  
device.  
output device  
output point  
An external device that receives a signal(s) from the PC System.  
The point at which an output leaves the PC System. An output point physical-  
ly corresponds to terminals or connector pin(s).  
output signal  
A change in the status of a connection leaving the PC. Generally an output  
signal is said to exist when, for example, a connection point goes from low to  
high voltage or from a nonconductive to a conductive state.  
overseeing  
overwrite  
Part of the processing performed by the CPU that includes general tasks re-  
quired to operate the PC.  
Changing the content of a memory location so that the previous content is  
lost.  
PC  
An acronym for Programmable Controller.  
PC System  
All of the Units connected to the CPU Unit up to, but not including the I/O de-  
vices. The limits of the PC System on the upper end is the PC and the pro-  
gram in its CPU and on the lower end, I/O Units, an I/O Link Unit, etc.  
PCB  
An acronym for printed circuit board.  
Peripheral Device  
Devices connected to a PC System to aid in system operation. Peripheral  
devices include printers, programming devices, external storage media, etc.  
present value  
The current time left on a timer or the current count of a counter. Present val-  
ue is abbreviated PV.  
printed circuit board  
program  
A board onto which electrical circuits are printed for mounting into a comput-  
er or electrical device.  
The list of instructions that tells the PC the sequence of control actions to be  
carried out.  
Programmable Controller  
A computerized device that can accept inputs from external devices and gen-  
erate outputs to external devices according to a program held in memory.  
Programmable Controllers are used to automate control of external devices.  
programmed alarm  
programmed error  
programmed message  
An alarm given as a result of execution of an instruction designed to gener-  
ate the alarm in the program as opposed to one generated by the system.  
An error arising as a result of execution of an instruction designed to gener-  
ate the error in the program as opposed to one generated by the system.  
A message generated as a result of execution of an instruction designed to  
generate the message in the program as opposed to one generated by the  
system.  
Programming Console  
The simplest form or Programming Device available for a PC. Programming  
Consoles are available both as hand-held models and as CPU-mounting  
models.  
209  
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Glossary  
Programming Device  
A peripheral device used to input a program into a PC or to alter or monitor a  
program already held in the PC. There are dedicated programming devices,  
such as Programming Consoles, and there are non-dedicated devices, such  
as a host computer.  
PROGRAM mode  
PROM Writer  
prompt  
A mode of operation that allows for inputting and debugging programs but  
that does not permit normal execution of the program.  
A Peripheral Device used to write programs and other data into a ROM for  
permanent storage and application.  
A message or symbol that appears on a display to request input from the op-  
erator.  
PV  
Short for present value.  
refresh  
The process of updating output status sent to external devices so that it  
agrees with the status of output bits held in memory and of updating input  
bits in memory so that they agree with the status of inputs from external de-  
vices.  
relay-based control  
The forerunner of PCs. In relay-based control, groups of relays are wired to  
each other to form control circuits. In a PC, these are replaced by program-  
mable circuits.  
Remote I/O Master Unit  
The Unit in a Remote I/O System through which signals are sent to all other  
Remote I/O Units. The Remote I/O Master Unit is mounted either to a  
C200H, C500, C1000H, or C2000H CPU Rack or an Expansion I/O Rack  
connected to the CPU Rack. Remote I/O Master Unit is generally abbreviated  
to simply “Master.”  
Remote I/O Slave Unit  
Remote I/O System  
A Unit mounted to a C200H, C500, C1000H, or C2000H Backplane to form a  
Slave Rack. Remote I/O Slave Unit is generally abbreviated to simply  
“Slave.”  
A C200H, C500, C1000H, or C2000H system in which remote I/O points are  
controlled through a Master mounted to a CPU Rack or an Expansion I/O  
Rack connected to the CPU Rack. K-type PCs can be connected to Remote  
I/O Systems through I/O Link Units.  
Remote I/O Unit  
reset  
Any of the Units in a Remote I/O System. Remote I/O Units include Masters,  
Slaves, Optical I/O Units, I/O Link Units, and Remote Terminals.  
The process of turning a bit or signal OFF or of changing the present value of  
a timer or counter to its set value or to zero.  
return  
The process by which instruction execution shifts from a subroutine back to  
the point from which the subroutine was called. A return is automatic upon  
completion of the subroutine and the return is always to.  
reversible counter  
A counter that can be both incremented and decrement depending on a spe-  
cified condition(s).  
reversible shift register  
A shift register that can shift data in either direction depending on a specified  
condition(s).  
210  
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Glossary  
right-hand instruction  
rightmost (bit/word)  
Another term for terminal instruction.  
The lowest numbered bits of a group of bits, generally of an entire word, or  
the lowest numbered words of a group of words. These bits/words are often  
called least significant bits/words.  
RUN mode  
scan time  
The operating mode used by the PC for normal control operations.  
See cycle time.  
self diagnosis  
A process whereby the system checks its own operation and generates a  
warning or error if an abnormality is discovered.  
self-maintaining bit  
servicing  
A bit that is programmed to maintain either an OFF or ON status until set or  
reset by a specific condition(s) different from the one that originally caused  
the bit to turn OFF or ON.  
The process whereby the PC provides data to or receives data from external  
devices or remote I/O or otherwise handles data transactions for Link Sys-  
tems.  
set  
The process of turning a bit or signal ON.  
set value  
The count from which a counter starts counting down (or, in the case of a  
reversible counter, the maximum count) or the time from which a timer starts  
timing. Set value is abbreviated SV.  
shift register  
One or more words in which data is shifted in bit, digit, or word units a speci-  
fied number of units to the right or left.  
Slave  
Short for Remote I/O Slave Unit.  
Slave Rack  
A C200H, C500, C1000H, or C2000H Rack containing a Remote I/O Slave  
Unit and controlled through a Remote I/O Master Unit. Slave Racks are gen-  
erally located away from the CPU Rack.  
software error  
An error that occurs in the execution of a program.  
software protects  
A software means of protecting data from being changed as opposed to a  
physical switch or other hardware setting.  
source  
The location from which data is taken for use in an instruction as opposed to  
the location to which the result of an instruction is to be written. The location  
to which the result of an instruction is to be written is called the destination.  
SR area  
A data area in a PC used mainly for flags, control bits, and other information  
provided about PC operation. The status of only certain SR bits may be con-  
trolled by the operator, i.e., most SR bits can only be read.  
subroutine  
A group of instructions placed after the main program and executed only if  
called from the main program or activated by an interrupt.  
subroutine number  
A definer used to identify the subroutine that a subroutine call or interrupt  
activates.  
211  
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Glossary  
SV  
Short for set value.  
switching capacity  
syntax error  
The voltage/current that a relay can switch on and off.  
An error in the way in which a program is written. Syntax errors can include  
‘spelling’ mistakes (i.e., a function code that does not exit), mistakes in speci-  
fying operands within acceptable parameters (e.g., specifying unwritable SR  
bits as a destination), and mistakes in actual application of instructions (e.g.,  
a call to a subroutine that does not exist).  
system error  
An error generated by the system as opposed to one resulting from execu-  
tion of an instruction designed to generate an error.  
system error message  
TC area  
An error message generated by the system as opposed to one resulting from  
execution of an instruction designed to generate a message.  
A data area that can be used only for timers and counters. Each bit in the TC  
area serves as the access point for the SV, PV, and Completion flag for the  
timer or counter defined with that bit.  
TC number  
terminal instruction  
timer  
A definer that corresponds to a bit in the TC area and used to define the bit  
as either a timer or a counter.  
An instruction placed on the right side of a ladder diagram that uses the final  
execution condition on an instruction line(s).  
A location in memory accessed through a TC bit and used to time down from  
the timer’s set value. Timers are turned ON and reset according to their ex-  
ecution conditions.  
TM area  
A memory area used to store the results of a trace.  
The distance that a signal can be transmitted.  
transmission distance  
TR area  
A data area used to store execution conditions so that they can be reloaded  
later for use with other instructions.  
transfer  
The process of moving data from one location to another within the PC or  
between the PC and external devices. When data is transferred, generally a  
copy of the data is sent to the destination, i.e., the content of the source of  
the transfer is not changed.  
UM area  
Unit  
The memory area used to hold the active program, i.e., the program that is  
being currently executed.  
In OMRON PC terminology, the word Unit is capitalized to indicate any prod-  
uct sold for a PC System. Though most of the names of these products end  
with the word Unit, not all do, e.g., a Remote Terminal is referred to in a col-  
lective sense as a Unit. Context generally makes any limitations of this word  
clear.  
unit number  
A number assigned to some Link Units and Special I/O Units to assign words  
and sometimes other operating parameters to it.  
watchdog timer  
A timer within the system that ensures that the cycle time stays within speci-  
fied limits. When limits are reached, either warnings are given or PC opera-  
tion is stopped depending on the particular limit that is reached. Although a  
default value of 130 ms is automatically set for the basic time limit, this value  
can be extended by the program.  
212  
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Glossary  
Wired Slave Rack  
word  
A Slave Rack connected through a Wired Remote I/O Slave Unit.  
A unit of storage in memory that consists of 16 bits. All data areas consists of  
words. Some data areas can be accessed by words; others, by either words  
or bits.  
word address  
The location in memory where a word of data is stored. A word address must  
specify (sometimes by default) the data area and the number of the word that  
is being addressed.  
work bit  
A bit in a work word.  
work word  
A word that can be used for data calculation or other manipulation in pro-  
gramming, i.e., a ‘work space’ in memory. A large portion of the IR area is  
always reserved for work words. Parts of other areas not required for special  
purposes may also be used as work words, e.g., I/O words not allocated to  
I/O Units.  
213  
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Index  
controlbits,usage,10  
Numbers  
controlsystem,definitionof,3  
Counter−CNT. Seeinstructionset  
CPUindicators,8  
16−TO−4ENCODER−DMPX(77). Seeinstructionset  
4−TO−16DECODER−MLPX(76). Seeinstructionset  
cycletime  
calculating,141  
components,140  
displaying,54  
forinstructionexecution,143,172  
longduration,140  
CycleTimeErrorFlag. Seedataareas  
A
ADD(30). Seeinstructionset  
AlwaysON/OFFflags. Seedataareas  
AnalogTimerUnit. Seeinstructionset  
AND. Seeinstructionset  
ANDLD. Seeinstructionset  
ANDLOAD. Seeinstructionset  
ANDNOT. Seeinstructionset  
ANDNOT−ANDNOT. Seeinstructionset  
arithmeticoperationflags. Seedataareas  
D
dataareas  
components,10  
DataMemoryarea,23  
HR,23  
IR  
B
I/Obitsavailable  
inCPUs,14  
inExpansionI/OUnits,15  
wordallocation,13  
SR  
AlwaysOFF/ONFlags,22  
arithmeticflags,22,189  
BatteryAlarmFlag,21  
ClockPulseBits,21  
CycleTimeErrorFlag,21  
ErrorFlag,22,189  
FirstCycleFlag,22  
highspeeddrum/counterreset,21  
StepFlag,22  
backup. Seecassettetapeoperation  
BatteryAlarmFlag. Seedataareas  
BCDADD−ADD(30). Seeinstructionset  
BCDDIVIDE−DIV(33). Seeinstructionset  
BCDMULTIPLY−MUL(32). Seeinstructionset  
BCDSUBTRACT−SUB(31). Seeinstructionset  
BCD(24). Seeinstructionset  
BCD−TO−BINARYCONVERSION−BIN(23). See  
instructionset  
BIN(23). Seeinstructionset  
binarytable,191  
BINARY−TO−BCDCONVERSION−BCD(24). See  
instructionset  
usage,21  
structure,10  
TC,23  
TR,24  
bits  
forceset/reset,153  
monitor,150  
selfmaintaining,60  
digit,monitor,150  
DIV(33). Seeinstructionset  
DMarea. Seedataareas  
DMPX(77). Seeinstructionset  
branching. Seeladderdiagram  
C
CarryFlag. Seedataareas  
E
cassettetapeoperation,157ć160  
comparingprogrammemorydata,159  
errormessages,158  
restoringprogrammemorydata,159  
savingprogrammemorydata,158  
END−END(01). Seeinstructionset  
ENDWAIT−ENDW(62). Seeinstructionset  
END(01). Seeinstructionset  
ENDW(62). Seeinstructionset  
EqualFlag. Seedataareas  
CLC(41). Seeinstructionset  
CLEARCARRY−CLC(41). Seeinstructionset  
ClockPulseBits. Seedataareas  
ErrorFlag. Seedataareas  
errors  
cassettetapeoperations,158  
clearingmessages,49  
fatal,163  
messagetables,162  
non−fatal,163  
CMP(20). Seeinstructionset  
CNTR(12). Seeinstructionset  
COMPARE−CMP(20). Seeinstructionset  
comparingprogram/memorydata. SeecassettetapeopĆ  
eration  
215  
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Index  
readingandclearingmessages,162  
SRareaflags,164  
CNTR(12),93  
DIFD(14)  
asabitcontrolinstruction,75  
useininterlocks,79  
DIFU(13)  
asabitcontrolinstruction,75  
useininterlocks,79  
DIV(33),124  
DMPX(77),118  
END(01),32,81  
ENDW(62),135  
HDM(61),94  
F
FactoryIntelligentTerminal. SeePeripheralDevices  
FirstCycleFlag. Seeinstructionset  
FIT. SeePeripheralDevices  
flags  
executionaffect,69  
usage,10  
IL(02),78  
FloppyDiskInterfaceUnit. SeePeripheralDevices  
convertingtomnemoniccode,72  
useinbranching,42  
ILC(03),78  
convertingtomnemoniccode,72  
useinbranching,42  
IORF(97),135  
G
GPC. SeePeripheralDevices  
GraphicProgrammingConsole. SeePeripheralDevices  
GreaterThanFlag. Seedataareas  
JME(05),80  
JMP(04),80  
KEEP(11)  
H
asabitcontrolinstruction,77  
controllingbitstatus,60  
LD,73  
useinladderdiagrams,30  
LDNOT,73  
useinladderdiagrams,30  
MLPX(76),116  
MOV(21),111  
HDM(61). Seeinstructionset  
high−speeddrumcounterreset. Seedataareas  
HIGHꢀSPEEDDRUMCOUNTER−HDM(61). See  
instructionset  
HIGHꢀSPEEDTIMER−TIMH(15). Seeinstruction  
set  
HRarea. Seedataareas  
MUL(32),123  
MVN(22),112  
NETW(63),136  
NOP(00),81  
NOT,28  
I
I/Obitsavailable  
inCPUs,14  
OR,73  
inExpansionI/OUnits,15  
I/OREFRESH−IORF(97). Seeinstructionset  
I/Oresponsetime,145  
combiningwithAND,31  
useinladderdiagrams,31  
ORLD,74  
combiningwithANDLD,35  
useinlogicblocks,33,34  
ORNOT,73  
I/OUnits. SeeUnits  
IL(02). Seeinstructionset  
ILC(03). Seeinstructionset  
inputbit,definitionof,3  
useinladderdiagrams,31  
OUT,75  
usingtocontrolbitstatus,32  
OUTNOT,75  
usingtocontrolbitstatus,32  
RDM(60),103  
RET(93),126  
SBN(92),126  
SBS(91),126  
SFT(10),106  
SFTR(84),109  
SNXT(09),128  
STC(40),125  
STEP(08),128  
SUB(31),122  
TIM,83  
changingsetvalue,156  
TIMH(15),86  
inputdevices,definitionof,3  
inputpoint,definitionof,3  
inputsignal,definitionof,3  
instructionset  
ADD(30),120  
AnalogTimerUnit,87  
AND,73  
combiningwithOR,31  
useinladderdiagrams,30  
ANDLD,74  
combiningwithORLD,35  
useinlogicblocks,33  
ANDNOT,73  
useinladderdiagrams,30  
BCD(24),115  
BIN(23),115  
CLC(41),125  
CMP(20),112  
CNT,90  
WSFT(16),110  
INTERLOCK−IL(02). Seeinstructionset  
INTERLOCKCLEAR−ILC(03). Seeinstructionset  
IORF(97). Seeinstructionset  
changingsetvalue,156  
216  
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Index  
IRarea. Seedataareas  
MUL(32). Seeinstructionset  
MVN(22). Seeinstructionset  
J
N
JME(05). Seeinstructionset  
JMP(04). Seeinstructionset  
JUMP−JMP(04). Seeinstructionset  
JUMPEND−JME(05). Seeinstructionset  
NETW(63). Seeinstructionset  
NOOPERATION−NOP(00). Seeinstructionset  
NOP(00). Seeinstructionset  
NOT. Seeinstructionset  
NOTATIONINSERT−NETW(63). Seeinstructionset  
K
KEEP(11). Seeinstructionset  
O
OR. Seeinstructionset  
L
branching  
ORLD. Seeinstructionset  
ORLOAD. Seeinstructionset  
ORNOT. Seeinstructionset  
ORNOT−ORNOT. Seeinstructionset  
outputbit,definitionof,3  
outputdevices,definitionof,3  
outputpoints,definitionof,3  
outputsignal,definitionof,3  
ladderdiagram  
useof,39  
usingIL(02)andILC(03),42  
usingJMP(04)andJME(05),43  
usingTRbits,40  
convertingtomnemoniccode,28ć44  
instructions  
combining  
ANDandOR,31  
ANDLDandORLD,35  
controllingbitstatus  
usingDIFU(13)andDIFD(14),75  
usingKEEP(11),60,77  
usingOUTandOUTNOT,32,75  
format,68  
functionof,26  
notation,68  
operands,functionof,27  
structureof,27  
usinglogicblocks,32  
P
PeripheralDevices,5  
FactoryIntelligentTerminal(FIT),6  
standardmodels,169  
FloppyDiskInterfaceUnit,6  
GraphicProgrammingConsole(GPC),5  
standardmodels,169  
LadderSupportSoftware(LSS),5  
PrinterInterfaceUnit,6  
ProgrammingConsole,5,44  
clearingmemory,47  
LadderSupportSoftware. SeePeripheralDevices  
LD. Seeinstructionset  
modesof,45  
operationof,46  
thekeyboard,44  
PROMWriter,6  
standardmodels,170  
PrinterInterfaceUnit. SeePeripheralDevices  
LDNOT. Seeinstructionset  
LEDs. SeeCPUindicators  
leftmost,definition,11  
LessThanFlag. Seedataareas  
LinkUnits. SeeUnits  
LOAD−LD. Seeinstructionset  
LOADNOT−LDNOT. Seeinstructionset  
logicblocks. Seeladderdiagram  
LSS. SeePeripheralDevices  
programexecution,65  
ProgramMemory,10  
Seealso memoryareas  
structure,29  
programming  
consoleoperationsintableform,183  
debugging,148  
displayingandclearingerrormessages,148  
inputting,modifyingandchecking,49  
insertinganddeletinginstructions,57  
instructiontable,171  
instructions. SeeInstructionset  
method,4  
overwritingexistingprograms,51  
precautions,63  
searchingtheprogram,55  
settingandreadingfrommemoryaddress,50  
M
memoryareas  
dataareas. Seedataareas  
definitionof,10  
programmemory. Seeprogrammemory  
MLPX(76). Seeinstructionset  
mnemoniccode,converting,28ć44  
MOV(21). Seeinstructionset  
MOVE−MOV(21). Seeinstructionset  
MOVENOT−MVN(22). Seeinstructionset  
ProgrammingConsole. SeePeripheralDevices  
217  
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Index  
PROMWriter. SeePeripheralDevices  
STC(40). Seeinstructionset  
StepFlag. Seedataareas  
STEPSTART−SNXT(09). Seeinstructionset  
STEP(08). Seeinstructionset  
SUB(31). Seeinstructionset  
SUBROUTINEENTER−SBS(91). Seeinstructionset  
SUBROUTINESTART−SBN(92). Seeinstructionset  
R
RDM(60). Seeinstructionset  
restore. Seecassettetapeoperation  
RET(93). Seeinstructionset  
RETURN−RET(93). Seeinstructionset  
REVERSIBLECOUNTER−CNTR(12). SeeinstrucĆ  
tionset  
T
REVERSIBLEDRUMCOUNTER−RDM(60). See  
instructionset  
REVERSIBLESHIFTREGISTER−SFTR(84). See  
instructionset  
TCarea. Seedataareas  
TIM. Seeinstructionset  
TIMH(15). Seeinstructionset  
TRarea. Seedataareas  
rightmost,definition,11  
TRbits  
convertingtomnemoniccode,71  
useinbranching,40  
S
SBN(92). Seeinstructionset  
SBS(91). Seeinstructionset  
SETCARRY−STC(40). Seeinstructionset  
SFT(10). Seeinstructionset  
U
UMarea. Seeprogrammemory  
Units  
SFTR(84). Seeinstructionset  
SHIFTREGISTER−SFT(10). Seeinstructionset  
SINGLESTEP−STEP(08). Seeinstructionset  
SNXT(09). Seeinstructionset  
SpecialI/OUnits. SeeUnits  
definitionof,3  
I/OUnits,definitionof,3  
LinkUnits,definitionof,4  
SpecialI/OUnits,definitionof,4  
SRarea. Seedataareas  
standardmodels  
DINUnits,169  
FactoryIntelligentTerminal,169  
GraphicProgrammingConsole,169  
I/OUnits,167  
W
words,I/O,13  
WORDSHIFT−WSFT(16). Seeinstructionset  
workbits,usage,10  
workwords,usage,10  
K−typeCPUs,166  
PeripheralDevices,170  
SpecialUnits,168  
writingaprogram  
Seealso programming  
steps,26  
statusindicators. SeeCPUindicators  
WSFT(16). Seeinstructionset  
218  
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