Intel® 21143 PCI/CardBus 10/
100Mb/s Ethernet LAN Controller
Design Guide
July 2002
Order Number: 278588-001
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Contents
Contents
1.0 Functional Overview........................................................................................................................5
21143 Overview....................................................................................................................5
Network Interface..................................................................................................................5
MII-Based PHY Block Diagram.............................................................................................6
SYM-Based PHY Block Diagram..........................................................................................6
2.0 21143 Ports .....................................................................................................................................7
3.0 Network Connection ........................................................................................................................9
10BASE-T Twisted-Pair Network Port..................................................................................9
3.2.1 Internal Optional Daughtercard..............................................................................13
3.2.3 100-Ready External Module Design ......................................................................14
3.2.5 MII/SYM Pin Listing ...............................................................................................14
AUI Network Port................................................................................................................15
Media-Specific Components...............................................................................................18
4.0 21143 Requirements .....................................................................................................................19
Unused JTAG Port Requirements ......................................................................................19
Current Reference and Capacitor Input Requirements ......................................................19
Crystal and Crystal Oscillator Connections ........................................................................20
5.0 Signal Routing and Placement ......................................................................................................21
Ground and Power Planes..................................................................................................21
5.1.1 3.3 V Power Supply ...............................................................................................22
LED Status Signals.............................................................................................................22
6.0 Design Considerations ..................................................................................................................23
Designing the Ethernet Corner on Motherboards...............................................................23
Suggestions for FCC Compliance ......................................................................................23
6.2.1 Suggestions for Quiet Ground and Power Planes .................................................23
6.2.2 Suggestions for Routing ........................................................................................24
Figures
MII-Based PHY Design.................................................................................................................6
SYM-Based PHY Design..............................................................................................................7
10BASE-T Network Connection with Buffers..............................................................................10
10BASE-T Network Connection Without Buffers........................................................................11
Minimum Components Required for 10BASE-T........................................................................12
10BASE-T 100-Ready Daughtercard Block Diagram.................................................................13
10BASE-T 100-Ready External Module Block Diagram.............................................................14
AUI 10BASE5 Network and Pin Connections.............................................................................16
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Contents
AUI 10BASE2 Network Connection............................................................................................17
10 21143 External Component Connections...................................................................................20
11 LED Time-Stretcher Circuit.........................................................................................................22
Tables
Signal gep<0>/aui_bnc Description..............................................................................................5
AUI Signals...................................................................................................................................7
Twisted-Pair Signals.....................................................................................................................7
MII Signals....................................................................................................................................8
SYM Signals.................................................................................................................................8
Internal vs. External Design Features .......................................................................................13
MII/SYM Pinout...........................................................................................................................14
10BASE-T Media-Specific Components.....................................................................................18
10BASE2 and 10BASE5 Media-Specific Components ..............................................................18
10 Pin Requirements When Not Using the JTAG Port....................................................................19
11 Current Reference and Capacitor Inputs....................................................................................19
12 Crystal Specifications .................................................................................................................20
Revision History
Date
Revision
Description
July 2002
001
First release.
4
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Intel® 21143 PCI/CardBus 10/100Mb/s Ethernet LAN Controller
This design guide provides a description of how to implement 100BASE-TX and 10BASE-T
network connections using the 21143 PCI/CardBus 10/100 Mb/s Ethernet LAN Controller
(referred to as the 21143).
While this document will not provide specific recommendations for physical layer devices, it will
provide design recommendations and layout recommendations.
This application note provides a description of how to implement 100BASE-TX and 10BASE-T
network connections using the 21143 PCI/CardBus 10/100 Mbs/s Ethernet LAN Controller
(referred to as the 21143).
1.0
Functional Overview
This section provides an overview of the 21143 and the implementation of 100 Mb/s and 10 Mb/s
network connections using MII-based or SYM-based PHY devices.
1.1
21143 Overview
The 21143 is a single-chip bus master Ethernet/Fast Ethernet device that supports direct memory
access (DMA) and has direct interfaces to both the CardBus and the PCI local bus. The 21143
implements a direct interface to the CardBus or PCI bus through a single 50-pin connection, which
consists of the control and address/data signals.
The 21143 provides a complete implementation of the IEEE 802.3 Ethernet specification. This
includes the attachment unit interface (AUI), twisted-pair (10BASE-T) interface, MII SYM port
interface, and the interface through the media access control (MAC) layer that creates a direct
interface to the PCI bus.
The PCI interface utilizes only about 10% of the bus bandwidth during fully networked operation
for 100 Mb/s Fast Ethernet reception or transmission. This bus master design results in high
throughput between the system and the network.
1.2
Network Interface
The 21143 physical layer design supports AUI drop cable Ethernet and 10BASE-T twisted-pair
(TP) Ethernet connections. The 21143 gep<0>/aui_bnc (pin 100), which is software controlled,
provides for a connection of either the AUI (10BASE5) or BNC (10BASE2) network connector.
Table 1 describes the function of this pin.
Table 1. Signal gep<0>/aui_bnc Description
Program State
Function
0
1
AUI port enabled; BNC port disabled.
BNC transceiver (or DC-to-DC converter) enabled; AUI port disabled
AUI signals interface with the Manchester encoder/decoder portion of the 21143. The 21143
supports 10BASE5 thickwire and 10BASE2 ThinWire connections. The 10BASE2 connection
requires an external transceiver.
Design Guide
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Intel® 21143 PCI/CardBus 10/100Mb/s Ethernet LAN Controller
The 21143 implements the 100BASE-T MII layer and the 100/10 Mb/s Ethernet MAC layer. The
21143 provides a dual network interface for both a 100BASE-T and a 10 Mb/s Ethernet. At the
100BASE-T port, the 21143 supports the industry-standard MII for any 100BASE-T
implementation.
The 21143 is fully compliant with the MII specifications (as defined in IEEE 802.3). The MII is a
nibblewide, general interface, that can be used with various physical interfaces, such as 100BASE-
TX, 100BASE-T4, shielded twisted-pair (STP), and fiber. It also supports dual rates of speed
(10 Mb/s and 100 Mb/s).
The 21143 includes special support for 100BASE-TX networks by including the PCS section
(scrambler and 5B/4B coding/decoding). Integrating the 10BASE-T ENDEC with the 100 Mb/s-
only SYM-based PHYs enables full support for a 10/100-implementation.
1.3
MII-Based PHY Block Diagram
Figure 1 is a block diagram of a 10BASE-T and 100BASE-T single-connector network connection
using a MII-based PHY device with the 21143.
MII-based PHY devices are provided by Intel, Integrated Circuit Systems*, National
Semiconductor*, Seeq*, and TDK*.
Figure 1. MII-Based PHY Design
MII Port
of
21143
MII-Based
PHY
Devices
10/100 Mb/s
Network
Magnetics
Module
The MII-based PHY design includes the following components:
• The MII-based PHY devices, which have a direct interface to the MII port of the 21143 with
dual-rate option (as specified in the MII specification) and a full interface to the 10/100 Mb/s
magnetics module.
• The magnetics module, which is based on transformers and serial chokes enabling the network
connection to the 100 Mb/s network (100BASE-TX or 100BASE-T4) and to the 10 Mb/s
network (10BASE-T).
1.4
SYM-Based PHY Block Diagram
Figure 2 is a block diagram of a 100BASE-TX single-connector network connection using a SYM-
based PHY device with the 21143. For a 10 Mb/s network connection, the network can be
connected directly to the 21143 through filters and chokes.
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Intel® 21143 PCI/CardBus 10/100Mb/s Ethernet LAN Controller
SYM-based PHY devices are provided by GEC Plessey*, Quality Semiconductor*, and Micro
Linear*.
Figure 2. SYM-Based PHY Design
SYM Port
of
21143
SYM-Based
PHY
Devices
100 Mb/s
Network
Magnetics
Module
The SYM-based PHY design includes the following components:
• The SYM-based PHY devices, which have a direct interface to the SYM port of the 21143
with an interface to the 100 Mb/s magnetics module.
• The magnetics module, which is based on transformers and serial chokes enabling the network
connection to the 100 Mb/s-only network (100BASE-TX or 100BASE-T4).
2.0
21143 Ports
Table 2 lists the active AUI signals when the 21143 AUI port is selected.
Table 2. AUI Signals
Signal
Pin Number
aui_cd–
aui_cd+
aui_rd–
aui_rd+
aui_td–
aui_td+
138
137
140
139
143
142
Table 3 lists the active twisted-pair signals when the 21143 10BASE-T port is selected.
Table 3. Twisted-Pair Signals
Signal
Pin Number
tp_rd–
tp_rd+
tp_td–
10
9
5
tp_td– –
tp_td+
4
6
tp_td+ +
7
Table 4 lists the active MII signals when the 21143 MII port is selected.
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Intel® 21143 PCI/CardBus 10/100Mb/s Ethernet LAN Controller
Table 4. MII Signals
Signal
Pin Number
mii_clsn
mii_crs
118
117
mii_dv
129
mii_mdc
mii_mdio
mii_rclk
mii_rx_err
134
135
128
127
mii_rxd <3:0>
mii_tclk
133:130
124
mii_txd<3:0>
mii_txen
119:122
123
Table 5 lists the active SYM signals when the 21143 SYM port is selected.
Table 5. SYM Signals
Signal
Pin Number
sd
117
127
128
130
131
132
133
118
124
122
121
120
119
123
sel10_100
sym_rclk
sym_rxd<0>
sym_rxd<1>
sym_rxd<2>
sym_rxd<3>
sym_rxd<4>
sym_tclk
sym_txd<0>
sym_txd<1>
sym_txd<2>
sym_txd<3>
sym_txd<4>
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Intel® 21143 PCI/CardBus 10/100Mb/s Ethernet LAN Controller
3.0
Network Connection
The network connections of the 21143 can be used in 10BASE-T, AUI, MII, or SYM
configurations. Different methods are used to connect each port to the actual cable connector.
3.1
10BASE-T Twisted-Pair Network Port
implementations.
1:1 transformer module. This implementation type requires a swing compensator (to swing the
21143 output from 3.3 V to 5 V) to meet the standard requirements.
provides the lowest component count for 10BASE-T. The filter and transformer components
minimize any potential electromagnetic interference and radio frequency interface problems.
Common-mode noise (when noise between two lines of the same polarity add rather than cancel)
can radiate energy from the twisted-pair interface. Also, significant common-mode power supply
noise can be generated on the board or adapter by other devices. Therefore, Intel recommends the
use of filter and transformer modules that incorporate common-mode chokes.
network connection with buffers. The required components for this configuration are as follows:
• Voltage swing compensator — 74ACT244
• Terminating and decoupling components
• Filter transformer and common-mode chokes
• RJ45 connector
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Intel® 21143 PCI/CardBus 10/100Mb/s Ethernet LAN Controller
Figure 3. 10BASE-T Network Connection with Buffers
21143
74ACT244
61.9
Ω
8
tp_td+ 6
12
14
301Ω
3
1
tp_td++ 7
6
Transmit
Path
TP Filters
and Chokes
78Z041
806 Ω
61.9 Ω
301Ω
tp_td- 5
tp_td-- 4
4
2
(SMD)
16
18
RJ45
8
1
2
6
5
9
3
6
GND
11
tp_rd- 9
14
49.9Ω
49.9Ω
Receive
Path
tp_rd- 10
GND
16
0.01 µF
GND
0.1 µF
GND
LJ-05141.WMF
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Intel® 21143 PCI/CardBus 10/100Mb/s Ethernet LAN Controller
Figure 4 shows the 10BASE-T network connection without buffers. The required components for
this configuration are as follows:
• Terminating and decoupling components
• Transformer module (ratio of 1: 2 for swing compensation)
• Filter transformer and common-mode chokes
• RJ45 connector
Figure 4. 10BASE-T Network Connection Without Buffers
21143
27 Ω
tp_td+ 6
1:
2
140Ω
3
1
tp_td++ 7
TP Filters
and Chokes
78Z041
Transmit
Path
510
PRI
SEC
Ω
27 Ω
(SMD)
tp_td- 5
tp_td-- 4
RJ45
140
8
1
2
6
5
9
3
6
11
tp_rd- 9
14
49.9 Ω
Receive
Path
Ω
49.9
GND
tp_rd- 10
16
0.01 µF
GND
0.1 µF
GND
LJ-05142.WMF
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Intel® 21143 PCI/CardBus 10/100Mb/s Ethernet LAN Controller
Figure 5 shows the minimum component requirement for the 10BASE-T network connection. This
implementation uses a filter transformer module with a 1: 2 transformer on the transmit path to
compensate for the voltage swing. The required components for this configuration are as follows:
• Terminating and decoupling components
• Filter, transformer, and common-mode chokes
• RJ45 connector
Figure 5. Minimum Components Required for 10BASE-T
21143
27 Ω
tp_td+ 6
140 Ω
TP Filters
and Chokes
tp_td++ 7
78Z1122 or
FD22-114G
(SMD)
Transmit
Path
510 Ω
27 Ω
tp_td- 5
tp_td-- 4
RJ45
140 Ω
1
2
3
6
tp_rd- 9
49.9 Ω
49.9 Ω
Receive
Path
GND
tp_rd- 10
0.01 µF
GND
0.1 µF
GND
LJ-05143.WMF
3.2
100-Ready Designs
The 21143 can also be designed for systems that are “100-Ready.” The term “100-Ready” implies
a system that has a 10 Mb/s network that can easily be upgraded to become a 10/100 Mb/s network.
There are two methods for providing 100-Ready designs:
• Provide a connector for an internal optional daughtercard.
• Provide an MII connector for an external module that connects to the MII/SYM port.
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Intel® 21143 PCI/CardBus 10/100Mb/s Ethernet LAN Controller
Table 6. Internal vs. External Design Features
Design
Features
•
•
Can be designed with an MII or any custom connector.
User opens cabinet to install 100 Mb/s daughtercard.
Internal optional daughtercard
•
User connects module to external MII/SYM connector; user does
not have to open cabinet for installation.
External MII/SYM module
3.2.1
Internal Optional Daughtercard
Figure 6 shows a block diagram of a 100-Ready design using a daughter card.
Figure 6. 10BASE-T 100-Ready Daughtercard Block Diagram
Optional
MII
21143
MII
Daughtercard
10BASE-T
RJ45
Connector
AUI
Optional
Coaxial
Connector
AUI Coaxial
Transceivers
PCI
Bus
LJ-05189.AI4
3.2.2
Description of 100-Ready Daughtercard Block Diagram
The blocks in the10BASE-T 100-Ready block diagram represent the following components:
• 21143 — A 21143 with all of the external components for operating the network connection
(reference parts, XTAL, and so on). The 21143 can use the PCI bus, and the MII/SYM,
10BASE-T, and AUI coaxial ports for communication.
• Optional MII/SYM daughtercard — A daughtercard with a 100 Mb/s or 10/100 Mb/s PHY
that interfaces with an MII connector or custom connector. The daughtercard can be designed
to use the same RJ45 connector.
• RJ45 — A network connection.
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Intel® 21143 PCI/CardBus 10/100Mb/s Ethernet LAN Controller
3.2.3
100-Ready External Module Design
Figure 7 shows a block diagram of a 100-Ready design using an external module.
Figure 7. 10BASE-T 100-Ready External Module Block Diagram
MII or
Custom
Connector
MII or
Custom
Connector
MII/SYM
RJ45
Connector
10/100
PHY Layer
21143
10BASE-T
RJ45
Connector
AUI
Optional
Coaxial
Connector
AUI Coaxial
Transceivers
PCI
Bus
LJ-05188.AI4
3.2.4
Description of 100-Ready External Module Block Diagram
The blocks in the100-Ready external module block diagram represent the following components:
• 21143 — A 21143 with all of the external components for operating the network connection
(reference parts, XTAL, and so on). The 21143 can use the PCI bus, and the MII/SYM,
10BASE-T, and AUI coaxial ports for communication.
• Optional external MII/SYM daughtercard — A daughtercard with a 100 Mb/s or 10/100 Mb/s
PHY that interfaces with an MII connector or custom connector. The daughtercard uses the
magnetics to connect to the RJ45 connector.
• MII connector — An MII or custom connector that connects with the MII/SYM port of the 21143.
• RJ45 — A network connection.
3.2.5
MII/SYM Pin Listing
Table 7 describes the MII/SYM pin multiplexing enabling the full flexibility for both network
connections options using the same internal connector for the MII-based or the SYM-based PHY
device (for detailed implementation notes, refer to the specific PHY device section in this document).
Table 7. MII/SYM Pinout (Sheet 1 of 2)
Pin Number
MII Interface Function
mii_crs
SYM Interface Function
117
118
119
120
121
sd
mii_clsn
sym_rxd<4>
sym_txd<3>
sym_txd<2>
sym_txd<1>
mi_txd<3>
mi_txd<2>
mi_txd<1>
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Intel® 21143 PCI/CardBus 10/100Mb/s Ethernet LAN Controller
Table 7. MII/SYM Pinout (Sheet 2 of 2)
Pin Number
MII Interface Function
mii_txd<0>
SYM Interface Function
sym_txd<0>
122
123
124
127
128
129
130
131
132
133
134
135
mii_txen
sym_txd<4>
sym_tclk
sel10_100
mii_rclk
mii_tclk
mii_rx_err
mii_rclk
mii_dv
N.C.
mii_rxd<0>
mii_rxd<1>
mii_rxd<2>
mii_rxd<3>
mii_mdc
sym_rxd<0>
sym_rxd<1>
sym_rxd<2>
sym_rxd<3>
N.C.
mii_mdio
N.C.
3.3
AUI Network Port
The 21143 is fully compliant with the AUI standard. The AUI can interface with an external
medium-attachment unit (MAU) and connect to alternate media, such as 10BASE2 (ThinWire) and
Figure 8 shows the AUI 10BASE5 network connection and the pin connections between the 21143
and the isolation transformer. The required components for this configuration are as follows:
• Terminating and decoupling components
• Isolation transformer
• AUI connector
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Intel® 21143 PCI/CardBus 10/100Mb/s Ethernet LAN Controller
Figure 8. AUI 10BASE5 Network and Pin Connections
AUI
Connector
Isolation
21143
Transformer
ST7032
10
XFMR_RD+
aui_rd+ 139
7
40.2 Ω
Ω
15
14
13
12
11
10
9
40.2
0.01 µF
Receive
Path
+12 V
40.2 Ω
XFMR_RD-
XFRM_CD+
8
4
GND
0.22 µF
9
aui_rd- 140
aui_cd+ 137
13
40.2 Ω
40.2 Ω
8
0.01 µF
Collision
Path
Ω
GND
40.2
7
6
XFRM_CD-
XFMR_TD+
0.01 µF
5
5
GND
12
16
aui_cd- 138
aui_td+ 142
4
Ω
18
3
1
GND
2
47Ω
1
22 pF
Transmit
Path
511
GND
Ω
XFMR_TD-
GND
2
15
aui_td- 143
18 Ω
LJ-05144.WMF
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Intel® 21143 PCI/CardBus 10/100Mb/s Ethernet LAN Controller
Figure 9 shows the AUI 10BASE2 network connection. In this configuration, the AUI is not
externally exposed. The required components for this configuration are as follows:
• Isolation transformer
• Terminating and decoupling components
• DC-to-DC converter
• Coaxial transceiver and BNC connector
Figure 9. AUI 10BASE2 Network Connection
Isolation
21143
Coaxial
Transceiver
NE8392
Transformer
ST7032
10
XFMR_RD+
XFMR_RD-
XFRM_CD+
XFRM_CD-
7
aui_rd+ 139
Coaxial
40.2 Ω
40.2 Ω
0.01 µF
511 Ω
511 Ω
511 Ω
511 Ω
Receive
Path
Receive
Collision
Transmit
8
4
5
GND
9
aui_rd- 140
aui_cd+ 137
13
40.2 Ω
40.2 Ω
0.01 µF
Collision
Path
1 k
Ω
GND
12
16
aui_cd- 138
aui_td+ 142
Ω
18
XFMR_TD+
1
2
47 Ω
40.2 Ω
40.2 Ω
XFMR_TD-
22 pF
Transmit
Path
511
GND
18 Ω
Ω
15
aui_td- 143
aui_bnc 100
2
+12 V
-9 V
Ω
1 M
3
1
Enable
8
7
0.1 µF
1000 pF
dc-to-dc
Converter
80Z1209
0.75 pF (1000 V)
1000 pF (1000 V)
22 µF
0.1 µF
GND
4700 pF
GND
Note:
Refer to the vendor data sheet for the specific implementation of the coaxial transceiver (NE8392).
LJ-05145.WMF
In cases where 10BASE2 MAU is a module separate from the board, MAU can be implemented on a
small add-in card. Ensure that the cable used to connect the board to MAU provides adequate shielding of
the AUI signals from external noise. This MAU add-in card includes the following components:
• Transceiver chip and BNC connector
• DC-to-DC converter
• Discrete devices
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Intel® 21143 PCI/CardBus 10/100Mb/s Ethernet LAN Controller
3.4
Media-Specific Components
media-specific interface components for 10BASE2 and 10BASE5 access.
Table 8. 10BASE-T Media-Specific Components
Access Type
10BASE-T
Components
74ACT244 driver
Available Part Numbers
74ACT244 or 74FCT244
1
Pulse Engineering* PE65745
1
Valor*PT4096
1
Filter and transformer module
Valor* ST7011
1
Halo* TD42-2006Q
1
Halo* TG42-2006W1
Pulse Engineering* PE65434
Valor* FL1012
Transformer filter and chokes
RJ45 wire jack connector
—
1.
Surface-mount device.
Table 9. 10BASE2 and 10BASE5 Media-Specific Components
Access Type
10BASE2
Components
DC-to-DC converter
Available Part Numbers
Fil Mag* 80Z1209DSND
1
Valor* ST7032
Pulse Engineering* PE65723
Valor* LT6032
Isolation transformer
Valor* ST6032/3
Halo* TD01-0756K
Halo* TG01-0756W
Coaxial transceiver
Connector
National Semiconductor* DP8392C
—
Valor* ST7032
Pulse Engineering* PE65723
Valor* LT6032
10BASE5
Isolation transformer
Valor* ST6032/3
Halo* TD01-0756K
Halo* TG01-0756W
AUI connector
—
1.
Surface-mount device.
18
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Intel® 21143 PCI/CardBus 10/100Mb/s Ethernet LAN Controller
4.0
21143 Requirements
This section provides information about the external component connections for the 21143, and
describes the following requirements:
• Unused JTAG port requirements
• Current reference and capacitor input
• Crystal connection or crystal oscillator connection for the serial clock connection
4.1
Unused JTAG Port Requirements
Table 10. Pin Requirements When Not Using the JTAG Port
Leave the Following JTAG Pins Open
tms (pin 1)
Pull the Following JTAG Pin Up or Down
tck (pin 120)
tdi (pin 2)
tdo (pin 4)
4.2
Current Reference and Capacitor Input Requirements
Table 11 describes the current reference and capacitor input requirements for the 21143, and
Figure 10 shows the external component connections.
Table 11. Current Reference and Capacitor Inputs
Pin Name Pin Number
Function
Connect This Pin...
Current reference input for the analog
phase-locked loop (PLL)
iref
108
110
Through a 2.4 kΩ resistor to ground
vcap_h
Capacitor input
Through a 0.022 µF capacitor to ground
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Intel® 21143 PCI/CardBus 10/100Mb/s Ethernet LAN Controller
Figure 10. 21143 External Component Connections
Intel® 21143
Ethernet Controller
106
xtal1
xtal2
Crystal
Connection
82 pF
20-MHz
Crystal
10 kΩ
100
Ω
120 pF
GND
105
20-MHz Input Clock
No Connection
106
107
Crystal
Oscillator
Connection
xtal1
xtal2
108
iref
Current
Reference
Connection
2.4 kΩ
GND
110
vcap_h
0.022 µF
GND
B0033-01
4.3
Crystal and Crystal Oscillator Connections
Figure 10 shows two serial clock connections; select either the crystal connection or the crystal
oscillator connection. According to the IEEE 802.3 standard, a 20 MHz crystal is required. The
crystal frequency must not vary by more than 100 parts per million (PPM), or 0.01%. Place the
crystal as close as possible to the 21143.
Because the frequency of crystals from different vendors can vary, test the crystals in the actual circuit. It
may be necessary to vary the tuning of the surrounding components. However, after the capacitors have
been tuned for the specific crystal, the design does not need to be altered on a board-by-board basis.
component and xtal2 should be left open.This is useful for applications with multiple network connections.
Table 12 lists the crystal specifications.
Table 12. Crystal Specifications
Specification
Value
Units
Crystal frequency
20.000
±50
50
MHz
PPM
pF
Frequency tolerance
Load capacitance
Frequency stability
±30
40
PPM
Ohms (Ω)
µW
Maximum effective series resistance
Test condition drive level
100
20
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Intel® 21143 PCI/CardBus 10/100Mb/s Ethernet LAN Controller
5.0
Signal Routing and Placement
The Ethernet circuitry should be kept free of interference from unrelated signal traces. Routing for
other signals must be kept away from the space surrounding the grouped Ethernet components. Place
the Ethernet circuitry at the perimeter of the board, as close as possible to the network connector.
The onchip crystal oscillator requires an external crystal and discrete components. For stable and
noise-free operation, place the crystal and discrete components as close as possible to the 21143,
keeping the etch length as short as possible. Do not route any noisy signals in this area.
The PCI pin ordering is fully compatible with the PCI specification recommendation and can be
easily routed within the specified etch limits of the PCI signals. This includes shared signal lengths
of up to 3.8 cm (1.5 in) and the clock signal length of 6.41 cm (2.5 in).
Keep all signal paths short and route them as directly as possible.
Systems using 10BASE-T nodes can be connected by cables up to 100 m (328 ft.). As a result, signals
that reach the board can be noisy and low in amplitude. To minimize corrupting this data, route these
signals, by most direct path, from the network connector and through the magnetics coupler to the 21143.
The length of this path should not exceed 8 cm (3 in) for the active AUI signals. The MII/SYM
interface operates at 25 MHz (or 2.5 MHz). All routing of the MII/SYM signals to the MII/SYM device
should be as short as possible and should not have significant differences of lengths and characteristics
within signal groups. Examples of signal groups include mii_rxd<4:0> and mii_txd<4:0>.
Note: The routing of these signals should be done with caution. The preferred routing of these signals is
in the external routing layers of the board. The MII/SYM device should be located between the
21143 and the magnetics port.
5.1
Ground and Power Planes
Up to four types of power signals require handling when implementing a design with the 21143:
• Gnd is adapter ground.
• Vcc (+5 V from PCI) drives the external components (boot ROM and Ethernet address ROM).
• Vdd (+3.3 V) drives the 21143.
• Vee (-9 V output) power from the DC-to-DC converter if the coaxial network connection is
implemented. For information specific to the -9 V power supply, refer to the transceiver used
to drive the coaxial network connection.
Intel recommends that at least two power planes be kept on the PCB: Vcc and Gnd. The Vdd
power plane (+3.3 V) can be implemented either by a cut in the Vcc power plane, or by a power
island under the 21143 on one of the signal routing layers.
Intel recommends that decoupling capacitors should be connected to all power supplies. These
capacitors should be placed as close as possible to the power pins of the chips. The recommended
values are as follows: 0.1 µF, 0.01 µF, 10 µF (tantalum), and 47 µF (tantalum).
For better noise-testing immunity, separate all power planes between the network connectors and
the transformer from the logic and analog power planes of the adapter for the 10BASE-T,
10BASE2, 100BASE-T4, and 100BASE-TX connections.
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Intel® 21143 PCI/CardBus 10/100Mb/s Ethernet LAN Controller
Intel also recommends that the connector’s shield of the adapter should be connected to the PC chassis.
5.1.1
3.3 V Power Supply
The 21143 operates with a power supply of 3.3 V. At least eight decoupling capacitors are
recommended and should contain the following values:
• Three each at 0.1 µF
• Three each at 0.01 µF
• One each at 10 µF (tantalum)
• One each at 47 µF (tantalum)
5.2
LED Status Signals
The LED connection requires a serial resistor that is connected to ground. This resistor value should
be calculated according to the type of LED used. A typical 2 mA LED requires a 750 Ω resistor. For
implementations using the boot ROM, the LED current should not exceed 2 mA. For LED indication
and programming information, refer to the CSR15 definition in the 21143 PCI /CardBus 10/100 Mb/s
Ethernet LAN Controller Hardware Reference Manual.
The 21143 requires LED time-stretching logic for a visible indication of the activity signal.
Figure 11 shows how to implement this circuit.
Figure 11. LED Time-Stretcher Circuit
+5 V
100 k Ω
1N14B
1N14B
750 Ω
750 Ω
Active Low
Active High
74
HCT132
22 nF
22 nF
+5 V
74
HCT132
100 k Ω
LJ-04061.AI4
22
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Intel® 21143 PCI/CardBus 10/100Mb/s Ethernet LAN Controller
6.0
Design Considerations
This section provides information to aid the user in designing Ethernet and Fast Ethernet capabilities
onto a motherboard. In addition, it also includes design considerations for FCC compliance.
6.1
Designing the Ethernet Corner on Motherboards
This subsection provides a list of routing suggestions and a list of component placement suggestions.
The following list contains routing recommendations:
• Minimize the length of high-frequency signals.
• Route differential signal pairs together.
• Minimize the use of vias for high-frequency signals.
The following list contains component placement recommendations.
• Refer to the PCI Local Bus Specification, Revision 2.1 for the placement of the 21143 with
relation to the PCI bus.
• Place the 21143 as close to the PHY device as possible.
• Place the PHY device as close to the filters and magnetics as possible.
• Place the filters and magnetics as close to the RJ45 connector as possible.
6.2
Suggestions for FCC Compliance
Product designs and their associated applications are unique. Therefore, the designer must consider
the total system or module implementation when determining a product design for FCC compliance.
The following information is provided as suggestions only to aid the designer in meeting FCC
regulations.
6.2.1
Suggestions for Quiet Ground and Power Planes
For quiet ground and power planes, consider the following suggestions:
• Isolate power plane for PLL stability and noise isolation of audio digital-analog converters and
amplifiers.
• Partition ground planes to isolate the I/O from common system noise. Do not route any etch
across an isolated or partitioned ground plane.
Note: Ground plane splits can affect a signal’s return path back to its source. If the signal return path is
along the ground plane underneath the signal etch, any interruption in the ground plane increases
the return path loop area, which in turn, increases its ability to radiate.
• Add common-mode chokes to the design at the output of the isolation transformer to isolate
the I/O from common system noise.
• Place high-speed signals between power and ground planes to reduce board-level radiation.
The following books are recommended as additional references:
• Fundamentals of Electromagnetic Capability, by William G. Duff
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Intel® 21143 PCI/CardBus 10/100Mb/s Ethernet LAN Controller
• Engineering Electromagnetic Capability, by V. Prasad Kodali
6.2.2
Suggestions for Routing
For routing information, consider the following suggestions:
• Never route any etch (power or ground) across a partition or void because the signal loses its
return-path integrity and contaminates the isolated plane.
• Avoid placing oscillators, phase-locked loops, and other clock-type devices near I/O connectors.
• Route all critical signals (for example; clocks, video output) directly in the etch and avoid, if
possible, using vias (signal paths routed between planes in an etch board).
Note: Critical signals should be prioritized from the fastest to the slowest with respect to frequency and
rise time. The fastest critical signals should be routed first.
24
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