Cypress Clock CYV15G0104TRB User Manual

CYV15G0104TRB

Independent Clock HOTLink II™ Serializer and

Reclocking Deserializer

transfer of data over a variety of high-speed serial links

including SMPTE 292M and SMPTE 259M video applications.

Features

• Second-generation HOTLink technology

• Compliant to SMPTE 292M and SMPTE 259M video

standards

• Single channel video serializer plus single channel

video reclocking deserializer

It supports signaling rates in the range of 195 to 1500 Mbps

per serial link. The transmit and receive channels are

independent and can operate simultaneously at different

rates. The transmit channel accepts 10-bit parallel characters

in an Input Register and converts them to serial data. The

receive channel accepts serial data and converts it to 10-bit

parallel characters and presents these characters to an Output

retransmitted through the reclocker serial outputs. Figure 1

illustrates typical connections between independent video co-

processors and corresponding CYV15G0104TRB chips.

— 195- to 1500-Mbps serial data signaling rate

— Simultaneous operation at different signaling rates

• Supports reception of either 1.485 or 1.485/1.001 Gbps

data rate with the same training clock

• Internal phase-locked loops (PLLs) with no external

PLL components

• Supports half-rate and full-rate clocking

• Selectable differential PECL-compatible serial inputs

— Internal DC-restoration

The CYV15G0104TRB satisfies the SMPTE 259M and

SMPTE 292M compliance as per SMPTE EG34-1999 Patho-

logical Test Requirements.

second-generation

HOTLink

device,

the

CYV15G0104TRB extends the HOTLink family with enhanced

levels of integration and faster data rates, while maintaining

serial-link compatibility (data and BIST) with other HOTLink

devices. The transmit (TX) channel of the CYV15G0104TRB

HOTLink II device accepts scrambled 10-bit transmission

characters. These characters are serialized and output from

dual Positive ECL (PECL) compatible differential trans-

mission-line drivers at a bit-rate of either 10- or 20-times the

input reference clock for that channel.

• Redundant differential PECL-compatible serial outputs

— No external bias resistors required

— Internal source termination

— Signaling-rate controlled edge-rates

• Synchronous LVTTL parallel interface

• JTAG boundary scan

• Built-In Self-Test (BIST) for at-speed link testing

• Link Quality Indicator

The receive (RX) channel of the CYV15G0104TRB HOTLink

II device accepts a serial bit-stream from one of two selectable

PECL-compatible differential line receivers, and using a

completely integrated Clock and Data Recovery PLL, recovers

the timing information necessary for data reconstruction. The

recovered bit-stream is reclocked and retransmitted through

the reclocker serial outputs. Also, the recovered serial data is

deserialized and presented to the destination host system.

—Analog signal detect

—Digital signal detect

• Low-power 1.8W @ 3.3V typical

• Single 3.3V supply

• Thermally enhanced BGA

• Pb-Free package option available

• 0.25µ BiCMOS technology

The transmit and receive channels contain an independent

BIST pattern generator and checker, respectively. This BIST

hardware allows at-speed testing of the high-speed serial data

paths in each transmit and receive section, and across the

interconnecting links.

Functional Description

The CYV15G0104TRB Independent Clock HOTLink II™

Serializer and Reclocking Deserializer is a point-to-point or

point-to-multipoint communications building block enabling

Reclocked

Output

Independent

Channel

Independent

Channel

CYV15G0104TRB

Serial

Links

CYV15G0104TRB

Device

Reclocked

Output

Figure 1. HOTLink II™ System Connections

Cypress Semiconductor Corporation

Document #: 38-02100 Rev. *B

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Revised July 8, 2005

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CYV15G0104TRB

Reclocking Deserializer Path Block Diagram

RESET

TRST

JTAG

Boundary

Scan

TRGRATEA

TMS

TCLK

TDI

TRGCLKA

Controller

TDO

SDASEL[2..1]A[1:0]

LDTDEN

INSELA

LFIA

Receive

Signal

Monitor

RXDA[9:0]

BISTSTA

INA1+

INA1–

Clock &

Data

Recovery

PLL

INA2+

INA2–

RXCLKA+

RXCLKA–

÷2

ULCA

SPDSELA

RXBISTA[1:0]

RXRATEA

RXPLLPDA

Recovered Serial Data

Recovered Character Clock

ROE[2..1]A

ROUTA1+

ROUTA1–

Reclocker

Output PLL

Clock Multiplier

ROE[2..1]A

ROUTA2+

ROUTA2–

RECLKOA

REPDOA

Character-Rate Clock

Bit-Rate Clock

Serializer Path Block Diagram

Bit-Rate Clock

= Internal Signal

REFCLKB+

REFCLKB–

TXRATEB

Transmit PLL

Clock Multiplier

TOE[2..1]B

Transmit PLL

SPDSELB

TXCLKOB

Character-Rate Clock

PABRSTB

TXERRB

TXCLKB

TOE[2..1]B

TXBISTB

TXCKSELB

TOUTB1+

TOUTB1–

TXDB[9:0]

TOUTB2+

TOUTB2–

Device Configuration and Control Block Diagram

= Internal Signal

RXRATEA

RXPLLPDA

TRGRATEA

TXRATEB

TXCKSELB

PABRSTB

SDASEL[2..1]A[1:0]

TOE[2..1]B

ROE[2..1]A

RXBISTA[1:0]

TXBISTB

WREN

Device Configuration

ADDR[2:0]

and Control Interface

DATA[6:0]

Document #: 38-02100 Rev. *B

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CYV15G0104TRB

Pin Configuration (Top View)^[1]

TOUT

B1–

TOUT

B2–

A1–

ROUT

A1–

A2–

ROUT

A2–

GND GND

GND

TOUT

B1+

TOUT

B2+

A1+

ROUT

A1+

A2+

ROUT

A2+

GND

TDI

TMS

DATA

[6]

DATA

[4]

DATA

[2]

DATA

[0]

SPD

SELB

LDTD TRST

TDO

GND

TCLK RESET

INSELA

ULCA

DATA

[5]

DATA

[3]

DATA

[1]

SCAN TMEN3

EN2

GND GND GND

WREN

SPD

SELA

GND

GND GND

GND GND GND GND

GND GND

GND

GND GND GND GND

DB[0]

DB[1]

DB[2]

DB[9]

ADDR

[0]

REF

CLKB–

DA[4]

BIST

STA

DA[0]

GND GND

GND GND GND

DB[3]

DB[4]

DB[8]

REF

CLKB+ CLKOA

DA[9]

DA[5]

DA[2]

DA[1]

GND

GND GND

DB[5]

DB[7]

ADDR ADDR

CLKA+

REPDO

LFIA

TRG

CLKA+ DA[6]

DA[3]

GND GND

[2]

[1]

CLKOB

CLKA–

TRG

DA[7]

GND

DB[6] CLKB

ERRB CLKA– DA[8]

Note:

1. NC = Do not connect.

Document #: 38-02100 Rev. *B

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CYV15G0104TRB

Pin Configuration (Bottom View)^[1]

ROUT

A2–

ROUT

A1–

TOUT

B2–

TOUT

B1–

GND

GND GND

ROUT

A2+

ROUT

A1+

TOUT

B2+

TOUT

B1+

GND

TDO

TRST LDTD

SPD

SELB

DATA

[0]

DATA

[2]

DATA

[4]

DATA

[6]

TMS

TDI

GND

TMEN3 SCAN

EN2

DATA

[1]

DATA

[3]

DATA

[5]

ULCA

INSELA

RESET TCLK

GND GND GND

SPD

SELA

WREN

GND GND

GND

GND GND GND GND

GND GND

GND

GND GND GND GND

DA[0]

BIST

STA

DA[4]

REF

CLKB–

ADDR

[0]

DB[9]

DB[2]

DB[1]

DB[0]

GND GND GND

GND GND

DA[1]

DA[2]

DA[5]

DA[9]

REF

DB[8]

DB[4]

DB[3]

GND GND

GND

CLKOA CLKB+

DA[3]

TRG

LFIA

REPDO

CLKA+

ADDR ADDR

[1]

DB[7]

DB[5]

GND GND

DA[6] CLKA+

[2]

DA[7]

TRG

CLKA–

CLKOB

GND

DA[8] CLKA– ERRB

CLKB DB[6]

Document #: 38-02100 Rev. *B

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CYV15G0104TRB

Pin Definitions

CYV15G0104TRB HOTLink II Serializer and Reclocking Deserializer

Name

I/O Characteristics Signal Description

Transmit Path Data and Status Signals

TXDB[9:0]

TXERRB

LVTTL Input,

synchronous,

sampled by

TXCLKB↑ or

Transmit Data Inputs. TXDB[9:0] data inputs are captured on the rising edge of the

transmit interface clock. The transmit interface clock is selected by the TXCKSELB latch

via the device configuration interface.

[2]

REFCLKB↑

LVTTL Output,

Transmit Path Error. TXERRB is asserted HIGH to indicate detection of a transmit

Phase-Align Buffer underflow or overflow. If an underflow or overflow condition is

detected, TXERRB, is asserted HIGH and remains asserted until the transmit Phase-Align

Buffer is re-centered with the PABRSTB latch via the device configuration interface. When

TXBISTB = 0, the BIST progress is presented on the TXERRB output. The TXERRB

signal pulses HIGH for one transmit-character clock period to indicate a pass through the

synchronous to

[3]

REFCLKB↑

asynchronous to

transmit channel

enable / disable,

asynchronous to loss BIST sequence once every 511 character times.

or return of

TXERRB is also asserted HIGH, when any of the following conditions is true:

REFCLKB±

• The TXPLL is powered down. This occurs when TOE2B and TOE1B are both disabled

by setting TOE2B = 0 and TOE1B = 0.

• The absence of the REFCLKB± signal.

Transmit Path Clock Signals

REFCLKB±

Differential LVPECL Reference Clock. REFCLKB± clock inputs are used as the timing reference for the

or single-ended

transmit PLL. This input clock may also be selected to clock the transmit parallel interface.

When driven by a single-ended LVCMOS or LVTTL clock source, connect the clock source

to either the true or complement REFCLKB input, and leave the alternate REFCLKB input

open (floating). When driven by an LVPECL clock source, the clock must be a differential

clock, using both inputs.

LVTTL input clock

TXCLKB

LVTTL Clock Input,

internal pull-down

Transmit Path Input Clock. When configuration latch TXCKSELB = 0, the associated

TXCLKB input is selected as the character-rate input clock for the TXDB[9:0] input. In this

mode, the TXCLKB input must be frequency-coherent to its TXCLKOB output clock, but

may be offset in phase by any amount. Once initialized, TXCLKB is allowed to drift in

phase by as much as ±180 degrees. If the input phase of TXCLKB drifts beyond the

handling capacity of the Phase Align Buffer, TXERRB is asserted to indicate the loss of

data, and remains asserted until the Phase Align Buffer is initialized. The phase of

TXCLKB relative to REFCLKB± is initialized when the configuration latch PABRSTB is

written as 0. When TXERRB is deasserted, the Phase Align Buffer is initialized and input

characters are correctly captured.

TXCLKOB

LVTTL Output

Transmit Clock Output. TXCLKOB output clock is synthesized by the transmit PLL and

operates synchronous to the internal transmit character clock. TXCLKOB operates at

either the same frequency as REFCLKB± (TXRATEB = 0), or at twice the frequency of

REFCLKB± (TXRATEB = 1). The transmit clock outputs have no fixed phase relationship

to REFCLKB±.

Receive Path Data and Status Signals

RXDA[9:0]

LVTTL Output,

synchronous to the

RXCLKA ± output

Parallel Data Output. RXDA[9:0] parallel data outputs change relative to the receive

interface clock. If RXCLKA± is a full-rate clock, the RXCLKA± clock outputs are comple-

mentary clocks operating at the character rate. The RXDA[9:0] outputs for the associated

receive channels follow rising edge of RXCLKA+ or falling edge of RXCLKA–. If RXCLKA±

is a half-rate clock, the RXCLKA± clock outputs are complementary clocks operating at

half the character rate. The RXDA[9:0] outputs for the associated receive channels follow

both the falling and rising edges of the associated RXCLKA± clock outputs.

When BIST is enabled on the receive channel, the BIST status is presented on the

RXDA[1:0] and BISTSTA outputs. See Table 6 for each status reported by the BIST state

machine. Also, while BIST is enabled, the RXDA[9:2] outputs should be ignored.

Notes:

2. When REFCLKB± is configured for half-rate operation, these inputs are sampled relative to both the rising and falling edges of the associated REFCLKB±.

3. When REFCLKB± is configured for half-rate operation, this output is presented relative to both the rising and falling edges of the associated REFCLKB±.

Document #: 38-02100 Rev. *B

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CYV15G0104TRB

Pin Definitions (continued)

CYV15G0104TRB HOTLink II Serializer and Reclocking Deserializer

Name

I/O Characteristics Signal Description

BISTSTA

LVTTL Output,

synchronous to the

RXCLKA ± output

BIST Status Output. When RXBISTA[1:0] = 10, BISTSTA (along with RXDA[1:0])

displays the status of the BIST reception. See Table 6 for the BIST status reported for

each combination of BISTSTA and RXDA[1:0].

When RXBISTA[1:0] ≠ 10, BISTSTA should be ignored.

REPDOA

Asynchronous to

reclocker output

channel

Reclocker Powered Down Status Output. REPDOA is asserted HIGH, when the

reclocker output logic is powered down. This occurs when ROE2A and ROE1A are both

disabled by setting ROE2A = 0 and ROE1A = 0.

enable/disable

Receive Path Clock Signals

TRGCLKA± Differential LVPECL CDR PLL Training Clock. TRGCLKA± clock inputs are used as the reference source for

or single-ended

LVTTL input clock

the frequency detector (Range Controller) of the receive PLL to reduce PLL acquisition

time.

In the presence of valid serial data, the recovered clock output of the receive CDR PLL

(RXCLKA±) has no frequency or phase relationship with TRGCLKA±.

When driven by a single-ended LVCMOS or LVTTL clock source, connect the clock source

to either the true or complement TRGCLKA input, and leave the alternate TRGCLKA input

open (floating). When driven by an LVPECL clock source, the clock must be a differential

clock, using both inputs.

RXCLKA±

RECLKOA

LVTTL Output Clock Receive Clock Output. RXCLKA± is the receive interface clock used to control timing of

the RXDA[9:0] parallel outputs. These true and complement clocks are used to control

timing of data output transfers. These clocks are output continuously at either the half-

character rate (1/20 the serial bit-rate) or character rate (1/10 the serial bit-rate) of the

data being received, as selected by RXRATEA.

LVTTL Output

Reclocker Clock Output. RECLKOA output clock is synthesized by the reclocker output

PLL and operates synchronous to the internal recovered character clock. RECLKOA

operates at either the same frequency as RXCLKA± (RXRATEA = 0), or at twice the

frequency of RXCLKA± (RXRATEA = 1).The reclocker clock outputs have no fixed phase

relationship to RXCLKA±.

Device Control Signals

RESET

LVTTL Input,

asynchronous,

internal pull-up

Asynchronous Device Reset. RESET initializes all state machines, counters, and

configuration latches in the device to a known state. RESET must be asserted LOW for a

minimum pulse width. When the reset is removed, all state machines, counters and config-

uration latches are at an initial state. See Table 4 for the initialize values of the device

configuration latches.

LDTDEN

LVTTL Input,

internal pull-up

Level Detect Transition Density Enable. When LDTDEN is HIGH, the Signal Level

Detector, Range Controller, and Transition Density Detector are all enabled to determine

if the RXPLL tracks TRGCLKA± or the selected input serial data stream. If the Signal Level

Detector, Range Controller, or Transition Density Detector are out of their respective limits

while LDTDEN is HIGH, the RXPLL locks to TRGCLKA± until such a time they become

valid. SDASEL[2..1]A[1:0] is used to configure the trip level of the Signal Level Detector.

The Transition Density Detector limit is one transition in every 60 consecutive bits. When

LDTDEN is LOW, only the Range Controller is used to determine if the RXPLL tracks

TRGCLKA± or the selected input serial data stream. it is recommended to set LDTDEN

= HIGH.

ULCA

LVTTL Input,

internal pull-up

Use Local Clock. When ULCA is LOW, the RXPLL is forced to lock to TRGCLKA± instead

of the received serial data stream. While ULCA is LOW, the link fault indicator LFIA is

LOW indicating a link fault.

When ULCA is HIGH, the RXPLL performs Clock and Data Recovery functions on the

input data streams. This function is used in applications in which a stable RXCLKA± is

needed. In cases when there is an absence of valid data transitions for a long period of

time, or the high-gain differential serial inputs (INA±) are left floating, there may be brief

frequency excursions of the RXCLKA± outputs from TRGCLKA±.

Document #: 38-02100 Rev. *B

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CYV15G0104TRB

Pin Definitions (continued)

CYV15G0104TRB HOTLink II Serializer and Reclocking Deserializer

Name

I/O Characteristics Signal Description

[4]

SPDSELA

SPDSELB

3-Level Select

Serial Rate Select. The SPDSELA and SPDSELB inputs specify the operating signaling-

rate range of the receive and transmit PLL, respectively.

static control input

LOW = 195 – 400 MBd

MID = 400 – 800 MBd

HIGH = 800 – 1500 MBd.

INSELA

LFIA

LVTTL Input,

asynchronous

Receive Input Selector. The INSELA input determines which external serial bit stream

is passed to the receiver’s Clock and Data Recovery circuit. When INSELA is HIGH, the

Primary Differential Serial Data Input, INA1±, is selected for the receive channel. When

INSELA is LOW, the Secondary Differential Serial Data Input, INA2±, is selected for the

receive channel.

LVTTL Output,

asynchronous

Link Fault Indication Output. LFIA is an output status indicator signal. LFIA is the logical

OR of six internal conditions. LFIA is asserted LOW when any of the following conditions

is true:

• Received serial data rate outside expected range

• Analog amplitude below expected levels

• Transition density lower than expected

• Receive channel disabled

• ULCA is LOW

• Absence of TRGCLKA±.

Device Configuration and Control Bus Signals

WREN

LVTTL input,

asynchronous,

Control Write Enable. The WREN input writes the values of the DATA[6:0] bus into the

latch specified by the address location on the ADDR[2:0] bus.

[5]

internal pull-up

ADDR[2:0]

LVTTL input

asynchronous,

internal pull-up

Control Addressing Bus. The ADDR[2:0] bus is the input address bus used to configure

the device. The WREN input writes the values of the DATA[6:0] bus into the latch specified

[5]

by the address location on the ADDR[2:0] bus. Table 4 lists the configuration latches

within the device, and the initialization value of the latches upon the assertion of RESET.

Table 5 shows how the latches are mapped in the device.

DATA[6:0]

LVTTL input

asynchronous,

internal pull-up

Control Data Bus. The DATA[6:0] bus is the input data bus used to configure the device.

The WREN input writes the values of the DATA[6:0] bus into the latch specified by address

[5 ]

location on the ADDR[2:0] bus. Table 4 lists the configuration latches within the device,

and the initialization value of the latches upon the assertion of RESET. Table 5 shows how

the latches are mapped in the device.

Internal Device Configuration Latches

[6]

RXRATEA

Internal Latch

Receive Clock Rate Select.

[6]

SDASEL[2..1] Internal Latch

A[1:0]

Signal Detect Amplitude Select.

[6]

TXCKSELB Internal Latch

Transmit Clock Select.

TXRATEB

Internal Latch

Transmit PLL Clock Rate Select.

Reclocker Output PLL Clock Rate Select.

Receive Channel Power Control.

Receive Bist Disabled.

TRGRATEA Internal Latch

RXPLLPDA Internal Latch

RXBISTA[1:0] Internal Latch

TXBISTB

TOE2B

Internal Latch

Transmit Bist Disabled.

Transmitter Differential Serial Output Driver 2 Enable.

Transmitter Differential Serial Output Driver 1 Enable.

TOE1B

Notes:

4. 3-Level Select inputs are used for static configuration. These are ternary inputs that make use of logic levels of LOW, MID, and HIGH. The LOW level is usually

implemented by direct connection to V (ground). The HIGH level is usually implemented by direct connection to V (power). The MID level is usually

implemented by not connecting the input (left floating), which allows it to self bias to the proper level.

5. See Device Configuration and Control Interface for detailed information on the operation of the Configuration Interface.

6. See Device Configuration and Control Interface for detailed information on the internal latches.

Document #: 38-02100 Rev. *B

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CYV15G0104TRB

Pin Definitions (continued)

CYV15G0104TRB HOTLink II Serializer and Reclocking Deserializer

Name

I/O Characteristics Signal Description

[6]

ROE2A

ROE1A

PABRSTB

Internal Latch

Reclocker Differential Serial Output Driver 2 Enable.

[6]

Reclocker Differential Serial Output Driver 1 Enable.

Transmit Clock Phase Alignment Buffer Reset.

Factory Test Modes

SCANEN2

LVTTL input,

internal pull-down

Factory Test 2. SCANEN2 input is for factory testing only. This input may be left as a NO

CONNECT, or GND only.

TMEN3

LVTTL input,

internal pull-down

Factory Test 3. TMEN3 input is for factory testing only. This input may be left as a NO

CONNECT, or GND only.

Analog I/O

TOUTB1±

CML Differential

Output

Transmitter Primary Differential Serial Data Output. The transmitter TOUTB1± PECL-

compatible CML outputs (+3.3V referenced) are capable of driving terminated trans-

mission lines or standard fiber-optic transmitter modules, and must be AC-coupled for

PECL-compatible connections.

TOUTB2±

ROUTA1±

ROUTA2±

CML Differential

Output

Transmitter Secondary Differential Serial Data Output. The transmitter TOUTB2± PECL-

compatible CML outputs (+3.3V referenced) are capable of driving terminated transmission lines

or standard fiber-optic transmitter modules, and must be AC-coupled for PECL-compatible

connections.

CML Differential

Output

Reclocker Primary Differential Serial Data Output. The reclocker ROUTA1± PECL-

compatible CML outputs (+3.3V referenced) are capable of driving terminated trans-

mission lines or standard fiber-optic transmitter modules, and must be AC-coupled for

PECL-compatible connections.

CML Differential

Output

Reclocker Secondary Differential Serial Data Output. The reclocker ROUTA2± PECL-

compatible CML outputs (+3.3V referenced) are capable of driving terminated transmission lines

or standard fiber-optic transmitter modules, and must be AC-coupled for PECL-compatible

connections.

INA1±

INA2±

Differential Input

Primary Differential Serial Data Input. The INA1± input accepts the serial data stream

for deserialization. The INA1± serial stream is passed to the receive CDR circuit to extract

the data content when INSELA = HIGH.

Secondary Differential Serial Data Input. The INA2± input accepts the serial data

stream for deserialization. The INA2± serial stream is passed to the receiver CDR circuit

to extract the data content when INSELA = LOW.

JTAG Interface

TMS

LVTTL Input,

internal pull-up

Test Mode Select. Used to control access to the JTAG Test Modes. If maintained high for

≥5 TCLK cycles, the JTAG test controller is reset.

TCLK

LVTTL Input,

internal pull-down

JTAG Test Clock.

TDO

TDI

3-State LVTTL Output Test Data Out. JTAG data output buffer. High-Z while JTAG test mode is not selected.

LVTTL Input,

Test Data In. JTAG data input port.

internal pull-up

TRST

LVTTL Input,

internal pull-up

JTAG reset signal. When asserted (LOW), this input asynchronously resets the JTAG

test access port controller.

Power

+3.3V Power.

GND

Signal and Power Ground for all internal circuits.

CYV15G0104TRB HOTLink II Operation

CYV15G0104TRB Transmit Data Path

The CYV15G0104TRB is a highly configurable, independent

clocking device designed to support reliable transfer of large

quantities of digital video data, using high-speed serial links

from multiple sources to multiple destinations.

Input Register

The parallel input bus TXDB[9:0] can be clocked in using

TXCLKB (TXCKSELB = 0) or REFCLKB (TXCKSELB = 1).

Document #: 38-02100 Rev. *B

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CYV15G0104TRB

Phase-Align Buffer

Table 1. Operating Speed Settings

Data from the Input Register is passed to the Phase-Align

Buffer, when the TXDB[9:0] input register is clocked using

TXCLKBA (TXCKSELB = 0) or when REFCLKB is a half-rate

clock (TXCKSELB = 1 and TXRATEB = 1). When the

TXDB[9:0] input register is clocked using REFCLKB±

(TXCKSELA = 1) and REFCLKB± is a full-rate clock

(TXRATEB = 0), the associated Phase Alignment Buffer in the

transmit path is bypassed. These buffers are used to absorb

clock phase differences between the TXCLKB input clock and

the internal character clock for that channel.

REFCLKB±

Frequency

(MHz)

Signaling

SPDSELB

TXRATEB

Rate (Mbps)

LOW

reserved

19.5–40

20–40

195–400

400–800

800–1500

MID (Open)

HIGH

40–80

40–75

Once initialized, TXCLKB is allowed to drift in phase as much

as ±180 degrees. If the input phase of TXCLKB drifts beyond

the handling capacity of the Phase Align Buffer, TXERRB is

asserted to indicate the loss of data, and remains asserted

until the Phase Align Buffer is initialized. The phase of

TXCLKB relative to its internal character rate clock is initialized

when the configuration latch PABRSTB is written as 0. When

the associated TXERRB is deasserted, the Phase Align Buffer

is initialized and input characters are correctly captured.

80–150

The REFCLKB± inputs are differential inputs with each input

internally biased to 1.4V. If the REFCLKB+ input is connected

to a TTL, LVTTL, or LVCMOS clock source, the input signal is

recognized when it passes through the internally biased

reference point. When driven by a single-ended TTL, LVTTL,

or LVCMOS clock source, connect the clock source to either

the true or complement REFCLKB input, and leave the

alternate REFCLKB input open (floating).

If the phase offset, between the initialized location of the input

clock and REFCLKB, exceeds the skew handling capabilities

of the Phase-Align Buffer, an error is reported on that

channel’s TXERRB output. This output indicates an error

continuously until the Phase-Align Buffer for that channel is

reset. While the error remains active, the transmitter for that

channel outputs a continuous “1001111000” character to

indicate to the remote receiver that an error condition is

present in the link.

When both the REFCLKB+ and REFCLKB– inputs are

connected, the clock source must be a differential clock. This

can either be a differential LVPECL clock that is DC-or

AC-coupled or a differential LVTTL or LVCMOS clock.

By connecting the REFCLKB– input to an external voltage

source, it is possible to adjust the reference point of the

REFCLKB+ input for alternate logic levels. When doing so, it

is necessary to ensure that the input differential crossing point

remains within the parametric range supported by the input.

Transmit BIST

The transmit channel contains an internal pattern generator

that can be used to validate both the link and device operation.

This generator is enabled by the TXBISTB latch via the device

configuration interface. When enabled, a register in the

transmit channel becomes a signature pattern generator by

logically converting to a Linear Feedback Shift Register

(LFSR). This LFSR generates a 511-character sequence. This

provides a predictable yet pseudo-random sequence that can

be matched to an identical LFSR in the attached Receiver(s).

Transmit Serial Output Drivers

The serial output interface drivers use differential Current

Mode Logic (CML) drivers to provide source-matched drivers

for 50Ω transmission lines. These drivers accept data from the

transmit shifter. These drivers have signal swings equivalent

to that of standard PECL drivers, and are capable of driving

AC-coupled optical modules or transmission lines.

Transmit Channels Enabled

A device reset (RESET sampled LOW) presets the BIST

Enable Latches to disable BIST on all channels.

Each driver can be enabled or disabled separately via the

device configuration interface.

All data present at the TXDB[9:0] inputs are ignored when

BIST is active on that channel.

When a driver is disabled via the configuration interface, it is

internally powered down to reduce device power. If both

transmit serial drivers are in this disabled state, the transmitter

internal logic for that channel is also powered down. A device

reset (RESET sampled LOW) disables all output drivers.

Transmit PLL Clock Multiplier

The Transmit PLL Clock Multiplier accepts a character-rate or

half-character-rate external clock at the REFCLKB± input, and

that clock is multiplied by 10 or 20 (as selected by TXRATEB)

to generate a bit-rate clock for use by the transmit shifter. It

also provides a character-rate clock used by the transmit

paths, and outputs this character rate clock as TXCLKOB.

Note. When the disabled transmit channel (i.e., both outputs

disabled) is re-enabled:

• the data on the transmit serial outputs may not meet all

timing specifications for up to 250 µs

• the state of the phase-align buffer cannot be guaranteed,

and a phase-align reset is required if the phase-align buffer

is used

The clock multiplier PLL can accept a REFCLKB± input

between 19.5 MHz and 150 MHz, however, this clock range is

limited by the operating mode of the CYV15G0104TRB clock

multiplier (TXRATEB) and by the level on the SPDSELB input.

CYV15G0104TRB Receive Data Path

[4]

SPDSELB is a 3-level select input that selects one of three

operating ranges for the serial data outputs of the transmit

channel. The operating serial signaling-rate and allowable

range of REFCLKB± frequencies are listed in Table 1.

Serial Line Receivers

Two differential Line Receivers, INA1± and INA2±, are

available on the receive channel for accepting serial data

streams. The active Serial Line Receiver is selected using the

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INSELA input. The Serial Line Receiver inputs are differential,

and can accommodate wire interconnect and filtering losses

or transmission line attenuation greater than 16 dB. For

normal operation, these inputs should receive a signal of at

Range Controls

The CDR circuit includes logic to monitor the frequency of the

PLL Voltage Controlled Oscillator (VCO) used to sample the

incoming data stream. This logic ensures that the VCO

operates at, or near the rate of the incoming data stream for

two primary cases:

least VI

> 100 mV, or 200 mV peak-to-peak differential.

DIFF

Each Line Receiver can be DC- or AC-coupled to +3.3V

powered fiber-optic interface modules (any ECL/PECL family,

not limited to 100K PECL) or AC-coupled to +5V powered

optical modules. The common-mode tolerance of these line

receivers accommodates a wide range of signal termination

voltages. Each receiver provides internal DC-restoration, to

the center of the receiver’s common mode range, for AC-

coupled signals.

• when the incoming data stream resumes after a time in

which it has been “missing.”

• when the incoming data stream is outside the acceptable

signaling rate range.

To perform this function, the frequency of the RXPLL VCO is

periodically compared to the frequency of the TRGCLKA±

input. If the VCO is running at a frequency beyond

[24]

Signal Detect/Link Fault

±1500ppm

as defined by the TRGCLKA± frequency, it is

periodically forced to the correct frequency (as defined by

TRGCLKA±, SPDSELA, and TRGRATEA) and then released

in an attempt to lock to the input data stream.

Each selected Line Receiver (i.e., that routed to the clock and

data recovery PLL) is simultaneously monitored for

• analog amplitude above amplitude level selected by

SDASELA

• transition density above the specified limit

The sampling and relock period of the Range Control is calcu-

lated as follows: RANGE_CONTROL_ SAMPLING_PERIOD

= (RECOVERED BYTE CLOCK PERIOD) * (4096).

• range controls report the received data stream inside

[24]

normal frequency range (±1500 ppm

• receive channel enabled

)

During the time that the Range Control forces the RXPLL VCO

to track TRGCLKA±, the LFIA output is asserted LOW. After a

valid serial data stream is applied, it may take up to one

RANGE CONTROL SAMPLING PERIOD before the PLL

locks to the input data stream, after which LFIA should be

HIGH.

• Presence of reference clock

• ULCA is not asserted.

All of these conditions must be valid for the Signal Detect block

to indicate a valid signal is present. This status is presented on

the LFIA (Link Fault Indicator) output associated with each

receive channel, which changes synchronous to the receive

interface clock.

The operating serial signaling-rate and allowable range of

TRGCLKA± frequencies are listed in Table 3.

Table 3. Operating Speed Settings

TRGCLKA±

Analog Amplitude

Frequency

(MHz)

Signaling

While most signal monitors are based on fixed constants, the

analog amplitude level detection is adjustable to allow

operation with highly attenuated signals, or in high-noise

environments. The analog amplitude level detection is set by

the SDASELA latch via device configuration interface. The

SDASELA latch sets the trip point for the detection of a valid

signal at one of three levels, as listed in Table 2. This control

input affects the analog monitors for all receive channels. The

Analog Signal Detect monitors are active for the Line Receiver

as selected by the INSELA input.

SPDSELA TRGRATEA

Rate (Mbps)

LOW

MID (Open)

HIGH

reserved

19.5–40

20–40

195–400

400–800

800–1500

40–80

40–75

80–150

[7]

Receive Channel Enabled

Table 2. Analog Amplitude Detect Valid Signal Levels

The receive channel can be enabled or disabled through the

RXPLLPDA input latch as controlled by the device configu-

ration interface. When RXPLLPDA = 0, the CDR PLL and

analog circuitry of the channel are disabled. Any disabled

channel indicates a constant link fault condition on the LFIA

output. When RXPLLPDA = 1, the CDR PLL and receive

channel are enabled to receive a serial stream.

Typical Signal with Peak Amplitudes

SDASELA

Above

Analog Signal Detector is disabled

140 mV p-p differential

280 mV p-p differential

420 mV p-p differential

Note. When the disabled receive channel is reenabled, the

status of the LFIA output and data on the parallel outputs for

the associated channel may be indeterminate for up to 2 ms.

Transition Density

The Transition Detection logic checks for the absence of

transitions spanning greater than six transmission characters

Clock/Data Recovery

(60 bits). If no transitions are present in the data received, the

Detection logic for that channel asserts LFIA.

The extraction of a bit-rate clock and recovery of bits from the

received serial stream is performed by a separate CDR block

within the receive channel. The clock extraction function is

Note:

7. The peak amplitudes listed in this table are for typical waveforms that have generally 3–4 transitions for every ten bits. In a worse case environment the signals

may have a sine-wave appearance (highest transition density with repeating 0101...). Signal peak amplitudes levels within this environment type could increase

the values in the table above by approximately 100 mV.

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performed by an integrated PLL that tracks the frequency of

the transitions in the incoming bit stream and aligns the phase

of the internal bit-rate clock to the transitions in the selected

serial data stream.

When a driver is disabled via the configuration interface, it is

internally powered down to reduce device power. If both

reclocker serial drivers are in this disabled state, the internal

reclocker logic is also powered down. The deserialization logic

and parallel outputs will remain enabled. A device reset

(RESET sampled LOW) disables all output drivers.

Each CDR accepts a character-rate (bit-rate ÷ 10) or half-

character-rate (bit-rate ÷ 20) training clock from the

TRGCLKA± input. This TRGCLKA± input is used to

Note. When the disabled reclocker function (i.e., both outputs

disabled) is re-enabled, the data on the reclocker serial

outputs may not meet all timing specifications for up to 250 µs.

• ensure that the VCO (within the CDR) is operating at the

correct frequency (rather than a harmonic of the bit-rate)

• reduce PLL acquisition time

Output Bus

• limit unlocked frequency excursions of the CDR VCO when

there is no input data present at the selected Serial Line

Receiver.

The receive channel presents a 10-bit data signal (and a BIST

status signal when RXBISTA[1:0] = 10).

Regardless of the type of signal present, the CDR attempts to

recover a data stream from it. If the signaling rate of the

recovered data stream is outside the limits set by the range

control monitors, the CDR tracks TRGCLKA± instead of the

data stream. Once the CDR output (RXCLKA±) frequency

returns back close to the TRGCLKA± frequency, the CDR

input is switched back to the input data stream. If no data is

present at the selected line receiver, this switching behavior

may result in brief RXCLKA± frequency excursions from

TRGCLKA±. However, the validity of the input data stream is

Receive BIST Operation

The receiver channel contains an internal pattern checker that

can be used to validate both device and link operation. These

pattern checkers are enabled by the RXBISTA[1:0] latch via

the device configuration interface. When enabled, a register in

the receive channel becomes a signature pattern generator

and checker by logically converting to a Linear Feedback Shift

sequence. This provides a predictable yet pseudo-random

sequence that can be matched to an identical LFSR in the

attached Transmitter(s). When synchronized with the received

data stream, the Receiver checks each character from the

deserializer with each character generated by the LFSR and

indicates compare errors and BIST status at the RXDA[1:0]

and BISTSTA bits of the Output Register.

indicated by the LFIA output. The frequency of TRGCLKA± is

[24]

required to be within ±1500ppm

of the frequency of the

clock that drives the REFCLKB± input of the remote trans-

mitter to ensure a lock to the incoming data stream. This large

ppm tolerance allows the CDR PLL to reliably receive a 1.485

or 1.485/1.001 Gbps SMPTE HD-SDI data stream with a

constant TRGCLK frequency.

The BIST status bus {BISTSTA, RXDA[0], RXDA[1]} indicates

010b or 100b for one character period per BIST loop to

indicate loop completion. This status can be used to check test

pattern progress.

For systems using multiple or redundant connections, the

LFIA output can be used to select an alternate data stream.

When an LFIA indication is detected, external logic can toggle

selection of the INA1± and INA2± input through the INSELA

input. When a port switch takes place, it is necessary for the

receive PLL for that channel to reacquire the new serial

stream.

The specific status reported by the BIST state machine is listed

in Table 6. These same codes are reported on the receive

status outputs.

If the number of invalid characters received ever exceeds the

number of valid characters by 16, the receive BIST state

machine aborts the compare operations and resets the LFSR

to look for the start of the BIST sequence again.

Reclocker

The receive channel performs a reclocker function on the

incoming serial data. To do this, the Clock and Data Recovery

PLL first recovers the clock from the data. The data is retimed

by the recovered clock and then passed to an output register.

Also, the recovered character clock from the receive PLL is

passed to the reclocker output PLL which generates the bit

clock that is used to clock the retimed data into the output

differential serial outputs.

A device reset (RESET sampled LOW) presets the BIST

Enable Latches to disable BIST on all channels.

BIST Status State Machine

When a receive path is enabled to look for and compare the

received data stream with the BIST pattern, the {BISTSTA,

RXDA[1:0]} bits identify the present state of the BIST compare

operation.

Reclocker Serial Output Drivers

The BIST state machine has multiple states, as shown in

Figure 2 and Table 6. When the receive PLL detects an out-of-

lock condition, the BIST state is forced to the Start-of-BIST

state, regardless of the present state of the BIST state

machine. If the number of detected errors ever exceeds the

number of valid matches by greater than 16, the state machine

is forced to the WAIT_FOR_BIST state where it monitors the

receive path for the first character of the next BIST sequence.

The serial output interface drivers use differential Current

Mode Logic (CML) drivers to provide source-matched drivers

for 50Ω transmission lines. These drivers accept data from the

reclocker output register in the reclocker channel. These

drivers have signal swings equivalent to that of standard PECL

drivers, and are capable of driving AC-coupled optical

modules or transmission lines.

Power Control

Reclocker Output Channels Enabled

Each driver can be enabled or disabled separately via the

device configuration interface.

The CYV15G0104TRB supports user control of the powered

up or down state of each transmit and receive channel. The

receive channels are controlled by the RXPLLPDA latch via

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the device configuration interface. When RXPLLPDA = 0, the

receive PLL and analog circuitry of the channel is disabled.

The transmit channel is controlled by the TOE1B and the

TOE2B latches via the device configuration interface. The

reclocker function is controlled by the ROE1A and the ROE2A

latches via the device configuration interface. When a driver is

disabled via the configuration interface, it is internally powered

down to reduce device power. If both serial drivers for a

channel are in this disabled state, the associated internal logic

for that channel is also powered down. When the reclocker

serial drivers are disabled, the reclocker function will be

disabled, but the deserialization logic and parallel outputs will

remain enabled.

initialization value of the latches upon the assertion of RESET.

Table 5 shows how the latches are mapped in the device.

Each row in the Table 5 maps to a 7-bit latch bank. There are

6 such write-only latch banks. When WREN = 0, the logic value

in the DATA[6:0] is latched to the latch bank specified by the

values in ADDR[2:0]. The second column of Table 5 specifies

the channels associated with the corresponding latch bank.

For example, the first three latch banks (0,1 and 2) consist of

configuration bits for the reclocker channel A.

Latch Types

There are two types of latch banks: static (S) and dynamic (D).

Each channel is configured by 2 static and 1 dynamic latch

banks. The S type contain those settings that normally do not

change for a given application, whereas the D type controls

the settings that could change during the application's lifetime.

The first and second rows of each channel (address numbers

0, 1, 5, and 6) are the static control latches. The third row of

latches for each channel (address numbers 2 and 7) are the

dynamic control latches that are associated with enabling

dynamic functions within the device. Address numbers 3 and

4 are internal test registers.

Device Reset State

When the CYV15G0104TRB is reset by assertion of RESET,

all state machines, counters, and configuration latches in the

device are initialized to a reset state. See Table 4 for the

initialize values of the configuration latches.

Following a device reset, it is necessary to enable the transmit

and receive channels used for normal operation. This can be

done by sequencing the appropriate values on the device

[5]

configuration interface.

Static Latch Values

There are some latches in the table that have a static value

(i.e. 1, 0, or X). The latches that have a ‘1’ or ‘0’ must be

configured with their corresponding value each time that their

associated latch bank is configured. The latches that have an

‘X’ are don’t cares and can be configured with any value.

Device Configuration and Control Interface

The CYV15G0104TRB is highly configurable via the configu-

ration interface. The configuration interface allows the trans-

mitter and reclocker to be configured independently. Table 4

lists the configuration latches within the device including the

Table 4. Device Configuration and Control Latch Descriptions

Name

Signal Description

RXRATEA

Receive Clock Rate Select. The initialization value of the RXRATEA latch = 1. RXRATEA is used to select

the rate of the RXCLKA± clock output.

When RXRATEA = 1, the RXCLKA± clock outputs are complementary clocks that follow the recovered clock

operating at half the character rate. Data for the associated receive channels should be latched alternately on

the rising edge of RXCLKA+ and RXCLKA–.

When RXRATEA = 0, the RXCLKA± clock outputs are complementary clocks that follow the recovered clock

operating at the character rate. Data for the associated receive channels should be latched on the rising edge

of RXCLKA+ or falling edge of RXCLKA–.

SDASEL1A[1:0] Primary Serial Data Input Signal Detector Amplitude Select. The initialization value of the SDASEL1A[1:0]

latch = 10. SDASEL1A[1:0] selects the trip point for the detection of a valid signal for the INA1± Primary

Differential Serial Data Inputs.

When SDASEL1A[1:0] = 00, the Analog Signal Detector is disabled.

When SDASEL1A[1:0] = 01, the typical p-p differential voltage threshold level is 140 mV.

When SDASEL1A[1:0] = 10, the typical p-p differential voltage threshold level is 280 mV.

When SDASEL1A[1:0] = 11, the typical p-p differential voltage threshold level is 420 mV.

SDASEL2A[1:0] Secondary Serial Data Input Signal Detector Amplitude Select. The initialization value of the

SDASEL2A[1:0] latch = 10. SDASEL2A[1:0] selects the trip point for the detection of a valid signal for the

INA2± Secondary Differential Serial Data Inputs.

When SDASEL2A[1:0] = 00, the Analog Signal Detector is disabled

When SDASEL2A[1:0] = 01, the typical p-p differential voltage threshold level is 140 mV.

When SDASEL2A[1:0] = 10, the typical p-p differential voltage threshold level is 280 mV.

When SDASEL2A[1:0] = 11, the typical p-p differential voltage threshold level is 420 mV.

TRGRATEA

Training Clock Rate Select. The initialization value of the TRGRATEA latch = 0. TRGRATEA is used to select

the clock multiplier for the training clock input to the CDR PLL. When TRGRATEA = 0, the TRGCLKA± input

is not multiplied before it is passed to the CDR PLL. When TRGRATEA = 1, the TRGCLKA± input is multiplied

by 2 before it is passed to the CDR PLL. TRGRATEA = 1 and SPDSELA = LOW is an invalid state and this

combination is reserved.

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Table 4. Device Configuration and Control Latch Descriptions (continued)

Name

Signal Description

RXPLLPDA

Receive Channel Enable. The initialization value of the RXPLLPDA latch = 0. RXPLLPDA selects if the

receive channel is enabled or powered-down. When RXPLLPDA = 0, the receive PLL and analog circuitry are

powered-down. When RXPLLPDA = 1, the receive PLL and analog circuitry are enabled.

RXBISTA[1:0]

ROE2A

Receive Bist Disable / SMPTE Receive Enable. The initialization value of the RXBISTA[1:0] latch = 11. For

SMPTE data reception, RXBISTA[1:0] should not remain in this initialization state (11). RXBISTA[1:0] selects

if receive BIST is disabled or enabled and sets the device for SMPTE data reception. When RXBISTA[1:0] =

01, the receiver BIST function is disabled and the device is set to receive SMPTE data. When RXBISTA[1:0]

= 10, the receive BIST function is enabled and the device is set to receive BIST data. RXBISTA[1:0] = 00 and

RXBISTA[1:0] = 11 are invalid states.

Reclocker Secondary Differential Serial Data Output Driver Enable. The initialization value of the ROE2A

latch = 0. ROE2A selects if the ROUTA2± secondary differential output drivers are enabled or disabled. When

ROE2A = 1, the associated serial data output driver is enabled allowing the reclocked data to be transmitted.

When ROE2A = 0, the associated serial data output driver is disabled. When a driver is disabled via the

configuration interface, it is internally powered down to reduce device power. If both serial drivers for a channel

are in this disabled state, the reclocker logic is also powered down. A device reset (RESET sampled LOW)

disables all output drivers.

ROE1A

Reclocker Primary Differential Serial Data Output Driver Enable. The initialization value of the ROE1A

latch = 0. ROE1A selects if the ROUTA1± primary differential output drivers are enabled or disabled. When

ROE1A = 1, the associated serial data output driver is enabled allowing the reclocked data to be transmitted.

When ROE1A = 0, the associated serial data output driver is disabled. When a driver is disabled via the

configuration interface, it is internally powered down to reduce device power. If both serial drivers for a channel

are in this disabled state, the reclocker logic is also powered down. A device reset (RESET sampled LOW)

disables all output drivers.

TXCKSELB

TXRATEB

Transmit Clock Select. The initialization value of the TXCKSELB latch = 1. TXCKSELB selects the clock

source used to write data into the Transmit Input Register. When TXCKSELB = 1, the input register TXDB[9:0]

is clocked by REFCLKB↑. In this mode, the phase alignment buffer in the transmit path is bypassed. When

TXCKSELB = 0, TXCLKB↑ is used to clock in the input register TXDB[9:0].

Transmit PLL Clock Rate Select. The initialization value of the TXRATEB latch = 0. TXRATEB is used to

select the clock multiplier for the Transmit PLL. When TXRATEB = 0, the transmit PLL multiples the REFCLKB±

input by 10 to generate the serial bit-rate clock. When TXRATEB = 0, the TXCLKOB output clocks are full-rate

clocks and follow the frequency and duty cycle of the REFCLKB± input. When TXRATEB = 1, the Transmit

PLL multiplies the REFCLKB± input by 20 to generate the serial bit-rate clock. When TXRATEB = 1, the

TXCLKOB output clocks are twice the frequency rate of the REFCLKB± input. When TXCKSELB = 1 and

TXRATEB = 1, the Transmit Data Inputs are captured using both the rising and falling edges of REFCLKB.

TXRATEB = 1 and SPDSELB = LOW, is an invalid state and this combination is reserved.

TXBISTB

TOE2B

Transmit Bist Disable. The initialization value of the TXBISTB latch = 1. TXBISTB selects if the transmit BIST

is disabled or enabled. When TXBISTB = 1, the transmit BIST function is disabled. When TXBISTB = 0, the

transmit BIST function is enabled.

Secondary Differential Serial Data Output Driver Enable. The initialization value of the TOE2B latch = 0.

TOE2B selects if the TOUTB2± secondary differential output drivers are enabled or disabled. When TOE2B

= 1, the associated serial data output driver is enabled allowing data to be transmitted from the transmit shifter.

When TOE2B = 0, the associated serial data output driver is disabled. When a driver is disabled via the

configuration interface, it is internally powered down to reduce device power. If both serial drivers for a channel

are in this disabled state, the associated internal logic for that channel is also powered down. A device reset

(RESET sampled LOW) disables all output drivers.

TOE1B

Primary Differential Serial Data Output Driver Enable. The initialization value of the TOE1B latch = 0.

TOE1B selects if the TOUTB1± primary differential output drivers are enabled or disabled. When TOE1B = 1,

the associated serial data output driver is enabled allowing data to be transmitted from the transmit shifter.

When TOE1B = 0, the associated serial data output driver is disabled. When a driver is disabled via the

configuration interface, it is internally powered down to reduce device power. If both serial drivers for a channel

are in this disabled state, the associated internal logic for that channel is also powered down. A device reset

(RESET sampled LOW) disables all output drivers.

PABRSTB

Transmit Clock Phase Alignment Buffer Reset. The initialization value of the PABRSTB latch = 1. The

PABRSTB is used to re-center the Transmit Phase Align Buffer. When the configuration latch PABRSTB is

written as a 0, the phase of the TXCLKB input clock relative to REFCLKB+/- is initialized. PABRSTB is an

asynchronous input, but is sampled by each TXCLKB↑ to synchronize it to the internal clock domain.

PABRSTB is a self clearing latch. This eliminates the requirement of writing a 1 to complete the initialization

of the Phase Alignment Buffer.

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Table 5. Device Control Latch Configuration Table

Reset

Value

ADDR Channel Type

DATA6

DATA5

DATA4

DATA3

DATA2

DATA1

DATA0

RXRATEA

1011111

(000b)

SDASEL2A[1]

RXBISTA[1]

SDASEL2A[0]

RXPLLPDA

SDASEL1A[1]

RXBISTA[0]

SDASEL1A[0]

TRGRATEA

1010110

1011001

(001b)

ROE2A

ROE1A

(010b)

INTERNAL TEST REGISTERS

(011b)

DO NOT WRITE TO THESE ADDRESSES

(100b)

1011111

1010110

1011001

(101b)

TXCKSELB

TOE1B

TXRATEB

PABRSTB

(110b)

TXBISTB

TOE2B

(111b)

Device Configuration Strategy

JTAG Support

The following is a series of ordered events needed to load the

configuration latches on a per channel basis:

The CYV15G0104TRB contains a JTAG port to allow system

level diagnosis of device interconnect. Of the available JTAG

modes, boundary scan, and bypass are supported. This

capability is present only on the LVTTL inputs and outputs, the

TRGCLKA± input, and the REFCLKB± clock input. The high-

speed serial inputs and outputs are not part of the JTAG test

chain.

1. Pulse RESET Low after device power-up. This operation

resets both channels.

2. Set the static latch banks for the target channel.

3. Set the dynamic bank of latches for the target channel.

Enable the Receive PLL and/or transmit channel. If the

receiver is enabled, set the device for SMPTE data

reception (RXBISTA[1:0] = 01) or BIST data reception

(RXBISTA[1:0] = 10).

3-Level Select Inputs

Each 3-Level select inputs reports as two bits in the scan

the associated input as 00, 10, and 11 respectively

4. Reset the Phase Alignment Buffer. [Optional if phase align

buffer is bypassed.]

JTAG ID

The JTAG device ID for the CYV15G0104TRB is ‘0C811069’x.

Table 6. Receive BIST Status Bits

{BISTSTA, RXDA[0], RXDA[1]}

Description

Receive BIST Status

(Receive BIST = Enabled)

000, 001

010

BIST Data Compare. Character compared correctly.

BIST Last Good. Last Character of BIST sequence detected and valid.

011

Reserved.

100

BIST Last Bad. Last Character of BIST sequence detected invalid.

101

BIST Start. Receive BIST is enabled on this channel, but character compares have not yet

commenced. This also indicates a PLL Out of Lock condition.

110

111

BIST Error. While comparing characters, a mismatch was found in one or more of the

character bits.

BIST Wait. The receiver is comparing characters but has not yet found the start of BIST

character to enable the LFSR.

Document #: 38-02100 Rev. *B

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CYV15G0104TRB

Monitor Data

Received

Receive BIST

Detected LOW

{BISTSTA, RXDA[0],

RXDA[1]} =

BIST_START (101)

RX PLL

Out of Lock

{BISTSTA, RXDA[0], RXDA[1]} =

BIST_WAIT (111)

Start of

BIST Detected

Yes, {BISTSTA, RXDA[0], RXDA[1]} =

BIST_DATA_COMPARE (000, 001)

Compare

Next Character

Mismatch

{BISTSTA, RXDA[0], RXDA[1]} =

BIST_DATA_COMPARE (000, 001)

Match

Auto-Abort

Condition

Yes

End-of-BIST

State

End-of-BIST

State

Yes, {BISTSTA, RXDA[0], RXDA[1]} =

BIST_LAST_BAD (100)

Yes, {BISTSTA, RXDA[0], RXDA[1]} =

BIST_LAST_GOOD (010)

No, {BISTSTA, RXDA[0], RXDA[1]} =

BIST_ERROR (110)

Figure 2. Receive BIST State Machine

Document #: 38-02100 Rev. *B

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CYV15G0104TRB

Static Discharge Voltage..........................................> 2000 V

(per MIL-STD-883, Method 3015)

Maximum Ratings

(Above which the useful life may be impaired. User guidelines

only, not tested.)

Latch-up Current.....................................................> 200 mA

Power-up Requirements

Storage Temperature ..................................–65°C to +150°C

The CYV15G0104TRB requires one power supply. The

Voltage on any input or I/O pin cannot exceed the power pin

during power-up.

Ambient Temperature with

Power Applied.............................................–55°C to +125°C

Supply Voltage to Ground Potential............... –0.5V to +3.8V

DC Voltage Applied to LVTTL Outputs

in High-Z State .......................................–0.5V to V + 0.5V

Operating Range

Range

Ambient Temperature

Output Current into LVTTL Outputs (LOW)..................60 mA

Commercial

0°C to +70°C

+3.3V ±5%

DC Input Voltage....................................–0.5V to V + 0.5V

CYV15G0104TRB DC Electrical Characteristics

Parameter

Description

Test Conditions

Min.

Max.

Unit

LVTTL-compatible Outputs

Output HIGH Voltage

Output LOW Voltage

= − 4 mA, V = Min.

2.4

OHT

OLT

= 4 mA, V = Min.

0.4

–100

[8]

Output Short Circuit Current

= 0V , V = 3.3V

–20

µA

OST

OZL

OUT

High-Z Output Leakage Current

= 0V, V

LVTTL-compatible Inputs

Input HIGH Voltage

Input LOW Voltage

Input HIGH Current

2.0

+ 0.3

IHT

ILT

–0.5

0.8

1.5

REFCLKB Input, V = V

µA

IHT

Other Inputs, V = V

+40

–1.5

–40

Input LOW Current

REFCLKB Input, V = 0.0V

ILT

Other Inputs, V = 0.0V

Input HIGH Current with internal pull-down

Input LOW Current with internal pull-up

= V

+200

–200

IHPDT

ILPUT

= 0.0V

LVDIFF Inputs: REFCLKB±

[9]

Input Differential Voltage

Highest Input HIGH Voltage

Lowest Input LOW voltage

Common Mode Range

400

1.2

0.0

1.0

DIFF

IHHP

ILLP

[10]

– 1.2V

COMREF

3-Level Inputs

Three-Level Input HIGH Voltage

Min. ≤ V ≤ Max.

0.87 * V

0.47 * V

0.0

IHH

IMM

ILL

Three-Level Input MID Voltage

Three-Level Input LOW Voltage

Input HIGH Current

Min. ≤ V ≤ Max.

0.53 * V

0.13 * V

200

Min. ≤ V ≤ Max.

= V

µA

IHH

Input MID current

= V /2

–50

IMM

ILL

Input LOW current

= GND

–200

Differential CML Serial Outputs: OUTA1±, OUTA2±, OUTB1±, OUTB2±, OUTC1±, OUTC2±, OUTD1±, OUTD2±

Output HIGH Voltage

(V Referenced)

100Ω differential load

150Ω differential load

– 0.5

– 0.2

OHC

Notes:

8. Tested one output at a time, output shorted for less than one second, less than 10% duty cycle.

9. This is the minimum difference in voltage between the true and complement inputs required to ensure detection of a logic-1 or logic-0. A logic-1 exists when

the true (+) input is more positive than the complement (−) input. A logic-0 exists when the complement (−) input is more positive than true (+) input.

10. The common mode range defines the allowable range of REFCLKB+ and REFCLKB− when REFCLKB+ = REFCLKB−. This marks the zero-crossing between

the true and complement inputs as the signal switches between a logic-1 and a logic-0.

Document #: 38-02100 Rev. *B

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CYV15G0104TRB

CYV15G0104TRB DC Electrical Characteristics (continued)

Parameter

Description

Output LOW Voltage

Test Conditions

100Ω differential load

150Ω differential load

100Ω differential load

150Ω differential load

Min.

Max.

Unit

– 1.4

– 0.7

OLC

(V Referenced)

– 1.4

– 0.7

Output Differential Voltage

|(OUT+) − (OUT−)|

450

900

ODIF

560

100

1000

Differential Serial Line Receiver Inputs: INA1±, INA2±

[9]

Input Differential Voltage |(IN+) − (IN−)|

Highest Input HIGH Voltage

Lowest Input LOW Voltage

Input HIGH Current

1200

DIFFs

IHE

– 2.0

ILE

= V Max.

IHE

1350

+3.1

µA

IHE

Input LOW Current

= V Min.

–700

ILE

[11]

Common Mode input range

((V – 2.0V)+0.5)min,

+1.25

COM

(V – 0.5V) max.

Power Supply

Typ.

Max.

[12, 13]

Max Power Supply Current

REFCLKB Commercial

= MAX

585

690

[12, 13]

Typical Power Supply Current

REFCLKB Commercial

= 125 MHz

560

660

AC Test Loads and Waveforms

3.3V

R_L= 100Ω

R1 = 590Ω

R2 = 435Ω

C_L≤ 7 pF

(Includes fixture and

probe capacitance)

(Includes fixture and

probe capacitance)

C_L

[14]

(b) CML Output Test Load

[14]

(a) LVTTL Output Test Load

V_IHE

3.0V

V_IHE

2.0V

0.8V

2.0V

0.8V

80%

V_th= 1.4V

20%

V_ILE

≤ 270 ps

GND

V_ILE

≤ 270 ps

≤ 1 ns

[15]

(d) CML/LVPECL Input Test Waveform

CYV15G0104TRB AC Electrical Characteristics

Parameter

Description

Min.

Max

Unit

CYV15G0104TRB Transmitter LVTTL Switching Characteristics Over the Operating Range

TXCLKB Clock Cycle Frequency

TXCLKB Period=1/f

19.5

6.66

2.2

150

MHz

51.28

TXCLK

TXCLKH

[16]

TXCLKB HIGH Time

TXCLKB LOW Time

2.2

TXCLKL

Notes:

11. The common mode range defines the allowable range of INPUT+ and INPUT− when INPUT+ = INPUT−. This marks the zero-crossing between the true and

complement inputs as the signal switches between a logic-1 and a logic-0.

12. Maximum I is measured with V = MAX,T = 25°C, with all channels and Serial Line Drivers enabled, sending a continuous alternating 01 pattern, and

outputs unloaded.

13. Typical I is measured under similar conditions except with V = 3.3V, T = 25°C,with all channels enabled and one Serial Line Driver per channel sending

a continuous alternating 01 pattern. The redundant outputs on each channel are powered down and the parallel outputs are unloaded.

14. Cypress uses constant current (ATE) load configurations and forcing functions. This figure is for reference only.

15. The LVTTL switching threshold is 1.4V. All timing references are made relative to where the signal edges cross the threshold voltage.

16. Tested initially and after any design or process changes that may affect these parameters, but not 100% tested.

Document #: 38-02100 Rev. *B

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CYV15G0104TRB

CYV15G0104TRB AC Electrical Characteristics (continued)

Parameter

Description

Min.

0.2

Max

1.7

Unit

[16, 17, 18, 19]

TXCLKB Rise Time

TXCLKB Fall Time

TXCLKR

TXCLKF

TXDS

[16, 17, 18, 19]

0.2

1.7

Transmit Data Set-up Time to TXCLKB↑ (TXCKSELB = 0)

Transmit Data Hold Time from TXCLKB↑ (TXCKSELB = 0)

TXCLKOB Clock Frequency = 1x or 2x REFCLKB Frequency

2.2

1.0

TXDH

19.5

6.66

–1.9

150

51.28

MHz

TOS

TXCLKOB Period=1/f

TXCLKO

TOS

TXCLKOB Duty Cycle centered at 60% HIGH time

TXCLKOD

CYV15G0104TRB Receiver LVTTL Switching Characteristics Over the Operating Range

RXCLKA± Clock Output Frequency

RXCLKA± Period = 1/f

9.75

6.66

150

102.56

+1.0

1.2

MHz

RXCLKP

RXCLKD

RXCLKR

RXCLKA± Duty Cycle Centered at 50% (Full Rate and Half Rate)

RXCLKA± Rise Time

–1.0

[16]

0.3

RXCLKA± Fall Time

0.3

1.2

RXCLKF

[20]

[21]

Status and Data Valid Time to RXCLKA± (RXRATEA = 0) (Full Rate)

Status and Data Valid Time to RXCLKA± (RXRATEA = 1) (Half Rate)

Status and Data Valid Time to RXCLKA± (RXRATEA = 0)

Status and Data Valid Time to RXCLKA± (RXRATEA = 1)

RECLKOA Clock Frequency

5UI–2.0

5UI–1.3

5UI–1.8

5UI–2.6

19.5

RXDv–

RXDv+

ROS

[20]

150

51.28

MHz

RECLKOA Period=1/f

6.66

RECLKO

ROS

RECLKOA Duty Cycle centered at 60% HIGH time

-1.9

RECLKOD

CYV15G0104TRB REFCLKB Switching Characteristics Over the Operating Range

REFCLKB Clock Frequency

REFCLKB Period = 1/f

19.5

6.6

150

MHz

REF

51.28

REFCLK

REFH

REF

REFCLKB HIGH Time (TXRATEB = 1)(Half Rate)

REFCLKB HIGH Time (TXRATEB = 0)(Full Rate)

REFCLKB LOW Time (TXRATEB = 1)(Half Rate)

REFCLKB LOW Time (TXRATEB = 0)(Full Rate)

REFCLKB Duty Cycle

5.9

[16]

2.9

5.9

REFL

[16]

2.9

[22]

REFD

[16, 17, 18, 19]

REFCLKB Rise Time (20%–80%)

REFR

REFF

[16, 17, 18, 19]

REFCLKB Fall Time (20%–80%)

Transmit Data Set-up Time to REFCLKB - Full Rate

(TXRATEB = 0, TXCKSELB = 1)

2.4

2.3

1.0

1.6

TREFDS

TREFDH

Transmit Data Set-up Time to REFCLKB - Half Rate

(TXRATEB = 1, TXCKSELB = 1)

Transmit Data Hold Time from REFCLKB - Full Rate

(TXRATEB= 0, TXCKSELB = 1)

Transmit Data Hold Time from REFCLKB - Half Rate

(TXRATEB = 1, TXCKSELB = 1)

CYV15G0104TRB TRGCLKA Switching Characteristics Over the Operating Range

TRGCLKA Clock Frequency

TRGCLKA Period = 1/f

19.5

6.6

150

MHz

TRG

51.28

REFCLK

TRG

Notes:

17. The ratio of rise time to falling time must not vary by greater than 2:1.

18. For a given operating frequency, neither rise or fall specification can be greater than 20% of the clock-cycle period or the data sheet maximum time.

19. All transmit AC timing parameters measured with 1ns typical rise time and fall time.

20. Parallel data output specifications are only valid if all outputs are loaded with similar DC and AC loads.

21. Receiver UI (Unit Interval) is calculated as 1/(f

* 20) (when TRGRATEA = 1) or 1/(f

* 10) (when TRGRATEA = 0). In an operating link this is equivalent to t .

TRG

22. The duty cycle specification is a simultaneous condition with the t

and t

parameters. This means that at faster character rates the REFCLKB± duty

REFH

REFL

cycle cannot be as large as 30%–70%.

Document #: 38-02100 Rev. *B

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CYV15G0104TRB AC Electrical Characteristics (continued)

Parameter

Description

TRGCLKA HIGH Time (TRGRATEA = 1)(Half Rate)

TRGCLKA HIGH Time (TRGRATEA = 0)(Full Rate)

TRGCLKA LOW Time (TRGRATEA = 1)(Half Rate)

TRGCLKA LOW Time (TRGRATEA = 0)(Full Rate)

TRGCLKA Duty Cycle

Min.

Max

Unit

5.9

TRGH

[16]

2.9

5.9

TRGL

[16]

2.9

[23]

TRGD

TRGR

TRGF

[16, 17, 18]

[24]

TRGCLKA Rise Time (20%–80%)

TRGCLKA Fall Time (20%–80%)

TRGCLKA Frequency Referenced to Received Clock Frequency

–0.15

+0.15

TRGRX

CYV15G0104TRB Bus Configuration Write Timing Characteristics Over the Operating Range

Bus Configuration Data Hold

DATAH

DATAS

WRENP

Bus Configuration Data Setup

Bus Configuration WREN Pulse Width

CYV15G0104TRB JTAG Test Clock Characteristics Over the Operating Range

JTAG Test Clock Frequency

JTAG Test Clock Period

MHz

TCLK

CYV15G0104TRB Device RESET Characteristics Over the Operating Range

Device RESET Pulse Width

RST

CYV15G0104TRB Transmitter and Reclocker Serial Output Characteristics Over the Operating Range

Parameter

Description

Condition

Min.

660

Max.

5128

270

Unit

Bit Time

[16]

CML Output Rise Time 20−80% (CML Test Load)

SPDSELx = HIGH

SPDSELx= MID

SPDSELx =LOW

SPDSELx = HIGH

SPDSELx = MID

SPDSELx =LOW

RISE

100

180

500

1000

270

[16]

CML Output Fall Time 80−20% (CML Test Load)

FALL

100

180

500

1000

PLL Characteristics

Parameter

Description

Condition

Min. Typ.

Max. Unit

CYV15G0104TRB Transmitter Output PLL Characteristics

[16, 25]

Transmit Jitter Generation - SD Data Rate

Transmit Jitter Generation - HD Data Rate

Transmit PLL lock to REFCLKB±

REFCLKB = 27 MHz

200

JTGENSD

JTGENHD

TXLOCK

[16, 25]

REFCLKB = 148.5 MHz

200

µs

CYV15G0104TRB Reclocker Output PLL Characteristics

[16, 26]

Reclocker Jitter Generation - SD Data Rate

Reclocker Jitter Generation - HD Data Rate

TRGCLKA = 27 MHz

133

107

JRGENSD

[16, 26]

TRGCLKA = 148.5 MHz

JRGENHD

Notes:

23. The duty cycle specification is a simultaneous condition with the t

and t

parameters. This means that at faster character rates the TRGCLKA± duty

TRGL

TRGH

cycle cannot be as large as 30%–70%.

24. TRGCLKA± has no phase or frequency relationship with the recovered clock(s) and only acts as a centering reference to reduce clock synchronization time.

TRGCLKA± must be within ±1500 PPM (±0.15%) of the transmitter PLL reference (REFCLK±) frequency. Although transmitting to a HOTLink II receiver channel

necessitates the frequency difference between the transmitter and receiver reference clocks to be within ±1500-PPM, the stability of the crystal needs to be

within the limits specified by the appropriate standard when transmitting to a remote receiver that is compliant to that standard.

25. While sending BIST data at the corresponding data rate, after 10,000 histogram hits, time referenced to REFCLKB± input.

26. Receiver input stream is BIST data from the transmit channel. This data is reclocked and output to a wide-bandwidth digital sampling oscilloscope. The

measurement was recorded after 10,000 histogram hits, time referenced to REFCLKB± of the transmit channel.

Document #: 38-02100 Rev. *B

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CYV15G0104TRB

PLL Characteristics

Parameter

Description

Condition

Min. Typ.

Max. Unit

CYV15G0104TRB Receive PLL Characteristics Over the Operating Range

Receive PLL lock to input data stream (cold start)

Receive PLL lock to input data stream

Receive PLL Unlock Rate

376k

RXLOCK

RXUNLOCK

Capacitance ^[16]

Parameter

Description

Test Conditions

T = 25°C, f = 1 MHz, V = 3.3V

Max.

Unit

TTL Input Capacitance

PECL input Capacitance

INTTL

T = 25°C, f = 1 MHz, V = 3.3V

INPECL

CYV15G0104TRB HOTLink II Transmitter Switching Waveforms

TXCLK

Transmit Interface

Write Timing

TXCLKB selected

TXCLKL

TXCLKH

TXCLKB

TXDH

TXDS

TXDB[9:0]

Transmit Interface

Write Timing

REFCLKB selected

TXRATEB = 0

REFCLK

REFL

REFH

REFCLKB

TREFDS

TREFDH

TXDB[9:0]

Transmit Interface

Write Timing

REFCLKB selected

TXRATEB = 1

REFCLK

REFL

REFH

REFCLKB

Note 27

TREFDS

TREFDH

TREFDS

TREFDH

TXDB[9:0]

Note:

27. When REFCLKB± is configured for half-rate operation (TXRATEB = 1) and data is captured using REFCLKB instead of a TXCLKB clock. Data is captured using

both the rising and falling edges of REFCLKB.

Document #: 38-02100 Rev. *B

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CYV15G0104TRB

CYV15G0104TRB HOTLink II Transmitter Switching Waveforms (continued)

Transmit Interface

TXCLKOB Timing

t_REFCLK

t_REFH

t_REFL

TXRATE = 1

REFCLKB

Note 28

t_TXCLKO

Note 29

TXCLKOB

(internal)

Transmit Interface

TXCLKOB Timing

REFCLK

REFH

REFL

TXRATEB = 0

Note28

REFCLKB

TXCLKO

Note29

TXCLKOB

Switching Waveforms for the CYV15G0104TRB HOTLink II Receiver

Receive Interface

Read Timing

RXRATEA = 0

RXCLKP

RXCLKA+

RXCLKA–

RXDV

–

RXDA[9:0]

RXDV+

Notes:

28. The TXCLKOB output remains at the character rate regardless of the state of TXRATEB and does not follow the duty cycle of REFCLKB±.

29. The rising edge of TXCLKOB output has no direct phase relationship to the REFCLKB± input.

Document #: 38-02100 Rev. *B

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Switching Waveforms for the CYV15G0104TRB HOTLink II Receiver

Receive Interface

Read Timing

RXRATEA = 1

RXCLKP

RXCLKA+

RXCLKA–

RXDV

–

RXDA[9:0]

RXDV+

Bus Configuration

Write Timing

ADDR[2:0]

DATA[6:0]

WREN

WRENP

DATAS

DATAH

Document #: 38-02100 Rev. *B

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CYV15G0104TRB

Table 7. Package Coordinate Signal Allocation

Ball

Signal Name

Signal Type

NO CONNECT

POWER

Signal Name

Signal Type

NO CONNECT

GROUND

Signal Name

VCC

Signal Type

POWER

A01

A02

A03

A04

A05

A06

A07

A08

A09

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

B01

B02

B03

B04

B05

B06

B07

B08

B09

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

C01

C02

C03

C07

C08

C09

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

C20

D01

D02

D03

D04

D05

D06

D07

D08

D09

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

D20

E01

E02

E03

E04

E17

E18

E19

E20

F01

F17

F18

F19

F20

G01

G02

G03

G04

G17

G18

G19

G20

H01

H02

H03

H04

H17

H18

H19

H20

J01

J02

J03

J04

J17

J18

J19

J20

K01

K02

K03

K04

K17

K18

K19

K20

L01

L02

L03

L04

L17

L18

L19

GND

NO CONNECT

GROUND

DATA[6]

DATA[4]

DATA[2]

DATA[0]

GND

LVTTL IN PU

GROUND

VCC

GND

WREN

GND

NO CONNECT

CML OUT

LVTTL IN PU

GROUND

TOUTB1–

GND

GROUND

NO CONNECT

3-LEVEL SEL

POWER

GROUND

GND

GROUND

SPDSELB

VCC

NO CONNECT

3-LEVEL SEL

NO CONNECT

GROUND

TOUTB2–

INA1–

ROUTA1–

GND

CML OUT

CML IN

LDTDEN

TRST

GND

LVTTL IN PU

GROUND

SPDSELA

CML OUT

GROUND

GND

INA2–

ROUTA2–

VCC

CML IN

TDO

LVTTL 3-S OUT

LVTTL IN PD

LVTTL IN PU

POWER

GROUND

CML OUT

TCLK

RESET

VCC

GROUND

POWER

GROUND

VCC

POWER

GROUND

NO CONNECT

POWER

INSELA

VCC

LVTTL IN

GROUND

VCC

POWER

GROUND

NO CONNECT

POWER

ULCA

LVTTL IN PU

NO CONNECT

GROUND

VCC

GROUND

NO CONNECT

POWER

GND

GROUND

VCC

DATA[5]

DATA[3]

DATA[1]

GND

LVTTL IN PU

GROUND

NO CONNECT

POWER

GROUND

VCC

NO CONNECT

GROUND

VCC

POWER

TOUTB1+

GND

CML OUT

GND

GROUND

GND

GROUND

NO CONNECT

CML OUT

NO CONNECT

POWER

TOUTB2+

INA1+

ROUTA1+

GND

VCC

CML IN

NO CONNECT

POWER

GND

CML OUT

VCC

GROUND

SCANEN2

TMEN3

VCC

LVTTL IN PD

POWER

NO CONNECT

GROUND

INA2+

ROUTA2+

VCC

CML IN

CML OUT

POWER

VCC

POWER

NO CONNECT

LVTTL IN PU

POWER

VCC

POWER

VCC

POWER

VCC

POWER

VCC

POWER

GND

TDI

VCC

POWER

NO CONNECT

TMS

VCC

POWER

VCC

NO CONNECT

Document #: 38-02100 Rev. *B

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CYV15G0104TRB

Table 7. Package Coordinate Signal Allocation (continued)

Ball

Signal Name

VCC

Signal Type

POWER

Signal Name

Signal Type

NO CONNECT

POWER

Signal Name

GND

Signal Type

GROUND

C04

C05

C06

M03

M04

M17

M18

M19

M20

N01

N02

N03

N04

N17

N18

N19

N20

P01

P02

P03

P04

P17

P18

P19

P20

R01

R02

R03

R04

R17

R18

R19

R20

T01

T02

T03

T04

T17

T18

T19

T20

U01

U02

F02

F03

F04

U03

U04

U05

U06

U07

U08

U09

U10

U11

U12

U13

U14

U15

U16

U17

U18

U19

U20

V01

V02

V03

V04

V05

V06

V07

V08

V09

V10

V11

V12

V13

V14

V15

V16

V17

V18

V19

V20

W01

W02

L20

M01

M02

W03

W04

W05

W06

W07

W08

W09

W10

W11

W12

W13

W14

W15

W16

W17

POWER

VCC

NO CONNECT

POWER

NO CONNECT

GROUND

NO CONNECT

LVTTL IN

TXDB[2]

TXDB[9]

VCC

LVTTL IN

POWER

VCC

NO CONNECT

GROUND

NO CONNECT

GROUND

GND

GROUND

GND

GROUND

ADDR [2]

ADDR [1]

RXCLKA+

REPDOA

GND

LVTTL IN PU

LVTTL OUT

GROUND

ADDR [0]

REFCLKB–

GND

LVTTL IN PU

PECL IN

GROUND

GND

GROUND

GND

GROUND

GND

GROUND

VCC

POWER

VCC

POWER

GROUND

VCC

POWER

VCC

POWER

NO CONNECT

GROUND

RXDA[4]

VCC

LVTTL OUT

POWER

LFIA

LVTTL OUT

PECL IN

W18 TRGCLKA+

BISTSTA

RXDA[0]

TXDB[3]

TXDB[4]

TXDB[8]

LVTTL OUT

LVTTL IN

W19

W20

Y01

Y02

Y03

Y04

Y05

Y06

Y07

Y08

Y09

Y10

Y11

Y12

Y13

Y14

Y15

Y16

Y17

RXDA[6]

RXDA[3]

TXDB[6]

TXCLKB

LVTTL OUT

LVTTL IN

GND

GROUND

LVTTL IN

LVTTL IN PD

NO CONNECT

POWER

GROUND

LVTTL IN

GROUND

NO CONNECT

POWER

NO CONNECT

POWER

VCC

NO CONNECT

GROUND

NO CONNECT

GROUND

GND

VCC

TXDB[0]

TXDB[1]

NO CONNECT

GROUND

TXCLKOB

LVTTL OUT

NO CONNECT

GROUND

POWER

GND

POWER

REFCLKB+

RECLKOA

GND

PECL IN

GND

POWER

LVTTL OUT

GROUND

RXCLKA–

GND

LVTTL OUT

GROUND

POWER

GND

GROUND

GND

GROUND

POWER

VCC

POWER

VCC

POWER

VCC

POWER

VCC

POWER

RXDA[9]

RXDA[5]

RXDA[2]

RXDA[1]

TXDB[5]

TXDB[7]

LVTTL OUT

LVTTL IN

TXERRB

LVTTL OUT

PECL IN

POWER

Y18 TRGCLKA–

POWER

Y19

Y20

RXDA[8]

RXDA[7]

LVTTL OUT

POWER

LVTTL IN

Document #: 38-02100 Rev. *B

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CYV15G0104TRB

Ordering Information

Package

Name

Operating

Range

Speed

Standard

Ordering Code

Package Type

CYV15G0104TRB-BGC

CYV15G0104TRB-BGXC

BL256

256-Ball Thermally Enhanced Ball Grid Array

Commercial

Pb-Free 256-Ball Thermally Enhanced Ball Grid Array

Package Diagram

256-Lead L2 Ball Grid Array (27 x 27 x 1.57 mm) BL256

51-85123-*E

HOTLink is a registered trademark and HOTLink II is a trademark of Cypress Semiconductor. All product and company names

mentioned in this document may be the trademarks of their respective holders.

Document #: 38-02100 Rev. *B

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CYV15G0104TRB

Document History Page

Document Title: CYV15G0104TRB Independent Clock HOTLink II™ Serializer and Reclocking Deserializer

Document Number: 38-02100

ISSUE

DATE

ORIG. OF

CHANGE

REV.

ECN NO.

244348

338721

384307

DESCRIPTION OF CHANGE

See ECN

FRE

SUA

AGT

New Data Sheet

Added Pb-Free package option availability

Revised setup and hold times (t , t

, t

)

TXDH TREFDS TREFDH RXDv– RXDv+

Document #: 38-02100 Rev. *B

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