Philips S1D13505 User Manual

S1D13505 Embedded RAMDAC LCD/CRT Controller

S1D13505

TECHNICAL MANUAL

Document Number: X23A-Q-001-12

Information in this document is subject to change without notice. You may download and use this document, but only for your own use in

evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any

representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain

material protected under U.S. and/or International Patent laws.

EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.

Epson Research and Development

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Vancouver Design Center

Customer Support Information

Comprehensive Support Tools

Seiko Epson Corp. provides to the system designer and computer OEM manufacturer a complete set

of resources and tools for the development of graphics systems.

Evaluation / Demonstration Board

• Assembled and fully tested graphics evaluation board with installation guide and schematics.

• To borrow an evaluation board, please contact your local Seiko Epson Corp. sales representative.

Chip Documentation

• Technical manual includes Data Sheet, Application Notes, and Programmer’s Reference.

Software

• OEM Utilities.

• User Utilities.

• Evaluation Software.

• To obtain these programs, contact Application Engineering Support.

Application Engineering Support

Engineering and Sales Support is provided by:

Japan

North America

Taiwan

Epson Taiwan Technology

& Trading Ltd.

Seiko Epson Corporation

Electronic Devices Marketing Division

421-8, Hino, Hino-shi

Tokyo 191-8501, Japan

Tel: 042-587-5812

Epson Electronics America, Inc.

150 River Oaks Parkway

San Jose, CA 95134, USA

Tel: (408) 922-0200

Fax: (408) 922-0238

http://www.eea.epson.com

10F, No. 287

Nanking East Road

Sec. 3, Taipei, Taiwan

Tel: 02-2717-7360

Fax: 02-2712-9164

Fax: 042-587-5564

http://www.epson.co.jp

Singapore

Europe

Hong Kong

Epson Singapore Pte., Ltd.

No. 1

Temasek Avenue #36-00

Millenia Tower

Singapore, 039192

Tel: 337-7911

Fax: 334-2716

Epson Europe Electronics GmbH

Riesstrasse 15

80992 Munich, Germany

Tel: 089-14005-0

Epson Hong Kong Ltd.

20/F., Harbour Centre

25 Harbour Road

Wanchai, Hong Kong

Tel: 2585-4600

Fax: 089-14005-110

Fax: 2827-4346

TECHNICAL MANUAL

Issue Date: 01/04/18

S1D13505

X23A-Q-001-12

Page 4

Epson Research and Development

Vancouver Design Center

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S1D13505

X23A-Q-001-12

TECHNICAL MANUAL

Issue Date: 01/04/18

ENERGY

SAVING

EPSON

GRAPHICS

S1D13505

S1D13505 EMBEDDED RAMDAC LCD/CRT CONTROLLER

October 2001

■ DESCRIPTION

The S1D13505 is a color/monochrome LCD/CRT graphics controller interfacing to a wide range of CPUs and display

devices. The S1D13505 architecture is designed to meet the low cost, low power requirements of the embedded

markets, such as Mobile Communications, Hand-Held PCs, and Office Automation.

The S1D13505 supports multiple CPUs, all LCD panel types, CRT, and additionally provides a number of

differentiating features. Products requiring a “Portrait” mode display can take advantage of the SwivelView feature.

Simultaneous, Virtual and Split Screen Display are just some of the display modes supported, while the Hardware

Cursor, Ink Layer, and the Memory Enhancement Registers offer substantial performance benefits. These features,

combined with the S1D13505’s Operating System independence, make it an ideal display solution for a wide variety

of applications.

Display Modes

■ FEATURES

• ^{1/2/4/8/16 bit-per-pixel (bpp) support on LCD/CRT.}

• ^{Up to 16 shades of gray using FRM on monochrome}

passive LCD panels.

Memory Interface

• ^{16-bit EDO-DRAM or FPM-DRAM interface.}

• ^{Memory size options:}

• ^{Up to 4096 colors on passive LCD panels.}

• ^{Up to 64K colors on active matrix TFT/D-TFD LCD}

panels and CRT in 16 bpp modes.

512K bytes using one 256K×16 device.

2M bytes using one 1M×16 device.

• ^{Addressable as a single linear address space.}

CPU Interface

• ^{Split Screen Display: allows two different images to be}

simultaneously viewed on the same display.

• ^{Supports the following interfaces:}

• ^{Virtual Display Support: displays images larger than the}

display size through the use of panning.

Hitachi SH-4.

Hitachi SH-3.

Motorola M68K.

• ^{Double Buffering/multi-pages: provides smooth}

Philips MIPS PR31500/PR31700.

Toshiba MIPS TX3912.

Motorola Power PC MPC821.

NEC MIPS VR4102/VR4111.

Epson E0C33.

PC Card (PCMCIA).

StrongARM (PC Card).

ISA bus.

animation and instantaneous screen update.

• ^{SwivelView: direct hardware 90° rotation of}

display image for portrait mode display.

• ^{Acceleration of screen updates by allocating full}

display memory bandwidth to CPU.

• ^{Hardware 64x64 pixel 2-bit cursor or full screen}

2-bit ink layer.

Clock Source

MPU bus interface with programmable READY.

• ^{Single clock input for both pixel and memory clocks.}

• ^{Memory clock can be input clock or (input clock/2),}

providing flexibility to use CPU bus clock as input.

• ^{CPU write buffer.}

Display Support

• ^{4/8-bit monochrome passive LCD interface.}

• ^{Pixel clock can be memory clock or (memory clock/2) or}

(memory clock/3) or (memory clock/4).

• ^{4/8/16-bit color passive LCD interface.}

• ^{Single-panel, single-drive displays.}

• ^{Dual-panel, dual-drive displays.}

• ^{Direct support for 9/12-bit TFT/D-TFD; 18-bit TFT/D-TFD}

is supported up to 64K color depth (16-bit data).

Power Down Modes

• ^{Software power save mode.}

• ^{LCD power sequencing.}

General Purpose IO Pins

• ^{Embedded RAMDAC with direct analog CRT drive.}

• ^{Simultaneous display of CRT and passive or TFT/D-TFD}

panels.

• ^{Up to 3 General Purpose IO pins are available.}

Operating Voltage

• 2.7 volts to 5.5 volts.

Package

• Maximum resolution of 800x600 pixels at a color

depth of 16 bpp.

• ^{128-pin QFP15 surface mount package.}

X23A-C-002-15

GRAPHICS

S1D13505

■ SYSTEM BLOCK DIAGRAM

EDO-DRAM

FPM-DRAM

Analog Out

Digital Out

Data and

CPU

S1D13505

Control Signals

CRT

Flat Panel

CONTACT YOUR SALES REPRESENTATIVE FOR THESE COMPREHENSIVE DESIGN TOOLS

• S1D13505 Technical

Manual

• Linux Console Driver

• S5U13505 Evaluation Boards • Windows CE Display Driver

• CPU Independent Software

Utilities

• VXWorks Tornado^TMDisplay

Driver

Japan

North America

Taiwan

Seiko Epson Corporation

Electronic Devices Marketing Division

421-8, Hino, Hino-shi

Tokyo 191-8501, Japan

Tel: 042-587-5812

Epson Electronics America, Inc.

150 River Oaks Parkway

San Jose, CA 95134, USA

Tel: (408) 922-0200

Epson Taiwan Technology & Trading Ltd.

10F, No. 287

Nanking East Road

Sec. 3, Taipei, Taiwan

Tel: 02-2717-7360

Fax: (408) 922-0238

Fax: 042-587-5564

http://www.epson.co.jp/

http://www.eea.epson.com/

Fax: 02-2712-9164

http://www.epson.com.tw/

Singapore

Europe

Hong Kong

Epson Singapore Pte., Ltd.

No. 1

Temasek Avenue #36-00

Millenia Tower

Singapore, 039192

Tel: 337-7911

Epson Europe Electronics GmbH

Riesstrasse 15

80992 Munich, Germany

Tel: 089-14005-0

Fax: 089-14005-110

http://www.epson-electronics.de/

Epson Hong Kong Ltd.

20/F., Harbour Centre

25 Harbour Road

Wanchai, Hong Kong

Tel: 2585-4600

Fax: 2827-4346

Fax: 334-2716

http://www.epson.com.hk/

http://www.epson.com.sg/

Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/

EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any representation that the contents of this document are

accurate or current. The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws.

EPSON is a registered trademark of Seiko Epson Corporation. Microsoft, Windows, and the Windows Embedded Partner Logo are registered trademarks of Mi-

crosoft Corporation. All other trademarks are the property of their respective owners.

X23A-C-002-15

S1D13505 Embedded RAMDAC LCD/CRT Controller

Hardware Functional Specification

Document Number: X23A-A-001-14

Information in this document is subject to change without notice. You may download and use this document, but only for your own use in

evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any

representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain

material protected under U.S. and/or International Patent laws.

EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.

Page 2

Epson Research and Development

Vancouver Design Center

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S1D13505

X23A-A-001-14

Hardware Functional Specification

Issue Date: 01/02/02

Epson Research and Development

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Vancouver Design Center

Table of Contents

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

1.1 Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

1.2 Overview Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.1 Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.2 CPU Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.3 Display Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.4 Display Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.5 Display Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.6 Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.7 Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Typical System Implementation Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Internal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.1 Block Diagram Showing Datapaths . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.2 Block Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.2.1

4.2.2

4.2.3

4.2.4

4.2.5

4.2.6

4.2.7

4.2.8

4.2.9

Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

CPU R/W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Display FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Cursor FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Look-Up Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

CRTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

LCD Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.2.10 DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.2.11 Power Save . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.2.12 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

5.1 Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

5.2 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.2.1

5.2.2

5.2.3

5.2.4

5.2.5

Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

LCD Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

CRT Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

5.3 Summary of Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . 33

5.4 Multiple Function Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

5.5 CRT Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

D.C. Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

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A.C. Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

7.1 CPU Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

7.1.1

7.1.2

7.1.3

7.1.4

7.1.5

7.1.6

7.1.7

7.1.8

7.1.9

SH-4 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

SH-3 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

MC68K Bus 1 Interface Timing (e.g. MC68000) . . . . . . . . . . . . . . . . . . . . . . . .46

MC68K Bus 2 Interface Timing (e.g. MC68030) . . . . . . . . . . . . . . . . . . . . . . . .48

PC Card Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

Generic Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

MIPS/ISA Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

Philips Interface Timing (e.g. PR31500/PR31700) . . . . . . . . . . . . . . . . . . . . . . .56

Toshiba Interface Timing (e.g. TX3912) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

7.1.10 Power PC Interface Timing (e.g. MPC8xx, MC68040, Coldfire) . . . . . . . . . . . . . . . .60

7.2 Clock Input Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

7.3 Memory Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

7.3.1

7.3.2

7.3.3

7.3.4

7.3.5

7.3.6

EDO-DRAM Read/Write/Read-Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . .63

EDO-DRAM CAS Before RAS Refresh Timing . . . . . . . . . . . . . . . . . . . . . . . .66

EDO-DRAM Self-Refresh Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

FPM-DRAM Read/Write/Read-Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . .69

FPM-DRAM CAS Before RAS Refresh Timing . . . . . . . . . . . . . . . . . . . . . . . .72

FPM-DRAM Self-Refresh Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

7.4 Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

7.4.1

7.4.2

LCD Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74

Power Save Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75

7.5 Display Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

7.5.1

7.5.2

7.5.3

7.5.4

7.5.5

7.5.6

7.5.7

7.5.8

7.5.9

4-Bit Single Monochrome Passive LCD Panel Timing . . . . . . . . . . . . . . . . . . . . .76

8-Bit Single Monochrome Passive LCD Panel Timing . . . . . . . . . . . . . . . . . . . . .78

4-Bit Single Color Passive LCD Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . .80

8-Bit Single Color Passive LCD Panel Timing (Format 1) . . . . . . . . . . . . . . . . . . .82

8-Bit Single Color Passive LCD Panel Timing (Format 2) . . . . . . . . . . . . . . . . . . .84

16-Bit Single Color Passive LCD Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . .86

8-Bit Dual Monochrome Passive LCD Panel Timing . . . . . . . . . . . . . . . . . . . . . .88

8-Bit Dual Color Passive LCD Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . .90

16-Bit Dual Color Passive LCD Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . .92

7.5.10 16-Bit TFT/D-TFD Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94

7.5.11 CRT Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97

Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

8.1 Register Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

8.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

8.2.1

8.2.2

8.2.3

8.2.4

Revision Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99

Memory Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Panel/Monitor Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Display Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

S1D13505

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Hardware Functional Specification

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Epson Research and Development

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8.2.5

8.2.6

8.2.7

8.2.8

8.2.9

Clock Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Power Save Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Miscellaneous Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Look-Up Table Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Ink/Cursor Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Display Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122

9.1 Image Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123

9.2 Ink/Cursor Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123

9.3 Half Frame Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123

10 Display Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124

10.1 Display Mode Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124

10.2 Image Manipulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126

11 Look-Up Table Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127

11.1 Monochrome Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127

11.2 Color Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129

12 Ink/Cursor Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133

12.1 Ink/Cursor Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133

12.2 Ink/Cursor Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133

12.3 Ink/Cursor Image Manipulation . . . . . . . . . . . . . . . . . . . . . . . . . . .134

12.3.1 Ink Image . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

12.3.2 Cursor Image . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

13 SwivelView™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135

13.1 Concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135

13.2 Image Manipulation in SwivelView . . . . . . . . . . . . . . . . . . . . . . . . . .136

13.3 Physical Memory Requirement . . . . . . . . . . . . . . . . . . . . . . . . . . .137

13.4 Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138

14 Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139

14.1 Maximum MCLK: PCLK Ratios . . . . . . . . . . . . . . . . . . . . . . . . . . .139

14.2 Frame Rate Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141

14.3 Bandwidth Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143

15 Power Save Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147

16 Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148

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Epson Research and Development

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List of Tables

Table 5-1: Host Interface Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 5-2: Memory Interface Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 5-2: LCD Interface Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 5-3: CRT Interface Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 5-4: Miscellaneous Interface Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 5-5: Summary of Power On/Reset Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 5-6: CPU Interface Pin Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 5-7: Memory Interface Pin Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 5-8: LCD Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 6-1: Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 6-2: Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 6-3: Electrical Characteristics for VDD = 5.0V typical . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 6-4: Electrical Characteristics for VDD = 3.3V typical . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 6-5: Electrical Characteristics for VDD = 3.0V typical . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 7-1: SH-4 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 7-2: SH-3 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 7-3: MC68000 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 7-4: MC68030 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 7-5: PC Card Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 7-6: Generic Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 7-7: MIPS/ISA Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 7-8: Philips Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 7-9: Clock Input Requirements for BUSCLK using Philips local bus. . . . . . . . . . . . . . . . . . . 57

Table 7-10: Toshiba Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 7-11: Clock Input Requirements for BUSCLK using Toshiba local bus . . . . . . . . . . . . . . . . . . 59

Table 7-12: Power PC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Table 7-13: Clock Input Requirements for CLKI divided down internally (MCLK = CLKI/2) . . . . . . . . . 62

Table 7-14: Clock Input Requirements for CLKI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Table 7-15: EDO-DRAM Read/Write/Read-Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Table 7-16: EDO-DRAM CAS Before RAS Refresh Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 7-17: EDO-DRAM Self-Refresh Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Table 7-18: FPM-DRAM Read/Write/Read-Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Table 7-19: FPM-DRAM CAS Before RAS Refresh Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Table 7-20: FPM-DRAM CBR Self-Refresh Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Table 7-21: LCD Panel Power Off/ Power On. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Table 7-22: Power Save Status and Local Bus Memory Access Relative to Power Save Mode . . . . . . . . . 75

Table 7-23: 4-Bit Single Monochrome Passive LCD Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . 77

Table 7-24: 8-Bit Single Monochrome Passive LCD Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . 79

Table 7-25: 4-Bit Single Color Passive LCD Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . 81

Table 7-26: 8-Bit Single Color Passive LCD Panel A.C. Timing (Format 1) . . . . . . . . . . . . . . . . . . . 83

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Table 7-27: 8-Bit Single Color Passive LCD Panel A.C. Timing (Format 2) . . . . . . . . . . . . . . . . . . .85

Table 7-28: 16-Bit Single Color Passive LCD Panel A.C. Timing. . . . . . . . . . . . . . . . . . . . . . . . .87

Table 7-29: 8-Bit Dual Monochrome Passive LCD Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . .89

Table 7-30: 8-Bit Dual Color Passive LCD Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . .91

Table 7-31: 16-Bit Dual Color Passive LCD Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . .93

Table 7-32: TFT/D-TFD A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96

Table 8-1: S1D13505 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99

Table 8-2: DRAM Refresh Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Table 8-3: Panel Data Width Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Table 8-4: FPLINE Polarity Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Table 8-5: FPFRAME Polarity Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Table 8-6: Simultaneous Display Option Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Table 8-7: Bit-per-pixel Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Table 8-8: Pixel Panning Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Table 8-9: PCLK Divide Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Table 8-10: Suspend Refresh Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Table 8-11: MA/GPIO Pin Functionality. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Table 8-12: Minimum Memory Timing Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Table 8-13: RAS#-to-CAS# Delay Timing Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Table 8-14: RAS Precharge Timing Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Table 8-15: Optimal NRC, NRP, and NRCD values at maximum MCLK frequency . . . . . . . . . . . . . . 116

Table 8-16: Minimum Memory Timing Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Table 8-17: Ink/Cursor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Table 8-18: Ink/Cursor Start Address Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Table 8-19: Recommended Alternate FRM Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Table 9-1: S1D13505 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Table 12-1: Ink/Cursor Start Address Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Table 12-2: Ink/Cursor Color Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

Table 13-2 Minimum DRAM Size Required for SwivelView. . . . . . . . . . . . . . . . . . . . . . . . . . 138

Table 14-1: Maximum PCLK Frequency with EDO-DRAM . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Table 14-2: Maximum PCLK Frequency with FPM-DRAM . . . . . . . . . . . . . . . . . . . . . . . . . . 140

Table 14-3: Example Frame Rates with Ink Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

Table 14-4: Number of MCLKs required for various memory access . . . . . . . . . . . . . . . . . . . . . . 143

Table 14-5: Total # MCLKs taken for Display refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

Table 14-6: Theoretical Maximum Bandwidth M byte/sec, Cursor/Ink disabled . . . . . . . . . . . . . . . . 145

Table 15-1: Power Save Mode Function Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

Table 15-2: Pin States in Power-save Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

S1D13505

X23A-A-001-14

Hardware Functional Specification

Issue Date: 01/02/02

Epson Research and Development

Page 9

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List of Figures

Figure 3-1:

Figure 3-2:

Figure 3-3:

Figure 3-4:

Figure 3-5:

Figure 3-6:

Figure 3-7:

Figure 3-8:

Figure 3-9:

Typical System Diagram (SH-4 Bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Typical System Diagram (SH-3 Bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Typical System Diagram (MC68K Bus 1, 16-Bit 68000) . . . . . . . . . . . . . . . . . . . . . 16

Typical System Diagram (MC68K Bus 2, 32-Bit 68030) . . . . . . . . . . . . . . . . . . . . . 16

Typical System Diagram (Generic Bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Typical System Diagram (NEC VR41xx (MIPS) Bus) . . . . . . . . . . . . . . . . . . . . . . 17

Typical System Diagram (Philips PR31500/PR31700 Bus). . . . . . . . . . . . . . . . . . . . 18

Typical System Diagram (Toshiba TX3912 Bus) . . . . . . . . . . . . . . . . . . . . . . . . . 18

Typical System Diagram (Power PC Bus). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 3-10: Typical System Diagram (PC Card (PCMCIA) Bus) . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 5-1:

Figure 5-3:

Figure 7-1:

Figure 7-2:

Figure 7-3:

Figure 7-4:

Figure 7-5:

Figure 7-6:

Figure 7-7:

Figure 7-8:

Figure 7-9:

Pinout Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

External Circuitry for CRT Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

SH-4 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

SH-3 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

MC68000 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

MC68030 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

PC Card Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Generic Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

MIPS/ISA Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Philips Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Clock Input Requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Figure 7-10: Toshiba Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Figure 7-11: Clock Input Requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Figure 7-12: Power PC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Figure 7-13: Clock Input Requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Figure 7-14: EDO-DRAM Read/Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Figure 7-15: EDO-DRAM Read-Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Figure 7-16: EDO-DRAM CAS Before RAS Refresh Timing . . . . . . . . . . . . . . . . . . . . . . . . . 66

Figure 7-17: EDO-DRAM Self-Refresh Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Figure 7-18: FPM-DRAM Read/Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Figure 7-19: FPM-DRAM Read-Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Figure 7-20: FPM-DRAM CAS Before RAS Refresh Timing . . . . . . . . . . . . . . . . . . . . . . . . . 72

Figure 7-21: FPM-DRAM Self-Refresh Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Figure 7-22: LCD Panel Power Off / Power On Timing. Drawn with LCDPWR set to active high polarity. . 74

Figure 7-23: Power Save Status and Local Bus Memory Access Relative to Power Save Mode . . . . . . . . 75

Figure 7-24: 4-Bit Single Monochrome Passive LCD Panel Timing . . . . . . . . . . . . . . . . . . . . . . 76

Figure 7-25: 4-Bit Single Monochrome Passive LCD Panel A.C. Timing . . . . . . . . . . . . . . . . . . . 77

Figure 7-26: 8-Bit Single Monochrome Passive LCD Panel Timing . . . . . . . . . . . . . . . . . . . . . . 78

Figure 7-27: 8-Bit Single Monochrome Passive LCD Panel A.C. Timing . . . . . . . . . . . . . . . . . . . 79

Figure 7-28: 4-Bit Single Color Passive LCD Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Figure 7-29: 4-Bit Single Color Passive LCD Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . 81

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Figure 7-30: 8-Bit Single Color Passive LCD Panel Timing (Format 1). . . . . . . . . . . . . . . . . . . . . 82

Figure 7-31: 8-Bit Single Color Passive LCD Panel A.C. Timing (Format 1). . . . . . . . . . . . . . . . . . 83

Figure 7-32: 8-Bit Single Color Passive LCD Panel Timing (Format 2). . . . . . . . . . . . . . . . . . . . . 84

Figure 7-33: 8-Bit Single Color Passive LCD Panel A.C. Timing (Format 2). . . . . . . . . . . . . . . . . . 85

Figure 7-34: 16-Bit Single Color Passive LCD Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Figure 7-35: 16-Bit Single Color Passive LCD Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . 87

Figure 7-36: 8-Bit Dual Monochrome Passive LCD Panel Timing . . . . . . . . . . . . . . . . . . . . . . . 88

Figure 7-37: 8-Bit Dual Monochrome Passive LCD Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . 89

Figure 7-38: 8-Bit Dual Color Passive LCD Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Figure 7-39: 8-Bit Dual Color Passive LCD Panel A.C. Timing. . . . . . . . . . . . . . . . . . . . . . . . . 91

Figure 7-40: 16-Bit Dual Color Passive LCD Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Figure 7-41: 16-Bit Dual Color Passive LCD Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . 93

Figure 7-42: 16-Bit TFT/D-TFD Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Figure 7-43: TFT/D-TFD A.C. Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Figure 7-44: CRT Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Figure 7-45: CRT A.C. Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Figure 9-1:

Display Buffer Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Figure 10-1: 1/2/4/8 Bit-per-pixel Format Memory Organization . . . . . . . . . . . . . . . . . . . . . . . 124

Figure 10-2: 15/16 Bit-per-pixel Format Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . 125

Figure 10-3: Image Manipulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

Figure 11-1: 1 Bit-per-pixel Monochrome Mode Data Output Path . . . . . . . . . . . . . . . . . . . . . . 127

Figure 11-2: 2 Bit-per-pixel Monochrome Mode Data Output Path . . . . . . . . . . . . . . . . . . . . . . 127

Figure 11-3: 4 Bit-per-pixel Monochrome Mode Data Output Path . . . . . . . . . . . . . . . . . . . . . . 128

Figure 11-4: 1 Bit-per-pixel Color Mode Data Output Path . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Figure 11-5: 2 Bit-per-pixel Color Mode Data Output Path . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Figure 11-6: 4 Bit-per-pixel Color Mode Data Output Path . . . . . . . . . . . . . . . . . . . . . . . . . . 131

Figure 11-7: 8 Bit-per-pixel Color Mode Data Output Path . . . . . . . . . . . . . . . . . . . . . . . . . . 132

Figure 12-1: Ink/Cursor Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Figure 12-2: Cursor Positioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

Figure 13-1: Relationship Between The Screen Image and the Image Residing in the Display Buffer . . . . 135

Figure 16-1: Mechanical Drawing QFP15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

S1D13505

X23A-A-001-14

Hardware Functional Specification

Issue Date: 01/02/02

Epson Research and Development

Page 11

Vancouver Design Center

1 Introduction

1.1 Scope

This is the Hardware Functional Specification for the S1D13505 Embedded RAMDAC LCD/CRT

Controller. Included in this document are timing diagrams, AC and DC characteristics, register

descriptions, and power management descriptions. This document is intended for two audiences:

Video Subsystem Designers and Software Developers.

This specification will be updated as appropriate. Please check the Epson Electronics America

Website at http://www.eea.epson.com or the Epson Research and Development website at

http://www.erd.epson.com for the latest revision of this document before beginning any devel-

opment.

We appreciate your comments on our documentation. Please contact us via email at

[email protected].

1.2 Overview Description

The S1D13505 is a color/monochrome LCD/CRT graphics controller interfacing to a wide range of

CPUs and display devices. The S1D13505 architecture is designed to meet the low cost, low power

requirements of the embedded markets, such as Mobile Communications, Hand-Held PCs, and

Office Automation.

The S1D13505 supports multiple CPUs, all LCD panel types, CRT, and additionally provides a

number of differentiating features. Products requiring a “Portrait” mode display can take advantage

of the SwivelView™ feature. Simultaneous, Virtual and Split Screen Display are just some of the

display modes supported, while the Hardware Cursor, Ink Layer, and the Memory Enhancement

Registers offer substantial performance benefits. These features, combined with the S1D13505’s

Operating System independence, make it an ideal display solution for a wide variety of applications.

Hardware Functional Specification

Issue Date: 01/02/02

S1D13505

X23A-A-001-14

Page 12

Epson Research and Development

Vancouver Design Center

2 Features

2.1 Memory Interface

• 16-bit DRAM interface:

• EDO-DRAM up to 40MHz data rate (80M bytes/sec.).

• FPM-DRAM up to 25MHz data rate (50M bytes/sec.).

• Memory size options:

• 512K bytes using one 256K×16 device.

• 2M bytes using one 1M×16 device.

• Performance Enhancement Register to tailor the memory control output timing for the DRAM

device.

2.2 CPU Interface

• Supports the following interfaces:

• 8/16-bit SH-4 bus interface.

• 8/16-bit SH-3 bus interface.

• 8/16-bit interface to 8/16/32-bit MC68000 microprocessors/microcontrollers.

• 8/16-bit interface to 8/16/32-bit MC68030 microprocessors/microcontrollers.

• Philips PR31500/PR31700 (MIPS).

• Toshiba TX3912 (MIPS)

• 16-bit Power PC (MPC821) microprocessor.

• 16-bit Epson E0C33 microprocessor.

• PC Card (PCMCIA).

• StrongARM (PC Card).

• NEC VR41xx (MIPS).

• ISA bus.

• Supports the following interface with external logic:

• GX486 microprocessor.

• One-stage write buffer for minimum wait-state CPU writes.

• Registers are memory-mapped – the M/R# pin selects between the display buffer and register

address space.

• The complete 2M byte display buffer address space is addressable as a single linear address

space through the 21-bit address bus.

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2.3 Display Support

• 4/8-bit monochrome passive LCD interface.

• 4/8/16-bit color passive LCD interface.

• Single-panel, single-drive displays.

• Dual-panel, dual-drive displays.

• Direct support for 9/12-bit TFT/D-TFD; 18-bit TFT/D-TFD is supported up to 64K color depth

(16-bit data).

• Embedded RAMDAC (DAC)with direct analog CRT drive.

• Simultaneous display of CRT and passive or TFT/D-TFD panels.

2.4 Display Modes

• 1/2/4/8/15/16 bit-per-pixel (bpp) support on LCD/CRT.

• Up to 16 shades of gray using FRM on monochrome passive LCD panels.

• Up to 4096 colors on passive LCD panels; three 256x4 Look-Up Tables (LUT) are used to map

1/2/4/8 bpp modes into these colors, 15/16 bpp modes are mapped directly using the 4 most

significant bits of the red, green and blue colors.

• Up to 64K colors on TFT/D-TFD LCD panels and CRT; three 256x4 Look-Up Tables are used to

map 1/2/4/8 bpp modes into 4096 colors, 15/16 bpp modes are mapped directly.

2.5 Display Features

• SwivelView™: direct hardware 90° rotation of display image for “portrait” mode display.

• Split Screen Display: allows two different images to be simultaneously viewed on the same

display.

• Virtual Display Support: displays images larger than the display size through the use of panning.

• Double Buffering/multi-pages: provides smooth animation and instantaneous screen update.

• Acceleration of screen updates by allocating full display memory bandwidth to CPU (see

REG[23h] bit 7).

• Hardware 64x64 pixel 2-bit cursor or full screen 2-bit ink layer.

• Simultaneous display of CRT and passive panel or TFT/D-TFD panel.

• Normal mode for cases where LCD and CRT screen sizes are identical.

• Line-doubling for simultaneous display of 240-line images on 240-line LCD and 480-line

CRT.

• Even-scan or interlace modes for simultaneous display of 480-line images on 240-line LCD

and 480-line CRT.

2.6 Clock Source

• Single clock input for both the pixel and memory clocks.

• Memory clock can be input clock or (input clock/2), providing flexibility to use CPU bus clock

as input.

• Pixel clock can be the memory clock, (memory clock/2), (memory clock/3) or (memory clock/4).

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2.7 Miscellaneous

• The memory data bus, MD[15:0], is used to configure the chip at power-on.

• Three General Purpose Input/Output pins, GPIO[3:1], are available if the upper Memory

Address pins are not required for asymmetric DRAM support.

• Suspend power save mode can be initiated by either hardware or software.

• The SUSPEND# pin is used either as an input to initiate Suspend mode, or as a General Purpose

Output that can be used to control the LCD backlight. Power-on polarity is selected by an MD

configuration pin.

• Operating voltages from 2.7 volts to 5.5 volts are supported

• 128-pin QFP15 surface mount package

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3 Typical System Implementation Diagrams

Power

Management

Oscillator

SH-4

BUS

FPDAT[15:8]

FPDAT[7:0]

FPSHIFT

UD[7:0]

A[21]

CSn#

M/R#

CS#

LD[7:0]

4/8/16-bit

LCD

FPSHIFT

A[20:0]

D[15:0]

AB[20:0]

DB[15:0]

FPFRAME

FPLINE

DRDY

FPFRAME

FPLINE

MOD

Display

WE1#

BS#

WE1#

BS#

S1D13505F00A

RD/WR#

RD#

LCDPWR

RD/WR#

RD#

RED,GREEN,BLUE

HRTC

WE0#

RDY#

WE0#

WAIT#

CRT

Display

VRTC

CKIO

BUSCLK

RESET#

IREF

256Kx16

FPM/EDO-DRAM

Figure 3-1: Typical System Diagram (SH-4 Bus)

Power

Oscillator

Management

SH-3

BUS

FPDAT[15:8]

FPDAT[7:0]

FPSHIFT

UD[7:0]

LD[7:0]

A[21]

CSn#

M/R#

CS#

4/8/16-bit

LCD

FPSHIFT

A[20:0]

D[15:0]

AB[20:0]

DB[15:0]

FPFRAME

FPLINE

DRDY

FPFRAME

FPLINE

MOD

Display

WE1#

BS#

WE1#

BS#

S1D13505F00A

RD/WR#

RD#

LCDPWR

RD/WR#

RD#

RED,GREEN,BLUE

HRTC

WE0#

WAIT#

WE0#

WAIT#

CRT

Display

VRTC

CKIO

BUSCLK

RESET#

IREF

256Kx16

FPM/EDO-DRAM

Figure 3-2: Typical System Diagram (SH-3 Bus)

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Oscillator

Power

Management

MC68000

BUS

A[23:21]

FC0, FC1

M/R#

CS#

FPDAT[15:8]

FPDAT[7:0]

FPSHIFT

UD[7:0]

LD[7:0]

Decoder

4/8/16-bit

FPSHIFT

LCD

A[20:1]

D[15:0]

AB[20:1]

DB[15:0]

FPFRAME

FPLINE

DRDY

FPFRAME

Display

FPLINE

MOD

LDS#

AB0#

S1D13505F00A

UDS#

AS#

WE1#

BS#

LCDPWR

RED,GREEN,BLUE

HRTC

R/W#

RD/WR#

WAIT#

CRT

Display

DTACK#

VRTC

BCLK

BUSCLK

RESET#

IREF

256Kx16

FPM/EDO-DRAM

Figure 3-3: Typical System Diagram (MC68K Bus 1, 16-Bit 68000)

Oscillator

Power

Management

MC68030

BUS

A[31:21]

FC0, FC1

M/R#

CS#

FPDAT[15:8]

FPDAT[7:0]

FPSHIFT

UD[7:0]

LD[7:0]

Decoder

4/8/16-bit

FPSHIFT

LCD

A[20:0]

AB[20:0]

DB[15:0]

FPFRAME

FPLINE

DRDY

FPFRAME

D[31:16]

Display

FPLINE

MOD

DS#

AS#

WE1#

BS#

S1D13505F00A

R/W#

LCDPWR

RD/WR#

RD#

SIZ1

RED,GREEN,BLUE

HRTC

SIZ0

WE0#

WAIT#

CRT

Display

DSACK1#

VRTC

BCLK

BUSCLK

RESET#

IREF

256Kx16

FPM/EDO-DRAM

Figure 3-4: Typical System Diagram (MC68K Bus 2, 32-Bit 68030)

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Power

Oscillator

Management

Generic

BUS

M/R#

CS#

A[27:21]

FPDAT[15:8]

FPDAT[7:0]

FPSHIFT

UD[7:0]

Decoder

LD[7:0]

CSn#

4/8/16-bit

LCD

FPSHIFT

A[20:0]

D[15:0]

AB[20:0]

DB[15:0]

FPFRAME

FPLINE

DRDY

FPFRAME

FPLINE

MOD

Display

WE0#

WE1#

WE0#

WE1#

S1D13505F00A

LCDPWR

RD#

RED,GREEN,BLUE

HRTC

RD/WR#

WAIT#

CRT

Display

WAIT#

VRTC

BCLK

BUSCLK

RESET#

IREF

1Mx16

FPM/EDO-DRAM

Figure 3-5: Typical System Diagram (Generic Bus)

Power

Oscillator

Management

MIPS

BUS

M/R#

CS#

A[25:21]

CSn#

FPDAT[15:8]

FPDAT[7:0]

FPSHIFT

UD[7:0]

LD[7:0]

Decoder

4/8/16-bit

LCD

FPSHIFT

A[20:0]

D[15:0]

AB[20:0]

DB[15:0]

FPFRAME

FPLINE

DRDY

FPFRAME

FPLINE

MOD

Display

MEMW#

SBHE#

WE0#

WE1#

S1D13505F00A

LCDPWR

MEMR#

RD#

RED,GREEN,BLUE

HRTC

VDD

CRT

Display

RD/WR#

WAIT#

RDY

BCLK

VRTC

BUSCLK

RESET#

RESET

IREF

1Mx16

FPM/EDO-DRAM

Figure 3-6: Typical System Diagram (NEC VR41xx (MIPS) Bus)

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Power

Oscillator

Management

Philips

PR31500

/PR31700

BUS

M/R#

CS#

FPDAT[15:8]

FPDAT[7:0]

FPSHIFT

UD[7:0]

LD[7:0]

BS#

AB[16:13]

4/8/16-bit

FPSHIFT

A[12:0]

AB[12:0]

DB[15:0]

LCD

D[31:16]

FPFRAME

FPLINE

DRDY

FPFRAME

Display

ALE

AB20

AB19

AB18

AB17

FPLINE

MOD

/CARDREG

/CARDIORD

/CARDIOWR

/CARDxCSH

S1D13505F00A

LCDPWR

WE1#

RD/WR#

RD#

/CARDxCSL

/RD

RED,GREEN,BLUE

HRTC

CRT

/WE

WE0#

WAIT#

Display

VRTC

/CARDxWAIT

DCLKOUT

RESET#

BUSCLK

RESET#

IREF

1Mx16

FPM/EDO-DRAM

Figure 3-7: Typical System Diagram (Philips PR31500/PR31700 Bus)

Power

Oscillator

Management

Toshiba

TX3912 BUS

M/R#

CS#

FPDAT[15:8]

FPDAT[7:0]

FPSHIFT

UD[7:0]

LD[7:0]

BS#

AB[16:13]

4/8/16-bit

FPSHIFT

A[12:0]

AB[12:0]

DB[15:8]

LCD

D[23:16]

DB[7:0]

AB20

FPFRAME

FPLINE

DRDY

FPFRAME

D[31:24]

ALE

Display

FPLINE

MOD

CARDREG*

AB19

AB18

AB17

CARDIORD*

CARDIOWR*

CARDxCSH*

S1D13505F00A

LCDPWR

WE1#

RD/WR#

RD#

CARDxCSL*

RD*

RED,GREEN,BLUE

HRTC

CRT

Display

WE*

WE0#

WAIT#

VRTC

CARDxWAIT*

DCLKOUT

RESET#

BUSCLK

RESET#

IREF

1Mx16

FPM/EDO-DRAM

Figure 3-8: Typical System Diagram (Toshiba TX3912 Bus)

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Oscillator

Power

Management

PowerPC

BUS

A[0:10]

M/R#

CS#

FPDAT[15:8]

FPDAT[7:0]

FPSHIFT

UD[7:0]

Decoder

LD[7:0]

4/8/16-bit

LCD

Decoder

FPSHIFT

A[11:31]

D[0:15]

AB[20:0]

DB[15:0]

FPFRAME

FPLINE

DRDY

FPFRAME

FPLINE

MOD

Display

BI#

TS#

WE1#

BS#

S1D13505F00A

RD/WR#

TSIZ0

TSIZ1

TA#

LCDPWR

RD/WR#

RD#

RED,GREEN,BLUE

HRTC

WE0#

WAIT#

CRT

Display

VRTC

CLKOUT

RESET#

BUSCLK

RESET#

IREF

256Kx16

FPM/EDO-DRAM

Figure 3-9: Typical System Diagram (Power PC Bus)

Power

Oscillator

Management

PC Card

BUS

Decoder

M/R#

CS#

A[25:21]

FPDAT[15:8]

FPDAT[7:0]

FPSHIFT

UD[7:0]

LD[7:0]

4/8/16-bit

LCD

FPSHIFT

A[20:0]

D[15:0]

AB[20:0]

DB[15:0]

FPFRAME

FPLINE

DRDY

FPFRAME

FPLINE

MOD

Display

-WE

WE0#

WE1#

S1D13505F00A

-CE2

LCDPWR

-OE

RD#

-CE1

RED,GREEN,BLUE

HRTC

RD/WR#

WAIT#

CRT

Display

-WAIT

VRTC

BCLK

BUSCLK

RESET#

RESET

IREF

1Mx16

FPM/EDO-DRAM

Figure 3-10: Typical System Diagram (PC Card (PCMCIA) Bus)

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4 Internal Description

4.1 Block Diagram Showing Datapaths

16-bit FPM/EDO-DRAM

Memory

Controller

CPU

R/W

LCD

Display

FIFO

Host

I/F

CPU/MPU

Look-

CRT

DAC

Tables

Cursor

FIFO

Power Save

CRTC

Clocks

4.2 Block Descriptions

4.2.1 Register

The Register block contains all the register latches

4.2.2 Host Interface

The Host Interface (I/F) block provides the means for the CPU/MPU to communicate with the

display buffer and internal registers via one of the supported bus interfaces.

4.2.3 CPU R/W

The CPU R/W block synchronizes the CPU requests for display buffer access. If SwivelView is

enabled, the data is rotated in this block.

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4.2.4 Memory Controller

The Memory Controller block arbitrates between CPU accesses and display refresh accesses as well

as generates the necessary signals to interface to one of the supported 16-bit memory devices (FPM-

DRAM or EDO-DRAM).

4.2.5 Display FIFO

4.2.6 Cursor FIFO

The Display FIFO block fetches display data from the Memory Controller for display refresh.

The Cursor FIFO block fetches Cursor/ink data from the Memory Controller for display refresh.

4.2.7 Look-Up Tables

The Look-Up Tables block contains three 256x4 Look-Up Tables (LUT), one for each primary

color. In monochrome mode, only the green LUT is selected and used. This block contains anti-

sparkle circuitry. The cursor/ink and display data are merged in this block.

4.2.8 CRTC

The CRTC generates the sync timing for the LCD and CRT, defining the vertical and horizontal

display periods.

4.2.9 LCD Interface

The LCD Interface block performs Frame Rate Modulation (FRM) for passive LCD panels and

generates the correct data format and timing control signals for various LCD and TFT/D-TFD

panels.

4.2.10 DAC

The DAC is the Digital to Analog converter for analog CRT support.

The Power Save block contains the power save mode circuitry.

The Clocks module is the source of all clocks in the chip.

4.2.11 Power Save

4.2.12 Clocks

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5 Pins

5.1 Pinout Diagram

96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65

MA5

MA1

MA6

MA0

MA7

MA10

VDD

DACVSS

DACVDD

100

RED

101

IREF

102

DACVDD

103

MA8

MA11

MA9

GREEN

104

DACVDD

105

BLUE

106

VDD

DACVSS

107

RAS#

WE#

HRTC

108

VRTC

109

UCAS#

LCAS#

VSS

VDD

110

VSS

111

AB20

112

MD7

AB19

113

MD8

AB18

114

S1D13505

MD6

AB17

115

MD9

AB16

116

MD5

AB15

117

MD10

MD4

AB14

118

AB13

119

MD11

MD3

AB12

120

AB11

121

AB10

MD12

MD2

122

AB9

123

AB8

MD13

MD1

124

AB7

125

MD14

MD0

AB6

126

AB5

127

AB4

MD15

VDD

128

AB3

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Figure 5-1: Pinout Diagram

128-pin QFP15 surface mount package

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5.2 Pin Description

Key:

Input

Output

Bi-Directional (Input/Output)

Analog

Power pin

CMOS level input

COx

TSx

CMOS level input with pull down resistor (typical values of 100KΩ/180ΚΩ at 5V/3.3V respectively)

CMOS level Schmitt input

CMOS output driver, x denotes driver type (see tables 6-3, 6-4, 6-5 for details)

Tri-state CMOS output driver, x denotes driver type (see tables 6-3, 6-4, 6-5 for details)

Tri-state CMOS output driver with pull down resistor (typical values of 100KΩ/180ΚΩ at 5V/3.3V)

TSxD

CNx

respectively), x denotes driver type (see tables 6-3, 6-4, 6-5 for details)

CMOS low-noise output driver, x denotes driver type (see tables 6-3, 6-4, 6-5 for details)

5.2.1 Host Interface

Table 5-1: Host Interface Pin Descriptions

RESET#

State

Pin Name

Type

Pin #

Cell

Description

•

For SH-3/SH-4 Bus, this pin inputs system address bit 0 (A0).

For MC68K Bus 1, this pin inputs the lower data strobe (LDS#).

For MC68K Bus 2, this pin inputs system address bit 0 (A0).

For Generic Bus, this pin inputs system address bit 0 (A0).

For MIPS/ISA Bus, this pin inputs system address bit 0 (SA0).

For Philips PR31500/31700 Bus, this pin inputs system address bit 0

(A0).

AB0

Hi-Z

•

For Toshiba TX3912 Bus, this pin inputs system address bit 0 (A0).

For PowerPC Bus, this pin inputs system address bit 31 (A31).

For PC Card (PCMCIA) Bus, this pin inputs system address bit 0

(A0).

See “Host Bus Interface Pin Mapping” for summary. See the respective

AC Timing diagram for detailed functionality.

•

For PowerPC Bus, these pins input the system address bits 19

through 30 (A[19:30]).

•

For all other busses, these pins input the system address bits 12

through 1 (A[12:1]).

119-128,

1, 2

AB[12:1]

Hi-Z

See “Host Bus Interface Pin Mapping” for summary. See the respective

AC Timing diagram for detailed functionality.

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Table 5-1: Host Interface Pin Descriptions (Continued)

RESET#

State

Pin Name

Type

Pin #

Cell

Description

• For Philips PR31500/31700 Bus, these pins are connected to V

• For Toshiba TX3912 Bus, these pins are connected to V

• For PowerPC Bus, these pins input the system address bits 15

through 18 (A[15:18]).

AB[16:13]

115-118

Hi-Z

• For all other busses, these pins input the system address bits 16

through 13 (A[16:13]).

See “Host Bus Interface Pin Mapping” for summary. See the respective

AC Timing diagram for detailed functionality.

• For Philips PR31500/31700 Bus, this pin inputs the IO write

command (/CARDIOWR).

• For Toshiba TX3912 Bus, this pin inputs the IO write command

(CARDIOWR*).

AB17

114

113

112

Hi-Z

• For PowerPC Bus, this pin inputs the system address bit 14 (A14).

• For all other busses, this pin inputs the system address bit 17 (A17).

See “Host Bus Interface Pin Mapping” for summary. See the respective

AC Timing diagram for detailed functionality.

• For Philips PR31500/31700 Bus, this pin inputs the IO read

command (/CARDIORD).

• For Toshiba TX3912 Bus, this pin inputs the IO read command

(CARDIORD*).

AB18

• For PowerPC Bus, this pin inputs the system address bit 13 (A13).

• For all other busses, this pin inputs the system address bit 18 (A18).

See “Host Bus Interface Pin Mapping” for summary. See the respective

AC Timing diagram for detailed functionality.

• For Philips PR31500/31700 Bus, this pin inputs the card control

• For Toshiba TX3912 Bus, this pin inputs the card control register

(CARDREG*).

AB19

• For PowerPC Bus, this pin inputs the system address bit 12 (A12).

• For all other busses, this pin inputs the system address bit 19 (A19).

See “Host Bus Interface Pin Mapping” for summary. See the respective

AC Timing diagram for detailed functionality.

• For the MIPS/ISA Bus, this pin inputs system address bit 20. Note

that for the ISA Bus, the unlatched LA20 must first be latched before

input to AB20.

• For Philips PR31500/31700 Bus, this pin inputs the address latch

enable (ALE).

• For Toshiba TX3912 Bus, this pin inputs the address latch enable

(ALE).

AB20

111

Hi-Z

• For PowerPC Bus, this pin inputs the system address bit 11 (A11).

• For all other busses, this pin inputs the system address bit 20 (A20).

See “Host Bus Interface Pin Mapping” for summary. See the respective

AC Timing diagram for detailed functionality.

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Table 5-1: Host Interface Pin Descriptions (Continued)

RESET#

State

Pin Name

Type

Pin #

Cell

Description

These pins are the system data bus. For 8-bit bus modes, unused data

pins should be tied to V

•

For SH-3/SH-4 Bus, these pins are connected to D[15:0].

For MC68K Bus 1, these pins are connected to D[15:0].

For MC68K Bus 2, these pins are connected to D[31:16] for 32-bit

devices (e.g. MC68030) or D[15:0] for 16-bit devices (e.g. MC68340).

•

For Generic Bus, these pins are connected to D[15:0].

For MIPS/ISA Bus, these pins are connected to SD[15:0].

DB[15:0]

16-31

C/TS2 Hi-Z

For Philips PR31500/31700 Bus, these pins are connected to

D[31:16].

•

For Toshiba TX3912 Bus, pins [15:8] are connected to D[23:16] and

pins [7:0] are connected to D[31:24].

•

For PowerPC Bus, these pins are connected to D[0:15].

For PC Card (PCMCIA) Bus, these pins are connected to D[15:0].

See “Host Bus Interface Pin Mapping” for summary. See the respective

AC Timing diagram for detailed functionality.

This is a multi-purpose pin:

•

For SH-3/SH-4 Bus, this pin inputs the write enable signal for the

upper data byte (WE1#).

•

For MC68K Bus 1, this pin inputs the upper data strobe (UDS#).

For MC68K Bus 2, this pin inputs the data strobe (DS#).

For Generic Bus, this pin inputs the write enable signal for the upper

data byte (WE1#).

•

For MIPS/ISA Bus, this pin inputs the system byte high enable signal

(SBHE#).

CS/TS

Hi-Z

WE1#

For Philips PR31500/31700 Bus, this pin inputs the odd byte access

enable signal (/CARDxCSH).

For Toshiba TX3912 Bus, this pin inputs the odd byte access enable

signal (CARDxCSH*).

•

For PowerPC Bus, this pin outputs the burst inhibit signal (BI#).

For PC Card (PCMCIA) Bus, this pin inputs the card enable 2 signal

(-CE2).

See “Host Bus Interface Pin Mapping” for summary. See the respective

AC Timing diagram for detailed functionality.

•

For Philips PR31500/31700 Bus, this pin is connected to V

For Toshiba TX3912 Bus, this pin is connected to V

For all other busses, this input pin is used to select between the

display buffer and register address spaces of the S1D13505. M/R# is

set high to access the display buffer and low to access the registers.

See Register Mapping.

M/R#

CS#

Hi-Z

See Table 5-6:, “CPU Interface Pin Mapping,” on page 34.

•

For Philips PR31500/31700 Bus, this pin is connected to V

For Toshiba TX3912 Bus, this pin is connected to V

For all other busses, this is the Chip Select input.

See Table 5-6:, “CPU Interface Pin Mapping,” on page 34. See the

respective AC Timing diagram for detailed functionality.

Hardware Functional Specification

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Table 5-1: Host Interface Pin Descriptions (Continued)

RESET#

State

Pin Name

Type

Pin #

Cell

Description

This pin inputs the system bus clock. It is possible to apply a 2x clock

and divide it by 2 internally - see MD12 in Summary of Configuration

Options.

• For SH-3/SH-4 Bus, this pin is connected to CKIO.

• For MC68K Bus 1, this pin is connected to CLK.

• For MC68K Bus 2, this pin is connected to CLK.

• For Generic Bus, this pin is connected to BCLK.

BUSCLK

Hi-Z

• For MIPS/ISA Bus, this pin is connected to CLK.

• For Philips PR31500/31700 Bus, this pin is connected to DCLKOUT.

• For Toshiba TX3912 Bus, this pin is connected to DCLKOUT.

• For PowerPC Bus, this pin is connected to CLKOUT.

• For PC Card (PCMCIA) Bus, this pin is connected to CLKI.

See “Host Bus Interface Pin Mapping” for summary. See the respective

AC Timing diagram for detailed functionality.

This is a multi-purpose pin:

• For SH-3/SH-4 Bus, this pin inputs the bus start signal (BS#).

• For MC68K Bus 1, this pin inputs the address strobe (AS#).

• For MC68K Bus 2, this pin inputs the address strobe (AS#).

• For Generic Bus, this pin is connected to V

• For MIPS/ISA Bus, this pin is connected to V

BS#

Hi-Z

• For Philips PR31500/31700 Bus, this pin is connected to V

• For Toshiba TX3912 Bus, this pin is connected to V

• For PowerPC Bus, this pin inputs the Transfer Start signal (TS#).

• For PC Card (PCMCIA) Bus, this pin is connected to V

See “Host Bus Interface Pin Mapping” for summary. See the respective

AC Timing diagram for detailed functionality.

This is a multi-purpose pin:

• For SH-3/SH-4 Bus, this pin inputs the read write signal (RD/WR#).

The S1D13505 needs this signal for early decode of the bus cycle.

• For MC68K Bus 1, this pin inputs the read write signal (R/W#).

• For MC68K Bus 2, this pin inputs the read write signal (R/W#).

• For Generic Bus, this pin inputs the read command for the upper data

byte (RD1#).

• For MIPS/ISA Bus, this pin is connected to V

RD/WR#

Hi-Z

• For Philips PR31500/31700 Bus, this pin inputs the even byte access

enable signal (/CARDxCSL).

• For Toshiba TX3912 Bus, this pin inputs the even byte access enable

signal (CARDxCSL*).

• For PowerPC Bus, this pin inputs the read write signal (RD/WR#).

• For PC Card (PCMCIA) Bus, this pin inputs the card enable 1 signal

(-CE1).

See “Host Bus Interface Pin Mapping” for summary. See the respective

AC Timing diagram for detailed functionality.

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Table 5-1: Host Interface Pin Descriptions (Continued)

RESET#

State

Pin Name

Type

Pin #

Cell

Description

This is a multi-purpose pin:

•

For SH-3/SH-4 Bus, this pin inputs the read signal (RD#).

For MC68K Bus 1, this pin is connected to V

For MC68K Bus 2, this pin inputs the bus size bit 1 (SIZ1).

For Generic Bus, this pin inputs the read command for the lower data

byte (RD0#).

•

For MIPS/ISA Bus, this pin inputs the memory read signal (MEMR#).

For Philips PR31500/31700 Bus, this pin inputs the memory read

command (/RD).

RD#

Hi-Z

•

For Toshiba TX3912 Bus, this pin inputs the memory read command

(RD*).

•

For PowerPC Bus, this pin inputs the transfer size 0 signal (TSIZ0).

For PC Card (PCMCIA) Bus, this pin inputs the output enable signal

(-OE).

See “Host Bus Interface Pin Mapping” for summary. See the respective

AC Timing diagram for detailed functionality.

This is a multi-purpose pin:

•

For SH-3/SH-4 Bus, this pin inputs the write enable signal for the

lower data byte (WE0#).

•

For MC68K Bus 1, this pin must be connected to V

For MC68K Bus 2, this pin inputs the bus size bit 0 (SIZ0).

For Generic Bus, this pin inputs the write enable signal for the lower

data byte (WE0#).

•

For MIPS/ISA Bus, this pin inputs the memory write signal

(MEMW#).

WE0#

Hi-Z

For Philips PR31500/31700 Bus, this pin inputs the memory write

command (/WE).

For Toshiba TX3912 Bus, this pin inputs the memory write command

(WE*).

•

For PowerPC Bus, this pin inputs the Transfer Size 1 signal (TSIZ1).

For PC Card (PCMCIA) Bus, this pin inputs the write enable signal (-

WE).

See “Host Bus Interface Pin Mapping” for summary. See the respective

AC Timing diagram for detailed functionality.

Hardware Functional Specification

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Table 5-1: Host Interface Pin Descriptions (Continued)

RESET#

State

Pin Name

Type

Pin #

Cell

Description

The active polarity of the WAIT# output is configurable; the state of MD5

on the rising edge of RESET# defines the active polarity of WAIT# - see

“Summary of Configuration Options”.

• For SH-3 Bus, this pin outputs the wait request signal (WAIT#); MD5

must be pulled low during reset by the internal pull-down resistor.

• For SH-4 Bus, this pin outputs the ready signal (RDY#); MD5 must be

pulled high during reset by an external pull-up resistor.

• For MC68K Bus 1, this pin outputs the data transfer acknowledge

signal (DTACK#); MD5 must be pulled high during reset by an

external pull-up resistor.

• For MC68K Bus 2, this pin outputs the data transfer and size

acknowledge bit 1 (DSACK1#); MD5 must be pulled high during reset

by an external pull-up resistor.

• For Generic Bus, this pin outputs the wait signal (WAIT#); MD5 must

be pulled low during reset by the internal pull-down resistor.

• For MIPS/ISA Bus, this pin outputs the IO channel ready signal

(IOCHRDY); MD5 must be pulled low during reset by the internal pull-

down resistor.

WAIT#

TS2

Hi-Z

• For Philips PR31500/31700 Bus, this pin outputs the wait state signal

(/CARDxWAIT); MD5 must be pulled low during reset by the internal

pull-down resistor.

• For Toshiba TX3912 Bus, this pin outputs the wait state signal

(CARDxWAIT*); MD5 must be pulled low during reset by the internal

pull-down resistor.

• For PowerPC Bus, this pin outputs the transfer acknowledge signal

(TA#); MD5 must be pulled high during reset by an external pull-up

resistor.

• For PC Card (PCMCIA) Bus, this pin outputs the wait signal (-WAIT);

MD5 must be pulled low during reset by the internal pull-down

resistor.

See “Host Bus Interface Pin Mapping” for summary. See the respective

AC Timing diagram for detailed functionality.

Active low input that clears all internal registers and forces all outputs to

their inactive states. Note that active high RESET signals must be

inverted before input to this pin.

RESET#

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5.2.2 Memory Interface

Table 5-2: Memory Interface Pin Descriptions

RESET#

State

Pin Name

Type

Pin #

Cell

Description

•

For dual-CAS# DRAM, this is the column address strobe for the

lower byte (LCAS#).

For single-CAS# DRAM, this is the column address strobe (CAS#).

LCAS#

CO1

See “Memory Interface Pin Mapping” for summary. See Memory

Interface Timing for detailed functionality.

This is a multi-purpose pin:

•

For dual-CAS# DRAM, this is the column address strobe for the

upper byte (UCAS#).

UCAS#

•

For single-CAS# DRAM, this is the write enable signal for the upper

byte (UWE#).

See “Memory Interface Pin Mapping” for summary. See Memory

Interface Timing for detailed functionality.

•

For dual-CAS# DRAM, this is the write enable signal (WE#).

For single-CAS# DRAM, this is the write enable signal for the lower

byte (LWE#).

WE#

CO1

See “Memory Interface Pin Mapping” for summary. See Memory

Interface Timing for detailed functionality.

Row address strobe - see Memory Interface Timing for detailed

functionality.

RAS#

Bi-Directional memory data bus.

34, 36, 38,

40, 42, 44,

46, 48, 49, C/TS

47, 45, 43, 1D

41, 39, 37,

During reset, these pins are inputs and their states at the rising edge of

RESET# are used to configure the chip - see Summary of

Configuration Options. Internal pull-down resistors (typical values of

100KΩ/180ΚΩ at 5V/3.3V respectively) pull the reset states to 0.

External pull-up resistors can be used to pull the reset states to 1.

MD[15:0]

Hi-Z

See Memory Interface Timing for detailed functionality.

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Table 5-2: Memory Interface Pin Descriptions (Continued)

RESET#

State

Pin Name

Type

Pin #

Cell

Description

58, 60, 62,

64, 66, 67, CO1 0utput

65, 63, 61

Multiplexed memory address - see Memory Interface Timing for

functionality.

MA[8:0]

This is a multi-purpose pin:

•

For 2M byte DRAM, this is memory address bit 9 (MA9).

For asymmetrical 512K byte DRAM, this is memory address bit 9

(MA9).

•

For symmetrical 512K byte DRAM, this pin can be used as general

purpose IO pin 3 (GPIO3).

C/TS

MA9

0utput

Note that unless configured otherwise, this pin defaults to an input and

must be driven to a valid logic level.

See “Memory Interface Pin Mapping” for summary. See Memory

Interface Timing for detailed functionality.

This is a multi-purpose pin:

•

For asymmetrical 2M byte DRAM this is memory address bit 10

(MA10).

•

For symmetrical 2M byte DRAM and all 512K byte DRAM this pin

can be used as general purpose IO pin 1 (GPIO1).

C/TS

MA10

0utput

Note that unless configured otherwise, this pin defaults to an input and

must be driven to a valid logic level.

See “Memory Interface Pin Mapping” for summary. See Memory

Interface Timing for detailed functionality.

This is a multi-purpose pin:

•

For asymmetrical 2M byte DRAM this is memory address bit 11

(MA11).

•

For symmetrical 2M byte DRAM and all 512K byte DRAM this pin

can be used as general purpose IO pin 2 (GPIO2).

C/TS

MA11

0utput

Note that unless configured otherwise, this pin defaults to an input and

must be driven to a valid logic level.

See “Memory Interface Pin Mapping” for summary. See Memory

Interface Timing for detailed functionality.

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5.2.3 LCD Interface

Table 5-2: LCD Interface Pin Descriptions

Cell RESET# State

Pin Name Type Pin #

Description

95-88,

86-79

Panel data bus. Not all pins are used for some panels - see LCD

Interface Pin Mapping for details. Unused pins are driven low.

FPDAT[15:0] O

CN3 0utput

FPFRAME

FPLINE

CN3 0utput

CO3 0utput

Frame pulse

Line pulse

Shift clock

FPSHIFT

LCD power control output. The active polarity of this output is selected

by the state of MD10 at the rising edge of RESET# - see Summary of

Configuration Options. This output is controlled by the power save

mode circuitry - see Power Save Modes for details.

0utput if

MD[10]=0

LCDPWR

DRDY

CO1

1 if MD[10]=1

This is a multi-purpose pin:

• For TFT/D-TFD panels this is the display enable output (DRDY).

• For passive LCD with Format 1 interface this is the 2nd Shift Clock

(FPSHIFT2)

CN3 0utput

• For all other LCD panels this is the LCD backplane bias signal

(MOD).

See LCD Interface Pin Mapping and REG[02h] for details.

5.2.4 CRT Interface

Table 5-3: CRT Interface Pin Descriptions

RESET

# State

Pin Name

HRTC

Type

Pin #

Cell

CN3

Description

107

108

100

103

105

0utput Horizontal retrace signal for CRT

0utput Vertical retrace signal for CRT

Analog output for CRT color Red

VRTC

RED

CN3

GREEN

BLUE

Analog output for CRT color Green

Analog output for CRT color Blue

Current reference for DAC - see Analog Pins. This pin must be left

unconnected if the DAC is not needed.

IREF

101

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5.2.5 Miscellaneous

Table 5-4: Miscellaneous Interface Pin Descriptions

Pin Name Type

Pin #

Cell

RESET# State

Description

This pin can be used as a power-down input (SUSPEND#)

or as an output possibly used for controlling the LCD

backlight power:

• When MD9 = 0 at rising edge of RESET#, this pin is an

active-low Schmitt input used to put the S1D13505 into

Hardware Suspend mode - see Section 15, “Power Save

Modes” for details.

Hi-Z if MD[9]=0

High if

SUSPEND# IO

CS/TS1 MD[10:9]=01

• When MD[10:9] = 01 at rising edge of RESET#, this pin

is an output (GPO) with a reset state of 1. The state of GPO

is controlled by REG[21h] bit 7.

Low if

MD[10:9]=11

• When MD[10:9] = 11 at rising edge of RESET#, this pin

is an output (GPO) with a reset state of 0. The state of GPO

is controlled by REG[21h] bit 7.

Input clock for the internal pixel clock (PCLK) and memory

clock (MCLK). PCLK and MCLK are derived from CLKI - see

REG[19h] for details.

CLKI

Test Enable. This pin should be connected to V for normal

TESTEN

Hi-Z

operation.

12, 33, 55, 72,

97, 109

VDD

DACVDD

VSS

99, 102, 104

DAC V

14, 32, 50, 68,

78, 87, 96, 110

DACVSS

98, 106

DAC V

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5.3 Summary of Configuration Options

Table 5-5: Summary of Power On/Reset Options

value on this pin at rising edge of RESET# is used to configure:

Pin Name

(1/0)

MD0

8-bit host bus interface

16-bit host bus interface

Select host bus interface:MD[11] = 0:

000 = SH-3/SH-4 bus interface

001 = MC68K Bus 1

010 = MC68K Bus 2

011 = Generic

MD[3:1]

100 = Reserved

101 = MIPS/ISA

110 = PowerPC

111 = PC Card (when MD11 = 1 Philips PR31500/PR31700 or Toshiba TX3912 Bus)

MD4

MD5

Little Endian

Big Endian

WAIT# is active high (1 = insert wait state)

Memory Address/GPIO configuration:

WAIT# is active low (0 = insert wait state)

00 = symmetrical 256K×16 DRAM. MA[8:0] = DRAM address. MA[11:9] = GPIO2,1,3 pins.

01 = symmetrical 1M×16 DRAM. MA[9:0] = DRAM address. MA[10:11] = GPIO2,1 pins.

10 = asymmetrical 256K×16 DRAM. MA[9:0] = DRAM address. MA[10:11] = GPIO2,1 pins.

11 = asymmetrical 1M×16 DRAM. MA[11:0] = DRAM address.

MD[7:6]

MD8

MD9

Not used

SUSPEND# pin configured as GPO output

SUSPEND# pin configured as SUSPEND# input

Active low LCDPWR polarity or

active high GPO polarity

Active high LCDPWR polarity or

active low GPO polarity

MD10

MD11

Alternate Host Bus Interface Selected

BUSCLK input divided by 2

Not used

Primary Host Bus Interface Selected

BUSCLK input not divided

MD12

MD[15:13]

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5.4 Multiple Function Pin Mapping

Table 5-6: CPU Interface Pin Mapping

S1D1350

Names

Philips

PR31500

/PR31700

MC68K

Bus 1

MC68K

Bus 2

Toshiba

TX3912

PC Card

(PCMCIA)

SH-3

SH-4

Generic MIPS/ISA

PowerPC

AB20

AB19

AB18

AB17

A20

A19

A18

A17

A20

A19

A18

A17

A20

A19

A18

A17

A20

A19

A18

A17

A20

A19

A18

A17

LatchA20

SA19

ALE

A11

A12

A20

A19

/CARDREG

CARDREG*

SA18

/CARDIORD CARDIORD*

/CARDIOWR CARDIOWR*

A13

A18

SA17

A14

A17

AB[16:13] A[16:13] A[16:13] A[16:13] A[16:13] A[16:13] SA[16:13]

A[15:18]

A[19:30]

A31

A[16:13]

A[12:1]

AB[12:1] A[12:1]

A[12:1]

LDS#

A[12:1]

SA[12:1]

SA0

A[12:1]

AB0

DB[15:8] D[15:8]

D[15:8]

D[7:0]

WE1#

D[15:8] D[31:24] D[15:8] SD[15:8]

D[31:24]

D[23:16]

D[31:24]

D[23:16]

D[0:7]

D[8:15

BI#

D[15:8]

D[7:0]

-CE2

DB[7:0]

WE1#

M/R#

D[7:0]

WE1#

D[7:0]

UDS#

D[23:16]

DS#

D[7:0]

WE1#

SD[7:0]

SBHE#

/CARDxCSH CARDxCSH*

External Decode

CS#

BUSCLK

BS#

CKIO

BS#

CKIO

BS#

CLK

AS#

CLK

AS#

BCLK

CLK

DCLKOUT

CLKOUT

TS#

CLKI

RD/WR# RD/WR# RD/WR#

R/W#

SIZ1

SIZ0

RD1#

RD0#

WE0#

/CARDxCSL CARDxCSL* RD/WR#

-CE1

-OE

RD#

WE0#

WAIT#

RD#

WE0#

WAIT#

RD#

WE0#

RDY

MEMR#

MEMW#

/RD

RD*

WE*

TSIZ0

TSIZ1

TA#

/WE

-WE

DTACK# DSACK1# WAIT# IOCHRDY /CARDxWAIT CARDxWAIT*

-WAIT

inverted

RESET

inverted

RESET

RESET# RESET# RESET# RESET# RESET# RESET#

RESET#

PON*

RESET#

Note

¹The bus signal A0 is not used by the S1D13505 internally.

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Table 5-7: Memory Interface Pin Mapping

FPM/EDO-DRAM

S1D13505

Pin Names

Sym 256Kx16

Asym 256Kx16

2-CAS# 2-WE#

D[15:0]

Sym 1Mx16

Asym 1Mx16

2-CAS# 2-WE#

2-CAS#

2-WE#

2-CAS#

2-WE#

MD[15:0]

MA[8:0]

MA9

A[8:0]

GPIO3

MA10

GPIO1

GPIO2

A10

A11

MA11

UCAS#

LCAS#

WE#

UCAS#

LCAS#

WE#

UWE#

CAS#

LWE#

UCAS#

UWE#

CAS#

LWE#

UCAS#

LCAS#

WE#

UWE#

CAS#

LWE#

UCAS#

LCAS#

WE#

UWE#

CAS#

LWE#

LCAS#

WE#

RAS#

Note

All GPIO pins default to input on reset and unless programmed otherwise, should be connected

to either V_SSor IO V_DDif not used.

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Table 5-8: LCD Interface Pin Mapping

Monochrome Passive

Panel

Color Passive Panel

S1D13505

Color TFT/D-TFD Panel

Single

Dual

8-bit

Single

4-bit

Single

16-Bit

Dual

16-bit

Names

Format 1 Format 2

4-bit

8-bit

9-bit

12-bit

18-bit

FPFRAME

FPLINE

FPFRAME

FPLINE

FPSHIFT

DRDY

MOD

DRDY

FPDAT0 driven 0

FPDAT1 driven 0

FPDAT2 driven 0

FPDAT3 driven 0

LD0

LD1

LD2

LD3

UD0

UD1

UD2

UD3

driven 0

LD0

LD1

LD2

LD3

UD0

UD1

UD2

UD3

LD0

LD1

LD2

LD3

UD0

UD1

UD2

UD3

LD4

LD5

LD6

LD7

FPDAT4

FPDAT5

FPDAT6

FPDAT7

FPDAT8 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0

FPDAT9 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0

FPDAT10 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0

FPDAT11 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0

FPDAT12] driven 0 driven 0 driven 0 driven 0 driven 0 driven 0

FPDAT13 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0

FPDAT14 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0

FPDAT15 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0

driven 0

D10

D11

D12

D13

D14

D15

driven 0 driven 0

driven 0 G0

driven 0 UD4

driven 0 UD5

driven 0 UD6

driven 0 UD7

driven 0 driven 0

driven 0

driven 0 driven 0

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5.5 CRT Interface

The following figure shows the external circuitry for the CRT interface.

DAC V = 3.3V

DAC V = 2.7V to 5.5V

1.5kΩ

1µF

4.6 mA

2N2222

4.6 mA

IREF

V+

LM334

1N457

140Ω

1kΩ

V-

29Ω

DAC V

290Ω

DAC V

To CRT

}

150Ω

DAC V

Figure 5-3: External Circuitry for CRT Interface

Hardware Functional Specification

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6 D.C. Characteristics

Table 6-1: Absolute Maximum Ratings

Parameter

Symbol

Rating

Units

Supply Voltage

- 0.3 to 6.0

DAC V

Supply Voltage

Input Voltage

- 0.3 to V + 0.5

Output Voltage

- 0.3 to V + 0.5

OUT

Storage Temperature

Solder Temperature/Time

-65 to 150

° C

STG

SOL

260 for 10 sec. max at lead

Table 6-2: Recommended Operating Conditions

Symbol

Parameter

Supply Voltage

Condition

Min

Typ

Max

Units

= 0 V

2.7

3.0/3.3/5.0 5.5

Input Voltage

Operating Temperature

-40

° C

OPR

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Table 6-3: Electrical Characteristics for VDD = 5.0V typical

Symbol

Parameter

Condition

Min

Typ

Max

400

Units

Quiescent Current

Quiescent Conditions

µA

DDS

Input Leakage Current

Output Leakage Current

-1

VDD = min

-4mA (Type1),

-8mA (Type2)

-12mA (Type3)

High Level Output Voltage

Low Level Output Voltage

- 0.4

VDD = min

4mA (Type1),

8mA (Type2)

12mA (Type3)

0.4

High Level Input Voltage

Low Level Input Voltage

CMOS level, V = max 3.5

CMOS level, V = min

1.0

4.0

CMOS Schmitt,

High Level Input Voltage

Low Level Input Voltage

Hysteresis Voltage

T+

= 5.0V

CMOS Schmitt,

= 5.0V

0.8

T-

CMOS Schmitt,

= 5.0V

0.3

Pull Down Resistance

V = V

100

200

kΩ

Input Pin Capacitance

Output Pin Capacitance

Bi-Directional Pin Capacitance

Hardware Functional Specification

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Table 6-4: Electrical Characteristics for VDD = 3.3V typical

Symbol

Parameter

Quiescent Current

Condition

Min

Typ

Max

290

Units

Quiescent Conditions

µA

DDS

Input Leakage Current

Output Leakage Current

-1

VDD = min

-2mA (Type1),

-4mA (Type2)

-6mA (Type3)

High Level Output Voltage

Low Level Output Voltage

- 0.3

VDD = min

2mA (Type1),

4mA (Type2)

6mA (Type3)

0.3

High Level Input Voltage

Low Level Input Voltage

CMOS level, V = max 2.2

CMOS level, V = min

0.8

2.4

CMOS Schmitt,

High Level Input Voltage

Low Level Input Voltage

Hysteresis Voltage

T+

= 3.3V

CMOS Schmitt,

= 3.3V

0.6

T-

CMOS Schmitt,

= 3.3V

0.1

Pull Down Resistance

V = V

180

360

kΩ

Input Pin Capacitance

Output Pin Capacitance

Bi-Directional Pin Capacitance

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Table 6-5: Electrical Characteristics for VDD = 3.0V typical

Symbol

Parameter

Condition

Min

Typ

Max

260

Units

Quiescent Current

Quiescent Conditions

µA

DDS

Input Leakage Current

Output Leakage Current

-1

VDD = min

-1.8mA (Type1),

-3.5mA (Type2)

-5mA (Type3)

High Level Output Voltage

Low Level Output Voltage

- 0.3

VDD = min

1.8mA (Type1),

3.5mA (Type2)

5mA (Type3)

0.3

High Level Input Voltage

Low Level Input Voltage

CMOS level, V = max 2.0

CMOS level, V = min

0.8

2.3

CMOS Schmitt,

High Level Input Voltage

Low Level Input Voltage

Hysteresis Voltage

T+

= 3.0V

CMOS Schmitt,

= 3.0V

0.5

0.1

T-

CMOS Schmitt,

= 3.0V

Pull Down Resistance

V = V

100

200

400

kΩ

Input Pin Capacitance

Output Pin Capacitance

Bi-Directional Pin Capacitance

Hardware Functional Specification

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7 A.C. Characteristics

Conditions: V_DD= 3.0V ± 10% and V_DD= 5.0V ± 10%

T_A= -40° C to 85° C

_riseand T_fallfor all inputs must be ≤ 5 nsec (10% ~ 90%)

C_L= 50pF (CPU Interface), unless noted

C_L= 100pF (LCD Panel Interface)

C_L= 10pF (Display Buffer Interface)

C_L= 10pF (CRT Interface)

7.1 CPU Interface Timing

7.1.1 SH-4 Interface Timing

CKIO

A[20:0], M/R#

RD/WR#

BS#

t12

CSn#

t10

WEn#

RD#

t12

t11

RDY#

t14

t13

D[15:0](write)

t15

t16

D[15:0](read)

Figure 7-1: SH-4 Timing

Note

The above timing diagram is not applicable if the BUSCLK divided by 2 configuration option is

selected.

S1D13505

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Hardware Functional Specification

Issue Date: 01/02/02

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Note

The SH-4 Wait State Control Register for the area in which the S1D13505 resides must be set to

a non-zero value. The SH-4 read-to-write cycle transition must be set to a non-zero value (with

reference to BUSCLK).

Table 7-1: SH-4 Timing

3.0V

5.0V

Symbol

Parameter

Min

Max

Min

Max

Units

Clock period

Clock pulse width high

Clock pulse width low

A[20:0], M/R#, RD/WR# setup to CKIO

A[20:0], M/R#, RD/WR# hold from CS#

BS# setup

BS# hold

CSn# setup

Falling edge RD# to D[15:0] driven

Rising edge CSn# to RDY# tri-state

Falling edge CSn# to RDY# driven

CKIO to WAIT# delay

t10

2.5

t11

t12

t13

t14

t15

t16

3.6

D[15:0] setup to 2 CKIO after BS# (write cycle)

D[15:0] hold (write cycle)

D[15:0] valid to RDY# falling edge (read cycle)

2.5

Rising edge RD# to D[15:0] tri-state (read cycle)

Two Software WAIT States Required

One Software WAIT State Required

1. If the S1D13505 host interface is disabled, the timing for RDY# driven is relative to the falling

edge of CSn# or the first positive edge of CKIO after A[20:0], M/R# becomes valid,

whichever one is later.

2. If the S1D13505 host interface is disabled, the timing for D[15:0] driven is relative to the fall-

ing edge of RD# or the first positive edge of CKIO after A[20:0], M/R# becomes valid,

whichever one is later.

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7.1.2 SH-3 Interface Timing

CKIO

A[20:0], M/R#

RD/WR#

BS#

t12

CSn#

t10

WEn#

RD#

t12

t11

WAIT#

t14

t13

D[15:0](write)

t15

t16

D[15:0](read)

Figure 7-2: SH-3 Timing

Note

The above timing diagram is not applicable if the BUSCLK divided by 2 configuration option is

selected.

Note

The SH-3 Wait State Control Register for the area in which the S1D13505 resides must be set to

a non-zero value.

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Issue Date: 01/02/02

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Table 7-2: SH-3 Timing

Parameter

3.0V

Min

5.0V

Min

Symbol

Max

Units

15.1

Clock period

Clock pulse width high

Clock pulse width low

A[20:0], M/R#, RD/WR# setup to CKIO

A[20:0], M/R#, RD/WR# hold from CS#

BS# setup

BS# hold

CSn# setup

Falling edge RD# to D[15:0] driven

Rising edge CSn# to WAIT# tri-state

Falling edge CSn# to WAIT# driven

CKIO to WAIT# delay

t10

2.5

t11

t12

t13

t14

t15

t16

3.6

D[15:0] setup to 2 CKIO after BS# (write cycle)

D[15:0] hold (write cycle)

D[15:0] valid to WAIT# rising edge (read cycle)

Rising edge RD# to D[15:0] tri-state (read cycle)

2.5

Two Software WAIT States Required

One Software WAIT State Required

1. If the S1D13505 host interface is disabled, the timing for WAIT# driven is relative to the fall-

ing edge of CSn# or the first positive edge of CKIO after A[20:0], M/R# becomes valid,

whichever one is later.

2. If the S1D13505 host interface is disabled, the timing for D[15:0] driven is relative to the fall-

ing edge of RD# or the first positive edge of CKIO after A[20:0], M/R# becomes valid,

whichever one is later.

Hardware Functional Specification

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7.1.3 MC68K Bus 1 Interface Timing (e.g. MC68000)

t2 t3

CLK

A[20:1]

M/R#

CS#

AS#

t17

t11

UDS#

LDS#

R/W#

t10

DTACK#

t12

t13

D[15:0](write)

t14

t16

t15

D[15:0](read)

Figure 7-3: MC68000 Timing

Note

The above timing diagram is not applicable if the BUSCLK divided by 2 configuration option is

selected.

S1D13505

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Hardware Functional Specification

Issue Date: 01/02/02

Epson Research and Development

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Table 7-3: MC68000 Timing

Parameter

3.0V

5.0V

Symbol

Min

Max

Min

Max

Units

Clock period

Clock pulse width high

Clock pulse width low

A[20:1], M/R# setup to first CLK where CS# = 0 AS# = 0, and

either UDS#=0 or LDS# = 0

A[20:1], M/R# hold from AS#

CS# hold from AS#

R/W# setup to before to either UDS#=0 or LDS# = 0

R/W# hold from AS#

AS# = 0 and CS# = 0 to DTACK# driven high

AS# high to DTACK# high

t10

t11

First BCLK where AS# = 1 to DTACK# high impedance

D[15:0] valid to third CLK where CS# = 0 AS# = 0, and either

UDS#=0 or LDS# = 0 (write cycle)

t12

t13

D[15:0] hold from falling edge of DTACK# (write cycle)

Falling edge of UDS#=0 or LDS#=0 to D[15:0] driven (read

cycle)

t14

t15

t16

t17

D[15:0] valid to DTACK# falling edge (read cycle)

UDS# and LDS# high to D[15:0] invalid/high impedance (read

cycle)

2.5

AS# high setup to CLK

1. If the S1D13505 host interface is disabled, the timing for DTACK# driven high is relative to

the falling edge of CS#, AS# or the first positive edge of CLK after A[20:1], M/R# becomes

valid,

whichever one is later.

2. If the S1D13505 host interface is disabled, the timing for D[15:0] driven is relative to the fall-

ing edge of UDS#, LDS# or the first positive edge of CLK after A[20:1], M/R# becomes valid,

whichever one is later.

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7.1.4 MC68K Bus 2 Interface Timing (e.g. MC68030)

CLK

A[20:0]

SIZ[1:0] M/R#

CS#

AS#

t17

t11

DS#

R/W#

t10

DSACK1#

D[31:16](write)

D[31:16](read)

t12

t13

t16

t14

t15

Figure 7-4: MC68030 Timing

Note

The above timing diagram is not applicable if the BUSCLK divided by 2 configuration option is

selected.

S1D13505

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Hardware Functional Specification

Issue Date: 01/02/02

Epson Research and Development

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Table 7-4: MC68030 Timing

Parameter

3.0V

5.0V

Symbol

Min

Max

Min

Max

Units

Clock period

Clock pulse width high

Clock pulse width low

A[20:0], SIZ[1:0], M/R# setup to first CLK where CS# = 0 AS# =

0, and either UDS#=0 or LDS# = 0

A[20:0], SIZ[1:0], M/R# hold from AS#

CS# hold from AS#

R/W# setup to DS#

R/W# hold from AS#

AS# = 0 and CS# = 0 to DSACK1# driven high

AS# high to DSACK1# high

t10

t11

2.5

First BCLK where AS# = 1 to DSACK1# high impedance

D[31:16] valid to third CLK where CS# = 0 AS# = 0, and either

UDS#=0 or LDS# = 0 (write cycle)

t12

t13

D[31:16] hold from falling edge of DSACK1# (write cycle)

Falling edge of UDS#=0 or LDS# = 0 to D[31:16] driven (read

cycle)

t14

t15

t16

t17

D[31:16] valid to DSACK1# falling edge (read cycle)

UDS# and LDS# high to D[31:16] invalid/high impedance (read

cycle)

2.5

AS# high setup to CLK

1. If the S1D13505 host interface is disabled, the timing for DSACK1# driven high is relative to

the falling edge of CS#, AS# or the first positive edge of CLK after A[20:0], M/R# becomes

valid, whichever one is later.

2. If the S1D13505 host interface is disabled, the timing for D[31:16] driven is relative to the

falling edge of UDS#, LDS# or the first positive edge of CLK after A[20:0], M/R# becomes

valid, whichever one is later.

Hardware Functional Specification

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7.1.5 PC Card Interface Timing

CLK

A[20:0]

M/R#

-CE[1:0]

CS#

-OE

-WE

-WAIT

D[15:0](write)

D[15:0](read)

t10

t11

t13

t12

Figure 7-5: PC Card Timing

Note

The above timing diagram is not applicable if the BUSCLK divided by 2 configuration option is

selected.

S1D13505

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Hardware Functional Specification

Issue Date: 01/02/02

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Table 7-5: PC Card Timing

Parameter

3.0V

5.0V

Symbol

Min

Max

Min

Max Units

Clock period

Clock pulse width high

Clock pulse width low

A[20:0], M/R# setup to first CLK where CS# = 0 and either -OE = 0 or -

WE = 0

A[20:0], M/R# hold from rising edge of either -OE or -WE

CS# hold from rising edge of either -OE or -WE

Falling edge of either -OE or -WE to -WAIT driven low

Rising edge of either -OE or -WE to -WAIT tri-state

D[15:0] setup to third CLK where CS# = 0 and -WE = 0 (write cycle)

D[15:0] hold (write cycle)

2.5

t10

t11

t12

t13

Falling edge -OE to D[15:0] driven (read cycle)

D[15:0] setup to rising edge -WAIT (read cycle)

Rising edge of -OE to D[15:0] tri-state (read cycle)

1. If the S1D13505 host interface is disabled, the timing for -WAIT driven low is relative to the

falling edge of -OE, -WE or the first positive edge of CLK after A[20:0], M/R# becomes valid,

whichever one is later.

2. If the S1D13505 host interface is disabled, the timing for D[15:0] driven is relative to the fall-

ing edge of -OE or the first positive edge of CLK after A[20:0], M/R# becomes valid, which-

ever one is later.

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7.1.6 Generic Interface Timing

CLK

A[20:0]

M/R#

CS#

RD0#,RD1#

WE0#,WE1#

WAIT#

D[15:0](write)

D[15:0](read)

t10

t11

t13

t12

Figure 7-6: Generic Timing

Note

The above timing diagram is not applicable if the BUSCLK divided by 2 configuration option is

selected.

S1D13505

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Hardware Functional Specification

Issue Date: 01/02/02

Epson Research and Development

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Table 7-6: Generic Timing

Parameter

3.0V

5.0V

Symbol

Min

Max

Min

Max Units

Clock period

Clock pulse width high

Clock pulse width low

A[20:0], M/R# setup to first CLK where CS# = 0 and either

RD0#,RD1#,WE0# or WE1# = 0

A[20:0], M/R# hold from rising edge of either RD0#,RD1#,WE0# or

WE1# = 0

CS# hold from rising edge of either RD0#,RD1#,WE0# or WE1# = 0

Falling edge of either RD0#,RD1#,WE0# or WE1# to WAIT# driven low

Rising edge of either RD0#,RD1#,WE0# or WE1# to WAIT# tri-state

2.5

D[15:0] setup to third CLK where CS# = 0 and WE0#,WE1# = 0 (write

cycle)

t10

D[15:0] hold (write cycle)

t11

t12

t13

Falling edge RD0#,RD1# to D[15:0] driven (read cycle)

D[15:0] setup to rising edge WAIT# (read cycle)

Rising edge of RD0#,RD1# to D[15:0] tri-state (read cycle)

1. If the S1D13505 host interface is disabled, the timing for WAIT# driven low is relative to the

falling edge of RD0#, RD1#, WE0#, WE1# or the first positive edge of CLK after A[20:0],

M/R# becomes valid, whichever one is later.

2. If the S1D13505 host interface is disabled, the timing for D[15:0] driven is relative to the fall-

ing edge of RD0#, RD1# or the first positive edge of CLK after A[20:0], M/R# becomes valid,

whichever one is later.

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7.1.7 MIPS/ISA Interface Timing

BUSCLK

LatchA20

SA[19:0]

M/R#, SBHE#

CS#

MEMR#

MEMW#

IOCHRDY

t10

SD[15:0](write)

SD[15:0](read)

t11

t12

t13

Figure 7-7: MIPS/ISA Timing

Note

The above timing diagram is not applicable if the BUSCLK divided by 2 configuration option is

selected.

S1D13505

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Hardware Functional Specification

Issue Date: 01/02/02

Epson Research and Development

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Table 7-7: MIPS/ISA Timing

Parameter

3.0V

5.0V

Symbol

Min

Max

Min

Max

Units

Clock period

Clock pulse width high

Clock pulse width low

LatchA20, SA[19:0], M/R#, SBHE# setup to first BUSCLK where

CS# = 0 and either MEMR# = 0 or MEMW# = 0

LatchA20, SA[19:0], M/R#, SBHE# hold from rising edge of

either MEMR# or MEMW#

CS# hold from rising edge of either MEMR# or MEMW#

Falling edge of either MEMR# or MEMW# to IOCHRDY# driven

low

2.5

Rising edge of either MEMR# or MEMW# to IOCHRDY# tri-state

SD[15:0] setup to third BUSCLK where CS# = 0 MEMW# = 0

(write cycle)

t10

SD[15:0] hold (write cycle)

t11

t12

t13

Falling edge MEMR# to SD[15:0] driven (read cycle)

SD[15:0] setup to rising edge IOCHRDY# (read cycle)

Rising edge of MEMR# toSD[15:0] tri-state (read cycle)

1. If the S1D13505 host interface is disabled, the timing for IOCHRDY driven low is relative to

the falling edge of MEMR#, MEMW# or the first positive edge of BUSCLK after LatchA20,

SA[19:0], M/R# becomes valid, whichever one is later.

2. If the S1D13505 host interface is disabled, the timing for SD[15:0] driven is relative to the

falling edge of MEMR# or the first positive edge of BUSCLK after LatchA20, SA[19:0],

M/R# becomes valid, whichever one is later.

Hardware Functional Specification

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7.1.8 Philips Interface Timing (e.g. PR31500/PR31700)

DCLKOUT

ADDR[12:0]

ALE

-CARDREG

-CARDxCSH

-CARDxCSL

-CARDIORD

-CARDIOWR

-WE -RD

t10

-CARDxWAIT

D[31:16](write)

D[31:16](read)

t11

t13

t12

t15

t14

Figure 7-8: Philips Timing

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Table 7-8: Philips Timing

Parameter

3.0V

5.0V

Symbol

Min

13.3

Max

Min

13.3

Max

Units

Clock period

Clock pulse width low

Clock pulse width high

ADDR[12:0] setup to first CLK of cycle

ADDR[12:0] hold from command invalid

ADDR[12:0] setup to falling edge ALE

ADDR[12:0] hold from falling edge ALE

-CARDREG hold from command invalid

Falling edge of chip select to -CARDxWAIT driven

Command invalid to -CARDxWAIT tri-state

D[31:16] valid to first CLK of cycle (write cycle)

D[31:16] hold from rising edge of -CARDxWAIT

Chip select to D[31:16] driven (read cycle)

D[31:16] setup to rising edge -CARDxWAIT (read cycle)

Command invalid to D[31:16] tri-state (read cycle)

t10

t11

t12

2.5

t13

t14

t15

2.5

1. If the S1D13505 host interface is disabled, the timing for -CARDxWAIT driven is relative to

the falling edge of chip select or the second positive edge of DCLKOUT after ADDR[12:0]

becomes valid, whichever one is later.

2. If the S1D13505 host interface is disabled, the timing for D[31:16] driven is relative to the

falling edge of chip select or the second positive edge of DCLKOUT after ADDR[12:0] be-

comes valid, whichever one is later.

Note

The Philips interface has different clock input requirements as follows:

PWH

PWL

90%

10%

OSC

Figure 7-9: Clock Input Requirement

Table 7-9: Clock Input Requirements for BUSCLK using Philips local bus

Symbol

Parameter

Input Clock Period)

Min

13.3

Max

Units

OSC

Input Clock Pulse Width High

Input Clock Pulse Width Low

PWH

PWL

Input Clock Fall Time (10% - 90%)

Input Clock Rise Time (10% - 90%)

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7.1.9 Toshiba Interface Timing (e.g. TX3912)

DCLKOUT

ADDR[12:0]

ALE

CARDREG*

CARDxCSH*

CARDxCSL*

CARDIORD*

CARDIOWR*

WE* RD*

t10

CARDxWAIT*

D[31:16](write)

D[31:16](read)

t11

t13

t12

t15

t14

Figure 7-10: Toshiba Timing

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Table 7-10: Toshiba Timing

Parameter

3.0V

5.0V

Symbol

Min

13.3

5.4

Max

Min

13.3

5.4

Max

Units

Clock period

Clock pulse width low

Clock pulse width high

ADDR[12:0] setup to first CLK of cycle

ADDR[12:0] hold from command invalid

ADDR[12:0] setup to falling edge ALE

ADDR[12:0] hold from falling edge ALE

CARDREG* hold from command invalid

Falling edge of chip select to CARDxWAIT* driven

Command invalid to CARDxWAIT* tri-state

D[31:16] valid to first CLK of cycle (write cycle)

D[31:16] hold from rising edge of CARDxWAIT*

Chip select to D[31:16] driven (read cycle)

D[31:16] setup to rising edge CARDxWAIT* (read cycle)

Command invalid to D[31:16] tri-state (read cycle)

t10

t11

t12

2.5

t13

t14

t15

2.5

1. If the S1D13505 host interface is disabled, the timing for CARDxWAIT* driven is relative to

the falling edge of chip select or the second positive edge of DCLKOUT after ADDR[12:0]

becomes valid, whichever one is later.

2. If the S1D13505 host interface is disabled, the timing for D[31:16] driven is relative to the

falling edge of chip select or the second positive edge of DCLKOUT after ADDR[12:0] be-

comes valid, whichever one is later.

Note

The Toshiba interface has different clock input requirements as follows:

PWH

PWL

90%

10%

OSC

Figure 7-11: Clock Input Requirement

Table 7-11: Clock Input Requirements for BUSCLK using Toshiba local bus

Symbol

Parameter

Input Clock Period)

Min

13.3

5.4

Max

Units

OSC

Input Clock Pulse Width High

Input Clock Pulse Width Low

PWH

5.4

PWL

Input Clock Fall Time (10% - 90%)

Input Clock Rise Time (10% - 90%)

Hardware Functional Specification

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7.1.10 Power PC Interface Timing (e.g. MPC8xx, MC68040, Coldfire)

CLKOUT

A[11:31], RD/WR#

TSIZ[0:1], M/R#

CS#

TS#

TA#

t11

t12 t13

t15 t16

t10

t14

BI#

t17

t18

D[0:15](write)

t19

t20

t21

D[0:15](read)

Figure 7-12: Power PC Timing

Note

The above timing diagram is not applicable if the BUSCLK divided by 2 configuration option is

selected.

S1D13505

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Hardware Functional Specification

Issue Date: 01/02/02

Epson Research and Development

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Table 7-12: Power PC Timing

Parameter

3.0V

5.0V

Symbol

Min

Max

Min

Max

Units

Clock period

Clock pulse width low

Clock pulse width high

AB[11:31], RD/WR#, TSIZ[0:1], M/R# setup

AB[11:31], RD/WR#, TSIZ[0:1], M/R# hold

CS# setup

CS# hold

TS# setup

TS# hold

t10

t11

t12

t13

t14

t15

t16

t17

t18

t19

t20

t21

CLKOUT to TA# driven

19.7

CLKOUT to TA# low

CLKOUT to TA# high

2.5

negative edge CLKOUT to TA# tri-state

CLKOUT to BI# driven

CLKOUT to BI# high

2.5

negative edge CLKOUT to BI# tri-state

D[0:15] setup to 2nd CLKOUT after TS# = 0 (write cycle)

D[0:15] hold (write cycle)

CLKOUT to D[0:15] driven (read cycle)

D[0:15] valid to TA# falling edge (read cycle)

CLKOUT to D[0:15] tri-state (read cycle)

2.5

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7.2 Clock Input Requirements

PWH

PWL

90%

10%

OSC

Figure 7-13: Clock Input Requirement

Table 7-13: Clock Input Requirements for CLKI divided down internally (MCLK = CLKI/2)

Symbol

Parameter

Min

12.5

5.6

Max

Units

Input Clock Period

OSC

Input Clock Pulse Width High

Input Clock Pulse Width Low

PWH

5.6

PWL

Input Clock Fall Time (10% - 90%)

Input Clock Rise Time (10% - 90%)

Table 7-14: Clock Input Requirements for CLKI

Symbol

Parameter

Min

Max

Units

Input Clock Period

OSC

11.3

Input Clock Pulse Width High

Input Clock Pulse Width Low

PWH

PWL

Input Clock Fall Time (10% - 90%)

Input Clock Rise Time (10% - 90%)

Note

When CLKI is more than 40MHz, REG[19h] bit 2 must be set to 1 (MCLK = CLKI/2).

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7.3 Memory Interface Timing

7.3.1 EDO-DRAM Read/Write/Read-Write Timing

Memory

Clock

RAS#

t5 t6

CAS#

t10

t11 t10 t11

t12

t13

WE# (read)

MD (read)

t17

t15

t14

t16

t18

t19

WE#(write)

MD(write)

t20 t21

t22

Figure 7-14: EDO-DRAM Read/Write Timing

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Memory

Clock

RAS#

CAS#

t5 t6

t10 t11

t12

t19

t23

t24

WE#

t15

t14

t25

t26

MD(Read)

MD(Write)

t20 t21

t22

Figure 7-15: EDO-DRAM Read-Write Timing

Table 7-15: EDO-DRAM Read/Write/Read-Write Timing

Symbol

Parameter

Min

Max

Units

Internal memory clock period

Random read cycle REG[22h] bit 6-5 == 00

Random read cycle REG[22h] bit 6-5 == 01

Random read cycle REG[22h] bit 6-5 == 10

RAS# precharge time (REG[22h] bits 3-2 = 00)

RAS# precharge time (REG[22h] bits 3-2 = 01)

RAS# precharge time (REG[22h] bits 3-2 = 10)

5t1

4t1

3t1

2t1 - 3

1.45 t1 - 3

1t1 - 3

RAS# to CAS# delay time (REG[22h] bit 4 = 0 and

bits 3-2 = 00 or 10)

2t1 - 3

1t1 - 3

RAS# to CAS# delay time (REG[22h] bit 4 = 1 and

bits 3-2 = 00 or 10)

RAS# to CAS# delay time (REG[22h] bits 3-2 = 01)

CAS# precharge time

1.45 t1 - 3

0.45 t1 - 3

1 t1 - 3

CAS# pulse width

RAS# hold time

Row address setup time (REG[22h] bits 3-2 = 00)

Row address setup time (REG[22h] bits 3-2 = 01)

Row address setup time (REG[22h] bits 3-2 = 10)

2.45 t1

2 t1

1.45 t1

Row address hold time (REG[22h] bits 3-2 = 00 or

10)

0.45 t1 - 3

Row address hold time (REG[22h] bits 3-2 = 01)

Column address setup time

1 t1 - 3

t10

t11

0.45 t1 - 3

Column address hold time

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Table 7-15: EDO-DRAM Read/Write/Read-Write Timing

Symbol

Parameter

Read Command Setup (REG[22h] bit 4 = 0 and bits

3-2 = 00)

Min

Max

Units

4.45 t1 - 3

Read Command Setup (REG[22h] bit 4 = 0 and bits

3-2 = 10)

3.45 t1 - 3

t12

Read Command Setup (REG[22h] bit 4 = 1 and bits

3-2 = 00)

Read Command Setup (REG[22h] bit 4 = 1 and bits

3-2 = 10)

2.45 t1 - 3

3.45 t1 - 3

Read Command Setup (REG[22h] bits 3-2 = 01)

Read Command Hold (REG[22h] bit 4 = 0 and bits 3-

2 = 00)

Read Command Hold (REG[22h] bit 4 = 0 and bits 3-

2 = 10)

2.45 t1 - 3

1.45 t1 - 3

t13

Read Command Hold (REG[22h] bit 4 = 1 and bits 3-

2 = 00)

Read Command Hold (REG[22h] bit 4 = 1 and bits 3-

2 = 10)

Read Command Hold (REG[22h] bits 3-2 = 01)

Read Data Setup referenced from CAS#

Read Data Hold referenced from CAS#

Last Read Data Setup referenced from RAS#

Bus Turn Off from RAS#

2.45 t1 - 3

t14

t15

t16

t17

t18

t19

t20

t21

t22

t23

t24

t1- 5

Write Command Setup

0.45 t1- 3

0.45 t1 - 3

0.45 t1

1 t1 - 3

1.45 t1- 3

Write Command Hold

Write Data Setup

Write Data Hold

MD Tri-state

0.45t1 + 21

CAS# to WE# active during Read-Write cycle

Write Command Setup during Read-Write cycle

Last Read Data Setup referenced from WE# during

Read-Write cycle

t25

t26

Bus Tri-state from WE# during Read-Write cycle

t1- 5

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7.3.2 EDO-DRAM CAS Before RAS Refresh Timing

Memory

Clock

RAS#

CAS#

Figure 7-16: EDO-DRAM CAS Before RAS Refresh Timing

Table 7-16: EDO-DRAM CAS Before RAS Refresh Timing

Symbol

Parameter

Internal memory clock period

Min

Max

Units

RAS# precharge time (REG[22h] bits 3-2 = 00)

RAS# precharge time (REG[22h] bits 3-2 = 01)

RAS# precharge time (REG[22h] bits 3-2 = 10)

2t1 - 3

1.45t1 - 3

1t1 - 3

RAS# pulse width (REG[22h] bit 6-5 = 00 and bits 3-2

= 00)

3 t1 - 3

3.45 t1 - 3

4 t1 - 3

RAS# pulse width (REG[22h] bit 6-5 = 00 and bits 3-2

= 01)

RAS# pulse width (REG[22h] bit 6-5 = 00 and bits 3-2

= 10)

RAS# pulse width (REG[22h] bit 6-5 = 01 and bits 3-2

= 00)

2 t1 - 3

RAS# pulse width (REG[22h] bit 6-5 = 01 and bits 3-2

= 01)

2.45 t1 - 3

3 t1 - 3

RAS# pulse width (REG[22h] bit 6-5 = 01 and bits 3-2

= 10)

RAS# pulse width (REG[22h] bit 6-5 = 10 and bits 3-2

= 00)

1 t1 - 3

RAS# pulse width (REG[22h] bit 6-5 = 10 and bits 3-2

= 01)

1.45 t1 - 3

2 t1 - 3

RAS# pulse width (REG[22h] bit 6-5 = 10 and bits 3-2

= 10)

CAS# pulse width

CAS# setup time (REG[22h] bits 3-2 = 00 or 10)

0.45 t1 - 3

1 t1 - 3

CAS# setup time (REG[22h] bits 3-2 = 01)

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Table 7-16: EDO-DRAM CAS Before RAS Refresh Timing

Symbol

Parameter

Min

Max

Units

CAS# Hold to RAS# (REG[22h] bit 6-5 = 00 and bits

3-2 = 00)

2.45 t1 - 3

CAS# Hold to RAS# (REG[22h] bit 6-5 = 00 and bits

3-2 = 01)

3 t1 - 3

3.45 t1 - 3

1.45 t1 - 3

2 t1 - 3

CAS# Hold to RAS# (REG[22h] bit 6-5 = 00 and bits

3-2 = 10)

CAS# Hold to RAS# (REG[22h] bit 6-5 = 01 and bits

3-2 = 00)

CAS# Hold to RAS# (REG[22h] bit 6-5 = 01 and bits

3-2 = 01)

CAS# Hold to RAS# (REG[22h] bit 6-5 = 01 and bits

3-2 = 10)

2.45 t1 - 3

0.45 t1 - 3

1 t1 - 3

CAS# Hold to RAS# (REG[22h] bit 6-5 = 10 and bits

3-2 = 00)

CAS# Hold to RAS# (REG[22h] bit 6-5 = 10 and bits

3-2 = 01)

CAS# Hold to RAS# (REG[22h] bit 6-5 = 10 and bits

3-2 = 10)

1.45 t1 - 3

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7.3.3 EDO-DRAM Self-Refresh Timing

Restarted for

active mode

Stopped for

suspend mode

Memory

Clock

RAS#

CAS#

Figure 7-17: EDO-DRAM Self-Refresh Timing

Table 7-17: EDO-DRAM Self-Refresh Timing

Symbol

Parameter

Min

Max

Units

Internal memory clock period

RAS# precharge time (REG[22h] bits 3-2 = 00)

RAS# precharge time (REG[22h] bits 3-2 = 01)

RAS# precharge time (REG[22h] bits 3-2 = 10)

RAS# to CAS# precharge time (REG[22h] bits 3-2 = 00)

RAS# to CAS# precharge time (REG[22h] bits 3-2 = 01 or 10)

2 t1 - 3

1.45t1 - 3

1 t1 - 3

1.45t1 - 3

0.45t1 - 3

CAS# setup time (REG[22h] bits 3-2 = 00 or 10)

1 t1 - 3

2 t1 - 3

1 t1 - 3

CAS# setup time (REG[22h] bits 3-2 = 01)

CAS# precharge time (REG[22h] bits 3-2 = 00)

CAS# precharge time (REG[22h] bits 3-2 = 01 or 10)

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7.3.4 FPM-DRAM Read/Write/Read-Write Timing

Memory

Clock

RAS#

t5 t6

CAS#

t11 t10 t11

t10

t12

t13

WE#(read)

MD(read)

t14

t15

t16

t17

t20

WE#(write)

MD(write)

t18 t19

Figure 7-18: FPM-DRAM Read/Write Timing

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Memory

Clock

RAS#

CAS#

t10 t11

t12

t17

t21 t16

WE#

t14

t15

MD(read)

MD(write)

t18 t19

t20

Figure 7-19: FPM-DRAM Read-Write Timing

Table 7-18: FPM-DRAM Read/Write/Read-Write Timing

Symbol

Parameter

Min

Max

Units

Internal memory clock period

Random read cycle REG[22h] bit 6-5 == 00

Random read cycle REG[22h] bit 6-5 == 01

Random read cycle REG[22h] bit 6-5 == 10

RAS# precharge time (REG[22h] bits 3-2 = 00)

RAS# precharge time (REG[22h] bits 3-2 = 01)

RAS# precharge time (REG[22h] bits 3-2 = 10)

5t1

4t1

3t1

2 t1 - 3

1.45 t1 - 3

1 t1 - 3

RAS# to CAS# delay time (REG[22h] bit 4 = 1 and

bits 3-2 = 00 or 10)

1.45 t1 - 3

2.45 t1 - 3

1t1 - 3

RAS# to CAS# delay time (REG[22h] bit 4 = 0 and

bits 3-2 = 00 or 10)

RAS# to CAS# delay time (REG[22h] bit 4 = 1 and

bits 3-2 = 01)

RAS# to CAS# delay time (REG[22h] bit 4 = 0 and

bits 3-2 = 01)

2t1 - 3

CAS# precharge time

0.45 t1 - 3

2 t1 - 3

CAS# pulse width

RAS# hold time

Row address setup time (REG[22h] bits 3-2 = 00)

Row address setup time (REG[22h] bits 3-2 = 01)

Row address setup time (REG[22h] bits 3-2 = 10)

1.45 t1 - 3

1 t1 - 3

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Table 7-18: FPM-DRAM Read/Write/Read-Write Timing

Symbol

Parameter

Row address hold time (REG[22h] bits 3-2 = 00 or

10)

Min

Max

Units

t1 - 3

Row address hold time (REG[22h] bits 3-2 = 01)

Column address setup time

Column address hold time

0.45 1t1 - 3

0.45 t1 - 3

t10

t11

Read Command Setup (REG[22h] bit 4 = 0 and bits

3-2 = 00)

4.45 t1 - 3

3.45 t1 - 3

2.45 t1 - 3

4 t1 - 3

Read Command Setup (REG[22h] bit 4 = 0 and bits

3-2 = 01 or 10)

t12

Read Command Setup (REG[22h] bit 4 = 1 and bits

3-2 = 00)

Read Command Setup (REG[22h] bit 4 = 1 and bits

3-2 = 01 or 10)

Read Command Hold (REG[22h] bit 4 = 0 and bits 3-

2 = 00)

Read Command Hold (REG[22h] bit 4 = 0 and bits 3-

2 = 01 or 10)

3 t1 - 3

t13

Read Command Hold (REG[22h] bit 4 = 1 and bits 3-

2 = 00)

3 t1 - 3

Read Command Hold (REG[22h] bit 4 = 1 and bits 3-

2 = 01 or 10)

2 t1 - 3

t14

t15

t16

t17

t18

t19

t20

t21

Read Data Setup referenced from CAS#

Bus Tri-State

t1- 5

Write Command Setup

Write Command Hold

Write Data Setup

0.45 t1- 3

0.45 t1 - 3

0.45 t1

Write Data Hold

MD Tri-state

0.45t1 + 21

CAS# to WE# active during Read-Write cycle

0.45 t1 - 3

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7.3.5 FPM-DRAM CAS Before RAS Refresh Timing

Memory

Clock

RAS#

CAS#

Figure 7-20: FPM-DRAM CAS Before RAS Refresh Timing

Table 7-19: FPM-DRAM CAS Before RAS Refresh Timing

Symbol

Parameter

Internal memory clock period

Min

Max

Units

RAS# precharge time (REG[22h] bits 3-2 = 00)

2.45 t1 - 3

1.45 t1 - 3

RAS# precharge time (REG[22h] bits 3-2 = 01 or 10)

RAS# pulse width (REG[22h] bits 6-5 = 00 and bits 3-

2 = 00)

2.45 t1 - 3

3.45 t1 - 3

1.45 t1 - 3

2.45 t1 - 3

0.45 t1 - 3

1.45 t1 - 3

RAS# pulse width (REG[22h] bits 6-5 = 00 and bits 3-

2 = 01 or 10)

RAS# pulse width (REG[22h] bits 6-5 = 01 and bits 3-

2 = 00)

RAS# pulse width (REG[22h] bits 6-5 = 01 and bits 3-

2 = 01 or 10)

RAS# pulse width (REG[22h] bits 6-5 = 10 and bits 3-

2 = 00)

RAS# pulse width (REG[22h] bits 6-5 = 10 and bits 3-

2 = 01 or 10)

CAS# pulse width (REG[22h] bits 3-2 = 00)

CAS# pulse width (REG[22h] bits 3-2 = 01 or 10)

CAS# Setup to RAS#

2 t1 - 3

1 t1 - 3

0.45 t1 - 3

CAS# Hold to RAS# (REG[22h] bits 6-5 = 00 and bits

3-2 = 00)

2.45 t1 - 3

3.45 t1 - 3

1.45 t1 - 3

2.45 t1 - 3

0.45 t1 - 3

1.45 t1 - 3

CAS# Hold to RAS# (REG[22h] bits 6-5 = 00 and bits

3-2 = 01 or 10)

CAS# Hold to RAS# (REG[22h] bits 6-5 = 01 and bits

3-2 = 00)

CAS# Hold to RAS# (REG[22h] bits 6-5 = 01 and bits

3-2 = 01 or 10)

CAS# Hold to RAS# (REG[22h] bits 6-5 = 10 and bits

3-2 = 00)

CAS# Hold to RAS# (REG[22h] bits 6-5 = 10 and bits

3-2 = 01 or 10)

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7.3.6 FPM-DRAM Self-Refresh Timing

Restarted for

active mode

Stopped for

suspend mode

Memory

Clock

RAS#

CAS#

Figure 7-21: FPM-DRAM Self-Refresh Timing

Table 7-20: FPM-DRAM CBR Self-Refresh Timing

Symbol

Parameter

Min

Max

Units

Internal memory clock

RAS# precharge time (REG[22h] bits 3-2 = 00)

2.45 t1 - 1

1.45 t1 - 1

2 t1

RAS# precharge time (REG[22h] bits 3-2 = 01 or 10)

RAS# to CAS# precharge time (REG[22h] bits 3-2 = 00)

RAS# to CAS# precharge time (REG[22h] bits 3-2 = 01 or 10)

1 t1

0.45 t1 - 2

CAS# setup time (CAS# before RAS# refresh)

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7.4 Power Sequencing

7.4.1 LCD Power Sequencing

SUSPEND# or

LCD Enable Bit

LCDPWR

FPFRAME

FPLINE

FPSHIFT

FPDATA

DRDY

CLKI

Figure 7-22: LCD Panel Power Off / Power On Timing. Drawn with LCDPWR set to active high polarity

Table 7-21: LCD Panel Power Off/ Power On

Symbol

Parameter

Min

Max

Units

FPFRAME

SUSPEND# or LCD ENABLE BIT low to LCDPWR off

PCLK

Frames

SUSPEND# or LCD ENABLE BIT low to FPFRAME inactive

FPFRAME inactive to FPLINE, FPSHIFT, FPDATA, DRDY inactive

SUSPEND# to CLKI inactive

128

130

SUSPEND# or LCD ENABLE BIT high to FPLINE, FPSHIFT,

FPDATA, DRDY active

FPFRAME

PCLK

FPLINE, FPSHIFT, FPDATA, DRDY active to LCDPWR, on and

FPFRAME active

128

Frames

CLKI active to SUSPEND# inactive

Note

Where T_FPFRAMEis the period of FPFRAME and T_PCLKis the period of the pixel clock.

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7.4.2 Power Save Status

Power Save

Power Save Status Bit

Memory Access

allowed

not allowed

allowed

Figure 7-23: Power Save Status and Local Bus Memory Access Relative to Power Save Mode

Note

Power Save can be initiated through either the SUSPEND# pin or Software Suspend Enable Bit.

Table 7-22: Power Save Status and Local Bus Memory Access Relative to Power Save Mode

Symbol

Parameter

Min

Max

130

Units

Frames

MCLK

Power Save initiated to rising edge of Power Save Status and the

last time memory access by the local bus may be performed.

129

Power Save deactivated to falling edge of Power Save Status

Falling edge of Power Save Status to the earliest time the local bus

may perform a memory access

Note

It is recommended that memory access not be performed after a Power Save Mode has been

initiated.

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7.5 Display Interface

7.5.1 4-Bit Single Monochrome Passive LCD Panel Timing

VDP

VNDP

FPFRAME

FPLINE

MOD

LINE1

LINE2

LINE3

LINE4

LINE239 LINE240

LINE1

LINE2

UD[3:0]

FPLINE

MOD

HDP

HNDP

FPSHIFT

UD3

1-317

1-318

1-319

1-320

1-1

1-2

1-3

1-4

1-5

1-6

UD2

UD1

1-7

1-8

UD0

* Diagram drawn with 2 FPLINE vertical blank period

Example timing for a 320x240 panel

Figure 7-24: 4-Bit Single Monochrome Passive LCD Panel Timing

VDP =

VNDP = Vertical Non-Display Period

HDP = Horizontal Display Period

Vertical Display Period

= (REG[09h] bits [1:0], REG[08h] bits [7:0]) + 1

= (REG[0Ah] bits [5:0]) + 1

= ((REG[04h] bits [6:0]) + 1)*8Ts

= ((REG[05h] bits [4:0]) + 1)*8Ts

HNDP = Horizontal Non-Display Period

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Sync Timing

FPFRAME

FPLINE

MOD

Data Timing

FPLINE

t10

t11

t12

FPSHIFT

UD[3:0]

t13

t14

Figure 7-25: 4-Bit Single Monochrome Passive LCD Panel A.C. Timing

Table 7-23: 4-Bit Single Monochrome Passive LCD Panel A.C. Timing

Symbol

Parameter

FPFRAME setup to FPLINE pulse trailing edge

FPFRAME hold from FPLINE pulse trailing edge

FPLINE pulse width

Min

Typ

Max

Units

note 2

Ts (note 1)

note 3

FPLINE period

note 4

MOD transition to FPLINE pulse trailing edge

FPSHIFT falling edge to FPLINE pulse leading edge

FPLINE pulse trailing edge to FPSHIFT falling edge

FPSHIFT period

note 5

t10 + t11

note 6

FPSHIFT falling edge to FPLINE pulse trailing edge

FPLINE pulse trailing edge to FPSHIFT rising edge

FPSHIFT pulse width high

t10

t11

t12

t13

t14

FPSHIFT pulse width low

UD[3:0] setup to FPSHIFT falling edge

UD[3:0] hold to FPSHIFT falling edge

1. Ts

= pixel clock period = memory clock, [memory clock]/2, [memory clock]/3, [memory clock]/4 (see REG[19h] bits [1:0])

= t4 - 14Ts

2. t1

3. t4

4. t5

5. t6

6. t9

min

= [((REG[04h] bits [6:0])+1)*8 + ((REG[05h] bits [4:0]) + 1)*8] + 33 Ts

= [(((REG[04h] bits [6:0])+1)*8 + ((REG[05h] bits [4:0]) + 1)*8)-1] Ts

= [((REG[05h] bits [4:0]) + 1)*8 - 27] Ts

= [((REG[05h] bits [4:0]) + 1)*8 - 18] Ts

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7.5.2 8-Bit Single Monochrome Passive LCD Panel Timing

VDP

VNDP

FPFRAME

FPLINE

MOD

LINE1

LINE2

LINE3

LINE4

LINE479 LINE480

LINE1

LINE2

UD[3:0], LD[3:0]

FPLINE

MOD

HDP

HNDP

FPSHIFT

1-633

1-634

1-635

1-636

1-637

1-638

1-639

1-640

1-1

1-2

1-3

1-4

1-5

1-9

UD3

UD2

1-10

1-11

1-12

1-13

UD1

UD0

LD3

1-6

1-7

1-14

1-15

LD2

LD1

LD0

1-8

1-16

* Diagram drawn with 2 FPLINE vertical blank period

Example timing for a 640x480 panel

Figure 7-26: 8-Bit Single Monochrome Passive LCD Panel Timing

VDP

VNDP = Vertical Non-Display Period

HDP = Horizontal Display Period

= Vertical Display Period

= (REG[09h] bits [1:0], REG[08h] bits [7:0]) + 1

= (REG[0Ah] bits [5:0]) + 1

= ((REG[04h] bits [6:0]) + 1)*8Ts

= ((REG[05h] bits [4:0]) + 1)*8Ts

HNDP = Horizontal Non-Display Period

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Sync Timing

FPFRAME

FPLINE

MOD

Data Timing

FPLINE

t10

t11

t12

FPSHIFT

t13

t14

UD[3:0]

LD[3:0]

Figure 7-27: 8-Bit Single Monochrome Passive LCD Panel A.C. Timing

Table 7-24: 8-Bit Single Monochrome Passive LCD Panel A.C. Timing

Symbol

Parameter

Min

Typ

Max

Units

note 2

FPFRAME setup to FPLINE pulse trailing edge

FPFRAME hold from FPLINE pulse trailing edge

FPLINE pulse width

Ts (note 1)

note 3

FPLINE period

note 4

MOD transition to FPLINE pulse trailing edge

FPSHIFT falling edge to FPLINE pulse leading edge

FPLINE pulse trailing edge to FPSHIFT falling edge

FPSHIFT period

note 5

t10 + t11

note 6

FPSHIFT falling edge to FPLINE pulse trailing edge

FPLINE pulse trailing edge to FPSHIFT rising edge

FPSHIFT pulse width high

t10

t11

t12

t13

t14

FPSHIFT pulse width low

UD[3:0], LD[3:0] setup to FPSHIFT falling edge

UD[3:0], LD[3:0] hold to FPSHIFT falling edge

1. Ts

= pixel clock period = memory clock, [memory clock]/2, [memory clock]/3, [memory clock]/4 (see REG[19h] bits [1:0])

= t4 - 14Ts

2. t1

3. t4

4. t5

5. t6

6. t9

min

= [((REG[04h] bits [6:0])+1)*8 + ((REG[05h] bits [4:0]) + 1)*8] + 33 Ts

= [(((REG[04h] bits [6:0])+1)*8 + ((REG[05h] bits [4:0]) + 1)*8)-1] Ts

= [((REG[05h] bits [4:0]) + 1)*8 - 25] Ts

= [((REG[05h] bits [4:0]) + 1)*8 - 16] Ts

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7.5.3 4-Bit Single Color Passive LCD Panel Timing

VNDP

VDP

FPFRAME

FPLINE

MOD

LINE1

LINE2

LINE3

LINE4

LINE479 LINE480

LINE1

LINE2

UD[3:0]

FPLINE

MOD

HDP

HNDP

FPSHIFT

1-R1 1-G2 1-B3

1-B319

UD3

UD2

UD1

UD0

1-R320

1-G320

1-B320

1-G1 1-B2

1-R4

1-G4

1-B1

1-R2

1-R3

1-G3 1-B4

* Diagram drawn with 2 FPLINE vertical blank period

Example timing for a 640x480 panel

Figure 7-28: 4-Bit Single Color Passive LCD Panel Timing

VDP

VNDP = Vertical Non-Display Period

HDP = Horizontal Display Period

= Vertical Display Period

= (REG[09h] bits [1:0], REG[08h] bits [7:0]) + 1

= (REG[0Ah] bits [5:0]) + 1

= ((REG[04h] bits [6:0]) + 1)*8Ts

= ((REG[05h] bits [4:0]) + 1)*8Ts

HNDP = Horizontal Non-Display Period

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Sync Timing

FPFRAME

FPLINE

MOD

Data Timing

FPLINE

t10

t11

t12

FPSHIFT

UD[3:0]

t13

t14

Figure 7-29: 4-Bit Single Color Passive LCD Panel A.C. Timing

Table 7-25: 4-Bit Single Color Passive LCD Panel A.C. Timing

Symbol

Parameter

Min

note 2

Typ

Max

Units

FPFRAME setup to FPLINE pulse trailing edge

FPFRAME hold from FPLINE pulse trailing edge

FPLINE pulse width

Ts (note 1)

note 3

FPLINE period

note 4

MOD transition to FPLINE pulse trailing edge

FPSHIFT falling edge to FPLINE pulse leading edge

FPLINE pulse trailing edge to FPSHIFT falling edge

FPSHIFT period

note 5

t10 + t11

note 6

FPSHIFT falling edge to FPLINE pulse trailing edge

FPLINE pulse trailing edge to FPSHIFT rising edge

FPSHIFT pulse width high

t10

t11

t12

t13

t14

0.45

FPSHIFT pulse width low

UD[3:0], setup to FPSHIFT falling edge

UD[3:0], hold from FPSHIFT falling edge

1. Ts

= pixel clock period = memory clock, [memory clock]/2, [memory clock]/3, [memory clock]/4 (see REG[19h] bits [1:0])

= t4 - 14Ts

2. t1

3. t4

4. t5

5. t6

6. t9

min

= [((REG[04h] bits [6:0])+1)*8 + ((REG[05h] bits [4:0]) + 1)*8] + 33 Ts

=[(((REG[04h] bits [6:0])+1)*8 + ((REG[05h] bits [4:0]) + 1)*8)-1] Ts

= [((REG[05h] bits [4:0]) + 1)*8 - 28] Ts

= [((REG[05h] bits [4:0]) + 1)*8 - 19] Ts

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7.5.4 8-Bit Single Color Passive LCD Panel Timing (Format 1)

VNDP

VDP

FPFRAME

FPLINE

LINE1

LINE2

LINE3

LINE4

LINE479 LINE480

LINE1

LINE2

UD[3:0], LD[3:0]

FPLINE

HDP

HNDP

FPSHIFT

FPSHIFT2

UD3

UD2

UD1

UD0

LD3

LD2

LD1

LD0

1-R1

1-B1

1-G2

1-R3

1-B3

1-G4

1-G1

1-G6

1-R7

1-B7

1-G8

1-R9

1-B6 1-B11 1-R12

1-G7 1-G12 1-B12

1-R8 1-R13 1-G13

1-B8 1-B13 1-R14

1-G9 1-G14 1-B14

1-R636

1-B636

1-G637

1-R2

1-B2

1-G3

1-R4

1-B4

1-R638

1-B638

1-B9 1-R10 1-R15 1-G15

1-G10 1-B10 1-B15 1-R16

1-R11 1-G11 1-G16 1-B16

1-G639

1-R640

1-B640

1-R5 1-G5

1-B5 1-R6

* Diagram drawn with 2 FPLINE vertical blank period

Example timing for a 640x480 panel

Figure 7-30: 8-Bit Single Color Passive LCD Panel Timing (Format 1)

VDP

= Vertical Display Period

= (REG[09h] bits [1:0], REG[08h] bits [7:0]) + 1

= (REG[0Ah] bits [5:0]) + 1

VNDP

HDP

= Vertical Non-Display Period

= Horizontal Display Period

= Horizontal Non-Display Period

= ((REG[04h] bits [6:0]) + 1)*8Ts

= ((REG[05h] bits [4:0]) + 1)*8Ts

HNDP

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Sync Timing

FPFRAME

FPLINE

Data Timing

t5a

t5b

t8a

t10

t11

FPSHIFT

t8b

FPSHIFT2

t12

t13

UD[3:0]

LD[3:0]

Figure 7-31: 8-Bit Single Color Passive LCD Panel A.C. Timing (Format 1)

Table 7-26: 8-Bit Single Color Passive LCD Panel A.C. Timing (Format 1)

Symbol

Parameter

Min

note 2

Typ

Max

Units

FPFRAME setup to FPLINE pulse trailing edge

FPFRAME hold from FPLINE pulse trailing edge

FPLINE pulse width

Ts (note 1)

note 3

note 4

note 5

FPLINE period

t5a

t5b

FPSHIFT2 falling edge to FPLINE pulse leading edge

FPSHIFT falling edge to FPLINE pulse leading edge

FPLINE pulse trailing edge to FPSHIFT2 rising, FPSHIFT falling

edge

t9 + t10

FPSHIFT2, FPSHIFT period

t8a

t8b

note 6

FPSHIFT falling edge to FPLINE pulse trailing edge

FPSHIFT2 falling edge to FPLINE pulse trailing edge

FPLINE pulse trailing edge to FPSHIFT rising edge

FPSHIFT2, FPSHIFT pulse width high

note 7

t10

t11

t12

t13

FPSHIFT2, FPSHIFT pulse width low

UD[3:0], LD[3:0] setup to FPSHIFT2 rising, FPSHIFT falling edge

UD[3:0], LD[3:0] hold from FPSHIFT2 rising, FPSHIFT falling edge

1. Ts

= pixel clock period = memory clock, [memory clock]/2, [memory clock]/3, [memory clock]/4 (see REG[19h] bits [1:0])

= t4 - 14Ts

2. t1

3. t4

4. t5

5. t5

6. t8

7. t8

min

= [((REG[04h] bits [6:0])+1)*8 + ((REG[05h] bits [4:0]) + 1)*8] Ts

= [((REG[05h] bits [4:0]) + 1)*8 - 27] Ts

= [((REG[05h] bits [4:0]) + 1)*8 - 29] Ts

= [((REG[05h] bits [4:0]) + 1)*8 - 20] Ts

= [((REG[05h] bits [4:0]) + 1)*8 - 18] Ts

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7.5.5 8-Bit Single Color Passive LCD Panel Timing (Format 2)

VDP

VNDP

FPFRAME

FPLINE

MOD

LINE1

LINE2

LINE3

LINE4

LINE479 LINE480

LINE1

LINE2

UD[3:0], LD[3:0]

FPLINE

MOD

HDP

HNDP

FPSHIFT

1-R1

1-G1

1-B1

1-R2

1-G2

1-B2

1-B3

1-R4

1-G4

1-B4

1-R5

1-G5

1-G6

1-G638

1-B638

1-R639

UD3

UD2

UD1

UD0

LD3

LD2

LD1

LD0

1-B6

1-R7

1-G7

1-B7

1-R8

1-G8

1-B8

1-G639

1-B639

1-R640

1-G640

1-B640

1-R3 1-B5

1-G3 1-R6

* Diagram drawn with 2 FPLINE vertical blank period

Example timing for a 640x480 panel

Figure 7-32: 8-Bit Single Color Passive LCD Panel Timing (Format 2)

VDP

= Vertical Display Period

= (REG[09h] bits [1:0], REG[08h] bits [7:0]) + 1

= (REG[0Ah] bits [5:0]) + 1

VNDP

HDP

= Vertical Non-Display Period

= Horizontal Display Period

= Horizontal Non-Display Period

= ((REG[04h] bits [6:0]) + 1)*8Ts

= ((REG[05h] bits [4:0]) + 1)*8Ts

HNDP

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Sync Timing

FPFRAME

FPLINE

MOD

Data Timing

FPLINE

t14

t11

t10

FPSHIFT

t12

t13

UD[3:0]

LD[3:0]

Figure 7-33: 8-Bit Single Color Passive LCD Panel A.C. Timing (Format 2)

Table 7-27: 8-Bit Single Color Passive LCD Panel A.C. Timing (Format 2)

Symbol

Parameter

Min

Typ

Max

Units

note 2

FPFRAME setup to FPLINE pulse trailing edge

FPFRAME hold from FPLINE pulse trailing edge

FPLINE period

Ts (note 1)

note 3

FPLINE pulse width

note 4

MOD transition to FPLINE pulse trailing edge

FPSHIFT falling edge to FPLINE pulse leading edge

FPSHIFT falling edge to FPLINE pulse trailing edge

FPLINE pulse trailing edge to FPSHIFT falling edge

FPSHIFT period

note 5

note 6

t14 + 2

t10

t11

t12

t13

t14

FPSHIFT pulse width low

FPSHIFT pulse width high

UD[3:0], LD[3:0] setup to FPSHIFT falling edge

UD[3:0], LD[3:0] hold to FPSHIFT falling edge

FPLINE pulse trailing edge to FPSHIFT rising edge

1. Ts

= pixel clock period = memory clock, [memory clock]/2, [memory clock]/3, [memory clock]/4 (see REG[19h] bits [1:0])

= t3 - 14Ts

2. t1

3. t3

4. t5

5. t6

6. t7

min

= [((REG[04h] bits [6:0])+1)*8 + ((REG[05h] bits [4:0]) + 1)*8] + 33 Ts

= [(((REG[04h] bits [6:0])+1)*8 + ((REG[05h] bits [4:0]) + 1)*8)-1] Ts

= [((REG[05h] bits [4:0]) + 1)*8 - 28] Ts

= [((REG[05h] bits [4:0]) + 1)*8 - 19] Ts

Hardware Functional Specification

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7.5.6 16-Bit Single Color Passive LCD Panel Timing

VDP

VNDP

FPFRAME

FPLINE

MOD

LINE1

LINE2

LINE3

LINE4

LINE479 LINE480

UD[7:0], LD[7:0]

LINE1

LINE2

FPLINE

MOD

HDP

HNDP

FPSHIFT

1-G6 1-B11

1-G635

1-G636

1-R1

1-B1

UD7

UD6

UD5

UD4

UD3

UD2

UD1

UD0

LD7

LD6

LD5

LD4

LD3

LD2

LD1

LD0

1-G12

1-R13

1-R7

1-B7

1-R637

1-B637

1-G638

1-R639

1-G2

1-R3

1-B3

1-G4

1-G8 1-B13

1-R9 1-G14

1-B9 1-R15

1-G10 1-B15

1-R5

1-B639

1-G640

1-G16

1-R12

1-B12

1-B5 1-R11

1-B6

1-G7

1-R8

1-B8

1-G1

1-R2

1-R636

1-B636

1-G637

1-R638

1-B638

1-B2

1-G3

1-G13

1-R14

1-R4

1-B4

1-G5

1-G9

1-B14

1-G639

1-R640

1-B640

1-R10 1-G15

1-B10

1-R16

1-R6 1-G11 1-B16

* Diagram drawn with 2 FPLINE vertical blank period

Example timing for a 640x480 panel

Figure 7-34: 16-Bit Single Color Passive LCD Panel Timing

VDP

VNDP = Vertical Non-Display Period

HDP = Horizontal Display Period

= Vertical Display Period

= (REG[09h] bits [1:0], REG[08h] bits [7:0]) + 1

= (REG[0Ah] bits [5:0]) + 1

= ((REG[04h] bits [6:0]) + 1)*8Ts

= ((REG[05h] bits [4:0]) + 1)*8Ts

HNDP = Horizontal Non-Display Period

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Sync Timing

FPFRAME

FPLINE

MOD

Data Timing

FPLINE

t10

t14

t11

FPSHIFT

t12

t13

UD[7:0]

LD[7:0]

Figure 7-35: 16-Bit Single Color Passive LCD Panel A.C. Timing

Table 7-28: 16-Bit Single Color Passive LCD Panel A.C. Timing

Symbol

Parameter

Min

Typ

Max

Units

note 2

FPFRAME setup to FPLINE pulse trailing edge

FPFRAME hold from FPLINE pulse trailing edge

FPLINE period

Ts (note 1)

note 3

FPLINE pulse width

note 4

MOD transition to FPLINE pulse trailing edge

FPSHIFT falling edge to FPLINE pulse leading edge

FPSHIFT falling edge to FPLINE pulse trailing edge

FPLINE pulse trailing edge to FPSHIFT falling edge

FPSHIFT period

note 5

note 6

t14 + 3

t10

t11

t12

t13

t14

FPSHIFT pulse width low

FPSHIFT pulse width high

UD[7:0], LD[7:0] setup to FPSHIFT falling edge

UD[7:0], LD[7:0] hold to FPSHIFT falling edge

FPLINE pulse trailing edge to FPSHIFT rising edge

1. Ts

= pixel clock period = memory clock, [memory clock]/2, [memory clock]/3, [memory clock]/4 (see REG[19h] bits [1:0])

= t3 - 14Ts

= [((REG[04h] bits [6:0])+1)*8 + ((REG[05h] bits [4:0]) + 1)*8] + 33 Ts

= [(((REG[04h] bits [6:0])+1)*8 + ((REG[05h] bits [4:0]) + 1)*8)-1] Ts

= [(REG[05h] bits [4:0]) + 1)*8 - 27] Ts

2. t1

3. t3

4. t5

5. t6

6. t7

min

= [((REG[05h] bits [4:0]) + 1)*8 - 18] Ts

Hardware Functional Specification

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7.5.7 8-Bit Dual Monochrome Passive LCD Panel Timing

VDP

VNDP

FPFRAME

FPLINE

MOD

LINE 1/241

LINE 2/242

LINE 3/243

LINE 4/244

LINE 239/479 LINE 240/480

LINE 1/241

LINE 2/242

UD[3:0], LD[3:0]

FPLINE

MOD

HNDP

HDP

FPSHIFT

1-1

1-2

1-3

1-4

1-5

1-6

1-637

UD3

UD2

UD1

UD0

LD3

LD2

LD1

LD0

1-638

1-639

1-7

1-8

1-640

241-1

241-2

241-3

241-4

241-5

241-6

241-7

241-8

241-637

241-638

241-639

241-640

* Diagram drawn with 2 FPLINE vertical blank period

Example timing for a 640x480 panel

Figure 7-36: 8-Bit Dual Monochrome Passive LCD Panel Timing

VDP

= Vertical Display Period

= (REG[09h] bits [1:0], REG[08h] bits [7:0]) + 1

= (REG[0Ah] bits [5:0]) + 1

VNDP

HDP

= Vertical Non-Display Period

= Horizontal Display Period

= Horizontal Non-Display Period

= ((REG[04h] bits [6:0]) + 1)*8Ts

= ((REG[05h] bits [4:0]) + 1)*8Ts

HNDP

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Sync Timing

FPFRAME

FPLINE

MOD

Data Timing

FPLINE

t10

t14

t11

FPSHIFT

t12

t13

UD[3:0]

LD[3:0]

Figure 7-37: 8-Bit Dual Monochrome Passive LCD Panel A.C. Timing

Table 7-29: 8-Bit Dual Monochrome Passive LCD Panel A.C. Timing

Symbol

Parameter

Min

Typ

Max

Units

note 2

FPFRAME setup to FPLINE pulse trailing edge

FPFRAME hold from FPLINE pulse trailing edge

FPLINE period

Ts (note 1)

note 3

FPLINE pulse width

note 4

MOD transition to FPLINE pulse trailing edge

FPSHIFT falling edge to FPLINE pulse leading edge

FPSHIFT falling edge to FPLINE pulse trailing edge

FPLINE pulse trailing edge to FPSHIFT falling edge

FPSHIFT period

note 5

note 6

t14 + 2

t10

t11

t12

t13

t14

FPSHIFT pulse width low

FPSHIFT pulse width high

UD[3:0], LD[3:0] setup to FPSHIFT falling edge

UD[3:0], LD[3:0] hold to FPSHIFT falling edge

FPLINE pulse trailing edge to FPSHIFT rising edge

1. Ts

= pixel clock period = memory clock, [memory clock]/2, [memory clock]/3, [memory clock]/4 (see REG[19h] bits [1:0])

= t3 - 14Ts

2. t1

3. t3

4. t5

5. t6

6. t7

min

= [((REG[04h] bits [6:0])+1)*8 + ((REG[05h] bits [4:0]) + 1)*8] + 33 Ts

= [(((REG[04h] bits [6:0])+1)*8 + ((REG[05h] bits [4:0]) + 1)*8)-1] Ts

= [((REG[05h] bits [4:0]) + 1)*8 - 19] Ts

= [((REG[05h] bits [4:0]) + 1)*8 - 10] Ts

Hardware Functional Specification

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7.5.8 8-Bit Dual Color Passive LCD Panel Timing

VDP

VNDP

FPFRAME

FPLINE

MOD

LINE 1/241

LINE 2/242

LINE 3/243

LINE 4/244

LINE 239/479 LINE 240/480

LINE 1/241

LINE 2/242

UD[3:0], LD[3:0]

FPLINE

MOD

HNDP

HDP

FPSHIFT

FPDAT7 (UD3)

1-G2

1-B2

1-R3

1-G3

1-G6

1-R1

1-G1

1-B1

1-R2

1-B3

1-R4

1-R5

1-G5

1-B5

1-R6

1-B7

1-R8

1-B639

1-R640

1-G640

1-B640

1-B6

1-R7

1-G7

FPDAT6 (UD2)

FPDAT5 (UD1)

FPDAT4 (UD0)

FPDAT3 (LD3)

FPDAT2 (UD2)

1-G8

1-G4

1-B4

1-B8

241-

B639

241-B7

241-R1 241-G2 241-B3 241-R5 241-G6

241-R4 241-G5

241-

R640

241-G1 241-B2

241-B6

241-R8

241-G8

241-

G640

241-B1 241-R3 241-G4 241-B5 241-R7

FPDAT1 (UD1)

FPDAT0 (UD0)

241-

B640

241-R2 241-G3 241-B4 241-R6 241-G7 241-B8

* Diagram drawn with 2 FPLINE vertical blank period

Example timing for a 640x480 panel

Figure 7-38: 8-Bit Dual Color Passive LCD Panel Timing

VDP

= Vertical Display Period

= (REG[09h] bits [1:0], REG[08h] bits [7:0]) + 1

= (REG[0Ah] bits [5:0]) + 1

VNDP

HDP

= Vertical Non-Display Period

= Horizontal Display Period

= Horizontal Non-Display Period

= ((REG[04h] bits [6:0]) + 1)*8Ts

= ((REG[05h] bits [4:0]) + 1)*8Ts

HNDP

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Sync Timing

FPFRAME

FPLINE

MOD

Data Timing

FPLINE

t14

t11

t10

FPSHIFT

t12

t13

UD[3:0]

LD[3:0]

Figure 7-39: 8-Bit Dual Color Passive LCD Panel A.C. Timing

Table 7-30: 8-Bit Dual Color Passive LCD Panel A.C. Timing

Symbol

Parameter

Min

note 2

Typ

Max

Units

FPFRAME setup to FPLINE pulse trailing edge

FPFRAME hold from FPLINE pulse trailing edge

FPLINE period

Ts (note 1)

note 3

FPLINE pulse width

note 4

MOD transition to FPLINE pulse trailing edge

FPSHIFT falling edge to FPLINE pulse leading edge

FPSHIFT falling edge to FPLINE pulse trailing edge

FPLINE pulse trailing edge to FPSHIFT falling edge

FPSHIFT period

note 5

note 6

t14 + t11

t10

t11

t12

t13

t14

0.45

FPSHIFT pulse width low

FPSHIFT pulse width high

UD[3:0], LD[3:0] setup to FPSHIFT falling edge

UD[3:0], LD[3:0] hold to FPSHIFT falling edge

FPLINE pulse trailing edge to FPSHIFT rising edge

1. Ts

= pixel clock period = memory clock, [memory clock]/2, [memory clock]/3, [memory clock]/4 (see REG[19h] bits [1:0])

= t3 - 14Ts

2. t1

3. t3

4. t5

5. t6

6. t7

min

= [((REG[04h] bits [6:0])+1)*8 + ((REG[05h] bits [4:0]) + 1)*8] + 33 Ts

= [(((REG[04h] bits [6:0])+1)*8 + ((REG[05h] bits [4:0]) + 1)*8)-1] Ts

= [((REG[05h] bits [4:0]) + 1)*8 - 20] Ts

= [((REG[05h] bits [4:0]) + 1)*8 - 11] Ts

Hardware Functional Specification

Issue Date: 01/02/02

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Epson Research and Development

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7.5.9 16-Bit Dual Color Passive LCD Panel Timing

VDP

VNDP

FPFRAME

FPLINE

MOD

LINE 1/241

LINE 2/242

LINE 3/243

LINE 4/244

LINE 239/479 LINE 240/480

LINE 1/241

LINE 2/242

UD[7:0], LD[7:0]

FPLINE

MOD

HDP

HNDP

FPSHIFT

1-R1,

1-B3,

1-G638,

UD7, LD7

UD6, LD6

UD5, LD5

UD4, LD4

UD3, LD3

UD2, LD2

UD1, LD1

UD0, LD0

241-B3

241-R1

241-G638

1-G1,

241-G1

1-R4,

241-R4

1-B638,

241-B638

1-G4,

241-G4

1-R639,

241-R639

1-B1,

241-B1

1-R2,

241-R2

1-B4,

241-B4

1-G639,

241-G639

1-B639,

241-B639

1-G2,

241-G2

1-R5,

241-R5

1-G5,

241-G5

1-R640,

241-R640

1-B2,

241-B2

1-R3,

241-R3

1-B5,

241-B5

1-G640,

241-G640

1-G3,

241-G3

1-R6,

241-R6

1-B640,

241-B640

* Diagram drawn with 2 FPLINE vertical blank period

Example timing for a 640x480 panel

Figure 7-40: 16-Bit Dual Color Passive LCD Panel Timing

VDP

= Vertical Display Period

= (REG[09h] bits [1:0], REG[08h] bits [7:0]) + 1

= (REG[0Ah] bits [5:0]) + 1

VNDP

HDP

= Vertical Non-Display Period

= Horizontal Display Period

= Horizontal Non-Display Period

= ((REG[04h] bits [6:0]) + 1)*8Ts

= ((REG[05h] bits [4:0]) + 1)*8Ts

HNDP

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Sync Timing

FPFRAME

FPLINE

MOD

Data Timing

FPLINE

t14

t11

t10

FPSHIFT

t12

t13

UD[7:0]

LD[7:0]

Figure 7-41: 16-Bit Dual Color Passive LCD Panel A.C. Timing

Table 7-31: 16-Bit Dual Color Passive LCD Panel A.C. Timing

Symbol

Parameter

Min

Typ

Max

Units

note 2

FPFRAME setup to FPLINE pulse trailing edge

FPFRAME hold from FPLINE pulse trailing edge

FPLINE period

Ts (note 1)

note 3

FPLINE pulse width

note 4

MOD transition to FPLINE pulse trailing edge

FPSHIFT falling edge to FPLINE pulse leading edge

FPSHIFT falling edge to FPLINE pulse trailing edge

FPLINE pulse trailing edge to FPSHIFT falling edge

FPSHIFT period

note 5

note 6

t14 + 2

t10

t11

t12

t13

t14

FPSHIFT pulse width low

FPSHIFT pulse width high

UD[7:0], LD[7:0] setup to FPSHIFT falling edge

UD[7:0], LD[7:0] hold to FPSHIFT falling edge

FPLINE pulse trailing edge to FPSHIFT rising edge

1. Ts

= pixel clock period = memory clock, [memory clock]/2, [memory clock]/3, [memory clock]/4 (see REG[19h] bits [1:0])

= t3 - 14Ts

= [((REG[04h] bits [6:0])+1)*8 + ((REG[05h] bits [4:0]) + 1)*8] + 33 Ts

= [(((REG[04h] bits [6:0])+1)*8 + ((REG[05h] bits [4:0]) + 1)*8)-1] Ts

= [((REG[05h] bits [4:0]) + 1)*8 - 20] Ts

2. t1

3. t3

4. t5

5. t6

6. t7

min

= [((REG[05h] bits [4:0]) + 1)*8 - 11] Ts

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7.5.10 16-Bit TFT/D-TFD Panel Timing

VNDP

VDP

FPFRAME

FPLINE

LINE480

LINE1

LINE480

R[5:1], G[5:0], B[5:1]

DRDY

FPLINE

HDP

HNDP₁

HNDP₂

FPSHIFT

DRDY

R[5:1]

G[5:0]

1-1

1-2

1-640

1-1

1-2

1-640

B[5:1]

Note: DRDY is used to indicate the first pixel

Example Timing for 640x480 panel

Figure 7-42: 16-Bit TFT/D-TFD Panel Timing

VDP

= Vertical Display Period

= (REG[09h] bits [1:0], REG[08h] bits [7:0]) + 1

= (REG[0Ah] bits [5:0]) + 1

VNDP

HDP

= Vertical Non-Display Period

= Horizontal Display Period

= Horizontal Non-Display Period

= ((REG[04h] bits [6:0]) + 1)*8Ts

HNDP

= HNDP + HNDP

= ((REG[05h] bits [4:0]) + 1)*8Ts

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FPFRAME

FPLINE

t12

FPLINE

t15

t17

DRDY

t14

t11

t13

t16

FPSHIFT

R[5:1]

G[5:0]

B[5:1]

639

640

t10

Note: DRDY is used to indicate the first pixel

Figure 7-43: TFT/D-TFD A.C. Timing

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Table 7-32: TFT/D-TFD A.C. Timing

Symbol

Parameter

Min

Typ

Max

Units

Ts (note 1)

FPSHIFT period

0.45

FPSHIFT pulse width high

FPSHIFT pulse width low

data setup to FPSHIFT falling edge

data hold from FPSHIFT falling edge

FPLINE cycle time

0.45

note 2

note 3

note 4

note 5

note 6

0.45

FPLINE pulse width low

FPFRAME cycle time

FPFRAME pulse width low

horizontal display period

FPLINE setup to FPSHIFT falling edge

t10

t11

FPFRAME pulse leading edge to FPLINE pulse

leading edge phase difference

t12

note 7

t13

t14

0.45

DRDY to FPSHIFT falling edge setup time

DRDY pulse width

note 8

DRDY falling edge to FPLINE pulse leading

edge

t15

note 9

t16

t17

0.45

DRDY hold from FPSHIFT falling edge

note 10

250

FPLINE pulse leading edge to DRDY active

1. Ts

= pixel clock period = memory clock, [memory clock]/2, [memory clock]/3, [memory clock]/4 (see REG[19h] bits [1:0])

= [((REG[04h] bits [6:0])+1)*8 + ((REG[05h] bits [4:0])+1)*8] Ts

= [((REG[07h] bits [3:0])+1)*8] Ts

2. t6

3. t7

4. t8

5. t9

min

= [((REG[09h] bits [1:0], REG[08h] bits [7:0])+1) + ((REG[0Ah] bits [5:0])+1)] lines

= [((REG[0Ch] bits [2:0])+1)] lines

6. t10

7. t12

8. t14

9. t15

10. t17

= [((REG[04h] bits [6:0])+1)*8] Ts

min

= [((REG[06h] bits [4:0])*8)+1] Ts

= [((REG[04h] bits [6:0])+1)*8] Ts

= [((REG[06h] bits [4:0])+1)*8 - 2] Ts

= [((REG[05h] bits [4:0])+1)*8 - ((REG[06h] bits [4:0])+1)*8 + 2]

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7.5.11 CRT Timing

VNDP

VDP

VRTC

HRTC

LINE480

LINE1

RED,GREEN,BLUE

HRTC

HDP

HNDP₁

HNDP₂

1-1

1-2

1-640

RED,GREEN,BLUE

Example Timing for 640x480 CRT

Figure 7-44: CRT Timing

VDP

= Vertical Display Period

= (REG[09h] bits [1:0], REG[08h] bits [7:0]) + 1

= (REG[0Ah] bits [5:0]) + 1

VNDP

HDP

= Vertical Non-Display Period

= Horizontal Display Period

= Horizontal Non-Display Period

= ((REG[04h] bits [6:0]) + 1)*8Ts

HNDP

= HNDP + HNDP

= ((REG[05h] bits [4:0]) + 1)*8Ts

Note

The signals RED, GREEN and BLUE are analog signals from the embedded DAC and represent

the color components which make up each pixel.

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VRTC

HRTC

Figure 7-45: CRT A.C. Timing

Symbol

Parameter

Min

Typ

Max

Units

note 1

note 2

VRTC cycle time

VRTC pulse width low

VRTC falling edge to FPLINE falling edge

phase difference

note 3

1. t8

2. t9

= [((REG[09h] bits 1:0, REG[08h] bits 7:0)+1) + ((REG[0Ah] bits 6:0)+1)] lines

= [((REG[0Ch] bits 2:0)+1)] lines

min

3. t12

= [((REG[06h] bits 4:0)+1)*8] Ts

min

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8 Registers

8.1 Register Mapping

The S1D13505 registers are memory mapped. The system addresses the registers through the CS#,

M/R#, and AB[5:0] input pins. When CS# = 0 and M/R# = 0, the registers are mapped by address

bits AB[5:0], e.g. REG[00h] is mapped to AB[5:0] = 000000, REG[01h] is mapped to AB[5:0] =

000001. See the table below:

Table 8-1: S1D13505 Addressing

CS#

M/R#

Access

•

REG[00h] is addressed when AB[5:0] = 0

REG[01h] is addressed when AB[5:0] = 1

REG[n] is addressed when AB[5:0] = n

Memory access: the 2M byte Display Buffer is addressed by

AB[20:0]

S1D13505 not selected

8.2 Register Descriptions

Unless specified otherwise, all register bits are reset to 0 during power-on. Reserved bits should be

written 0 when programming unless otherwise noted.

8.2.1 Revision Code Register

Revision Code Register

REG[00h]

Product Code Product Code Product Code Product Code Product Code Product Code Revision

Revision

Code Bit 0

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Code Bit 1

bits 7-2

Product Code Bits [5:0]

This is a read-only register that indicates the product code of the chip. The product code for the

S1D13505 is 000011.

bits 1-0

Revision Code Bits [1:0]

This is a read-only register that indicates the revision code of the chip. The revision code for the

S1D13505F00A is 00.

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8.2.2 Memory Configuration Registers

Memory Configuration Register

REG[01h]

Refresh Rate Refresh Rate Refresh Rate

n/a

WE# Control n/a

Memory Type

Bit 2

Bit 1

Bit 0

bits 6-4

DRAM Refresh Rate Select Bits [2:0]

These bits specify the divisor used to generate the DRAM refresh rate from the input clock (CLKI).

Table 8-2: DRAM Refresh Rate Selection

Example period for

256 refresh cycles at

CLKI = 33MHz

DRAM Refresh Rate

Select Bits [2:0]

CLKI Frequency

Divisor

Example Refresh Rate

for CLKI = 33MHz

000

001

010

011

100

101

110

111

520 kHz

260 kHz

130 kHz

65 kHz

33 kHz

16 kHz

8 kHz

0.5 ms

1 ms

128

256

2 ms

512

4 ms

1024

2048

4096

8192

8 ms

16 ms

32 ms

64 ms

4 kHz

bit 2

bit 0

WE# Control

When this bit = 1, 2-WE# DRAM is selected.

When this bit = 0, 2-CAS# DRAM is selected.

Memory Type

When this bit = 1, FPM-DRAM is selected.

When this bit = 0, EDO-DRAM is selected.

This bit should be changed only when there are no read/write DRAM cycles. This condition occurs

when all of the following are true: the Display FIFO is disabled (REG[23h] bit 7 = 1), and the Half

Frame Buffer is disabled (REG[1Bh] bit 0 = 1), and the Ink/Cursor is inactive

(Reg[27h] bits 7-6 = 00). This condition also occurs when the CRT and LCD enable bits (Reg[0Dh]

bits 1-0) have remained 0 since chip reset. For further programming information, see S1D13505

Programming Notes and Examples, document number X23A-G-003-xx.

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8.2.3 Panel/Monitor Configuration Registers

Panel Type Register

REG[02h]

TFT/ Passive

LCD Panel

Select

EL Panel

Enable

Panel Data

Width Bit 1

Panel Data

Width Bit 0

Panel Data

Format Select Panel Select Panel Select

Color/Mono.

Dual/Single

n/a

bit 7

EL Panel Mode Enable

When this bit = 1, EL Panel support mode is enabled. Every 262143 frames (approximately 1 hour

at 60Hz frame rate) the identical panel data is sent to two consecutive frames, i.e. the frame rate

modulation circuitry is frozen for one frame.

bits 5-4

Panel Data Width Bits [1:0]

These bits select the LCD interface data width as shown in the following table.

Table 8-3: Panel Data Width Selection

Passive LCD Panel Data

Width Size

TFT/D-TFD Panel Data Width

Size

Panel Data Width Bits [1:0]

4-bit

8-bit

9-bit

12-bit

16-bit

Reserved

bit 3

bit 2

bit 1

bit 0

Panel Data Format Select

When this bit = 1, color passive LCD panel data format 2 is selected.

When this bit = 0, passive LCD panel data format 1 is selected.

Color/Mono Panel Select

When this bit = 1, color passive LCD panel is selected.

When this bit = 0, monochrome passive LCD panel is selected.

Dual/Single Panel Select

When this bit = 1, dual passive LCD panel is selected.

When this bit = 0, single passive LCD panel is selected.

TFT/Passive LCD Panel Select

When this bit = 1, TFT/D-TFD panel is selected.

When this bit = 0, passive LCD panel is selected.

MOD Rate Register

REG[03h]

MOD Rate Bit MOD Rate Bit MOD Rate Bit MOD Rate Bit MOD Rate Bit MOD Rate Bit

n/a

bits 5-0

MOD Rate Bits [5:0]

When the DRDY pin is configured as MOD, this register controls the toggle rate of the MOD out-

put. When this register is zero, the MOD output signal toggles every FPFRAME. When this register

is non-zero, its value represents the number of FPLINE pulses between toggles of the MOD output

signal.

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Horizontal Display Width Register

REG[04h]

Horizontal

Display Width Display Width Display Width Display Width Display Width Display Width Display Width

Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Horizontal

n/a

bits 6-0

Horizontal Display Width Bits [6:0]

These bits specify the LCD panel and/or the CRT horizontal display width as follows.

Contents of this Register = (Horizontal Display Width ÷ 8) - 1

For passive LCD panels the Horizontal Display Width must be divisible by 16, and for TFT LCD

panels/CRTs the Horizontal Display Width must be divisible by 8. The maximum horizontal dis-

play width is 1024 pixels.

Note

This register must be programmed such that REG[04h] ≥ 3 (32 pixels)

Note

When setting a horizontal resolution greater than 767 pixels, with a color depth of 15/16 bpp, the

Memory Offset Registers (REG[16h], REG[17h]) must be set to a virtual horizontal pixel

resolution of 1024.

Horizontal Non-Display Period Register

REG[05h]

Horizontal

n/a

Non-Display

Period Bit 4

Non-Display

Period Bit 3

Non-Display

Period Bit 2

Non-Display

Period Bit 1

Non-Display

Period Bit 0

bits 4-0

Horizontal Non-Display Period Bits [4:0]

These bits specify the horizontal non-display period.

Horizontal non-display period (pixels) = (Horizontal Non-Display Period Bits [4:0] + 1) × 8

The recommended minimum value which should be programmed into this register is 3 (32 pixels).

The maximum value which can be programmed into this register is 1Fh, which gives a horizontal

non-display period of 256 pixels.

Note

This register must be programmed such that

REG[05h] ≥ 3 and (REG[05h] + 1) ≥ (REG[06h] + 1) + (REG[07h] bits [3:0] +1)

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HRTC/FPLINE Start Position Register

REG[06h]

HRTC/

n/a

FPLINE Start FPLINE Start FPLINE Start FPLINE Start FPLINE Start

Position Bit 4 Position Bit 3 Position Bit 2 Position Bit 1 Position Bit 0

bits 4-0

HRTC/FPLINE Start Position Bits [4:0]

For CRT and TFT/D-TFD, these bits specify the delay from the start of the horizontal non-display

period to the leading edge of the HRTC pulse and FPLINE pulse respectively.

HRTC/FPLINE start position (pixels) = (HRTC/FPLINE Start Position Bits [4:0] + 1) × 8 - 2

Note

This register must be programmed such that

(REG[05h] + 1) ≥ (REG[06h] + 1) + (REG[07h] bits [3:0] +1)

HRTC/FPLINE Pulse Width Register

REG[07h]

HRTC

Polarity

Select

FPLINE

Polarity

Select

HRTC/

FPLINEPulse FPLINEPulse FPLINEPulse FPLINEPulse

Width Bit 3 Width Bit 2 Width Bit 1 Width Bit 0

HRTC/

n/a

bit 7

HRTC Polarity Select

This bit selects the polarity of the HRTC pulse to the CRT.

When this bit = 1, the HRTC pulse is active high.

When this bit = 0, the HRTC pulse is active low.

bit 6

FPLINE Polarity Select

This bit selects the polarity of the FPLINE pulse to TFT/D-TFD or passive LCD.

When this bit = 1, the FPLINE pulse is active high for TFT/D-TFD and active low for passive LCD.

When this bit = 0, the FPLINE pulse is active low for TFT/D-TFD and active high for passive LCD.

Table 8-4: FPLINE Polarity Selection

FPLINE Polarity Select

Passive LCD FPLINE Polarity TFT/D-TFD FPLINE Polarity

active high

active low

active high

bits 3-0

HRTC/FPLINE Pulse Width Bits [3:0]

For CRT and TFT/D-TFD, these bits specify the pulse width of HRTC and FPLINE respectively.

For passive LCD, FPLINE is automatically created and these bits have no effect.

HRTC/FPLINE pulse width (pixels) = (HRTC/FPLINE Pulse Width Bits [3:0] + 1) × 8

The maximum HRTC pulse width is 128 pixels.

Note

This register must be programmed such that

(REG[05h] + 1) ≥ (REG[06h] + 1) + (REG[07h] bits [3:0] +1)

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Vertical Display Height Register 0

REG[08h]

Vertical

Display

Height Bit 7

Height Bit 6

Height Bit 5

Height Bit 4

Height Bit 3

Height Bit 2

Height Bit 1

Height Bit 0

Vertical Display Height Register 1

REG[09h]

Vertical

n/a

Display

Height Bit 9

Height Bit 8

REG[08h] bits 7-0

REG[09h] bits 1-0

Vertical Display Height Bits [9:0]

These bits specify the vertical display height.

Vertical display height (lines) = Vertical Display Height Bits [9:0] + 1

• For CRT, TFT/D-TFD, and single passive LCD panel this register is programmed to:

(vertical resolution of the display) - 1, e.g. EFh for a 240-line display.

• For dual-panel passive LCD not in simultaneous display mode, this register is programmed to:

((vertical resolution of the display)/2) - 1, e.g. EFh for a 480-line display.

• For all simultaneous display modes, this register is programmed to:

(vertical resolution of the CRT) - 1, e.g. 1DFh for a 480-line CRT.

Vertical Non-Display Period Register

REG[0Ah]

Vertical Non-

Display

Period Status

(RO)

Vertical Non- Vertical Non- Vertical Non- Vertical Non- Vertical Non- Vertical Non-

n/a

Display

Period Bit 5

Period Bit 4

Period Bit 3

Period Bit 2

Period Bit 1

Period Bit 0

bit 7

Vertical Non-Display Period Status

This is a read-only status bit.

When this bit = 1, a vertical non-display period is indicated.

When this bit = 0, a vertical display period is indicated.

bits 5-0

Vertical Non-Display Period Bits [5:0]

These bits specify the vertical non-display period.

Vertical non-display period (lines) = Vertical Non-Display Period Bits [5:0] + 1

Note

This register must be programmed such that

REG[0Ah] ≥ 1 and (REG[0Ah] bits [5:0] + 1) ≥ (REG[0Bh] + 1) + (REG[0Ch] bits [2:0] + 1)

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VRTC/FPFRAME Start Position Register

REG[0Bh]

VRTC/

FPFRAME

VRTC/

FPFRAME

VRTC/

FPFRAME

VRTC/

FPFRAME

VRTC/

FPFRAME

VRTC/

FPFRAME

n/a

Start Position Start Position Start Position Start Position Start Position Start Position

Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

bits 5-0

VRTC/FPFRAME Start Position Bits [5:0]

For CRT and TFT/D-TFD, these bits specify the delay in lines from the start of the vertical non-dis-

play period to the leading edge of the VRTC pulse and FPFRAME pulse respectively. For passive

LCD, FPFRAME is automatically created and these bits have no effect.

VRTC/FPFRAME start position (lines) = VRTC/FPFRAME Start Position Bits [5:0] + 1

The maximum start delay is 64 lines.

Note

This register must be programmed such that

(REG[0Ah] bits [5:0] + 1) ≥ (REG[0Bh] + 1) + (REG[0Ch] bits [2:0] + 1)

For exact timing please use the timing diagrams in section 7.5

VRTC/FPFRAME Pulse Width Register

REG[0Ch]

VRTC/

FPFRAME

Polarity

Select

VRTCPolarity

Select

FPFRAME

Pulse Width

Bit 2

FPFRAME

Pulse Width

Bit 1

FPFRAME

Pulse Width

Bit 0

n/a

bit 7

VRTC Polarity Select

This bit selects the polarity of the VRTC pulse to the CRT.

When this bit = 1, the VRTC pulse is active high.

When this bit = 0, the VRTC pulse is active low.

bit 6

FPFRAME Polarity Select

This bit selects the polarity of the FPFRAME pulse to the TFT/D-TFD or passive LCD.

When this bit = 1, the FPFRAME pulse is active high for TFT/D-TFD and active low for passive.

When this bit = 0, the FPFRAME pulse is active low for TFT/D-TFD and active high for passive.

Table 8-5: FPFRAME Polarity Selection

FPFRAME Polarity Select

Passive LCD FPFRAME Polarity

active high

TFT/D-TFD FPFRAME Polarity

active low

active high

bits 2-0

VRTC/FPFRAME Pulse Width Bits [2:0]

For CRT and TFT/D-TFD, these bits specify the pulse width of VRTC and FPFRAME respectively.

For passive LCD, FPFRAME is automatically created and these bits have no effect.

VRTC/FPFRAME pulse width (lines) = VRTC/FPFRAME Pulse Width Bits [2:0] + 1

Note

This register must be programmed such that

(REG[0Ah] bits [5:0] + 1) ≥ (REG[0Bh] + 1) + (REG[0Ch] bits [2:0] + 1)

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8.2.4 Display Configuration Registers

Display Mode Register

REG[0Dh]

Simultaneous Simultaneous

SwivelView

Enable

Display

Bit-per-pixel

Select Bit 1

Bit-per-pixel

Select Bit 0

CRT Enable

LCD Enable

Option Select Option Select Select Bit 2

Bit 1

Bit 0

bit 7

SwivelView Enable

When this bit = 1, all CPU accesses to the display buffer are translated to provide clockwise 90°

hardware rotation of the display image. Refer to “Section 13 SwivelView” for application and limi-

tations.

bits 6-5

Simultaneous Display Option Select Bits [1:0]

These bits are used to select one of four different simultaneous display mode options: Normal, Line

Doubling, Interlace, or Even Scan Only. The purpose of these modes is to manipulate the vertical

resolution of the image so that it fits on both the CRT, typically 640x480, and LCD. The following

table describes the four modes using a 640x480 CRT as an example:

Table 8-6: Simultaneous Display Option Selection

Simultaneous

Display Option

Select Bits [1:0]

Simultaneous

Display Mode

Mode Description

The image is not manipulated. This mode is used when the CRT and LCD have the same

resolution, e.g. 480 lines.

Normal

It is necessary to suit the vertical retrace period to the CRT. This results in a lower LCD

duty cycle (1/525 compared to the usual 1/481). This reduced duty cycle may result in

lower contrast on the LCD.

Each line is replicated on the CRT. This mode is used to display a 240-line image on a

240-line LCD and stretch it to a 480-line image on the CRT. The CRT has a heightened

aspect ratio.

Line Doubling

It is necessary to suit the vertical retrace period to the CRT. This results in a lower LCD

duty cycle (2/525 compared to the usual 1/241). This reduced duty cycle is not extreme

and the contrast of the LCD image should not be greatly reduced.

The odd and even fields of a 480-line image are interlaced on the LCD. This mode is used

to display a 480-line image on the CRT and squash it onto a 240-line LCD. The full image

is viewed on the LCD but the interlacing may create flicker. The LCD has a shortened

aspect ratio.

Interlace

It is necessary to suit the vertical retrace period to the CRT. This results in a lower LCD

duty cycle (2/525 compared to the usual 1/241). This reduced duty cycle is not extreme

and the contrast of the LCD image should not be greatly reduced.

Only the even field of a 480-line image is displayed on the LCD. This is an alternate

method to display a 480-line image on the CRT and squash it onto a 240-line LCD. Only

the even scans are viewed on the LCD. The LCD has a shortened aspect ratio.

Even Scan Only

It is necessary to suit the vertical retrace period to the CRT. This results in a lower LCD

duty cycle (2/525 compared to the usual 1/241). This reduced duty cycle is not extreme

and the contrast of the LCD image should not be greatly reduced.

Note

1. Dual Panel Considerations: When configured for a dual LCD panel and using

Simultaneous Display, the Half Frame Buffer Disable, REG[1Bh] bit 0, must be set to 1.

This results in a lower contrast on the LCD panel, which may require adjustment.

2. The Line doubling option is not supported with dual panel.

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bits 4-2

Bit-per-pixel Select Bits [2:0]

These bits select the color depth (bpp) for the displayed data. See “Section 10.1 Display Mode For-

mats” for details of how the pixels are mapped into the image buffer.

Table 8-7: Bit-per-pixel Selection

Bit-per-pixel Select Bits [2:0]

Color Depth (bpp)

1 bpp

000

001

2 bpp

010

4 bpp

011

8 bpp

100

15 bpp

101

16 bpp

110 – 111

Reserved

bit 1

bit 0

CRT Enable

This bit enables the CRT monitor.

When this bit = 1, the CRT is enabled.

When this bit = 0, the CRT is disabled.

LCD Enable

This bit enables the LCD panel.

Programming this bit from a 0 to a 1 starts the LCD power-on sequence.

Programming this bit from a 1 to a 0 starts the LCD power-off sequence.

Screen 1 Line Compare Register 0

REG[0Eh]

Screen 1 Line Screen 1 Line Screen 1 Line Screen 1 Line Screen 1 Line Screen 1 Line Screen 1 Line Screen 1 Line

Compare Bit 7 Compare Bit 6 Compare Bit 5 Compare Bit 4 Compare Bit 3 Compare Bit 2 Compare Bit 1 Compare Bit 0

Screen 1 Line Compare Register 1

REG[0Fh]

Screen 1 Line Screen 1 Line

Compare Bit 9 Compare Bit 8

n/a

REG[0Eh] bits 7-0

REG[0Fh] bits 1-0

Screen 1 Line Compare Bits [9:0]

These bits are set to 1 during power-on.

The display can be split into two images: Screen 1 and Screen 2, with Screen 1 above Screen 2.

This 10-bit value specifies the height of Screen 1.

Height of Screen 1 (lines) = Screen 1 Line Compare Bits [9:0] + 1

If the height of Screen 1 is less than the display height then the remainder of the display is taken up

by Screen 2. For normal operation (no split screen) this register must be set greater than the Vertical

Display Height register (e.g. set to the reset value of 3FFh).

See “Display Configuration” for details.

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Screen 1 Display Start Address Register 0

REG[10h]

Start Address Start Address Start Address Start Address Start Address Start Address Start Address Start Address

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Screen 1 Display Start Address Register 1

REG[11h]

Start Address Start Address Start Address Start Address Start Address Start Address Start Address Start Address

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8

Screen 1 Display Start Address Register 2

REG[12h]

Start Address Start Address Start Address Start Address

n/a

Bit 19 Bit 18 Bit 17 Bit 16

REG[10h] bits 7-0

REG[11h] bits 7-0

REG[12h] bits 3-0

Screen 1 Start Address Bits [19:0]

These registers form the 20-bit address for the starting word of the Screen 1 image in

the display buffer.

Note that this is a word address.

A combination of this register and the Pixel Panning register (REG[18h]) can be used to uniquely

identify the start (top left) pixel within the Screen 1 image stored in the display buffer.

See “Display Configuration” for details.

Screen 2 Display Start Address Register 0

REG[13h]

Start Address Start Address Start Address Start Address Start Address Start Address Start Address Start Address

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Screen 2 Display Start Address Register 1

REG[14h]

Start Address Start Address Start Address Start Address Start Address Start Address Start Address Start Address

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8

Screen 2 Display Start Address Register 2

REG[15h]

Start Address Start Address Start Address Start Address

n/a

Bit 19 Bit 18 Bit 17 Bit 16

REG[13h] bits 7-0

REG[14h] bits 7-0

REG[15h] bits 3-0

Screen 2 Start Address Bits [19:0]

These registers form the 20-bit address for the starting word of the Screen 2 image in

the display buffer.

Note that this is a word address.

A combination of this register and the Pixel Panning register (REG[18h]) can be used to uniquely

identify the start (top left) pixel within the Screen 2 image stored in the display buffer.

See “Display Configuration” for details.

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Memory Address Offset Register 0

REG[16h]

Memory

Address

Offset Bit 7

Offset Bit 6

Offset Bit 5

Offset Bit 4

Offset Bit 3

Offset Bit 2

Offset Bit 1

Offset Bit 0

Memory Address Offset Register 1

REG[17h]

Memory

n/a

Address

Offset Bit 10

Offset Bit 9

Offset Bit 8

REG[16h] bits 7-0

REG[17h] bits 2-0

Memory Address Offset Bits [10:0]

These bits form the 11-bit address offset from the starting word of line n to the starting word of line

n+1. This value is applied to both Screen 1 and Screen 2.

Note that this value is in words.

A virtual image can be formed by setting this register to a value greater than the width of the dis-

play. The displayed image is a window into the larger virtual image.

See “Section 10 Display Configuration” for details.

Pixel Panning Register

REG[18h]

Screen 2

Screen 1

Pixel Panning Pixel Panning Pixel Panning Pixel Panning Pixel Panning Pixel Panning Pixel Panning Pixel Panning

Bit 3

Bit 2

Bit 1

Bit 0

Bit 3

Bit 2

Bit 1

Bit 0

This register is used to control the horizontal pixel panning of Screen 1 and Screen 2. Each screen

can be independently panned to the left by programming its respective Pixel Panning Bits to a non-

zero value. The value represents the number of pixels panned. The maximum pan value is dependent

on the display mode.

Table 8-8: Pixel Panning Selection

Display Mode

1 bpp

Maximum Pan Value

Pixel Panning Bits active

Bits [3:0]

Bits [2:0]

Bits [1:0]

Bit 0

2 bpp

4 bpp

8 bpp

15/16 bpp

none

Smooth horizontal panning can be achieved by a combination of this register and the Display Start

Address registers.

See “Section 10 Display Configuration” for details.

bits 7-4

bits 3-0

Screen 2 Pixel Panning Bits [3:0]

Pixel panning bits for screen 2.

Screen 1 Pixel Panning Bits [3:0]

Pixel panning bits for screen 1.

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8.2.5 Clock Configuration Register

Clock Configuration Register

REG[19h]

MCLK Divide PCLK Divide PCLK Divide

Reserved

n/a

Select

Select Bit 1

Select Bit 0

bit 7

Reserved

This bit must be set to 0.

Note

There must always be a source clock at CLKI.

bit 2

MCLK Divide Select

When this bit = 1 the MCLK frequency is half of its source frequency.

When this bit = 0 the MCLK frequency is equal to its source frequency.

The MCLK frequency should always be set to the maximum frequency allowed by the DRAM; this

provides maximum performance and minimum overall system power consumption.

bits 1-0

PCLK Divide Select Bits [1:0]

These bits select the MCLK: PCLK frequency ratio

Table 8-9: PCLK Divide Selection

PCLK Divide Select Bits [1:0]

MCLK: PCLK Frequency Ratio

1: 1

2: 1

3: 1

4: 1

See section on “Maximum MCLK:PCLK Frequency Ratios” for selection of clock ratios.

8.2.6 Power Save Configuration Registers

Power Save Configuration Register

REG[1Ah]

Power Save

Status

Suspend

Refresh

Select Bit 1

Suspend

Refresh

Select Bit 0

Software

Suspend

Mode Enable

LCD Power

Disable

n/a

bit 7

Power Save Status

This is a read-only status bit.

This bit indicates the power-save state of the chip.

When this bit = 1, the panel has been powered down and the memory controller is either in self

refresh mode or is performing only CAS-before-RAS refresh cycles.

When this bit = 0, the chip is either powered up, in transition of powering up, or in transition of

powering down. See Section 15 Power Save Modes for details.

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bit 3

LCD Power Disable

This bit is used to override the panel on/off sequencing logic.

When this bit = 0 the LCDPWR output is controlled by the panel on/off sequencing logic.

When this bit = 1 the LCDPWR output is directly forced to the off state.

The LCDPWR “On/Off” polarity is configured by MD10 at the rising edge of RESET# (MD10 = 0

configures LCDPWR = 0 as the Off state; MD10 = 1 configures LCDPWR = 1 as the Off state).

bits 2-1

Suspend Refresh Select Bits [1:0]

These bits specify the type of DRAM refresh to use in Suspend mode.

Table 8-10: Suspend Refresh Selection

Suspend Refresh Select Bits [1:0]

DRAM Refresh Type

CAS-before-RAS (CBR) refresh

Self-Refresh

No Refresh

Note

These bits should not be changed while suspend mode is active.

bit 0

Software Suspend Mode Enable

When this bit = 1 software Suspend mode is enabled.

When this bit = 0 software Suspend mode is disabled.

See Section 15 Power Save Modes for details.

8.2.7 Miscellaneous Registers

Miscellaneous Register

REG[1Bh]

Half Frame

Host Interface

Disable

n/a

Buffer Disable

bit 7

Host Interface Disable

This bit is set to 1 during power-on/reset.

This bit must be programmed to 0 to enable the Host Interface. When this bit is high, all memory

and all registers except REG[1Ah] (read-only) and REG[1Bh] are inaccessible.

bit 0

Half Frame Buffer Disable

This bit is used to disable the Half Frame Buffer.

When this bit = 1, the Half Frame Buffer is disabled.

When this bit = 0, the Half Frame Buffer is enabled.

When a single panel is selected, the Half Frame Buffer is automatically disabled and this bit has no

effect.

The half frame buffer is needed to fully support dual panels. Disabling the Half Frame Buffer

reduces memory bandwidth requirements and increases the supportable pixel clock frequency, but

results in reduced contrast on the LCD panel (the duty cycle of the LCD is halved). This mode is

not normally used except under special circumstances such as simultaneous display on a CRT and

dual panel LCD. When this mode is used the Alternate Frame Rate Modulation scheme should be

used (see REG[31h]). For details on Frame Rate calculation see Section 14.2, “Frame Rate Calcu-

lation” on page 141.

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MD Configuration Readback Register 0

REG[1Ch]

MD[7] Status MD[6] Status MD[5] Status MD[4] Status MD[3] Status MD[2] Status MD[1] Status MD[0] Status

MD Configuration Readback Register 1

REG[1Dh]

MD[15]

Status

MD[14]

Status

MD[13]

Status

MD[12]

Status

MD[11]

Status

MD[10]

Status

MD[9]

Status

MD[8]

Status

REG[1Ch] bits 7-0

REG[1Dh] bits 7-0

MD[15:0] Configuration Status

These are read-only status bits for the MD[15:0] pins configuration status at the rising edge of

RESET#. MD[15:0] are used to configure the chip at the rising edge of RESET# – see Pin Descrip-

tions and Summary of Configuration Options for details.

General IO Pins Configuration Register 0

REG[1Eh]

GPIO3 Pin

IO Config.

GPIO2 Pin

IO Config.

GPIO1 Pin

IO Config.

n/a

Pins MA9, MA10, MA11 are multi-functional – they can be DRAM address outputs or general

purpose IO dependent on the DRAM type. MD[7:6] are used to identify the DRAM type and

configure these pins as follows:

Table 8-11: MA/GPIO Pin Functionality

MD[7:6] at

rising edge of

RESET#

Pin Function

MA10

MA9

MA11

GPIO3

MA9

GPIO1

MA10

GPIO2

MA11

MA9

These bits are used to control the direction of these pins when they are used as general purpose IO.

These bits have no effect when the pins are used as DRAM address outputs.

bit 3

bit 2

bit 1

GPIO3 Pin IO Configuration

When this bit = 1, the GPIO3 pin is configured as an output pin.

When this bit = 0 (default), the GPIO3 pin is configured as an input pin.

GPIO2 Pin IO Configuration

When this bit = 1, the GPIO2 pin is configured as an output pin.

When this bit = 0 (default), the GPIO2 pin is configured as an input pin.

GPIO1 Pin IO Configuration

When this bit = 1, the GPIO1 pin is configured as an output pin.

When this bit = 0 (default), the GPIO1 pin is configured as an input pin.

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General IO Pins Configuration Register 1

REG[1Fh]

n/a

This register position is reserved for future use.

General IO Pins Control Register 0

REG[20h]

GPIO3 Pin

IO Status

GPIO2 Pin

IO Status

GPIO1 Pin

IO Status

n/a

bit 3

GPIO3 Pin IO Status

When GPIO3 is configured as an output (see REG[1Eh]), a “1” in this bit drives GPIO3 high and a

“0” in this bit drives GPIO3 low.

When GPIO3 is configured as an input, a read from this bit returns the status of GPIO3.

bit 2

bit 1

GPIO2 Pin IO Status

When GPIO2 is configured as an output (see REG[1Eh]), a “1” in this bit drives GPIO2 high and a

“0” in this bit drives GPIO2 low.

When GPIO2 is configured as an input, a read from this bit returns the status of GPIO2.

GPIO1 Pin IO Status

When GPIO1 is configured as an output (see REG[1Eh]), a “1” in this bit drives GPIO1 high and a

“0” in this bit drives GPIO1 low.

When GPIO1 is configured as an input, a read from this bit returns the status of GPIO1.

General IO Pins Control Register 1

REG[21h]

GPO Control n/a

n/a

bit 7

GPO Control

This bit is used to control the state of the SUSPEND# pin when it is configured as General Purpose

Output (GPO). When this bit = 0, the GPO output is set to the reset state. When this bit = 1, the

GPO output is set to the inverse of the reset state. For information on the reset state of this pin see

“Miscellaneous Interface Pin Descriptions“ on page 32 and “Summary of Power On/Reset

Options“ on page 33.

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Performance Enhancement Register 0

REG[22h]

RAS#

Precharge

Timing Value Timing Value

Bit 1 Bit 0

RAS#

Precharge

RAS#-to-

CAS# Delay

Value

RC Timing

Value Bit 1

RC Timing

Value Bit 0

Reserved

Note

Changing this register to non-zero value, or to a different non-zero value, should be done only

when there are no read/write DRAM cycles. This condition occurs when all of the following are

true: the Display FIFO is disabled (REG[23h] bit 7 = 1), and the Half Frame Buffer is disabled

(REG[1Bh] bit 0 = 1), and the Ink/Cursor is inactive (Reg[27h] bits 7-6 = 00). This condition also

occurs when the CRT and LCD enable bits (Reg[0Dh] bits 1-0) have remained 0 since chip reset.

For further programming information, see S1D13505 Programming Notes and Examples, docu-

ment number X23A-G-003-xx.

bit 7

Reserved

bits 6-5

RC Timing Value (N_RC) Bits [1:0]

These bits select the DRAM random-cycle timing parameter, t_RC. These bits specify the number

(N_RC) of MCLK periods (T_M) used to create t_RC. N_RCshould be chosen to meet t_RCas well as

_RAS, the RAS pulse width. Use the following two formulae to calculate N_RCthen choose the larger

value. Note, these formulae assume an MCLK duty cycle of 50 +/- 5%.

N_RC

= Round-Up (t_RC/T_M)

= Round-Up (t_RAS/T_M+ N_RP

= Round-Up (t_RAS/T_M+ 1.55)

)

if N_RP= 1 or 2

if N_RP= 1.5

The resulting t_RCis related to N_RCas follows:

t_RC

= (N_RC) T_M

Table 8-12: Minimum Memory Timing Selection

Minimum Random Cycle

REG[22h] bits [6:5]

Width (t_RC

)

Reserved

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bit 4

RAS#-to-CAS# Delay Value (N_RCD)

This bit selects the DRAM RAS#-to-CAS# delay parameter, t_RCD. This bit specifies the number

(N_RCD) of MCLK periods (T_M) used to create t_RCD. N_RCDmust be chosen to satisfy the RAS#

access time, t_RAC. Note, these formulae assume an MCLK duty cycle of 50 +/- 5%.

N_RCD

= Round-Up((t_RAC+ 5)/T_M- 1)

= 2

= Round-Up(t_RAC/T_M- 1)

= Round-Up(t_RAC/T_M- 0.45)

if EDO and N_RP= 1 or 2

if EDO and N_RP= 1.5

if FPM and N_RP= 1 or 2

if FPM and N_RP= 1.5

Note that for EDO-DRAM and N_RP= 1.5, this bit is automatically forced to 0 to select 2 MCLK for

_RCD. This is done to satisfy the CAS# address setup time, t_ASC

The resulting t_RCis related to N_RCDas follows:

t_RCD

= (N_RCD) T_M

= (1.5) T_M

= (N_RCD+ 0.5) T_Mif FPM and N_RP= 1 or 2

= (N_RCD) T_Mif FPM and N_RP= 1.5

if EDO and N_RP= 1 or 2

if EDO and N_RP= 1.5

Table 8-13: RAS#-to-CAS# Delay Timing Select

REG[22h] bit 4

RAS#-to-CAS# Delay (t

)

RCD

bits 3-2

RAS# Precharge Timing Value (N_RP) Bits [1:0]

Minimum Memory Timing for RAS# precharge

These bits select the DRAM RAS# Precharge timing parameter, t_RP. These bits specify the number

(N_RP) of MCLK periods (T_M) used to create t_RP– see the following formulae. Note, these formulae

assume an MCLK duty cycle of 50 +/- 5%.

N_RP

= 1

if (t_RP/T_M) < 1

= 1.5

= 2

if 1 ≤ (t_RP/T_M) < 1.45

if (t_RP/T_M) ≥ 1.45

The resulting t_RCis related to N_RPas follows:

t_RP

= (N_RP+ 0.5) T_M

= (N_RP) T_M

if FPM refresh cycle and N_RP= 1 or 2

for all other

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bits 1-0

Reserved

These bits must be set to 0.

Table 8-14: RAS Precharge Timing Select

REG[22h] bits [3:2]

RAS# Precharge Width (t

)

1.5

Reserved

Optimal DRAM Timing

The following table contains the optimally programmed values of N_RC, N_RP, and N_RCDfor different

DRAM types, at maximum MCLK frequencies.

Table 8-15: Optimal N , N , and N

values at maximum MCLK frequency

RCD

RC RP

DRAM Speed

(ns)

RCD

(#MCLK)

DRAM Type

EDO

(ns)

(#MCLK)

1.5

FPM

bit 0

Reserved

This reserved bit must be set to 0.

Performance Enhancement Register 1

REG[23h]

Display FIFO Display FIFO Display FIFO Display FIFO Display FIFO

CPU to

Display FIFO Memory Wait Memory Wait

Disable

Threshold

Bit 4

Threshold

Bit 3

Threshold

Bit 2

Threshold

Bit 1

Threshold

Bit 0

State

Bit 1

State

Bit 0

bit 7

Display FIFO Disable

When this bit = 1 the display FIFO is disabled and all data outputs are forced to zero (i.e., the

screen is blanked). This accelerates screen updates by allocating more memory bandwidth to CPU

accesses.

When this bit = 0 the display FIFO is enabled.

Note

For further performance increase in dual panel mode disable the half frame buffer (see section

8.2.7) and disable the cursor (see section 8.2.9).

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bit 6-5

CPU to Memory Wait State Bits [1:0]

These bits are used to optimize the handshaking between the host interface and the memory con-

troller. The bits should be set according to the relationship between BCLK and MCLK – see the

table below where T_Band T_Mare the BCLK and MCLK periods respectively.

Table 8-16: Minimum Memory Timing Selection

Wait State Bits [1:0]

Condition

no restrictions (default)

2T - 4ns > T

undefined

bits 4-0

Display FIFO Threshold Bits [4:0]

These bits specify the display FIFO depth required to sustain uninterrupted display fetches. When

these bits are all “0”, the display FIFO depth is calculated automatically.

These bits should always be set to 0, except in the following configurations:

Landscape mode at 15/16 bpp (with MCLK=PCLK),

Portrait mode at 8/16 bpp (with MCLK=PCLK).

When in the above configurations, a value of 1Bh should be used.

Note

The utility 13505CFG will, given the correct configuration values, automatically generate the

correct values for the Performance Enhancement Registers.

8.2.8 Look-Up Table Registers

Look-Up Table Address Register

REG[24h]

LUT Address LUT Address LUT Address LUT Address LUT Address LUT Address LUT Address LUT Address

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

bits 7-0

LUT Address Bits [7:0]

These 8 bits control a pointer into the Look-Up Tables (LUT). The S1D13505 has three 256-posi-

tion, 4-bit wide LUTs, one for each of red, green, and blue – refer to “Look-Up Table Architecture”

for details.

This register selects which LUT entry is read/write accessible through the LUT Data Register

(REG[26h]). Writing the LUT Address Register automatically sets the pointer to the Red LUT.

Accesses to the LUT Data Register automatically increment the pointer.

For example, writing a value 03h into the LUT Address Register sets the pointer to R[3]. A subse-

quent access to the LUT Data Register accesses R[3] and moves the pointer onto G[3]. Subsequent

accesses to the LUT Data Register move the pointer onto B[3], R[4], G[4], B[4], R[5], etc. Note that

the RGB data is inserted into the LUT after the Blue data is written, i.e. all three colors must be

written before the LUT is updated.

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Look-Up Table Data Register

REG[26h]

LUT Data

Bit 3

LUT Data

Bit 2

LUT Data

Bit 1

LUT Data

Bit 0

n/a

bits 7-4

LUT Data

This register is used to read/write the RGB Look-Up Tables. This register accesses the entry at the

pointer controlled by the Look-Up Table Address Register (REG[24h]) – see above.

Accesses to the Look-Up Table Data Register automatically increment the pointer.Note that the

RGB data is inserted into the LUT after the Blue data is written, i.e. all three colors must be written

before the LUT is updated.

8.2.9 Ink/Cursor Registers

Ink/Cursor Control Register

REG[27h]

Ink/Cursor

Mode

Bit 1

Ink/Cursor

Mode

Bit 0

Cursor High

Threshold

Bit 3

Cursor High

Threshold

Bit 2

Cursor High

Threshold

Bit 1

Cursor High

Threshold

Bit 0

n/a

bit 7-6

Ink/Cursor Control Bits [1:0]

These bits select the operating mode of the Ink/Cursor circuitry. See table below

Table 8-17: Ink/Cursor Selection

REG[27h]

Operating Mode

Bit 7

Bit 6

inactive

Cursor

Ink

reserved

bit 3-0

Ink/Cursor FIFO Threshold Bits [3:0]

These bits specify the Ink/Cursor FIFO depth required to sustain uninterrupted display fetches.

When these bits are all 0, the Ink/Cursor FIFO depth is calculated automatically.

Cursor X Position Register 0

REG[28h]

Cursor X

Position Bit 7 Position Bit 6 Position Bit 5 Position Bit 4 Position Bit 3 Position Bit 2 Position Bit 1 Position Bit 0

Cursor X Position Register 1

REG[29h]

Cursor X

Position Bit 9 Position Bit 8

Cursor X

Reserved

n/a

REG[29] bit 7

Reserved

This bit must be set to 0.

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REG[28] bits 7-0

REG[29] bits 1-0

Cursor X Position Bits [9:0]

In Cursor mode, this 10-bit register is used to program the horizontal pixel position of the Cursor’s

top left pixel.

This register must be set to 0 in Ink mode.

Note

The Cursor X Position register must be set during VNDP (vertical non-display period). Check

the VNDP status bit (REG[0Ah] bit 7) to determine if you are in VNDP, then update the register.

Cursor Y Position Register 0

REG[2Ah]

Cursor Y

Position Bit 7 Position Bit 6 Position Bit 5 Position Bit 4 Position Bit 3 Position Bit 2 Position Bit 1 Position Bit 0

Cursor Y Position Register 1

REG[2Bh]

Cursor Y

Position Bit 9 Position Bit 8

Cursor Y

Reserved

n/a

REG[2Bh] bit 7

Reserved

This bit must be set to 0.

REG[2Ah] bits 7-0

REG[2Bh] bits 1-0

Cursor Y Position Bits [9:0]

In Cursor mode, this 10-bit register is used to program the vertical pixel position of the Cursor’s top

left pixel.

This register must be set to 0 in Ink mode.

Note

The Cursor Y Position register must be set during VNDP (vertical non-display period). Check

the VNDP status bit (REG[0Ah] bit 7) to determine if you are in VNDP, then update the register.

Ink/Cursor Color 0 Register 0

REG[2Ch]

Cursor Color Cursor Color Cursor Color Cursor Color Cursor Color Cursor Color Cursor Color Cursor Color

0 Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0

Ink/Cursor Color 0 Register 1

REG[2Dh]

Cursor Color Cursor Color Cursor Color Cursor Color Cursor Color Cursor Color Cursor Color Cursor Color

0 Bit 15 0 Bit 14 0 Bit 13 0 Bit 12 0 Bit 11 0 Bit 10 0 Bit 9 0 Bit 8

REG[2C] bits 7:0

REG[2D] bits 7:0

Ink/Cursor Color 0 Bits [15:0]

These bits define the 5-6-5 RGB Ink/Cursor color 0.

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Ink/Cursor Color 1 Register 0

REG[2Eh]

Cursor Color Cursor Color Cursor Color Cursor Color Cursor Color Cursor Color Cursor Color Cursor Color

1 Bit 7 1 Bit 6 1 Bit 5 1 Bit 4 1 Bit 3 1 Bit 2 1 Bit 1 1 Bit 0

Ink/Cursor Color 1 Register 1

REG[2Fh]

Cursor Color Cursor Color Cursor Color Cursor Color Cursor Color Cursor Color Cursor Color Cursor Color

1 Bit 15

1 Bit 14

1 Bit 13

1 Bit 12

1 Bit 11

1 Bit 10

1 Bit 9

1 Bit 8

REG[2E] bits 7:0

REG[2F] bits 7:0

Ink/Cursor Color 1 Bits [15:0]

These bits define the 5-6-5 RGB Ink/Cursor color 1

Ink/Cursor Start Address Select Register

REG[30h]

Ink/Cursor

Start Address Start Address Start Address Start Address Start Address Start Address Start Address Start Address

Select

Bit 7

Select

Bit 6

Select

Bit 5

Select

Bit 4

Select

Bit 3

Select

Bit 2

Select

Bit 1

Select

Bit 0

bits 7-0

Ink/Cursor Start Address Select Bits [7:0]

These bits define the start address for the Ink/Cursor buffer. The Ink/Cursor buffer must be posi-

tioned where it does not conflict with the image buffer and half-frame buffer – see Memory Map-

ping for details.

The start address for the Ink/Cursor buffer is programmed as shown in the following table where

Display Buffer Size represents the size in bytes of the attached DRAM device (see MD[7:6] in

Summary of Configuration Options):

Table 8-18: Ink/Cursor Start Address Encoding

Ink/Cursor Start Address Bits [7:0]

Start Address (Bytes)

Display Buffer Size - 1024

Display Buffer Size - (n × 8192)

n = 255...1

The Ink/Cursor image is stored contiguously. The address offset from the starting word of line n to

the starting word of line n+1 is calculated as follows:

Ink Address Offset (words) = REG[04h] + 1

Cursor Address Offset (words) = 8

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Alternate FRM Register

REG[31h]

Alternate

FRM

Bit 7

Alternate

FRM

Bit 6

Alternate

FRM

Bit 5

Alternate

FRM

Bit 4

Alternate

FRM

Bit 3

Alternate

FRM

Bit 2

Alternate

FRM

Bit 1

Alternate

FRM

Bit 0

bits 7-0

Alternate Frame Rate Modulation Select

selected. For single passive, or dual passive with the half frame buffer enabled, either the original or

the alternate FRM scheme may be used. The alternate FRM scheme may produce more visually

appealing output. The following table shows the recommended alternate FRM scheme values.

Table 8-19: Recommended Alternate FRM Scheme

Panel Mode

0000 0000 or 1111 1111

0000 0000 or 1111 1010

1111 1111

Single Passive

Dual Passive w/Half Frame Buffer Enabled

Dual Passive w/Half Frame Buffer Disabled

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9 Display Buffer

The system addresses the display buffer through the CS#, M/R#, and AB[20:0] input pins. When

CS# = 0 and M/R# = 1, the display buffer is addressed by bits AB[20:0]. See the table below:

Table 9-1: S1D13505 Addressing

CS#

M/R#

Access

• REG[00h] is addressed when AB[5:0] = 0

• REG[01h] is addressed when AB[5:0] = 1

• REG[n] is addressed when AB[5:0] = n

Memory access: the 2M byte display buffer is addressed by

AB[20:0]

S1D13505 not selected

The display buffer address space is always 2M bytes. However, the physical display buffer may be

either 512K bytes or 2M bytes – see “Summary of Configuration Options”.

The display buffer can contain an image buffer, one or more Ink/Cursor buffers, and a half-frame

buffer.

A 512K byte display buffer is replicated in the 2M byte address space – see the figure below.

512K Byte Buffer

AB[20:0]

2M Byte Buffer

000000h

Image Buffer

Ink/Cursor Buffer

Half-Frame Buffer

Image Buffer

07FFFFh

080000h

Image Buffer

Ink/Cursor Buffer

Half-Frame Buffer

0FFFFFh

100000h

Image Buffer

Ink/Cursor Buffer

Half-Frame Buffer

17FFFFh

180000h

Image Buffer

Ink/Cursor Buffer

Half-Frame Buffer

Ink/Cursor Buffer

Half-Frame Buffer

1FFFFFh

Figure 9-1: Display Buffer Addressing

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9.1 Image Buffer

The image buffer contains the formatted display mode data – see “Display Mode Data Formats”.

The displayed image(s) could take up only a portion of this space; the remaining area may be used

for multiple images – possibly for animation or general storage. See “Display Configuration” on

page 124 for the relationship between the image buffer and the display.

9.2 Ink/Cursor Buffers

The Ink/Cursor buffers contain formatted image data for the Ink or Cursor. There may be several

Ink/Cursor images stored in the display buffer but only one may be active at any given time. See

“Ink/Cursor Architecture” on page 133 for details.

9.3 Half Frame Buffer

In dual panel mode, with the half frame buffer enabled, the top of the display buffer is allocated to

the half-frame buffer. The size of the half frame buffer is a function of the panel resolution and

whether the panel is color or monochrome type:

Half Frame Buffer Size (in bytes)= (panel width x panel length) * factor / 16

where factor

= 4 for color panel

= 1 for monochrome panel

For example, for a 640x480 8 bpp color panel the half frame buffer size is 75K bytes. In a 512K byte

display buffer, the half-frame buffer resides from 6D400h to 7FFFFh. In a 2M byte display buffer,

the half-frame buffer resides from 1ED400h to 1FFFFFh.

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10 Display Configuration

10.1 Display Mode Data Format

The following diagrams show the display mode data formats for a little-endian system.

1 bpp:

bit 7

bit 0

P P P P

Byte 0

= (A )

Panel Display

Host Address

2 bpp:

Display Memory

bit 7

bit 0

P P P P

Byte 0

Byte 1

P = (A , B )

Panel Display

Host Address

4 bpp:

Display Memory

bit 7

bit 0

P P P P

Byte 0

Byte 1

Byte 2

= (A , B , C , D )

Panel Display

Host Address

8 bpp:

Display Memory

bit 7

bit 0

P P P P

Byte 0

Byte 1

Byte 2

= (A , B , C , D ,E , F , G , H )

Panel Display

Host Address

Display Memory

Figure 10-1: 1/2/4/8 Bit-per-pixel Format Memory Organization

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15 bpp:

Byte 0

P P P P

5-5-5 RGB

bit 7

bit 0

4-0

P = (R

, G

, B

)

Byte 1

Byte 2

Byte 3

Panel Display

Display Memory

5-6-5 RGB

Host Address

16 bpp:

P P P P

P P

bit 7

bit 0

Byte 0

Byte 1

Byte 2

Byte 3

4-0

5-0

4-0

= (R

, G

, B

)

Panel Display

Display Memory

Host Address

Figure 10-2: 15/16 Bit-per-pixel Format Memory Organization

Note

1. The Host-to-Display mapping shown here is for a little-endian system.

2. For 15/16 bpp formats, R_n, G_n, B_nrepresent the red, green, and blue color components.

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10.2 Image Manipulation

The figure below shows how Screen 1 and 2 images are stored in the image buffer and positioned

on the display. Screen 1 and Screen 2 can be parts of a larger virtual image or images.

• (REG[17h],REG[16h]) defines the width of the virtual image(s)

• (REG[12h],REG[11h],REG[10]) defines the starting word of the Screen 1,

(REG[15h],REG[14h],REG[13]) defines the starting word of the Screen 2

• REG[18h] bits [3:0] define the starting pixel within the starting word for Screen 1, REG[18h]

bits [7:4] define the starting pixel within the starting word for Screen 2

• (REG[0Fh],REG[0Eh]) define the last line of Screen 1, the remainder of the display is taken up

by Screen 2

Image Buffer

Display

(REG[12h], REG[11h], REG[10h])

REG[18h] bits [3:0]

((REG[09h], REG[08h])+1) lines

Screen 1

Line 0

Line 1

Screen 1

(REG[15h], REG[14h], REG[13h])

REG[18h] bits [7:4]

Line (REG[0Fh], REG[0Eh])

Screen 2

((REG[04h]+1)*8) pixels

(REG[17h], REG[16h])

Figure 10-3: Image Manipulation

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11 Look-Up Table Architecture

The following figures are intended to show the display data output path only.

11.1 Monochrome Modes

The green Look-Up Table (LUT) is used for all monochrome modes.

1 Bit-per-pixel Monochrome mode

Green Look-Up Table 256x4

4-bit Grey Data

1 bit-per-pixel data

from Image Buffer

Figure 11-1: 1 Bit-per-pixel Monochrome Mode Data Output Path

2 Bit-per-pixel Monochrome Mode

Green Look-Up Table 256x4

4-bit Grey Data

2 bit-per-pixel data

from Image Buffer

Figure 11-2: 2 Bit-per-pixel Monochrome Mode Data Output Path

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4 Bit-per-pixel Monochrome Mode

Green Look-Up Table 256x4

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

4-bit Grey Data

4 bit-per-pixel data

from Image Buffer

Figure 11-3: 4 Bit-per-pixel Monochrome Mode Data Output Path

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11.2 Color Modes

1 Bit-per-pixel Color Mode

Red Look-Up Table 256x4

4-bit Red Data

4-bit Green Data

4-bit Blue Data

Green Look-Up Table 256x4

Blue Look-Up Table 256x4

1 bit-per-pixel data

from Image Buffer

Figure 11-4: 1 Bit-per-pixel Color Mode Data Output Path

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2 Bit-per-pixel Color Mode

Red Look-Up Table 256x4

4-bit Red Data

4-bit Green Data

4-bit Blue Data

Green Look-Up Table 256x4

Blue Look-Up Table 256x4

2 bit-per-pixel data

from Image Buffer

Figure 11-5: 2 Bit-per-pixel Color Mode Data Output Path

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4 Bit-per-pixel Color Mode

Red Look-Up Table 256x4

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

4-bit Red Data

4-bit Green Data

4-bit Blue Data

Green Look-Up Table 256x4

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

Blue Look-Up Table 256x4

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

4 bit-per-pixel data

from Image Buffer

Figure 11-6: 4 Bit-per-pixel Color Mode Data Output Path

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8 Bit-per-pixel Color Mode

Red Look-Up Table 256x4

0000 0000

0000 0001

0000 0010

0000 0011

0000 0100

0000 0101

0000 0110

0000 0111

4-bit Red Data

4-bit Green Data

4-bit Blue Data

1111 1000

1111 1001

1111 1010

1111 1011

1111 1100

1111 1101

1111 1110

1111 1111

Green Look-Up Table 256x4

0000 0000

0000 0001

0000 0010

0000 0011

0000 0100

0000 0101

0000 0110

0000 0111

1111 1000

1111 1001

1111 1010

1111 1011

1111 1100

1111 1101

1111 1110

1111 1111

Blue Look-Up Table 256x4

0000 0000

0000 0001

0000 0010

0000 0011

0000 0100

0000 0101

0000 0110

0000 0111

1111 1000

1111 1001

1111 1010

1111 1011

1111 1100

1111 1101

1111 1110

1111 1111

8 bit-per-pixel data

from Image Buffer

Figure 11-7: 8 Bit-per-pixel Color Mode Data Output Path

15/16 Bit-per-pixel Color Modes

The LUT is bypassed and the color data is directly mapped for this color mode – See “Display

Configuration” on page 124.

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12 Ink/Cursor Architecture

12.1 Ink/Cursor Buffers

The Ink/Cursor buffers contain formatted image data for the Ink Layer or Hardware Cursor. There

may be several Ink/Cursor images stored in the display buffer but only one may be active at any

given time.

The active Ink/Cursor buffer is selected by the Ink/Cursor Start Address register (REG[30h]). This

positioned where it does not conflict with the image buffer and half-frame buffer. The start address

for the Ink/Cursor buffer is programmed as shown in the following table:

Table 12-1: Ink/Cursor Start Address Encoding

Ink/Cursor Start

Address Bits [7:0]

Start Address (Bytes)

Comments

This default value is suitable for a cursor

when there is no half-frame buffer.

Display Buffer Size - 1024

These positions can be used to:

•

position an Ink buffer at the top of the

display buffer;

Display Buffer Size -

position an Ink buffer between the image

and half-frame buffers;

n = 255...1

(n × 8192)

position a Cursor buffer between the image

and half-frame buffers;

select from a multiple of Cursor buffers.

The Ink/Cursor image is stored contiguously. The address offset from the starting word of line n to

the starting word of line n+1 is calculated as follows:

Ink Address Offset (words) = REG[04h] + 1

Cursor Address Offset (words) = 8

12.2 Ink/Cursor Data Format

The Ink/Cursor image is always 2 bit-per-pixel. The following diagram shows the Ink/Cursor data

format for a little-endian system.

2 bpp:

bit 7

bit 0

P P

P P P

Byte 0

Byte 1

= (A , B )

Panel Display

Host Address

Ink/Cursor Buffer

Figure 12-1: Ink/Cursor Data Format

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The image data for pixel n, (A_n,B_n), selects the color for pixel n as follows:

Table 12-2: Ink/Cursor Color Select

(A ,B )

Color

Comments

Color 0

Color 1

Ink/Cursor Color 0 Register, (REG[2Dh],REG[2Ch])

Ink/Cursor Color 1 Register, (REG[2Fh],REG[2Eh])

Ink/Cursor is transparent – show background

Background

Ink/Cursor is transparent – show inverted

background

Inverted Background

12.3 Ink/Cursor Image Manipulation

12.3.1 Ink Image

The Ink image should always start at the top left pixel, i.e. Cursor X Position and Cursor Y Position

registers should always be set to zero. The width and height of the ink image are automatically calcu-

lated to completely cover the display.

12.3.2 Cursor Image

The Cursor image size is always 64x64 pixels. The Cursor X Position and Cursor Y Position

registers specify the position of the top left pixel. The following diagram shows how to position a

cursor.

P(0;0)

P(x;y)

P(x+63;y)

P(x;y+63)

P(x+63;y+63)

Figure 12-2: Cursor Positioning

where

x = (REG[29h] bits [1:0], REG[28h])

y = (REG[2Bh] bits [1:0], REG[2Ah])

REG[29h] bit 7 = 0

REG[2Bh] bit 7 = 0

Note

There is no means to set a negative cursor position. If a cursor must be set to a negative position,

this must be dealt with through software.

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13 SwivelView™

13.1 Concept

Computer displays are refreshed in landscape – from left to right and top to bottom; computer images

are stored in the same manner. When a display is used in SwivelView it becomes necessary to rotate

the display buffer image by 90°. SwivelView rotates the image 90° clockwise as it is written to the

display buffer. This rotation is done in hardware and is transparent to the programmer for all display

buffer reads and writes.

SwivelView uses a 1024 × 1024 pixel virtual image. The following figures show how the

programmer sees the image and how the image is actually stored in the display buffer. The display

is refreshed in the following sense: C–A–D–B. The application image is written to the S1D13505 in

the following sense: A–B–C–D. The S1D13505 rotates and stores the application image in the

following sense: C–A–D–B, the same sense as display refresh.

1024 pixels

display

start

address

portrait

window

image in display buffer

image seen by programmer

Figure 13-1: Relationship Between The Screen Image and the Image Residing in the Display Buffer

Note

The image must be written with a 1024 pixel offset between adjacent lines (e.g. 1024 bytes for

8 bpp mode or 2048 bytes for 16 bpp mode) and a display start address that is non-zero.

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13.2 Image Manipulation in SwivelView

Display Start Address

It can be seen from Figure 13-1 that the top left pixel of the display is not at the top left corner of the

virtual image, i.e. it is non-zero. The Display Start Address register must be set accordingly:

Display Start Address (words)

=(1024 - W)

=(1024 - W) / 2

for 16 bpp mode

for 8 bpp mode

Memory Address Offset

The Memory Address Offset register must be set for a 1024 pixel offset:

Memory Address Offset (words) =1024

=512

for 16 bpp mode

for 8 bpp mode

Horizontal Panning

Horizontal panning is achieved by changing the start address. Panning of the portrait window to the

right by 1 pixel is achieved by adding 1024 pixels to the Display Start Address register (or

subtracting if panning to the left).

• Panning to right by 1 pixel: add current start address by 1024 (16 bpp mode) or 512 (8 bpp

mode).

• Panning to left by 1 pixel: subtract current start address by 1024 (16 bpp mode) or 512 (8 bpp

mode).

How far the portrait window can be panned to the right is limited not only by 1024 pixels but also

by the amount of physical memory installed.

Vertical Scrolling

Vertical scrolling is achieved by changing the Display Start Address register and/or changing the

Pixel Panning register.

• Increment/decrement Display Start Address register in 8 bpp mode: scroll down/up by 2 lines.

• Increment/decrement Display Start Address register in 16 bpp mode: scroll down/up by 1 line.

• Increment/decrement Pixel Panning register in 8 bpp or 16 bpp mode: scroll down/up by 1 line.

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13.3 Physical Memory Requirement

Because the programmer must now deal with a virtual display, the amount of image buffer required

for a particular display mode has increased. The minimum amount of image buffer required is:

Minimum Required Image Buffer (bytes)

=(1024 × H) × 2

=(1024 × H)

for 16 bpp mode

for 8 bpp mode

For single panel, the required display buffer size is the same as the image buffer required. For dual

panel, the display buffer required is the sum of the image buffer required and the half-frame buffer

memory required. The half-frame buffer memory requirement is:

Half-Frame Buffer Memory (bytes)

=(W × H) / 4

=(W × H) / 16

for color mode

for monochrome mode

The half-frame buffer memory is always located at the top of the physical memory.

For simplicity the hardware cursor and ink layer memory requirement is ignored. The hardware

cursor and ink layer memory must be located at 16K byte boundaries and it must not overlap the

image buffer and half-frame buffer memory areas.

Even though the virtual display is 1024×1024 pixels, the actual panel window is always smaller.

Thus it is possible for the display buffer size to be smaller than the virtual display but large enough

to fit both the required image buffer and the half-frame buffer memory. This poses a maximum

“accessible” horizontal virtual size limit.

Maximum Accessible Horizontal Virtual Size (pixels)

= (Physical Memory – Half-Frame Buffer Memory) / 2048

= (Physical Memory – Half-Frame Buffer Memory) / 1024

for 16 bpp mode

for 8 bpp mode

For example, a 640×480 single panel running 8 bpp mode requires 480K byte of image buffer and

0K byte of half-frame buffer memory. The virtual display size is 1024×1024 = 1M byte. The

programmer may use a 512K byte DRAM which is smaller than the 1M byte virtual display but

greater than the 480K byte minimum required image buffer. The maximum accessible horizontal

virtual size is = (512K byte - 0K byte) / 1024 = 512. The programmer therefore has room to pan the

portrait window to the right by 512 - 480 = 32 pixels. The programmer also should not read/write to

the memory beyond the maximum accessible horizontal virtual size because that memory is either

reserved for the half-frame buffer or not associated with any real memory at all.

The following table summarizes the DRAM size requirement for SwivelView using different panel

sizes and display modes. Note that DRAM size for the S1D13505 is limited to either 512K byte or

2M byte. The calculation is based on the minimum required image buffer size. The calculated

minimum display buffer size is based on the image buffer and the half-frame buffer only; it does not

take into account the hardware cursor/ink layer and so it may or may not be sufficient to support it

– this is noted in the table. The hardware cursor requires 1K byte of memory and the 2-bit ink layer

requires (W × H) / 4 bytes of memory; both must reside at 16K byte boundaries but only one is

supported at a time. The table shows only one possible sprite/ink layer location – at the highest

possible 16K byte boundary below the half-frame buffer which is always at the top.

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Table 13-2 Minimum DRAM Size Required for SwivelView

Sprite/Ink

Ink/Cursor

Layer Buffer

Layer Location

Size

Display

Mode

Display Half-Frame Minimum

Buffer Size Buffer Size DRAM Size

Panel Size Panel Type

8 bpp

16 bpp

8 bpp

240KB

Color

480KB

0KB

Single

Mono

496KB/ 480KB

240KB

16 bpp

8 bpp

480KB

320 × 240

Color

1KB/18.75KB

480KB/464KB

240KB

480KB

240KB

480KB

960KB

480KB

960KB

480KB

960KB

480KB

960KB

600KB

1.2MB

600KB

1.2MB

600KB

1.2MB

600KB

1.2MB

512KB

18.75KB

4.69KB

16 bpp

8 bpp

480KB/--

Dual

Mono

496KB/480KB

16 bpp

8 bpp

496KB/--

2032KB/1968KB

496KB/--

Color

16 bpp

8 bpp

2MB

Single

Mono

0KB

512KB

16 bpp

8 bpp

640 × 480

Color

1KB/75KB

2MB

2032K/1968K

75KB

16 bpp

8 bpp

Dual

512KB

496KB/--

Mono

18.75KB

16 bpp

8 bpp

2032KB/1968KB

Color

16 bpp

8 bpp

Single

Mono

0KB

16 bpp

8 bpp

2MB

1KB/

800 × 600

Color

2032KB/1920KB

117.19KB

29.30KB

16 bpp

8 bpp

Dual

Mono

16 bpp

Where KB = K bytes and MB = 1024K bytes

13.4 Limitations

The following limitations apply to SwivelView:

• Only 8 bpp and 16 bpp modes are supported – 1/2/4 bpp modes are not supported.

• Hardware cursor and ink layer images are not rotated – software rotation must be used. Swivel-

View must be turned off when the programmer is accessing the sprite or the ink layer.

• Split screen images appear side-by-side, i.e. the portrait display is split vertically.

• Pixel panning works vertically.

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14 Clocking

14.1 Maximum MCLK: PCLK Ratios

Table 14-1: Maximum PCLK Frequency with EDO-DRAM

Maximum PCLK Allowed

Ink

Display type

N_RC

1 bpp

2 bpp

4 bpp

8 bpp

16 bpp

• Single Panel.

• CRT.

• Dual Monochrome/Color Panel with Half Frame Buffer

Disabled.

5, 4, 3

MCLK

• Simultaneous CRT + Single Panel.

• Simultaneous CRT + Dual Monochrome/Color Panel

with Half Frame Buffer Disabled.

off

• Dual Monochrome Panel with Half Frame Buffer

Enabled.

MCLK/2 MCLK/2 MCLK/2 MCLK/2 MCLK/3

• Simultaneous CRT + Dual Monochrome Panel with

Half Frame Buffer Enable.

MCLK

MCLK MCLK/2 MCLK/2 MCLK/2

• Dual Color Panel with Half Frame Buffer Enabled.

MCLK/2 MCLK/2 MCLK/2 MCLK/3 MCLK/3

MCLK/2 MCLK/2 MCLK/2 MCLK/2 MCLK/3

• Simultaneous CRT + Dual Color Panel with Half

Frame Buffer Enable.

• Single Panel.

• CRT.

MCLK

MCLK MCLK/2 MCLK/2 MCLK/2

• Dual Monochrome/Color Panel with Half Frame Buffer

Disabled.

• Simultaneous CRT + Single Panel.

MCLK

MCLK MCLK/2 MCLK/2

• Simultaneous CRT + Dual Monochrome/Color Panel

with Half Frame Buffer Disabled.

• Dual Monochrome Panel with Half Frame Buffer

Enabled.

MCLK/2 MCLK/3 MCLK/3 MCLK/3 MCLK/3

MCLK/2 MCLK/2 MCLK/2 MCLK/3 MCLK/3

• Simultaneous CRT + Dual Monochrome Panel with

Half Frame Buffer Enable.

MCLK/2 MCLK/2 MCLK/2 MCLK/2 MCLK/3

• Dual Color Panel with Half Frame Buffer Enabled.

MCLK/3 MCLK/3 MCLK/3 MCLK/3 MCLK/4

MCLK/2 MCLK/2 MCLK/3 MCLK/3 MCLK/3

MCLK/2 MCLK/2 MCLK/2 MCLK/2 MCLK/3

• Simultaneous CRT + Dual Color Panel with Half

Frame Buffer Enable.

Hardware Functional Specification

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Table 14-2: Maximum PCLK Frequency with FPM-DRAM

Maximum PCLK allowed

Ink

Display type

N_RC

1 bpp

2 bpp

4 bpp

8 bpp

16 bpp

• Single Panel.

• CRT.

• Dual Monochrome/Color Panel with Half Frame Buffer

Disabled.

5, 4, 3

MCLK

• Simultaneous CRT + Single Panel.

• Simultaneous CRT + Dual Monochrome/Color Panel

with Half Frame Buffer Disabled.

off

• Dual Monochrome with Half Frame Buffer Enabled.

MCLK/2 MCLK/2 MCLK/2 MCLK/2 MCLK/3

MCLK/2 MCLK/2 MCLK/2 MCLK/2 MCLK/2

• Simultaneous CRT + Dual Monochrome Panel with

Half Frame Buffer Enable.

MCLK

MCLK MCLK/2 MCLK/2

• Dual Color with Half Frame Buffer Enabled.

MCLK/2 MCLK/2 MCLK/2 MCLK/2 MCLK/3

MCLK/2 MCLK/2 MCLK/2 MCLK/2 MCLK/2

MCLK/2 MCLK/2 MCLK/2 MCLK/2 MCLK/3

• Simultaneous CRT + Dual Color Panel with Half

Frame Buffer Enable.

• Single Panel.

• CRT.

MCLK

MCLK MCLK/2 MCLK/2 MCLK/2

• Dual Monochrome/Color Panel with Half Frame Buffer

Disabled.

• Simultaneous CRT + Single Panel.

MCLK

MCLK MCLK/2 MCLK/2

• Simultaneous CRT + Dual Monochrome/Color Panel

with Half Frame Buffer Disabled.

• Dual Monochrome with Half Frame Buffer Enabled.

MCLK/2 MCLK/2 MCLK/3 MCLK/3 MCLK/3

MCLK/2 MCLK/2 MCLK/2 MCLK/2 MCLK/3

MCLK/3 MCLK/3 MCLK/3 MCLK/3 MCLK/4

MCLK/2 MCLK/2 MCLK/2 MCLK/3 MCLK/3

MCLK/2 MCLK/2 MCLK/2 MCLK/2 MCLK/3

• Simultaneous CRT + Dual Monochrome Panel with

Half Frame Buffer Enable.

• Dual Color with Half Frame Buffer Enabled.

• Simultaneous CRT + Dual Color Panel with Half

Frame Buffer Enable.

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14.2 Frame Rate Calculation

The frame rate is calculated using the following formula:

PCLK_max

FrameRate = ----------------------------------------------------------------------------------------

(HDP + HNDP) × (VDP + VNDP)

Where:

VDP

= Vertical Display Period

= REG[09h] bits [1:0], REG[08h] bits [7:0] + 1

VNDP = Vertical Non-Display Period

= REG[0Ah] bits [5:0] + 1

= in table below

HDP

= Horizontal Display Period

= ((REG[04h] bits [6:0]) + 1) * 8Ts

= ((REG[05h] bits [4:0]) + 1) * 8Ts

= given in table below

= PCLK

HNDP = Horizontal Non-Display Period

= Pixel Clock

Table 14-3: Example Frame Rates with Ink Disabled

Maximum

Maximum Frame

Rate (Hz)

Minimum

Panel

DRAM Type

Color Depth

(bpp)

Pixel

Clock

(MHz)

Display

Resolution

(Speed Grade)

HNDP(T )

Panel

CRT

• Single Panel.

1/2/4/8

800x600

• CRT.

15/16

• Dual Monochrome/Color Panel

with Half Frame Buffer Disabled.

1/2/4/8

15/16

123

119

247

242

243

232

471

441

640x480

640x240

480x320

320x240

• Simultaneous CRT + Single Panel.

1/2/4/8

15/16

• Simultaneous CRT + Dual

Monochrome/Color Panel with Half

Frame Buffer Disabled.

50ns

EDO-DRAM

1/2/4/8

15/16

MClk = 40MHz

= 4

= 1.5

1/2/4/8

15/16

= 2

RCD

• Dual Color with Half Frame Buffer

Enabled.

1/2/4/8

13.3

2,3

800x600

15/16

• Dual Mono with Half Frame Buffer

Enabled.

1/2/4/8

15/16

123

640x480

13.3

Hardware Functional Specification

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Table 14-3: Example Frame Rates with Ink Disabled (Continued)

Maximum

Maximum Frame

Minimum

Rate (Hz)

Panel

DRAM Type

Color Depth

(bpp)

Pixel

Clock

(MHz)

Display

Resolution

(Speed Grade)

HNDP(T )

Panel

CRT

• Single Panel.

1/2/4/8

800x600

• CRT.

15/16

• Dual Mono/Color Panel with Half

Frame Buffer Disabled.

1/2/4/8

15/16

101

640x480

640x240

480x320

320x240

• Simultaneous CRT + Single Panel.

1/2/4/8

15/16

203

200

196

388

380

• Simultaneous CRT + Dual

Mono/Color Panel with Half Frame

Buffer Disabled.

60ns

EDO-DRAM

1/2/4/8

15/16

MClk = 33MHz

= 4

= 1.5

1/2/4/8

15/16

= 2

RCD

• Dual Color with Half Frame Buffer

Enabled.

1/2/4/8

16.5

2,3

800x600

15/16

• Dual Mono with Half Frame Buffer

Enabled.

1/2/4/8

15/16

16.5

103

640x480

• Single Panel.

1/2/4/8

800x600

• CRT.

15/16

• Dual Mono/Color Panel with Half

Frame Buffer Disabled.

1/2/4/8

15/16

640x480

640x240

480x320

320x240

• Simultaneous CRT + Single Panel.

1/2/4/8

15/16

142

136

152

145

294

280

• Simultaneous CRT + Dual

Mono/Color Panel with Half Frame

Buffer Disabled.

60ns

FPM-DRAM

1/2/4/8

15/16

MClk = 25MHz

1/2/4/8

15/16

= 4

= 1.5

• Dual Mono with Half Frame Buffer

Enabled.

800x600

1/2/4/8/15/16

1/2/4/8

12.5

8.33

12.5

8.33

= 2

RCD

640x480

640x400

• Dual Color with Half Frame Buffer

Enabled.

2,3

800x600

15/16

1/2/4/8

15/16

640x480

1. Must set N_RC= 4MCLK. See REG[22h], Performance Enhancement Register.

2. 800x600 @ 16 bpp requires 2M bytes of display buffer for all display types.

3. 800x600 @ 8 bpp on a dual color panel requires 2M bytes of display buffer if the half frame

buffer is enabled.

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Hardware Functional Specification

Issue Date: 01/02/02

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4. Optimum frame rates for panels range from 60Hz to 150Hz. If the maximum refresh rate is too

high for a panel, MCLK should be reduced or PCLK should be divided down.

5. Half Frame Buffer disabled by REG[1Bh] bit 0.

6. When setting a horizontal resolution greater than 767 pixels, with a color depth of 15/16 bpp,

the Memory Offset Registers (REG[16h], REG[17h]) must be set to a virtual horizontal pixel

resolution of 1024.

14.3 Bandwidth Calculation

When calculating the average bandwidth, there are two periods that must be calculated separately.

The first period is the time when the CPU is in competition with the display refresh fetches. The CPU

can only access the memory when the display refresh releases the memory controller. The CPU

bandwidth during this period is called the “bandwidth during display period”.

The second period is the time when the CPU has full access to the memory, with no competition from

the display refresh. The CPU bandwidth during this period is called the “bandwidth during non

display period.”

To calculate the average bandwidth, calculate the percentage of time between display period and non

display period. The percentage of display period is multiplied with the bandwidth during display

period. The percentage of non display period is multiplied with the bandwidth during non display

period. The two products are summed to provide the average bandwidth.

Bandwidth during non display period

Based on simulation, it requires a minimum of 12 MCLKs to service one, two byte, CPU access to

memory. This includes all the internal handshaking and assumes that N_RCis set to 4MCLKs and the

wait state bits are set to 10b.

Bandwidth during non display period = f(MCLK) / 6 Mb/s

Bandwidth during display period

The amount of time taken up by display refresh fetches is a function of the color depth, and the

display type. Below is a table of the number of MCLKs required for various memory fetches to

display 16 pixels. Assuming N_RC= 4MCLKs.

Table 14-4: Number of MCLKs required for various memory access

Memory access

Half Frame Buffer, monochrome

Half Frame Buffer, color

Display @ 1 bpp

Number of MCLKs

Display @ 2 bpp

Display @ 4 bpp

Display @ 8 bpp

Display @ 16 bpp

CPU

Hardware Functional Specification

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Table 14-5: Total # MCLKs taken for Display refresh

MCLKs for Display Refresh

Display

1 bpp 2 bpp 4 bpp 8 bpp 16 bpp

• Single Panel.

• CRT.

• Dual Monochrome/Color Panel with Half Frame Buffer Disabled.

• Simultaneous CRT + Single Panel.

• Simultaneous CRT + Dual Monochrome/Color Panel with Half Frame

Buffer Disabled.

• Dual Monochrome Panel with Half Frame Buffer Enabled.

• Simultaneous CRT + Dual Monochrome Panel with Half Frame

Buffer Enable.

• Dual Color Panel with Half Frame Buffer Enabled.

Bandwidth during display period = MIN (bandwidth during non display period, B/C/D)

where B = number of MCLKs left available for CPU access after every 16 pixels drawn

= (f(MCLK)/f(PCLK) * 16 - Total MCLK for Display refresh), units in MCLKs 16 pixels

where C = number of MCLKs required to service 1 CPU access (2 bytes of data)

= 4, units in MCLKs/2 bytes

where D = time to draw 16 pixels

= 16 / f(PCLK), units in 16 pixels

The minimum function limits the bandwidth to the bandwidth available during non display period

should the display fetches constitute a small percentage of the overall memory activity.

For 16 bpp single panel/CRT/dual panel with half frame buffer disable, the number of MCLKs

required to fetch 16 pixels when PCLK = MCLK exceeds 16. In this case, the display fetch does not

allow any CPU access during the display period. CPU access can only be achieved during non

display periods.

Average Bandwidth

All displays have a horizontal non display period, and a vertical non display period. The formula for

calculating the percentage of non display period is as follows

Percentage of non display period = (HTOT * VTOT - WIDTH * HEIGHT)/(HTOT * VTOT)

Percentage of non display period for CRT = (800*525 - 640*480)/(800*525) = 26.6%

Percentage of non display period for single panel = (680*482 - 640*480)/680*482) = 6.2%

Percentage of non display period for dual panel = (680*242 - 640*240)/680*242) = 6.6%

Average Bandwidth =

Percentage of non display period * Bandwidth during non display period +

(1- Percentage of non display period) * Bandwidth during display period

S1D13505

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Hardware Functional Specification

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Table 14-6: Theoretical Maximum Bandwidth M byte/sec, Cursor/Ink disabled

Max. Pixel

Clock

(MHz)

Maximum Bandwidth (M byte/sec)

DRAM Type

640x480 Display

(Speed Grade)

1 bpp

2 bpp

4 bpp

8 bpp 16 bpp

• CRT.

• Simultaneous CRT + Single Panel.

6.67

6.36

1.79

• Simultaneous CRT + Dual

Monochrome/Color Panel with Half

Frame Buffer Disabled.

• Single Panel.

6.67

6.60

6.67

6.27

6.67

0.41

6.67

• Dual Monochrome/Color Panel with Half

Frame Buffer Disabled.

50ns

EDO-DRAM

MCLK = 40MHz

• Dual Monochrome Panel with Half Frame

Buffer Enabled.

6.27

6.67

5.11

6.67

3.94

6.67

13.3

• Simultaneous CRT + Dual Mono Panel

with Half Frame Buffer Enable.

6.36

5.44

• Dual Color Panel with Half Frame Buffer

Enabled.

6.67

6.27

6.67

6.27

6.67

13.3

6.67

• CRT.

• Simultaneous CRT + Single Panel.

5.5

5.24

1.47

• Simultaneous CRT + Dual

Monochrome/Color Panel with Half

Frame Buffer Disabled.

• Single Panel.

5.5

5.17

5.5

0.34

5.5

• Dual Monochrome/Color Panel with Half

Frame Buffer Disabled.

16.5

60ns

EDO-DRAM

MCLK = 33MHz

• Dual Monochrome Panel with Half Frame

Buffer Enabled.

16.5

5.17

5.5

4.21

5.5

3.25

5.5

• Simultaneous CRT + Dual Monochrome

Panel with Half Frame Buffer Enable.

5.24

4.49

• Dual Color Panel with Half Frame Buffer

Enabled.

16.5

5.5

5.17

5.5

Hardware Functional Specification

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Table 14-6: Theoretical Maximum Bandwidth M byte/sec, Cursor/Ink disabled (Continued)

Max. Pixel

Clock

(MHz)

Maximum Bandwidth (M byte/sec)

DRAM Type

640x480 Display

(Speed Grade)

1 bpp

2 bpp

4 bpp

8 bpp 16 bpp

• CRT.

• Simultaneous CRT + Single Panel.

4.16

3.97

1.11

• Simultaneous CRT + Dual

Monochrome/Color Panel with Half

Frame Buffer Disabled.

• Single Panel.

4.16

3.92

4.16

0.26

4.16

• Dual Monochrome/Color Panel with Half

Frame Buffer Disabled.

12.5

60ns

FPM-DRAM

MCLK = 25MHz

• Dual Monochrome with Half Frame Buffer

Enabled.

12.5

8.3

3.92

4.16

3.19

4.16

2.46

4.16

• Simultaneous CRT + Dual Monochrome

Panel with Half Frame Buffer Enable.

3.97

3.40

• Dual Color Panel with Half Frame Buffer

Enabled.

12.5

8.33

4.16

3.92

4.16

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15 Power Save Modes

Three power save modes are incorporated into the S1D13505 to meet the important need for power

reduction in the hand-held device market.

Table 15-1: Power Save Mode Function Summary

Power Save Mode (PSM)

No Display

LCDEnable = 0

CRTEnable = 0

Function

Normal

(Active)

Software

Suspend

Hardware

Suspend

Display Active?

Yes

Memory Access Possible?

LUT Access Possible?

Yes

Table 15-2: Pin States in Power-save Modes

Pin State

No Display

LCDEnable = 0

CRTEnable = 0

Pins

Normal

(Active)

Software

Hardware

Suspend

Forced Low

Off

Suspend

Forced Low

Off

Active

(LCDEnable = 1)

LCD outputs

LCDPWR

Forced Low

Off

(LCDEnable = 1)

CBR Refresh

only

DRAM outputs

Active

Refresh Only

Active

(CRTEnable = 1)

CRT/DAC outputs

Disabled

Active

Disabled

Active

Disabled

Host Interface outputs

Active

1. Refresh method is selectable by REG[1Ah]. Supported methods are CBR refresh, self-refresh

or no refresh at all.

2. The FPFRAME and FPLINE signals are set to their inactive states during power-down. The in-

active states are determined by REG[07h] bit 6 and REG[0Ch] bit 6. A problem may occur if

the inactive state is high (typical TFT/D-TFD configuration) and power is removed from the

LCD panel.

For software suspend the problem can be solved in the following manner. At power-down, first

enable software suspend, then wait ~120 VNDP, and lastly reverse the polarity bits. At power-

up, first disable software suspend, then revert the polarity bits back to the configuration state.

For hardware suspend an external hardware solution would be to use an AND gate on the sync

signal. One input of the AND gate is connected to a sync signal, the other input would be tied

to the panel’s logic power supply. When the panel’s logic power supply is removed, the sync

signal is forced low.

Hardware Functional Specification

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16 Mechanical Data

128-pin QFP15 surface mount package

Unit: mm

16.0 ± 0.4

14.0 ± 0.1

Index

128

0.4

0.16 ± 0.1

0~10°

0.5 ± 0.2

1.0

Figure 16-1: Mechanical Drawing QFP15

S1D13505

X23A-A-001-14

Hardware Functional Specification

Issue Date: 01/02/02

S1D13505 Embedded RAMDAC LCD/CRT Controller

Programming Notes and Examples

Document Number: X23A-G-003-07

Information in this document is subject to change without notice. You may download and use this document, but only for your own use in

evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any

representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain

material protected under U.S. and/or International Patent laws.

EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.

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S1D13505

X23A-G-003-07

Programming Notes and Examples

Issue Date: 01/02/05

Epson Research and Development

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Table of Contents

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.1 Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Memory Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.1 Display Buffer Location . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.1.1 Memory Organization for One Bit-Per-Pixel (2 Colors/Gray Shades) . . . . . . . . 16

3.1.2 Memory Organization for Two Bit-Per-Pixel (4 Colors/Gray Shades) . . . . . . . . 17

3.1.3 Memory Organization for Four Bit-Per-Pixel (16 Colors/Gray Shades) . . . . . . . 17

3.1.4 Memory Organization for Eight Bit-Per-Pixel (256 Colors/16 Gray Shades) . . . . 18

3.1.5 Memory Organization for Fifteen Bit-Per-Pixel (32768 Colors/16 Gray Shades) . . 18

3.1.6 Memory Organization for Sixteen Bit-Per-Pixel (65536 Colors/16 Gray Shades) . . 19

Look-Up Table (LUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.1 Look-Up Table Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.2 Look-Up Table Organization . . . . . . . . . . . . . . . . . . . . . . . . 21

Advanced Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5.1 Virtual Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5.1.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5.1.2 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

5.2 Panning and Scrolling . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

5.2.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

5.2.2 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

5.3 Split Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

5.3.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

5.3.2 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

LCD Power Sequencing and Power Save Modes . . . . . . . . . . . . . . . . . . . 38

6.1 LCD Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . 38

6.1.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

6.1.2 LCD Power Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

6.2 Software Power Save . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

6.2.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

6.3 Hardware Power Save . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Hardware Cursor/Ink Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

7.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

7.3 Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

7.3.1 Updating Hardware Cursor Addresses . . . . . . . . . . . . . . . . . . . . . . . . 46

Programming Notes and Examples

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7.3.2 Reg[29h] And Reg[2Bh] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

7.3.3 Reg [30h] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

7.3.4

No Top/Left Clipping on Hardware Cursor . . . . . . . . . . . . . . . . . . . . . 46

7.4 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

SwivelView . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

8.1 Introduction To SwivelView . . . . . . . . . . . . . . . . . . . . . . . . .47

8.2 S1D13505 SwivelView . . . . . . . . . . . . . . . . . . . . . . . . . . .47

8.3 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

8.4 Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

8.5 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

CRT Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

9.1.1 CRT Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

9.1.2 Simultaneous Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

10 Identifying the S1D13505 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

11 Hardware Abstraction Layer (HAL) . . . . . . . . . . . . . . . . . . . . . . . . . . .53

11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

11.2 Contents of the HAL_STRUCT . . . . . . . . . . . . . . . . . . . . . . . .53

11.3 Using the HAL library . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

11.4 API for 13505HAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

11.5 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

11.5.1 General HAL Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

11.5.2 Advanced HAL Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

11.5.3 Register / Memory Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

11.5.4 Color Manipulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

11.5.5 Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

11.5.6 Hardware Cursor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

11.5.7 Ink Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

11.5.8 Power Save . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

11.6 Porting LIBSE to a new target platform . . . . . . . . . . . . . . . . . . . . .78

11.6.1 Building the LIBSE library for SH3 target example . . . . . . . . . . . . . . . . . 79

11.6.2 Building the HAL library for the target example . . . . . . . . . . . . . . . . . . . 80

11.6.3 Building a complete application for the target example . . . . . . . . . . . . . . . . 80

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12 Sample Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

12.1.1 Sample code using the S1D13505 HAL API . . . . . . . . . . . . . . . . . . . . . 84

12.1.2 Sample code without using the S1D13505 HAL API . . . . . . . . . . . . . . . . . 86

12.1.3 Header Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Appendix A

Supported Panel Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107

A.1 Supported Panel Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107

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List of Tables

Table 2-1: S1D13505 Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 4-1: Look-Up Table Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 4-2: Recommended LUT Values for 1 Bpp Color Mode . . . . . . . . . . . . . . . . . . . . 22

Table 4-3: Example LUT Values for 2 Bpp Color Mode . . . . . . . . . . . . . . . . . . . . . . . 22

Table 4-4: Suggested LUT Values to Simulate VGA Default 16 Color Palette . . . . . . . . . . . 23

Table 4-5: Suggested LUT Values to Simulate VGA Default 256 Color Palette . . . . . . . . . . . 24

Table 4-6: Recommended LUT Values for 1 Bpp Gray Shade . . . . . . . . . . . . . . . . . . . . 26

Table 4-7: Suggested Values for 2 Bpp Gray Shade . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 4-8: Suggested LUT Values for 4 Bpp Gray Shade . . . . . . . . . . . . . . . . . . . . . . 27

Table 5-1: Number of Pixels Panned Using Start Address . . . . . . . . . . . . . . . . . . . . . . 33

Table 5-2: Active Pixel Pan Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 6-1: Suspend Refresh Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 7-1: Ink/Cursor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 7-2: Cursor/Ink Start Address Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 11-1: HAL Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 12-1: Passive Single Panel @ 320x240 with 40MHz Pixel Clock . . . . . . . . . . . . . . . 107

Table 12-2: Passive Single Panel @ 640x480 with 40MHz Pixel Clock . . . . . . . . . . . . . . . 107

Table 12-3: Passive Dual Panel @ 640x480 with 40MHz Pixel Clock . . . . . . . . . . . . . . . . 108

Table 12-4: TFT Single Panel @ 640x480 with 25.175 MHz Pixel Clock . . . . . . . . . . . . . . 108

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List of Figures

Figure 3-1: Pixel Storage for 1 Bpp (2 Colors/Gray Shades) in One Byte of Display Buffer . . . . .16

Figure 3-2: Pixel Storage for 2 Bpp (4 Colors/Gray Shades) in One Byte of Display Buffer . . . . .17

Figure 3-3: Pixel Storage for 4 Bpp (16 Colors/Gray Shades) in One Byte of Display Buffer . . . .17

Figure 3-4: Pixel Storage for 8 Bpp (256 Colors/16 Gray Shades) in One Byte of Display Buffer . .18

Figure 3-5: Pixel Storage for 15 Bpp (32768 Colors/16 Gray Shades) in

Two Bytes of Display Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Figure 3-6: Pixel Storage for 16 Bpp (65536 Colors/16 Gray Shades) in

Two Bytes of Display Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Figure 5-1: Viewport Inside a Virtual Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Figure 5-2: Memory Address Offset Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Figure 5-3: Screen 1 Start Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Figure 5-4: Pixel Panning Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Figure 5-5: 320x240 Single Panel For Split Screen . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 5-6: Screen 1 Line Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Figure 5-7: Screen 2 Display Start Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Figure 11-1: Components needed to build 13505 HAL application . . . . . . . . . . . . . . . . . . .78

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1 Introduction

This guide describes how to program the S1D13505 Embedded RAMDAC LCD/CRT

Controller. The guide presents the basic concepts of the LCD/CRT controller and provides

methods to directly program the registers. It explains some of the advanced techniques used

and the special features of the S1D13505.

The guide also introduces the Hardware Abstraction Layer (HAL), which is designed to

simplify the programming of the S1D13505. Most S1D1350x and S1D1370x products

support the HAL allowing OEMs to switch chips with relative ease.

This document is updated as appropriate. Please check the Epson Electronics America

Website at http://www.eea.epson.com for the latest revision of this document before

beginning any development.

We appreciate your comments on our documentation. Please contact us via email at

[email protected].

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2 Initialization

This section describes how to initialize the S1D13505. Sample code for performing

initialization of the S1D13505 is provided in the file init13505.c which is available on the

internet at http://www.eea.epson.com.

S1D13505 initialization can be broken into three steps. First, enable the S1D13505

controller (if necessary identify the specific controller). Next, set all the registers to their

initial values. Finally, program the Look-Up Table (LUT) with color values. This section

does not deal with programming the LUT, see Section 4 of this manual for LUT

programming details.

Note

When using an ISA evaluation board in a PC (i.e. S5U13505B00C), there are two addi-

tional steps that must be carried out before initialization. First, confirm that 16-bit mode

is enabled by writing to address F80000h. Then, if hardware suspend is enabled, disable

suspend mode by writing to F00000h. For further information on ISA evaluation boards

refer to the S5U13505B00C Rev. 1.0 ISA Bus Evaluation Board User Manual, document

number X23A-G-004-xx.

The following table represents the sequence and values written to the S1D13505 registers

to control a configuration with these specifications:

• 640x480 color dual passive format 1 LCD @ 75Hz.

• 8-bit data interface.

• 8 bit-per-pixel (bpp) - 256 colors.

• 31.5 MHz input clock.

• 50 ns EDO-DRAM, 2 CAS, 4 ms refresh, CAS before RAS.

Table 2-1: S1D13505 Initialization Sequence

[1B]

Value

Notes

See Also:

Example:

seDisplayFifo() - for enabling/disabling the FIFO.

seSetDisplayMode(DevID, DISP_MODE_LCD, CLEAR_MEM |

DISP_FIFO_OFF);

The above example will initialize for the LCD, and then clear display buffer memory

and blank the screen. The advantage to this approach is that afterwards the appli-

cation can write to the display without showing the image until memory is

completely updated; the application would then call seDisplayFIFO(DevID, ON).

Note

See note from seSetInit().

11.5.1 General HAL Support

General HAL support covers the miscellaneous functions. There is usually no more than

one or two functions devoted to any particular aspect of S1D13505 operation.

int seGetId(int DevID, int * pId)

Description: Reads the S1D13505 revision code register to determine the chip product and

revisions. The interpreted value is returned in pID.

Parameters: DevID

- registered device ID

pId

- pointer to the int to receive the controller ID.

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For the S1D13505 the return values are currently:

ID_S1D13505_REV0

ID_UNKNOWN

Other HAL libraries will return their respective controller IDs upon detection of

their controller.

Return Value: ERR_OK - operation completed with no problems

ERR_UNKNOWN_DEVICE - returned when pID returns ID_UNKNOWN.

(The HAL was unable to identify the display controller).

Note

seGetId() will disable hardware suspend on x86 platforms, and will enable the host in-

terface (register [1Bh]) on all platforms.

void seGetHalVersion(const char ** pVersion, const char ** pStatus,

const char **pStatusRevision)

Description: Retrieves the HAL library version. The return pointers are all to ASCII strings. A

typical return would be: *pVersion == “1.01” (HAL version 1.01),*pStatus == “B”

(The 'B' is the beta designator), *pStatusRevision == “5”. The programmer need

only create pointers of const char type to pass as parameters (see Example below).

Parameters: pVersion

- pointer to string of HAL version code

pStatus

- pointer to string of HAL status code (NULL is release)

pStatusRevision - pointer to string of HAL statusRevision

Return Value: None

Example:

const char *pVersion, *pStatus, *pStatusRevision;

seGetHalVersion( &pVersion, &pStatus, &pStatusRevision);

Note

This document was written for HAL version “1.04”, so any later versions should be a

superset of the functions described here.

void seGetLibseVersion(int ** Version)

Description: Retrieves the LIBSE library version for non-x86 platforms. The return pointer in

parameter Version is valid if the function return value is ERR_OK.

Parameters: Version

- pointer to an int to store LIBSE version code

Return Value: ERR_OK - no problems encountered, version code is valid

ERR_FAILED - unable to complete operation. Probably on x86 platform where

LIBSE is not used.

int seGetMemSize(int DevID, DWORD * pSize)

Description: This routine returns the amount of installed video memory. The memory size is

determined by reading the status of MD6 and MD7. *pSize will be set to either

80000h (512 KB) or 200000h (2 MB).

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Parameters: DevID

- registered device ID

- pointer to a DWORD to receive the size

pSize

Return Value: ERR_OK - the operation completed successfully

Note

Memory size is only checked when calling seRegisterDevice(), seSetDisplayMode() or

seSetInit(). Afterwards, the memory size is stored and made available through seGet-

MemSize().

int seGetLastUsableByte(int DevID, DWORD * pLastByte)

Description: Calculates the offset of the last byte in the display buffer which can be used by appli-

cations. Locations following LastByte are reserved for system use. Items such as the

half frame buffer, hardware cursor and ink layer will be located in memory from

GetLastUsableByte() + 1 to the end of memory.

It is assumed that the registers will have been initialized before calling seGetLastUs-

ableByte(). Factors such as the half frame buffer and hardware cursor / ink layer

being enabled dynamically alter the amount of display buffer available to an appli-

cation. Call seGetLastUsableByte() any time the true end of usable memory is

required.

Parameters: DevID

- registered device ID

pLastByte - pointer to a DWORD to receive the offset to the last usable byte of

display buffer

Return Value: ERR_OK - operation completed with no problems

int seGetBytesPerScanline(int DevID, UINT * pBytes)

Description: Determines the number of bytes per scan line of the current display mode. It is

assumed that the registers have already been correctly initialized before seGetBytes-

PerScanline() is called.

The number of bytes per scanline calculation includes the value in the offset register.

For rotated modes the return value will be either 1024 (8 bpp) or 2048 (15/16 bpp)

to reflect the 1024 x 1024 virtual area of the rotated memory.

Parameters: DevID

- registered device ID

pBytes

- pointer to an integer which indicates the number of bytes per scan line

Return Value: ERR_OK - operation completed with no problems

ERR_FAILED- returned when this function is called for rotated display modes other

than 8, 15 or 16 bpp.

int seGetScreenSize(int DevID, UINT * Width, UINT * Height)

Description: Gets the width and height in pixels of the display surface. The width and height are

derived by reading the horizontal and vertical size registers and calculating the

dimensions.

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When the display is in portrait mode the dimensions will be swapped. (i.e. a 640x480

display in portrait mode will return a width and height of 480 and 640, respectively).

Parameters: DevID

- registered device ID

Width

Height

- unsigned integer to receive the display width

- unsigned integer to receive the display height

Return value: ERR_OK

- the operation completed successfully

int seSelectBusWidth(int DevID, int Width)

Description: Call this function to select the interface bus width on the ISA evaluation card.

Selectable widths are 8 bit and 16 bit.

Parameters: DevID

- registered device ID

Width

- desired bus width. Must be 8 or 16.

Return Value: ERR_OK - the operation completed successfully

ERR_FAILED- the function was called on a non-ISA platform or width was not set

to 8 or 16.

Note

This call applies to the S1D13505 ISA evaluation cards only.

int seGetHostBusWidth(int DevID, int * Width)

Description: This function retrieves the default (as set by 13505CFG.EXE) value for the host bus

interface width and returns it in Width.

Parameters: DevID

- registered device ID

Width

- integer to hold the returned value of the host bus width

Return Value: ERR_OK - the function completed successfully

int seDisplayEnable(int DevID, BYTE State)

Description: This routine turns the display on or off by enabling or disabling the ENABLE bit of

the display device (PANEL, CRT, or SIMULTANEOUS). The Display Mode

setting (LCD, CRT or SIMULTANEOUS) determines which device(s) will be

affected, the default mode is stored in the HAL_STRUCT.

Parameters: DevID

- registered device ID

State

- set to ON or OFF to respectively enable or disable the display

Return Value: ERR_OK - the function completed successfully

int seDisplayFifo(int DevID, BYTE State)

Description: This routine turns the display on or off by enabling or disabling the display FIFO

(the hardware cursor and ink layer are not affected).

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To quickly blank the display, use seDisplayFifo() instead of seDisplayEnable().

Enabling and disabling the display FIFO is much faster, allowing full CPU

bandwidth to the display buffer.

Parameters: DevID

State

- registered device ID

- set to ON or OFF respectively to enable or disable the display FIFO

Return Value: ERR_OK - the function completed successfully

Note

Disabling the display FIFO will force all display data outputs to zero but horizontal and

vertical sync pulses and panel power supply are still active. As stated earlier, the hard-

ware cursor and ink layer are not affected by disabling the FIFO.

int seDelay(int DevID, DWORD Seconds)

Description: This function will delay for the number of seconds given in Seconds before

returning to the caller.

This function was originally intended for non-PC platforms. Because information on

how to access the timers was not always immediately available, we use the frame

rate for timing calculations. The S1D13505 registers must be initialized for this

function to work correctly.

The PC platform version of seDelay() calls the C timing functions and is therefore

independent of the register settings.

Parameters: DevID

- registered device ID

Seconds

- time to delay in seconds

Return Value: ERR_OK - operation completed with no problems

ERR_FAILED- returned only on non-PC platforms when the S1D13505 registers

have not been initialized.

int seGetLinearDispAddr(int device, DWORD * pDispLogicalAddr)

Description: Determines the logical address of the start of the display buffer. This address may

be used in programs for direct control over the display buffer.

Parameter: device

- registered device ID

pDispLogicalAddr - logical address is returned in this variable.

Return Value: ERR_OK - operation completed with no problems.

11.5.2 Advanced HAL Functions

Advanced HAL functions include the functions to support split and virtual screen opera-

tions and are the same features that were described in the section on advanced programming

techniques.

int seSplitInit(int DevID, DWORD Scrn1Addr, DWORD Scrn2Addr)

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Description: This function prepares the system for split screen operation. In order for split screen

to function the starting address in the display buffer for the upper portion (screen 1),

and the lower portion (screen 2) must be specified. Screen 1 is always displayed

above screen 2 on the display regardless of the location of their respective starting

addresses.

Parameters: DevID

- registered device ID

Scrn1Addr - offset in display buffer, in bytes, to the start of screen 1

Scrn2Addr - offset in display buffer, in bytes, to the start of screen 2

Return Value: ERR_OK - operation completed with no problems

Note

It is assumed that the system has been properly initialized prior to calling seSplitInit().

int seSplitScreen(int DevID, int WhichScreen, long VisibleScanlines)

Description: Changes the relevant registers to adjust the split screen according to the number of

visible lines requested. WhichScreen determines which screen, screen 1 or screen 2,

to change.

The smallest screen 1 can be set to is one line. This is due to the way the register

values are used internally on the S1D13505. Setting the line compare register to zero

results in one line of screen 1 being displayed followed by screen 2.

Parameters: DevID

- registered device ID

WhichScreen- must be set to 1 or 2, or use the constants SCREEN1 or SCREEN2,

to identify which screen to base calculations on

VisibleScanlines- number of lines to show for the selected screen

Return Value: ERR_OK - operation completed with no problems

ERR_HAL_BAD_ARG- argument VisibleScanlines is negative or is greater than

vertical panel size or WhichScreen is not SCREEN1 or SCREEN 2.

Note

seSplitInit() must be called before calling seSplitScreen()

Changing the number of lines for one screen will also change the number of lines in the

other screen (e.g. increasing screen 1 lines by 5 will reduce screen 2 lines by 5).

int seVirtInit(int DevID, DWORD VirtX, DWORD * VirtY)

Description: This function prepares the system for virtual screen operation. The programmer

passes the desired virtual width, in pixels, as VirtX. When the routine returns, VirtY

will contain the maximum number of lines that can be displayed at the requested

virtual width.

Parameter: DevID

- registered device ID

VirtX

- horizontal size of virtual display in pixels.

(Must be greater or equal to physical size of display)

- a return placeholder for the maximum number of lines available

given VirtX

VirtY

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Return Value: ERR_OK - operation completed with no problems

ERR_HAL_BAD_ARG - returned in three situations

1) the virtual width (VirtX) is greater than the largest attainable width

The maximum allowable xVirt is 7FFh * (16 / bpp))

2) the virtual width is less than the physical width, or

3) the maximum number of lines is less than the physical number of

lines

Note

The system must have been properly initialized prior to calling seVirtInit()

int seVirtMove(int DevID, int WhichScreen, DWORD x, DWORD y)

Description: This routine pans and scrolls the display. In the case where split screen operation is

being used the WhichScreen argument specifies which screen to move. The x and y

parameters specify, in pixels, the starting location in the virtual image for the top left

corner of the applicable display.

Parameter: DevID

- registered device ID

WhichScreen- must be set to 1 or 2, or use the constants SCREEN1 or SCREEN2,

to identify which screen to base calculations on

- new starting X position in pixels

- new starting Y position in pixels

Return Value: ERR_OK - operation completed with no problems

ERR_HAL_BAD_ARG- there are several reasons for this return value:

1) WhichScreen is not SCREEN1 or SCREEN2.

2) the y argument is greater than the last available line.

Note

seVirtInit() must be called before calling seVirtMove().

11.5.3 Register / Memory Access

The Register/Memory Access functions provide access to the S1D13505 registers and

display buffer through the HAL.

int seSetReg(int DevID, int Index, BYTE Value)

Description: Writes Value to the register specified by Index.

Parameters: DevID

- registered device ID

Index

Value

- register index to set

- value to write to the register

Return Value: ERR_OK - operation completed with no problems

int seSetWordReg(int DevID, int Index, WORD Value)

Description: Writes WORD sized Value to the register specified by Index.

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Parameters: DevID

- registered device ID

Index

Value

- register index to set

- value to write to the register

Return Value: ERR_OK - operation completed with no problems

int seSetDwordReg(int DevID, int Index, DWORD Value)

Description: Writes DWORD sized Value to the register specified by Index.

Parameters: DevID

- registered device ID

Index

Value

- register index to set

- value to write to the register

Return Value: ERR_OK - operation completed with no problems

int seGetReg(int DevID, int Index, BYTE * pValue)

Description: Reads the value in the register specified by index.

Parameters: DevID

Index

- registered device ID

- register index to read

- return value of the register

pValue

Return Value: ERR_OK - operation completed with no problems

int seGetWordReg(int DevID, int Index, WORD * pValue)

Description: Reads the WORD sized value in the register specified by index.

Parameters: DevID

Index

- registered device ID

- register index to read

- return value of the register

pValue

Return Value: ERR_OK - operation completed with no problems

int seGetDwordReg(int DevID, int Index, DWORD * pValue)

Description: Reads the DWORD sized value in the register specified by index.

Parameters: DevID

Index

- registered device ID

- register index to read

- return value of the register

pValue

Return Value: ERR_OK - operation completed with no problems

int seWriteDisplayBytes(int DevID, DWORD Offset, BYTE Value, DWORD Count)

Description: This routine writes one or more bytes to the display buffer at the offset specified by

Offset. If a count greater than one is specified all bytes will have the same value.

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Parameters: DevID

- registered device ID

Offset

Value

Count

- offset from start of the display buffer

- BYTE value to write

- number of bytes to write

Return Value: ERR_OK - operation completed with no problems

ERR_HAL_BAD_ARG - if the value for Offset is greater than the amount of

installed memory.

Note

If offset + count > memory size, this function will limit the writes to the end of memory.

int seWriteDisplayWords(int DevID, DWORD Offset, WORD Value, DWORD Count)

Description: Writes one or more words to the display buffer.

Parameters: DevID

- registered device ID

Offset

Value

Count

- offset from start of the display buffer

- WORD value to write

- number of words to write

Return Value: ERR_OK - operation completed with no problems

ERR_HAL_BAD_ARG - if the value for Offset is greater than the amount of

installed memory.

Note

If offset + (count*2) > memory size, this function will limit the writes to the end of

memory.

int seWriteDisplayDwords(int DevID, DWORD Offset, DWORD Value, DWORD Count)

Description: Writes one or more dwords to the display buffer.

Parameters: DevID

- registered device ID

Offset

Value

Count

- offset from start of the display buffer

- DWORD value to write

- number of dwords to write

Return Value: ERR_OK - operation completed with no problems

ERR_HAL_BAD_ARG - if the value for Offset is greater than the amount of

installed memory.

Note

If offset + (count*4) > memory size, this function will limit the writes to the end of

memory.

int seReadDisplayByte(int DevID, DWORD Offset, BYTE *pByte)

Description: Reads a byte from the display buffer at the specified offset and returns the value in

pByte.

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Parameters: DevID

- registered device ID

Offset

pByte

- offset, in bytes, from start of the display buffer

- return value of the display buffer location.

Return Value: ERR_OK - operation completed with no problems

ERR_HAL_BAD_ARG - if the value for Offset is greater than the amount of

installed memory.

int seReadDisplayWord(int DevID, DWORD Offset, WORD *pWord)

Description: Reads a word from the display buffer at the specified offset and returns the value in

pWord.

Parameters: DevID

Offset

- registered device ID

- offset, in bytes, from start of the display buffer

- return value of the display buffer location

pWord

Return Value: ERR_OK - operation completed with no problems.

ERR_HAL_BAD_ARG - if the value for Offset is greater than the amount of

installed memory.

int seReadDisplayDword(int DevID, DWORD Offset, DWORD *pDword)

Description: Reads a dword from the display buffer at the specified offset and returns the value

in pDword.

Parameters: DevID

Offset

- registered device ID

- offset from start of the display buffer

- return value of the display buffer location

pDword

Return Value: ERR_OK - operation completed with no problems.

ERR_HAL_BAD_ARG - if the value for Offset is greater than the amount of

installed memory.

11.5.4 Color Manipulation

The functions in the Color Manipulation section deal with altering the color values in the

Look-Up Table directly through the accessor functions and indirectly through the color

depth setting functions.

int seSetLut(int DevID, BYTE *pLut, int Count)

Description: This routine can write one or more LUT entries. The writes always start with Look-

Up Table index 0 and continue for Count entries.

A Look-Up Table entry consists of three bytes, one each for Red, Green, and Blue.

The color information is stored in the four most significant bits of each byte.

Parameters: DevID

- registered device ID

pLut

- pointer to an array of BYTE lut[16][3]

lut[x][0] == RED component

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lut[x][1] == GREEN component

ut[x][2] == BLUE component

Count

- the number of LUT entries to write.

Return Value: ERR_OK - operation completed with no problems

int seGetLut(int DevID, BYTE *pLUT, int Count)

Description: This routine reads one or more LUT entries and puts the result in the byte array

pointed to by pLUT.

A Look-Up Table entry consists of three bytes, one each for Red, Green, and Blue.

The color information is stored in the four most significant bits of each byte.

Parameters: DevID

- registered device ID

pLUT

- pointer to an array of BYTE lut[16][3]

pLUT must point to enough memory to hold Count x 3 bytes of data.

- the number of LUT elements to read.

Count

Return Value: ERR_OK - operation completed with no problems

int seSetLutEntry(int DevID, int Index, BYTE *pEntry)

Description: This routine writes one LUT entry. Unlike seSetLut, the LUT entry indicated by

Index can be any value from 0 to 255.

A Look-Up Table entry consists of three bytes, one each for Red, Green, and Blue.

The color information is stored in the four most significant bits of each byte.

Parameters: DevID

- registered device ID

Index

pEntry

- index to LUT entry (0 to 255)

- pointer to an array of three bytes.

Return Value: ERR_OK - operation completed with no problems

int seGetLutEntry(int DevID, int index, BYTE *pEntry)

Description: This routine reads one LUT entry from any index.

Parameters: DevID

- registered device ID

Index

pEntry

- index to LUT entry (0 to 255)

- pointer to an array of three bytes

Return Value: ERR_OK - operation completed with no problems

int seSetBitsPerPixel(int DevID, UINT BitsPerPixel)

Description: This routine sets the system color depth. Valid arguments for BitsPerPixel is are: 1,

2, 4, 8, 15, and 16.

After performing validity checks for the requested color depth the appropriate

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registers are changed and the Look-Up Table is set its default value.

This call is similar to a mode set call on a standard VGA.

Parameter: DevID

- registered device ID

BitsPerPixel - desired color depth in bits per pixel

Return Value: ERR_OK - operation completed with no problems

ERR_FAILED- possible causes for this error message include:

1) attempted to set other than 8 or 15/16 bpp in portrait mode

(portrait mode only supports 8 and 15/16 bpp)

2) factors such as input clock and memory speed will affect the ability

to set some color depths. If the requested color depth cannot be set this

call will fail

int seGetBitsPerPixel(int DevID, UINT * pBitsPerPixel)

Description: This function reads the S1D13505 registers to determine the current color depth and

returns the result in pBitsPerPixel.

Determines the color depth of current display mode.

Parameters: DevID

- registered device ID

pBitsPerPixel - return value is the current color depth (1/2/4/8/15/16 bpp)

Return Value: ERR_OK - operation completed with no problems

11.5.5 Drawing

The Drawing section covers HAL functions that deal with displaying pixels, lines and

shapes.

int seSetPixel(int DevID, long x, long y, DWORD Color)

Description: Draws a pixel at coordinates (x,y) in the requested color. This routine can be used

for any color depth.

Parameters: DevID

- Registered device ID

- horizontal coordinate of the pixel (starting from 0)

- vertical coordinate of the pixel (starting from 0)

- at 1, 2, 4, and 8 bpp Color is an index into the LUT.

At 15 and 16 bpp Color defines the color directly

(i.e. rrrrrggggggbbbbb for 16 bpp)

Color

Return Value: ERR_OK - operation completed with no problems.

int seGetPixel(int DevID, long x, long y, DWORD *pColor)

Description: Reads the pixel color at coordinates (x,y). This routine can be used for any color

depth.

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Parameters: DevID

- Registered device ID

- horizontal coordinate of the pixel (starting from 0)

- vertical coordinate of the pixel (starting from 0)

- at 1, 2, 4, and 8 bpp pColor points to an index into the LUT.

At 15 and 16 bpp pColor points to the color directly

(i.e. rrrrrggggggbbbbb for 16 bpp)

pColor

Return Value: ERR_OK - operation completed with no problems.

int seDrawLine(int DevID, long x1, long y1, long x2, long y2, DWORD Color)

Description: This routine draws a line on the display from the endpoints defined by (x1,y1) to

(x2,y2) in the requested Color.

seDrawLine() supports horizontal, vertical, and diagonal lines.

Parameters: DevID

(x1, y1)

- registered device ID.

- top left corner of line

(x2, y2)

Color

- bottom right corner of line (see note below)

- color of line

- For 1, 2, 4, and 8 bpp, 'Color' refers to the pixel value which points to

the respective LUT/DAC entry.

- For 15 and 16 bpp, 'Color' refers to the pixel value which stores the

red, green, and blue intensities within a WORD.

Return Value: ERR_OK - operation completed with no problems

ERR_INVALID_REG_DEVICE - device argument is not valid.

int seDrawRect(int DevID, long x1, long y1, long x2, long y2, DWORD Color, BOOL

SolidFill)

Description: This routine draws and optionally fills a rectangular area of display buffer. The

upper right corner of the rectangle is defined by (x1,y1) and the lower right corner

is defined by (x2,y2). The color, defined by Color, applies to the border and to the

optional fill.

Parameters: DevID

(x1, y1)

- registered device ID

- top left corner of the rectangle (in pixels)

(x2, y2)

Color

- bottom right corner of the rectangle (in pixels)

- The color to draw the rectangle outline and solid fill

- At 1, 2, 4, and 8 bpp Color is an index into the Look-Up Table.

- At 15/16 bpp Color defines the color directly

(i.e. rrrrrggggggbbbbb for 16 bpp)

SolidFill

- Flag whether to fill the rectangle or simply draw the border.

- Set to 0 for no fill, set to non-0 to fill the inside of the rectangle

Return Value: ERR_OK - operation completed with no problems.

int seDrawEllipse(int DevID, long xc, long yc, long xr, long yr, DWORD Color, BOOL

SolidFill)

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Description: This routine draws an ellipse with the center located at (xc,yc). The xr and yr param-

eters specify the x any y radii, in pixels, respectively. The ellipse will be drawn in

the color specified in 'Color'.

Parameters: DevID

- registered device ID

(xc, yc)

- The center location of the ellipse (in pixels)

- horizontal radius of the ellipse (in pixels)

- vertical radius of the ellipse (in pixels)

- The color to draw the ellipse

Color

- At 1, 2, 4, and 8 bpp Color is an index into the Look-Up Table.

- At 15/16 bpp Color defines the color directly

(i.e. rrrrrggggggbbbbb for 16 bpp)

- unused

SolidFill

Return Value: ERR_OK - operation completed with no problems.

Note

The 'SolidFill' argument is currently unused and is included for future considerations.

int seDrawCircle(int DevID, long xc, long yc, long Radius, DWORD Color, BOOL

SolidFill)

Description: This routine draws an circle with the center located at (xc,yc) and a radius of Radius.

The circle will be drawn in the color specified in Color.

Parameters: DevID

- registered device ID

xc, yc

Radius

Color

- The center of the circle (in pixels)

- the circles radius (in pixels)

- The color to draw the ellipse

- At 1, 2, 4, and 8 bpp Color is an index into the Look-Up Table.

- At 15/16 bpp Color defines the color directly

(i.e. rrrrrggggggbbbbb for 16 bpp)

- unused

SolidFill

Return Value: ERR_OK - operation completed with no problems.

Note

The SolidFill argument is currently unused and is included for future considerations.

11.5.6 Hardware Cursor

The routines in this section support hardware cursor functionality. Several of the calls look

similar to normal drawing calls (i.e. seDrawCursorLine()); however, these calls remove the

programmer from having to know the particulars of the cursor memory location, layout and

whether portrait mode is enabled. Note that hardware cursor and ink layers utilize some of

the same registers and are mutually exclusive.

int seInitCursor(int DevID)

Description: Prepares the hardware cursor for use. This consists of determining a location in

display buffer for the cursor, setting cursor memory to the transparent color and

enabling the cursor.

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When this call returns the cursor is enabled, the cursor image is transparent and

ready to be drawn.

Parameters: DevID

- a registered device ID

Return Value: ERR_OK - operation completed with no problems

int seCursorOn(int DevID)

Description: This function enables the cursor after it has been disabled through a call to seCur-

sorOff(). After enabling the cursor will have the same shape and position as it did

prior to being disabled. The exception to the size and position occurs if the ink layer

was used while the cursor was disabled.

Parameters: DevID

- a registered device ID

Return Value: ERR_OK - operation completed with no problems

int seCursorOff(int DevID)

Description: This routine disables the cursor. While disabled the cursor is invisible.

Parameters: DevID

- a registered device ID

Return Value: ERR_OK - operation completed with no problems

int seGetCursorStartAddr(int DevID, DWORD * Offset)

Description: This function retrieves the offset to the first byte of hardware cursor memory.

Parameters: DevID

- a registered device ID

Offset

- a DWORD to hold the return value.

Return Value: ERR_OK - the operation completed with no problems.

int seMoveCursor(int DevID, long x, long y)

Description: Moves the upper left corner of the hardware cursor to the pixel position (x,y).

Parameters: DevID

- a registered device ID

(x, y)

- the (x,y) position (in pixels) to move the cursor to

Return Value: ERR_OK - operation completed with no problems

int seSetCursorColor(int DevID, int Index, DWORD Color)

Description: Sets the color of the specified ink/cursor index to 'Color'. The user definable

hardware cursor colors are 16-bit 5-6-5 RGB colors.

The hardware cursor image is always 2 bpp or four colors. Two of the colors are

defined to be transparent and inverse. This leaves two colors which are user

definable.

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Parameters: DevID

- a registered device ID

Index

Color

- the cursor index to set. Valid values are 0 and 1

- a DWORD value which hold the requested color

Return Value: ERR_OK - operation completed with no problems

ERR_FAILED- returned if Index if other than 0 or 1

int seSetCursorPixel(int DevID, long x, long y, DWORD Color)

Description: Draws a single pixel into the hardware cursor. The pixel will be of color 'Color'

located at (x,y) pixels relative to the top left of the hardware cursor.

The value of 'Color' must be 0 to 3. Values 0 and 1 refer to the two user definable

colors. If 'Color' is 2 then the pixel will be transparent and if the value is 3 the pixel

will be an inversion of the underlying screen color.

Parameters: DevID

- a registered device ID

(x, y)

Color

- draw coordinates, in pixels, relative to the top left corner of the cursor

- a value of 0 to 3 to draw the pixel with

Return Value: ERR_OK - operation completed with no problems

int seDrawCursorLine(int DevID, long x1, long y1, long x2, long y2, DWORD Color)

Description: Draws a line between the two endpoints, (x1,y1) and (x2,y2), in the hardware cursor

display buffer using color 'Color'.

The value of 'Color' must be 0 to 3. Values 0 and 1 refer to the two user definable

colors. If 'Color' is 2 then the pixel will be transparent and if the value is 3 the pixel

will be an inversion of the underlying screen color.

Parameters: DevID

(x1,y1)

- a registered device ID

- first line endpoint (in pixels)

- second line endpoint (in pixels)

- a value of 0 to 3 to draw the pixel with

(x2,y2)

Color

Return Value: ERR_OK - operation completed with no problems

int seDrawCursorRect(int DevID, long x1, long y1, long x2, long y2, DWORD Color,

BOOL SolidFill)

Description: This routine will draw a rectangle in hardware cursor memory. The upper left corner

of the rectangle is defined by the point (x1,y1) and the lower right is the point

(x2,y2). Both points are relative to the upper left corner of the cursor.

The value of 'Color' must be 0 to 3. Values 0 and 1 refer to the two user definable

colors. If 'Color' is 2 then the pixel will be transparent and if the value is 3 the pixel

result will be an inversion of the underlying screen color.

If 'SolidFill' is specified the interior of the rectangle will be filled with 'Color',

otherwise the rectangle is only outlined in 'Color'.

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Parameters: DevID

(x1,y1)

- a registered device ID

- upper left corner of the rectangle (in pixels)

- lower right corner of the rectangle (in pixels)

- a 0 to 3 value to draw the rectangle with

- flag for filling the rectangle interior

(x2,y2)

Color

SolidFill

- if equal to 0 then outline the rectangle;

if not equal to 0 then fill the rectangle with Color

Return Value: ERR_OK - operation completed with no problems

int seDrawCursorEllipse(int DevID, long xc, long yc, long xr, long yr, DWORD Color,

BOOL SolidFill)

Description: This routine draws an ellipse within the hardware cursor display buffer. The ellipse

will be centered on the point (xc,yc) and will have a horizontal radius of xr and a

vertical radius of yr.

The value of 'Color' must be 0 to 3. Values 0 and 1 refer to the two user definable

colors. If 'Color' is 2 then the pixel will be transparent and if the value is 3 the pixel

will be an inversion of the underlying screen color.

Currently seDrawCursorEllipse() does not support solid fill of the ellipse.

Parameters: DevID

- a registered device ID

(xc, yc)

- center of the ellipse (in pixels)

- horizontal radius (in pixels)

- vertical radius (in pixels)

Color

SolidFill

- 0 to 3 value to draw the pixels with

- flag to solid fill the ellipse (not currently used)

Return Value: ERR_OK - operation completed with no problems

int seDrawCursorCircle(int DevID, long x, long y, long Radius, DWORD Color, BOOL

SolidFill)

Description: This routine draws a circle in hardware cursor display buffer. The center of the circle

will be at (x,y) and the circle will have a radius of 'Radius' pixels.

The value of 'Color' must be 0 to 3. Values 0 and 1 refer to the two user definable

colors. If 'Color' is 2 then the pixel will be transparent and if the value is 3 the pixel

will be an inversion of the underlying screen color.

Currently seDrawCursorCircle() does not support the solid fill option.

Parameters: DevID

- a registered device ID

(x,y)

Radius

Color

- center of the circle (in pixels)

- radius of the circle (in pixels)

- 0 to 3 value to draw the circle with

- flag to solid fill the circle (currently not used)

SolidFill

Return Value: ERR_OK - operation completed with no problems

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11.5.7 Ink Layer

The functions in this section support the hardware ink layer. Overall these functions are

nearly identical to the hardware cursor routines. In fact the same S1D13505 hardware is

used for both features which means that only the cursor or the ink layer can be active at any

given time.The difference between the hardware cursor and the ink layer is that in cursor

mode the image is a maximum of 64x64 pixels and can be moved around the display while

in ink layer mode the image is as large as the physical size of the display and is in a fixed

position. Both the Ink layer and Hardware cursor have the same number of colors and

handle these colors identically.

int seInitInk(int DevID)

Description: This routine prepares the ink layer for use. This consists of determining the start

address for the ink layer, setting the ink layer to the transparent color and enabling

the ink layer.

When this function returns the ink layer is enabled, transparent and ready to be

drawn on.

Parameters: DevID

- a registered device ID

Return Value: ERR_OK - operation completed with no problems

ERR_FAILED- if the ink layer cannot be enabled due to timing constraints this

value will be returned.

int seInkOn(int DevID)

Description: Enables the ink layer after a call to seInkOff(). If the hardware cursor has not been

used between the time seInkOff() was called and this call then the contents of the ink

layer should be exactly as it was prior to the call to seInkOff().

Parameters: DevID

- a registered device ID

Return Value: ERR_OK - operation completed with no problems

int seInkOff(int DevID)

Description: Disables the ink layer. When disabled the ink layer is not visible.

Parameters: DevID

- a registered device ID

Return Value: ERR_OK - operation completed with no problems

int seGetInkStartAddr(int DevID, DWORD * Offset)

Description: This function retrieves the offset to the first byte of hardware ink layer memory.

Parameters: DevID

- a registered device ID

Offset

- a DWORD to hold the return value.

Return Value: ERR_OK - the operation completed with no problems.

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int seSetInkColor(int DevID, int Index, DWORD Color)

Description: Sets the color of the specified ink/cursor index to 'Color'. The user definable

hardware cursor colors are sixteen bit 5-6-5 RGB colors.

The hardware ink layer image is always 2 bpp or four colors. Two of the colors are

defined to be transparent and inverse. This leaves two colors which are user

definable.

Parameters: DevID

- a registered device ID

Index

Color

- the index, 0 or 1, to write the color to

- a sixteen bit RRRRRGGGGGGBBBBB color to write to 'Index'

Return Value: ERR_OK - operation completed with no problems

ERR_FAILED- an index other than 0 or 1 was specified.

int seSetInkPixel(int DevID, long x, long y, DWORD Color)

Description: Sets one pixel located at (x,y) to the value 'Color'. The point (x,y) is relative to the

upper left corner of the display.

The value of 'Color' must be 0 to 3. Values 0 and 1 refer to the two user definable

colors. If 'Color' is 2 then the pixel will be transparent and if the value is 3 the pixel

will be an inversion of the underlying screen color.

Parameters: DevID

- a registered device ID

(x,y)

Color

- coordinates of the pixel to draw

- a 0 to 3 value to draw the pixel with

Return Value: ERR_OK - operation completed with no problems

int seDrawInkLine(int DevID, long x1, long y1, long x2, long y2, DWORD Color)

Description: This routine draws a line in 'Color' between the endpoints (x1,y1) and (x2,y2).

The value of 'Color' must be 0 to 3. Values 0 and 1 refer to the two user definable

colors. If 'Color' is 2 then the pixel will be transparent and if the value is 3 the pixel

will be an inversion of the underlying screen color.

Parameters: DevID

(x1,y1)

- a registered device ID

- first endpoint of the line (in pixels)

- second endpoint of the line (in pixels)

-a value from 0 to 3 to draw the line with

(x2,y2)

Color

Return Value: ERR_OK - operation completed with no problems

int seDrawInkRect(int DevID, long x1, long y1, long x2, long y2, DWORD Color,

BOOL SolidFill)

Description: Draws a rectangle of color 'Color' and optionally fills it. The upper left corner of the

rectangle is the point (x1,y1) and the lower right corner of the rectangle is the point

(x2,y2).

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The value of 'Color' must be 0 to 3. Values 0 and 1 refer to the two user definable

colors. If 'Color' is 2 then the pixel will be transparent and if the value is 3 the pixel

will be an inversion of the underlying screen color.

Parameters: DevID

- a registered device ID

(x1,y1)

(x2.y2)

Color

- upper left corner of the rectangle (in pixels)

- lower right corner of the rectangle (in pixels)

- a two bit value (0 to 3) to draw the rectangle with

- a flag to indicate that the interior should be filled

SolidFill

Return Value: ERR_OK - operation completed with no problems

int seDrawInkEllipse(int DevID, long xc, long yc, long xr, long yr, DWORD Color,

BOOL SolidFill)

Description: This routine draws an ellipse with the center located at xc,yc. The xr and yr param-

eters specify the x and y radii, in pixels, respectively. The ellipse will be drawn in

the color specified by 'Color'.

The value of 'Color' must be 0 to 3. Values 0 and 1 refer to the two user definable

colors. If 'Color' is 2 then the pixel will be transparent and if the value is 3 the pixel

will be an inversion of the underlying screen color.

This solid fill option is not yet available for this function.

Parameters: DevID

- a registered device ID

xc,yc

Color

SolidFill

- center point for the ellipse (in pixels)

- horizontal radius of the ellipse (in pixels)

- vertical radius of the ellipse (in pixels)

- a two bit value (0 to 3) to draw the rectangle with

- flag to enable filling the interior of the ellipse (currently not used)

Return Value: ERR_OK - operation completed with no problems

int seDrawInkCircle(int DevID, long x, long y, long Radius, DWORD Color, BOOL

SolidFill)

Description: This routine draws a circle in the ink layer display buffer. The center of the circle

will be at x,y and the circle will have a radius of 'Radius' pixels.

The value of 'Color' must be 0 to 3. Values 0 and 1 refer to the two user definable

colors. If 'Color' is 2 then the pixel will be transparent and if the value is 3 the pixel

will be an inversion of the underlying screen color.

Currently seDrawCursorCircle() does not support the solid fill option.

Parameters: DevID

- a registered device ID

x,y

- center of the circle (in pixels)

Radius

Color

SolidFill

- circle radius (in pixels)

- a two bit (0 to 3) value to draw the circle with

- flag to fill the interior of the circle (currently not used)

Return Value: ERR_OK - operation completed with no problems

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11.5.8 Power Save

This section covers the HAL functions dealing with the Power Save features of the

S1D13505.

int seSWSuspend(int DevID, BOOL Suspend)

Description: Causes the S1D13505 to enter software suspend mode.

When software suspend mode is engaged the display is disabled and display buffer

is inaccessible. In this mode the registers and the LUT are accessible.

Parameters: DevID

- a registered device ID

Suspend

- boolean flag to indicate which state to engage.

- enter suspend mode when non-zero and return to normal power

when equal to zero.

Return Value: ERR_OK - operation completed with no problems

int seHWSuspend(int DevID, BOOL Suspend)

Description: Causes the S1D13505 to enter/leave hardware suspend mode. This option in only

supported on S1D13505B0B ISA evaluation boards.

When hardware suspend mode is engaged the display is disabled and display buffer

is inaccessible and the registers and LUT are inaccessible.

Parameters: DevID

- a registered device ID

Suspend

- boolean flag to indicate which state to engage.

- enter suspend mode when non-zero and return to normal power

when equal to zero.

Return Value: ERR_OK - operation completed with no problems

11.6 Porting LIBSE to a new target platform

Building Epson applications like a simple HelloApp for a new target platform requires 3

things, the HelloApp code, the 13505HAL library, and a some standard C functions

(portable ones are encapsulated in our mini C library LIBSE).

HelloApp Source code

HelloApp

C Library Functions (LIBSE for embedded platforms)

13505HAL Library

Figure 11-1: Components needed to build 13505 HAL application

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For example, when building HELLOAPP.EXE for the x86 16-bit platform, you need the

HELLOAPP source files, the 13505HAL library and its include files, and some Standard C

library functions (which in this case would be supplied by the compiler as part of its run-

time library). As this is a DOS .EXE application, you do not need to supply start-up code

that sets up the chip selects or interrupts, etc... What if you wanted to build the application

for an SH-3 target, one not running DOS?

Before you can build that application to load onto the target, you need to build a C library

for the target that contains enough of the Standard C functions (like sprintf and strcpy) to

let you build the application. Epson supplies the LIBSE for this purpose, but your compiler

may come with one included. You also need to build the 13505HAL library for the target.

This library is the graphics chip dependent portion of the code. Finally, you need to build

the final application, linked together with the libraries described earlier. The following

examples assume that you have a copy of the complete source code for the S1D13505

utilities, including the nmake makefiles, as well as a copy of the GNU Compiler v2.7-96q3a

for Hitachi SH3. These are available on the Epson Electronics America Website at

http://www.eea.epson.com.

11.6.1 Building the LIBSE library for SH3 target example

In the LIBSE files, there are three main types of files:

• C files that contain the library functions.

• assembler files that contain the target specific code.

• makefiles that describe the build process to construct the library.

The C files are generic to all platforms, although there are some customizations for targets

in the form of #ifdef LCEVBSH3 code (the ifdef used for the example SH3 target Low Cost

Eval Board SH3). The majority of this code remains constant whichever target you build

for.

The assembler files contain some platform setup code (stacks, chip selects) and jumps into

the main entry point of the C code that is contained in the C file entry.c. For our example,

the assembler file is STARTSH3.S and it performs only some stack setup and a jump into

the code at _mainEntry (entry.c).

In the embedded targets, printf (in file rprintf.c), putchar (putchar.c) and getch (kb.c)

resolve to serial character input/output. For SH3, much of the detail of handling serial IO

is hidden in the monitor of the evaluation board, but in general the primitives are fairly

straight forward, providing the ability to get characters to/from the serial port.

For our target example, the nmake makefile is makesh3.mk. This makefile calls the Gnu

compiler at a specific location (TOOLDIR), enumerates the list of files that go into the

target and builds a .a library file as the output of the build process.

With nmake.exe in your path run:

nmake -fmakesh3.mk

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11.6.2 Building the HAL library for the target example

Building the HAL for the target example is less complex because the code is written in C

and requires little platform specific adjustment. The nmake makefile for our example is

makesh3.mk.This makefile contains the rules for building sh3 objects, the files list for the

library and the library creation rules. The Gnu compiler tools are pointed to by TOOLDIR.

With nmake in your path run:

nmake -fmakesh3.mk

11.6.3 Building a complete application for the target example

The following source code is available on the Epson Electronics America Website at

http://www.eea.epson.com.

#include <stdio.h>

#include "Hal.h"

#include "Appcfg.h"

#include "Hal_regs.h"

int main(void);

#define RED16BPP 0xf800

#define GREEN16BPP 0x07e0

#define BLUE16BPP 0x001f

int main(void)

{

int DevId;

UINT height, width, Bpp;

const char *p1, *p2, *p3;

DWORD color_red, color_blue;

BYTE RedBlueLut[3][3] = {

{0, 0, 0},

/* Black */

/* Red */

{0xF0, 0, 0},

{0, 0, 0xF0}

/* Blue */

};

BOOL verbose = TRUE;

long x1, x2, y1, y2;

** Call this to get hal.c linked into the image, and HalInfoArray

** which is defined in hal.c and used by other HAL pieces.

seGetHalVersion( &p1, &p2, &p3 );

printf("1355 Hal version %s\n", p1);

** Register the device with the HAL

** NOTE: HalInfo is an instance of HAL_STRUCT and is defined

** in Appcfg.h

if (seRegisterDevice(&HalInfo, &DevId) != ERR_OK)

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{

printf("\r\nERROR: Unable to register device with

return -1;

HAL\r\n");

}

** Init the SED1355 with the defaults stored in the HAL_STRUCT

if (seSetInit(DevId) != ERR_OK)

{

printf("\r\nERROR: Unable to initialize the

SED1355\r\n");

return -1;

}

** Determine the screen size

if (seGetScreenSize(DevId, &width, &height) != ERR_OK)

{

printf("\r\nERROR: Unable to get screen size\r\n");

return -1;

}

** Determine the Bpp mode, and set colors appropriately

** Note: if less than 15Bpp set the color Lookup Table (LUT)

** local color variables contain either index into LUT or RGB value

seGetBitsPerPixel(DevId, &Bpp);

if (verbose)

printf("Bpp is %d\n", Bpp);

switch(Bpp)

{

case 1: /* Can't really do red and blue here */

seSetLut(DevId, (BYTE *)&RedBlue-

Lut[0][0], 3);

and Blue */

color_red = 1;

color_blue = 1;

break;

/* Set the LUT to values appropriate to Black, Red,

case 2:

case 4:

case 8:

seSetLut(DevId, (BYTE *)&RedBlue-

Lut[0][0], 3);

color_red = 1;

color_blue = 2;

break;

default: /* 15 or 16 bpp */

color_red = RED16BPP;

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color_blue = BLUE16BPP;

break;

}

** Draw a Blue line from top left hand corner to bottom right hand

corner

if (seDrawLine(DevId, 0,0, width-1, height-1, color_blue) != ERR_OK)

{

printf("\r\nERROR: Unable to draw line\r\n");

return -1;

}

** Delay for 2 seconds and then draw a filled rectangle

seDelay(DevId, (DWORD)2);

** Centre the rectangle at 1/4 x,y and 3/4 x,y

x1 = width/4;

x2 = width/2 + x1;

y1 = height/4;

y2 = height/2 + y1;

seDrawRect(DevId, x1, y1, x2, y2, color_red, TRUE);

** Draw a box around the screen

if ((seDrawLine(DevId, 0, 0, width-1, 0, color_blue) != ERR_OK)

|(seDrawLine(DevId, 0, height-1, width-1, height-1, color_blue) !=

ERR_OK)

|(seDrawLine(DevId, 0, 0, 0, height-1, color_blue) != ERR_OK)

|(seDrawLine(DevId, width-1, 0, width-1, height-1, color_blue) !=

ERR_OK))

{

printf("\r\nERROR: Unable to draw box\r\n");

return -1;

}

** Load a cursor with a blue outlined green rectangle

seInitCursor(DevId);

seCursorOff(DevId);

seSetCursorColor(DevId, 0, GREEN16BPP);

seSetCursorColor(DevId, 1, BLUE16BPP);

seDrawCursorRect(DevId, 0, 0, 63, 63, 1, FALSE);

seDrawCursorRect(DevId, 1, 1, 62, 62, 0, TRUE);

seCursorOn(DevId);

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** Delay for 2 seconds

seDelay(DevId, (DWORD)2);

Move the cursor

seMoveCursor(DevId, width-1-63, 0);

return 0;

}

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12 Sample Code

12.1 Introduction

There are two included examples of programming the S1D13505 color graphics controller.

First is a demonstration using the HAL library and the second without. These code samples

are for example purposes only. Lastly, are three header files that may make some of the

structures used clearer.

12.1.1 Sample code using the S1D13505 HAL API

// Sample code using 1355HAL API

**-------------------------------------------------------------------------

** Created 1998, Epson Research & Development

** Vancouver Design Centre

** The HAL API code is configured for the following:

** 25.175 MHz ClkI

** 640x480 8 bit dual color STN panel @60Hz

** 50 ns EDO, 32 ms (self) refresh time

** Initial color depth - 8 bpp

**-------------------------------------------------------------------------

#include <stdio.h>

#include <stdlib.h>

#include <string.h>

#include "hal.h"

constants and prototypes. */

#include "appcfg.h"

/* Structures,

/* HAL configu-

ration information. */

/*--------------------------------------------------------------------------*/

void main(void)

{

int ChipId;

int Device;

** Initialize the HAL.

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** This step sets up the HAL for use but does not access the 1355.

switch (seRegisterDevice(&HalInfo, &Device))

{

case ERR_OK:

break;

case HAL_DEVICE_ERR:

printf("\nERROR: Too many devices

registered.");

exit(1);

default:

printf("\nERROR: Could not regis-

exit(1);

ter SED1355 device.");

}

** Identify that this is indeed an SED1355.

seGetId( Device, &ChipId);

if (ID_SED1355F0A != ChipId)

{

printf("\nERROR: Did not detect SED1355.");

exit(1);

}

** Initialize the SED1355.

** This step will actually program the registers with values taken

from

** the default register table in appcfg.h.

if (ERR_OK != seSetInit(Device))

{

printf("\nERROR: Could not initialize device.");

exit(1);

}

** The default initialization clears the display.

** Draw a 100x100 red rectangle in the upper left corner (0,0)

** of the display.

seDrawRect(Device, 0, 0, 100, 100, 1, TRUE);

** Init the HW cursor. The HAL performs several calculations to

** determine the best location to place the cursor image and

** will use that location from here on.

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** The background must be set to transparent.

seInitCursor(Device);

seDrawCursorRect(Device, 0, 0, 63, 63, 2, TRUE);

** Set the first user definable color to black and

** the second user definable color to white.

seSetCursorColor(Device, 0, 0);

seSetCursorColor(Device, 1, 0xFFFFFFFF);

** Draw a hollow rectangle around the cursor and move

** the cursor to 101,101.

seDrawCursorRect(Device, 0, 0, 63, 63, 1, FALSE);

seMoveCursor(Device, 101, 101);

exit(0);

}

12.1.2 Sample code without using the S1D13505 HAL API

**===========================================================================

** INIT1355.C - sample code demonstrating the initialization of the SED1355.

Beta release 2.0 98-10-29

** The code in this example will perform initialization to the following

** specification:

** - 640 x 480 dual 16-bit color passive panel.

** - 75 Hz frame rate.

** - 8 BPP (256 colors).

** - 33 MHz input clock.

** - 2 MB of 60 ns EDO memory.

*** This is sample code only! ***

** This means:

** 1) Generic C is used. I assume that pointers can access the

relevant memory addresses (this is not always the case).

i.e. using the 1355B0B card on an x86 16 bit platform will require

changes to use a DOS extender to access memory and registers.

** 2) Register setup is done with discrete writes rather than being

table driven. This allows for clearer commenting. A real program

would probably store the register settings in an array and loop

through the array writing each element to a control register.

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** 3) The pointer assignment for the register offset does not work on

x86 16 bit platforms.

**---------------------------------------------------------------------------

**===========================================================================

** Note that only the upper four bits of the LUT are actually used.

unsigned char LUT8[256*3] =

{

/* Primary and secondary colors */

0x00, 0x00, 0x00, 0x00, 0x00, 0xA0, 0x00, 0xA0, 0x00, 0x00, 0xA0, 0xA0,

0xA0, 0x00, 0x00, 0xA0, 0x00, 0xA0, 0xA0, 0xA0, 0x00, 0xA0, 0xA0, 0xA0,

0x50, 0x50, 0x50, 0x00, 0x00, 0xF0, 0x00, 0xF0, 0x00, 0x00, 0xF0, 0xF0,

0xF0, 0x00, 0x00, 0xF0, 0x00, 0xF0, 0xF0, 0xF0, 0x00, 0xF0, 0xF0, 0xF0,

/* Gray shades */

0x00, 0x00, 0x00, 0x10, 0x10, 0x10, 0x20, 0x20, 0x20, 0x30, 0x30, 0x30,

0x40, 0x40, 0x40, 0x50, 0x50, 0x50, 0x60, 0x60, 0x60, 0x70, 0x70, 0x70,

0x80, 0x80, 0x80, 0x90, 0x90, 0x90, 0xA0, 0xA0, 0xA0, 0xB0, 0xB0, 0xB0,

0xC0, 0xC0, 0xC0, 0xD0, 0xD0, 0xD0, 0xE0, 0xE0, 0xE0, 0xF0, 0xF0, 0xF0,

/* Black to red */

0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x20, 0x00, 0x00, 0x30, 0x00, 0x00,

0x40, 0x00, 0x00, 0x50, 0x00, 0x00, 0x60, 0x00, 0x00, 0x70, 0x00, 0x00,

0x80, 0x00, 0x00, 0x90, 0x00, 0x00, 0xA0, 0x00, 0x00, 0xB0, 0x00, 0x00,

0xC0, 0x00, 0x00, 0xD0, 0x00, 0x00, 0xE0, 0x00, 0x00, 0xF0, 0x00, 0x00,

/* Black to green */

0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x20, 0x00, 0x00, 0x30, 0x00,

0x00, 0x40, 0x00, 0x00, 0x50, 0x00, 0x00, 0x60, 0x00, 0x00, 0x70, 0x00,

0x00, 0x80, 0x00, 0x00, 0x90, 0x00, 0x00, 0xA0, 0x00, 0x00, 0xB0, 0x00,

0x00, 0xC0, 0x00, 0x00, 0xD0, 0x00, 0x00, 0xE0, 0x00, 0x00, 0xF0, 0x00,

/* Black to blue */

0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x20, 0x00, 0x00, 0x30,

0x00, 0x00, 0x40, 0x00, 0x00, 0x50, 0x00, 0x00, 0x60, 0x00, 0x00, 0x70,

0x00, 0x00, 0x80, 0x00, 0x00, 0x90, 0x00, 0x00, 0xA0, 0x00, 0x00, 0xB0,

0x00, 0x00, 0xC0, 0x00, 0x00, 0xD0, 0x00, 0x00, 0xE0, 0x00, 0x00, 0xF0,

/* Blue to cyan (blue and green) */

0x00, 0x00, 0xF0, 0x00, 0x10, 0xF0, 0x00, 0x20, 0xF0, 0x00, 0x30, 0xF0,

0x00, 0x40, 0xF0, 0x00, 0x50, 0xF0, 0x00, 0x60, 0xF0, 0x00, 0x70, 0xF0,

0x00, 0x80, 0xF0, 0x00, 0x90, 0xF0, 0x00, 0xA0, 0xF0, 0x00, 0xB0, 0xF0,

0x00, 0xC0, 0xF0, 0x00, 0xD0, 0xF0, 0x00, 0xE0, 0xF0, 0x00, 0xF0, 0xF0,

/* Cyan (blue and green) to green */

0x00, 0xF0, 0xF0, 0x00, 0xF0, 0xE0, 0x00, 0xF0, 0xD0, 0x00, 0xF0, 0xC0,

0x00, 0xF0, 0xB0, 0x00, 0xF0, 0xA0, 0x00, 0xF0, 0x90, 0x00, 0xF0, 0x80,

0x00, 0xF0, 0x70, 0x00, 0xF0, 0x60, 0x00, 0xF0, 0x50, 0x00, 0xF0, 0x40,

0x00, 0xF0, 0x30, 0x00, 0xF0, 0x20, 0x00, 0xF0, 0x10, 0x00, 0xF0, 0x00,

/* Green to yellow (red and green) */

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0x00, 0xF0, 0x00, 0x10, 0xF0, 0x00, 0x20, 0xF0, 0x00, 0x30, 0xF0, 0x00,

0x40, 0xF0, 0x00, 0x50, 0xF0, 0x00, 0x60, 0xF0, 0x00, 0x70, 0xF0, 0x00,

0x80, 0xF0, 0x00, 0x90, 0xF0, 0x00, 0xA0, 0xF0, 0x00, 0xB0, 0xF0, 0x00,

0xC0, 0xF0, 0x00, 0xD0, 0xF0, 0x00, 0xE0, 0xF0, 0x00, 0xF0, 0xF0, 0x00,

/* Yellow (red and green) to red */

0xF0, 0xF0, 0x00, 0xF0, 0xE0, 0x00, 0xF0, 0xD0, 0x00, 0xF0, 0xC0, 0x00,

0xF0, 0xB0, 0x00, 0xF0, 0xA0, 0x00, 0xF0, 0x90, 0x00, 0xF0, 0x80, 0x00,

0xF0, 0x70, 0x00, 0xF0, 0x60, 0x00, 0xF0, 0x50, 0x00, 0xF0, 0x40, 0x00,

0xF0, 0x30, 0x00, 0xF0, 0x20, 0x00, 0xF0, 0x10, 0x00, 0xF0, 0x00, 0x00,

/* Red to magenta (blue and red) */

0xF0, 0x00, 0x00, 0xF0, 0x00, 0x10, 0xF0, 0x00, 0x20, 0xF0, 0x00, 0x30,

0xF0, 0x00, 0x40, 0xF0, 0x00, 0x50, 0xF0, 0x00, 0x60, 0xF0, 0x00, 0x70,

0xF0, 0x00, 0x80, 0xF0, 0x00, 0x90, 0xF0, 0x00, 0xA0, 0xF0, 0x00, 0xB0,

0xF0, 0x00, 0xC0, 0xF0, 0x00, 0xD0, 0xF0, 0x00, 0xE0, 0xF0, 0x00, 0xF0,

/* Magenta (blue and red) to blue */

0xF0, 0x00, 0xF0, 0xE0, 0x00, 0xF0, 0xD0, 0x00, 0xF0, 0xC0, 0x00, 0xF0,

0xB0, 0x00, 0xF0, 0xA0, 0x00, 0xF0, 0x90, 0x00, 0xF0, 0x80, 0x00, 0xF0,

0x70, 0x00, 0xF0, 0x60, 0x00, 0xF0, 0x50, 0x00, 0xF0, 0x40, 0x00, 0xF0,

0x30, 0x00, 0xF0, 0x20, 0x00, 0xF0, 0x10, 0x00, 0xF0, 0x00, 0x00, 0xF0,

/* Black to magenta (blue and red) */

0x00, 0x00, 0x00, 0x10, 0x00, 0x10, 0x20, 0x00, 0x20, 0x30, 0x00, 0x30,

0x40, 0x00, 0x40, 0x50, 0x00, 0x50, 0x60, 0x00, 0x60, 0x70, 0x00, 0x70,

0x80, 0x00, 0x80, 0x90, 0x00, 0x90, 0xA0, 0x00, 0xA0, 0xB0, 0x00, 0xB0,

0xC0, 0x00, 0xC0, 0xD0, 0x00, 0xD0, 0xE0, 0x00, 0xE0, 0xF0, 0x00, 0xF0,

/* Black to cyan (blue and green) */

0x00, 0x00, 0x00, 0x00, 0x10, 0x10, 0x00, 0x20, 0x20, 0x00, 0x30, 0x30,

0x00, 0x40, 0x40, 0x00, 0x50, 0x50, 0x00, 0x60, 0x60, 0x00, 0x70, 0x70,

0x00, 0x80, 0x80, 0x00, 0x90, 0x90, 0x00, 0xA0, 0xA0, 0x00, 0xB0, 0xB0,

0x00, 0xC0, 0xC0, 0x00, 0xD0, 0xD0, 0x00, 0xE0, 0xE0, 0x00, 0xF0, 0xF0,

/* Red to white */

0xF0, 0x00, 0x00, 0xF0, 0x10, 0x10, 0xF0, 0x20, 0x20, 0xF0, 0x30, 0x30,

0xF0, 0x40, 0x40, 0xF0, 0x50, 0x50, 0xF0, 0x60, 0x60, 0xF0, 0x70, 0x70,

0xF0, 0x80, 0x80, 0xF0, 0x90, 0x90, 0xF0, 0xA0, 0xA0, 0xF0, 0xB0, 0xB0,

0xF0, 0xC0, 0xC0, 0xF0, 0xD0, 0xD0, 0xF0, 0xE0, 0xE0, 0xF0, 0xF0, 0xF0,

/* Green to white */

0x00, 0xF0, 0x00, 0x10, 0xF0, 0x10, 0x20, 0xF0, 0x20, 0x30, 0xF0, 0x30,

0x40, 0xF0, 0x40, 0x50, 0xF0, 0x50, 0x60, 0xF0, 0x60, 0x70, 0xF0, 0x70,

0x80, 0xF0, 0x80, 0x90, 0xF0, 0x90, 0xA0, 0xF0, 0xA0, 0xB0, 0xF0, 0xB0,

0xC0, 0xF0, 0xC0, 0xD0, 0xF0, 0xD0, 0xE0, 0xF0, 0xE0, 0xF0, 0xF0, 0xF0,

/* Blue to white */

0x00, 0x00, 0xF0, 0x10, 0x10, 0xF0, 0x20, 0x20, 0xF0, 0x30, 0x30, 0xF0,

0x40, 0x40, 0xF0, 0x50, 0x50, 0xF0, 0x60, 0x60, 0xF0, 0x70, 0x70, 0xF0,

0x80, 0x80, 0xF0, 0x90, 0x90, 0xF0, 0xA0, 0xA0, 0xF0, 0xB0, 0xB0, 0xF0,

0xC0, 0xC0, 0xF0, 0xD0, 0xD0, 0xF0, 0xE0, 0xE0, 0xF0, 0xF0, 0xF0, 0xF0

};

** REGISTER_OFFSET points to the starting address of the SED1355 registers

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#define REGISTER_OFFSET

((unsigned char *) 0x14000000)

** DISP_MEM_OFFSET points to the starting address of the display buffer memory

#define DISP_MEM_OFFSET ((unsigned char *) 0x4000000)

** DISP_MEMORY_SIZE is the size of display buffer memory

#define DISP_MEMORY_SIZE 0x200000

** Calculate the value to put in Ink/Cursor Start Address Select Register

** Offset = (DISP_MEM_SIZE - (X * 8192)

** We want the offset to be just past the end of display memory so:

** (640 * 480) = DISP_MEMORY_SIZE - (X * 8192)

** CURSOR_START = (DISP_MEMORY_SIZE - (640 * 480)) / 8192

#define CURSOR_START 218

void main(void)

{

unsigned char * pRegs = REGISTER_OFFSET;

unsigned char * pMem;

unsigned char * pLUT;

unsigned char * pTmp;

unsigned char * pCursor;

long lpCnt;

int idx;

int rgb;

long x, y;

** Initialize the chip.

** Step 1: Enable the host interface.

** Register 1B: Miscellaneous Disable - host interface enabled, half frame

buffer enabled.

*(pRegs + 0x1B) = 0x00;

** Step 2: Disable the FIFO

/* 0000 0000 */

/* 1000 0000 */

*(pRegs + 0x23) = 0x80;

** Step 3: Set Memory Configuration

** Register 1: Memory Configuration - 4 ms refresh, EDO

*(pRegs + 0x01) = 0x30;

/* 0011 0000 */

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** Step 4: Set Performance Enhancement 0 register

*(pRegs + 0x22) = 0x24;

/* 0010 0100 */

** Step 5: Set the rest of the registers in order.

** Register 2: Panel Type - 16-bit, format 1, color, dual, passive.

*(pRegs + 0x02) = 0x26;

/* 0010 0110 */

** Register 3: Mod Rate

*(pRegs + 0x03) = 0x00;

/* 0000 0000 */

** Register 4: Horizontal Display Width (HDP) - 640 pixels

(640 / 8) - 1 = 79t = 4Fh

*(pRegs + 0x04) = 0x4f;

/* 0100 1111 */

** Register 5: Horizontal Non-Display Period (HNDP)

PCLK

Frame Rate = -----------------------------

(HDP + HNDP) * (VDP + VNDP)

16,500,000

= -----------------------------

(640 + HNDP) * (480 + VNDP)

** HNDP and VNDP must be calculated such that the desired frame rate

** is achieved.

*(pRegs + 0x05) = 0x1F;

/* 0001 1111 */

** Register 6: HRTC/FPLINE Start Position - applicable to CRT/TFT only.

*(pRegs + 0x06) = 0x00;

/* 0000 0000 */

** Register 7: HRTC/FPLINE Pulse Width - applicable to CRT/TFT only.

*(pRegs + 0x07) = 0x00;

/* 0000 0000 */

** Registers 8-9: Vertical Display Height (VDP) - 480 lines.

480/2 - 1 = 239t = 0xEF

*(pRegs + 0x08) = 0xEF;

*(pRegs + 0x09) = 0x00;

/* 1110 1111 */

/* 0000 0000 */

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** Register A: Vertical Non-Display Period (VNDP)

This register must be programed with register 5 (HNDP)

to arrive at the frame rate closest to the desired

frame rate.

*(pRegs + 0x0A) = 0x01;

/* 0000 0001 */

** Register B: VRTC/FPFRAME Start Position - applicable to CRT/TFT only.

*(pRegs + 0x0B) = 0x00;

/* 0000 0000 */

** Register C: VRTC/FPFRAME Pulse Width - applicable to CRT/TFT only.

*(pRegs + 0x0C) = 0x00;

/* 0000 0000 */

** Register D: Display Mode - 8 BPP, LCD disabled.

*(pRegs + 0x0D) = 0x0C;

/* 0000 1100 */

** Registers E-F: Screen 1 Line Compare - unless setting up for

split screen operation use 0x3FF.

*(pRegs + 0x0E) = 0xFF;

*(pRegs + 0x0F) = 0x03;

/* 1111 1111 */

/* 0000 0011 */

** Registers 10-12: Screen 1 Display Start Address - start at the

first byte in display memory.

*(pRegs + 0x10) = 0x00;

*(pRegs + 0x11) = 0x00;

*(pRegs + 0x12) = 0x00;

/* 0000 0000 */

** Register 13-15: Screen 2 Display Start Address - not applicable

unless setting up for split screen operation.

*(pRegs + 0x13) = 0x00;

*(pRegs + 0x14) = 0x00;

*(pRegs + 0x15) = 0x00;

/* 0000 0000 */

** Register 16-17: Memory Address Offset - this address represents the

starting WORD. At 8BPP our 640 pixel width is 320

WORDS

*(pRegs + 0x16) = 0x40;

*(pRegs + 0x17) = 0x01;

/* 0100 0000 */

/* 0000 0001 */

** Register 18: Pixel Panning

*(pRegs + 0x18) = 0x00;

/* 0000 0000 */

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** Register 19: Clock Configuration - In this case we must divide

PCLK by 2 to arrive at the best frequency to set

our desired panel frame rate.

*(pRegs + 0x19) = 0x01;

/* 0000 0001 */

** Register 1A: Power Save Configuration - enable LCD power, CBR refresh,

not suspended.

*(pRegs + 0x1A) = 0x00;

/* 0000 0000 */

** Register 1C-1D: MD Configuration Readback - these registers are

read only, but it's OK to write a 0 to keep

the register configuration logic simpler.

*(pRegs + 0x1C) = 0x00;

*(pRegs + 0x1D) = 0x00;

/* 0000 0000 */

** Register 1E-1F: General I/O Pins Configuration

*(pRegs + 0x1E) = 0x00;

*(pRegs + 0x1F) = 0x00;

/* 0000 0000 */

** Register 20-21: General I/O Pins Control

*(pRegs + 0x20) = 0x00;

*(pRegs + 0x21) = 0x00;

/* 0000 0000 */

** Registers 24-26: LUT control.

For this example do a typical 8 BPP LUT setup.

** Setup the pointer to the LUT data and reset the LUT index register.

** Then, loop writing each of the RGB LUT data elements.

pLUT = LUT8;

*(pRegs + 0x24) = 0;

for (idx = 0; idx < 256; idx++)

{

for (rgb = 0; rgb < 3; rgb++)

{

*(pRegs + 0x26) = *pLUT;

pLUT++;

}

** Register 27: Ink/Cursor Control - disable ink/cursor

*(pRegs + 0x27) = 0x00;

/* 0000 0000 */

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** Registers 28-29: Cursor X Position

*(pRegs + 0x28) = 0x00;

*(pRegs + 0x29) = 0x00;

/* 0000 0000 */

** Registers 2A-2B: Cursor Y Position

*(pRegs + 0x2A) = 0x00;

*(pRegs + 0x2B) = 0x00;

/* 0000 0000 */

** Registers 2C-2D: Ink/Cursor Color 0 - blue

*(pRegs + 0x2C) = 0x1F;

*(pRegs + 0x2D) = 0x00;

/* 0001 1111 */

/* 0000 0000 */

** Registers 2E-2F: Ink/Cursor Color 1 - green

*(pRegs + 0x2E) = 0xE0;

*(pRegs + 0x2F) = 0x07;

/* 1110 0000 */

/* 0000 0111 */

** Register 30: Ink/Cursor Start Address Select

*(pRegs + 0x30) = 0x00;

/* 0000 0000 */

** Register 31: Alternate FRM Register

*(pRegs + 0x31) = 0x00;

** Register 23: Performance Enhancement - display FIFO enabled, optimum

performance. The FIFO threshold is set to 0x00; for

15/16 bpp modes, set the FIFO threshold

to a higher value, such as 0x1B.

*(pRegs + 0x23) = 0x00;

/* 0000 0000 */

** Register D: Display Mode - 8 BPP, LCD enable.

*(pRegs + 0x0D) = 0x0D;

/* 0000 1101 */

** Clear memory by filling 2 MB with 0

pMem = DISP_MEM_OFFSET;

for (lpCnt = 0; lpCnt < DISP_MEMORY_SIZE; lpCnt++)

{

*pMem = 0;

pMem++;

}

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** Draw a 100x100 red rectangle in the upper left corner (0, 0)

** of the display.

pMem = DISP_MEM_OFFSET;

for (y = 0; y < 100; y++)

{

pTmp = pMem + y * 640L;

for (x = 0; x < 100; x++)

{

*pTmp = 0x0c;

pTmp++;

}

** Init the HW cursor. In this example the cursor memory will be located

** immediately after display memory. Why here? Because it's an easy

** location to calculate and will not interfere with the half frame buffer.

** Additionally, the HW cursor can be turned into an ink layer quite

** easily from this location.

*(pRegs + 0x30) = CURSOR_START;

pTmp = pCursor = pMem + (DISP_MEMORY_SIZE - (CURSOR_START * 8192L));

** Set the contents of the cursor memory such that the cursor

** is transparent. To do so, write a 10101010b pattern in each byte.

** The cursor is 2 bpp so a 64x64 cursor requires

** 64/4 * 64 = 1024 bytes of memory.

for (lpCnt = 0; lpCnt < 1024; lpCnt++)

{

*pTmp = 0xAA;

pTmp++;

}

** Set the first user definable cursor color to black and

** the second user definable cursor color to white.

*(pRegs + 0x2C) = 0;

*(pRegs + 0x2D) = 0;

*(pRegs + 0x2E) = 0xFF;

*(pRegs + 0x2F) = 0xFF;

** Draw a hollow rectangle around the cursor.

pTmp = pCursor;

for (lpCnt = 0; lpCnt < 16; lpCnt++)

{

*pTmp = 0x55;

pTmp++;

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}

for (lpCnt = 0; lpCnt < 14; lpCnt++)

{

*pTmp = 0x6A;

pTmp += 15;

*pTmp = 0xA9;

pTmp++;

}

for (lpCnt = 0; lpCnt < 16; lpCnt++)

{

*pTmp = 0x55;

pTmp++;

}

** Move the cursor to 100, 100.

** First we wait for the next vertical non-display

** period before updating the position registers.

while (*(pRegs + 0x0A) & 0x80);

/* wait while in VNDP */

while (!(*(pRegs + 0x0A) & 0x80)); /* wait while in VDP */

** Now update the position registers.

*(pRegs + 0x28) = 100; /* Set Cursor X = 100 */

*(pRegs + 0x29) = 0x00;

*(pRegs + 0x2A) = 100; /* Set Cursor Y = 100 */

*(pRegs + 0x2B) = 0x00;

** Enable the hardware cursor.

*(pRegs + 0x27) = 0x40;

}

12.1.3 Header Files

The following header files are included as they help to explain some of the structures used

when programming the S1D13505.

The following header file defines the structure used to store the configuration information

contained in all utilities using the S1D13505 HAL API.

/********************************************************************************/

/* 1355 HAL INF

/* HAL_STRUCT Information generated by 1355CFG.EXE

(do not remove)

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/* Include this file ONCE in your primary source file

/********************************************************************************/

HAL_STRUCT HalInfo =

{

"1355 HAL EXE",

0x1234,

/* ID string */

/* Detect Endian */

sizeof(HAL_STRUCT), /* Size

/* Default Mode */

{

/* LCD */

0x00, 0x50, 0x16, 0x00, 0x4F, 0x03, 0x00, 0x00,

0xEF, 0x00, 0x34, 0x00, 0x00, 0x0D, 0xFF, 0x03,

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x01,

0x00, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00,

0x00, 0x00, 0x48, 0x00, 0x00, 0x00, 0x00, 0x00,

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,

0x00, 0x00

{

/* CRT */

0x00, 0x50, 0x16, 0x00, 0x4F, 0x13, 0x01, 0x0B,

0xDF, 0x01, 0x2B, 0x09, 0x01, 0x0E, 0xFF, 0x03,

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x01,

0x00, 0x00, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00,

0x00, 0x00, 0x48, 0x00, 0x00, 0x00, 0x00, 0x00,

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,

0x00, 0x00

{

/* SIMUL */

0xFF, 0x50, 0x16, 0x00, 0x4F, 0x13, 0x01, 0x0B,

0xDF, 0x01, 0x2B, 0x09, 0x01, 0x0F, 0xFF, 0x03,

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x01,

0x00, 0x01, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00,

0x00, 0x00, 0x48, 0x00, 0x00, 0x00, 0x00, 0x00,

0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,

0x00, 0x00

25175,

8000,

/* ClkI (kHz)

/* BusClk (kHz)

0xE00000,

0xC00000,

60,

/* Register Address */

/* Display Address */

/* Panel Frame Rate (Hz) */

/* CRT Frame Rate (Hz) */

60,

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50,

84,

30,

50,

/* Memory speed in ns */

/* Ras to Cas Delay in ns */

/* Ras Access Charge time in ns */

/* RAS Access Charge time in ns */

/* Host CPU bus width in bits */

};

The following header file defines the S1D13505 HAL registers.

/*===========================================================================

** HAL_REGS.H

** Created 1998, Epson Research & Development

Vancouver Design Center.

** Copyright(c) Epson Research and Development Inc. 1997, 1998. All rights

reserved.

=============================================================================*/

#ifndef __HAL_REGS_H__

#define __HAL_REGS_H__

** 1355 register names

#define REG_REVISION_CODE

#define REG_MEMORY_CONFIG

#define REG_PANEL_TYPE

#define REG_MOD_RATE

0x00

0x01

0x02

0x03

0x04

0x05

0x06

0x07

0x08

0x09

0x0A

0x0B

0x0C

0x0D

0x0E

0x0F

0x10

0x11

0x12

0x13

0x14

0x15

0x16

0x17

0x18

#define REG_HORZ_DISP_WIDTH

#define REG_HORZ_NONDISP_PERIOD

#define REG_HRTC_START_POSITION

#define REG_HRTC_PULSE_WIDTH

#define REG_VERT_DISP_HEIGHT0

#define REG_VERT_DISP_HEIGHT1

#define REG_VERT_NONDISP_PERIOD

#define REG_VRTC_START_POSITION

#define REG_VRTC_PULSE_WIDTH

#define REG_DISPLAY_MODE

#define REG_SCRN1_LINE_COMPARE0

#define REG_SCRN1_LINE_COMPARE1

#define REG_SCRN1_DISP_START_ADDR0

#define REG_SCRN1_DISP_START_ADDR1

#define REG_SCRN1_DISP_START_ADDR2

#define REG_SCRN2_DISP_START_ADDR0

#define REG_SCRN2_DISP_START_ADDR1

#define REG_SCRN2_DISP_START_ADDR2

#define REG_MEM_ADDR_OFFSET0

#define REG_MEM_ADDR_OFFSET1

#define REG_PIXEL_PANNING

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#define REG_CLOCK_CONFIG

#define REG_POWER_SAVE_CONFIG

#define REG_MISC

#define REG_MD_CONFIG_READBACK0

#define REG_MD_CONFIG_READBACK1

#define REG_GPIO_CONFIG0

0x19

0x1A

0x1B

0x1C

0x1D

0x1E

0x1F

0x20

0x21

0x22

0x23

0x24

0x25

0x26

0x27

0x28

0x29

0x2A

0x2B

0x2C

0x2D

0x2E

0x2F

0x30

0x31

#define REG_GPIO_CONFIG1

#define REG_GPIO_CONTROL0

#define REG_GPIO_CONTROL1

#define REG_PERF_ENHANCEMENT0

#define REG_PERF_ENHANCEMENT1

#define REG_LUT_ADDR

#define REG_RESERVED_1

#define REG_LUT_DATA

#define REG_INK_CURSOR_CONTROL

#define REG_CURSOR_X_POSITION0

#define REG_CURSOR_X_POSITION1

#define REG_CURSOR_Y_POSITION0

#define REG_CURSOR_Y_POSITION1

#define REG_INK_CURSOR_COLOR0_0

#define REG_INK_CURSOR_COLOR0_1

#define REG_INK_CURSOR_COLOR1_0

#define REG_INK_CURSOR_COLOR1_1

#define REG_INK_CURSOR_START_ADDR

#define REG_ALTERNATE_FRM

** WARNING!!! MAX_REG must be the last available register!!!

#define MAX_REG

0x31

#endif /* __HAL_REGS_H__ */

The following header file defines the structures used in the S1D13505 HAL API.

**===========================================================================

** HAL.H

**---------------------------------------------------------------------------

** Created 1998, Epson Research & Development

Vancouver Design Center.

** Copyright(c) Epson Research and Development Inc. 1997, 1998. All rights

reserved.

**===========================================================================

#ifndef _HAL_H_

#define _HAL_H_

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#pragma warning(disable:4001) // Disable the 'single line comment' warning.

#include "hal_regs.h"

/*-------------------------------------------------------------------------*/

typedef unsigned char BYTE;

typedef unsigned short WORD;

typedef unsigned long DWORD;

typedef unsigned int UINT;

typedef

int BOOL;

#ifdef INTEL

typedef BYTE far *LPBYTE;

typedef WORD far *LPWORD;

typedef DWORD far *LPDWORD;

#else

typedef BYTE

typedef WORD

typedef DWORD

#endif

*LPBYTE;

*LPWORD;

*LPDWORD;

#ifndef LOBYTE

#define LOBYTE(w)

#endif

((BYTE)(w))

#ifndef HIBYTE

#define HIBYTE(w)

#endif

((BYTE)(((UINT)(w) >> 8) & 0xFF))

((WORD)(DWORD)(l))

#ifndef LOWORD

#define LOWORD(l)

#endif

#ifndef HIWORD

#define HIWORD(l)

#endif

((WORD)((((DWORD)(l)) >> 16) & 0xFFFF))

#ifndef MAKEWORD

#define MAKEWORD(lo, hi) ((WORD)(((WORD)(lo)) | (((WORD)(hi)) << 8)) )

#endif

#ifndef MAKELONG

#define MAKELONG(lo, hi) ((long)(((WORD)(lo)) | (((DWORD)((WORD)(hi))) << 16)))

#endif

#ifndef TRUE

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#define TRUE 1

#endif

#ifndef FALSE

#define FALSE 0

#endif

#define OFF 0

#define ON 1

#ifndef NULL

#ifdef __cplusplus

#define NULL

#else

#define NULL

#endif

((void *)0)

#endif

/*-------------------------------------------------------------------------*/

** SIZE_VERSION is the size of the version string (eg. "1.00")

** SIZE_STATUS is the size of the status string (eg. "b" for beta)

** SIZE_REVISION is the size of the status revision string (eg. "00")

#define SIZE_VERSION

#define SIZE_STATUS

#define SIZE_REVISION

#ifdef ENABLE_DPF

/* Debug_printf() */

#define DPF(exp) printf(#exp "\n")

#define DPF1(exp) printf(#exp " = %d\n", exp)

#define DPF2(exp1, exp2) printf(#exp1 "=%d " #exp2 "=%d\n", exp1, exp2)

#define DPFL(exp) printf(#exp " = %x\n", exp)

#else

#define DPF(exp) ((void)0)

#define DPF1(exp) ((void)0)

#define DPFL(exp) ((void)0)

#endif

/*-------------------------------------------------------------------------*/

enum

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{

ERR_OK = 0,

ERR_FAILED,

/* No error, call was successful. */

/* General purpose failure. */

ERR_UNKNOWN_DEVICE,

ERR_INVALID_PARAMETER,

ERR_HAL_BAD_ARG,

/* */

/* Function was called with invalid parameter. */

ERR_TOOMANY_DEVS,

ERR_INVALID_STD_DEVICE

};

/*******************************************

* Definitions for seGetId()

*******************************************/

enum

{

ID_UNKNOWN,

ID_SED1355,

ID_SED1355F0A

};

#define MAX_DEVICE

** SE_RESERVED is for reserved device

#define SE_RESERVED

** DetectEndian is used to determine whether the most significant

** and least significant bytes are reversed by the given compiler.

#define ENDIAN

0x1234

#define REV_ENDIAN 0x3412

/*******************************************

* Definitions for Internal calculations.

*******************************************/

#define MIN_NON_DISP_X

#define MAX_NON_DISP_X

256

#define MIN_NON_DISP_Y

#define MAX_NON_DISP_Y

/*******************************************

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* Definitions for seSetFont

*******************************************/

enum

{

HAL_STDOUT,

HAL_STDIN,

HAL_DEVICE_ERR

};

#define FONT_NORMAL

#define FONT_DOUBLE_WIDTH

0x00

0x01

#define FONT_DOUBLE_HEIGHT 0x02

enum

{

RED,

GREEN,

BLUE

};

/*******************************************

* Definitions for seSplitScreen()

*******************************************/

enum

{

SCREEN1 = 1,

SCREEN2

};

/*******************************************

* Definitions for sePowerSaveMode()

*******************************************/

#define PWR_CBR_REFRESH 0x00

#define PWR_SELF_REFRESH 0x01

#define PWR_NO_REFRESH

0x02

/*************************************************************************/

enum

{

DISP_MODE_LCD = 0,

DISP_MODE_CRT,

DISP_MODE_SIMULTANEOUS,

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MAX_DISP_MODE

};

typedef struct tagHalStruct

{

char szIdString[16];

WORD wDetectEndian;

WORD wSize;

WORD wDefaultMode;

BYTE Regs[MAX_DISP_MODE][MAX_REG + 1];

DWORD dwClkI;

/* Input Clock Frequency (in kHz) */

DWORD dwBusClk;

DWORD dwRegAddr;

DWORD dwDispMem;

/* Bus Clock Frequency (in kHz) */

/* Starting address of registers */

/* Starting address of display buffer memory */

WORD wPanelFrameRate; /* Desired panel frame rate */

WORD wCrtFrameRate;

WORD wMemSpeed;

WORD wTrc;

WORD wTrp;

WORD wTrac;

/* Desired CRT rate */

/* Memory speed in ns */

/* Ras to Cas Delay in ns */

/* Ras Precharge time in ns */

/* Ras Access Charge time in ns */

/* Host CPU bus width in bits */

WORD wHostBusWidth;

} HAL_STRUCT;

typedef HAL_STRUCT * PHAL_STRUCT;

#ifdef INTEL

typedef HAL_STRUCT far * LPHAL_STRUCT;

#else

typedef HAL_STRUCT

#endif

* LPHAL_STRUCT;

/*=========================================================================*/

/* FUNCTION PROTO-TYPES */

/*=========================================================================*/

/*---------------------------- HAL Support --------------------------------*/

int seInitHal( void );

int seGetDetectedBusWidth(int *bits);

int seRegisterDevice( const LPHAL_STRUCT lpHalInfo, int *Device );

int seGetMemSize( int seReserved1, DWORD *val );

#define CLEAR_MEM

TRUE

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#define DONT_CLEAR_MEM FALSE

int seSetDisplayMode(int device, int DisplayMode, int ClearMem);

int seSetInit(int device);

int seGetId( int seReserved1, int *pId );

void seGetHalVersion( const char **pVersion, const char **pStatus, const char **pSta-

tusRevision );

/*---------------------------- Chip Access --------------------------------*/

int seGetReg( int seReserved1, int index, BYTE *pValue );

int seSetReg( int seReserved1, int index, BYTE value );

/*------------------------------- Misc ------------------------------------*/

int seSetBitsPerPixel( int seReserved1, UINT nBitsPerPixel );

int seGetBitsPerPixel( int seReserved1, UINT *pBitsPerPixel );

int seGetBytesPerScanline( int seReserved1, UINT *pBytes );

int seGetScreenSize( int seReserved1, UINT *width, UINT *height );

int seHWSuspend(int seReserved1, BOOL val);

int seSelectBusWidth(int seReserved1, int width);

int seDelay( int seReserved1, DWORD Seconds );

int seGetLastUsableByte( int seReserved1, DWORD *LastByte );

int seDisplayEnable(int seReserved1, BYTE NewState);

int seSplitInit( int seReserved1, DWORD wScrn1Addr, DWORD wScrn2Addr );

int seSplitScreen( int nReserved1, int WhichScreen, long VisibleScanlines );

int seVirtInit( int seReserved1, DWORD xVirt, DWORD *yVirt );

int seVirtMove( int seReserved1, int nWhichScreen, DWORD x, DWORD y );

/*-------------------------- Power Save -----------------------------------*/

int seSetPowerSaveMode( int seReserved1, int PowerSaveMode );

/*------------------------- Memory Access ---------------------------------*/

int seReadDisplayByte( int seReserved1, DWORD offset, BYTE *pByte );

int seReadDisplayWord( int seReserved1, DWORD offset, WORD *pWord );

int seReadDisplayDword( int seReserved1, DWORD offset, DWORD *pDword );

int seWriteDisplayBytes( int seReserved1, DWORD addr, BYTE val, DWORD count );

int seWriteDisplayWords( int seReserved1, DWORD addr, WORD val, DWORD count );

int seWriteDisplayDwords( int seReserved1, DWORD addr, DWORD val, DWORD count );

/*------------------------------- Drawing ---------------------------------*/

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int seGetInkStartAddr(int seReserved1, DWORD *addr);

int seGetPixel( int seReserved1, long x, long y, DWORD *pVal );

int seSetPixel( int seReserved1, long x, long y, DWORD color );

int seDrawLine( int seReserved1, long x1, long y1, long x2, long y2, DWORD color );

int seDrawRect( int seReserved1, long x1, long y1, long x2, long y2, DWORD color,

BOOL SolidFill );

int seDrawEllipse(int seReserved1, long xc, long yc, long xr, long yr, DWORD color,

BOOL SolidFill);

int seDrawCircle( int seReserved1, long xCenter, long yCenter, long radius, DWORD

color, BOOL SolidFill );

/*------------------------------- Hardware Cursor ------------------------------*/

int seInitCursor(int seReserved1);

int seCursorOff(int seReserved1);

int seGetCursorStartAddr(int seReserved1, DWORD *addr);

int seMoveCursor(int seReserved1, long x, long y);

int seSetCursorColor(int seReserved1, int index, DWORD color);

int seSetCursorPixel( int seReserved1, long x, long y, DWORD color );

int seDrawCursorLine( int seReserved1, long x1, long y1, long x2, long y2, DWORD

color );

int seDrawCursorRect( int seReserved1, long x1, long y1, long x2, long y2, DWORD

color, BOOL SolidFill );

int seDrawCursorEllipse(int seReserved1, long xc, long yc, long xr, long yr, DWORD

color, BOOL SolidFill);

int seDrawCursorCircle( int seReserved1, long xCenter, long yCenter, long radius,

DWORD color, BOOL SolidFill );

/*------------------------------- Hardware Ink Layer ---------------------------*/

int seInitInk(int seReserved1);

int seInkOff(int seReserved1);

int seGetInkStartAddr(int seReserved1, DWORD *addr);

int seSetInkColor(int seReserved1, int index, DWORD color);

int seSetInkPixel( int seReserved1, long x, long y, DWORD color );

int seDrawInkLine( int seReserved1, long x1, long y1, long x2, long y2, DWORD color

);

int seDrawInkRect( int seReserved1, long x1, long y1, long x2, long y2, DWORD color,

BOOL SolidFill );

int seDrawInkEllipse(int seReserved1, long xc, long yc, long xr, long yr, DWORD

color, BOOL SolidFill);

int seDrawInkCircle( int seReserved1, long xCenter, long yCenter, long radius, DWORD

color, BOOL SolidFill );

/*------------------------------ Color ------------------------------------*/

int seSetLut( int seReserved1, BYTE *pLut, int count );

int seGetLut( int seReserved1, BYTE *pLut, int count );

Programming Notes and Examples

Issue Date: 01/02/05

S1D13505

X23A-G-003-07

Page 106

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int seSetLutEntry( int seReserved1, int index, BYTE *pEntry );

int seGetLutEntry( int seReserved1, int index, BYTE *pEntry );

/*--------------------------- C Like Support ------------------------------*/

int seDrawText( int seReserved1, char *fmt, ... );

int sePutChar( int seReserved1, int ch );

int seGetChar( void );

/*--------------------------- XLIB Support --------------------------------*/

int seGetLinearDispAddr(int seReserved1, DWORD *pDispLogicalAddr);

int InitLinear(int seReserved1);

#endif

/* _HAL_H_ */

S1D13505

X23A-G-003-07

Programming Notes and Examples

Issue Date: 01/02/05

Epson Research and Development

Page 107

Vancouver Design Center

Appendix A Supported Panel Values

A.1 Supported Panel Values

The following tables show related register data for different panels. All the examples are

based on 8 bpp and 2M bytes of 50 ns EDO-DRAM.

Note

The following settings may not reflect the ideal settings for your system configuration.

Power, speed, and cost requirements may dictate different starting parameters for your

system (e.g. 320x240@78Hz using 12MHz clock).

Table 12-1: Passive Single Panel @ 320x240 with 40MHz Pixel Clock

Mono 4-Bit

Color 8-Bit

Format 2

Mono 4-Bit

320X240@60Hz

Color 8-Bit

320X240@60Hz

Notes

320X240@60Hz

1000 0000

0000 0000

0010 0111

0001 0111

1110 1111

0000 0000

0011 1110

0000 1101

0000 0011

0000 0001

0000 0000

load LUT

320X240@60Hz

0001 1100

0000 0000

0010 0111

0001 0111

1110 1111

0000 0000

0011 1110

0000 1101

0000 0011

0000 0001

0000 0000

load LUT

REG[02h] 0000 0000

REG[03h] 0000 0000

REG[04h] 0010 0111

REG[05h] 0001 0111

REG[08h] 1110 1111

REG[09h] 0000 0000

REG[0Ah] 0011 1110

REG[0Dh] 0000 1101

REG[19h] 0000 0011

REG[1Bh] 0000 0001

REG[24h] 0000 0000

0001 0100

0000 0000

0010 0111

0001 0111

1110 1111

0000 0000

0011 1110

0000 1101

0000 0011

0000 0001

0000 0000

load LUT

set panel type

set MOD rate

set horizontal display width

set horizontal non-display period

set vertical display height bits 7-0

set vertical display height bits 9-8

set vertical non-display period

set 8 bpp and LCD enable

set MCLK and PCLK divide

disable half frame buffer

set Look-Up Table address to 0

load Look-Up Table

REG[26h]

load LUT

Table 12-2: Passive Single Panel @ 640x480 with 40MHz Pixel Clock

Mono 8-Bit

640X480@60Hz 640X480@60Hz

Color 8-Bit

Color 16-Bit

640X480@60Hz

Notes

REG[02h] 0001 0000

REG[03h] 0000 0000

REG[04h] 0100 1111

REG[05h] 0000 0011

REG[08h] 1101 1111

REG[09h] 0000 0001

REG[0Ah] 0000 0010

REG[0Dh] 0000 1101

REG[19h] 0000 0001

REG[1Bh] 0000 0001

REG[24h] 0000 0000

0001 0100

0000 0000

0100 1111

0000 0011

1101 1111

0000 0001

0000 0010

0000 1101

0000 0001

0000 0000

load LUT

0010 0100

0000 0000

0100 1111

0000 0011

1101 1111

0000 0001

0000 0010

0000 1101

0000 0001

0000 0000

load LUT

set panel type

set MOD rate

set horizontal display width

set horizontal non-display period

set vertical display height bits 7-0

set vertical display height bits 9-8

set vertical non-display period

set 8 bpp and LCD enable

set MCLK and PCLK divide

disable half frame buffer

set Look-Up Table address to 0

load Look-Up Table

REG[26h]

load LUT

Programming Notes and Examples

Issue Date: 01/02/05

S1D13505

X23A-G-003-07

Page 108

Epson Research and Development

Vancouver Design Center

Table 12-3: Passive Dual Panel @ 640x480 with 40MHz Pixel Clock

Mono 4-Bit EL Mono 8-Bit

Color 8-Bit

640X480@60Hz 640X480@60Hz

Color 16-Bit

Notes

640X480@60Hz

1000 0010

0000 0000

0100 1111

0000 0101

1110 1111

0000 0000

0011 1110

0000 1101

0000 0010

0000 0000

load LUT

640X480@60Hz

0001 0010

0000 0000

0100 1111

0000 0101

1110 1111

0000 0000

0011 1110

0000 1101

0000 0010

0000 0000

load LUT

REG[02h]

REG[03h]

REG[04h]

REG[05h]

REG[08h]

REG[09h]

REG[0Ah]

REG[0Dh]

REG[19h]

REG[1Bh]

REG[24h]

REG[26h]

0001 0110

0000 0000

0100 1111

0000 0101

1110 1111

0000 0000

0011 1110

0000 1101

0000 0010

0000 0000

load LUT

0010 0110

0000 0000

0100 1111

0000 0101

1110 1111

0000 0000

0011 1110

0000 1101

0000 0010

0000 0000

load LUT

set panel type

set MOD rate

set horizontal display width

set horizontal non-display period

set vertical display height bits 7-0

set vertical display height bits 9-8

set vertical non-display period

set 8 bpp and LCD enable

set MCLK and PCLK divide

enable half frame buffer

set Look-Up Table address to 0

load Look-Up Table

Table 12-4: TFT Single Panel @ 640x480 with 25.175 MHz Pixel Clock

Color 16-Bit

Notes

640X480@60Hz

0010 0101

0000 0000

0100 1111

0001 0011

0000 0001

0000 1011

1101 1111

0000 0001

0010 1011

0000 1001

0000 0001

0000 1101

0000 0000

0000 0001

0000 0000

load LUT

REG[02h]

REG[03h]

REG[04h]

REG[05h]

REG[06h]

REG[07h]

REG[08h]

REG[09h]

REG[0Ah]

REG[0Bh]

REG[0Ch]

REG[0Dh]

REG[19h]

REG[1Bh]

REG[24h]

REG[26h]

set panel type

set MOD rate

set horizontal display width

set horizontal non-display period

set HSYNC start position

set HSYNC polarity and pulse width

set vertical display height bits 7-0

set vertical display height bits 9-8

set vertical non-display period

set VSYNC start position

set VSYNC polarity and pulse width

set 8 bpp and LCD enable

set MCLK and PCLK divide

disable half frame buffer

set Look-Up Table address to 0

load Look-Up Table

S1D13505

X23A-G-003-07

Programming Notes and Examples

Issue Date: 01/02/05

S1D13505F00A Register Summary

X23A-R-001-04

REG[11h] SCREEN 1 DISPLAY START ADDRESS REGISTER 1

Screen 1 Start Address

Bit 12 Bit 11

REG[22h] PERFORMANCE ENHANCEMENT REGISTER 0

REG[00h] REVISION CODE REGISTER

(For S1D13505: Product Code=000011b, Revision Code=00b)RO

Revision Code

Bit 1 Bit 0

RC Timing Value

Bit 1

RAS#-to- RAS# Precharge Timing

CAS#

Product Code

Bit 3 Bit 2

Reserved

Bit 15

Bit 14

Bit 13

Bit 10

Bit 9

Bit 8

Bit 0

Bit 1

Bit 0

Bit 5

Bit 4

Bit 1

n/a

Bit 0

Delay

REG[12h] SCREEN 1 DISPLAY START ADDRESS REGISTER 2

n/a n/a n/a n/a

REG[23h] PERFORMANCE ENHANCEMENT REGISTER 1

REG[01h] MEMORY CONFIGURATION REGISTER

1/0

n/a

Screen 1 Start Address

CPU to Memory Wait State

DisplayFIFO

Display FIFO Threshold

Refresh Rate

Memory

Type

Bit 19

Bit 18

Bit 2

Bit 17

Bit 1

Bit 9

Bit 16

Disable

n/a

WE# Control

Bit 1

Bit 0

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Bit 2

Bit 1

Bit 0

REG[13h] SCREEN 2 DISPLAY START ADDRESS REGISTER 0

Screen 2 Start Address

Bit 4 Bit 3

REG[24h] LOOK-UP TABLE ADDRESS REGISTER

Look-Up Table Address

REG[02h] PANEL TYPE REGISTER

1/0

EL Panel

Enable

Panel Data Width

Panel Data Color/Mono Dual/Single TFT/Passive

n/a

Bit 7

Bit 6

Bit 5

Bit 0

Format Slct Panel Slct

Panel Slct LCD Pan Slct

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

n/a

Bit 1

n/a

Bit 0

Bit 1

Bit 0

REG[14h] SCREEN 2 DISPLAY START ADDRESS REGISTER 1

Screen 2 Start Address

Bit 12 Bit 11

REG[03h] MOD RATE REGISTER

n/a n/a

REG[26h] LOOK-UP TABLE DATA REGISTER

n/a

MOD Rate

Look-Up Table Data

n/a

Bit 15

Bit 14

Bit 13

Bit 10

Bit 8

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Bit 3

Bit 2

Bit 1

Bit 0

n/a

REG[15h] SCREEN 2 DISPLAY START ADDRESS REGISTER 2

n/a n/a n/a n/a

REG[04h] HORIZONTAL DISPLAY WIDTH REGISTER

Horizontal Display Width = 8(REG + 1)

Bit 4 Bit 3 Bit 2

REG[27h] INK/CURSOR CONTROL REGISTER

Screen 2 Start Address

Ink/Cursor Mode

n/a

Cursor High Threshold

n/a

Bit 19

Bit 18

Bit 2

Bit 17

Bit 1

Bit 16

Bit 6

Bit 5

Bit 1

Bit 0

Bit 1

Bit 0

Bit 3

Bit 2

Bit 1

Bit 0

REG[16h] MEMORY ADDRESS OFFSET REGISTER 0

Memory Address Offset

REG[05h] HORIZONTAL NON-DISPLAY PERIOD REGISTER

Horizontal Non-Display Period = 8(REG + 1)

Bit 3 Bit 2 Bit 1

REG[28h] CURSOR X POSITION REGISTER 0

Cursor X Position

n/a

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 0

Bit 4

Bit 0

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

n/a

Bit 1

Bit 0

REG[17h] MEMORY ADDRESS OFFSET REGISTER 1

REG[06h] HRTC/FPLINE START POSITION REGISTER

HRTC/FPLINE Start Position = 8(REG + 1) - 2

Bit 3 Bit 2 Bit 1

REG[29h] CURSOR X POSITION REGISTER 1

Reserved n/a n/a

Memory Address Offset

Cursor X Position

n/a

Bit 10

Bit 9

Bit 8

Bit 4

Bit 0

Bit 9

Bit 8

REG[18h] PIXEL PANNING REGISTER

REG[07h] HRTC/FPLINE PULSE WIDTH REGISTER

HRTC FPLINE

REG[2Ah] CURSOR Y POSITION REGISTER 0

Screen 2 Pixel Panning

Screen 1 Pixel Panning

HRTC/FPLINE Pulse Width = 8(REG + 1)

Cursor Y Position

n/a

Bit 3

Bit 2

Bit 1

Bit 0

n/a

Bit 3

n/a

Bit 2

Bit 1

Bit 0

Polarity Slct Polarity Slct

Bit 3

Bit 2

Bit 1

Bit 0

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

n/a

Bit 1

Bit 0

REG[19h] CLOCK CONFIGURATION REGISTER

Reserved n/a n/a

PCLK Divide Slct

Bit 1 Bit 0

REG[08h] VERTICAL DISPLAY HEIGHT REGISTER 0

Vertical Display Height = (REG + 1)

REG[2Bh] CURSOR Y POSITION REGISTER 1

Reserved n/a n/a

Cursor Y Position

Bit 8

MCLK

Divide Slct

n/a

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

n/a

Bit 1

Bit 0

Bit 9

Bit 1

Bit 9

Bit 1

Bit 9

Bit 1

REG[1Ah] POWER SAVE CONFIGURATION REGISTER

REG[09h] VERTICAL DISPLAY HEIGHT REGISTER 1

n/a n/a n/a n/a

Vertical Display Height

Bit 9 Bit 8

REG[2Ch] INK/CURSOR COLOR 0 REGISTER 0

Suspend Refresh Select

Power Save

LCD Power

Disable

Software

Suspend En

Cursor Color 0

Bit 4 Bit 3

n/a

Status RO

Bit 1

Bit 0

Bit 7

Bit 6

Bit 5

Bit 2

Bit 10

Bit 2

Bit 0

REG[1Bh] MISCELLANIOUS REGISTER

REG[0Ah] VERTICAL NON-DISPLAY PERIOD REGISTER

REG[2Dh] INK/CURSOR COLOR 0 REGISTER 1

Host

Interface

Disable

Half Frame

Buffer

Disable

Vertical Non-Display Period (VNDP) = (REG + 1)

Bit 4 Bit 3 Bit 2 Bit 1

Cursor Color 0

Bit 12 Bit 11

VNDP

Status (RO)

n/a

Bit 5

Bit 0

Bit 15

Bit 14

Bit 13

Bit 8

REG[0Bh] VRTC/FPFRAME START POSITION REGISTER

VRTC/FPFRAME Start Position = (REG + 1)

REG[1Ch] MD CONFIGURATION READBACK REGISTER 0

REG[2Eh] INK/CURSOR COLOR 1 REGISTER 0

MD7

Status

MD6

Status

MD5

Status

MD4

Status

MD3

Status

MD2

Status

MD1

Status

MD0

Status

Cursor Color 1

Bit 4 Bit 3

n/a

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Bit 7

Bit 6

Bit 5

Bit 0

REG[1Dh] MD CONFIGURATION READBACK REGISTER 1

REG[0Ch] VRTC/FPFRAME PULSE WIDTH REGISTER

VRTC/FPFRAME Pulse Width = (REG + 1)

REG[2Fh] INK/CURSOR COLOR 1 REGISTER 1

MD15

Status

MD14

Status

MD13

Status

MD12

Status

MD11

Status

MD10

Status

MD9

Status

MD8

Status

Cursor Color 1

Bit 12 Bit 11

VRTC

FPFRAME

n/a

Polarity Slct Polarity Slct

Bit 2

Bit 1

Bit 0

Bit 15

Bit 14

Bit 13

Bit 10

Bit 2

Bit 8

REG[1Eh] GENERAL IO PINS CONFIGURATION REGISTER 0

GPIO3 Pin GPIO2 Pin GPIO1 Pin

n/a

REG[0Dh] DISPLAY MODE REGISTER

REG[30h] INK/CURSOR START ADDRESS SELECT REGISTER

Ink/Cursor Start Address Select

Bit 4 Bit 3

n/a

IO Config

Hardware

Portrait

Mode

Simultaneous Display

Option Select

Bit-per-pixel Select

Bit 1

CRT Enable LCD Enable

Bit 7 WO

Bit 6

Bit 5

Bit 0

Bit 1

Bit 0

Bit 2

Bit 0

REG[1Fh] GENERAL IO PINS CONFIGURATION REGISTER 1

n/a n/a n/a n/a

n/a

Enable

REG[31h] ALTERNATE FRM REGISTER

Alternate Frame Range Modulation Select

Bit 5 Bit 4 Bit 3 Bit 2

n/a

REG[0Eh] SCREEN 1 LINE COMPARE REGISTER 0

Screen 1 Line Compare

Bit 7

Bit 6

Bit 0

REG[20h] GENERAL IO PINS CONTROL REGISTER 0

n/a n/a n/a n/a

n/a

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

n/a

Bit 1

Bit 0

GPIO3 Pin GPIO2 Pin GPIO1 Pin

IO Status

REG[0Fh] SCREEN 1 LINE COMPARE REGISTER 1

n/a n/a n/a n/a

Screen 1 Line Compare

Notes

These bits are used to identify the S1D13505. For the S1D13505 the product code should be 3. The host

interface must be enabled before reading this register (set REG[1B] b7=0).

REG[21h] GENERAL IO PINS CONTROL REGISTER 1

n/a

Bit 9

Bit 8

GPO

Control

n/a

N/A bits should be written 0.

Reserved bits must be written 0.

REG[10h] SCREEN 1 DISPLAY START ADDRESS REGISTER 0

Screen 1 Start Address

Bit 4 Bit 3

Bit 7

Bit 6

Bit 5

Bit 2

Bit 1

Bit 0

Page 1

01/02/06

S1D13505F00A Register Summary

X23A-R-001-04

DRAM Refresh Rate Select

11 RAS Precharge Timing Select

DRAM Refresh

Rate Select Bits

[2:0]

Example Refresh

Rate for CLKI =

33MHz

Example period for

256 refresh cycles at

CLKI = 33MHz

REG[22h] Bits [3:2]

RAS Precharge Width (t

)

CLKI Frequency

Divisor

1.5

000

001

010

011

100

101

110

111

520 kHz

260 kHz

130 kHz

65 kHz

33 kHz

16 kHz

8 kHz

0.5 ms

1 ms

128

Reserved

256

2 ms

12 Ink/Cursor Start Address Encoding

512

4 ms

1024

2048

4096

8192

8 ms

Ink/Cursor Start Address Bits [7:0]

Start Address (Bytes)

Display Buffer Size – 1024

Display Buffer Size – (n x 8192)

16 ms

32 ms

64 ms

n = 255...1

4 kHz

Panel Data Width Selection

PanelData Width Bits

[1:0]

Passive LCD Panel Data Width

Size

TFT Panel Data Width Size

4-bit

8-bit

9-bit

12-bit

16-bit

Reserved

Simultaneous Display Option Selection

Simultaneous Display Option Select Bits

[1:0]

Simultaneous Display Mode

Normal

Line Doubling

Interlace

Even Scan Only

Number of Bits-Per-Pixel Selection

Bit-Per-Pixel Select Bits [2:0]

Color Depth (Bit-Per-Pixel)

000

001

1 bpp

2 bpp

010

4 bpp

011

8 bpp

100

15 bpp

16 bpp

Reserved

101

110-111

PCLK Divide Selection

PCLK Divide Select Bits [1:0]

MCLK: PCLK Frequency Ratio

1: 1

2: 1

3: 1

4: 1

Suspend Refresh Selection

Suspend Refresh Select Bits [1:0]

DRAM Refresh Type

CAS-before-RAS (CBR) Refresh

Self-Refresh

No Refresh

Minimum Memory Timing Selection

REG[22h] Bits [6:5]

Minimum Random Cycle

Width (t

)

Reserved

10 RAS#-to-CAS# Delay Timing Select

REG[22h] Bit 4

RAS#-to-CAS# Delay (t

)

RCD

Page 2

01/02/06

S1D13505 Embedded RAMDAC LCD/CRT Controller

13505CFG Configuration Program

Document Number: X23A-B-001-04

Information in this document is subject to change without notice. You may download and use this document, but only for your own use in

evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any

representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain

material protected under U.S. and/or International Patent laws.

EPSON is a registered trademark of Seiko Epson Corporation. Microsoft and Windows are registered trademarks of Microsoft Corporation.

All other trademarks are the property of their respective owners.

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S1D13505

X23A-B-001-04

13505CFG Configuration Program

Issue Date: 01/03/29

Epson Research and Development

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Table of Contents

13505CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

S1D13505 Supported Evaluation Platforms . . . . . . . . . . . . . . . . . . . . . . 5

Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

13505CFG Configuration Tabs . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

General Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Preferences Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Memory Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Clocks Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Panel Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

CRT/TV Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Registers Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

13505CFG Menus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Open... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Save . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Save As... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Configure Multiple . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Export . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Enable Tooltips . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

ERD on the Web . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

About 13505CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Comments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

13505CFG Configuration Program

Issue Date: 01/03/29

S1D13505

X23A-B-001-04

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S1D13505

X23A-B-001-04

13505CFG Configuration Program

Issue Date: 01/03/29

Epson Research and Development

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13505CFG

13505CFG is an interactive Windows® 9x/ME/NT/2000 program that calculates register

values for a user defined S1D13505 configuration. The configuration information can be

used to directly alter the operating characteristics of the S1D13505 utilities or any program

built with the Hardware Abstraction Layer (HAL) library. Alternatively, the configuration

information can be saved in a variety of text file formats for use in other applications.

S1D13505 Supported Evaluation Platforms

13505CFG runs on PC systems running Windows 9x/ME/NT/2000 and can modify the

executable files based on the S1D13505 HAL for the following evaluation platforms:

• PC system with an Intel 80x86 processor.

• M68EC000IDP (Integrated Development Platform) board, revision 3.0, with a Motorola

M68EC000 processor.

• MC68030IDP (Integrated Development Platform) board, revision 3.0, with a Motorola

MC68030 processor.

• SH3-LCEVB board, revision B, with an Hitachi SH-3 HD6417780 processor.

• MPC821ADS (Applications Development System) board, revision B, with a Motorola

MPC821 processor.

13505CFG Configuration Program

Issue Date: 01/03/29

S1D13505

X23A-B-001-04

Page 6

Epson Research and Development

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Installation

Create a directory for 13505cfg.exe and the S1D13505 utilities. Copy the files

13505cfg.exe and panels.def to that directory. Panels.def contains configuration infor-

mation for a number of panels and must reside in the same directory as 13505cfg.exe.

Usage

13505CFG can be started from the Windows desktop or from a Windows command

prompt.

To start 13505CFG from the Windows desktop, double click the program icon or the link

icon if one was created during installation.

To start 13505CFG from a Windows command prompt, change to the directory

13505cfg.exe was installed to and type the command 13505cfg.

The basic procedure for using 13505CFG is:

1. Start 13505CFG as described above.

2. Open an existing file to serve as a starting reference point (this step is optional).

3. Modify the configuration. For specific information on editing the configuration, see

“13505CFG Configuration Tabs ” on page 7.

4. Save the new configuration. The configuration information can be saved in two ways;

as an ASCII text file or by modifying the executable image on disk.

Several ASCII text file formats are supported. Most are formatted C header files used

to build display drivers or standalone applications.

Utility files based on the Hardware Abstraction Layer (HAL) can be modified directly

by 13505CFG.

S1D13505

X23A-B-001-04

13505CFG Configuration Program

Issue Date: 01/03/29

Epson Research and Development

Page 7

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13505CFG Configuration Tabs

13505CFG provides a series of tabs which can be selected at the top of the main window.

Each tab allows the configuration of a specific aspect of S1D13505 operation.

The tabs are labeled “General”, “Preference”, “Memory”, “Clocks”, “Panel”, “CRT”, and

“Registers”. The following sections describe the purpose and use of each of the tabs.

General Tab

Decode Addresses

Display Buffer Address

The General tab contains S1D13505 evaluation board specific information. The values

presented are used for configuring HAL based executable utilities. The settings on this tab

specify where in CPU address space the registers and display buffer are located.

Decode Addresses

Selecting one of the listed evaluation platforms changes

the values for the “Register address” and “Display

buffer address” fields. The values used for each evalu-

ation platform are examples of possible implementa-

tions as used by the Epson S1D13505 evaluation

boards. If your hardware implementation differs from

the addresses used, select the User-Defined option and

enter the correct addresses for “Register address” and

“Display buffer address”.

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The physical address of the start of register decode

space (in hexadecimal).

This field is automatically set according to the Decode

Address unless the “User-Defined” decode address is

selected.

Display Buffer Address

The physical address of the start of display buffer

decode space (in hexadecimal).

This field is automatically set according to the Decode

Address unless the “User-Defined” decode address is

selected.

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Preferences Tab

Initial Display

Panel SwivelView

Panel Color Depth

CRT Color Depth

The Preference tab contains settings pertaining to the initial display state. During runtime

the display or color depth may be changed.

Initial Display

Sets which display device is used for the initial display.

Selections made on the CRT tab may cause selections

on this tab to be grayed out. The selections “None” and

“Panel” are always available.

Panel SwivelView

The S1D13505 SwivelView feature is capable of

rotating the image displayed on an LCD panel 90° in a

clockwise direction. This sets the initial orientation of

the panel.

This setting is greyed out when any display device other

than “Panel” is selected as the Initial Display.

Panel Color Depth

CRT Color Depth

Sets the initial color depth on the LCD panel.

Sets the initial color depth on the CRT display.

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Memory Tab

Access Time

Memory Type

Refresh Time

WE# Control

Suspend Mode

Memory

Performance

Installed Memory

The Memory tab contains settings that control the configuration of the DRAM used for the

S1D13505 display buffer.

Note

The DRAM memory type and access time determines the optimal memory clock

(MCLK). See “Clocks Tab ” on page 12 for an explanation on how to determine the op-

timal memory clock.

Memory Configuration

These four settings must be configured based on the

specification of the DRAM being used. For each of the

following settings refer to the DRAM manufacturer’s

specification unless otherwise noted.

Access Time

Selects the access time of the DRAM.

The S1D13505 evaluation boards use 50ns DRAM.

Memory Type

Selects the memory type, either Extended Data Out

(EDO) or Fast Page Mode (FPM).

The S1D13505 evaluation boards use EDO DRAM.

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WE# Control

Selects the WE# control used for the DRAM. DRAM

uses one of two methods of control when writing to

memory. These methods are referred to as 2-CAS# and

2-WE#.

The S5U13505 evaluation boards use DRAM requiring

the 2-CAS# method.

Refresh Time

This value represents the number of ms required to

refresh 256 rows of DRAM.

Memory Performance

These settings optimize the memory timings for best

performance. The default values change based on the

memory configuration (access time, memory type, etc.).

For further information on configuring these settings,

refer to the S1D13505 Hardware Functional Specifi-

cation, document number X23A-A-001-xx and the

DRAM manufacturer’s specification.

Suspend Mode Refresh

Selects the DRAM refresh method used during power

save mode.

The S5U13505 evaluation boards use DRAM requiring

Self Refresh. For all other implementations, refer to the

manufacturer’s specification for DRAM refresh

requirements.

CAS before RAS

Select this setting for DRAM that requires timing where

the CAS signal occurs before the RAS signal for low

power memory refresh.

Self refresh

No refresh

Select this setting for DRAM that requires no signal

from the S1D13505 to maintain memory refresh.

This selection does not refresh the memory during

power save mode. If this option is selected, the memory

contents are lost during power save.

Installed Memory

Selects the amount of DRAM available for the display

buffer.

The S1D13505 evaluation boards have 2M bytes of

DRAM installed.

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Clocks Tab

LCD PCLK

Source

LCD PCLK

Divide

CLKI

BUSCLK

CRT/TV PCLK

Source

CRT/TV PCLK

Divide

MCLK Divide

MCLK Source

The Clocks tab is intended to simplify the selection of input clock frequencies and the

source of internal clocking signals. For further information regarding clocking and clock

sources, refer to the S1D13505 Hardware Functional Specification, document number

X23A-A-001-xx.

In automatic mode the values are calculated based on either the LCD or CRT tab settings.

In this mode, the required frequencies for the input clocks are displayed in blue in the

“Auto” section of each group. It is the responsibility of the system designer to ensure that

the correct CLKI frequencies are supplied to the S1D13505.

Making a selection other than “Auto” indicates that the value for CLKI is known and is

fixed by the system design. Options for LCD and CRT frame rates are limited to ranges

determined by the clock values.

Note

Changing clock values may modify or invalidate Panel or CRT settings. Confirm all set-

tings on these two tabs after changing any clock settings.

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The S1D13505 may use as many as three input clocks or as few as one. The more clocks

used the greater the flexibility of choice in display type and memory speed.

CLKI

This setting determines the frequency of CLKI. CLKI is

the source clock for all of the S1D13505 internal clocks.

Select “LCD Auto” or “CRT Auto” to have the CLKI

frequency determined automatically based on settings

made on the Panels or CRT configuration tabs. After

completing the other configurations, the required CLKI

frequency will be displayed in blue in the Auto section.

If the CLKI frequency must be fixed to a particular rate,

set this value by selecting a preset frequency from the

drop down list or entering the desired frequency in

MHz.

BUSCLK

This setting determines the frequency of the bus

interface clock (BUSCLK).

The BUSCLK frequency must be specified. Set this

value by selecting a preset frequency from the drop

down list or entering the desired frequency in MHz.

LCD PCLK

These settings select the signal source and input clock

divisor for the panel pixel clock (LCD PCLK).

Source

Divide

The LCD PCLK source is MCLK.

Specifies the divide ratio of MCLK to derive the LCD

PCLK.

Selecting “Auto” for the divisor allows the configu-

ration program to calculate the best clock divisor.

Unless a very specific clocking is being specified, it is

best to leave this setting on “Auto”.

Timing

This field shows the actual LCD PCLK frequency used

by the configuration process calculations.

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CRT PCLK

These settings select the signal source and input clock

divisor for the CRT pixel clock (CRT PCLK).

Source

Divide

The CRT PCLK source is CLKI.

Specifies the divide ratio of CLKI to derive the CRT

PCLK.

Selecting “Auto” for the divisor allows the configu-

ration program to calculate the best clock divisor.

Unless a very specific clocking is required, it is best to

leave this setting on “Auto”.

Timing

This field shows the actual CRT PCLK frequency used

by the configuration process calculations.

MCLK

These settings select the signal source and input clock

divisor for the memory clock (MCLK).

Source

Divide

The MCLK source is CLKI.

Specifies the divide ratio of CLKI to derive MCLK.

Leave this setting at 1:1 ratio unless MCLK is greater

than 40MHz.

Timing

This field shows the actual MCLK frequency used by

the configuration process calculations.

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Panel Tab

Dual Panel

Buffer Disable

Panel Data Width

Single/Dual

Mono/Color

Format 2

Panel Type

EL Support

FPLINE

Polarity

FPFRAME

Polarity

Frame Rate

Pixel Clock

Panel Dimensions

Predefined

Panels

HRTC/FPLINE

Non-Display

Period

VRTC/FPFRAME

The S1D13505 supports many panel types. This tab allows configuration of most panel

settings such as panel dimensions, type and timings.

Panel Type

Selects between passive (STN) and active (TFT) panel

types.

Several options may change or become unavailable

when the STN/TFT setting is switched. Therefore,

confirm all settings on this tab after the Panel Type is

changed.

EL Support

Enable Electro-Luminescent panel support. This option

is only available when the selected panel type is STN.

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Panel Data Width

Selects the panel data width. Panel data width is the

number of bits of data transferred to the LCD panel on

each clock cycle and shouldn’t be confused with color

depth which determines the number of displayed colors.

When the panel type is STN, the available options are 4

bit, 8 bit, and 16 bit. When the panel type is TFT the

available options are 9 bit, 12 bit, and 18 bit.

Single / Dual

Selects between a single or dual panel.

When the panel type is TFT, “Single” is automatically

selected and the “Dual” option is grayed out.

Disable Dual Panel Buffer

The Dual Panel Buffer is used with dual STN panels to

improve image quality by buffering display data in a

format directly usable by the panel.

This option is primarily intended for testing purposes. It

is not recommended that the Dual Panel Buffer be

disabled as a reduction of display quality results.

Mono / Color

Format 2

Selects between a monochrome or color panel.

Selects color STN panel format 2. This option is specif-

ically for configuring 8-bit color STN panels.

See the S1D13505 Hardware Functional Specification,

document number X23A-A-001-xx, for description of

format 1 / format 2 data formats. Most new panels use

the format 2 data format.

FPLINE Polarity

Selects the polarity of the FPLINE pulse.

Refer to the panel specification for the correct polarity

of the FPLINE pulse.

FPFRAME Polarity

Selects the polarity of the FPFRAME pulse.

Refer to the panel specification for the correct polarity

of the FPFRAME pulse.

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Panel Dimensions

These fields specify the panel width and height. A

number of common widths and heights are available in

the selection boxes. If the width/height of your panel is

not listed, enter the actual panel dimensions into the edit

field.

Manually entered panel widths must be a multiple of 16

pixels for passive (STN) panels and 8 pixels for TFT

panels. If a manually entered panel width does not meet

the above restrictions a notification box appears and

13505CFG rounds up the value to the next allowable

width.

Non-display period

It is recommended that these automatically generated

non-display values be used without adjustment.

However, manual adjustment may be required to fine

tune the non-display width and the non-display height.

As a general rule passive LCD panels and some CRTs

are tolerant of a wide range of non-display times. Active

panels and some CRTs are far less tolerant of changes

to the non-display period.

Frame Rate

Select the desired frame rate (in Hz) from the drop-

down list. The values in the list are the range of possible

frame rates using the currently selected pixel clock. To

change the range of frame rates, select a different Pixel

Clock rate (in MHz).

Panel dimensions are fixed, therefore frame rate can

only be adjusted by changing either PCLK or non-

display period values. Higher frame rates correspond to

smaller horizontal and vertical non-display values, or

higher frequencies.

Pixel Clock

Select the desired Pixel Clock (in MHz) from the drop-

down list. The range of frequencies displayed is

dependent on settings selected on the Clocks tab.

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HRTC/FPLINE (pixels)

These settings allow fine tuning the TFT line pulse

parameters and are only available when the selected

panel type is TFT. Refer to S1D13505 Hardware

Functional Specification, document number X23A-A-

001-xx for a complete description of the FPLINE pulse

settings.

Start pos

Specifies the delay (in pixels) from the start of the

horizontal non-display period to the leading edge of the

FPLINE pulse.

Pulse Width

Specifies the pulse width (in pixels) of the FPLINE

output signal.

VRTC/FPFRAME (lines)

These settings allow fine tuning the TFT frame pulse

parameters and are only available when the selected

panel type is TFT. Refer to S1D13505 Hardware

Functional Specification, document number X23A-A-

001-xx, for a complete description of the FPFRAME

pulse settings.

Start pos

Specify the delay (in lines) from the start of the vertical

non-display period to the leading edge of the

FPFRAME pulse.

Pulse width

Specifies the pulse width (in lines) of the FPFRAME

output signal.

Predefined Panels

13505CFG uses a file (panels.def) which lists various

panel manufacturers recommended settings. If the file

panels.def is present in the same directory as

13505cfg.exe, the settings for a number of predefined

panels are available in the drop-down list. If a panel is

selected from the list, 13505CFG loads the predefined

settings contained in the file.

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CRT/TV Tab

CRT Display

Dimensions

Simultaneous

Display Options

The CRT tab configures settings specific to the CRT display device.

CRT Display Dimensions

Select the CRT resolution and frame rate from the drop-

down list. The available options vary based on selec-

tions made in the Clocks tab.

If no selections are available, the CRT pixel clock

settings on the Clocks tab must be changed.

Simultaneous Display Options

When both the LCD and CRT are operating in simulta-

neous display mode, a method of displaying both

images must be selected based on the vertical resolution

(height) of the images. If both displays are the same

resolution, select “Normal”. Otherwise, refer to the

S1D13505 Hardware Functional Specification,

document number X23A-A-001-xx for information on

selecting the best option.

Note

For CRT operations, 13505CFG supports VESA timings only. Overriding these register

values on the Registers page may cause the CRT to display incorrectly.

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Registers Tab

The Registers tab allows viewing and direct editing the S1D13505 register values.

Scroll up and down the list of registers and view their configured value. Individual register

settings may be changed by double-clicking on the register in the listing. Manual changes

to the registers are not checked for errors, so caution is warranted when directly

editing these values. It is strongly recommended that the S1D13505 Hardware Functional

Specification, document number X23A-A-001-xx be referred to before making an manual

Manually entered values may be changed by 13505CFG if further configuration changes

are made on the other tabs. In this case, the user is notified of the changes when they return

to the registers tab.

Note

Manual changes to the registers may have unpredictable results if incorrect values are

entered.

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13505CFG Menus

The following sections describe each of the options in the File and Help menus.

Open...

From the Menu Bar, select “File”, then “Open...” to display the Open File Dialog Box.

The Open option allows 13505CFG to open files containing HAL configuration infor-

mation. When 13505CFG opens a file it scans the file for an identification string, and if

found, reads the configuration information. This may be used to quickly arrive at a starting

point for register configuration. The only requirement is that the file being opened must

contain a valid S1D13505 HAL library information block.

13505CFG supports a variety of executable file formats. Select the file type(s) 13505CFG

should display in the Files of Type drop-down list and then select the filename from the list

and click on the Open button.

Note

13505CFG is designed to work with utilities programmed using a given version of the

HAL. If the configuration structure contained in the executable file differs from the ver-

sion 13505CFG expects the Open will fail and an error message is displayed. This may

happen if the version of 13505CFG is substantially older, or newer, than the file being

opened.

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Save

From the Menu Bar, select “File”, then “Save” to initiate the save action. The Save menu

option allows a fast save of the configuration information to a file that was opened with the

Open menu option.

Note

This option is only available once a file has been opened.

Note

13505cfg.exe can be configured by making a copy of the file 13505cfg.exe and config-

uring the copy. It is not possible to configure the original while it is running.

Save As...

From the Menu Bar, select “File”, then “Save As...” to display the Save As Dialog Box.

“Save as” is very similar to Save except a dialog box is displayed allowing the user to name

the file before saving.

Using this technique a tester can configure a number of files differing only in configuration

information and name (e.g. BMP60Hz.EXE, BMP72Hz.EXE, BMP75Hz.EXE where only

the frame rate changes in each of these files).

Note

When “Save As” is selected then an exact duplicate of the file as opened by the “Open”

option is created containing the new configuration information.

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Configure Multiple

After determining the desired configuration, “Configure Multiple” allows the information

to be saved into one or more executable files built with the HAL library.

From the Menu Bar, select “File”, then “Configure Multiple” to display the Configure

Multiple Dialog Box.This dialog box is also displayed when a file(s) is dragged onto the

13505CFG window.

The left pane lists files available for configuration; the right pane lists files that have been

selected for configuration. Files can be selected by clicking the “Add” or “Add All”

buttons, double clicking any file in the left pane, or by dragging the file(s) from Windows

Explorer.

Selecting “Show all files” displays all files in the selected directory, whereas selecting

“Show conf. files only” will display only files that can be configured using 13505CFG.

The configuration values can be saved to a specific EXE file for Intel platforms, or to a

specific S9 or ELF file for non-Intel platforms. The file must have been compiled using the

13505 HAL library.

Checking “Preserve Physical Addresses” instructs 13505CFG to use the register and

display buffer address values the files were previously configured with. Addresses

specified in the General Tab are discarded. This is useful when configuring several

programs for various hardware platforms at the same time. For example, if configuring

ISA, MPC and IDP based programs at the same time for a new panel type, the physical

addresses for each are retained. This feature is primarily intended for the test lab where

multiple hardware configurations exist and are being tested.

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Export

After determining the desired configuration, “Export” permits the user to save the register

information as a variety of ASCII text file formats. The following is a list and description

of the currently supported output formats:

• a C header file for use in writing HAL library based applications.

• a C header file which lists each register and the value it should be set to.

• a C header file for use in developing Window CE display drivers.

• a C header file for use in developing display drivers for other operating systems such as

Linux, QNX, and VxWorks UGL or WindML.

• a comma delimited text file containing an offset, a value, and a description for each

S1D13505 register.

After selecting the file format, click the “Export As..." button to display the file dialog box

which allows the user to enter a filename before saving. Before saving the configuration

file, clicking the “Preview” button starts Notepad with a copy of the configuration file about

to be saved.

When the C Header File for S1D13505 WinCE Drivers option is selected as the export

type, additional options are available and can be selected by clicking on the Options button.

The options dialog appears as:

Mode Number

selects the mode number for

use in the header file

Cursor Support

selects the type of cursor support

enabled in the header file

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Enable Tooltips

Tooltips provide useful information about many of the items on the configuration tabs.

Placing the mouse pointer over nearly any item on any tab generates a popup window

containing helpful advice and hints.

To enable/disable tooltips check/uncheck the “Tooltips” option form the “Help” menu.

Note

Tooltips are enabled by default.

ERD on the Web

This “Help” menu item is actually a hotlink to the Epson Research and Development

website. Selecting “Help” then “ERD on the Web” starts the default web browser and

points it to the ERD product web site.

The latest software, drivers, and documentation for the S1D13505 is available at this

website.

About 13505CFG

Selecting the “About 13505CFG” option from the “Help” menu displays the about dialog

box for 13505CFG. The about dialog box contains version information and the copyright

notice for 13505CFG.

Comments

• On any tab particular options may be grayed out if selecting them would violate the

operational specification of the S1D13505 (i.e. Selecting extremely low CLKI frequen-

cies on the Clocks tab may result in no possible CRT options. Selecting TFT or STN on

the Panel tab enables/disables options specific to the panel type).

• The file panels.def is a text file containing operational specifications for several

supported, and tested, panels. This file can be edited with any text editor.

• 13505CFG allows manually altering register values. The manual changes may violate

memory and LCD timings as specified in the S1D13505 Hardware Functional Specifi-

cation, document number X23A-A-001-xx. If this is done, unpredictable results may

occur. Epson Research and Development, Inc. does not assume liability for any damage

done to the display device as a result of configuration errors.

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S1D13505

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13505CFG Configuration Program

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S1D13505 Embedded RAMDAC LCD/CRT Controller

13505SHOW Demonstration Program

Document Number: X23A-B-002-05

Information in this document is subject to change without notice. You may download and use this document, but only for your own use in

evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any

representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain

material protected under U.S. and/or International Patent laws.

EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.

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S1D13505

X23A-B-002-05

13505SHOW Demonstration Program

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13505SHOW

13505SHOW is designed to demonstrate and test some of the S1D13505 display capabilities. The

program can cycle through all the color depths and display a pattern showing all available colors, or

the user can specify a color depth and display configuration.

The 13505SHOW demonstration program must be configured and/or compiled to work with your

hardware platform. The program 13505CFG.EXE can be used to configure 13505SHOW. Consult

the 13505CFG users guide, document number X23A-B-001-xx, for more information on config-

uring S1D13505 utilities.

This software is designed to work in both embedded and personal computer (PC) environments. For

the embedded environment, it is assumed that the system has a means of downloading software from

the PC to the target platform. Typically this is done by serial communications, where the PC uses a

terminal program to send control commands and information to the target processor. Alternatively,

the PC can program an EPROM, which is then placed in the target platform. Some target platforms

can also communicate with the PC via a parallel port connection, or an Ethernet connection.

S1D13505 Supported Evaluation Platforms

13505SHOW supports the following S1D13505 evaluation platforms:

• PC system with an Intel 80x86 processor.

• M68332BCC (Business Card Computer) board, revision B, with a Motorola MC68332

processor.

• M68EC000IDP (Integrated Development Platform) board, revision 3.0, with a Motorola

M68EC000 processor.

• SH3-LCEVB board, revision B, with an Hitachi SH-3 HD6417780 processor.

Installation

PC platform: copy the file 13505SHOW.EXE to a directory that is in the DOS path on your hard

drive.

Embedded platform: download the program 13505SHOW to the system.

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Usage

PC platform: at the prompt, type

13505show [b=??] [/a] [/crt] [/g] [/lcd] [/noinit] [/p] [/read] [/s]

[/?].

Embedded platform: execute 13505showand at the prompt, type the command line argument.

Where:

b=??

starts 13505SHOW at a user specified bit-per-pixel (bpp)

level, where ?? can be: 1, 2, 4, 8, 15, or 16

automatically cycles through all video modes

displays the image on the CRT

shows grid on the image

/crt

/lcd

/noinit

displays the image on the LCD panel

bypasses register initialization

draws the image in portrait mode

/read

after drawing the image, continually read from the screen

(for testing purposes)

displays vertical stripe pattern

displays the help screen

Note

Pressing the ESC key will exit the program.

13505SHOW Examples

The 13505SHOW demonstration program is designed to both demonstrate and test some of the

features of the S1D13505. Some examples follow showing how to use the program in both instances.

Using 13505SHOW For Demonstration

1. To show color patterns which must be manually stepped through all bit-per-pixel modes, type

the following:

13505SHOW

The program will display 16 bit-per-pixel mode. Press any key to go to the next screen. The

program will display 15 bit-per-pixel mode. Once all screens are shown the program exits. To

exit the program immediately press ESC.

2. To show color patterns which automatically step through all bit-per-pixel modes, type the

following:

13505SHOW /a

The program will display 16 bit-per-pixel mode. Each screen is shown for approximately 1

second, then the next screen is automatically shown. The program exits after the last screen is

shown. To exit the program immediately press CTRL+BREAK.

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3. To show a color pattern for a specific bit-per-pixel mode, type the following:

13505SHOW b=[mode]

where mode = 1, 2, 4, 8, 15, or 16.

The program will display the requested screen and then exit.

4. To show the color patterns in portrait mode, type the following:

13505SHOW /p

The program will display 16 bit-per-pixel mode. Press any key to go to the next screen. The

program will next display 15 bit-per-pixel mode and then 8 bit-per-pixel mode. Since portrait

mode is limited to 8, 15, and 16 bit-per-pixel mode the program exits. To exit the program im-

mediately press ESC.

The “/p” switch can be used in combination with other command line switches.

5. To show solid vertical stripes, type the following:

13505SHOW /s

The program will display 16 bit-per-pixel mode. Press any key to go to the next screen. The

program will display 15 bit-per-pixel mode. Once all screens are shown the program exits. To

exit the program immediately press ESC.

The “/s” switch can be used in combination with other command line switches.

Using 13505SHOW For Testing

1. To show a test grid over the color pattern, type the following:

13505SHOW b=8 /g

The program will display the 8 bit-per-pixel color pattern overlaid with a one pixel wide white

grid and then exit. The grid makes it obvious if the image is shifted or if pixels are missing.

Note the grid is not aligned with the color pattern, therefore the color boxes will not match the

grid boxes.

The “/g” switch can be used in combination with other command line switches.

2. To test background memory reads, type the following:

13505SHOW b=16 /read

The program will test screen reads. If there is a problem with memory access, the displayed

pattern will appear different than when the “/read” switch is not used. If there is a problem,

check the configuration parameters of 13505SHOW using the utility 13505CFG. See the

13505CFG user guide, document number X23A-B-001-xx, for more information.

The “/read” switch should be used in combination with the “b=” setting, otherwise the test will

always start with the 16 bit-per-pixel screen. To exit the program after using “/read”, press

ESC and wait for a couple of seconds (the keystroke is checked after reading a full screen).

13505SHOW Demonstration Program

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Comments

• 13505SHOW cannot show a greater color depth than the display allows.

• Portrait mode is available only for 8, 15, and 16 bit-per-pixel.

• When using a PC with the S5U13505 evaluation board, the PC must not have more than 12M

bytes of system memory.

• 13505SHOW uses the panel color setup to determine whether to display a mono or color image

on both the panel and the CRT. When editing in 13505CFG with CRT enabled and panel

disabled, select “Color” from the “Panel” dialog box if you want the CRT to show color.

• For simultaneous display, select both “/lcd” and “/crt”.

• If the “b=” option is not used, 13505SHOW will cycle through all available bit-per-pixel modes.

S1D13505

X23A-B-002-05

13505SHOW Demonstration Program

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Program Messages

ERROR: Could not initialize device.

These messages generally mean that the given hardware/software setup violates the timing limita-

tions described in the 13505 Hardware Functional Specification, document number X23A-A-001-

xx.

ERROR: Unknown command line argument.

An invalid command line argument was entered. Refer to the help screen or documentation for valid

command line arguments.

ERROR: Too many devices registered.

There are too many display devices attached to the HAL. The HAL currently supports only one

device.

ERROR: Could not register S1D13505 device.

A 13505 device was not found at the configured addresses. Check the configuration address using

the 13505CFG configuration program.

ERROR: Did not find a 13505 device.

The HAL was unable to read the revision code register on the S1D13505. Ensure that the S1D13505

hardware is installed and that the hardware platform has been set up correctly.

ERROR: Continual screen read will not work with the /a switch.

The continual screen read function reads one screen indefinitely, so it is not possible to automatically

cycle through the video modes.

WARNING: b= option used with /noinit, so bit-per-pixel and display

memory will NOT be changed.

The b= option requests that registers be changed for a given bit-per-pixel mode, while the /noinit

option requests the opposite. To resolve this contradiction 13505SHOW will not change either the

registers or the display memory. Consequently “13505SHOW b=?? /noinit” is only useful for

continually reading the display memory.

UNSUPPORTED MODE: Cannot show ?? bpp in portrait mode.

Only 8, 15, 16 bit-per-pixel modes are supported in portrait mode.

ERROR: Could not change to ?? bit-per-pixel.

The HAL library detected that the requested bit-per-pixel mode will violate the hardware specifica-

tions for clocks. To reprogram the clocks, run 13505CFG and select the desired bit-per-pixel mode.

13505SHOW Demonstration Program

Issue Date: 01/02/02

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S1D13505

X23A-B-002-05

13505SHOW Demonstration Program

Issue Date: 01/02/02

S1D13505 Embedded RAMDAC LCD/CRT Controller

13505SPLT Display Utility

Document Number: X23A-B-003-03

Information in this document is subject to change without notice. You may download and use this document, but only for your own use in

evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any

representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain

material protected under U.S. and/or International Patent laws.

EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.

Page 2

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Vancouver Design Center

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S1D13505

X23A-B-003-03

13505SPLT Display Utility

Issue Date: 01/02/02

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13505SPLT

13505SPLT demonstrates S1D13505 split screen capability by showing two different areas of

display memory on the screen simultaneously. Screen 1 shows horizontal bars and Screen 2 shows

vertical bars.

Screen 1 memory is located at the start of the display buffer. Screen 2 memory is located immedi-

ately after Screen 1 in the display buffer. On user input, or elapsed time, the line compare register

value is changed to adjust the amount of area displayed on either screen. The result is a movement

up or down of screen 2 on the display.

The 13505SPLT display utility must be configured and/or compiled to work with your hardware

platform. The program 13505CFG.EXE can be used to configure 13505SPLT. Consult the

13505CFG users guide, document number X23A-B-001-xx, for more information on configuring

S1D13505 utilities.

This software is designed to work in both embedded and personal computer (PC) environments. For

the embedded environment, it is assumed that the system has a means of downloading software from

the PC to the target platform. Typically, this is done by serial communications. The PC uses a

terminal program to send control commands and information to the target processor. Alternatively,

the PC can program an EPROM, which is then placed in the target platform. Some target platforms

can also communicate with the PC via a parallel port connection, or an Ethernet connection.

S1D13505 Supported Evaluation Platforms

13505SPLT supports the following S1D13505 evaluation platforms:

• PC system with an Intel 80x86 processor.

• M68332BCC (Business Card Computer) board, revision B, with a Motorola MC68332

processor.

• M68EC000IDP (Integrated Development Platform) board, revision 3.0, with a Motorola

M68EC000 processor.

• SH3-LCEVB board, revision B, with an Hitachi SH-3 HD6417780 processor.

Installation

PC platform: copy the file 13505SPLT.EXE to a directory that is in the DOS path on your hard

drive.

Embedded platform: download the program 13505SPLT to the system.

13505SPLT Display Utility

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Usage

PC platform: at the prompt, type 13505splt [/a] [/?].

Embedded platform: execute 13505spltand at the prompt, type the command line argument.

Where:

no argument

enables manual split screen operation

enables automatic split screen operation

displays the help screen

The following keyboard commands are for navigation within the program.

Manual mode:

↑

moves Screen 2 up one line

↓

moves Screen 2 down one line

CTRL-↑

CTRL-↓

HOME

END

moves Screen 2 up several lines

moves Screen 2 down several lines

Screen 2 moved up as high as possible

Screen 2 moved down as low as possible

Automatic and Manual modes:

changes the color depth (bit-per-pixel)

exits 13505SPLT

ESC

13505SPLT Example

1. Type “13505splt /a” to automatically move the split screen.

2. Press "b" to change the bit-per-pixel value from 16 to 15 bit-per-pixel.

3. Repeat step 2 for the remaining bit-per-pixel color depths: 8, 4, 2, and 1.

4. Press <ESC> to exit the program.

Comments

• When using a PC with the S5U13505 evaluation board, the PC must not have more than 12M

bytes of system memory.

S1D13505

X23A-B-003-03

13505SPLT Display Utility

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Program Messages

ERROR: Did not find a 13505 device.

The HAL was unable to read the revision code register on the S1D13505. Ensure that the S1D13505

hardware is installed and that the hardware platform has been set up correctly.

ERROR: Too many devices registered.

There are too many display devices attached to the HAL. The HAL currently supports only one

device.

ERROR: Could not register S1D13505FOA device.

A S1D13505 device was not found at the configured addresses. Check the configuration address

using the 13505CFG configuration program.

ERROR: Could not set ?? bit-per-pixel display mode.

This message generally means that the given hardware/software setup violates the timing limitations

described in the S1D13505 Hardware Functional Specification, document number X23A-A-001-xx.

13505SPLT Display Utility

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X23A-B-003-03

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S1D13505

X23A-B-003-03

13505SPLT Display Utility

Issue Date: 01/02/02

S1D13505 Embedded RAMDAC LCD/CRT Controller

13505VIRT Display Utility

Document Number: X23A-B-004-04

Information in this document is subject to change without notice. You may download and use this document, but only for your own use in

evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any

representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain

material protected under U.S. and/or International Patent laws.

EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.

Page 2

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Vancouver Design Center

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S1D13505

X23A-B-004-04

13505VIRT Display Utility

Issue Date: 01/02/02

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13505VIRT

13505VIRT demonstrates the virtual display capability of the S1D13505. A virtual display is where

the image to be displayed is larger than the physical display device (CRT or LCD). 13505VIRT uses

panning and scrolling to allow the display device to show a “window” into the entire image.

The 13505VIRT display utility must be configured and/or compiled to work with your hardware

platform. The program 13505CFG.EXE can be used to configure 13505VIRT. Consult the

13505CFG users guide, document number X23A-B-001-xx, for more information on configuring

S1D13505 utilities.

This software is designed to work in both embedded and personal computer (PC) environments. For

the embedded environment, it is assumed that the system has a means of downloading software from

the PC to the target platform. Typically this is done by serial communications, where the PC uses a

terminal program to send control commands and information to the target processor. Alternatively,

the PC can program an EPROM, which is then placed in the target platform. Some target platforms

can also communicate with the PC via a parallel port connection, or an Ethernet connection.

S1D13505 Supported Evaluation Platforms

13505VIRT has been tested with the following S1D13505 supported evaluation platforms:

• PC system with an Intel 80x86 processor.

• M68332BCC (Business Card Computer) board, revision B, with a Motorola MC68332

processor.

• M68EC000IDP (Integrated Development Platform) board, revision 3.0, with a Motorola

M68EC000 processor.

• SH3-LCEVB board, revision B, with an Hitachi SH-3 HD6417780 processor.

Installation

PC platform: copy the file 13505VIRT.EXE to a directory that is in the DOS path on your hard

drive.

Embedded platform: download the program 13505VIRT to the system.

13505VIRT Display Utility

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Usage

PC platform: at the prompt, type 13505virt[w=??] [/a][/?].

Embedded platform: execute 13505virtand at the prompt, type the command line argument.

Where:

no argument

w=??

panning and scrolling is performed manually

for manual mode, specifies the width of the virtual

display which must be a multiple of 8 and less than

2048 (the default width is double the physical panel

width); the maximum height is based on the display

memory

panning and scrolling is performed automatically

displays the help screen

The following keyboard commands are for navigation within the program.

Manual mode:

↑

scrolls up

↓

scrolls down

←

pans to the left

→

pans to the right

CTRL-↑

CTRL-↓

CTRL-←

CTRL-→

HOME

scrolls up several lines

scrolls down several lines

pans to the left several lines

pans to the right several lines

moves the display screen so that the upper right corner

of the virtual screen shows in the display

END

moves the display screen so that the lower left corner

of the virtual screen shows in the display

Automatic and Manual modes:

changes the color depth (bit-per-pixel)

exits 13505VIRT

ESC

S1D13505

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13505VIRT Display Utility

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13505VIRT Example

1. Type "13505virt /a" to automatically pan and scroll.

2. Press "b" to change the bit-per-pixel value from 16 to 15 bit-per-pixel.

3. Repeat step 2 for the following bit-per-pixel values:

16, 15, 8, 4, 2, and 1.

4. Press <ESC> to exit the program.

Comments

• When using a PC with the S5U13505 evaluation board, the PC must not have more than 12M

bytes of system memory.

Program Messages

ERROR: Did not find a 13505 device.

The HAL was unable to read the revision code register on the S1D13505. Ensure that the S1D13505

hardware is installed and that the hardware platform has been set up correctly.

ERROR: Too many devices registered.

There are too many display devices attached to the HAL. The HAL currently supports only one

device.

ERROR: Could not register S1D13505F00A device.

A 13505 device was not found at the configured addresses. Check the configuration address using

the 13505CFG configuration program.

ERROR: Not enough display buffer memory for ?? BPP.

There was not enough memory for a virtual screen.

13505VIRT Display Utility

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S1D13505

X23A-B-004-04

13505VIRT Display Utility

Issue Date: 01/02/02

S1D13505 Embedded RAMDAC LCD/CRT Controller

13505PLAY Diagnostic Utility

Document Number: X23A-B-005-04

Information in this document is subject to change without notice. You may download and use this document, but only for your own use in

evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any

representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain

material protected under U.S. and/or International Patent laws.

EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.

Page 2

Epson Research and Development

Vancouver Design Center

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S1D13550

X23A-B-005-04

13505PLAY Diagnostic Utility

Issue Date: 01/02/02

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Vancouver Design Center

13505PLAY

13505PLAY is a diagnostic utility which allows the user to read/write to all the S1D13505 Registers,

Look-Up Tables and Display Buffer. 13505PLAY is similar to the DOS DEBUG program;

commands are received from the standard input device, and output is sent to the standard output

device (console for Intel, terminal for embedded platforms). This utility requires the target platform

to support standard IO (stdio).

13505PLAY commands can be entered interactively by a user, or be executed from a script file.

Scripting is a powerful feature which allows command sequences to be used repeatedly without

re-entry.

The 13505PLAY diagnostic utility must be configured and/or compiled to work with your hardware

platform. The program 13505CFG.EXE can be used to configure 13505PLAY. Consult the

13505CFG users guide, document number X23A-B-001-xx, for more information on configuring

S1D13505 utilities.

This software is designed to work in both embedded and personal computer (PC) environments. For

the embedded environment, it is assumed that the system has a means of downloading software from

the PC to the target platform. Typically this is done by serial communications, where the PC uses a

terminal program to send control commands and information to the target processor. Alternatively,

the PC can program an EPROM, which is then placed in the target platform. Some target platforms

can also communicate with the PC via a parallel port connection, or an Ethernet connection.

S1D13505 Supported Evaluation Platforms

13505PLAY supports the following S1D13505 evaluation platforms:

• PC system with an Intel 80x86 processor.

• M68332BCC (Business Card Computer) board, revision B, with a Motorola MC68332

processor.

• M68EC000IDP (Integrated Development Platform) board, revision 3.0, with a Motorola

M68EC000 processor.

• SH3-LCEVB board, revision B, with an Hitachi SH-3 HD6417780 processor.

Installation

PC platform: copy the file 13505PLAY.EXE to a directory that is in the DOS path on your hard

drive.

Embedded platform: download the program 13505PLAY to the system.

13505PLAY Diagnostic Utility

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Usage

PC platform: at the prompt, type 13505play [/?].

Embedded platform: execute 13505playand at the prompt, type the command line argument.

Where: /? displays program version information.

The following commands are valid within the 13505PLAY program.

b 8|16

- Sets the ISA bus to 8 or 16 bits.

- Only sets up the PAL on the S5U13505 evaluation

board. There is no readback capability.

- Only supported on a S5U13505 evaluation board for

the PC platform. Switch 1-1 on the ealuation board

must be set to the same bus width as used with this

command.

f[w] addr1 addr2 data . . .

- Fills bytes or words [w] from address 1 to address 2

with the data specified.

- Data can be multiple values (e.g. F 0 20 1 2 3 4

fills 0 to 0x20 with a repeating pattern of 1 2 3 4).

h [lines]

- Halts after lines of display. This feature halts the

display during long read operations to prevent data

from scrolling off the display. Similar to the DOS

MORE command.

- Set to 0 to disable this feature.

i [LCD] [CRT]

- Initializes the chip with the specified configuration.

The configuration is embedded in the 13505PLAY

utility and can be changed using the 13505CFG utility.

See the 13505CFG guide, document number

X23A-B-001-xx, for instructions on changing the

configuration.

- If the output device is specified, the user can select

LCD, CRT, or both devices.

l index [red green blue]

- Reads/writes Look-Up Table (LUT) values.

- Writes data to the LUT[index] when data is specified.

- Reads the LUT[index] when the data is not specified.

- Reads all LUT values.

m [bpp]

- Reads current mode information.

- Sets the color depth (bpp) if “bpp” is specified.

S1D13550

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13505PLAY Diagnostic Utility

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p 1|0

- Set power mode (hardware suspend).

1 = set hardware suspend.

0 = reset hardware suspend.

- This command is only supported on a S5U13505

evaluation board for the PC platform.

r[w] addr [count]

- Quits the 13505PLAY utility.

- Reads number of bytes or words [w] from the address

specified by “addr”. If “count” is not specified, then

16 bytes/words are read.

- Calculates the frame rate from VNDP count (PC

platform only).

w[w] addr data . . .

- Writes bytes or words [w] of data to the address

specified by “addr”.

- Data can be multiple values (e.g. W 0 1 2 3 4

writes the byte values 1 2 3 4 starting at address 0).

x[w] index [data]

- Reads/writes bytes or words [w] to/from the registers.

- Writes data to REG[index] when “data” is specified.

- Reads data from REG[index] when “data” is not

specified.

- Some platforms may provide upredictable results

when non-aligned word addresses are entered.

- Reads all registers.

- Displays Help information.

13505PLAY Example

1. Type "13505PLAY" to start the program.

2. Type "?" for help.

3. Type "i" to initialize the registers.

4. Type "xa" to display the contents of the registers.

5. Type "x 5" to read register 5.

6. Type "x 3 10" to write 10h to register 3.

7. Type "f 0 ffff aa" to fill the first FFFFh bytes of the display buffer with AAh.

8. Type "f 0 1fffff aa" to fill 2M bytes of the display buffer with AAh.

9. Type "r 0 100" to read the first 100h bytes of the display buffer.

10. Type "q" to exit the program.

13505PLAY Diagnostic Utility

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Scripting

13505PLAY can be driven by a script file. This is useful when:

• there is no display output and a current register status is required.

• various registers must be quickly changed to view results.

A script file is an ASCII text file with one 13505PLAY command per line. All scripts must end with

a “q” (quit) command.

On a PC platform, a typical script command line might be:

“13505PLAY < dumpregs.scr > results.”

This causes the file “dumpregs.scr” to be interpreted as commands by 13505PLAY and the results

to be sent to the file “results.”

Example: Create an ASCII text file that contains the commands i, xa, and q.

; This file initializes the S1D13505 and reads the registers.

; Note: after a semicolon (;), all characters on a line are ignored.

; Note: all script files must end with the “q” command.

Comments

• All numeric values are considered to be hexadecimal unless identified otherwise. For example,

10 = 10h = 16 decimal; 10t = 10 decimal; 010b = 2 decimal.

• Redirecting commands from a script file (PC platform) allows those commands to be executed as

though they were typed.

• When using a PC with the S5U13505 evaluation board, the PC must not have more than 12M

bytes of system memory.

S1D13550

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13505PLAY Diagnostic Utility

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Program Messages

WARNING: Did not find a 13505 device.

The HAL was unable to read the revision code register on the S1D13505. Ensure that the S1D13505

hardware is installed and that the hardware platform has been set up correctly.

ERROR: Failed to change to ?? mode.

Could not change to CRT, LCD, or SIMUL mode. This message generally means that the given

hardware/software setup violates the timing limitations described in the S1D13505 Hardware

Functional Specification, document number X23A-A-001-xx.

ERROR: Could not change to ?? bit-per-pixel.

This message generally means that the given hardware/software setup violates the timing limitations

described in the S1D13505 Hardware Functional Specification, document number X23A-A-001-xx.

ERROR: Too many devices registered.

There are too many display devices attached to the HAL. The HAL currently supports only one

device.

ERROR: Could not register S1D13505F00A device.

A S1D13505 device was not found at the configured addresses. Check the configuration address

using the 13505CFG configuration program.

ERROR: Insufficient memory for ?? bit-per-pixel.

The given display resolution requires a larger display buffer than is available to store the image.

Either increase the amount of display buffer or select a lower color depth (bpp).

WARNING: Clocks are too fast for given mode.

This message is only shown if the “m” command was entered and the MCLK/PCLK frequencies

violated the timings in the S1D13505 Hardware Functional Specification, document number X23A-

A-001-xx.

13505PLAY Diagnostic Utility

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S1D13550

X23A-B-005-04

13505PLAY Diagnostic Utility

Issue Date: 01/02/02

S1D13505 Embedded RAMDAC LCD/CRT Controller

13505BMP Demonstration Program

Document Number: X23A-B-006-04

Information in this document is subject to change without notice. You may download and use this document, but only for your own use in

evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any

representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain

material protected under U.S. and/or International Patent laws.

EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.

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S1D13505

X23A-B-006-04

13505BMP Demonstration Program

Issue Date: 01/02/02

Epson Research and Development

Page 1

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13505BMP

13505BMP is a demonstration utility used to show the S1D13505 display capabilities by rendering

bitmap images on the display. The program will display any bitmap in Windows BMP file format

and then exit. 13505BMP also loads images to demonstrate the hardware cursor and ink layer.

13505BMP is designed to operate on a personal computer (PC) in the DOS environment only. Other

embedded platforms are not supported due to the possible lack of system memory or structured file

system.

The 13505BMP demonstration utility must be configured and/or compiled to work with your

hardware configuration. The program 13505CFG.EXE can be used to configure 13505BMP.

Consult the 13505CFG users guide, document number X23A-B-001-xx, for more information on

configuring S1D13505 utilities.

S1D13505 Supported Evaluation Platforms

13505BMP supports the following S1D13505 evaluation platforms:

• PC system with an Intel 80x86 processor.

Note

The 13505BMP source code may be modified by the OEM to support other evaluation platforms.

Installation

Usage

Copy the file 13505BMP.EXE to a directory that is in the DOS path on your hard drive.

At the prompt, type 13505bmp bmpfile [t=reg | cursor | ink] [x=n y=n]

[/buffer] [/crt] [/lcd] [/mouse] [/noclear] [/noinit] [/p] [/v]

[/?].

Where: bmpfile

filename of a windows format bmp image

t=??

reg:

cursor: hardware cursor image

ink: ink layer image

regular display image

x=n

n = starting cursor x position (default position = 0)

n = starting cursor y position (default position = 0)

y=n

/buffer

enable double buffering (image not displayed until completely loaded

in memory)

/crt

/lcd

displays the image on a CRT

displays the image on an LCD panel

13505BMP Demonstration Program

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/mouse

/noclear

/noinit

use mouse to move hardware cursor (press ESC to exit program)

don’t clear display buffer memory

skips register initialization

portrait mode (not available for hardware cursor or ink layer images)

verbose mode (provides information about the displayed images)

displays the Help screen

Note

13505BMP will automatically finish execution and return to the prompt.

Hardware Cursor/Ink Layer

13505BMP requires the BMP images for the Hardware Cursor and the Ink Layer to be stored in

specific formats. The Hardware Cursor BMP image must have a color depth of four bit-per-pixel and

be 64x64 pixels in resolution. The Ink Layer BMP image must have a color depth of four bit-per-

pixel and be the same resolution as the displayed image.

Both images are stored at a color depth of four bit-per-pixel allowing easy editing and saving in most

paint programs. To allow the two bit-per-pixel Hardware Cursor and Ink Layer to use the four bit-

per-pixel images, they are translated to two bit-per-pixel as in the following table.

Table 1: 4 Bpp to 2 Bpp Translation

Image Color

white

Displayed Color

white

black

red

invert

any other color

transparent

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13505BMP Examples

To display a bmp image on a CRT, type the following:

13505BMP bmpfile.bmp /crt

To display a bmp image on an LCD, type the following:

13505BMP bmpfile.bmp /lcd

To display a bmp image on an LCD in portrait mode, type the following:

13505BMP bmpfile.bmp /lcd /p

To load a bmp image and a hardware cursor image on an LCD, type the following:

13505BMP /lcd bmpfile.bmp

13505BMP t=cursor /noinit arrow.bmp

To control the cursor with the mouse, include the “/mouse” option when loading the cursor image.

Comments

• 13505BMP displays only Windows BMP format images.

• The PC must not have more than 12M bytes of memory when used with the S5U13505 evalua-

tion board.

• A 24-bit true color bitmap will be displayed at a color depth of 16 bit-per-pixel.

• Only the green component of the image will be seen on a monochrome display.

• Prior to selecting the “/mouse” option, a valid mouse driver must be loaded.

• If x and y coordinates are not specified for the Hardware Cursor, the Hardware Cursor will be

displayed starting in the top left corner (position x=0,y=0).

13505BMP Demonstration Program

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Program Messages

ERROR: Could not initialize device.

The given hardware/software setup violates the timing specification as described in the S1D13505

Hardware Functional Specification, document number X23A-A-001-xx.

ERROR: Too many devices registered.

There are too many display devices attached to the HAL. The HAL currently supports only one

device.

ERROR: Could not register S1D13505F00A device.

A 13505 device was not found at the configured addresses. Check the configuration address using

the 13505CFG configuration program.

ERROR: Did not detect S1D13505.

The HAL was unable to read the revision code register on the S1D13505. Ensure that the S1D13505

hardware is installed and that the hardware platform has been set up correctly.

ERROR: Insufficient memory for ?? bit-per-pixel.

The given display resolution requires more memory than is available to store one complete image.

Either increase the amount of display memory or select an image with a lower bit-per-pixel value.

ERROR: Cannot use /p option with hardware cursor and ink layer.

Instead, rotate BMP file manually and load without /p option.

Because the Hardware Cursor and Ink Layer are not automatically rotated in portrait mode

13505BMP does not support the “/p” option. Instead, rotate the BMP with a paint program and then

load the rotated image in landscape (non-portrait) mode.

ERROR: Cannot use /buffer option without 2 Mbyte of display buffer

memory.

The “/buffer” option is not supported unless the platform has 2M bytes of memory.

ERROR: Could not switch portrait buffer.

The HAL library reported an error when changing the screen 1 start address register.

ERROR: Failed to open BMP file:‘filename’

The BMP file could not be opened as a read-only file.

ERROR: ‘filename’ is not a valid bitmap file.

The file does not contain a valid BMP format image.

ERROR: Could not initialize hardware cursor.

The HAL library could not initialize the Hardware Cursor.

ERROR: BMP file is ?? bit-per-pixel; hardware cursor requires 4 bit-

per-pixel BMP file.

The Hardware Cursor BMP image must always have a color depth of four bit-per-pixel.

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ERROR: Could not initialize ink layer.

The HAL library could not initialize the Ink Layer.

ERROR: BMP file is ?? bit-per-pixel; ink layer requires 4 bit-per-

pixel BMP file.

The Ink Layer BMP image must always have a color depth of four bit-per-pixel.

ERROR: Could not change to ?? bit-per-pixel.

The HAL library detected that the requested color depth (bit-per-pixel) will violate the S1D13505

hardware specification for clocks. To reprogram the clocks, run 13505CFG and select the desired

color depth (bit-per-pixel).

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S1D13505

X23A-B-006-04

13505BMP Demonstration Program

Issue Date: 01/02/02

S1D13505 Embedded RAMDAC LCD/CRT Controller

13505PWR Software Suspend Power

Sequencing Utility

Document Number: X23A-B-007-03

Information in this document is subject to change without notice. You may download and use this document, but only for your own use in

evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any

representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain

material protected under U.S. and/or International Patent laws.

EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.

Page 2

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S1D13505

X23A-B-007-03

13505PWR Software Suspend Power Sequencing Utility

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13505PWR

13505PWR is a diagnostic utility used to test some of the power save capabilities of the S1D13505.

13505PWR enables or disables the software suspend mode, hardware suspend mode, and the LCD,

allowing testing of the power sequencing in each mode.

To measure the timing for power sequencing, GPIO pin 1 is used to trigger an oscilloscope at the

point the requested power sequencing function is activated/deactivated. For further information on

LCD Power Sequencing and Power Save Modes, refer to the S1D13505 Programming Notes and

Examples, document number X23A-G-003-xx, and the S1D13505 Functional Hardware Specifi-

cation, document number X23A-A-01-xx.

The 13505PWR software suspend power sequencing utility must be configured and/or compiled to

work with your hardware platform. The program 13505CFG.EXE can be used to configure

13505PWR. Consult the 13505CFG users guide, document number X23A-B-001-xx, for more

information on configuring S1D13505 utilities.

This software is designed to work in both embedded and personal computer (PC) environments. For

the embedded environment, it is assumed that the system has a means of downloading software from

the PC to the target platform. Typically this is done by serial communications, where the PC uses a

terminal program to send control commands and information to the target processor. Alternatively,

the PC can program an EPROM, which is then placed in the target platform. Some target platforms

can also communicate with the PC via a parallel port connection, or an Ethernet connection.

S1D13505 Supported Evaluation Platforms

13505PWR supports the following S1D13505 evaluation platforms:

• PC system with an Intel 80x86 processor.

• M68332BCC (Business Card Computer) board, revision B, with a Motorola MC68332

processor.

• M68EC000IDP (Integrated Development Platform) board, revision 3.0, with a Motorola

M68EC000 processor.

• SH3-LCEVB board, revision B, with an Hitachi SH-3 HD6417780 processor.

Installation

PC platform: copy the file 13505PWR.EXE to a directory that is in the DOS path on your hard

drive.

Embedded platform: download the program 13505PWR to the system.

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Usage

PC platform: at the prompt, type

13505pwr [/software /hardware | /lcd] [/enable /disable] [/i]

[/0 | /1] [/?].

Embedded platform: execute 13505pwrand at the prompt, type the command line argument.

Where:

/software

/hardware

/lcd

selects software suspend

selects hardware suspend (PC only)

selects the LCD

/enable

/disable

activates software suspend, hardware suspend, or the LCD

deactivates software suspend, hardware suspend, or the LCD

initializes registers

GPIO1 triggers on falling edge (1->0)

GPIO1 triggers on rising edge (0->1)

displays this usage message

Note

13505PWR will automatically finish execution and return to the prompt.

13505PWR Examples

To enable software suspend mode, type the following:

13505PWR /software /enable

To disable software suspend mode, type the following:

13505PWR /software /disable

To enable hardware suspend mode, type the following:

13505PWR /hardware /enable

To disable hardware suspend mode, type the following:

13505PWR /hardware /disable

To enable the LCD, type the following:

13505PWR /lcd /enable

To disable the LCD, type the following:

13505PWR /lcd /disable

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Comments

• The /iargument is to be used when the registers have not been previously initialized.

• When using a PC with the S5U13505 evaluation board, the PC must not have more than 12M

bytes of system memory.

• GPIO1 is used to signal when the software suspend mode, hardware suspend mode, or LCD has

been enabled or disabled.

• Hardware suspend is changed by reading or writing to a memory address decoded by the PAL on

the S5U13505 evaluation board. This PAL is currently only used for PC platforms, so the

S5U13505 evaluation board does not support hardware suspend on embedded platforms.

Program Messages

ERROR: Did not detect S1D13505.

The HAL was unable to read the revision code register on the S1D13505. Ensure that the S1D13505

hardware is installed and that the hardware platform has been set up correctly.

ERROR: Unknown command line argument.

An invalid command line argument was entered. Enter a valid command line argument.

ERROR: Already selected SOFTWARE.

Command line argument /softwarewas selected more than once. Select /softwareonly once.

ERROR: Already selected HARDWARE.

Command line argument /hardwarewas selected more than once. Select /hardwareonly once.

ERROR: Already selected LCD.

Command line argument /lcdwas selected more than once. Select /lcdonly once.

ERROR: Already selected ENABLE.

Command line argument /enablewas selected more than once. Select /enableonly once.

ERROR: Already selected DISABLE.

Command line argument /disablewas selected more than once. Select /disableonly once.

ERROR: Select /software, /hardware or /lcd.

Did not select one of the following command line arguments: /software, /hardwareor /lcd.

Select /software, /hardwareor /lcd.

ERROR: Select /enable or /disable.

Neither command line argument /enableor /disablewas selected. Select /enableor

/disable.

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ERROR: Too many devices registered.

There are too many display devices attached to the HAL. The HAL currently supports only one

device.

ERROR: Could not register S1D13505F00A device.

A S1D13505 device was not found at the configured addresses. Check the configuration address

using the 13505CFG configuration program.

S1D13505

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13505PWR Software Suspend Power Sequencing Utility

Issue Date: 01/02/02

S1D13505 Embedded RAMDAC LCD/CRT Controller

Windows® CE 2.x Display Drivers

Document Number: X23A-E-001-06

Information in this document is subject to change without notice. You may download and use this document, but only for your own use in

evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any

representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain

material protected under U.S. and/or International Patent laws.

EPSON is a registered trademark of Seiko Epson Corporation. Microsoft and Windows are registered trademarks of Microsoft Corporation.

All other trademarks are the property of their respective owners.

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S1D13505

Windows® CE 2.x Display Drivers

X23A-E-001-06

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WINDOWS® CE 2.x DISPLAY DRIVERS

The Windows CE display driver is designed to support the S1D13505 Embedded

RAMDAC LCD/CRT Controller running under the Microsoft Windows CE 2.x operating

system. The driver is capable of: 4, 8 and 16 bit-per-pixel landscape modes (no rotation),

and 8 and 16 bit-per-pixel SwivelView™ 90 degree mode.

This document and the source code for the Windows CE drivers are updated as appropriate.

Before beginning any development, please check the Epson Electronics America Website

at www.eea.epson.com or the Epson Research and Development Website at

www.erd.epson.com for the latest revisions.

We appreciate your comments on our documentation. Please contact us via email at

[email protected].

Windows® CE 2.x Display Drivers

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Example Driver Builds

The following sections describe how to build the Windows CE display driver for:

1. Windows CE 2.0 using a command-line interface.

2. Windows CE Platform Builder 2.1x using a command-line interface.

In all examples “x:” refers to the drive letter where Platform Builder is installed.

Build for CEPC (X86) on Windows CE 2.0 using a Command-Line Interface

To build a Windows CE v2.0 display driver for the CEPC (X86) platform using a

S5U13505B00C evaluation board, follow the instructions below:

1. Install Microsoft Windows NT v4.0 or 2000.

2. Install Microsoft Visual C/C++ version 5.0 or 6.0.

3. Install the Microsoft Windows CE Embedded Toolkit (ETK) by running SETUP.EXE

from the ETK compact disc #1.

4. Create a new project by following the procedure documented in “Creating a New

Project Directory” from the Windows CE ETK V2.0. Alternately, use the current

“DEMO7” project included with the ETK v2.0. Follow the steps below to create a

“X86 DEMO7” shortcut on the Windows NT v4.0 desktop which uses the current

“DEMO7” project:

a. Right click on the “Start” menu on the taskbar.

b. Click on the item “Open All Users” and the “Start Menu” window will come up.

c. Click on the icon “Programs”.

d. Click on the icon “Windows CE Embedded Development Kit”.

e. Drag the icon “X86 DEMO1” onto the desktop using the right mouse button.

f. Click on “Copy Here”.

g. Rename the icon “X86 DEMO1” on the desktop to “X86 DEMO7” by right click-

ing on the icon and choosing “rename”.

h. Right click on the icon “X86 DEMO7” and click on “Properties” to bring up the

“X86 DEMO7 Properties” window.

i. Click on “Shortcut” and replace the string “DEMO1” under the entry “Target”

with “DEMO7”.

j. Click on “OK” to finish.

5. Create a sub-directory named S1D13505 under x:\wince\platform\cepc\drivers\dis-

play.

6. Copy the source code to the S1D13505 subdirectory.

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7. Edit the file x:\wince\platform\cepc\drivers\display\dirs and add S1D13505 into the

list of directories.

8. Edit the file PLATFORM.BIB (located in x:\wince\platform\cepc\files) to set the de-

fault display driver to the file EPSON.DLL (EPSON.DLL will be created during the

build in step 13).

Replace or comment out the following lines in PLATFORM.BIB:

IF CEPC_DDI_VGA2BPP

ddi.dll

ENDIF

IF CEPC_DDI_VGA8BPP

ddi.dll $(_FLATRELEASEDIR)\ddi_vga8.dll

ENDIF

$(_FLATRELEASEDIR)\ddi_vga2.dll

NK SH

IF CEPC_DDI_VGA2BPP !

IF CEPC_DDI_VGA8BPP !

ddi.dll

ENDIF

$(_FLATRELEASEDIR)\ddi_s364.dll

NK SH

ENDIF

with this line:

ddi.dll

$(_FLATRELEASEDIR)\EPSON.dll

9. The file MODE0.H (located in x:\wince\platform\cepc\drivers\display\S1D13505)

contains the register values required to set the screen resolution, color depth (bpp),

display type, active display (LCD/CRT/TV), display rotation, etc.

Before building the display driver, refer to the descriptions in the file MODE0.H for

the default settings of the driver. If the default does not match the configuration you

are building for then MODE0.H will have to be regenerated with the correct informa-

tion.

Use the program 13505CFG to generate the header file. For information on how to use

13505CFG, refer to the 13505CFG Configuration Program User Manual, document

number X23A-B-001-xx, available at www.erd.epson.com

After selecting the desired configuration, export the file as a “C Header File for

S1D13505 WinCE Drivers”. Save the new configuration as MODE0.H in

x:\wince\platform\cepc\drivers\display\S1D13505, replacing the original configura-

tion file.

10. Edit the file PLATFORM.REG to match the screen resolution, color depth (bpp), ac-

tive display (LCD/CRT/TV) and rotation information in MODE.H. PLAT-

FORM.REG is

located in x:\wince\platform\cepc\files.

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For example, the display driver section of PLATFORM.REG should be as follows

when using a 640x480 LCD panel with a color depth of 8 bpp in SwivelView 0°

(landscape) mode:

; Default for EPSON Display Driver

; 640x480 at 8 bits/pixel, LCD display, no rotation

; Useful Hex Values

; 1024=0x400, 768=0x300 640=0x280 480=0x1E0 320=140 240=0xF0

[HKEY_LOCAL_MACHINE\Drivers\Display\S1D13505]

"Width"=dword:280

"Height"=dword:1E0

"Bpp"=dword:8

“ActiveDisp”=dword:1

“Rotation”=dword:0

11. Delete all the files in the x:\wince\release directory, and delete x:\wince\plat-

form\cepc\*.bif

12. Generate the proper building environment by double-clicking on the sample project

icon (i.e. X86 DEMO7).

13. Type BLDDEMO <ENTER> at the command prompt of the X86 DEMO7 window to

generate a Windows CE image file (NK.BIN).

Build for CEPC (X86) on Windows CE Platform Builder 2.1x using a Command-Line Interface

Throughout this section 2.1x refers to either 2.11 or 2.12 as appropriate.

1. Install Microsoft Windows NT v4.0 or 2000.

2. Install Microsoft Visual C/C++ version 5.0 or 6.0.

3. Install Platform Builder 2.1x by running SETUP.EXE from compact disk #1.

4. Follow the steps below to create a “Build Epson for x86” shortcut which uses the

current “Minshell” project icon/shortcut on the Windows desktop.

a. Right click on the “Start” menu on the taskbar.

b. Click on the item “Explore”, and “Exploring -- Start Menu” window will come

up.

c. Under “x:\winnt\profiles\all users\start menu\programs\microsoft windows ce

platform builder\x86 tools”, find the icon “Build Minshell for x86”.

d. Drag the icon “Build Minshell for x86” onto the desktop using the right mouse

button.

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e. Choose “Copy Here”.

f. Rename the icon “Build Minshell for x86” to “Build Epson for x86” by right

clicking on the icon and choosing “rename”.

g. Right click on the icon “Build Epson for x86” and click on “Properties” to bring

up the “Build Epson for x86 Properties” window.

h. Click on “Shortcut” and replace the string “Minshell” under the entry “Target”

with “Epson”.

i. Click on “OK” to finish.

5. Create an EPSON project.

a. Make an Epson directory under x:\wince\public.

b. Copy MAXALL and its sub-directories (x:\wince\public\maxall) to the Epson di-

rectory.

xcopy /s /e x:\wince\public\maxall\*.* \wince\public\epson

c. Rename x:\wince\public\epson\maxall.bat to epson.bat.

d. Edit EPSON.BAT to add the following lines to the end of the file:

@echo on

set CEPC_DDI_S1D13505=1

@echo off

6. Make an S1D13505 directory under x:\wince\platform\cepc\drivers\display, and copy

the S1D13505 driver source code into x:\wince\platform\cepc\drivers\dis-

play\S1D13505.

7. Edit the file x:\wince\platform\cepc\drivers\display\dirs and add S1D13505 into the

list of directories.

8. Edit the file x:\wince\platform\cepc\files\platform.bib and make the following two

changes:

a. Insert the following text after the line “IF ODO_NODISPLAY !”:

IF CEPC_DDI_S1D13505

ddi.dll

ENDIF

b. Find the section shown below, and insert the lines as marked:

$(_FLATRELEASEDIR)\epson.dll

NK SH

IF CEPC_DDI_S1D13505 !

IF CEPC_DDI_S3VIRGE !

IF CEPC_DDI_CT655X !

IF CEPC_DDI_VGA8BPP !

Insert this line

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ddi.dll

ENDIF

$(_FLATRELEASEDIR)\ddi_s364.dll

NK SH

ENDIF

Insert this line

9. The file MODE0.H (located in x:\wince\platform\cepc\drivers\display\S1D13505)

contains the register values required to set the screen resolution, color depth (bpp),

display type, active display (LCD/CRT/TV), display rotation, etc.

Before building the display driver, refer to the descriptions in the file MODE0.H for

the default settings of the driver. If the default does not match the configuration you

are building for then MODE0.H will have to be regenerated with the correct informa-

tion.

Use the program 13505CFG to generate the header file. For information on how to use

13505CFG, refer to the 13505CFG Configuration Program User Manual, document

number X23A-B-001-xx, available at www.erd.epson.com

After selecting the desired configuration, export the file as a “C Header File for

S1D13505 WinCE Drivers”. Save the new configuration as MODE0.H in

x:\wince\platform\cepc\drivers\display\S1D13505, replacing the original configura-

tion file.

10. Edit the file PLATFORM.REG to match the screen resolution, color depth (bpp), ac-

tive display (LCD/CRT/TV) and rotation information in MODE.H. PLAT-

FORM.REG is located in x:\wince\platform\cepc\files.

For example, the display driver section of PLATFORM.REG should be as follows

when using a 640x480 LCD panel with a color depth of 8 bpp in SwivelView 0°

(landscape) mode:

; Default for EPSON Display Driver

; 640x480 at 8 bits/pixel, LCD display, no rotation

; Useful Hex Values

; 1024=0x400, 768=0x300 640=0x280 480=0x1E0 320=140 240=0xF0

[HKEY_LOCAL_MACHINE\Drivers\Display\S1D13505]

"Width"=dword:280

"Height"=dword:1E0

"Bpp"=dword:8

“ActiveDisp”=dword:1

“Rotation”=dword:0

11. Delete all the files in \wince\release directory and delete x:\wince\platform\cepc\*.bif

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12. Generate the proper building environment by double-clicking on the Epson project

icon --”Build Epson for x86”.

13. Type BLDDEMO <ENTER> at the command prompt of the “Build Epson for x86”

window to generate a Windows CE image file (NK.BIN).

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Installation for CEPC Environment

Once the NK.BIN file is built, the CEPC environment can be started by booting either from a

floppy or hard drive configured with a Windows 9x operating system. The two methods are

described below.

1. To start CEPC after booting from a floppy drive:

a. Create a bootable floppy disk.

b. Edit CONFIG.SYS on the floppy disk to contain only the following line:

device=a:\himem.sys

c. Edit AUTOEXEC.BAT on the floppy disk to contain the following lines:

mode com1:9600,n,8,1

loadcepc /B:9600 /C:1 c:\nk.bin

d. Copy LOADCEPC.EXE and HIMEM.SYS to the bootable floppy disk. Search for

the loadCEPC utility in your Windows CE directories.

e. Copy NK.BIN to c:\.

f. Boot the system from the bootable floppy disk.

2. To start CEPC after booting from a hard drive:

a. Copy LOADCEPC.EXE to C:\. Search for the loadCEPC utility in your Windows

CE directories.

b. Edit CONFIG.SYS on the hard drive to contain only the following line:

device=c:\himem.sys

c. Edit AUTOEXEC.BAT on the hard drive to contain the following lines:

mode com1:9600,n,8,1

loadcepc /B:9600 /C:1 c:\nk.bin

d. Copy NK.BIN and HIMEM.SYS to c:\.

e. Boot the system.

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Configuration

There are several issues to consider when configuring the display driver. The issues cover

debugging support, register initialization values and memory allocation. Each of these

issues is discussed in the following sections.

Compile Switches

There are several switches, specific to the S1D13505 display driver, which affect the

display driver.

The switches are added or removed from the compile options in the file SOURCES.

WINCEVER

This option is automatically set to the numerical version of WinCE for version 2.12 or later.

If the environment variable, _WINCEOSVER is not defined, then WINCEVER will

default 2.11. The display driver may test against this option to support different WinCE

version-specific features.

EpsonMessages

This debugging option enables the display of EPSON-specific debug messages. These

debug message are sent to the serial debugging port. This option should be disabled unless

you are debugging the display driver, as they will significantly impact the performance of

the display driver.

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Mode File

A second variable which will affect the finished display driver is the register configurations

contained in the mode file.

The MODE tables (contained in files MODE0.H, MODE1.H, MODE2.H . . .) contain

generated by the configuration program 13505CFG.EXE. The display driver comes with

example MODE tables.

By default, only MODE0.H is used by the display driver. New mode tables can be created

using the 13505CFG program. Edit the #include section of MODE.H to add the new mode

table.

If you only support a single display mode, you do not need to add any information to the

WinCE registry. If, however, you support more that one display mode, you should create

registry values (see below) that will establish the initial display mode. If your display driver

contains multiple mode tables, and if you do not add any registry values, the display driver

will default to the first mode table in your list.

To select which display mode the display driver should use upon boot, add the following

lines to your PLATFORM.REG file:

[HKEY_LOCAL_MACHINE\Drivers\Display\S1D13505]

“Width”=dword:280

“Height”=dword:1E0

“Bpp”=dword:8

“Rotation”=dword:0

“RefreshRate”=dword:3C

“Flags”=dword:2

Note that all dword values are in hexadecimal, therefore 280h = 640, 1E0h = 480, and 3Ch

= 60. The value for “Flags” should be 1 (LCD), 2 (CRT), or 3 (both LCD and CRT). When

the display driver starts, it will read these values in the registry and attempt to match a mode

table against them. All values must be present and valid for a match to occur, otherwise the

display driver will default to the FIRST mode table in your list.

A WinCE desktop application (or control panel applet) can change these registry values,

and the display driver will select a different mode upon warmboot. This allows the display

driver to support different display configurations and/or orientations. An example appli-

cation that controls these registry values will be made available upon the next release of the

display driver; preliminary alpha code is available by special request.

S1D13505

Windows® CE 2.x Display Drivers

X23A-E-001-06

Issue Date: 01/05/25

Epson Research and Development

Page 13

Vancouver Design Center

Comments

• The display driver is CPU independent, allowing use of the driver for several Windows

CE Platform Builder supported platforms.

• When using 13505CFG.EXE to produce multiple MODE tables, make sure you change

the Mode Number in the WinCE tab for each mode table you generate. The display

driver supports multiple mode tables, but only if each mode table has a unique mode

number.

• At this time, the drivers have been tested on the x86 CPUs and have been run with

version 2.0 of the ETK, Platform Builder v2.1x.

Windows® CE 2.x Display Drivers

Issue Date: 01/05/25

S1D13505

X23A-E-001-06

Page 14

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S1D13505

Windows® CE 2.x Display Drivers

X23A-E-001-06

Issue Date: 01/05/25

S1D13505 Embedded RAMDAC LCD/CRT Controller

Wind River WindML v2.0 Display

Drivers

Document Number: X23A-E-002-03

Information in this document is subject to change without notice. You may download and use this document, but only for your own use in

evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any

representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain

material protected under U.S. and/or International Patent laws.

EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.

Page 2

Epson Research and Development

Vancouver Design Center

THIS PAGE LEFT BLANK

S1D13505

X23A-E-002-03

Wind River WindML v2.0 Display Drivers

Issue Date: 01/04/06

Epson Research and Development

Page 3

Vancouver Design Center

Wind River WindML v2.0 DISPLAY DRIVERS

The Wind River WindML v2.0 display drivers for the S1D13505 Embedded RAMDAC

LCD/CRT Controller are intended as “reference” source code for OEMs developing for

Wind River’s WindML v2.0. The driver package provides support for both 8 and 16 bit-

per-pixel color depths. The source code is written for portability and contains functionality

for most features of the S1D13505. Source code modification is required to provide a

smaller, more efficient driver for mass production (e.g. CRT support may be removed for

products not requiring a CRT).

The WindML display drivers are designed around a common configuration include file

called mode0.h which is generated by the configuration utility 13505CFG. This design

allows for easy customization of display type, clocks, decode addresses, rotation, etc. by

OEMs. For further information on 13505CFG, see the 13505CFG Configuration Program

User Manual, document number X23A-B-001-xx.

Note

The WindML display drivers are provided as “reference” source code only. They are in-

tended to provide a basis for OEMs to develop their own drivers for WindML v2.0.

These drivers are not backwards compatible with UGL v1.2. For information on the

UGL v1.2 display drivers, see Wind River UGL v1.2 Display Drivers, document number

X23A-E-003-xx.

This document and the source code for the WindML display drivers is updated as appro-

priate. Please check the Epson Electronics America website at http://www.eea.epson.com

or the Epson Research and Development website at http://www.erd.epson.com for the latest

revisions before beginning any development.

We appreciate your comments on our documentation. Please contact us via email at

[email protected].

Wind River WindML v2.0 Display Drivers

Issue Date: 01/04/06

S1D13505

X23A-E-002-03

Page 4

Epson Research and Development

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Building a WindML v2.0 Display Driver

The following instructions produce a bootable disk that automatically starts the UGL demo

program. These instructions assume that Wind River’s Tornado platform is already

installed.

Note

For the example steps where the drive letter is given as “x:”. Substitute “x” with the

drive letter that your development environment is on.

1. Create a working directory and unzip the WindML display driver into it.

From a command prompt or GUI interface create a new directory (e.g. x:\13505).

Unzip the file 13505windml.zip to the newly created working directory. The files will

be unzipped to the directories “x:\13505\8bpp” and “x:\13505\16bpp”.

2. Configure for the target execution model.

This example build creates a VxWorks image that fits onto and boots from a single

floppy diskette. In order for the VxWorks image to fit on the disk certain modifica-

tions are required.

Replace the file “x:\Tornado\target\config\pcPentium\config.h” with the file

“x:\13505\8bpp\File\config.h” (or “x:\13505\16bpp\File\config.h”). The new config.h

file removes networking components and configures the build image for booting from

a floppy disk.

Note

Rather than simply replacing the original config.h file, rename it so the file can be kept

for reference purposes.

3. Build a boot ROM image.

From the Tornado tool bar, select Build -> Build Boot ROM. Select “pcPentium” as

the BSP and “bootrom_uncmp” as the image.

4. Create a bootable disk (in drive A:).

From a command prompt change to the directory “x:\Tornado\host\x86-win32\bin”

and run the batch file torvars.bat. Next, change to the directory “x:\Tornado\tar-

get\config\pcPentium” and type:

mkboot a: bootrom_uncmp

5. If necessary, generate a new mode0.h configuration file.

The file mode0.h contains the register values required to set the screen resolution, col-

or depth (bpp), display type, active display (LCD/CRT), rotation, etc. The mode0.h

file included with the drivers, may not contain applicable values and must be regener-

ated. The configuration program 13505CFG can be used to build a new mode0.h file.

If building for 8 bpp, place the new mode0.h file in the directory

“x:\13505\8bpp\File”. If building for 16 bpp, place the new mode0.h file in

“x:\13505\16bpp\File”.

S1D13505

X23A-E-002-03

Wind River WindML v2.0 Display Drivers

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Page 5

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Note

Mode0.h should be created using the configuration utility 13505CFG. For more infor-

mation on 13505CFG, see the 13505CFG Configuration Program User Manual, docu-

ment number X23A-B-001-xx available at www.erd.epson.com.

6. Build the WindML v2.0 library.

From a command prompt change to the directory “x:\Tornado\host\x86-win32\bin”

and run the batch file torvars.bat. Next, change to the directory “x:\Tornado\tar-

get\src\ugl” and type the command:

make CPU=PENTIUM ugl

7. Open the S1D13505 workspace.

From the Tornado tool bar, select File->Open Workspace...->Existing->Browse... and

select the file “x:\13505\8bpp\13505.wsp” (or “x:\13505\16bpp\13505.wsp”).

8. Add support for single line comments.

The WindML v2.0 display driver source code uses single line comment notation, “//”,

rather than the ANSI conventional comments, “/*...*/”.

To add support for single line comments follow these steps:

a. In the Tornado “Workspace Views” window, click on the “Builds” tab.

b. Expand the “8bpp Builds” (or “16bpp Builds”) view by clicking on the “+”

next to it. The expanded view will contain the item “default”. Right-click on

“default” and select “Properties...”. A “Properties:” window will appear.

c. Select the “C/C++ compiler” tab to display the command switches used in

the build. Remove the “-ansi” switch from the line that contains “-g -mpen-

tium -ansi -nostdinc -DRW_MULTI_THREAD”.

(Refer to GNU ToolKit user's guide for details)

9. Compile the VxWorks image.

Select the “Builds” tab in the Tornado “Workspace Views” window.

Right-click on “8bpp files” (or “16bpp files”) and select “Dependencies...”. Click on

“OK” to regenerate project file dependencies for “All Project files”.

Right-click on “8bpp files” (or “16bpp files”) and select “ReBuild All(vxWorks)” to

build VxWorks.

10. Copy the VxWorks file to the diskette.

From a command prompt or through the Windows interface, copy the file

“x:\13505\8bpp\default\vxWorks” (or “x:\13505\16bpp\default\vxWorks”) to the

bootable disk created in step 4.

11. Start the VxWorks demo.

Boot the target PC with the VxWorks bootable diskette to run the UGLDEMO auto-

matically.

Wind River WindML v2.0 Display Drivers

Issue Date: 01/04/06

S1D13505

X23A-E-002-03

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S1D13505

X23A-E-002-03

Wind River WindML v2.0 Display Drivers

Issue Date: 01/04/06

S1D13505 Embedded RAMDAC LCD/CRT Controller

Wind River UGL v1.2 Display Drivers

Document Number: X23A-E-003-02

Information in this document is subject to change without notice. You may download and use this document, but only for your own use in

evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any

representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain

material protected under U.S. and/or International Patent laws.

EPSON is a registered trademark of Seiko Epson Corporation. Microsoft and Windows are registered trademarks of Microsoft Corporation.

All other trademarks are the property of their respective owners.

Page 2

Epson Research and Development

Vancouver Design Center

THIS PAGE LEFT BLANK

S1D13505

X23A-E-003-02

Wind River UGL v1.2 Display Drivers

Issue Date: 01/02/05

Epson Research and Development

Page 3

Vancouver Design Center

Wind River UGL v1.2 Display Drivers

The Wind River UGL v1.2 display drivers for the S1D13505 Embedded RAMDAC

LCD/CRT Controller are intended as “reference” source code for OEMs developing for

Wind River’s UGL v1.2. The drivers provide support for both 8 and 16 bit-per-pixel color

depths. The source code is written for portability and contains functionality for most

features of the S1D13505. Source code modification is required to provide a smaller, more

efficient driver for mass production.

The UGL display drivers are designed around a common configuration include file called

mode0.h which is generated by the configuration utility 13505CFG. This design allows for

easy customization of display type, clocks, addresses, rotation, etc. by OEMs. For further

information on 13505CFG, see the 13505CFG Configuration Program User Manual,

document number X23A-B-001-xx.

This document and the source code for the UGL display drivers are updated as appropriate.

Please check the Epson Electronics America website at http://www.eea.epson.com or the

Epson Research and Development website at http://www.erd.epson.com for the latest

revisions before beginning any development.

We appreciate your comments on our documentation. Please contact us via e-mail at

[email protected].

Wind River UGL v1.2 Display Drivers

Issue Date: 01/02/05

S1D13505

X23A-E-003-02

Page 4

Epson Research and Development

Vancouver Design Center

Building a UGL v1.2 Display Driver

The following instructions produce a bootable disk that automatically starts the UGL demo

software. These instructions assume that the Wind River Tornado platform is correctly

installed.

Note

For the example steps where the drive letter is given as “x:”. Substitute “x” with the

drive letter your development environment is on.

1. Create a working directory and unzip the UGL display driver into it.

Using a command prompt or GUI interface create a new directory (e.g. x:\13505).

Unzip the file 13505ugl.zip to newly created working directory. The files will be un-

zipped to the directories “x:\13505\8bpp” and “x:\13505\16bpp”.

2. Configure for the target execution model.

This example build creates a VxWorks image fits onto and boots from a single floppy

diskette. In order for the VxWorks image to fit on the disk certain modifications are

required.

Replace the file “x:\Tornado\target\config\pcPentium\config.h” with the file

“x:\13505\8bpp\File\config.h” (or “x:\13505\16bpp\File\config.h”). The new config.h

file removes networking components and configures the build image for booting from

a floppy disk.

Note

Rather than simply replacing the original config.h file, rename it so the file can be kept

for reference purposes.

3. Build a boot ROM image.

From the Tornado tool bar, select Build -> Build Boot ROM. Select “pcPentium” as

the BSP and “bootrom_uncmp” as the image.

4. Create a bootable disk (in drive A:).

From a command prompt in the directory “x:\Tornado\target\config\pcPentium” type

mkboot a: bootrom_uncmp

5. If necessary, generate a new mode0.h configuration file.

The file mode0.h contains the register values required to set the screen resolution, col-

or depth (bpp), display type, active display (LCD/CRT), rotation, etc. The mode0.h,

included with the drivers, sets the display for 640x480 60 Hz output to a CRT display.

If this setting is inappropriate then mode0.h must be regenerated. The configuration

program 13505CFG can be used to build a new mode0.h file. If building for 8 bpp,

place the new mode0.h file in “x:\13505\8bpp\File”. If building for 16 bpp, place the

new mode0.h file in “x:\13505\16bpp\File”.

S1D13505

X23A-E-003-02

Wind River UGL v1.2 Display Drivers

Issue Date: 01/02/05

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Page 5

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Note

Mode0.h should be created using the configuration utility 13505CFG. For more infor-

mation on 13505CFG, see the 13505CFG Configuration Program User Manual, docu-

ment number X23A-B-001-xx available at www.erd.epson.com.

6. Open the S1D13505 workspace.

From the Tornado tool bar, select File->Open Workspace...->Existing->Browse... and

select the file “x:\13505\8bpp\13505.wsp” (or “x:\13505\16bpp\13505.wsp”).

7. Add support for single line comments.

The UGL v1.2 display driver source code uses single line comment notation, “//”,

rather than the ANSI conventional comments, “/* . . . */”.

To add support for single line comments follow these steps:

a. In the Tornado “Workspace” window, click on the “Builds” tab.

b. Expand the “8bpp Builds” (or “16bpp Builds”) view by clicking on

the “+” next to it. The expanded view will contain the item “default”.

Right-click on “default” and select “Properties...”. A properties win-

dow will appear.

c. Select the “C/C++ compiler” tab to display the command switches

used in the build. Remove the “-ansi” switch from the line that con-

tains “-g -mpentium -ansi -nostdinc -DRW_MULTI_THREAD”.

(Refer to GNU ToolKit user's guide for details)

8. Compile the VxWorks image.

Select the “Files” tab in the Tornado “Workspace” window.

Right-click on “8bpp files” (or “16bpp files”) and select “Dependencies...”. Click on

“OK” to regenerate project file dependencies for “All Project files”.

Right-click on “8bpp files” and select “ReBuild All(vxWorks)” to build VxWorks.

9. Copy the VxWorks file to the diskette.

From a command prompt or through the Windows interface, copy the file

“x:\13505\8bpp\default\vxWorks” (or “x:\13505\16bpp\default\vxWorks”) to the

bootable disk created in step 4.

10. Start the VxWorks demo.

Boot the target PC with the VxWorks bootable diskette to run the UGLDEMO auto-

matically.

Wind River UGL v1.2 Display Drivers

Issue Date: 01/02/05

S1D13505

X23A-E-003-02

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S1D13505

X23A-E-003-02

Wind River UGL v1.2 Display Drivers

Issue Date: 01/02/05

S1D13505 Embedded RAMDAC LCD/CRT Controller

Windows® CE 3.x Display Drivers

Document Number: X23A-E-006-01

Information in this document is subject to change without notice. You may download and use this document, but only for your own use in

evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any

representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain

material protected under U.S. and/or International Patent laws.

EPSON is a registered trademark of Seiko Epson Corporation. Microsoft and Windows are registered trademarks of Microsoft Corporation.

All other trademarks are the property of their respective owners.

Page 2

Epson Research and Development

Vancouver Design Center

THIS PAGE LEFT BLANK

S1D13505

Windows® CE 3.x Display Drivers

X23A-E-006-01

Issue Date: 01/05/17

Epson Research and Development

Page 3

Vancouver Design Center

WINDOWS® CE 3.x DISPLAY DRIVERS

The Windows CE 3.x display driver is designed to support the S1D13505 Embedded

RAMDAC LCD/CRT Controller running the Microsoft Windows CE operating system,

version 3.0. The driver is capable of: 4, 8 and 16 bit-per-pixel landscape modes (no

rotation), and 8 and 16 bit-per-pixel SwivelView™ 90 degree mode.

This document and the source code for the Windows CE drivers are updated as appropriate.

Before beginning any development, please check the Epson Electronics America Website

at www.eea.epson.com or the Epson Research and Development Website at

www.erd.epson.com for the latest revisions.

We appreciate your comments on our documentation. Please contact us via email at

[email protected].

Windows® CE 3.x Display Drivers

Issue Date: 01/05/17

S1D13505

X23A-E-006-01

Page 4

Epson Research and Development

Vancouver Design Center

Example Driver Builds

The following sections describe how to build the Windows CE display driver for:

1. Windows CE Platform Builder 3.00 using the GUI interface.

2. Windows CE Platform Builder 3.00 using the command-line interface.

In all examples “x:” refers to the drive letter where Platform Builder is installed.

Build for CEPC (X86) on Windows CE Platform Builder 3.00 using the GUI Interface

1. Install Microsoft Windows 2000 Professional, or Windows NT Workstation version

4.0 with Service Pack 5 or later.

2. Install Windows CE Platform Builder 3.00.

3. Start Platform Builder by double-clicking on the Microsoft Windows CE Platform

Builder icon.

4. Create a new project.

a. Select File | New.

b. In the dialog box, select the Platforms tab.

c. In the platforms dialog box, select “WCE Platform”, set a location for the project

(such as x:\myproject), set the platform name (such as myplatform), and set the

Processors to “Win32 (WCE x86)”.

d. Click the OK button.

e. In the dialog box “WCE Platform - Step 1 of 2”, select CEPC.

f. Click the Next button.

g. In the dialog box “WCE Platform - Step 2 of 2”, select Minimal OS (Minkern).

h. Click the Finish button.

i. In the dialog box “New Platform Information”, click the OK button.

5. Set the active configuration to “Win32 (WCE x86) Release”.

a. From the Build menu, select “Set Active Configuration”.

b. Select “MYPLATFORM - Win32 (WCE x86) Release”.

c. Click the OK button.

6. Add the environment variable CEPC_DDI_S1D13X0X.

a. From the Platform menu, select “Settings”.

b. Select the “Environment” tab.

c. In the Variable box, type “CEPC_DDI_S1D13X0X”.

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d. In the Value box, type “1”.

e. Click the Set button.

f. Click the OK button.

7. Create a new directory S1D13505, under x:\wince300\platform\cepc\drivers\display,

and copy the S1D13505 driver source code into this new directory.

8. Add the S1D13505 driver component.

a. From the Platform menu, select “Insert | User Component”.

b. Set “Files of type:” to “All Files (*.*)”.

c. Select the file x:\wince300\platform\cepc\drivers\display\S1D13505\sources.

d. In the “User Component Target File” dialog box, select browse and then select the

path and the file name of “sources”.

9. Delete the component “ddi_flat”.

a. In the Workspace window, select the ComponentView tab.

b. Show the tree for MYPLATFORM components by clicking on the ‘+’ sign at the

root of the tree.

c. Right-click on the ddi_flat component.

d. Select “Delete”.

e. From the File menu, select “Save Workspace”.

10. From the Workspace window, click on ParameterView Tab. Show the tree for MY-

PLATFORM Parameters by clicking on the ‘+’ sign at the root of the tree. Expand the

the WINCE300 tree and then click on “Hardware Specific Files” and then double

click on “PLATFORM.BIB”. Edit the file the PLATFORM.BIB file and make the fol-

lowing two changes:

a. Insert the following text after the line “IF ODO_NODISPLAY !”:

IF CEPC_DDI_S1D13X0X

ddi.dll $(_FLATRELEASEDIR)\S1D13X0X.dll NK SH

ENDIF

b. Find the section shown below, and insert the lines as marked:

IF CEPC_DDI_FLAT !

IF CEPC_DDI_S1D13X0X!

IF CEPC_DDI_S3VIRGE !

IF CEPC_DDI_CT655X !

IF CEPC_DDI_VGA8BPP !

IF CEPC_DDI_S3TRIO64 !

IF CEPC_DDI_ATI !

;Insert this line

Windows® CE 3.x Display Drivers

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ddi.dll $(_FLATRELEASEDIR)\ddi_flat.dll

NK SH

ENDIF

;Insert this line

11. Modify MODE0.H.

The file MODE0.H (located in x:\wince300\platform\cepc\drivers\display\S1D13505)

contains the register values required to set the screen resolution, color depth (bpp),

display type, active display (LCD/CRT/TV), display rotation, etc.

Before building the display driver, refer to the descriptions in the file MODE0.H for

the default settings of the console driver. If the default does not match the configura-

tion you are building for then MODE0.H will have to be regenerated with the correct

information.

Use the program 13505CFG to generate the header file. For information on how to use

13505CFG, refer to the 13505CFG Configuration Program User Manual, document

number X23A-B-001-xx, available at www.erd.epson.com

After selecting the desired configuration, export the file as a “C Header File for

S1D13505 WinCE Drivers”. Save the new configuration as MODE0.H in the

\wince300\platform\cepc\drivers\display, replacing the original configuration file.

12. From the Platform window, click on ParameterView Tab. Show the tree for MY-

PLATFORM Parameters by clicking on the ‘+’ sign at the root of the tree. Expand the

the WINCE300 tree and click on “Hardware Specific Files”, then double click on

“PLATFORM.REG”. Edit the file PLATFORM.REG to match the screen resolution,

color depth, and rotation information in MODE.H.

For example, the display driver section of PLATFORM.REG should be as follows

when using a 640x480 LCD panel with a color depth of 8 bpp and a SwivelView

mode of 0° (landscape):

; Default for EPSON Display Driver

; 640x480 at 8 bits/pixel, LCD display, no rotation

; Useful Hex Values

; 1024=0x400, 768=0x300 640=0x280 480=0x1E0 320=140 240=0xF0

[HKEY_LOCAL_MACHINE\Drivers\Display\S1D13505]

“Width”=dword:280

“Height”=dword:1E0

“Bpp”=dword:8

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“ActiveDisp”=dword:1

“Rotation”=dword:0

13. From the Build menu, select “Rebuild Platform” to generate a Windows CE image file

(NK.BIN) in the project directory

x:\myproject\myplatform\reldir\x86_release\nk.bin.

Build for CEPC (X86) on Windows CE Platform Builder 3.00 using the Command-Line Interface

1. Install Microsoft Windows 2000 Professional, or Windows NT Workstation version

4.0 with Service Pack 5 or later.

2. Install Windows CE Platform Builder 3.00.

3. Create a batch file called x:\wince300\cepath.bat. Put the following in cepath.bat:

cd \wince300\public\common\oak\misc

call wince x86 i486 CE MINSHELL CEPC

set IMGNODEBUGGER=1

set WINCEREL=1

set CEPC_DDI_S1D13X0X=1

4. Generate the build environment by calling cepath.bat.

5. Create a new folder called S1D13505 under x:\wince300\platform\cepc\drivers\dis-

play, and copy the S1D13505 driver source code into x:\wince300\platform\cepc\driv-

ers\display\S1D13505.

6. Edit the file x:\wince300\platform\cepc\drivers\display\dirs and add S1D13505 into

the list of directories.

7. Edit the file x:\wince300\platform\cepc\files\platform.bib and make the following two

changes:

a. Insert the following text after the line “IF ODO_NODISPLAY !”:

IF CEPC_DDI_S1D13X0X

ddi.dll $(_FLATRELEASEDIR)\S1D13X0X.dll NK SH

ENDIF

b. Find the section shown below, and insert the lines as marked:

IF CEPC_DDI_FLAT !

IF CEPC_DDI_S1D13X0X!

IF CEPC_DDI_S3VIRGE !

IF CEPC_DDI_CT655X !

IF CEPC_DDI_VGA8BPP !

IF CEPC_DDI_S3TRIO64 !

IF CEPC_DDI_ATI !

;Insert this line

Windows® CE 3.x Display Drivers

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ddi.dll $(_FLATRELEASEDIR)\ddi_flat.dll

NK SH

ENDIF

;Insert this line

8. Modify MODE0.H.

The file MODE0.H (located in x:\wince300\platform\cepc\drivers\display\S1D13505)

contains the register values required to set the screen resolution, color depth (bpp),

display type, active display (LCD/CRT/TV), display rotation, etc.

Before building the display driver, refer to the descriptions in the file MODE0.H for

the default settings of the display driver. If the default does not match the configura-

tion you are building for then MODE0.H will have to be regenerated with the correct

information.

Use the program 13505CFG to generate the header file. For information on how to use

13505CFG, refer to the 13505CFG Configuration Program User Manual, document

number X23A-B-001-xx, available at www.erd.epson.com

After selecting the desired configuration, export the file as a “C Header File for

S1D13505 WinCE Drivers”. Save the new configuration as MODE0.H in the

\wince300\platform\cepc\drivers\display, replacing the original configuration file.

9. Edit the file PLATFORM.REG to match the screen resolution, color depth, and rota-

tion information in MODE.H. PLATFORM.REG is located in x:\wince300\plat-

form\cepc\files.

For example, the display driver section of PLATFORM.REG should be as follows

when using a 640x480 LCD panel with a color depth of 8 bpp and a SwivelView

mode of 0° (landscape):

; Default for EPSON Display Driver

; 640x480 at 8 bits/pixel, LCD display, no rotation

; Useful Hex Values

; 1024=0x400, 768=0x300 640=0x280 480=0x1E0 320=140 240=0xF0

[HKEY_LOCAL_MACHINE\Drivers\Display\S1D13505]

“Width”=dword:280

“Height”=dword:1E0

“Bpp”=dword:8

“ActiveDisp”=dword:1

“Rotation”=dword:0

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10. Delete all the files in the x:\wince300\release directory and delete the file

x:\wince300\platform\cepc\*.bif

11. Type BLDDEMO <ENTER> at the command prompt to generate a Windows CE image

file. The file generated will be x:\wince300\release\nk.bin.

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Installation for CEPC Environment

Once the NK.BIN file is built, the CEPC environment can be started by booting either from a

floppy or hard drive configured with a Windows 9x operating system. The two methods are

described below.

1. To start CEPC after booting from a floppy drive:

a. Create a bootable floppy disk.

b. Edit CONFIG.SYS on the floppy disk to contain only the following line:

device=a:\himem.sys

c. Edit AUTOEXEC.BAT on the floppy disk to contain the following lines:

mode com1:9600,n,8,1

loadcepc /B:9600 /C:1 c:\nk.bin

d. Copy LOADCEPC.EXE and HIMEM.SYS to the bootable floppy disk. Search for

the loadCEPC utility in your Windows CE directories.

e. Copy NK.BIN to c:\.

f. Boot the system from the bootable floppy disk.

2. To start CEPC after booting from a hard drive:

a. Copy LOADCEPC.EXE to C:\. Search for the loadCEPC utility in your Windows

CE directories.

b. Edit CONFIG.SYS on the hard drive to contain only the following line:

device=c:\himem.sys

c. Edit AUTOEXEC.BAT on the hard drive to contain the following lines:

mode com1:9600,n,8,1

loadcepc /B:9600 /C:1 c:\nk.bin

d. Copy NK.BIN and HIMEM.SYS to c:\.

e. Boot the system.

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Configuration

There are several issues to consider when configuring the display driver. The issues cover

debugging support, register initialization values and memory allocation. Each of these

issues is discussed in the following sections.

Compile Switches

There are several switches, specific to the S1D13505 display driver, which affect the

display driver.

The switches are added or removed from the compile options in the file SOURCES.

WINCEVER

This option is automatically set to the numerical version of WinCE for version 2.12 or later.

If the environment variable, _WINCEOSVER is not defined, then WINCEVER will

default 2.11. The S1D display driver may test against this option to support different

WinCE version-specific features.

EnablePreferVmem

This option enables the use of off-screen video memory. When this option is enabled,

WinCE can optimize some BLT operations by using off-screen video memory to store

images. You may need to disable this option for systems with 512K bytes of video memory

and VGA (640x480) panels.

ENABLE_ANTIALIASED_FONTS

This option enables the display driver support of antialiased fonts in WinCE. Fonts created

with the ANTIALIASED_QUALITY attribute will be drawn with font smoothing.

If you want all fonts to be antialiased by default, add the following line to

PLATFORM.REG: [HKEY_LOCAL_MACHINE\SYSTEM\GDI\Fontsmoothing]. This

registry option causes WinCE to draw all fonts with smoothing.

Font smoothing is only applicable to 16bpp mode.

EpsonMessages

This debugging option enables the display of EPSON-specific debug messages. These

debug message are sent to the serial debugging port. This option should be disabled unless

you are debugging the display driver, as they will significantly impact the performance of

the display driver.

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DEBUG_MONITOR

This option enables the use of the debug monitor. The debug monitor can be invoked when

the display driver is first loaded and can be used to view registers, and perform a few

debugging tasks. The debug monitor is still under development and is UNTESTED.

This option should remain disabled unless you are performing specific debugging tasks that

require the debug monitor.

GrayPalette

This option is intended for the support of monochrome panels only.

The option causes palette colors to be grayscaled for correct display on a mono panel. For

use with color panels this option should not be enabled.

Mode File

The MODE tables (contained in files MODE0.H, MODE1.H, MODE2.H . . .) contain

generated by the configuration program 13505CFG.EXE. The display driver comes with

example MODE tables.

By default, only MODE0.H is used by the display driver. New mode tables can be created

using the 13505CFG program. Edit the #include section of MODE.H to add the new mode

table.

If you only support a single display mode, you do not need to add any information to the

WinCE registry. If, however, you support more that one display mode, you should create

registry values (see below) that will establish the initial display mode. If your display driver

contains multiple mode tables, and if you do not add any registry values, the display driver

will default to the first mode table in your list.

To select which display mode the display driver should use upon boot, add the following

lines to your PLATFORM.REG file:

[HKEY_LOCAL_MACHINE\Drivers\Display\S1D13505]

“Width”=dword:280

“Height”=dword:1E0

“Bpp”=dword:8

“Rotation”=dword:0

“RefreshRate”=dword:3C

“Flags”=dword:2

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Note that all dword values are in hexadecimal, therefore 280h = 640, 1E0h = 480, and 3Ch

= 60. The value for “Flags” should be 1 (LCD), 2 (CRT), or 3 (both LCD and CRT). When

the display driver starts, it will read these values in the registry and attempt to match a mode

table against them. All values must be present and valid for a match to occur, otherwise the

display driver will default to the first mode table in your list.

A WinCE desktop application (or control panel applet) can change these registry values,

and the display driver will select a different mode upon warmboot. This allows the display

driver to support different display configurations and/or orientations. An example appli-

cation that controls these registry values will be made available upon the next release of the

display driver; preliminary alpha code is available by special request.

Resource Management Issues

The Windows CE 3.0 OEM must deal with certain display driver issues relevant to

Windows CE 3.0. These issues require the OEM balance factors such as: system vs. display

memory utilization, video performance, and power off capabilities.

The section “Simple Display Driver Configuration ” on page 15 provides a configuration

which should work with most Windows CE platforms. This section is only intended as a

means of getting started. Once the developer has a functional system, it is recommended to

optimize the display driver configuration as described below in “Description of Windows

CE Display Driver Issues”.

Description of Windows CE Display Driver Issues

The following are some issues to consider when configuring the display driver to work with

Windows CE:

1. When Windows CE enters the Suspend state (power-off), the LCD controller and dis-

play memory may lose power, depending on how the system is designed. If display

memory loses power, all images stored in display memory are lost.

If power-off/power-on features are required, the OEM has several options:

•

If display memory power is turned off, add code to the display driver to save any

images in display memory to system memory before power-off, and add code to

restore these images after power-on.

If display memory power is turned off, instruct Windows CE to redraw all images

upon power-on. Unfortunately it is not possible to instruct Windows CE to redraw

any off-screen images, such as icons, slider bars, etc., so in this case the OEM

must also configure the display driver to never use off-screen memory.

•

Ensure that display memory never loses power.

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2. Using off-screen display memory significantly improves display performance. For ex-

ample, slider bars appear more smooth when using off-screen memory. To enable or

disable the use of off-screen memory, edit the file: x:\wince300\platform\cepc\driv-

ers\display\S1D13505\sources. In SOURCES, there is a line which, when uncom-

mented, will instruct Windows CE to use off-screen display memory (if sufficient

display memory is available):

CDEFINES=$(CDEFINES) -DEnablePreferVmem

3. In the file PROJECT.REG under CE 3.0, there is a key called PORepaint (search the

Windows CE directories for PROJECT.REG). PORepaint is relevant when the Sus-

pend state is entered or exited. PORepaint can be set to 0, 1, or 2 as described below:

a. PORepaint=0

•

This mode tells Windows CE not to save or restore display memory on sus-

pend or resume.

•

Since display data is not saved and not repainted, this is the FASTEST mode.

Main display data in display memory must NOT be corrupted or lost on sus-

pend. The memory clock must remain running.

•

Off-screen data in display memory must NOT be corrupted or lost on sus-

pend. The memory clock must remain running.

•

This mode cannot be used if power to the display memory is turned off.

b. PORepaint=1

•

This is the default mode for Windows CE.

This mode tells Windows CE to save the main display data to the system

memory on suspend.

•

This mode is used if display memory power is going to be turned off when the

system is suspended, and there is enough system memory to save the image.

Any off-screen data in display memory is LOST when suspended. Therefore

off-screen memory usage must either be disabled in the display driver (i.e:

EnablePreferVmem not defined in SOURCES file), or new OEM-specific

code must be added to the display driver to save off-screen data to system

memory when the system is suspended, and restored when resumed.

•

If off-screen data is used (provided that the OEM has provided code to save

off-screen data when the system suspends), additional code must be added to

the display driver’s surface allocation routine to prevent the display driver

from allocating the “main memory save region” in display memory. When

WinCE OS attempts to allocate a buffer to save the main display data, WinCE

OS marks the allocation request as preferring display memory. We believe

this is incorrect. Code must be added to prevent this specific allocation from

being allocated in display memory - it MUST be allocated from system mem-

ory.

•

Since the main display data is copied to system memory on suspend, and then

simply copied back on resume, this mode is FAST, but not as fast as mode 0.

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c. PORepaint=2

•

This mode tells WinCE to not save the main display data on suspend, and

causes WinCE to REPAINT the main display on resume.

•

This mode is used if display memory power is going to be turned off when the

system is suspended, and there is not enough system memory to save the im-

age.

•

Any off-screen data in display memory is LOST, and since there is insuffi-

cient system memory to save display data, off-screen memory usage MUST

be disabled.

•

When the system is resumed, WinCE instructs all running applications to re-

paint themselves. This is the SLOWEST of the three modes.

Simple Display Driver Configuration

The following display driver configuration should work with most platforms running

Windows CE. This configuration disables the use of off-screen display memory and forces

the system to redraw the main display upon power-on.

1. This step disables the use of off-screen display memory.

Edit the file x:\wince300\platform\cepc\drivers\display\S1D13505\sources and

change the line

CDEFINES=$(CDEFINES) -DEnablePreferVmem

#CDEFINES=$(CDEFINES) -DEnablePreferVmem

2. This step causes the system to redraw the main display upon power-on. This step is

only required if display memory loses power when Windows CE is shut down. If dis-

play memory is kept powered up (set the S1D13505 in powersave mode), then the dis-

play data will be maintained and this step can be skipped.

Search for the file PROJECT.REG in your Windows CE directories, and inside

PROJECT.REG find the key PORepaint. Change PORepaint as follows:

“PORepaint”=dword:2

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Comments

• The display driver is CPU independent, allowing use of the driver for several Windows

CE Platform Builder supported platforms.

• If you are running 13505CFG.EXE to produce multiple MODE tables, make sure you

change the Mode Number in the WinCE tab for each mode table you generate. The

display driver supports multiple mode tables, but only if each mode table has a unique

mode number.

• At this time, the drivers have been tested on the x86 CPUs and have been built with Plat-

form Builder v3.00.

S1D13505

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S1D13505 Embedded RAMDAC LCD/CRT Controller

SDU1355B0C Rev. 1.0 ISA Bus Evaluation

Board User Manual

Document Number: X23A-G-004-05

Information in this document is subject to change without notice. You may download and use this document, but only for your own use in

evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any

representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain

material protected under U.S. and/or International Patent laws.

EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.

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S1D13505

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S5U13505B00C Rev. 1.0 ISA Bus Evaluation Board User Manual

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Table of Contents

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Installation and Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

LCD Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

CPU/Bus Interface Connector Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Host Bus Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Technical Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

6.1 ISA Bus Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

6.2 Non-ISA Bus Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

6.3 DRAM Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

6.4 Decode Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

6.5 Clock Input Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

6.6 Monochrome LCD Panel Support . . . . . . . . . . . . . . . . . . . . . . . . .14

6.7 Color Passive LCD Panel Support . . . . . . . . . . . . . . . . . . . . . . . . .14

6.8 Color TFT/D-TFD LCD Panel Support . . . . . . . . . . . . . . . . . . . . . . .15

6.9 CRT Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

6.10 Power Save Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

6.11 Adjustable LCD Panel Negative Power Supply . . . . . . . . . . . . . . . . . . . .15

6.12 Adjustable LCD Panel Positive Power Supply . . . . . . . . . . . . . . . . . . . .15

6.13 CPU/Bus Interface Header Strips . . . . . . . . . . . . . . . . . . . . . . . . . .16

6.14 Schematic Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Schematic Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

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List of Tables

Table 2-1: Configuration DIP Switch Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 2-2: Host Bus Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 2-3: Jumper Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 3-1: LCD Signal Connector (J6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 4-1: CPU/BUS Connector (H1) Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 4-2: CPU/BUS Connector (H2) Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 5-1: CPU Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

List of Figures

Figure 1: S1D13505B00C Schematic Diagram (1 of 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 2: S1D13505B00C Schematic Diagram (2 of 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 3: S1D13505B00C Schematic Diagram (3 of 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 4: S1D13505B00C Schematic Diagram (4 of 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

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1 Introduction

This manual describes the setup and operation of the S5U13505B00C Rev. 1.0 Evaluation Board.

Implemented using the S1D13505 Embedded RAMDAC LCD/CRT Controller, the

S5U13505B00C is designed for the ISA bus environment. It also provides CPU/Bus interface

connectors for non-ISA bus support.

For more information regarding the S1D13505, refer to the S1D13505 Hardware Functional Speci-

fication, document number X23A-A-001-xx.

1.1 Features

• 128-pin QFP15 surface mount package.

• SMT technology for all appropriate devices.

• 4/8-bit monochrome passive LCD panel support.

• 4/8/16-bit color passive LCD panel support.

• 9/12/18-bit LCD TFT/D-TFD panel support.

• Embedded RAMDAC for CRT support.

• 16-bit ISA bus support.

• Oscillator support for CLKI (up to 40.0MHz).

• 5.0V 1M x 16 EDO-DRAM (2M byte).

• Support for software and hardware suspend modes.

• On-board adjustable LCD bias power supply (+24..38V or -24..14V).

• CPU/Bus interface header strips for non-ISA bus support.

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2 Installation and Configuration

The S1D13505 has 16 configuration inputs MD[15:0] which are read on the rising edge of RESET#.

Inputs MD[5:1] are fully configurable on this evaluation board for different host bus selections; one

eight-position DIP switch is provided for this purpose. All remaining configuration inputs are hard-

wired. See the S1D13505 Hardware Functional Specification, document number X23A-A-001-xx

for more information.

The following settings are recommended when using the S5U13505B00C with the ISA bus.

Table 2-1: Configuration DIP Switch Settings

Switch Signal

SW1-1 MD1

SW1-2 MD2

SW1-3 MD3

SW1-4 MD4

SW1-5 MD5

SW1-6 MD13

SW1-7 MD14

SW1-8 MD15

Closed (1)

Open (0)

See “Host Bus Selection” table below See “Host Bus Selection” table below

Little Endian

Big Endian

Wait# signal is active high

Wait# signal is active low

Reserved

Table 2-2: Host Bus Selection

MD3 / SW1-3

MD2 / SW1-2

MD1 / SW1-1

Host Bus Interface

SH-3/SH-4 bus interface

open (0)

closed (1)

open (0)

closed (1)

open (0)

MC68K bus 1 interface (e.g. MC68000)

MC68K bus 2 interface (e.g. MC68030)

Generic bus interface

Reserved

open (0)

closed (1)

open (0)

closed (1)

open (0)

closed (1)

open (0)

MIPS/ISA

closed (1)

PowerPC

closed (1)

PC Card (PCMCIA)

= recommended settings (configured for ISA bus support)

Table 2-3: Jumper Settings

Description

1-2

2-3

JP1

JP2

DRDY (pin 76, S1D13505)

LCD V_DDSelection

Pin 76 connected to J6 pin 38

5.0V LCD driver V_DD

Pin 76 connected to J6 pin 35

3.3V LCD driver V_DD

Note

JP1 is for internal use only, default setting is 1-2.

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3 LCD Interface Pin Mapping

Table 3-1: LCD Signal Connector (J6)

Color TFT/D-TFD

Color Passive

Mono Passive

S1D13505

Pin Names

Connector

Pin No.

9-bit

12-bit

18-bit

4-bit

8-bit

16-bit

4-bit

8-bit

FPDAT0

FPDAT1

FPDAT2

FPDAT3

FPDAT4

FPDAT5

FPDAT6

FPDAT7

FPDAT8

FPDAT9

FPDAT10

FPDAT11

FPDAT12

FPDAT13

FPDAT14

FPDAT15

FPSHIFT

DRDY

LD0

LD1

LD2

LD3

UD0

UD1

UD2

UD3

LD0

LD1

LD2

LD3

UD0

UD1

UD2

UD3

LD4

LD5

LD6

LD7

UD4

UD5

UD6

UD7

LD0

LD1

LD2

LD3

UD0

UD1

UD2

UD3

UD0

UD1

UD2

UD3

UD0

UD1

UD2

UD3

FPSHIFT

FPSHIFT2

FPLINE

FPFRAME

2-26

(Even Pins)

GND

N/C

VEEH

Adjustable -24..-14V negative LCD bias

Jumper selectable +3.3V/+5V

+12V

LCDVCC

+12V

VDDH

Adjustable +15..+38V positive LCD bias

DRDY

MOD

FPSHIFT2

MOD

LCDPWR#

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4 CPU/Bus Interface Connector Pinouts

Table 4-1: CPU/BUS Connector (H1) Pinout

Connector

Pin No.

Comments

Connected to DB0 of the S1D13505

Connected to DB1 of the S1D13505

Connected to DB2 of the S1D13505

Connected to DB3 of the S1D13505

Ground

Connected to DB4 of the S1D13505

Connected to DB5 of the S1D13505

Connected to DB6 of the S1D13505

Connected to DB7 of the S1D13505

Ground

Connected to DB8 of the S1D13505

Connected to DB9 of the S1D13505

Connected to DB10 of the S1D13505

Connected to DB11 of the S1D13505

Ground

Connected to DB12 of the S1D13505

Connected to DB13 of the S1D13505

Connected to DB14 of the S1D13505

Connected to DB15 of the S1D13505

Connected to RESET# of the S1D13505

Ground

+12 volt supply

Connected to WE0# of the S1D13505

Connected to WAIT# of the S1D13505

Connected to CS# of the S1D13505

Connected to MR# of the S1D13505

Connected to WE1# of the S1D13505

Not connected

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Table 4-2: CPU/BUS Connector (H2) Pinout

Connector

Pin No.

Comments

Connected to AB0 of the S1D13505

Connected to AB1 of the S1D13505

Connected to AB2 of the S1D13505

Connected to AB3 of the S1D13505

Connected to AB4 of the S1D13505

Connected to AB5 of the S1D13505

Connected to AB6 of the S1D13505

Connected to AB7 of the S1D13505

Ground

Connected to AB8 of the S1D13505

Connected to AB9 of the S1D13505

Connected to AB10 of the S1D13505

Connected to AB11 of the S1D13505

Connected to AB12 of the S1D13505

Connected to AB13 of the S1D13505

Ground

Connected to AB14 of the S1D13505

Connected to AB16 of the S1D13505

Connected to AB17 of the S1D13505

Connected to AB18 of the S1D13505

Connected to AB19 of the S1D13505

Ground

+5 volt supply

Connected to RD/WR# of the S1D13505

Connected to BS# of the S1D13505

Connected to BUSCLK of the S1D13505

Connected to RD# of the S1D13505

Connected to AB20 of the S1D13505

Not connected

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5 Host Bus Interface Pin Mapping

Table 5-1: CPU Interface Pin Mapping

S1D13505

Pin Names

MC68K

Bus 1

MC68K

Bus 2

SH-3

SH-4

Generic

MIPS/ISA PowerPC PCMCIA

AB20

AB[16:13]

AB[12:1]

AB0

A20

A[19:13]

A[12:1]

LDS#

A20

A[19:13]

A[12:1]

A20

A[19:13]

A[12:1]

LatchA20

A11

A20

A[19:13]

A[12:1]

A[19:13] A[19:13]

SA[19:13] A[12:18]

A[12:1]

SA[12:1]

SA0

A[19:30]

A31

DB[15:0]

WE1#

D[15:0]

WE1#

D[15:0]

WE1#

D[15:0]

UDS#

D[31:16]

DS#

D[15:0]

WE1#

SD[15:0]

SBHE#

D[0:15]

BI#

D[15:0]

-CE2

M/R#

External Decode

CS#

BUSCLK

BS#

CKIO

BS#

CKIO

BS#

CLK

AS#

CLK

AS#

BCLK

CLK

CLKOUT

TS#

CLKI

RD/WR#

RD#

RD/WR# RD/WR#

R/W#

SIZ1

RD1#

RD0#

WE0#

WAIT#

RD/WR#

TSIZ0

TSIZ1

TA#

-CE1

-OE

RD#

WE0#

WAIT#

RD#

WE0#

RDY

MEMR#

MEMW#

IOCHRDY

WE0#

SIZ0

-WE

WAIT#

DTACK#

DSACK1#

-WAIT

inverted

RESET

inverted

RESET

RESET#

RESET# RESET#

RESET#

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6 Technical Description

6.1 ISA Bus Support

The S5U13505B00C directly supports the 16-bit ISA bus environment. All the configuration options

[MD15:0] are either hard-wired or selectable through the eight-position DIP Switch S1. Refer to

Table 2-1 “Configuration DIP Switch Settings ” on page 8 for details.

Note

1. This evaluation board supports a 16-bit ISA bus only.

2. The S1D13505 is a memory-mapped device with 2M bytes of linear addressed display buffer

and a separate 47 byte register space. On the S5U13505B00C, the S1D13505 2M byte display

buffer has been mapped to a start address of C00000h and the registers have been mapped to a

start address of E00000h.

3. When using this board in a PC environment, system memory must be limited to 12M bytes, to

prevent the system addresses will conflict with the S1D13505 display buffer/register

addresses.

4. The hardware suspend enable/disable address is at location F00000h. A read to this location

will enable the hardware suspend, a write to the same location will disable it.

Note

Due to backwards compatibility with the S5U13505B00B Evaluation Board, which supports

both an 8 and a 16-bit CPU interface, third party software must perform a write at address

F80000h in order to enable a 16-bit ISA environment. This must be done prior to initializing the

S1D13505. Failure to do so will result in the S1D13505 being configured as a 16-bit device (de-

fault, power-up), with the ISA Bus interface (supported through the PAL (U4)) configured for an

8-bit

interface.

The Epson supplied software performs this function automatically.

6.2 Non-ISA Bus Support

This evaluation board is specifically designed to support the standard 16-bit ISA bus. However, the

S1D13505 directly supports many other host bus interfaces. Header strips H1 and H2 have been

provided and contain all the necessary I/O pins to interface to these buses. See, Section 4 “CPU/Bus

Interface Connector Pinouts ” on page 10, Table 2-1 “Configuration DIP Switch Settings ” on page

8, an d Table 2-3 “Jumper Settings ” on page 8, for details.

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When using the header strips to provide the bus interface observe the following:

• All I/O signals on the ISA bus card edge must be isolated from the ISA bus (do not plug the card

into a computer). Voltage lines are provided on the header strips.

• For the ISA bus, a 22V10 PAL (U4, socketed) is currently used to provide the S1D13505

CS# (pin 4), M/R# (pin 5) and other decode logic signals. This functionality must now be

provided externally. Remove the PAL from its socket to eliminate conflicts resulting from two

different outputs driving the same input. Refer to Table 2-2 “Host Bus Selection ” on page 8 for

connection details.

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6.3 DRAM Support

The S1D13505 supports 256K x 16 as well as 1M x 16 FPM/EDO-DRAM in symmetrical and

asymmetrical formats.

The S5U13505B00C board supports a 5.0V 1M x 16 symmetrical EDO-DRAM (42-pin SOJ

package). This provides a 2M byte display buffer.

6.4 Decode Logic

This board utilizes the MIPS/ISA Interface of the S1D13505 (see the S1D13505 Hardware

Functional Specification, document number X23A-A-001-xx).

All required decode logic is provided through a 22V10 PAL (U4, socketed).

6.5 Clock Input Support

The S1D13505 supports up to a 40.0Mhz input clock frequency. A 40.0MHz oscillator (U2,

socketed) is provided on the S5U13505 board as the clock (CLKI) source.

6.6 Monochrome LCD Panel Support

The S1D13505 supports 4 and 8-bit, dual and single, monochrome passive LCD panels. All

necessary signals are provided on the 40-pin ribbon cable header J6. The interface signals on the

cable are alternated with grounds to reduce crosstalk and noise.

Refer to Table 3-1 “LCD Signal Connector (J6)” on page 9 for connection information.

6.7 Color Passive LCD Panel Support

The S1D13505 directly supports 4, 8 and 16-bit, dual and single, color passive LCD panels. All the

necessary signals are provided on the 40-pin ribbon cable header J6. The interface signals on the

cable are alternated with grounds to reduce crosstalk and noise.

Refer to Table 3-1 “LCD Signal Connector (J6)” on page 9 for connection information.

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6.8 Color TFT/D-TFD LCD Panel Support

The S1D13505 supports 9, 12 and 18-bit active matrix color TFT/D-TFD panels. All the necessary

signals can also be found on the 40-pin LCD connector J6. The interface signals on the cable are

alternated with grounds to reduce crosstalk and noise.

When supporting an 18-bit TFT/D-TFD panel, the S1D13505 can display 64K of a possible 256K

colors. A maximum 16 of the possible 18 bits of LCD data are available from the S1D13505. Refer

to the S1D13505 Hardware Functional Specification, document number X23A-A-001-xx for details.

Refer to Table 3-1 “LCD Signal Connector (J6)” on page 9 for connection information.

6.9 CRT Support

This evaluation board provides CRT support through the S1D13505’s embedded RAMDAC. Refer

to the S1D13505 Hardware Functional Specification, document number X23A-A-001-xx for details.

6.10 Power Save Modes

The S1D13505 supports one hardware suspend and one software suspend Power Save Mode.

The software suspend mode is controlled by the utility 13505PWR Software Suspend Power

Sequencing.

The hardware suspend mode can be enabled by a memory read to location F00000h. A memory write

to the same location will disable it.

6.11 Adjustable LCD Panel Negative Power Supply

Most monochrome passive LCD panels require a negative power supply to provide between -18V

and -23V (I_out=45mA). For ease of implementation, such a power supply has been provided as an

integral part of this design. The signal VLCD can be adjusted by R29 to supply an output voltage

from -14V to -23V and is enabled/disabled by the S1D13505 control signal LCDPWR#.

Determine the panel’s specific power requirements and set the potentiometer accordingly before

connecting the panel.

6.12 Adjustable LCD Panel Positive Power Supply

Most passive LCD passive color panels and most single monochrome 640x480 passive LCD panels

require a positive power supply to provide between +23V and +40V (I_out=45mA). For ease of imple-

mentation, such a power supply has been provided as an integral part of this design. The signal

VDDH can be adjusted by R23 to provide an output voltage from +23V to +40V and is

enabled/disabled by the S1D13505 control signal LCDPWR#.

Determine the panel’s specific power requirements and set the potentiometer accordingly before

connecting the panel.

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6.13 CPU/Bus Interface Header Strips

All of the CPU/Bus interface pins of the S1D13505 are connected to the header strips H1 and H2 for

easy interface to a CPU, or bus other than ISA.

Refer to Table 4-1 “CPU/BUS Connector (H1) Pinout ” on page 10 and Table 4-2 “CPU/BUS

Connector (H2) Pinout ” on page 11 for specific settings.

Note

These headers only provide the CPU/Bus interface signals from the S1D13505. When another

host bus interface is selected through [MD3:1] configuration, appropriate external decode logic

MUST be used to access the S1D13505. See the section “Host Bus Interface Pin Mapping” of the

S1D13505 Hardware Functional Specification, document number X23A-A-001-xx.

6.14 Schematic Notes

The following schematics are for reference only and may not reflect actual implementation. Please

request updated information before starting any hardware design.

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7 Parts List

Item # Qty/board

Designation

Part Value

Description

C1,C2,C3,C4,C5,C6,C7,C10,C11,

C12,C13,C18,C25,C27,C28,C29

0.1uF

0805 ceramic capacitor

0.01uF

0805 ceramic capacitor

Tantalum capacitor size A

Tantalum capacitor size D

Low-ESR electrolytic

C9,C30

1uF 6V

C14,C19

47uF 6V

4.7uF 50V

56uF 35V

4.7uF 16V

BAV99

C15,C16,C17

C20

C21,C22,C23,C24

Tantalum capacitor size B

Signal diode

D1,D2,D3

H1,H2

HEADER 17X2

HEADER 3

VGA connector

AT CON-A

JP1,JP2

AT CON-B

AT CON-C

AT CON-D

CON40A

L1,L2,L3,L4,L5,L7

Ferrite bead

Inductor 1µH

MMBT2222A

MMBT2907A

Philips BDS3/3/8.9-4S2

Q1,Q3”

R1,R2,R21,R26,R30,R31,R32,R33,R

34,R35

10K

0805 resistor

R3,R4

R5,R6,R7

39 Ohms

150 1%

2.8K 1%

1K 1%

0805 resistor

R10

140 1%

R11,R12,R13,R14,R15,R16,R17,R18,

R19,R20

15K

0805 resistor

R22

R23

R24

R25

R28,R27

R29

470K

200K Pot.

14K

0805 resistor

4.7K

100K

100K Pot.

SW DIP-8

S1D13505F00A

40MHz oscillator

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Item # Qty/board

Designation

Part Value

MT4C1M16E5DJS-5

PAL22V10-15

RD-0412

Description

50ns self-refresh EDO DRAM

Xentek RD-0412

Xentek EPN001

EPN001

U7,U8,U9

U10

74AHC244

LT1117CM-3.3

“5V to 3.3V regulator, 800mA”

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8 Schematic Diagrams

Figure 1: S1D13505B00C Schematic Diagram (1 of 4)

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T U O D C _

N C

G N

J D A _ T U V O

I N D C _

1 0

1 1

T U O D C _

D A J _ U T O V

N C

1 2

G N

1 1

1 0

E T O M R E

I N D C _

Figure 2: S1D13505B00C Schematic Diagram (2 of 4)

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Figure 3: S1D13505B00C Schematic Diagram (3 of 4)

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A D

Figure 4: S1D13505B00C Schematic Diagram (4 of 4)

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S1D13505

X23A-G-004-05

S5U13505B00C Rev. 1.0 ISA Bus Evaluation Board User Manual

Issue Date: 01/02/05

S5U13505-D9000

Evaluation Board User Manual

Document Number: X23A-G-002-04

Information in this document is subject to change without notice. You may download and use this document, but only for your own use in

evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any

representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain

material protected under U.S. and/or International Patent laws.

EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners

Microsoft and Windows are registered trademarks of Microsoft Corporation.

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Table of Contents

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.1 S1D13505 Embedded RAMDAC LCD/CRT Controller . . . . . . . . . . . . . . . . . . .8

2.1.1

2.1.2

2.1.3

2.1.4

2.1.5

2.1.6

Display Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

LCD Display Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Touchscreen Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

CRT Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Jumper Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Adjustable LCD BIAS Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

D9000 Specifics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.1 Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.1.1

3.1.2

Connector Pinout for Channel A6 and A7 . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Memory Address (CS#, M/R#) Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.2 FPGA Code Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.3 Board Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Schematic Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Component Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

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List of Tables

Table 2-1: LCD Connector Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 2-2: Touchscreen Header (TS1) Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 2-3: Touchscreen Header Pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 3-1: Connectors Pinout for Channel A7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 3-2: Connectors Pinout for Channel A6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

List of Figures

Figure 5-1: S5U13505-D9000 Schematic Diagram (1 of 3). . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 5-2: S5U13505-D9000 Schematic Diagram (2 of 3). . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 5-3: S5U13505-D9000 Schematic Diagram (3 of 3). . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 6-1: Component Placement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

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1 Introduction

The Hitachi D9000 Development System/Microsoft Windows® CE ODO Reference Platform uses

expansion boards to interface peripherals to the FPGA/processor combination. This manual

describes how the S5U13505-D9000 Evaluation Board is used to provide a color LCD/CRT solution

for the Windows CE environment.

Reference

S1D13505 Hardware Functional Specification, document number X23A-A-001-xx.

D9000 Development System, Hardware User Manual - Hitachi.

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2 Features

• S1D13505 Embedded RAMDAC LCD/CRT controller.

• 4/8-bit monochrome or 4/8/16-bit color LCD interface for single-panel, single-drive displays.

• 8-bit monochrome or 8/16-bit color LCD interface for dual-panel, dual-drive displays.

• Direct support for 9/12-bit TFT/D-TFD; 18-bit TFT/D-TFD is supported to 64K colors (16-bit

data).

• Direct CRT support to 64K colors using the S1D13505 embedded RAMDAC.

• Up to 16 shades of gray using Frame Rate Modulation (FRM) on monochrome passive LCD

panels.

• Up to 4096 colors on color passive LCD panels; three 256x4 Look-Up Tables (LUT) are used

to map 1/2/4/8 bpp modes into these colors, 15/16 bpp modes are mapped directly using the

four most significant bits of the red, green and blue colors.

• Up to 64K colors on TFT/D-TFD and CRT; three 256x4 Look-Up Tables are used to map

1/2/4/8 bpp modes into 4096 colors, 15/16 bpp modes are mapped directly.

• On-board 2M byte EDO-DRAM display buffer.

• On-board adjustable LCD bias voltage power supply.

• SmallTypeZ x 2 form factor (requires two side-by-side SmallTypeZ slots).

2.1 S1D13505 Embedded RAMDAC LCD/CRT Controller

The S1D13505 is a low cost, low power, color/monochrome LCD/CRT controller with an embedded

RAMDAC capable of interfacing to a wide range of CPUs and LCD displays.

The S1D13505 supports LCD interfaces with data widths up to 16-bits. Using Frame Rate

Modulation (FRM), it can display 16 shades of gray on monochrome panels, up to 4096 colors on

passive panels and 64K colors on active matrix TFT/D-TFD. CRT support is handled through the

use of an embedded RAMDAC allowing simultaneous display of both the CRT and LCD displays.

In this design, the S1D13505 has a 3.3V supply voltage for both logic and the embedded RAMDAC.

For complete details on register functionality and programming, refer to the S1D13505 Hardware

Functional Specification, document number X23A-A-001-xx, and the S1D13505 Programming

Notes and Examples, document number X23A-G-003-xx.

2.1.1 Display Buffer

The S1D13505 supports a 512K byte or 2M byte FPM-DRAM or EDO-DRAM display buffer. On

the S5U13505-D9000 evaluation board a 1Mx16 EDO-DRAM (2M byte) is used to provide memory

for all supported display resolutions, and when smaller display sizes are used, to provide multiple

“pages” of memory.

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2.1.2 LCD Display Support

The S1D13505 provides a wide range of flexibility for display type and resolution. Display types

include:

• 4/8-bit monochrome passive.

• 4/8/16-bit color passive.

• 9/12/18-bit Active matrix TFT/D-TFD.

• other (EL, REC, etc.).

Display resolutions range from 4x1 to 800x600, with color depths from black-and-white to 64K

colors.

The LCD connector is a 2 x 20 pin, 0.100", straight header. Pinout assignment is shown in the

following table “LCD Connector Pinout ”.

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Table 2-1: LCD Connector Pinout

Pin #

Color TFT/D-TFD

Color STN

8-bit

LD0

Mono STN

Comments

S1D13505F00A

Pin Names

9-bit

12-bit

18-bit

4-bit

16-bit

LD0

LD1

LD2

LD3

UD0

UD1

UD2

UD3

LD4

LD5

LD6

LD7

UD4

UD5

UD6

UD7

4-bit

8-bit

FPDAT[0]

FPDAT[1]

FPDAT[2]

FPDAT[3]

FPDAT[4]

FPDAT[5]

FPDAT[6]

FPDAT[7]

FPDAT[8]

FPDAT[9]

FPDAT[10]

FPDAT[11]

FPDAT[12]

FPDAT[13]

FPDAT[14]

FPDAT[15]

FPSHIFT

LD0

LD1

LD2

LD3

UD0

UD1

UD2

UD3

LD1

LD2

LD3

UD0

UD1

UD2

UD3

UD0

UD1

UD2

UD3

UD1

UD2

UD3

FPSHIFT

Jumper

selectable

35 or 38

DRDY

MOD/FPSHIFT2

FPLINE

FPFRAME

2, 4, 6, 8,

10, 12, 14,

16, 18, 20,

22, 24, 26

GND

On/Off

Control for

Backlight

LCDBACK#

Selectable

3.3V/5V

LCDVCC

+12V

+30v LCD

bias

VDDH

On/Off

LCDPWR#

Control for

LCD Power

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2.1.3 Touchscreen Support

If the LCD panel being used has an integrated Touchscreen, the touchscreen interface signals are

connected to header strip TS1. These signals are then routed through JP3 and into the standard

"Platform II Audio/Touch" peripheral board. Pinout assignment is described in the table below.

Table 2-2: Touchscreen Header (TS1) Pinout

Pin #

Signal

GND

2.1.4 CRT Support

The S1D13505 has an embedded RAMDAC and provides complete one-chip CRT support. Refer to

the Programmer’s Notes and Examples, document number X23A-G-003-xx, for programming

details.

2.1.5 Jumper Selection

Jumpers labelled LCDVCC1 and FPS2 provide LCD logic supply voltage and connector pinout

options respectively. Jumper options are described in the table below.

Table 2-3: Touchscreen Header Pinout

Jumper

LCDVCC1

FPS2

Function

1-2

2-3

LCD logic supply

3.3V

FPSHIFT2/DRDY/MOD To pin 38

To pin 35

= default settings

Note

Setting the panel supply voltage to 5V does not affect the signalling voltage which remains at

3.3V.

2.1.6 Adjustable LCD BIAS Power Supply

Many color passive LCD panels require a positive power supply to provide the LCD BIAS voltage.

Such a power supply has been provided as an integral part of this design. The signal VDDH can be

adjusted by R16 to provide an output voltage from +24V to +38V (I_out= 45mA) and is

enabled/disabled by the S1D13505 control signal LCDPWR.

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LCDPWR is an output signal which follows a pre-defined power-up/power-down sequence

designed to protect the LCD panel from damage caused by the power supply being enabled in the

absence of control signals. Determine the panel’s specific power requirements and set the

potentiometer accordingly before connecting the panel.

S5U13505-D9000

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3 D9000 Specifics

3.1 Interface Signals

The S5U13505-D9000 is designed to support the standard Register Interface of the Windows CE

development platform together with the FPGA code that comes with the board.

3.1.1 Connector Pinout for Channel A6 and A7

Table 3-1: Connectors Pinout for Channel A7

Channel A7

Pin #

FPGA Signal

S1D13505 Signal

SmXY

Pin #

FPGA Signal

S1D13505 Signal

chA7p1

chA7p2

chA7p3

chA7p4

chA7p5

chA7p6

chA7p7

chA7p8

chA7p9

chA7p10

ib8

BCLK

N/C

GND

dc5v

GND

DC5V

GND

DC3V

GND

DC3V

GND

N/C

dc3v

GND

dc3v

GND

dc3vs

GND

DC12V

GND

N/C

dc12v

GND

battery

GND

ib7

GND

N/C

ib6

dcXA

base5vDc

dcXB

GND

ib5

N/C

ib4

N/C

ib3

GND

N/C

ib2

dcXC

GND

ib1

GND

N/C

GND

senseH

senseL

GND

N/C

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Table 3-1: Connectors Pinout for Channel A7 (Continued)

Channel A7

Pin #

FPGA Signal

S1D13505 Signal

SmZ

Pin #

FPGA Signal

S1D13505 Signal

chA7p11

chA7p12

chA7p13

chA7p14

chA7p15

chA7p16

chA7p17

chA7p18

chA7p19

chA7p20

chA7p21

chA7p22

chA7p23

chA7p24

chA7p25

chA7p26

chA7p27

chA7p28

chA7p29

chA7p30

N/C

A20

A18

A17

A16

N/C

A14

A13

A12

A11

GND

A19

chA7p34

GND

A15

GND

chA7p33

GND

A10

GND

chA7p32

GND

chA7p31

GND

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Table 3-2: Connectors Pinout for Channel A6

Channel A6

Pin #

FPGA Signal

S1D13505 Signal

SmXY

Pin #

FPGA Signal

S1D13505 Signal

chA6p1

chA6p2

chA6p3

chA6p4

chA6p5

chA6p6

chA6p7

chA6p8

chA6p9

chA6p10

ib1

CS#

BS#

WE0#

RD/WR#

WAIT#

N/C

dc5v

GND

DC5V

GND

DC3V

GND

DC3V

GND

N/C

dc3v

GND

dc3v

GND

N/C

dc3vs

GND

N/C

GND

DC12V

GND

N/C

dc12v

GND

N/C

battery

GND

ib2

GND

N/C

ib3

dcXA

base5vDc

dcXB

GND

ib4

N/C

ib5

N/C

ib6

N/C

GND

N/C

ib7

N/C

dcXC

GND

ib8

GND

N/C

GND

senseH

senseL

GND

N/C

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Table 3-2: Connectors Pinout for Channel A6 (Continued)

Channel A6

Pin #

FPGA Signal

S1D13505 Signal

SmZ

Pin #

FPGA Signal

S1D13505 Signal

chA6p11

chA6p12

chA6p13

chA6p14

chA6p15

chA6p16

chA6p17

chA6p18

chA6p19

chA6p20

chA6p21

chA6p22

chA6p23

chA6p24

chA6p25

chA6p26

chA6p27

chA6p28

chA6p29

chA6p30

M/R#

RD#

WE1#

RESET#

N/C

D14

D13

D12

D11

GND

N/C

chA6p34

GND

D15

GND

chA6p33

GND

D10

GND

chA6p32

GND

chA6p31

GND

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3.1.2 Memory Address (CS#, M/R#) Decoding

The S1D13505 is a memory-mapped device for both the registers and the display buffer access. The

specific memory address is solely controlled by the CS# and M/R# decode logic. The memory space

requirements are:

• A 2M byte linear address range for the display buffer.

• 47 bytes for the registers.

With the FPGA code that comes with this board, the registers are located at 0x12000000 and the

display buffer is located at 0x12200000.

3.2 FPGA Code Functionality

The D9000/ODO is a flexible hardware/software development system designed for use with the

Microsoft Windows CE operating system. It is designed so that an arbitrary set of peripherals may

be quickly compiled in a way that is identical to the final product. A 100K FPGA is at the center of

the system and sits between the CPU and all other peripherals. Most peripherals, except analog

components, are implemented within the FPGA.

In order to support several different CPUs, any peripherals that connect to the system have to use a

common Register Interface. This interface is similar to a standard bus, in that it allows the CPU to

read and write registers associated with the peripheral. For each peripheral, whether implemented

internal or external to the FPGA, a VHDL module has to be written to implement the register

interface and to assign the necessary signals to the slot where the peripheral is going to be located.

The D9000/ODO platform supports 32-bit accesses to peripherals. The S1D13505 provides a 16-bt

CPU interface, and therefore, the FPGA files provided with the S5U13505-D9000 convert any 32-

bit accesses to back-to-back 16-bit cycles.

3.3 Board Dimensions

To obtain the required number of interface signals, the S5U13505-D9000 utilizes two SmallTypeZ

slots (6 and 7). Board dimensions are 2.65 x 3.20cm with both the CRT and LCD connectors acces-

sible on the outside edge.

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4 Parts List

Item #

Qty

Reference

Part

Description

C1,C2,C3,C4,C5,C6,C7,

C8,C9,C11,C21,C26,C27,C29,

C34,C35,C37,C38, C39,C40

0.1uF

0.1uF ceramic capacitor

C10,C24,C25,C32,C33

10uF

47uF/10V

22uF/63V

10uF/63V

4.7uF

10uF tantalum capacitor

C17

C18

47uF/10V tantalum capacitor

22uF/63V electrolytic, aluminum can capacitor

10uF/63V electrolytic, aluminum can capacitor

4.7uF tantalum capacitor

C20

C22,C30

D1,D2,D3

FPS2,LCDVCC1

BAV99

BAV99 signal diode

Header

Header, 3x1, .1"

D9000 SmallTypeX/Y/Z D9000 SmallTypeX/Y/Z connector. Samtec

JP2,JP3,JP4,JP5

connector

PS/2 Connector

Header

TFM-120-11-S-D

15-pin VGA connector

Header, 20x2, .1"

Ferrite bead on wire

1uH inductor

MMBT2222A

15K

LCD1

L1,L2,L3,L4,L5

Ferrite bead

1uH

MMBT2222A

15K

R1,R2,R5,R6,R7,R8,R17

R9,R10,R11

150 1%

R12,R13

39 Ohms

R15

470K

R16

200K Pot.

10K

200K potentiometer

10K

R18,R19,R20,R27

R21

R22

R23

TS1

1.5K 1%

1K 1%

1.5K 1%

1K 1%

140 1%

140 Ohms 1%

Header, 3x2, .1"

S1D13505F00A

Header

S1D13505F00A

DRAM1MX16-SOJ-3.3V, Micron

MT4LC1M16E5DJ-6

DRAM1MX16-SOJ-3.3V

RD-0412

RD-0412, Xentek

33.333MHz

33.333MHz 8-DIP Oscillator

S5U13505-D9000

X23A-G-002-04

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5 Schematic Diagrams

Figure 5-1: S5U13505-D9000 Schematic Diagram (1 of 3)

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T U O D C _

D A J _ U T O V

1 2

N C

G N

1 1

1 0

E T O M R E

I N D C _

Figure 5-2: S5U13505-D9000 Schematic Diagram (2 of 3)

S5U13505-D9000

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Figure 5-3: S5U13505-D9000 Schematic Diagram (3 of 3)

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6 Component Placement

Figure 6-1: Component Placement

S5U13505-D9000

X23A-G-002-04

Evaluation Board User Manual

Issue Date: 01/02/05

S1D13505 Embedded RAMDAC LCD/CRT Controller

Power Consumption

Document Number: X23A-G-006-03

Information in this document is subject to change without notice. You may download and use this document, but only for your own use in

evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any

representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain

material protected under U.S. and/or International Patent laws.

EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.

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S1D13505

X23A-G-006-03

Power Consumption

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1 S1D13505 Power Consumption

S1D13505 power consumption is affected by many system design variables.

• Input clock frequency (CLKI): the CLKI frequency determines the LCD frame-rate, CPU perfor-

mance to memory, and other functions – the higher the input clock frequency, the higher the

frame-rate, performance and power consumption.

• CPU interface: the S1D13505 current consumption depends on the BUSCLK frequency, data

width, number of toggling pins, and other factors – the higher the BUSCLK, the higher the CPU

performance and power consumption.

• V_DDvoltage level: the voltage level affects power consumption – the higher the voltage, the

higher the consumption.

• Display mode: the resolution and color depth affect power consumption – the higher the

resolution/color depth, the higher the consumption.

• Internal CLK divide: internal registers allow the input clock to be divided before going to the

internal logic blocks – the higher the divide, the lower the power consumption.

There are two power save modes in the S1D13505: Software and Hardware SUSPEND. The power

consumption of these modes is affected by various system design variables.

• DRAM refresh mode (CBR or self-refresh): self-refresh capable DRAM allows the S1D13505 to

disable the internal memory clock thereby saving power.

• CPU bus state during SUSPEND: the state of the CPU bus signals during SUSPEND has a

substantial effect on power consumption. An inactive bus (e.g. BUSCLK = low, Addr = low etc.)

reduces overall system power consumption.

• CLKI state during SUSPEND: disabling the CLKI during SUSPEND has substantial power

savings.

Power Consumption

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1.1 Conditions

Table 1-1: “S1D13505 Total Power Consumption ” below gives an example of a specific

environment and its effects on power consumption.

Table 1-1: S1D13505 Total Power Consumption

Total Power Consumption

Power Save Mode

Test Condition

Gray Shades /

Colors

= 3.3V

Active

ISA Bus (8MHz)

Software

Hardware

Input Clock = 6MHz

LCD Panel = 320x240 4-bit Single Monochrome 4 Gray Shades

16 Gray Shades

Black-and-White

18.6mW

20.3mW

22.8mW

4.29mW

0.33µW

Input Clock = 6MHz

LCD Panel = 320x240 8-bit Single Color

4 Colors

16 Colors

256 Colors

22.3mW

25.3mW

29.0mW

4.32mW

Input Clock = 25MHz

LCD Panel = 640x480 8-bit Dual Monochrome

Black-and-White

16 Gray Shades

58.5mW

71.7mW

5.71mW

Input Clock = 25MHz

LCD Panel = 640x480 16-bit Dual Color

16 Colors

256 Colors

64K Colors

93.4mW

98.1mW

101.3mW

5.74mW

16 Colors

256 Colors

64K Colors

221.1mW

234.0mW

237.3mW

Input Clock = 33.333MHz

CRT = 640x480 Color

6.34mW

Note

1. Conditions for Software SUSPEND:

• CPU interface active (signals toggling)

• CLKI active

• Self-Refresh DRAM

2. Conditions for Hardware SUSPEND:

• CPU interface inactive (high impedance)

• CLKI stopped

• Self-Refresh DRAM

2 Summary

The system design variables in Section 1, “S1D13505 Power Consumption ” and in Table 1-1:

“S1D13505 Total Power Consumption ” show that S1D13505 power consumption depends on the

specific implementation. Active Mode power consumption depends on the desired CPU perfor-

mance and LCD frame-rate, whereas Power Save Mode consumption depends on the CPU Interface

and Input Clock state.

In a typical design environment, the S1D13505 can be configured to be an extremely power-efficient

LCD Controller with high performance and flexibility.

S1D13505

X23A-G-006-03

Power Consumption

Issue Date: 01/02/05

S1D13505 Embedded RAMDAC LCD/CRT Controller

Interfacing to the Philips MIPS

PR31500/PR31700 Processor

Document Number: X23A-G-001-07

Information in this document is subject to change without notice. You may download and use this document, but only for your own use in

evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any

representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain

material protected under U.S. and/or International Patent laws.

EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.

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S1D13505

X23A-G-001-07

Interfacing to the Philips MIPS PR31500/PR31700 Processor

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Table of Contents

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Interfacing to the PR31500/PR31700 . . . . . . . . . . . . . . . . . . . . . . . . . . 8

S1D13505 Host Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.1 PR31500/PR31700 Host Bus Interface Pin Mapping . . . . . . . . . . . . . . . . 9

3.2 PR31500/PR31700 Host Bus Interface Signals . . . . . . . . . . . . . . . . . 10

Direct Connection to the Philips PR31500/PR31700 . . . . . . . . . . . . . . . . . 11

4.1 Hardware Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4.2 S1D13505 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.3 Memory Mapping and Aliasing . . . . . . . . . . . . . . . . . . . . . . . 13

System Design Using the IT8368E PC Card Buffer . . . . . . . . . . . . . . . . . . 14

5.1 Hardware Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.2 IT8368E Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.3 S1D13505 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

7.1 Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

7.2 Document Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

8.1 EPSON LCD/CRT Controllers (S1D13505) . . . . . . . . . . . . . . . . . . 18

8.2 Philips MIPS PR31500/PR31700 Processor . . . . . . . . . . . . . . . . . . . 18

8.3 ITE IT8368E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Interfacing to the Philips MIPS PR31500/PR31700 Processor

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S1D13505

X23A-G-001-07

Interfacing to the Philips MIPS PR31500/PR31700 Processor

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List of Tables

Table 3-1: PR31500/PR31700 Host Bus Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . 9

Table 4-1: S1D13505 Configuration for Direct Connection. . . . . . . . . . . . . . . . . . . . . . 12

Table 4-2: PR31500/PR31700 to PC Card Slots Address Remapping for Direct Connection . . . . 13

List of Figures

Figure 4-1: Typical Implementation of Direct Connection . . . . . . . . . . . . . . . . . . . . . . .11

Figure 5-1: IT8368E Implementation Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . .14

Interfacing to the Philips MIPS PR31500/PR31700 Processor

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X23A-G-001-07

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S1D13505

X23A-G-001-07

Interfacing to the Philips MIPS PR31500/PR31700 Processor

Issue Date: 01/02/05

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1 Introduction

This application note describes the hardware and software environment necessary to

provide an interface between the S1D13505 Embedded RAMDAC LCD/CRT Controller

and the Philips MIPS PR31500/PR31700 Processor.

The designs described in this document are presented only as examples of how such

interfaces might be implemented. This application note will be updated as appropriate.

Please check the Epson Electronics America website at http://www.eea.epson.com for the

latest revision of this document before beginning any development.

We appreciate your comments on our documentation. Please contact us via email at

[email protected].

Interfacing to the Philips MIPS PR31500/PR31700 Processor

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X23A-G-001-07

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2 Interfacing to the PR31500/PR31700

The Philips MIPS PR31500/PR31700 processor supports up to two PC Card (PCMCIA)

slots. It is through this host bus interface that the S1D13505 connects to the

PR31500/PR31700 processor.

The S1D13505 can be successfully interfaced using one of the following configurations:

• Direct connection to the PR31500/PR31700 (see Section 4, “Direct Connection to the

Philips PR31500/PR31700 ” on page 11).

• System design using the ITE IT8368E PC Card/GPIO buffer chip (see Section 5,

“System Design Using the IT8368E PC Card Buffer ” on page 14).

S1D13505

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Interfacing to the Philips MIPS PR31500/PR31700 Processor

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3 S1D13505 Host Bus Interface

The S1D13505 implements a 16-bit host bus interface specifically for interfacing to the

PR31500/PR31700 microprocessor.

The PR31500/PR31700 host bus interface is selected by the S1D13505 on the rising edge

of RESET#. After releasing reset, the bus interface signals assume their selected

configuration. For details on S1D13505 configuration, see Section 4.2, “S1D13505 Config-

uration ” on page 12.

Note

At reset, the Host Interface Disable bit in the Miscellaneous Disable Register

(REG[1Bh] bit 7) is set to 1. This means that only REG[1Ah] (read-only) and

REG[1Bh] are accessible until a write to REG[1Bh] sets bit 7 to 0 making all regis-

ters accessible. When debugging a new hardware design, this can sometimes give the

appearance that the interface is not working, so it is important to remember to clear this

bit before proceeding with debugging.

3.1 PR31500/PR31700 Host Bus Interface Pin Mapping

The following table shows the function of each host bus interface signal.

Table 3-1: PR31500/PR31700 Host Bus Interface Pin Mapping

S1D13505 Pin Name

AB20

Philips PR31500/PR31700

ALE

AB19

/CARDREG

AB18

/CARDIORD

/CARDIOWR

AB17

AB[16:13]

AB[12:0]

DB[15:8]

DB[7:0]

WE1#

A[12:0]

D[23:16]

D[31:24]

/CARDxCSH

M/R#

CS#

BUSCLK

BS#

DCLKOUT

RD/WR#

RD#

/CARDxCSL

/RD

WE0#

/WE

WAIT#

RESET#

/CARDxWAIT

RESET#

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3.2 PR31500/PR31700 Host Bus Interface Signals

When the S1D13505 is configured to operate with the PR31500/PR31700, the host

interface requires the following signals:

• BUSCLK is a clock input required by the S1D13505 host bus interface. It is separate

from the input clock (CLKI) and should be driven by the PR31500/PR31700 bus clock

output DCLKOUT.

• Address input AB20 corresponds to the PR31500/PR31700 signal ALE (address latch

enable) whose falling edge indicates that the most significant bits of the address are

present on the multiplexed address bus (AB[12:0]).

• Address input AB19 should be connected to the PR31500/PR31700 signal /CARDREG.

This signal is active when either IO or configuration space of the PR31500/PR31700

PC Card slot is being accessed.

• Address input AB18 should be connected to the PR31500/PR31700 signal

/CARDIORD. Either AB18 or the RD# input must be asserted for a read operation to

take place.

• Address input AB17 should be connected to the PR31500/PR31700 signal

/CARDIOWR. Either AB17 or the WE0# input must be asserted for a write operation to

take place.

• Address inputs AB[16:13] and control inputs M/R#, CS# and BS# must be tied to V

as they are not used in this interface mode.

• Address inputs AB[12:0], and the data bus DB[15:0], connect directly to the

PR31500/PR31700 address and data bus, respectively. MD4 must be set to select the

proper endian mode on reset (see Section 4.2, “S1D13505 Configuration ” on page 12).

Because of the PR31500/PR31700 data bus naming convention and endian mode,

S1D13505 DB[15:8] must be connected to PR31500/PR31700 D[23:16], and

S1D13505 DB[7:0] must be connected to PR31500/PR31700 D[31:24].

• Control inputs WE1# and RD/WR# should be connected to the PR31500/PR31700

signals /CARDxCSH and /CARDxCSL respectively for byte steering.

• Input RD# should be connected to the PR31500/PR31700 signal /RD. Either RD# or the

AB18 input (/CARDIORD) must be asserted for a read operation to take place.

• Input WE0# should be connected to the PR31500/PR31700 signal /WR. Either WE0# or

the AB17 input (/CARDIOWR) must be asserted for a write operation to take place.

• WAIT# is a signal output from the S1D13505 that indicates the host CPU must wait

until data is ready (read cycle) or accepted (write cycle) on the host bus. Since the host

CPU accesses to the S1D13505 may occur asynchronously to the display update, it is

possible that contention may occur in accessing the S1D13505 internal registers and/or

display buffer. The WAIT# line resolves these contentions by forcing the host to wait

until the resource arbitration is complete.

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4 Direct Connection to the Philips PR31500/PR31700

The S1D13505 was specifically designed to support the Philips MIPS PR31500/PR31700

processor. When configured, the S1D13505 will utilize one of the PC Card slots supported

by the processor.

4.1 Hardware Description

In this example implementation, the S1D13505 occupies one PC Card slot and resides in

the Attribute and IO address range. The processor provides address bits A[12:0], with

A[23:13] being multiplexed and available on the falling edge of ALE. Peripherals requiring

more than 8K bytes of address space would require an external latch for these multiplexed

bits. However, the S1D13505 has an internal latch specifically designed for this processor

making additional logic unnecessary. To further reduce the need for external components,

the S1D13505 has an optional BUSCLK divide-by-2 feature, allowing the high speed

DCLKOUT from the processor to be directly connected to the BUSCLK input of the

S1D13505. An optional external oscillator may be used for BUSCLK since the S1D13505

will accept host bus control signals asynchronously with respect to BUSCLK.

The following diagram shows a typical implementation of the interface.

(+3.3V)

PR31500/PR31700

S1D13505

M/R#

CS#

BS#

AB[16:13]

AB[12:0]

DB[15:8]

DB[7:0]

A[12:0]

D[23:16]

D[31:24]

AB20

AB19

AB18

AB17

ALE

/CARDREG

/CARDIORD

/CARDIOWR

/CARDxCSH

WE1#

RD/WR#

RD#

/CARDxCSL

/RD

/WE

WE0#

WAIT#

pull-up

/CARDxWAIT

System RESET

RESET#

ENDIAN

...or...

DCLKOUT

Oscillator

See text

BUSCLK

CLKI

Note:

When connecting the S1D13505 RESET# pin, the system designer should be aware of all

conditions that may reset the S1D13505 (e.g. CPU reset can be asserted during wake-up

from power-down modes, or during debug states).

Figure 4-1: Typical Implementation of Direct Connection

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The host interface control signals of the S1D13505 are asynchronous with respect to the

S1D13505 bus clock. This gives the system designer full flexibility to choose the

appropriate source (or sources) for CLKI and BUSCLK. The choice of whether both clocks

should be the same, whether to use DCLKOUT as clock source, and whether an external or

internal clock divider is needed, should be based on the desired:

• pixel and frame rates.

• power budget.

• part count.

• maximum S1D13506 clock frequencies.

The S1D13505 also has internal CLKI dividers providing additional flexibility.

4.2 S1D13505 Configuration

The S1D13505 latches MD15 through MD0 to allow selection of the bus mode and other

configuration data on the rising edge of RESET#. For details on configuration, refer to the

S1D13505 Hardware Functional Specification, document number X23A-A-001-xx.

The table below shows those configuration settings relevant to the Philips

PR31500/PR31700 host bus interface.

Table 4-1: S1D13505 Configuration for Direct Connection

Value on this pin at rising edge of RESET# is used to configure:

S1D13505

Pin Name

1 (V

)

0 (V

)

MD0

8-bit host bus interface

111 = Philips PR31500/PR31700 host bus interface if Alternate host bus interface is selected

16-bit host bus interface

MD[3:1]

MD4

Little Endian

Big Endian

MD5

WAIT# is active high (1 = insert wait state)

WAIT# is active low (0 = insert wait state)

MD11

MD12

Alternate host bus interface selected

Primary host bus interface selected

BUSCLK input divided by two: use with DCLKOUT BUSCLK input not divided: use with external oscillator

= configuration for Philips PR31500/PR31700 host bus interface

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4.3 Memory Mapping and Aliasing

The PR31500/PR31700 uses a portion of the PC Card Attribute and IO space to access the

S1D13505. The S1D13505 responds to both PC Card Attribute and IO bus accesses, thus

freeing the programmer from having to set the PR31500/PR31700 Memory Configuration

PR31500/PR31700 sees the S1D13505 on its PC Card slot as described in the table below.

Table 4-2: PR31500/PR31700 to PC Card Slots Address Remapping for Direct Connection

S1D13505 Uses PC Card Slot #

Philips Address

Size

Function

0800 0000h

16M byte

Card 1 IO or Attribute

S1D13505 registers,

0900 0000h

0980 0000h

8M byte

aliased 4 times at 2M byte intervals

S1D13505 display buffer,

aliased 4 times at 2M byte intervals

Card 1 IO or Attribute

Card 1 Memory

0A00 0000h

6400 0000h

0C00 0000h

32M byte

64M byte

16M byte

Card 2 IO or Attribute

S1D13505 registers,

0D00 0000h

0D80 0000h

8M byte

aliased 4 times at 2M byte intervals

S1D13505 display buffer,

aliased 4 times at 2M byte intervals

Card 2 IO or Attribute

0E00 0000h

6800 0000h

32M byte

64M byte

Card 2 Memory

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5 System Design Using the IT8368E PC Card Buffer

In a system design using one or two ITE IT8368E PC Card and multiple-function IO

buffers, the S1D13505 can be interfaced so as to share one of the PC Card slots.

5.1 Hardware Description

The IT8368E can be programmed to allocate the same portion of the PC Card Attribute and

IO space to the S1D13505 as in the direct connection implementation described in Section

4, “Direct Connection to the Philips PR31500/PR31700 ” on page 11.

Following is a block diagram showing an implementation using the IT8368E PC Card

buffer.

PR31500/

S1D13505

PR31700

PC Card

IT8368E

Device

PC Card

IT8368E

Device

Figure 5-1: IT8368E Implementation Block Diagram

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5.2 IT8368E Configuration

The ITE IT8368E has been specifically designed to support EPSON LCD/CRT controllers.

Older EPSON Controllers not supporting a direct interface to the Philips processor can

utilize the IT8368E MFIO pins to provide the necessary control signals, however when

using the S1D13505 this is not necessary as the Direct Connection described in Section 4,

“Direct Connection to the Philips PR31500/PR31700 ” on page 11 can be used.

The IT8368E must have both “Fix Attribute/IO” and “VGA” modes enabled. When both

these modes are enabled a 16M byte portion of the system PC Card attribute and IO space

is allocated to address the S1D13505.

When the IT8368E senses that the S1D13505 is being accessed, it does not propagate the

PC Card signals to its PC Card device. This makes S1D13505 accesses transparent to any

PC Card device connected to the same slot.

For mapping details, refer to Section 4.3, “Memory Mapping and Aliasing ” on page 13. For

further information on configuring the IT8368E, refer to the IT8368E PC Card/GPIO

Buffer Chip Specification.

5.3 S1D13505 Configuration

For S1D13505 configuration, refer to Section 4.2, “S1D13505 Configuration ” on page 12.

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6 Software

Test utilities and Windows® CE v2.0 display drivers are available for the S1D13505. Full

source code is available for both the test utilities and the drivers.

The test utilities are configurable for different panel types using a program called

13505CFG, or by directly modifying the source. The Windows CE v2.0 display drivers can

be customized by the OEM for different panel types, resolutions and color depths only by

modifying the source.

The S1D13505 test utilities and Windows CE v2.0 display drivers are available from your

sales support contact or on the internet at http://www.eea.epson.com.

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7 References

7.1 Documents

• Philips Electronics, PR31500/PR31700 Preliminary Specifications.

• Epson Research and Development, Inc., S1D13505 Hardware Functional Specification,

Document Number X23A-A-001-xx.

• Epson Research and Development, Inc., S5U13505B00C Rev. 1.0 ISA Bus Evaluation

Board User Manual, Document Number X23A-G-004-xx.

• Epson Research and Development, Inc., S1D13505 Programming Notes and Examples,

Document Number X23A-G-003-xx.

7.2 Document Sources

• Philips Electronics Website: http://www-us2.semiconductors.philips.com.

• Epson Electronics America Website: http://www.eea.epson.com.

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8 Technical Support

8.1 EPSON LCD/CRT Controllers (S1D13505)

Taiwan, R.O.C.

Epson Taiwan Technology

& Trading Ltd.

North America

Japan

Epson Electronics America, Inc.

150 River Oaks Parkway

San Jose, CA 95134, USA

Tel: (408) 922-0200

Fax: (408) 922-0238

http://www.eea.epson.com

Seiko Epson Corporation

Electronic Devices Marketing Division

421-8, Hino, Hino-shi

Tokyo 191-8501, Japan

Tel: 042-587-5812

10F, No. 287

Nanking East Road

Sec. 3, Taipei, Taiwan, R.O.C.

Tel: 02-2717-7360

Fax: 02-2712-9164

Fax: 042-587-5564

http://www.epson.co.jp

Singapore

Epson Singapore Pte., Ltd.

No. 1

Temasek Avenue #36-00

Millenia Tower

Singapore, 039192

Tel: 337-7911

Hong Kong

Europe

Epson Hong Kong Ltd.

20/F., Harbour Centre

25 Harbour Road

Wanchai, Hong Kong

Tel: 2585-4600

Epson Europe Electronics GmbH

Riesstrasse 15

80992 Munich, Germany

Tel: 089-14005-0

Fax: 089-14005-110

Fax: 2827-4346

Fax: 334-2716

8.2 Philips MIPS PR31500/PR31700 Processor

Philips Semiconductors

Handheld Computing Group

4811 E. Arques Avenue

M/S 42, P.O. Box 3409

Sunnyvale, CA 94088-3409

Tel: (408) 991-2313

http://www.philips.com

8.3 ITE IT8368E

Integrated Technology Express, Inc.

Sales & Marketing Division

2710 Walsh Avenue

Santa Clara, CA 95051, USA

Tel: (408) 980-8168

Fax: (408) 980-9232

http://www.iteusa.com

S1D13505

X23A-G-001-07

Interfacing to the Philips MIPS PR31500/PR31700 Processor

Issue Date: 01/02/05

S1D13505 Embedded RAMDAC LCD/CRT Controller

Interfacing to the PC Card Bus

Document Number: X23A-G-005-06

Information in this document is subject to change without notice. You may download and use this document, but only for your own use in

evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any

representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain

material protected under U.S. and/or International Patent laws.

EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.

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Table of Contents

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Interfacing to the PC Card Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.1 The PC Card System Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.1.1 PC Card Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.1.2 Memory Access Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

S1D13505 Host Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3.1 PC Card Host Bus Interface Pin Mapping . . . . . . . . . . . . . . . . . . . 11

3.2 PC Card Host Bus Interface Signals . . . . . . . . . . . . . . . . . . . . . . 12

PC Card to S1D13505 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.1 Hardware Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.2 S1D13505 Hardware Configuration . . . . . . . . . . . . . . . . . . . . . . 15

4.3 Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.4 Register/Memory Mapping . . . . . . . . . . . . . . . . . . . . . . . . . 16

Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.1 Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.2 Document Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

7.1 Epson LCD/CRT Controllers (S1D13505) . . . . . . . . . . . . . . . . . . . 19

7.2 PC Card Standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Interfacing to the PC Card Bus

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List of Tables

Table 3-1: PC Card Host Bus Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 4-1: Summary of Power-On/Reset Options . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 4-2: Register/Memory Mapping for Typical Implementation . . . . . . . . . . . . . . . . . 16

List of Figures

Figure 2-1: PC Card Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 2-2: PC Card Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Figure 4-1: Typical Implementation of PC Card to S1D13505 Interface. . . . . . . . . . . . . . . .14

Interfacing to the PC Card Bus

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1 Introduction

This application note describes the hardware and software environment required to provide

an interface between the S1D13505 Embedded RAMDAC LCD/CRT Controller and the

PC Card (PCMCIA) bus.

The designs described in this document are presented only as examples of how such

interfaces might be implemented. This application note will be updated as appropriate.

Please check the Epson Electronics America website at http://www.eea.epson.com for the

latest revision of this document before beginning any development.

We appreciate your comments on our documentation. Please contact us via email at

[email protected].

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2 Interfacing to the PC Card Bus

2.1 The PC Card System Bus

PC Card technology has gained wide acceptance in the mobile computing field as well as

in other markets due to its portability and ruggedness. This section is an overview of the

operation of the 16-bit PC Card interface conforming to the PCMCIA 2.0/JEIDA 4.1

Standard (or later).

2.1.1 PC Card Overview

The 16-bit PC Card provides a 26-bit address bus and additional control lines which allow

access to three 64M byte address ranges. These ranges are used for common memory space,

IO space, and attribute memory space. Common memory may be accessed by a host system

for memory read and write operations. Attribute memory is used for defining card specific

information such as configuration registers, card capabilities, and card use. IO space

maintains software and hardware compatibility with hosts such as the Intel x86

architecture, which address peripherals independently from memory space.

Bit notation follows the convention used by most micro-processors, the high bit being the

most significant. Therefore, signals A25 and D15 are the most significant bits for the

address and data busses respectively.

Support is provided for on-chip DMA controllers. To find further information on these

topics, refer to Section 6, “References ” on page 18.

PC Card bus signals are asynchronous to the host CPU bus signals. Bus cycles are started

with the assertion of the CE1# and/or the CE2# card enable signals. The cycle ends once

these signals are de-asserted. Bus cycles can be lengthened using the WAIT# signal.

Note

The PCMCIA 2.0/JEIDA 4.1 (and later) PC Card Standard support the two signals

WAIT# and RESET which are not supported in earlier versions of the standard. The

WAIT# signal allows for asynchronous data transfers for memory, attribute, and IO

access cycles. The RESET signal allows resetting of the card configuration by the reset

line of the host CPU.

2.1.2 Memory Access Cycles

A data transfer is initiated when a memory address is placed on the PC Card bus and one,

or both, of the card enable signals (CE1# and CE2#) are driven low. REG# must be inactive.

If only CE1# is driven low, 8-bit data transfers are enabled and A0 specifies whether the

even or odd data byte appears on data bus lines D[7:0]. If both CE1# and CE2# are driven

low, a 16-bit word transfer takes place. If only CE2# is driven low, an odd byte transfer

occurs on data lines D[15:8].

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During a read cycle, OE# (output enable) is driven low. A write cycle is specified by

driving OE# high and driving the write enable signal (WE#) low. The cycle can be

lengthened by driving WAIT# low for the time needed to complete the cycle.

Figure 2-1: illustrates a typical memory access read cycle on the PC Card bus.

A[25:0]

REG#

ADDRESS VALID

CE1#

CE2#

OE#

WAIT#

D[15:0]

Hi-Z

DATA VALID

Transfer Start

Transfer Complete

Figure 2-1: PC Card Read Cycle

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Figure 2-2: illustrates a typical memory access write cycle on the PC Card bus.

A[25:0]

REG#

ADDRESS VALID

CE1#

CE2#

OE#

WE#

WAIT#

Hi-Z

D[15:0]

DATA VALID

Transfer Complete

Transfer Start

Figure 2-2: PC Card Write Cycle

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3 S1D13505 Host Bus Interface

The S1D13505 implements a 16-bit PC Card (PCMCIA) host bus interface which is used

to interface to the PC Card bus.

The PC Card host bus interface is selected by the S1D13505 on the rising edge of RESET#.

After releasing reset the bus interface signals assume their selected configuration. For

details on S1D13505 configuration, see Section 4.2, “S1D13505 Hardware Configuration ”

on page 15.

Note

At reset, the Host Interface Disable bit in the Miscellaneous Disable Register

(REG[1Bh] bit 7) is set to 1. This means that only REG[1Ah] (read-only) and

REG[1Bh] are accessible until a write to REG[1Bh] sets bit 7 to 0 making all regis-

ters accessible. When debugging a new hardware design, this can sometimes give the

appearance that the interface is not working, so it is important to remember to clear this

bit before proceeding with debugging.

3.1 PC Card Host Bus Interface Pin Mapping

The following table shows the functions of each host bus interface signal.

Table 3-1: PC Card Host Bus Interface Pin Mapping

S1D13505 Pin Name

AB[20:0]

DB[15:0]

WE1#

PC Card (PCMCIA)

A[20:0]

D[15:0]

-CE2

M/R#

External Decode

CS#

BUSCLK

BS#

n/a

RD/WR#

RD#

-CE1

-OE

WE0#

-WE

WAIT#

-WAIT

RESET#

Inverted RESET

Note

The bus signal A0 is not used by the S1D13505 internally.

Although a clock is not directly supplied by the PC Card interface, one is required by

the S1D13505 PC Card host bus interface. For an example of how this can be accom-

plished see the discussion on BUSCLK in Section 3.2, “PC Card Host Bus Interface

Signals ” on page 12.

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3.2 PC Card Host Bus Interface Signals

The S1D13505 PC Card host bus interface is designed to support processors which

interface the S1D13505 through the PC Card bus.

The S1D13505 PC Card host bus interface requires the following signals from the PC Card

bus.

• BUSCLK is a clock input which is required by the S1D13505 host bus interface. It is

separate from the input clock (CLKI) and is typically driven by the host CPU system

clock. Since PC Card signalling is independent of any clock, BUSCLK can come from

any oscillator already implemented. For example, the source for the CLKI input of the

S1D13505 may be used.

• The address inputs AB[20:0], and the data bus DB[15:0], connect directly to the PC

Card address (A[20:0]) and data bus (D[15:0]), respectively. MD4 must be set to select

little endian mode upon reset.

• M/R# (memory/register) selects between memory or register access. It may be

connected to an address line, allowing system address A21 to be connected to the M/R#

line.

• Chip Select (CS#) must be driven low whenever the S1D13505 is accessed by the PC

Card bus.

• WE1# and RD/WR# connect to -CE2 and -CE1 (the byte enables for the high-order and

low-order bytes). They are driven low when the PC Card bus is accessing the

S1D13505.

• RD# connects to -OE (the read enable signal from the PC Card bus).

• WE0# connects to -WE (the write enable signal from the PC Card bus).

• WAIT# is a signal output from the S1D13505 that indicates the PC Card bus must wait

until data is ready (read cycle) or accepted (write cycle) on the host bus. Since PC Card

bus accesses to the S1D13505 may occur asynchronously to the display update, it is

possible that contention may occur in accessing the S1D13505 internal registers and/or

display buffer. The WAIT# line resolves these contentions by forcing the host to wait

until the resource arbitration is complete. For PC Card applications, this signal should

be set active low using the MD5 configuration input.

• The Bus Start (BS#) signal is not used for the PC Card host bus interface and should be

tied high (connected to V ).

• The RESET# (active low) input of the S1D13505 may be connected to the PC Card

RESET (active high) using an inverter.

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4 PC Card to S1D13505 Interface

4.1 Hardware Description

The S1D13505 is designed to directly support a variety of CPUs, providing an interface to

each processor’s unique “local bus”. However, in order to provide support for processors

not having an appropriate local bus, the S1D13505 supports a specific PC Card interface.

The S1D13505 provides a “glueless” interface to the PC Card bus except for the following.

• The RESET# signal on the S1D13505 is active low and must be inverted to support the

active high RESET provided by the PC Card interface.

• Although the S1D13505 supports an asynchronous bus interface, a clock source is

required on the BUSCLK input pin.

In this implementation, the address inputs (AB[20:0]) and data bus (DB[15:0]) connect

directly to the CPU address (A[20:0]) and data bus (D[15:0]). M/R# is treated as an address

line so that it can be controlled using system address A21.

The PC Card interface does not provide a bus clock, so one must be supplied for the

S1D13505. Since the bus clock frequency is not critical, nor does it have to be synchronous

to the bus signals, it may be the same as CLKI. BS# (bus start) is not used and should be

tied high (connected to V ).

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The following diagram shows a typical implementation of the PC Card to S1D13505

interface.

PC Card socket

S1D13505

-OE

-WE

RD#

WE0#

-CE1

-CE2

RD/WR#

WE1#

RESET

RESET#

BS#

CS#

A21

A[20:0]

M/R#

AB[20:0]

DB[15:0]

A[21:0]

D[15:0]

15K

WAIT#

BUSCLK

CLKI

Oscillator

Note:

When connecting the S1D13505 RESET# pin, the system designer should be aware of all

conditions that may reset the S1D13505 (e.g. CPU reset can be asserted during wake-up

from power-down modes, or during debug states).

Figure 4-1: Typical Implementation of PC Card to S1D13505 Interface

S1D13505

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4.2 S1D13505 Hardware Configuration

The S1D13505 latches MD15 through MD0 to allow selection of the bus mode and other

configuration data on the rising edge of RESET#. For details on configuration, refer to the

S1D13505 Hardware Functional Specification, document number X23A-A-001-xx.

The table below shows only those configuration settings important to the PC Card host bus

interface.

Table 4-1: Summary of Power-On/Reset Options

value on this pin at rising edge of RESET# is used to configure:(1/0)

S1D13505

Pin Name

MD0

8-bit host bus interface

16-bit host bus interface

Big Endian

MD[3:1]

MD4

111 = PC Card host bus interface selected

Little Endian

MD5

WAIT# is active high (1 = insert wait state)

WAIT# is active low (0 = insert wait state)

MD11

MD12

Alternate Host Bus Interface Selected

BUSCLK input divided by two

Primary Host Bus Interface Selected

BUSCLK input not divided by two

= configuration for PC Card host bus interface

4.3 Performance

The S1D13505 PC Card Interface specification supports a BCLK up to 50MHz, and

therefore can provide a high performance display solution.

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4.4 Register/Memory Mapping

The S1D13505 is a memory mapped device. The internal registers require 47 bytes and are

mapped in the lower PC Card memory address space starting at zero.The display buffer

requires 2M bytes and is mapped in the third and fourth megabytes of the PC Card address

space (ranging from 200000h to 3FFFFFh).

A typical implementation as shown in Figure 4-1: “Typical Implementation of PC Card to

S1D13505 Interface,” on page 14 has Chip Select (CS#) connected to ground (always

enabled) and the Memory/Register select pin (M/R#) connected to address bit A21. This

provides the following decoding:

Table 4-2: Register/Memory Mapping for Typical Implementation

CS#

M/R# (A21)

Address Range

Function

Internal Register

Set decoded

0 - 1F FFFFh

Display Buffer

decode

20 0000h - 3F FFFFh

The PC Card socket provides 64M byte of address space. Without further resolution on the

decoding logic (M/R# connected to A21), the entire register set is aliased for every 64 byte

boundary within the specified address range above. Since address bits A[25:22] are

ignored, the S1D13505 registers and display buffer are aliased 16 times.

Note

If aliasing is not desirable, the upper addresses must be fully decoded.

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5 Software

Test utilities and Windows® CE v2.0 display drivers are available for the S1D13505. Full

source code is available for both the test utilities and the drivers.

The test utilities are configurable for different panel types using a program called

13505CFG, or by directly modifying the source. The Windows CE v2.0 display drivers can

be customized by the OEM for different panel types, resolutions and color depths only by

modifying the source.

The S1D13505 test utilities and Windows CE v2.0 display drivers are available from your

sales support contact or on the internet at http://www.eea.epson.com.

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6 References

6.1 Documents

• PC Card (PCMCIA) Standard, March 1997

• Epson Research and Development, Inc., S1D13505 Hardware Functional Specification,

Document Number X23A-A-001-xx.

• Epson Research and Development, Inc., S1D13505 Programming Notes and Examples,

Document Number X23A-G-003-xx.

• Epson Research and Development, Inc., S5U13505B00C Rev. 1.0 ISA Bus Evaluation

Board User Manual, Document Number X23A-G-004-xx.

6.2 Document Sources

• PC Card Website: http://www.pc-card.com.

• Epson Electronics America Website: http://www.eea.epson.com.

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7 Technical Support

7.1 Epson LCD/CRT Controllers (S1D13505)

Japan

Seiko Epson Corporation

Electronic Devices Marketing Division

421-8, Hino, Hino-shi

North America

Epson Electronics America, Inc.

150 River Oaks Parkway

San Jose, CA 95134, USA

Taiwan, R.O.C.

Epson Taiwan Technology

& Trading Ltd.

10F, No. 287

Tokyo 191-8501, Japan

Tel: (408) 922-0200

Nanking East Road

Sec. 3, Taipei, Taiwan, R.O.C.

Tel: 02-2717-7360

Fax: 02-2712-9164

Tel: 042-587-5812

Fax: (408) 922-0238

http://www.eea.epson.com

Fax: 042-587-5564

http://www.epson.co.jp

Singapore

Europe

Hong Kong

Epson Singapore Pte., Ltd.

No. 1

Temasek Avenue #36-00

Millenia Tower

Singapore, 039192

Tel: 337-7911

Fax: 334-2716

Epson Europe Electronics GmbH

Riesstrasse 15

80992 Munich, Germany

Tel: 089-14005-0

Epson Hong Kong Ltd.

20/F., Harbour Centre

25 Harbour Road

Wanchai, Hong Kong

Tel: 2585-4600

Fax: 089-14005-110

Fax: 2827-4346

7.2 PC Card Standard

PCMCIA

(Personal Computer Memory Card International Association)

2635 North First Street, Suite 209

San Jose, CA 95134, USA

Tel: (408) 433-2273

Fax: (408) 433-9558

http://www.pc-card.com

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S1D13505

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Issue Date: 01/02/05

S1D13505 Embedded RAMDAC LCD/CRT Controller

Interfacing to the NEC

VR4102/VR4111™ Microprocessors

Document Number: X23A-G-007-06

Information in this document is subject to change without notice. You may download and use this document, but only for your own use in

evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any

representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain

material protected under U.S. and/or International Patent laws.

EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.

Microsoft and Windows are registered trademarks of Microsoft Corporation.

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Table of Contents

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Interfacing to the VR4102/VR4111 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.1 The NEC VR4102/VR4111 System Bus . . . . . . . . . . . . . . . . . . . . . 8

2.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.1.2 LCD Memory Access Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

S1D13505 Host Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.1 Host Bus Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . 10

3.2 Host Bus Interface Signals Descriptions . . . . . . . . . . . . . . . . . . . . 11

VR4102/VR4111 to S1D13505 Interface . . . . . . . . . . . . . . . . . . . . . . . . 12

4.1 Hardware Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.2 S1D13505 Hardware Configuration . . . . . . . . . . . . . . . . . . . . . . 13

4.3 NEC VR4102/VR4111 Configuration . . . . . . . . . . . . . . . . . . . . . 13

Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6.1 Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6.2 Document Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

7.1 EPSON LCD/CRT Controllers (S1D13505) . . . . . . . . . . . . . . . . . . 16

7.2 NEC Electronics Inc. (VR4102/VR4111). . . . . . . . . . . . . . . . . . . . 16

Interfacing to the NEC VR4102/VR4111™ Microprocessors

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List of Tables

Table 3-1: Host Bus Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 4-1: Summary of Power-On/Reset Options . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

List of Figures

Figure 2-1: NEC VR4102/VR4111 Read/Write Cycles . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 4-1: NEC VR4102/VR4111 to S1D13505 Configuration Schematic . . . . . . . . . . . . . .12

Interfacing to the NEC VR4102/VR4111™ Microprocessors

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1 Introduction

This application note describes the hardware and software environment necessary to

provide an interface between the S1D13505 Embedded RAMDAC LCD/CRT Controller

and the NEC V^R4102 (µPD30102) or V^R4111 (µPD30111) Microprocessors.

The designs described in this document are presented only as examples of how such

interfaces might be implemented. This application note will be updated as appropriate.

Please check the Epson Electronics America Website at http://www.eea.epson.com for the

latest revision of this document before beginning any development.

We appreciate your comments on our documentation. Please contact us via email at

[email protected].

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2 Interfacing to the VR4102/VR4111

2.1 The NEC VR4102/VR4111 System Bus

The VR-Series family of microprocessors features a high-speed synchronous system bus

typical of modern microprocessors. Designed with external LCD controller support and

Windows CE based embedded consumer applications in mind, the VR4102/VR4111 offers

a highly integrated solution for portable systems. This section provides an overview of the

operation of the CPU bus in order to establish interface requirements.

2.1.1 Overview

The NEC VR4102/VR4111 is designed around the RISC architecture developed by MIPS.

This microprocessor is based on the 66MHz VR4100 CPU core which supports 64-bit

processing. The CPU communicates with the Bus Control Unit (BCU) using its internal

SysAD bus. The BCU in turn communicates with external devices using its ADD and DAT

buses which can be dynamically sized for 16 or 32-bit operation.

The NEC VR4102/VR4111 has direct support for an external LCD controller. Specific

control signals are assigned for an external LCD controller providing an easy interface to

the CPU. A 16M byte block of memory is assigned for the LCD controller and its own chip

select and ready signals are available. Word or byte accesses are controlled by the system

high byte signal (SHB#).

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2.1.2 LCD Memory Access Cycles

Once an address in the LCD block of memory is placed on the external address bus

(ADD[25:0]), the LCD chip select (LCDCS#) is driven low. The read or write enable

signals (RD# or WR#) are driven low for the appropriate cycle and LCDRDY is driven low

to insert wait states into the cycle. The high byte enable (SHB#) in conjunction with address

bit 0 allows for byte steering.

The following figure illustrates typical NEC VR4102/VR4111 memory read and write

cycles to the LCD controller interface.

TCLK

ADD[25:0]

VALID

SHB#

LCDCS#

WR#,RD#

D[15:0]

(write)

VALID

Hi-Z

D[15:0]

(read)

Hi-Z

VALID

LCDRDY

Figure 2-1: NEC VR4102/VR4111 Read/Write Cycles

Interfacing to the NEC VR4102/VR4111™ Microprocessors

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3 S1D13505 Host Bus Interface

The S1D13505 directly supports multiple processors. The S1D13505 implements a 16-bit

MIPS/ISA Host Bus Interface which is most suitable for direct connection to the

VR4102/VR4111 microprocessor.

The MIPS/ISA host bus interface is selected by the S1D13505 on the rising edge of

RESET#. After releasing reset the bus interface signals assume their selected configuration.

For details on S1D13505 configuration, see Section 4.2, “S1D13505 Hardware Configu-

ration ” on page 13.

Note

At reset, the Host Interface Disable bit in the Miscellaneous Disable Register

(REG[1Bh] bit 7) is set to 1. This means that only REG[1Ah] (read-only) and

REG[1Bh] are accessible until a write to REG[1Bh] sets bit 7 to 0 making all regis-

ters accessible. When debugging a new hardware design, this can sometimes give the

appearance that the interface is not working, so it is important to remember to clear this

bit before proceeding with debugging.

3.1 Host Bus Interface Pin Mapping

The following table shows the functions of each host bus interface signal.

Table 3-1: Host Bus Interface Pin Mapping

S1D13505 Pin Name

AB20

NEC VR4102/VR4111 Pin Name

ADD20

ADD[19:0]

DAT[15:0]

SHB#

AB[19:0]

DB[15:0]

WE1#

M/R#

ADD21

CS#

LCDCS#

BUSCLK

BS#

Connected to V

RD#

RD/WR#

RD#

WE0#

WR#

WAIT#

LCDRDY

RESET#

connected to system reset

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3.2 Host Bus Interface Signals Descriptions

The S1D13505 MIPS/ISA Host Bus Interface requires the following signals.

• BUSCLK is a clock input which is required by the S1D13505 Host Bus Interface. It is

separate from the input clock (CLKI) and is typically driven by the host CPU system

clock.

• The address inputs AB[20:0], and the data bus DB[15:0], connect directly to the

VR4102/VR4111 address (ADD[20:0]) and data bus (DAT[15:0]), respectively. MD4

must be set to select the proper endian mode upon reset.

• M/R# (memory/register) selects between memory or register access. It may be

connected to an address line, allowing system address ADD21 to be connected to the

M/R# line.

• Chip Select (CS#) must be driven low by LCDCS# whenever the S1D13505 is accessed

by the VR4102/VR4111.

• WE1# connects to SHB# (the high byte enable signal from the VR4102/VR4111) which

in conjunction with address bit 0 allows byte steering of read and write operations.

• WE0# connects to WR# (the write enable signal from the VR4102/VR4111) and must

be driven low when the VR4102/VR4111 is writing data to the S1D13505.

• RD# connects to RD# (the read enable signal from the VR4102/VR4111) and must be

driven low when the VR4102/VR4111 is reading data from the S1D13505.

• WAIT# connects to LCDRDY and is a signal output from the S1D13505 that indicates

the VR4102/VR4111 must wait until data is ready (read cycle) or accepted (write cycle)

on the host bus. Since VR4102/VR4111 accesses to the S1D13505 may occur asynchro-

nously to the display update, it is possible that contention may occur in accessing the

S1D13505 internal registers and/or display buffer. The WAIT# line resolves these

contentions by forcing the host to wait until the resource arbitration is complete.

• The BS# and RD/WR# signals are not used for the MIPS/ISA Host Bus Interface and

should be tied high (connected to V ).

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4 VR4102/VR4111 to S1D13505 Interface

4.1 Hardware Description

The NEC V^R4102/V^R4111 Microprocessors are specifically designed to support an external

LCD controller. They provide the necessary internal address decoding and control signals.

The diagram below shows a typical implementation utilizing the S1D13505.

NEC VR4102/VR4111

S1D13505

WR#

WE0#

SHB#

WE1#

RD#

CS#

LCDCS#

LCDRDY

Pull-up

WAIT#

M/R#

ADD21

System RESET

RESET#

AB[20:0]

ADD[25:0]

DAT[15:0]

DB[15:0]

BUSCLK

V_DD

BS#

RD/WR#

Note:

When connecting the S1D13505 RESET# pin, the system designer should be aware of all

conditions that may reset the S1D13505 (e.g. CPU reset can be asserted during wake-up

from power-down modes, or during debug states).

Figure 4-1: NEC V^R4102/V^R4111 to S1D13505 Configuration Schematic

Note

For pin mapping see Table 3-1:, “Host Bus Interface Pin Mapping,” on page 10.

S1D13505

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4.2 S1D13505 Hardware Configuration

The S1D13505 latches MD15 through MD0 to allow selection of the bus mode and other

configuration data on the rising edge of RESET#. For details on configuration, refer to the

S1D13505 Hardware Functional Specification, document number X23A-A-001-xx.

The table below shows those configuration settings important to the NEC V^R4102/V^R4111

CPU interface.

Table 4-1: Summary of Power-On/Reset Options

value on this pin at rising edge of RESET# is used to configure:(1/0)

S1D13505

Pin Name

MD0

8-bit host bus interface

16-bit host bus interface

Big Endian

MD[3:1]

MD4

101 = MIPS/ISA bus interface

Little Endian

MD5

WAIT# is active high (1 = insert wait state)

WAIT# is active low (0 = insert wait state)

MD11

Alternate Host Bus Interface Selected

Primary Host Bus Interface Selected

= configuration for NEC VR4102/VR4111 microprocessor

4.3 NEC V^R4102/V^R4111 Configuration

NEC V^R4102/V^R4111The NEC V^R4102/V^R4111 provides the internal address decoding

necessary to map an external LCD controller. Physical address 0A00 0000h to 0AFF

FFFFh (16M bytes) is reserved for an external LCD controller.

The S1D13505 supports up to 2M bytes of display buffer. The NEC V^R4102/V^R4111

address line A21 is used to select between the S1D13505 display buffer (A21=1) and

internal registers (A21=0).

The NEC V^R4102/V^R4111 has a 16-bit internal register named BCUCNTREG2 located at

address 0B00 0002h. It must be set to the value of 0001h to indicate that LCD controller

accesses using a non-inverting data bus.

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5 Software

Test utilities and Windows® CE v2.0 display drivers are available for the S1D13505. Full

source code is available for both the test utilities and the drivers.

The test utilities are configurable for different panel types using a program called

13505CFG, or by directly modifying the source. The Windows CE v2.0 display drivers can

be customized by the OEM for different panel types, resolutions and color depths only by

modifying the source.

The S1D13505 test utilities and Windows CE v2.0 display drivers are available from your

sales support contact or on the internet at http://www.eea.epson.com.

S1D13505

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6 References

6.1 Documents

• NEC Electronics Inc., VR4102 Preliminary Users Manual, Document Number

U12739EJ2V0UM00.

• NEC Electronics Inc., VR4111 Preliminary Users Manual, Document Number

U13137EJ2V0UM00.

• Epson Research and Development, Inc., S1D13505 Hardware Functional Specification,

Document Number X23A-A-001-xx.

• Epson Research and Development, Inc., S5U13505B00C Rev. 1.0 ISA Bus Evaluation

Board User Manual, Document Number X23A-G-004-xx.

• Epson Research and Development, Inc., S1D13505 Programming Notes and Examples,

Document Number X23A-G-003-xx.

6.2 Document Sources

• NEC Electronics Website: http://www.necel.com.

• Epson Electronics America Website: http://www.eea.epson.com.

Interfacing to the NEC VR4102/VR4111™ Microprocessors

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7 Technical Support

7.1 EPSON LCD/CRT Controllers (S1D13505)

Japan

Seiko Epson Corporation

North America

Epson Electronics America, Inc.

Taiwan, R.O.C.

Epson Taiwan Technology

& Trading Ltd.

Electronic Devices Marketing Division

150 River Oaks Parkway

421-8, Hino, Hino-shi

San Jose, CA 95134, USA

10F, No. 287

Tokyo 191-8501, Japan

Tel: (408) 922-0200

Nanking East Road

Sec. 3, Taipei, Taiwan, R.O.C.

Tel: 02-2717-7360

Fax: 02-2712-9164

Tel: 042-587-5812

Fax: (408) 922-0238

http://www.eea.epson.com

Fax: 042-587-5564

http://www.epson.co.jp

Singapore

Europe

Hong Kong

Epson Singapore Pte., Ltd.

No. 1

Temasek Avenue #36-00

Millenia Tower

Singapore, 039192

Tel: 337-7911

Fax: 334-2716

Epson Europe Electronics GmbH

Riesstrasse 15

80992 Munich, Germany

Tel: 089-14005-0

Epson Hong Kong Ltd.

20/F., Harbour Centre

25 Harbour Road

Wanchai, Hong Kong

Tel: 2585-4600

Fax: 089-14005-110

Fax: 2827-4346

7.2 NEC Electronics Inc. (V^R4102/V^R4111).

NEC Electronics Inc. (U.S.A.)

Corporate Headquarters

2880 Scott Blvd.

Santa Clara, CA 95050-8062, USA

Tel: (800) 366-9782

Fax: (800) 729-9288

http://www.nec.com

S1D13505

Interfacing to the NEC VR4102/VR4111™ Microprocessors

X23A-G-007-06

Issue Date: 01/02/05

S1D13505 Embedded RAMDAC LCD/CRT Controller

Interfacing to the Motorola MPC821

Microprocessor

Document Number: X23A-G-008-05

Information in this document is subject to change without notice. You may download and use this document, but only for your own use in

evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any

representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain

material protected under U.S. and/or International Patent laws.

EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.

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Table of Contents

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Interfacing to the MPC821 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.1 The MPC8xx System Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.2 MPC821 Bus Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.2.1 Normal (Non-Burst) Bus Transactions . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.2.2 Burst Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.3 Memory Controller Module . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.3.1 General-Purpose Chip Select Module (GPCM) . . . . . . . . . . . . . . . . . . . . 11

2.3.2 User-Programmable Machine (UPM) . . . . . . . . . . . . . . . . . . . . . . . . . 12

S1D13505 Host Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.1 PowerPC Host Bus Interface Pin Mapping . . . . . . . . . . . . . . . . . . . 13

3.2 PowerPC Host Bus Interface Signals . . . . . . . . . . . . . . . . . . . . . 14

MPC821 to S1D13505 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.1 Hardware Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.2 Hardware Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.3 S1D13505 Hardware Configuration . . . . . . . . . . . . . . . . . . . . . . 18

4.4 Register/Memory Mapping . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.5 MPC821 Chip Select Configuration . . . . . . . . . . . . . . . . . . . . . . 19

4.6 Test Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6.1 Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6.2 Document Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

7.1 EPSON LCD/CRT Controllers (S1D13505) . . . . . . . . . . . . . . . . . . 23

7.2 Motorola MPC821 Processor . . . . . . . . . . . . . . . . . . . . . . . . 23

Interfacing to the Motorola MPC821 Microprocessor

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List of Tables

Table 3-1: PowerPC Host Bus Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 4-1: List of Connections from MPC821ADS to S1D13505 . . . . . . . . . . . . . . . . . . 16

Table 4-2: Summary of Power-On/Reset Options . . . . . . . . . . . . . . . . . . . . . . . . . . 18

List of Figures

Figure 2-1: Power PC Memory Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 2-2: Power PC Memory Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Figure 4-1: Typical Implementation of MPC821 to S1D13505 Interface . . . . . . . . . . . . . . .15

Interfacing to the Motorola MPC821 Microprocessor

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1 Introduction

This application note describes the hardware and software environment required to provide

an interface between the S1D13505 Embedded RAMDAC LCD/CRT Controller and the

Motorola MPC821 processor.

The designs described in this document are presented only as examples of how such

interfaces might be implemented. This application note will be updated as appropriate.

Please check the Epson Electronics America Website at http://www.eea.epson.com for the

latest revision of this document before beginning any development.

We appreciate your comments on our documentation. Please contact us via email at

[email protected].

Interfacing to the Motorola MPC821 Microprocessor

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2 Interfacing to the MPC821

2.1 The MPC8xx System Bus

The MPC8xx family of processors feature a high-speed synchronous system bus typical of

modern RISC microprocessors. This section provides an overview of the operation of the

CPU bus in order to establish interface requirements.

2.2 MPC821 Bus Overview

The MPC8xx microprocessor family uses a synchronous address and data bus. All IO is

synchronous to a square-wave reference clock called MCLK (Master Clock). This clock

runs at the machine cycle speed of the CPU core (typically 25 to 50 MHz). Most outputs

from the processor change state on the rising edge of this clock. Similarly, most inputs to

the processor are sampled on the rising edge.

Note

The external bus can run at one-half the CPU core speed using the clock control register.

This is typically used when the CPU core is operated above 50 MHz.

The MPC821 can generate up to eight independent chip select outputs, each of which may

be controlled by one of two types of timing generators: the General Purpose Chip Select

Module (GPCM) or the User-Programmable Machine (UPM). Examples are given using

the GPCM.

It should be noted that all Power PC microprocessors, including the MPC8xx family, use

bit notation opposite from the convention used by most other microprocessor systems. Bit

numbering for the MPC8xx always starts with zero as the most significant bit, and incre-

ments in value to the least-significant bit. For example, the most significant bits of the

address bus and data bus are A0 and D0, while the least significant bits are A31 and D31.

The MPC8xx uses both a 32-bit address and data bus. A parity bit is supported for each of

the four byte lanes on the data bus. Parity checking is done when data is read from external

memory or peripherals, and generated by the MPC8xx bus controller on write cycles. All

IO accesses are memory-mapped meaning there is no separate IO space in the Power PC

architecture.

Support is provided for both on-chip (DMA controllers) and off-chip (other processors and

peripheral controllers) bus masters. For further information on this topic, refer to Section

6, “References ” on page 22.

The bus can support both normal and burst cycles. Burst memory cycles are used to fill

on-chip cache memory, and for certain on-chip DMA operations. Normal cycles are used

for all other data transfers.

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2.2.1 Normal (Non-Burst) Bus Transactions

A data transfer is initiated by the bus master by placing the memory address on address

lines A0 through A31 and driving TS (Transfer Start) low for one clock cycle. Several

control signals are also provided with the memory address:

• TSIZ[0:1] (Transfer Size) -- indicates whether the bus cycle is 8, 16, or 32-bit.

• RD/WR -- set high for read cycles and low for write cycles.

• AT[0:3] (Address Type Signals) -- provides more detail on the type of transfer being

attempted.

When the peripheral device being accessed has completed the bus transfer, it asserts TA

(Transfer Acknowledge) for one clock cycle to complete the bus transaction. Once TA has

been asserted, the MPC821 will not start another bus cycle until TA has been de-asserted.

The minimum length of a bus transaction is two bus clocks.

Figure 2-1: “Power PC Memory Read Cycle ” on page 9 illustrates a typical memory read

cycle on the Power PC system bus.

SYSCLK

A[0:31]

RD/WR

TSIZ[0:1], AT[0:3]

D[0:31]

Transfer Start

Sampled when TA low

Wait States

Transfer

Next Transfer

Starts

Complete

Figure 2-1: Power PC Memory Read Cycle

Interfacing to the Motorola MPC821 Microprocessor

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Figure 2-2: “Power PC Memory Write Cycle ” on page 10 illustrates a typical memory

write cycle on the Power PC system bus.

SYSCLK

A[0:31]

RD/WR

TSIZ[0:1], AT[0:3]

D[0:31]

Transfer Start

Valid

Wait States

Transfer

Next Transfer

Starts

Complete

Figure 2-2: Power PC Memory Write Cycle

If an error occurs, TEA (Transfer Error Acknowledge) is asserted and the bus cycle is

aborted. For example, a peripheral device may assert TEA if a parity error is detected, or

the MPC821 bus controller may assert TEA if no peripheral device responds at the

addressed memory location within a bus time-out period.

For 32-bit transfers, all data lines (D[0:31]) are used and the two low-order address lines

A30 and A31 are ignored. For 16-bit transfers, data lines D[0:15] are used and address line

A31 is ignored. For 8-bit transfers, data lines D[0:7] are used and all address lines (A[0:31])

are used.

Note

This assumes that the Power PC core is operating in big endian mode (typically the case

for embedded systems).

2.2.2 Burst Cycles

Burst memory cycles are used to fill on-chip cache memory and to carry out certain on-chip

DMA operations. They are very similar to normal bus cycles with the following exceptions:

• Always 32-bit.

• Always attempt to transfer four 32-bit words sequentially.

• Always address longword-aligned memory (i.e. A30 and A31 are always 0:0).

• Do not increment address bits A28 and A29 between successive transfers; the addressed

device must increment these address bits internally.

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If a peripheral is not capable of supporting burst cycles, it can assert Burst Inhibit (BI)

simultaneously with TA, and the processor will revert to normal bus cycles for the

remaining data transfers.

Burst cycles are mainly intended to facilitate cache line fills from program or data memory.

They are normally not used for transfers to/from IO peripheral devices such as the

S1D13505, therefore the interfaces described in this document do not attempt to support

burst cycles. However, the example interfaces include circuitry to detect the assertion of

BDIP and respond with BI if caching is accidently enabled for the S1D13505 address space.

2.3 Memory Controller Module

2.3.1 General-Purpose Chip Select Module (GPCM)

The General-Purpose Chip Select Module (GPCM) is used to control memory and

peripheral devices which do not require special timing or address multiplexing. In addition

to the chip select output, it can generate active-low Output Enable (OE) and Write Enable

(WE) signals compatible with most memory and x86-style peripherals. The MPC821 bus

controller also provides a Read/Write (RD/WR) signal which is compatible with most 68K

peripherals.

The GPCM is controlled by the values programmed into the Base Register (BR) and Option

block size of the chip select, and controls the following timing parameters:

• The ACS bit field allows the chip select assertion to be delayed by 0, ¼, or ½ clock

cycle with respect to the address bus valid.

• The CSNT bit causes chip select and WE to be negated ½ clock cycle earlier than

normal.

• The TRLX (relaxed timing) bit will insert an additional one clock delay between

assertion of the address bus and chip select. This accommodates memory and

peripherals with long setup times.

• The EHTR (Extended hold time) bit will insert an additional 1 clock delay on the first

access to a chip select.

• Up to 15 wait states may be inserted, or the peripheral can terminate the bus cycle itself

by asserting TA (Transfer Acknowledge).

• Any chip select may be programmed to assert BI (Burst Inhibit) automatically when its

memory space is addressed by the processor core.

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2.3.2 User-Programmable Machine (UPM)

The UPM is typically used to control memory types, such as Dynamic RAMs, which have

complex control or address multiplexing requirements. The UPM is a general purpose

RAM-based pattern generator which can control address multiplexing, wait state gener-

ation, and five general-purpose output lines on the MPC821. Up to 64 pattern locations are

available, each 32 bits wide. Separate patterns may be programmed for normal accesses,

burst accesses, refresh (timer) events, and exception conditions. This flexibility allows

almost any type of memory or peripheral device to be accommodated by the MPC821.

In this application note, the GPCM is used instead of the UPM, since the GPCM has enough

flexibility to accommodate the S1D13505 and it is desirable to leave the UPM free to

handle other interfacing duties, such as EDO DRAM.

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3 S1D13505 Host Bus Interface

The S1D13505 implements a 16-bit native PowerPC host bus interface which is used to

interface to the MPC821 microprocessor.

The PowerPC host bus interface is selected by the S1D13505 on the rising edge of

RESET#. After releasing reset the bus interface signals assume their selected configuration.

For details on S1D13505 configuration, see Section 4.3, “S1D13505 Hardware Configu-

ration ” on page 18.

Note

At reset, the Host Interface Disable bit in the Miscellaneous Disable Register

(REG[1Bh] bit 7) is set to 1. This means that only REG[1Ah] (read-only) and

REG[1Bh] are accessible until a write to REG[1Bh] sets bit 7 to 0 making all regis-

ters accessible. When debugging a new hardware design, this can sometimes give the

appearance that the interface is not working, so it is important to remember to clear this

bit before proceeding with debugging.

3.1 PowerPC Host Bus Interface Pin Mapping

The following table shows the functions of each host bus interface signal.

Table 3-1: PowerPC Host Bus Interface Pin Mapping

S1D13505

PowerPC

Pin Names

AB[20:0]

DB[15:0]

WE1#

A[11:31]

D[0:15]

M/R#

External Decode

CLKOUT

CS#

BUSCLK

BS#

RD/WR#

RD#

RD/WR

TSIZ0

WE0#

TSIZ1

WAIT#

RESET#

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3.2 PowerPC Host Bus Interface Signals

The interface requires the following signals:

• BUSCLK is a clock input which is required by the S1D13505 host bus interface. It is

separate from the input clock (CLKI) and is typically driven by the host CPU system

clock.

• The address inputs AB[20:0], and the data bus DB[15:0], connect directly to the

PowerPC bus address (A[11:31]) and data bus (D[0:15]), respectively. MD4 must be set

to select the proper endian mode upon reset.

• M/R# (memory/register) selects between memory or register access. It may be

connected to an address line, allowing system address A10 to be connected to the M/R#

line.

• Chip Select (CS#) must be driven low whenever the S1D13505 is accessed by the

PowerPC bus.

• RD/WR# connects to RD/WR which indicates whether a read or a write access is being

performed on the S1D13505.

• WE1# connects to BI (burst inhibit signal). WE1# is output by the S1D13505 to indicate

whether the S1D13505 is able to perform burst accesses.

• WE0# and RD# connect to TSIZ1 and TSIZ0 (high and low byte enable signals). These

signals must be driven by the PowerPC bus to indicate the size of the transfer taking

place on the bus.

• WAIT# connects to TA and is output from the S1D13505 that indicates the PowerPC

bus must wait until data is ready (read cycle) or accepted (write cycle) on the host bus.

Since the PowerPC bus accesses to the S1D13505 may occur asynchronously to the

display update, it is possible that contention may occur in accessing the S1D13505

internal registers and/or display buffer. The WAIT# line resolves these contentions by

forcing the host to wait until the resource arbitration is complete.

• The Bus Start (BS#) signal connects to TS (the transfer start signal).

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4 MPC821 to S1D13505 Interface

4.1 Hardware Description

The S1D13505 provides native Power PC bus support making it very simple to interface

the two devices. This application note describes both the environment necessary to connect

the S1D13505 to the MPC821 native system bus and the connection between the

S5U13505B00B Evaluation Board and the Motorola MPC821 Application Development

System (ADS).

Additionally, by implementing a dedicated display buffer, the S1D13505 can reduce

system power consumption, improve image quality, and increase system performance as

compared to the MPC821’s on-chip LCD controller.

The S1D13505, through the use of the MPC821 chip selects, can share the system bus with

all other MPC821 peripherals. The following figure demonstrates a typical implementation

of the S1D13505 to MPC821 interface.

MPC821

S1D13505

M/R#

A10

A[11:31]

D[0:15]

AB[20:0]

DB[15:0]

CS4

CS#

BS#

WAIT#

RD/WR#

RD/WR

RD#

TSIZ0

TSIZ1

WE0#

WE1#

BUSCLK

RESET#

SYSCLK

System

RESET

Note:

When connecting the S1D13505 RESET# pin, the system designer should be aware of all

conditions that may reset the S1D13505 (e.g. CPU reset can be asserted during wake-up

from power-down modes, or during debug states).

Figure 4-1: Typical Implementation of MPC821 to S1D13505 Interface

Interfacing to the Motorola MPC821 Microprocessor

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Table 4-1:,“List of Connections from MPC821ADS to S1D13505 ” on page 16 shows the

connections between the pins and signals of the MPC821 and the S1D13505.

Note

The interface was designed using a Motorola MPC821 Application Development

System (ADS). The ADS board has 5 volt logic connected to the data bus, so the

interface included two 74F245 octal buffers on D[0:15] between the ADS and the

S1D13505. In a true 3 volt system, no buffering is necessary.

4.2 Hardware Connections

The following table details the connections between the pins and signals of the MPC821

and the S1D13505.

Table 4-1: List of Connections from MPC821ADS to S1D13505

MPC821 Signal Name

MPC821ADS Connector and Pin Name

S1D13505 Signal Name

Vcc

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

A26

A27

A28

A29

A30

A31

P6-A1, P6-B1

P6-C23

P6-A22

P6-B22

P6-C21

P6-C20

P6-D20

P6-B24

P6-C24

P6-D23

P6-D22

P6-D19

P6-A19

P6-D28

P6-A28

P6-C27

P6-A26

P6-C26

P6-A25

P6-D26

P6-B25

P6-B19

P6-D17

P12-A9

P12-C9

P12-D9

P12-A8

P12-B8

P12-D8

P12-B7

P12-C7

Vcc

M/R#

AB20

AB19

AB18

AB17

AB16

AB15

AB14

AB13

AB12

AB11

AB10

AB9

AB8

AB7

AB6

AB5

AB4

AB3

AB2

AB1

AB0

DB15

DB14

DB13

DB12

DB11

DB10

DB9

DB8

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Table 4-1: List of Connections from MPC821ADS to S1D13505 (Continued)

MPC821 Signal Name

MPC821ADS Connector and Pin Name

S1D13505 Signal Name

P12-A15

P12-C15

P12-D15

P12-A14

P12-B14

P12-D14

P12-B13

P12-C13

P9-D15

P9-C2

DB7

DB6

D10

DB5

D11

DB4

D12

DB3

D13

DB2

D14

DB1

D15

DB0

SRESET

SYSCLK

CS4

RESET#

BUSCLK

CS#

P6-D13

P6-B7

BS#

P6-B6

WAIT#

RD/WR#

RD#

R/W

TSIZ0

TSIZ1

P6-D8

P6-B18

P6-C18

P6-B9

WE0#

WE1#

P12-A1, P12-B1, P12-A2, P12-B2,

P12-A3, P12-B3, P12-A4, P12-B4,

P12-A5, P12-B5, P12-A6, P12-B6,

P12-A7

Gnd

Vss

Note

Note that the bit numbering of the Power PC bus signals is reversed. e.g. the most

significant address bit is A0, the next is A1, A2, etc.

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4.3 S1D13505 Hardware Configuration

The S1D13505 latches MD15 through MD0 to allow selection of the bus mode and other

configuration data on the rising edge of RESET#. For details on configuration, refer to the

S1D13505 Hardware Functional Specification, document number X23A-A-001-xx.

The following table shows those configuration settings important to the MPC821 host bus

interface.

Table 4-2: Summary of Power-On/Reset Options

value on this pin at rising edge of RESET# is used to configure: (1/0)

S1D13505

Pin Name

MD0

8-bit host bus interface

16-bit host bus interface

MD[3:1]

MD4

110 = PowerPC host bus interface selected

Little Endian

Big Endian

MD5

Wait# signal is active high

Wait# signal is active low

Configure SUSPEND# pin as Hardware

Suspend Enable

MD9

Reserved

MD11

Alternate Host Bus Interface Selected

= required settings for MPC821 support.

Primary Host Bus Interface Selected

4.4 Register/Memory Mapping

The DRAM on the MPC821 ADS board extends from address 0 through 3F FFFFh, so the

S1D13505 is addressed starting at 40 0000h. A total of 4M bytes of address space is used,

where the lower 2M bytes is reserved for the S1D13505 on-chip registers and the upper 2M

bytes is used to access the S1D13505 display buffer.

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4.5 MPC821 Chip Select Configuration

Chip select 4 is used to control the S1D13505. The following options are selected in the

base address register (BR4):

• BA[0:16] = 0000 0000 0100 0000 0 – set starting address of S1D13505 to 40 0000h.

• AT[0:2] = 0 – ignore address type bits.

• PS[0:1] = 1:0 – memory port size is 16-bit.

• PARE = 0 – disable parity checking.

• WP = 0 – disable write protect.

• MS[0:1] = 0:0 – select General Purpose Chip Select module to control this chip select.

• V = 1 – set valid bit to enable chip select.

The following options were selected in the option register (OR4):

• AM[0:16] = 1111 1111 1100 0000 0 – mask all but upper 10 address bits; S1D13505

consumes 4M byte of address space.

• ATM[0:2] = 0 – ignore address type bits.

• CSNT = 0 – normal CS/WE negation.

• ACS[0:1] = 1:1 – delay CS assertion by ½ clock cycle from address lines.

• BI = 0 – do not assert Burst Inhibit.

• SCY[0:3] = 0 – wait state selection; this field is ignored since external transfer acknowl-

edge is used; see SETA below.

• SETA = 1 – the S1D13505 generates an external transfer acknowledge using the

WAIT# line.

• TRLX = 0 – normal timing.

• EHTR = 0 – normal timing.

Interfacing to the Motorola MPC821 Microprocessor

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4.6 Test Software

The test software is very simple. It configures chip select 4 (CS4) on the MPC821 to map

the S1D13505 to an unused 4M byte block of address space. Next, it loads the appropriate

values into the option register for CS4 and writes the value 0 to the S1D13505 register

REG[1Bh] to enable the S1D13505 host interface. Lastly, the software runs a tight loop that

reads the S1D13505 Revision Code Register REG[00h]. This allows monitoring of the bus

timing on a logic analyzer.

The following source code was entered into the memory of the MPC821ADS using the

line-by-line assembler in MPC8BUG (the debugger provided with the ADS board). Once

the program was executed on the ADS, a logic analyzer was used to verify operation of the

interface hardware.

It is important to note that when the MPC821 comes out of reset, the on-chip caches and

MMU are disabled. If the data cache is enabled, then the MMU must be set so that the

S1D13505 memory block is tagged as non-cacheable. This ensures the MPC821 does not

attempt to cache any data read from, or written to, the S1D13505 or its display buffer.

BR4

OR4

MemStart

DisableReg

RevCodeReg

equ

$120

$124

$40

$1b

; CS4 base register

; CS4 option register

; upper word of S1D13505 start address

; address of S1D13505 Disable Register

; address of Revision Code Register

Start

mfspr

andis.

oris

ori

stw

andis.

oris

ori

r1,IMMR

r1,r1,$ffff

r2,r0,0

r2,r2,MemStart

r2,r2,$0801

r2,BR4(r1)

r2,r0,0

r2,r2,$ffc0

r2,r2,$0608

; get base address of internal registers

; clear lower 16 bits to 0

; clear r2

; write base address

; port size 16 bits; select GPCM; enable

; write value to base register

; clear r2

; address mask – use upper 10 bits

; normal CS negation; delay CS ½ clock;

; no burst inhibit (13505 does this)

; write to option register

; clear r1

stw

r2,OR4(r1)

r1,r0,0

r1,r1,MemStart

r1,DisableReg(r1) ; write 0 to disable register

r0,RevCodeReg(r1) ; read revision code into r1

andis.

oris

stb

; point r1 to start of S1D13505 mem space

Loop

lbz

Loop

; branch forever

end

Note

MPC8BUG does not support comments or symbolic equates; these have been added for

clarity.

S1D13505

X23A-G-008-05

Interfacing to the Motorola MPC821 Microprocessor

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5 Software

Test utilities and Windows® CE display drivers are available for the S1D13505. Full

source code is available for both the test utilities and the drivers.

The test utilities are configurable for different panel types using a program called

13505CFG, or by directly modifying the source. The Windows CE display drivers can be

customized by the OEM for different panel types, resolutions and color depths only by

modifying the source.

The S1D13505 test utilities and Windows CE display drivers are available from your sales

support contact or on the internet at http://www.eea.epson.com.

Interfacing to the Motorola MPC821 Microprocessor

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6 References

6.1 Documents

• Motorola Inc., Power PC MPC821 Portable Systems Microprocessor User’s Manual;

Motorola Publication no. MPC821UM/AD.

• Epson Research and Development, Inc., S1D13505 Hardware Functional Specification,

Document Number X23A-A-001-xx.

• Epson Research and Development, Inc., S5U13505B00B Rev. 1.0 ISA Bus Evaluation

Board User Manual, Document Number X19A-G-001-xx.

6.2 Document Sources

• Motorola Literature Distribution Center: (800) 441-2447.

• Epson Electronics America Website: www.eea.epson.com.

S1D13505

X23A-G-008-05

Interfacing to the Motorola MPC821 Microprocessor

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7 Technical Support

7.1 EPSON LCD/CRT Controllers (S1D13505)

Japan

Seiko Epson Corporation

Electronic Devices Marketing Division

421-8, Hino, Hino-shi

North America

Epson Electronics America, Inc.

150 River Oaks Parkway

San Jose, CA 95134, USA

Taiwan, R.O.C.

Epson Taiwan Technology

& Trading Ltd.

10F, No. 287

Tokyo 191-8501, Japan

Tel: (408) 922-0200

Nanking East Road

Sec. 3, Taipei, Taiwan, R.O.C.

Tel: 02-2717-7360

Fax: 02-2712-9164

Tel: 042-587-5812

Fax: (408) 922-0238

http://www.eea.epson.com

Fax: 042-587-5564

http://www.epson.co.jp

Singapore

Europe

Hong Kong

Epson Singapore Pte., Ltd.

No. 1

Temasek Avenue #36-00

Millenia Tower

Singapore, 039192

Tel: 337-7911

Fax: 334-2716

Epson Europe Electronics GmbH

Riesstrasse 15

80992 Munich, Germany

Tel: 089-14005-0

Epson Hong Kong Ltd.

20/F., Harbour Centre

25 Harbour Road

Wanchai, Hong Kong

Tel: 2585-4600

Fax: 089-14005-110

Fax: 2827-4346

7.2 Motorola MPC821 Processor

• Motorola Design Line, (800) 521-6274.

• Local Motorola sales office or authorized distributor.

Interfacing to the Motorola MPC821 Microprocessor

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S1D13505

X23A-G-008-05

Interfacing to the Motorola MPC821 Microprocessor

Issue Date: 01/02/05

S1D13505 Embedded RAMDAC LCD/CRT Controller

Interfacing to the Toshiba MIPS

TX3912 Processor

Document Number: X23A-G-010-04

Information in this document is subject to change without notice. You may download and use this document, but only for your own use in

evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any

representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain

material protected under U.S. and/or International Patent laws.

EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.

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S1D13505

X23A-G-010-04

Interfacing to the Toshiba MIPS TX3912 Processor

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Table of Contents

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Interfacing to the TX3912 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

S1D13505 Host Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.1 TX3912 Host Bus Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . 9

3.2 TX3912 Host Bus Interface Signals . . . . . . . . . . . . . . . . . . . . . . 10

Direct Connection to the Toshiba TX3912 . . . . . . . . . . . . . . . . . . . . . . 11