Intel 8XC196Jx User Manual

8XC196Lx Supplement to  
8XC196Kx, 8XC196Jx,  
87C196CA User’s Manual  
August 2004  
Order Number: 272973-003  
CHAPTER 1  
GUIDE TO THIS MANUAL  
1.1  
1.2  
CHAPTER 2  
ARCHITECTURAL OVERVIEW  
2.1  
2.2  
2.3  
2.4  
2.5  
MICROCONTROLLER FEATURES.............................................................................. 2-1  
INTERNAL PERIPHERALS........................................................................................... 2-6  
I/O Ports ....................................................................................................................2-7  
Synchronous Serial I/O Port .....................................................................................2-7  
2.5.1  
2.5.2  
2.5.3  
2.5.4  
2.6  
CHAPTER 3  
ADDRESS SPACE  
3.1  
3.2  
3.3  
3.4  
CHAPTER 4  
STANDARD AND PTS INTERRUPTS  
4.1  
4.2  
4.2.1  
4.2.2  
4.2.3  
INTERRUPT SOURCES, VECTORS, AND PRIORITIES ............................................. 4-1  
INTERRUPT REGISTERS............................................................................................. 4-2  
CHAPTER 5  
I/O PORTS  
5.1  
5.2  
5.2.1  
5.2.2  
5.3  
I/O PORTS OVERVIEW ................................................................................................ 5-1  
INTERNAL STRUCTURE FOR PORTS 1, 2, 5, AND 6 (BIDIRECTIONAL PORTS).... 5-1  
Configuring Ports 1, 2, 5, and 6 (Bidirectional Ports) ................................................5-3  
Special Bidirectional Port Considerations .................................................................5-4  
INTERNAL STRUCTURE FOR PORTS 3 AND 4 (ADDRESS/DATA BUS).................. 5-5  
iii  
8XC196LX SUPPLEMENT  
CHAPTER 6  
6.1  
6.2  
CHAPTER 7  
EVENT PROCESSOR ARRAY  
7.1  
7.1.1  
7.1.2  
7.1.3  
EPA FUNCTIONAL OVERVIEW ................................................................................... 7-1  
CHAPTER 8  
8.1  
8.2  
8.3  
8.3.1  
8.3.1.1  
8.3.1.2  
8.3.1.3  
8.3.1.4  
8.3.2  
8.3.2.1  
8.3.2.2  
8.3.2.3  
8.3.2.4  
8.3.3  
8.4  
8.4.1  
8.4.1.1  
8.4.1.2  
8.4.1.3  
8.4.1.4  
8.4.2  
IFR Messaging Type 2: Single Byte, Multiple Responders ................................8-12  
IFR Messaging Type 3: Multiple Bytes, Single Responder ................................8-13  
8.4.2.1  
8.4.2.2  
8.4.2.3  
8.5  
8.5.1  
8.5.2  
8.5.3  
TRANSMITTING AND RECEIVING MESSAGES ....................................................... 8-13  
Transmitting Messages ...........................................................................................8-13  
Receiving Messages ...............................................................................................8-15  
IFR Messages .........................................................................................................8-16  
iv  
8.6  
8.6.1  
8.6.2  
8.6.3  
8.6.4  
PROGRAMMING THE J1850 CONTROLLER ............................................................ 8-16  
Programming the J1850 Command (J_CMD) Register ..........................................8-16  
Programming the J1850 Status (J_STAT) Register ................................................8-21  
CHAPTER 9  
9.1  
9.2  
DESIGN CONSIDERATIONS FOR 8XC196LA, LB, AND LD ....................................... 9-2  
CHAPTER 10  
CHAPTER 11  
PROGRAMMING THE NONVOLATILE MEMORY  
11.4 SERIAL PORT PROGRAMMING CIRCUIT AND ADDRESS MAP............................. 11-4  
APPENDIX A  
SIGNAL DESCRIPTIONS  
A.1  
A.2  
FUNCTIONAL GROUPINGS OF SIGNALS ................................................................. A-1  
DEFAULT CONDITIONS.............................................................................................. A-7  
GLOSSARY  
v
8XC196LX SUPPLEMENT  
Figure  
2-1  
2-2  
2-3  
2-4  
2-5  
3-1  
4-1  
4-2  
4-3  
4-4  
4-5  
4-6  
5-1  
5-2  
6-1  
6-2  
7-1  
7-2  
7-3  
7-4  
7-5  
7-6  
7-7  
8-1  
8-2  
8-3  
8-4  
8-5  
8-6  
8-7  
8-8  
8-9  
8-10  
8-11  
8-13  
8-12  
8-15  
8-14  
8-16  
8-17  
8-18  
8-19  
9-1  
10-1  
J1850 Command (J_CMD) Register ..........................................................................8-17  
J1850 Configuration (J_CFG) Register......................................................................8-18  
J1850 Delay (J_DLY) Register...................................................................................8-20  
J1850 Status (J_STAT) Register................................................................................8-21  
Reset Source (RSTSRC) Register...............................................................................9-1  
Clock Circuitry (87C196LA, LB Only) .........................................................................10-2  
vi  
Page  
Figure  
11-1  
11-2  
A-1  
A-2  
A-3  
Slave Programming Circuit.........................................................................................11-3  
Serial Port Programming Circuit.................................................................................11-4  
87C196LA 52-pin PLCC Package............................................................................... A-3  
87C196LB 52-pin PLCC Package............................................................................... A-5  
83C196LD 52-pin PLCC Package............................................................................... A-7  
vii  
8XC196LX SUPPLEMENT  
Table  
1-1  
2-1  
2-2  
2-3  
2-4  
3-1  
3-2  
3-3  
3-4  
4-1  
5-1  
7-1  
7-2  
8-1  
8-2  
8-3  
8-4  
11-1  
11-2  
11-3  
11-4  
A-1  
A-2  
A-3  
A-4  
A-5  
A-6  
Features of the 8XC196Lx and 8XC196Kx Product Famiies .......................................2-1  
EPA Interrupt Priority Vectors.......................................................................................7-6  
87C196LA Signals Arranged by Functional Categories .............................................. A-2  
87C196LB Signals Arranged by Functional Categories .............................................. A-4  
83C196LD Signals Arranged by Functional Categories.............................................. A-6  
Definition of Status Symbols ....................................................................................... A-7  
87C196LA, LB Default Signal Conditions.................................................................... A-8  
83C196LD Default Signal Conditions.......................................................................... A-9  
viii  
1
Guide to This Manual  
CHAPTER 1  
GUIDE TO THIS MANUAL  
This document is a supplement to the 8XC196Kx, 8XC196Jx, 87C196CA Microcontroller Family  
Users Manual. It describes the differences between the 8XC196Lx and the 8XC196Kx family of  
microcontrollers. For information not found in this supplement, please consult the 8XC196Kx,  
8XC196Jx, 87C196CA Microcontroller Family Users Manual (order number 272258) or the  
8XC196Lx datasheets listed in the “Related Documents” section of this chapter.  
1.1 MANUAL CONTENTS  
This supplement contains several chapters, an appendix, a glossary, and an index. This chapter,  
Chapter 1, provides an overview of the supplement. This section summarizes the contents of the  
remaining chapters and appendixes. The remainder of this chapter provides references to related  
documentation.  
Chapter 2 — Architectural Overview — compares the features of the 8XC196Lx microcon-  
troller family with those of the 8XC196Kx microcontroller family and describes the 87C196LA,  
LB internal clock circuitry.  
Chapter 3 — Address Space — describes the addressable memory space of the 52-pin  
8XC196Lx, lists the peripheral special-function registers (SFRs), and provides tables of WSR  
values for windowing higher memory into the lower register file for direct access.  
Chapter 4 — Standard and PTS Interrupts — describes the additional interrupts for the  
87C196LB’s J1850 communications controller peripheral and the SFRs that support those inter-  
rupts.  
Chapter 5 — I/O Ports — describes the port differences and explains the change in the port reset  
Chapter 6 — Synchronous Serial I/O Port — describes the enhanced synchronous serial I/O  
Chapter 7 — Event Processor Array — describes the event processor array channel differenc-  
es.  
Chapter 8 — J1850 Communications Controller — describes the 87C196LB’s integrated  
Chapter 9 — Minimum Hardware Considerations — describes device reset options through  
the reset source register, and discusses hardware design considerations.  
Chapter 10 — Special Operating Modes — illustrates the internal clock control circuitry of the  
87C196LA, LB and describes how to enter and exit on-circuit emulation (ONCE) mode.  
Chapter 11 — Programming the Nonvolatile Memory — describes the memory maps and rec-  
ommended circuits to support programming of the 87C196LA, LB’s 24 Kbytes of OTPROM.  
1-1  
       
8XC196LX SUPPLEMENT  
Appendix A — Signal Descriptions — provides reference information for the 8XC196Lx de-  
vice pins, including descriptions of the pin functions, reset status of the I/O and control pins, and  
package pin assignments.  
Glossary — defines terms with special meaning used throughout this supplement.  
Index — lists key topics with page number references.  
1.2 RELATED DOCUMENTS  
Table 1-1 lists additional documents that you may find useful in designing systems incorporating  
the 8XC196Lx microcontrollers.  
Table 1-1. Related Documents  
Title and Description  
Order Number  
8XC196Kx, 8XC196Jx, 87C196CA Microcontroller Family User’s Manual  
87C196LA-20 MHz CHMOS 16-Bit Microcontroller Automotive datasheet  
87C196LB-20 MHz CHMOS 16-Bit Microcontroller Automotive datasheet  
83C196LD CHMOS 16-Bit Microcontroller Automotive datasheet  
272258  
272806  
272807  
272805  
1-2  
         
2
Architectural  
Overview  
CHAPTER 2  
ARCHITECTURAL OVERVIEW  
This chapter describes architectural differences between the 8XC196Lx (87C196LA, 87C196LB,  
and 83C196LD) and the 8XC196Kx (8XC196Kx, 8XC196Jx, and 87C196CA) microcontroller  
families. Both the 8XC196Lx and the 8XC196Kx are designed for high-speed calculations and  
fast I/O, and share a common architecture and instruction set with few deviations. This chapter  
provides a high-level overview of the deviations between the two families.  
NOTE  
This supplement describes two product families within the MCS® 96  
microcontroller family. For brevity, the name 8XC196Lx is used when the  
discussion applies to all three Lx controllers. Likewise, the name 8XC196Kx is  
used when the discussion applies to all the Kx, Jx, and CA controllers.  
2.1 MICROCONTROLLER FEATURES  
Table 2-1 lists the features of the 8XC196Lx and the 8XC196Kx.  
Table 2-1. Features of the 8XC196Lx and 8XC196Kx Product Famiies  
OTPROM/  
Pins EPROM/  
ROM (1)  
SIO/  
Ext.  
Register Code  
RAM (2) RAM Pins Pins  
I/O EPA  
Device  
SSIO A/D CAN J1850 Interrupt  
Ports  
Pins  
87C196LA  
87C196LB  
83C196LD  
8XC196JV  
8XC196KT  
8XC196JT  
87C196CA  
8XC196KR  
8XC196JR  
NOTES:  
52  
52  
52  
52  
68  
52  
68  
68  
52  
24 K  
24 K  
16 K  
48 K  
32 K  
32 K  
32 K  
16 K  
16 K  
768  
768  
41  
41  
41  
41  
56  
41  
51  
56  
41  
6
6
3
3
3
3
3
3
3
3
3
6
6
1
1
1
1
1
1
2
1
2
2
1
384  
6
6
1536  
1024  
1024  
1024  
512  
512  
512  
512  
256  
256  
256  
6
10  
6
8
6
6
6
10  
6
8
512  
6
1. Optional. The second character of the device name indicates the presence and type of nonvolatile  
memory. 80C196xx = none; 83C196xx = ROM; 87C196xx = OTPROM or EPROM.  
2. Register RAM amounts include the 24 bytes allocated to core SFRs and the stack pointer.  
2-1  
             
8XC196LX SUPPLEMENT  
2.2 BLOCK DIAGRAM  
Figure 2-1 is a simplified block diagram that shows the major blocks within the microcontroller.  
Observe that the slave port peripheral does not exist on the 8XC196Lx.  
Optional  
ROM/  
OTPROM  
Core  
(CPU, Memory  
Controller)  
Interrupt  
Controller  
Peripheral  
Transaction  
Server  
Optional  
Code/Data  
RAM  
Clock and  
Power Mgmt.  
J1850  
EPA  
WDT  
I/O  
SIO  
SSIO  
A/D  
Note:  
The J1850 peripheral is unique to the 87C196LB device.  
A5253-01  
Figure 2-1. 8XC196Lx Block Diagram  
2.3 INTERNAL TIMING  
The 87C196LA, LB clock circuitry (Figure 2-2) implements a phase-locked loop and clock mul-  
tiplier circuitry, which can substantially increase the CPU clock rate while using a lower-frequen-  
cy input clock. The clock circuitry accepts an input clock signal on XTAL1 provided by an  
external crystal or oscillator. Depending on the value of the PLLEN pin, this frequency is routed  
either through the phase-locked loop and multiplier or directly to the divide-by-two circuit. The  
multiplier circuitry can double the input frequency (FXTAL1) before the frequency (f) reaches the  
divide-by-two circuitry. The clock generators accept the divided input frequency (f/2) from the  
divide-by-two circuit and produce two nonoverlapping internal timing signals, PH1 and PH2.  
These signals are active when high.  
NOTE  
This manual uses lowercase “f” to represent the internal clock frequency. For  
the 87C196LA and LB, f is equal to either FXTAL1 or 2FXTAL1, depending on the  
clock multiplier mode, which is controlled by the PLLEN input pin.  
2-2  
           
ARCHITECTURAL OVERVIEW  
Disable  
PLL  
(Powerdown)  
Phase  
Comparator  
Filter  
FXTAL1  
XTAL1  
XTAL2  
Phase-locked  
Oscillator  
Phase-locked Loop  
Clock Multiplier  
PLLEN  
1
0
Disable Oscillator  
(Powerdown)  
f
Disable Clock Input (Powerdown)  
To reset logic  
Divide by two  
Circuit  
f/2  
Disable Clocks (Idle, Powerdown)  
CPU Clocks (PH1, PH2)  
Clock  
Failure  
Detection  
Clock  
Generators  
Peripheral Clocks (PH1, PH2)  
f/2  
Programmable  
Divider  
(CLK1:0)  
OSC  
0
CLKOUT  
1
Disable Clocks (Powerdown)  
A5290-01  
Figure 2-2. Clock Circuitry (87C196LA, LB Only)  
The rising edges of PH1 and PH2 generate the internal CLKOUT signal (Figure 2-3). The clock  
circuitry routes separate internal clock signals to the CPU and the peripherals to provide flexibil-  
ity in power management. It also outputs the CLKOUT signal on the CLKOUT pin. Because of  
the complex logic in the clock circuitry, the signal on the CLKOUT pin is a delayed version of  
the internal CLKOUT signal. This delay varies with temperature and voltage.  
2-3  
     
8XC196LX SUPPLEMENT  
XTAL1  
PH1  
t
t
1 State Time  
1 State Time  
PH2  
CLKOUT  
Phase 1  
Phase 2  
Phase 1  
Phase 2  
A0805-01  
Figure 2-3. Internal Clock Phases (Assumes PLL is Bypassed)  
The combined period of phase 1 and phase 2 of the internal CLKOUT signal defines the basic  
time unit known as a state time or state. Table 2-2 lists state time durations at various frequencies.  
Table 2-2. State Times at Various Frequencies  
f
(Frequency Input to the  
Divide-by-two Circuit)  
State Time  
8 MHz  
12 MHz  
16 MHz  
20 MHz  
250 ns  
167 ns  
125 ns  
100 ns  
The following formulas calculate the frequency of PH1 and PH2, the duration of a state time, and  
the duration of a clock period (t).  
f
2
1
t = --  
f
PH1 (in MHz) = -- = PH2  
State Time (in µs) = --  
2
f
Because the device can operate at many frequencies, this manual defines time requirements (such  
as instruction execution times) in terms of state times rather than specific measurements.  
Datasheets list AC characteristics in terms of clock periods (t; sometimes called Tosc).  
Figure 2-4 illustrates the timing relationships between the input frequency (FXTAL1), the operating  
frequency (f), and the CLKOUT signal with each PLLEN pin configuration. Table 2-3 details the  
relationships between the input frequency (FXTAL1), the PLLEN pin, the operating frequency (f),  
the clock period (t), and state times.  
2-4  
                 
ARCHITECTURAL OVERVIEW  
TXHCH  
XTAL1  
(16 MHz)  
f
PLLEN = 0  
t = 62.5ns  
Internal  
CLKOUT  
f
PLLEN = 1  
t = 31.25ns  
Internal  
CLKOUT  
A3376-01  
Figure 2-4. Effect of Clock Mode on Internal CLKOUT Frequency  
Table 2-3. Relationships Between Input Frequency, Clock Multiplier, and State Times  
FXTAL1  
(Frequency  
on XTAL1)  
f
t
PLLEN  
Multiplier  
(Input Frequency to  
the Divide-by-two Circuit)  
(Clock  
Period)  
State Time  
4 MHz  
8 MHz  
0
0
0
0
0
1
1
1
1
1
1
1
1
2
2
2
4 MHz  
8 MHz  
250 ns  
125 ns  
83.5 ns  
62.5 ns  
50 ns  
500 ns  
250 ns  
167 ns  
125 ns  
100 ns  
250 ns  
125 ns  
100 ns  
12 MHz  
16 MHz  
20 MHz  
4 MHz  
12 MHz  
16 MHz  
20 MHz  
8 MHz  
125 ns  
62.5 ns  
50 ns  
8 MHz  
16 MHz  
20 MHz  
10 MHz  
2.4 EXTERNAL TIMING  
You can control the output frequency on the CLKOUT pin by programming two uneraseable  
PROM bits. Figure 2-5 illustrates the read-only USFR1, which reflects the state of the unerasable  
PROM bits. You can select one of three frequencies: f/2, f/4, or f/8. As Figure 2-2 on page 2-3  
shows, the configurable divider accepts the output of the clock generators (f/2) and further di-  
vides that frequency to produce the desired output frequency. The CLK1:0 bits control the divisor  
(divide f/2 by either 1, 2, or 4).  
2-5  
           
8XC196LX SUPPLEMENT  
USFR1 (read only)  
Address:  
Reset State:  
1FF2H  
XXH  
The UPROM special-function register 1 (USFR1) reflects the status of unerasable, programmable  
read-only memory (UPROM) locations. This read-only register reflects the status of two bits that  
control the output frequency on CLKOUT.  
7
0
CLK1  
CLK0  
Bit  
Bit  
Function  
Number Mnemonic  
7:2  
1:0  
Reserved.  
CLK1:0  
CLKOUT Control  
These bits reflect the programmed frequency of the CLKOUT signal:  
CLK1 CLK0  
0
0
1
1
0
1
0
1
divide by 1 (CLKOUT = f/2)  
divide by 2 (CLKOUT = f/4)  
divide by 4 (CLKOUT = f/8)  
divide by 1 (CLKOUT = f/2)  
Figure 2-5. Unerasable PROM 1 (USFR1) Register (LA, LB Only)  
To program these bits, write the correct value to the locations shown in Table 2-4 using slave pro-  
gramming mode. During normal operation, you can determine the values of these bits by reading  
the UPROM SFR (Figure 2-5).  
You can verify a UPROM bit to make sure it programmed, but you cannot erase it. For this rea-  
son, Intel cannot test the bits before shipment. However, Intel does test the features that the UP-  
ROM bits enable, so the only undetectable defects are (unlikely) defects within the UPROM cells  
themselves.  
Table 2-4. UPROM Programming Values and Locations  
To set this bit  
Write this value  
To this location  
CLK0  
CLK1  
0001H  
0002H  
0768H  
0728H  
2.5 INTERNAL PERIPHERALS  
The internal peripheral modules provide special functions for a variety of applications. This sec-  
tion provides a brief description of the peripherals that differ between the 8XC196Lx and the  
8XC196Kx families.  
2-6  
           
ARCHITECTURAL OVERVIEW  
2.5.1 I/O Ports  
The I/O ports of the 8XC196Lx are functionally identical to those of the 8XC196Jx. However, on  
the 87C196LA and LB the reset state level of all 41 general-purpose I/O pins has changed from  
a weak logic “1” (wk1) to a weak logic “0” (wk0).  
2.5.2 Synchronous Serial I/O Port  
The synchronous serial I/O (SSIO) port on the 8XC196Lx has been enhanced, implementing two  
new special function registers (SSIO0_CLK and SSIO1_CLK) that allow you to select the oper-  
ating mode and configure the phase and polarity of the serial clock signals.  
2.5.3 Event Processor Array  
The 8XC196Lx’s event processor array (EPA) is functionally identical to that of the 8XC196Jx,  
except that it has only two EPA capture/compare channels without pins instead of four. In addi-  
tion the LD has no compare-only channels.  
2.5.4 J1850 Communications Controller  
The 87C196LB microcontroller has a peripheral not found on the 8XC196Kx microcontrollers or  
any other Lx microcontroller, the J1850 peripheral. The J1850 communications controller man-  
ages communications between multiple network nodes. This integrated peripheral supports the  
10.4 Kb/s VPW (variable pulse-width) medium-speed, class B, in-vehicle network protocol. It  
also supports both the standard and in-frame response (IFR) message framing as specified by the  
Society of Automotive Engineering (SAE) J1850 (revised May 1994) technical standards.  
2.6 DESIGN CONSIDERATIONS  
With the exception of a few new multiplexed functions, the 8XC196Lx microcontrollers are pin  
compatible with the 8XC196Jx microcontrollers. The 8XC196Jx microcontrollers are 52-lead  
versions of 8XC196Kx microcontrollers. For registers that are implemented in both the  
8XC196Lx and the 8XC196Jx, configure the 8XC196Lx register as you would for the 8XC196Jx  
unless differences are noted in this supplement.  
2-7  
         
3
Address Space  
CHAPTER 3  
ADDRESS SPACE  
This chapter describes the differences in the address space of the 8XC196Lx from that of the  
8XC196Kx.  
3.1 ADDRESS PARTITIONS  
Table 3-1 is an address map of the 8XC196Lx and 8XC196Kx microcontroller family members.  
Table 3-1. Address Map  
Device and Hex Address Range  
Addressing  
Description  
Modes  
External device (memory  
or I/O) connected to  
address/data bus  
FFFF  
A000  
FFFF  
6000  
FFFF  
6000  
FFFF  
8000  
FFFF  
A000  
FFFF  
E000  
Indirect or  
indexed  
Program memory  
9FFF  
2080  
5FFF  
2080  
5FFF  
2080  
7FFF  
2080  
9FFF  
2080  
DFFF (internal nonvolatile or  
2080 external memory); see  
Note 1  
Indirect or  
indexed  
Special-purpose memory  
207F  
207F  
2000  
207F  
2000  
207F  
2000  
207F  
2000  
207F  
2000  
Indirect or  
indexed  
(internal nonvolatile or  
2000  
external memory)  
1FFF  
1FE0  
1FFF  
1FE0  
1FFF  
1FE0  
1FFF  
1FE0  
1FFF  
1FE0  
1FFF  
Indirect or  
indexed  
Memory-mapped SFRs  
1FE0  
Indirect,  
indexed, or  
windowed  
direct  
Peripheral SFRs  
1FDF  
1FDF  
1F00  
1FDF  
1F00  
1FDF  
1F00  
1FDF  
1F00  
1FDF  
1F00  
(Includes J1850 SFRs on  
1F00  
87C196LB)  
indexed, or  
windowed  
direct  
1EFF  
1E00  
CAN SFRs  
External device (memory  
or I/O) connected to  
address/data bus;  
(future SFR expansion;  
see Note 2)  
1DFF  
1C00  
1EFF  
1C00  
1EFF  
1C00  
1EFF  
0300  
1EFF  
1C00  
1EFF  
1E00  
Indirect or  
indexed  
Indirect,  
indexed, or  
windowed  
direct  
1DFF  
1C00  
Register RAM  
NOTES:  
1. After a reset, the device fetches its first instruction from 2080H.  
2. The content or function of these locations may change in future device revisions, in which case  
a program that relies on a location in this range might not function properly.  
3-1  
             
8XC196LX SUPPLEMENT  
Table 3-1. Address Map (Continued)  
Device and Hex Address Range  
Addressing  
Modes  
Description  
External device (memory  
or I/O) connected to  
address/data bus  
1BFF  
0500  
1BFF  
0500  
1BFF  
0600  
1BFF  
0600  
1BFF  
0600  
Indirect or  
indexed  
04FF  
0400  
04FF  
0400  
05FF  
0400  
05FF  
0400  
Indirect or  
indexed  
Internal code or data RAM  
External device (memory  
or I/O) connected to  
address/data bus  
03FF  
0200  
05FF  
0180  
Indirect or  
indexed  
Indirect,  
indexed, or  
windowed  
direct  
Upper register file  
(general-purpose register  
RAM)  
03FF  
0100  
01FF  
0100  
017F  
0100  
02FF  
0100  
03FF  
0100  
03FF  
0100  
Lower register file  
(register RAM, stack  
pointer, and CPU SFRs)  
Direct,  
indirect, or  
indexed  
00FF  
0000  
00FF  
0000  
00FF  
0000  
00FF  
0000  
00FF  
0000  
00FF  
0000  
NOTES:  
1. After a reset, the device fetches its first instruction from 2080H.  
2. The content or function of these locations may change in future device revisions, in which case  
a program that relies on a location in this range might not function properly.  
Figure 3-1 compares the register file addresses of the 8XC196Lx and 8XC196Kx. The register  
file in Figure 3-1 is divided into an upper register file and a lower register file. The upper register  
file consists of general-purpose register RAM. The lower register file contains general-purpose  
register RAM along with the stack pointer (SP) and the CPU special-function registers (SFRs).  
Table 3-2 lists the register file memory addresses. The RALU accesses the lower register file di-  
rectly, without the use of the memory controller. It also accesses a windowed location directly  
(see “Windowing” on page 3-6). The upper register file and the peripheral SFRs can be win-  
dowed. Registers in the lower register file and registers being windowed can be accessed with  
register-direct addressing.  
NOTE  
The register file must not contain code. An attempt to execute an instruction  
from a location in the register file causes the memory controller to fetch the  
instruction from external memory.  
3-2  
   
ADDRESS SPACE  
Address  
03FFH  
(CA, JT, JV, KT)  
General-purpose  
Register RAM  
02FFH (LA, LB)  
01FFH (JR, KR)  
017FH (LD)  
0100H  
00FFH  
Address  
03FFH  
General-purpose  
Register RAM  
Upper  
Register File  
001AH  
0019H  
0018H  
0017H  
0000H  
0100H  
00FFH  
Stack Pointer  
CPU SFRs  
Lower  
Register File  
0000H  
A5260-01  
Figure 3-1. Register File Address Map  
Table 3-2. Register File Memory Addresses  
Device and Hex Address Range  
CA,JT,KT LA, LB JR, KR  
Description  
Addressing Modes  
JV  
LD  
1DFF  
1C00  
Indirect, indexed, or  
windowed direct  
Register RAM  
03FF  
0100  
03FF  
0100  
02FF  
0100  
01FF  
0100  
017F  
0100  
Indirect, indexed, or  
windowed direct  
Upper register file (register RAM)  
Lower register file (register RAM)  
Lower register file (stack pointer)  
Lower register file (CPU SFRs)  
00FF  
001A  
00FF  
001A  
00FF  
001A  
00FF  
001A  
00FF  
001A  
Direct, indirect, or  
indexed  
0019  
0018  
0019  
0018  
0019  
0018  
0019  
0018  
0019  
0018  
Direct, indirect, or  
indexed  
0017  
0000  
0017  
0000  
0017  
0000  
0017  
0000  
0017  
0000  
Direct, indirect, or  
indexed  
3-3  
       
8XC196LX SUPPLEMENT  
3.3 PERIPHERAL SPECIAL-FUNCTION REGISTERS  
Table 3-3 lists the peripheral SFR addresses. Highlighted addresses are unique to the 8XC196Lx.  
Table 3-3. 8XC196Lx Peripheral SFRs  
Ports 3, 4, 5, and UPROM SFRs  
Ports 0, 1, 2, and 6 SFRs  
Address High (Odd) Byte Low (Even) Byte  
Address High (Odd) Byte Low (Even) Byte  
1FFEH  
P4_PIN  
P3_PIN  
1FDEH  
Reserved  
Reserved  
Reserved  
P0_PIN  
1FFCH P4_REG  
P3_REG  
1FDCH Reserved  
1FFAH  
1FF8H  
1FF6H  
1FF4H  
1FF2H  
1FF0H  
SLP_CON  
Reserved  
P5_PIN  
SLP_CMD  
SLP_STAT  
USFR  
1FDAH  
1FD8H  
1FD6H  
1FD4H  
1FD2H  
1FD0H  
1FCEH  
Reserved  
Reserved  
P6_PIN  
Reserved  
P1_PIN  
P5_REG  
P5_DIR  
P34_DRV  
USFR1 (LA, LB)  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
P6_REG  
P6_DIR  
P1_REG  
P1_DIR  
P5_MODE  
P6_MODE  
P2_PIN  
P1_MODE  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
1FEEH Reserved  
1FECH Reserved  
1FEAH Reserved  
1FCCH P2_REG  
1FCAH  
1FC8H  
1FC6H  
1FC4H  
1FC2H  
1FC0H  
P2_DIR  
1FE8H  
1FE6H  
1FE4H  
1FE2H  
1FE0H  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
P2_MODE  
Reserved  
Reserved  
Reserved  
Reserved  
Must be addressed as a word.  
3-4  
     
ADDRESS SPACE  
Table 3-3. 8XC196Lx Peripheral SFRs (Continued)  
SIO and SSIO SFRs  
EPA SFRs (Continued)  
Address High (Odd) Byte Low (Even) Byte  
Address High (Odd) Byte Low (Even) Byte  
1FBEH Reserved  
1FBCH SP_BAUD (H)  
1FBAH SP_CON  
Reserved  
1F7EH EPA7_TIME (H)  
Reserved  
1F7AH EPA6_TIME (H)  
1F78H Reserved  
1F76H EPA5_TIME (H)  
1F74H Reserved  
1F72H EPA4_TIME (H)  
1F70H Reserved  
EPA7_TIME (L)  
EPA7_CON  
SP_BAUD (L)  
SBUF_TX  
1F7CH  
EPA6_TIME (L)  
EPA6_CON  
1FB8H  
1FB6H  
1FB4H  
1FB2H  
1FB0H  
SP_STATUS  
SSIO1_CLK  
SSIO0_CLK  
SSIO1_CON  
SSIO0_CON  
SBUF_RX  
Reserved  
EPA5_TIME (L)  
EPA5_CON  
SSIO_BAUD  
SSIO1_BUF  
SSIO0_BUF  
EPA4_TIME (L)  
EPA4_CON  
A/D SFRs (LA, LB Only)  
Address High (Odd) Byte Low (Even) Byte  
1F6EH EPA3_TIME (H)  
1F6CH EPA3_CON (H)  
EPA3_TIME (L)  
EPA3_CON (L)  
EPA2_TIME (L)  
EPA2_CON  
1FAEH  
1FACH Reserved  
1FAAH AD_RESULT (H)  
AD_TIME  
AD_TEST  
1F6AH EPA2_TIME (H)  
AD_COMMAND  
AD_RESULT (L)  
1F68H  
Reserved  
1F66H EPA1_TIME (H)  
1F64H EPA1_CON (H)  
1F62H EPA0_TIME (H)  
EPA1_TIME (L)  
EPA1_CON (L)  
EPA0_TIME (L)  
EPA0_CON  
EPA Interrupt SFRs  
Address High (Odd) Byte Low (Even) Byte  
1FA8H  
1FA6H  
1FA4H  
Reserved  
Reserved  
Reserved  
EPAIPV  
1F60H  
Reserved  
EPA_PEND1  
EPA_MASK1  
EPA_PEND (L)  
EPA_MASK (L)  
J1850 SFRs (LB Only)  
Address High (Odd) Byte Low (Even) Byte  
1FA2H EPA_PEND (H)  
1FA0H EPA_MASK (H)  
1F5EH  
1F5CH  
1F5AH  
1F58H  
1F56H  
1F54H  
1F52H  
1F50H  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
J_STAT  
Reserved  
Reserved  
Reserved  
J_DLY  
Timer 1, Timer 2, and EPA SFRs  
Address High (Odd) Byte Low (Even) Byte  
1F9EH TIMER2 (H)  
Reserved  
1F9AH TIMER1 (H)  
TIMER2 (L)  
T2CONTROL  
TIMER1 (L)  
T1CONTROL  
Reserved  
Reserved  
J_CFG  
J_RX  
1F9CH  
1F98H  
1F96H  
1F94H  
1F92H  
1F90H  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
J_CMD  
J_TX  
Reserved  
RST_SRC  
Reserved  
EPA SFRs  
Address High (Odd) Byte Low (Even) Byte  
1F8EH COMP1_TIME (H) COMP1_TIME (L)  
1F8CH  
Reserved  
COMP1_CON  
1F8AH COMP0_TIME (H) COMP0_TIME (L)  
1F88H  
Reserved  
1F86H EPA9_TIME (H)  
1F84H Reserved  
1F82H EPA8_TIME (H)  
1F80H Reserved  
Must be addressed as a word.  
COMP0_CON  
EPA9_TIME (L)  
EPA9_CON  
EPA8_TIME (L)  
EPA8_CON  
3-5  
8XC196LX SUPPLEMENT  
3.4 WINDOWING  
Windowing maps a segment of higher memory (the upper register file or peripheral SFRs) into  
the lower register file. The window selection register (WSR) selects a 32-, 64- or 128-byte seg-  
ment of higher memory to be windowed into the top of the lower register file space. Table 3-4  
lists the WSR values for windowing the upper register file for both the 8XC196Lx and  
8XC196Kx.  
Table 3-4. Windows  
WSR Value for  
WSR Value  
for 32-byte Window  
(00E0–00FFH)  
WSR Value  
for 64-byte Window  
(00C0–00FFH)  
Base  
Address  
128-byte  
Window  
(0080–00FFH)  
Peripheral SFRs  
1FE0H  
1FC0H  
1FA0H  
1F80H  
1F60H  
1F40H  
1F20H  
1F00H  
7FH (Note)  
7EH  
3FH (Note)  
3EH  
7DH  
7CH  
1FH (Note)  
1EH  
7BH  
7AH  
3DH  
79H  
78H  
3CH  
CAN Peripheral SFRs (87C196CA Only)  
1EE0H  
1EC0H  
1EA0H  
1E80H  
1E60H  
1E40H  
1E20H  
1E00H  
77H  
76H  
75H  
74H  
73H  
72H  
71H  
70H  
3BH  
3AH  
39H  
38H  
1DH  
1CH  
Register RAM (87C196JV Only)  
1DE0H  
1DC0H  
1DA0H  
1D80H  
1D60H  
1D40H  
1D20H  
1D00H  
6FH  
6EH  
6DH  
6CH  
6BH  
6AH  
69H  
68H  
37H  
36H  
35H  
34H  
1BH  
1AH  
NOTE: Locations 1FE0–1FFFH contain memory-mapped SFRs that cannot be accessed through a  
window. Reading these locations through a window returns FFH; writing these locations  
through a window has no effect.  
3-6  
         
ADDRESS SPACE  
Table 3-4. Windows (Continued)  
WSR Value for  
128-byte  
Window  
(0080–00FFH)  
WSR Value  
for 32-byte Window  
WSR Value  
for 64-byte Window  
(00C0–00FFH)  
Base  
Address  
(00E0–00FFH)  
Register RAM (87C196JV Only; Continued)  
1CE0H  
1CC0H  
1CA0H  
1C80H  
1C60H  
1C40H  
1C20H  
1C00H  
67H  
66H  
65H  
64H  
63H  
62H  
61H  
60H  
33H  
32H  
31H  
30H  
19H  
18H  
Upper Register File (CA, JT, JV, KT)  
03E0H  
03C0H  
03A0H  
0380H  
0360H  
0340H  
0320H  
0300H  
5FH  
5EH  
5DH  
5CH  
5BH  
5AH  
59H  
58H  
2FH  
2EH  
2DH  
2CH  
17H  
16H  
Upper Register File (CA, JT, JV, KT, LA, LB)  
02E0H  
02C0H  
02A0H  
0280H  
0260H  
0240H  
0220H  
0200H  
57H  
56H  
55H  
54H  
53H  
52H  
51H  
50H  
2BH  
2AH  
29H  
28H  
15H  
14H  
Upper Register File (CA, JR, JT, JV, KR, KT, LA, LB)  
01E0H  
01C0H  
01A0H  
0180H  
4FH  
4EH  
4DH  
4CH  
27H  
26H  
13H  
NOTE: Locations 1FE0–1FFFH contain memory-mapped SFRs that cannot be accessed through a  
window. Reading these locations through a window returns FFH; writing these locations  
through a window has no effect.  
3-7  
8XC196LX SUPPLEMENT  
Table 3-4. Windows (Continued)  
WSR Value for  
128-byte  
Window  
(0080–00FFH)  
WSR Value  
for 32-byte Window  
(00E0–00FFH)  
WSR Value  
for 64-byte Window  
(00C0–00FFH)  
Base  
Address  
Upper Register File (CA, JR, JT, JV, KR, KT, LA, LB, LD)  
0160H  
0140H  
0120H  
0100H  
4BH  
4AH  
49H  
48H  
25H  
24H  
12H  
NOTE: Locations 1FE0–1FFFH contain memory-mapped SFRs that cannot be accessed through a  
window. Reading these locations through a window returns FFH; writing these locations  
through a window has no effect.  
3-8  
4
Standard and PTS  
Interrupts  
CHAPTER 4  
STANDARD AND PTS INTERRUPTS  
The interrupt structure of the 8XC196Lx is the same as that of the 8XC196Jx. The only difference  
is that the slave port interrupts (INT08:06) now support the J1850 controller peripheral.  
4.1 INTERRUPT SOURCES, VECTORS, AND PRIORITIES  
Table 4-1 lists the 8XC196Lx’s interrupts sources, default priorities (30 is highest and 0 is low-  
est), and vector addresses.  
4-1  
     
8XC196LX SUPPLEMENT  
Table 4-1. Interrupt Sources, Vectors, and Priorities  
Interrupt Controller  
Service  
PTS Service  
Interrupt Source  
Mnemonic  
Nonmaskable Interrupt  
EXTINT Pin  
NMI  
INT15  
203EH  
203CH  
203AH  
2038H  
2036H  
2034H  
2032H  
2030H  
2030H  
2012H  
2010H  
200EH  
200EH  
200CH  
200CH  
200AH  
200AH  
2008H  
2006H  
2004H  
2002H  
2000H  
30  
14  
13  
12  
11  
10  
09  
08  
08  
29  
28  
27  
26  
25  
24  
23  
23  
EXTINT  
INT14  
INT13  
INT12  
INT11  
INT10  
INT09  
INT08  
INT08  
PTS14  
PTS13  
PTS12  
PTS11  
PTS10  
PTS09  
PTS08  
PTS08  
205CH  
205AH  
2058H  
2056H  
2054H  
2052H  
2050H  
2050H  
Reserved  
SIO Receive  
RI  
SIO Transmit  
TI  
SSIO Channel 1 Transfer  
SSIO Channel 0 Transfer  
J1850 Status (LB only)  
Reserved (LA, LD)  
Unimplemented Opcode  
Software TRAP Instruction  
J1850 Receive (LB only)  
Reserved (LA, LD)  
J1850 Transmit (LB only)  
Reserved (LA, LD)  
SSIO1  
SSIO0  
J1850ST  
J1850RX  
INT07  
INT07  
INT06  
INT06  
INT05  
INT05  
INT04  
INT03  
INT02  
INT01  
INT00  
07  
07  
06  
06  
05  
05  
04  
03  
02  
01  
00  
PTS07  
PTS07  
PTS06  
PTS06  
PTS05  
PTS05  
PTS04  
PTS03  
PTS02  
PTS01  
PTS00  
204EH  
204EH  
204CH  
204CH  
204AH  
204AH  
2048H  
2046H  
2044H  
2042H  
2040H  
22  
22  
21  
21  
20  
20  
19  
18  
17  
16  
15  
J1850TX  
A/D Conv. Complete (LA, LB) AD_DONE  
Reserved (LD)  
EPA Capture/Compare 0  
EPA Capture/Compare 1  
EPA Capture/Compare 2  
EPA Capture/Compare 3  
EPA Capture/Compare 6–9,  
EPA0  
EPA1  
EPA2  
EPA3  
EPAx  
††  
EPA 0–3, 8–9 Overrun,  
†††  
EPA Compare 0–1  
Timer 1 Overflow, &  
Timer 2 Overflow  
,
The NMI pin is not bonded out on the 8XC196Lx. To protect against glitches, create a dummy interrupt  
service routine that contains a RET instruction.  
††  
These interrupts are individually prioritized in the EPAIPV register. Read the EPA pending registers  
(EPA_PEND and EPA_PEND1) to determine which source caused the interrupt.  
†††  
87C196LA, LB only. The 83C196LD has no EPA compare-only channels.  
4.2 INTERRUPT REGISTERS  
This section describes the changes in the interrupt register bit definitions for the 8XC196Lx fam-  
ily.  
4-2  
     
STANDARD AND PTS INTERRUPTS  
4.2.1 Interrupt Mask Registers  
Figures 4-1 and 4-2 illustrate the interrupt mask registers for the 8XC196Lx microcontrollers.  
Address:  
Reset State:  
0008H  
00H  
INT_MASK  
The interrupt mask (INT_MASK) register enables or disables (masks) individual interrupt requests.  
(The EI and DI instructions enable and disable servicing of all maskable interrupts.) INT_MASK is the  
low byte of the processor status word (PSW). PUSHF or PUSHA saves the contents of this register  
onto the stack and then clears this register. Interrupt calls cannot occur immediately following a push  
instruction. POPF or POPA restores it.  
7
0
LA  
LB  
LD  
AD  
AD  
EPA0  
EPA0  
EPA0  
EPA1  
EPA1  
EPA1  
EPA2  
EPA2  
EPA2  
EPA3  
EPA3  
EPA3  
EPAx  
EPAx  
EPAx  
7
0
0
J1850RX J1850TX  
7
Bit  
Number  
Function  
7:0  
Setting a bit enables the corresponding interrupt.  
Bit Mnemonic Interrupt Description  
J1850RX  
J1850TX  
AD  
EPA0  
EPA1  
J1850 Receive (LB only)  
J1850 Transmit (LB only)  
A/D Conversion Complete (LA, LB)  
EPA Capture/Compare Channel 0  
EPA Capture/Compare Channel 1  
EPA Capture/Compare Channel 2  
EPA Capture/Compare Channel 3  
Shared EPA interrupt  
EPA2  
EPA3  
††  
EPAx  
††  
†††  
EPA 6–9 capture/compare channel events, EPA 0–1 compare channel events , EPA  
0–3 and 8–9 capture/compare overruns, and timer overflows can generate this  
multiplexed interrupt. The EPA mask and pending registers decode the EPAx interrupt.  
Write the EPA mask registers to enable the interrupt sources; read the EPA pending  
registers to determine which source caused the interrupt.  
†††  
87C196LA, LB only.  
Bits 6–7 are reserved on the 87C196LA, and bits 5–7 are reserved on the 83C196LD. For  
compatibility with future devices, write zeros to these bits.  
Figure 4-1. Interrupt Mask (INT_MASK) Register  
4-3  
       
8XC196LX SUPPLEMENT  
INT_MASK1  
Address:  
Reset State:  
0013H  
00H  
The interrupt mask 1 (INT_MASK1) register enables or disables (masks) individual interrupt requests.  
(The EI and DI instructions enable and disable servicing of all maskable interrupts.) INT_MASK1 can  
be read from or written to as a byte register. PUSHA saves this register on the stack and POPA  
restores it.  
7
0
LB  
NMI  
EXTINT  
RI  
RI  
TI  
TI  
SSIO1  
SSIO1  
SSIO0  
SSIO0  
J1850ST  
7
0
LA, LD  
NMI  
EXTINT  
Bit  
Number  
Function  
7:0  
Setting a bit enables the corresponding interrupt.  
Bit Mnemonic Interrupt Description  
††  
NMI  
Nonmaskable Interrupt  
EXTINT Pin  
EXTINT  
Reserved  
RI  
SIO Receive  
TI  
SIO Transmit  
SSIO1  
SSIO0  
J1850ST  
SSIO1 Transfer  
SSIO0 Transfer  
J1850 Status (LB only)  
††  
NMI is always enabled. This nonfunctional mask bit exists for design symmetry with the  
INT_PEND1 register. Always write zero to this bit.  
Bit 5 is reserved on the 8XC196Lx devices, and bit 0 is reserved on the 87C196LA and 83C196LD.  
For compatibility with future devices, always write zeros to these bits.  
Figure 4-2. Interrupt Mask 1 (INT_MASK1) Register  
4.2.2 Interrupt Pending Registers  
Figures 4-3 and 4-4 illustrate the interrupt pending registers for the 8XC196Lx microcontrollers.  
4-4  
       
STANDARD AND PTS INTERRUPTS  
Address:  
Reset State:  
0009H  
00H  
INT_PEND  
When hardware detects an interrupt request, it sets the corresponding bit in the interrupt pending  
(INT_PEND or INT_PEND1) registers. When the vector is taken, the hardware clears the pending bit.  
Software can generate an interrupt by setting the corresponding interrupt pending bit.  
7
0
LA  
LB  
LD  
AD  
AD  
EPA0  
EPA0  
EPA0  
EPA1  
EPA1  
EPA1  
EPA2  
EPA2  
EPA2  
EPA3  
EPA3  
EPA3  
EPAx  
EPAx  
EPAx  
7
0
0
J1850RX J1850TX  
7
Bit  
Number  
Function  
7:0  
Any set bit indicates that the corresponding interrupt is pending. The interrupt bit is cleared  
when processing transfers to the corresponding interrupt vector.  
Bit Mnemonic Interrupt Description  
J1850RX  
J1850TX  
AD  
EPA0  
EPA1  
J1850 Receive (LB only)  
J1850 Transmit (LB only)  
A/D Conversion Complete (LA, LB)  
EPA Capture/Compare Channel 0  
EPA Capture/Compare Channel 1  
EPA Capture/Compare Channel 2  
EPA Capture/Compare Channel 3  
Shared EPA Interrupt  
EPA2  
EPA3  
††  
EPAx  
††  
†††  
EPA 6–9 capture/compare channel events, EPA 0–1 compare channel events , EPA  
0–3 and 8–9 capture/compare overruns, and timer overflows can generate this shared  
interrupt. Write the EPA mask registersto enable the interrupt sources; read the EPA  
pending registers to determine which source caused the interrupt.  
†††  
87C196LA, LB only.  
Bits 6–7 are reserved on the 87C196LA, and bits 5–7 are reserved on the 83C196LD. For  
compatibility with future devices, write zeros to these bits.  
Figure 4-3. Interrupt Pending (INT_PEND) Register  
4-5  
     
8XC196LX SUPPLEMENT  
INT_PEND1  
Address:  
Reset State:  
0012H  
00H  
When hardware detects an interrupt request, it sets the corresponding bit in the interrupt pending  
(INT_PEND or INT_PEND1) registers. When the vector is taken, the hardware clears the pending bit.  
Software can generate an interrupt by setting the corresponding interrupt pending bit.  
7
0
LB  
NMI  
EXTINT  
RI  
RI  
TI  
TI  
SSIO1  
SSIO1  
SSIO0  
SSIO0  
J1850ST  
7
0
LA, LD  
NMI  
EXTINT  
Bit  
Number  
Function  
7:0  
Any set bit indicates that the corresponding interrupt is pending. The interrupt bit is cleared  
when processing transfers to the corresponding interrupt vector.  
Bit Mnemonic Interrupt Description  
NMI  
Nonmaskable Interrupt  
EXTINT Pin  
EXTINT  
Reserved  
RI  
SIO Receive  
TI  
SIO Transmit  
SSIO1  
SSIO0  
J1850ST  
SSIO 1 Transfer  
SSIO 0 Transfer  
J1850 Status (LB only)  
Bit 5 is reserved on the 8XC196Lx devices and bit 0 is reserved on the 87C196LA and 83C196LD.  
For compatibility with future devices, always write zeros to these bits.  
Figure 4-4. Interrupt Pending 1 (INT_PEND1) Register  
4.2.3 Peripheral Transaction Server Registers  
Figures 4-5 and 4-6 illustrate the PTS interrupt select and service registers for the 8XC196Lx mi-  
crocontrollers.  
4-6  
       
STANDARD AND PTS INTERRUPTS  
Address:  
Reset State:  
0004H  
0000H  
PTSSEL  
The PTS select (PTSSEL) register selects either a PTS microcode routine or a standard interrupt  
service routine for each interrupt request. Setting a bit selects a PTS microcode routine; clearing a bit  
selects a standard interrupt service routine. In PTS modes that use the PTSCOUNT register, hardware  
clears the corresponding PTSSEL bit when PTSCOUNT reaches zero. The end-of-PTS interrupt service  
routine must reset the PTSSEL bit to re-enable the PTS channel.  
15  
8
LA  
LB  
LD  
EXTINT  
AD  
RI  
EPA0  
RI  
TI  
EPA1  
TI  
SSIO1  
EPA2  
SSIO1  
EPA2  
SSIO1  
EPA2  
SSIO0  
EPA3  
SSIO0  
EPA3  
SSIO0  
EPA3  
7
0
EPAx  
15  
7
8
EXTINT  
J1850ST  
0
EPAx  
8
J1850RX J1850TX  
AD  
EPA0  
RI  
EPA1  
TI  
15  
EXTINT  
7
0
EPA0  
EPA1  
EPAx  
Bit  
Number  
Function  
14:0  
Setting a bit causes the corresponding interrupt to be handled by a PTS microcode routine.  
The PTS interrupt vector locations are as follows:  
Bit Mnemonic Interrupt  
PTS Vector  
205CH  
205AH  
2058H  
2056H  
2054H  
2052H  
2050H  
204EH  
204CH  
204AH  
2048H  
2046H  
2044H  
2042H  
2040H  
EXTINT  
Reserved  
RI  
TI  
SSIO1  
SSIO0  
EXTINT pin  
SIO Receive  
SIO Transmit  
SSIO 1 Transfer  
SSIO 0 Transfer  
J1850ST (LB) J1850 Status  
J1850RX(LB)  
J1850TX(LB)  
AD(LA, LB)  
EPA0  
EPA1  
EPA2  
J1850 Receive  
J1850 Transmit  
A/D Conversion Complete  
EPA Capture/Compare Channel 0  
EPA Capture/Compare Channel 1  
EPA Capture/Compare Channel 2  
EPA Capture/Compare Channel 3  
Multiplexed EPA  
EPA3  
††  
EPAx  
††  
PTS service is not useful for shared interrupts because the PTS cannot readily  
determine the source of these interrupts.  
Bit 13 is reserved on the 8XC196Lx devices and bits 6–8 are reserved on the 87C196LA and  
83C196LD. For compatibility with future devices, write zeros to these bits.  
Figure 4-5. PTS Select (PTSSEL) Register  
4-7  
     
8XC196LX SUPPLEMENT  
PTSSRV  
Address:  
Reset State:  
0006H  
0000H  
The PTS service (PTSSRV) register is used by the hardware to indicate that the final PTS interrupt has  
been serviced by the PTS routine. When PTSCOUNT reaches zero, hardware clears the corresponding  
PTSSEL bit and sets the PTSSRV bit, which requests the end-of-PTS interrupt. When the end-of-PTS  
interrupt is called, hardware clears the PTSSRV bit. The end-of-PTS interrupt service routine must set  
the PTSSEL bit to re-enable the PTS channel.  
15  
8
LA  
LB  
LD  
EXTINT  
AD  
RI  
EPA0  
RI  
TI  
EPA1  
TI  
SSIO1  
EPA2  
SSIO1  
EPA2  
SSIO1  
EPA2  
SSIO0  
EPA3  
SSIO0  
EPA3  
SSIO0  
EPA3  
7
0
EPAx  
15  
7
8
EXTINT  
J1850ST  
0
EPAx  
8
J1850RX J1850TX  
AD  
EPA0  
RI  
EPA1  
TI  
15  
EXTINT  
7
0
EPA0  
EPA1  
EPAx  
Bits  
Function  
14:0  
A bit is set by hardware to request an end-of-PTS interrupt for the corresponding interrupt  
through its standard interrupt vector.  
The standard interrupt vector locations are as follows:  
Bit Mnemonic Interrupt  
Standard Vector  
203CH  
203AH  
2038H  
2036H  
2034H  
EXTINT  
Reserved  
RI  
EXTINT pin  
SIO Receive  
SIO Transmit  
SSIO 1 Transfer  
SSIO 0 Transfer  
TI  
SSIO1  
SSIO0  
2032H  
J1850ST (LB) J1850 Status  
J1850RX (LB) J1850 Receive  
J1850TX (LB) J1850 Transmit  
2030H  
202EH  
202CH  
202AH  
2028H  
2026H  
2024H  
AD (LA, LB)  
EPA0  
A/D Conversion Complete  
EPA Capture/Compare Channel 0  
EPA Capture/Compare Channel 1  
EPA Capture/Compare Channel 2  
EPA Capture/Compare Channel 3  
Multiplexed EPA  
EPA1  
EPA2  
EPA3  
2022H  
2020H  
††  
EPAx  
††  
PTS service is not useful for shared interrupts because the PTS cannot readily  
determine the source of these interrupts.  
Bit 13 is reserved on the 8XC196Lx devices and bits 6–8 are reserved on the 87C196LA and  
83C196LD. For compatibility with future devices, write zeros to these bits.  
Figure 4-6. PTS Service (PTSSRV) Register  
4-8  
     
5
I/O Ports  
CHAPTER 5  
I/O PORTS  
The I/O ports of the 8XC196Lx are functionally identical to those of the 8XC196Jx. However, on  
the 87C196LA and LB, the reset state level of all 41 general-purpose I/O pins has changed from  
a weak logic “1” (wk1) to a weak logic “0” (wk0). This chapter outlines the differences between  
the 87C196LA, LB and the 8XC196Kx controllers.  
5.1 I/O PORTS OVERVIEW  
Table 5-1 provides an overview of the 8XC196Lx and 8XC196Kx I/O ports.  
Table 5-1. Microcontroller Ports  
Configuration  
Options  
Associated Peripheral or  
System Function  
Port  
Pins  
8 (Kx)  
Type  
A/D converter  
(not supported on LD)  
Port 0  
Port 1  
Standard  
Input-only  
6 (CA, Jx, Lx)  
8 (Kx)  
4 (CA, Jx, Lx)  
Complementary  
Open-drain  
Standard  
Standard  
EPA and timers  
J1850 (LB only), SIO,  
interrupts, bus control, clock  
gen.  
8 (Kx)  
6 (CA, Jx, Lx)  
Complementary  
Open-drain  
Port 2  
Complementary  
Open-drain  
Port 3  
Port 4  
Port 5  
Port 6  
8
8
Memory mapped  
Memory mapped  
Memory mapped  
Standard  
Address/data bus  
Address/data bus  
Bus control, slave port  
EPA, SSIO  
Complementary  
Open-drain  
8 (Kx)  
3 (CA, Jx, Lx)  
Complementary  
Open-drain  
8 (Kx)  
6 (CA, Jx, Lx)  
Complementary  
Open-drain  
5.2 INTERNAL STRUCTURE FOR PORTS 1, 2, 5, AND 6 (BIDIRECTIONAL  
PORTS)  
Figure 5-1 shows the logic for driving the output transistors, Q1 and Q2. Consult the datasheet  
for specifications on the amount of current that each port can source or sink.  
In I/O mode (selected by clearing a port mode register bit), the port data output and the port di-  
rection registers are input to the multiplexers. These signals combine to drive the gates of Q1 and  
Q2 so that the output is high, low, or high impedance.  
In special-function mode (selected by setting a port mode register bit), SFDIR and SFDATA are  
input to the multiplexers. These signals combine to drive the gates of Q1 and Q2 so that the output  
is high, low, or high impedance. Special-function output signals clear SFDIR; special-function  
5-1  
                         
8XC196LX SUPPLEMENT  
input signals set SFDIR. Even if a pin is to be used in special-function mode, you must still ini-  
tialize the pin as an input or output by writing to the port direction register.  
Resistor R1 provides ESD protection for the pin. Input signals are buffered. The standard ports  
use Schmitt-triggered buffers for improved noise immunity. Port 5 uses a standard input buffer  
because of the high speeds required for bus control functions. The signals are latched into the port  
pin register sample latch and output onto the internal bus when the port pin register is read.  
The falling edge of RESET# turns on transistor Q3, which remains on for about 300 ns, causing  
the pin to change rapidly to its reset state. The active-low level of RESET# turns on transistor Q4,  
which weakly holds the pin low. Q4 remains on, weakly holding the pin low, until your software  
writes to the port mode register.  
NOTE  
P2.7 is an exception. After reset, P2.7 carries the CLKOUT signal (half the  
crystal input frequency) rather than being held low. When CLKOUT is  
selected, it is always a complementary output.  
5-2  
     
I/O PORTS  
Internal Bus  
VCC  
Px_REG  
SFDATA  
0
1
Q1  
I/O Pin  
P
x
_DRV  
0
1
Q2  
SFDIR  
RESET#  
Buffer  
VSS  
P
x_MODE  
R1  
150to 200Ω  
Sample  
Latch  
P
x_PIN  
Q
D
LE  
Read Port  
PH1 Clock  
Medium  
Pullup  
300ns Delay  
Q3  
RESET#  
VSS  
Weak  
Pullup  
RESET#  
R
Q
Q4  
Any Write to Px_MODE  
S
VSS  
A5265-01  
Figure 5-1. Ports 1, 2, 5, and 6 Internal Structure (87C196LA, LB Only)  
5.2.1 Configuring Ports 1, 2, 5, and 6 (Bidirectional Ports)  
Using the port mode register, you can individually configure each pin for port 1, 2, 5, and 6 to  
operate either as a general-purpose I/O signal (I/O mode) or as a special-function signal (special-  
function mode). In either mode, three configurations are possible: complementary output, high-  
5-3  
       
8XC196LX SUPPLEMENT  
impedance input, or open-drain output. The port direction and data output registers select the con-  
figuration for each pin. Complementary output means that the microcontroller drives the signal  
high or low. High-impedance input means that the microcontroller floats the signal. Open-drain  
output means that the microcontroller drives the signal low or floats it. For I/O mode, the port  
data output register determines whether the microcontroller drives the signal high, drives it low,  
or floats it. For special-function mode, the on-chip peripheral or system function determines  
whether the microcontroller drives the signal high or low for complementary outputs.  
The pins for ports 1, 2, 5, and 6 are weakly pulled low during and after reset. Initializing the pins  
by writing to the port mode register turns off the weak pull-downs. To ensure that the ports are  
initialized correctly, follow this suggested initialization sequence:  
1. Write to Px_DIR to configure the individual pins. Clearing a bit configures a pin as a  
complementary output. Setting a bit configures a pin as a high-impedance input or open-  
drain output.  
2. Write to Px_MODE to select either I/O or special-function mode. Writing to Px_MODE  
(regardless of the value written) turns off the weak pull-downs. Even if the entire port is to  
be used as I/O (its default configuration after reset), you must write to Px_MODE to  
ensure that the weak pull-downs are turned off.  
3. Write to Px_REG.  
For complementary output configurations:  
In I/O mode, write the data that is to be driven by the pins to the corresponding Px_REG  
bits. In special-function mode, the value is immaterial because the on-chip peripheral or  
system function controls the pin. However, you must still write to Px_REG to initialize the  
pin.  
For high-impedance input or open-drain output configurations:  
In I/O mode, write to Px_REG to either float the pin, making it available as a high  
impedance input, or pull it low. Setting the corresponding Px_REG bit floats the pin;  
clearing the corresponding Px_REG bit pulls the pin low. In special-function mode, if the  
on-chip peripheral uses the pin as an input signal, you must set the corresponding Px_REG  
bit so that the pin can be driven externally. If the on-chip peripheral uses the pin as an  
output signal, the value of the corresponding Px_REG bit is immaterial because the on-  
chip peripheral or system function controls the pin. However, you must still write to  
Px_REG to initialize the pin.  
5.2.2 Special Bidirectional Port Considerations  
This section outlines special consideration for using the pins of ports 1, 2, 5, and 6.  
1. After reset, your software must configure the device to match the external system. This  
accomplished by writing appropriate configuration data into Px_MODE. Writing to  
Px_MODE not only configures the pins but also turns off the transistor that weakly holds  
the pins low. For this reason, even if your port is to be used as it is configured at reset, you  
should still write data into Px_MODE.  
2. P2.6/TXJ1850 is the enable pin for ONCE mode. Because a high input during reset can  
cause the device to enter ONCE mode or a reserved test mode, caution must be exercised  
5-4  
 
I/O PORTS  
in using this pin. Be certain that your system meets the V specifications during reset to  
IH  
prevent inadvertent entry into ONCE mode or a test mode.  
3. Following reset, P2.7/CLKOUT carries the strongly driven CLKOUT signal. It is not held  
low. When P2.7/CLKOUT is configured as CLKOUT, it is always a complementary  
output.  
5.3 INTERNAL STRUCTURE FOR PORTS 3 AND 4 (ADDRESS/DATA BUS)  
Figure 5-2 shows the logic of ports 3 and 4. Consult the datasheet for specifications on the amount  
of current ports 3 and 4 can source and sink.  
During reset, the active-low level of RESET# turns off Q1 and Q2 and turns on transistor Q4,  
which weakly holds the pin low. Resistor R1 provides ESD protection for the pin. During normal  
operation, the device controls the port through BUS CONTROL SELECT, an internal control sig-  
nal.  
When the device needs to access external memory, it clears BUS CONTROL SELECT, selecting  
ADDRESS/DATA as the input to the multiplexer. ADDRESS/DATA then drives Q1 and Q2 as  
complementary outputs.  
When external memory access is not required, the device sets BUS CONTROL SELECT, select-  
ing Px_REG as the input to the multiplexer. Px_REG then drives Q1 and Q2. If P34_DRV is set,  
Q1 and Q2 are driven as complementary outputs. If P34_DRV is cleared, Q1 is disabled and Q2  
is driven as an open-drain output requiring an external pull-up resistor. With the open-drain con-  
figuration (BUS CONTROL SELECT set and P34_DRV cleared) and Px_REG set, the pin can  
be used as an input. The signal on the pin is latched in the Px_PIN register. The pins can be read,  
making it easy to see which pins are driven low by the device and which are driven high by ex-  
ternal drivers while in open-drain mode.  
5-5  
     
8XC196LX SUPPLEMENT  
Internal Bus  
VCC  
P
x_REG  
1
0
Address/Data  
Q1  
Bus Control Select  
0 = Address/Data  
1 = I/O  
I/O Pin  
Q2  
P34_DRV  
RESET#  
Buffer  
VSS  
R1  
150to 200Ω  
Sample  
Latch  
Px_PIN  
Q
D
LE  
Read Port  
PH1 Clock  
Medium  
Pullup  
300ns Delay  
Q3  
RESET#  
VSS  
Weak  
Pullup  
Q4  
VSS  
A5264-01  
Figure 5-2. Ports 3 and 4 Internal Structure (87C196LA, LB Only)  
5-6  
   
6
Synchronous Serial  
I/O Port  
CHAPTER 6  
SYNCHRONOUS SERIAL I/O PORT  
The synchronous serial I/O (SSIO) port on the 8XC196Lx has been enhanced, implementing two  
new special function registers (SSIO0_CLK and SSIO1_CLK) that allow you to select the oper-  
ating mode and configure the phase and polarity of the serial clock signals.  
6.1 SSIO 0 CLOCK REGISTER  
The SSIO 0 clock (SSIO_CLK) register selects the phase and polarity for the SC0 clock signal.  
In standard mode, SC0 is channel 0’s clock signal. In duplex and channel-select modes, SC0 is  
the common clock signal for both SSIO channels.  
Address:  
Reset State:  
1FB5H  
00H  
SSIO0_CLK  
The SSIO 0 clock (SSIO0_CLK) register configures the serial clock for channel 0. In standard mode,  
the SC0 is channel 0’s clock signal. In duplex and channel-select modes, SC0 is the common clock  
signal for both SSIO channels.  
7
0
PHAS  
POLS  
Bit  
Number  
Bit  
Mnemonic  
Function  
7:2  
Reserved; for compatibility with future devices, write zeros to these bits.  
Phase and Polarity Select  
1
0
PHAS  
POLS  
For normal transfers, these bits determine the idle state of the serial  
clock and select the serial clock signal edge on which the SSIO samples  
incoming data bits or shifts out outgoing data bits. These bits are ignored  
for handshaking transfers. Use SSIO0_ CON to select the type of data  
transfer (normal or handshaking) for channel 0.  
For transmissions  
PHAS  
POLS  
0
0
1
1
0
1
0
1
low idle state; shift on falling edges  
high idle state; shift on rising edges  
low idle state; shift on rising edges  
high idle state; shift on falling edges  
For receptions  
PHAS  
POLS  
0
0
1
1
0
1
0
1
low idle state; sample on rising edges  
high idle state; sample on falling edges  
low idle state; sample on falling edges  
high idle state; sample on rising edges  
Figure 6-1. SSIO 0 Clock (SSIO0_CLK) Register  
6-1  
         
8XC196LX SUPPLEMENT  
For transmissions, SSIO0_CLK determines whether the SSIO shifts out data bits on rising or fall-  
ing clock edges. For receptions, SSIO0_CLK determines whether the SSIO samples data bits on  
rising or falling clock edges.  
6.2 SSIO 1 CLOCK REGISTER  
SSIO1_CLK selects the SSIO mode of operation (standard, duplex, or channel-select), enables  
the channel-select master contention interrupt request, and selects the phase and polarity for the  
serial clock (SC1) for channels. In standard mode, use this register to configure the serial clock  
for channel 1.  
Address:  
Reset State:  
1FB7H  
00H  
SSIO1_CLK  
The SSIO 1 clock (SSIO1_CLK) register selects the SSIO mode of operation (standard, duplex, or  
channel-select), enables the channel-select master contention interrupt request, and selects the  
phase and polarity for the serial clock (SC1) for channel 1.  
7
0
CHS  
DUP  
CONINT  
CONPND  
PHAS  
POLS  
Bit  
Number  
Bit  
Mnemonic  
Function  
7:6  
Reserved; for compatibility with future devices, write zeros to these bits.  
5
4
CHS  
DUP  
These bits determine the SSIO operating mode.  
CHS DUP  
0
0
1
1
0
1
0
1
standard mode  
duplex mode  
channel-select half-duplex mode (uses SD1 only)  
channel-select full-duplex mode (uses both SD0 and SD1)  
3
CONINT  
Master Contention Interrupt  
For channel-select master operations, the SSIO sets the master  
contention interrupt pending bit (CONPND) when the CHS# pin is  
externally activated. In a system with multiple masters, an external  
master activates the CHS# signal to request control of the serial clock.  
CONINT determines whether the SSIO sets both CONPND and the  
SSIO0 interrupt pending bit or only CONPND when the CHS# pin is  
externally activated.  
0 = SSIO sets only CONPND  
1 = SSIO sets both CONPND and the SSIO0 interrupt pending bit  
This bit is valid for channel-select master operations and ignored for all  
other operations.  
Figure 6-2. SSIO 1 Clock (SSIO1_CLK) Register  
6-2  
     
SYNCHRONOUS SERIAL I/O PORT  
Address:  
Reset State:  
1FB7H  
00H  
SSIO1_CLK (Continued)  
The SSIO 1 clock (SSIO1_CLK) register selects the SSIO mode of operation (standard, duplex, or  
channel-select), enables the channel-select master contention interrupt request, and selects the  
phase and polarity for the serial clock (SC1) for channel 1.  
7
0
CHS  
DUP  
CONINT  
CONPND  
PHAS  
POLS  
Bit  
Number  
Bit  
Mnemonic  
Function  
Master Contention Interrupt Pending  
2
CONPND  
For channel-select master operations, the SSIO sets this bit when the  
CHS# pin is externally activated. In a system with multiple masters, an  
external master activates the CHS# signal to request control of the serial  
clock.  
This bit is valid for channel-select master operations and ignored for all  
other operations.  
1
0
PHAS  
POLS  
Phase and Polarity Select  
For normal transfers, these bits determine the idle state of the serial  
clock and select the serial clock signal edge that the SSIO samples  
incoming data bits or shifts out outgoing data bits.  
For transmissions  
PHAS  
POLS  
0
0
1
1
0
1
0
1
low idle state; shift on falling edges  
high idle state; shift on rising edges  
low idle state; shift on rising edges  
high idle state; shift on falling edges  
For receptions  
PHAS  
POLS  
0
0
1
1
0
1
0
1
low idle state; sample on rising edges  
high idle state; sample on falling edges  
low idle state; sample on falling edges  
high idle state; sample on rising edges  
These bits are ignored for duplex and channel-select modes; these  
modes use SC0 as the common clock signal. The SSIO0_CLK register  
contains the phase and polarity select bits for the SC0 clock signal.  
These bits are also ignored for handshaking transfers. Use SSIO1_ CON  
to select the type of data transfer (normal or handshaking) for channel 1.  
Figure 6-2. SSIO 1 Clock (SSIO1_CLK) Register (Continued)  
For transmissions, SSIO1_CLK determines whether the SSIO shifts out data bits on rising or fall-  
ing clock edges. For receptions, SSIO1_CLK determines whether the SSIO samples data bits on  
the rising or falling clock edges.  
6-3  
7
Event Processor  
Array  
CHAPTER 7  
EVENT PROCESSOR ARRAY  
The EPA on the 8XC196Lx is functionally identical to that of the 8XC196Jx; however, the  
8XC196Lx has only two capture/compare channels without pins instead of four. In addition, the  
83C196LD has no compare-only channels.  
7.1 EPA FUNCTIONAL OVERVIEW  
Table 7-1 lists the capture/compare (with and without pins) and compare-only channels for each  
device in the 8XC196Lx and 8XC196Kx families.  
Table 7-1. EPA Channels  
Capture/Compare  
Channels With Pins  
Capture/Compare  
Channels Without Pins  
Compare-only  
Channels  
Device  
8XC196LA, LB  
8XC196LD  
EPA3:0 and EPA9:8  
EPA3:0 and EPA9:8  
EPA3:0 and EPA9:8  
EPA9:0  
EPA7:6  
EPA7:6  
EPA7:4  
COMP1:0  
87C196CA, 8XC196Jx  
8XC196Kx  
COMP1:0  
COMP1:0  
The 8XC196Lx’s EPA performs input and output functions associated with two timer/counters,  
timer 1 and timer 2, as depicted in Figures 7-1 and 7-2.  
7-1  
         
8XC196LX SUPPLEMENT  
Timer-Counter Unit  
TIMER1  
TIMER2  
Capture/Compare  
Channel 0–3  
EPA 3:0 Interrupts  
EPA 3:0  
Capture/Compare  
Channel 6–7  
Capture/Compare  
Channel 8  
EPA8 / COMP0  
EPAx  
Interrupt  
Indirect  
Interrupt  
Processor  
Logic  
Compare-only  
Channel 0  
Capture/Compare  
Channel 9  
EPA9 / COMP1  
Compare-only  
Channel 1  
A5269-01  
Figure 7-1. EPA Block Diagram (87C196LA, LB Only)  
7-2  
   
EVENT PROCESSOR ARRAY  
Timer-Counter Unit  
TIMER1  
TIMER2  
Capture/Compare  
Channel 0–3  
EPA 3:0 Interrupts  
EPA 3:0  
Capture/Compare  
Channel 6–7  
Capture/Compare  
Channel 8  
EPA8  
EPAx  
Interrupt  
Indirect  
Interrupt  
Processor  
Logic  
Capture/Compare  
Channel 9  
EPA9  
A5281-01  
Figure 7-2. EPA Block Diagram (83C196LD Only)  
7-3  
   
8XC196LX SUPPLEMENT  
7.1.1 EPA Mask Registers  
Figures 7-3 and 7-4 illustrate the EPA mask registers, EPA_MASK and EPA_MASK1, for the  
8XC196Lx microcontroller family.  
Address:  
Reset State:  
1FA0H  
0000H  
EPA_MASK  
The EPA interrupt mask (EPA_MASK) register enables or disables (masks) interrupts associated with  
the shared EPAx interrupt.  
15  
8
Lx  
EPA6  
EPA7  
EPA8  
EPA9  
OVR0  
OVR8  
OVR1  
7
0
0VR2  
OVR3  
OVR9  
Bit  
Number  
Function  
15:0  
Setting a bit enables the corresponding interrupt as a EPAx interrupt source. The shared  
EPAx interrupt is enabled by setting its interrupt enable bit in the interrupt mask register  
(INT_MASK.0 = 1).  
Bits 2–5 and 14–15 are reserved on the 8XC196Lx device family. For compatibility with future  
devices, write zeros to these bits.  
Figure 7-3. EPA Interrupt Mask (EPA_MASK) Register  
Address:  
Reset State:  
1FA4H  
00H  
EPA_MASK1  
The EPA interrupt mask 1 (EPA_MASK1) register enables or disables (masks) interrupts associated  
with the multiplexed EPAx interrupt.  
7
0
COMP0  
COMP1  
OVRTM1  
OVRTM2  
Bit  
Number  
Function  
Reserved; for compatibility with future devices, write zeros to these bits.  
7:4  
3:0  
Setting a bit enables the corresponding interrupt as a multiplexed EPAx interrupt source.  
The multiplexed EPAx interrupt is enabled by setting its interrupt enable bit in the  
interrupt mask register (INT_MASK.0 = 1).  
87C196LA, LB only; reserved on 83C196LD.  
Figure 7-4. EPA Interrupt Mask 1 (EPA_MASK1) Register  
7-4  
             
EVENT PROCESSOR ARRAY  
7.1.2 EPA Pending Registers  
Figures 7-5 and 7-6 illustrate the EPA pending registers, EPA_PEND and EPA_PEND1, for the  
8XC196Lx microcontroller family.  
Address:  
Reset State:  
1FA2H  
0000H  
EPA_PEND  
When hardware detects a pending EPA6–9 or OVR0–3, 8–9 interrupt request, it sets the  
corresponding bit in the EPA interrupt pending register (EPA_PEND or EPA_PEND1). The EPAIPV  
register contains a number that identifies the highest priority, active, shared interrupt source. When  
EPAIPV is read, the EPA interrupt pending bit associated with the EPAIPV priority value is cleared.  
15  
8
Lx  
EPA6  
EPA7  
EPA8  
EPA9  
OVR0  
OVR8  
OVR1  
7
0
0VR2  
OVR3  
OVR9  
Bit  
Number  
Function  
15:0  
Any set bit indicates that the corresponding EPAx interrupt source is pending. The bit is  
cleared when software reads the EPA interrupt priority vector register (EPAIPV).  
Bits 2–5 and 14–15 are reserved on the 8XC196Lx device family. For compatibility with future  
devices, write zeros to these bits.  
Figure 7-5. EPA Interrupt Pending (EPA_PEND) Register  
Address:  
Reset State:  
1FA6H  
00H  
EPA_PEND1  
When hardware detects a pending EPAx interrupt, it sets the corresponding bit in the EPA interrupt  
pending register (EPA_PEND or EPA_PEND1). The EPAIPV register contains a number that  
identifies the highest priority, active, multiplexed interrupt source. When EPAIPV is read, the EPA  
interrupt pending bit associated with the EPAIPV priority value is cleared.  
7
0
COMP0  
COMP1  
OVRTM1  
OVRTM2  
Bit  
Number  
Function  
7:4  
Reserved; always write as zeros.  
3:0  
Any set bit indicates that the corresponding EPAx interrupt source is pending. The bit is  
cleared when the EPA interrupt priority vector register (EPAIPV) is read.  
87C196LA, LB only; reserved on 83C196LD.  
Figure 7-6. EPA Interrupt Pending 1 (EPA_PEND1) Register  
7-5  
             
8XC196LX SUPPLEMENT  
7.1.3 EPA Interrupt Priority Vector Register  
Figure 7-7 illustrates the EPA interrupt priority vector (EPAIPV) register for the 8XC196Lx mi-  
crocontroller family.  
Address:  
Reset State:  
1FA8H  
00H  
EPAIPV  
When an EPAx interrupt occurs, the EPA interrupt priority vector (EPAIPV) register contains a number  
that identifies the highest priority, active, multiplexed interrupt source (see Table 7-2).  
EPAIPV allows software to branch via the TIJMP instruction to the correct interrupt service routine  
when EPAx is activated. Reading EPAIPV clears the EPA pending bit for the interrupt associated with  
the value in EPAIPV. When all the EPA pending bits are cleared, the EPAx pending bit is also cleared.  
7
0
PV4  
PV3  
PV2  
PV1  
PV0  
Bit  
Bit  
Mnemonic  
Function  
Number  
5:7  
4:0  
Reserved; for compatibility with future devices, write zeros to these bits.  
Priority Vector  
PV4:0  
These bits contain a number from 01H to 14H corresponding to the  
highest-priority active interrupt source. This value, when used with the  
TIJMP instruction, allows software to branch to the correct interrupt  
service routine.  
Figure 7-7. EPA Interrupt Priority Vector Register (EPAIPV)  
Table 7-2. EPA Interrupt Priority Vectors  
Value  
Interrupt  
Value  
Interrupt  
Value  
Interrupt  
14H  
13H  
12H  
11H  
10H  
0FH  
0EH  
0DH  
0CH  
0BH  
0AH  
09H  
08H  
07H  
OVR1  
OVR2  
OVR3  
06H  
05H  
04H  
03H  
02H  
01H  
00H  
OVR8  
OVR9  
EPA6  
EPA7  
EPA8  
EPA9  
OVR0  
COMP0  
COMP1  
OVRTM1  
OVRTM2  
None  
87C196LA, LB only; reserved on 83C196LD.  
7-6  
           
8
J1850  
Communications  
Controller  
CHAPTER 8  
J1850 COMMUNICATIONS CONTROLLER  
The J1850 communications controller manages communications between multiple network  
nodes. This integrated peripheral supports the 10.4 Kb/s VPW (variable pulse width) medium-  
speed class B in-vehicle network protocol. It also supports both the standard and in-frame re-  
sponse (IFR) message framing as specified by the Society of Automotive Engineering (SAE)  
J1850 (revised May 1994) technical standards. Its lower cost per node makes it suitable for diag-  
nostics and non-real-time data sharing in applications with high numbers of nodes. This chapter  
details the integrated J1850 controller and explains how to configure it.  
8.1 J1850 FUNCTIONAL OVERVIEW  
The integrated J1850 communications controller transfers messages between network nodes ac-  
cording to the J1850 protocol. The complete J1850 communications protocol solution includes  
an on-chip, J1850 digital-logic controller working with an external analog bus transceiver circuit.  
Figure 8-1 illustrates the J1850 protocol with the J1850 controller integrated on the 87C196LB  
16-bit microcontroller and a standalone J1850 bus transceiver device. The example uses the Har-  
ris HIP7020 as the remote transceiver device.  
J1850  
Bus  
TXJ1850  
RXJ1850  
TX  
RX  
HIP7020  
87C196LB  
Microcontroller  
PLL/  
CLKOUT  
Clock  
A5168-01  
Figure 8-1. Integrated J1850 Communications Protocol Solution  
The benefit of an integrated, J1850 protocol solution is threefold:  
Minimizes CPU overhead for reception and transmission of J1850 messages.  
Frees up serial and parallel communications ports for other purposes.  
Offers significant printed-circuit board area savings when compared with conventional  
standalone protocol devices.  
8-1  
         
8XC196LX SUPPLEMENT  
The J1850 controller can handle network protocol functions including message frame sequenc-  
ing, bit arbitration, in-frame response (IFR) messaging, error detection, and delay compensation.  
The J1850 communications controller (Figure 8-2) consists of a control state machine (CSM),  
symbol synchronization and timing (SST) circuitry, six control and status registers, transmit and  
receive buffers, and an interrupt handler.  
J1850 Communications Controller  
J1850ST  
Bus Error  
RX  
J1850RX Interrupt  
Handler  
J1850TX  
TX  
J_DLY  
J_STAT  
Error  
Detection  
Circuitry  
OVR  
UNDR  
J_TX  
Delay  
Compensator  
Symbol  
Encoder  
TXJ1850  
RXJ1850  
Bit  
Arbitration  
Circuitry  
JTX_BUF  
JRX_BUF  
Symbol  
Decoder  
Digital  
Filter  
Cyclic  
Redundancy  
Check Circuitry  
J_RX  
Prescaler  
CSM  
SST  
J_CMD  
J_CFG  
Internal Clocking  
A5169-01  
Figure 8-2. J1850 Communications Controller Block Diagram  
8-2  
   
J1850 COMMUNICATIONS CONTROLLER  
8.2 J1850 CONTROLLER SIGNALS AND REGISTERS  
Table 8-1 describes the J1850 controller’s pins, and Table 8-2 describes the control and status  
registers.  
Table 8-1. J1850 Controller Signals  
Signal  
Type  
Description  
RXJ1850  
I
Receive  
Carries digital symbols from a remote transceiver to the J1850 controller.  
TXJ1850  
O
Transmit  
Carries digital symbols from the J1850 controller to a remote transceiver.  
Table 8-2. Control and Status Registers  
Mnemonic  
Address  
Description  
J_CFG  
1F54H J1850 Configuration  
Program this byte register to specify the oscillator prescaler  
divisor, mode of operation, and normalization bit format. You must  
write to this register during the initialization sequence.  
J_CMD  
1F51H J1850 Command  
Program this byte register to specify the number of bytes to be  
transmitted in the next message frame. This register also  
monitors the status of the message transmission in progress, and  
it can abort, ignore, or retry a message if necessary. Read this  
register to determine the status of transmissions in progress.  
J_DLY  
1F58H J1850 Delay Compensation  
Program this byte register to define the length of the delay time  
through the external transceiver to compensate for the inherent  
propagation delays and to accurately resolve bus contention  
during arbitration. You must write to this register during the  
initialization sequence.  
J_RX  
1F52H J1850 Receiver  
Read this byte register to receive data in byte increments from the  
J1850 bus to the microcontroller CPU. This register is buffered to  
allow for reception of a second data byte while the first data byte  
is being read.  
J_STAT  
1F53H J1850 Status  
Read this byte register to determine the current status of the  
receive and transmit buffers and the J1850 interrupt sources. You  
can also determine bus status and in-frame response messaging  
status. All bits of this register are cleared when read, with the  
exception of the BUS_STAT bit.  
J_TX  
1F50H J1850 Transmitter  
Program this byte register to transmit data in byte increments to  
the J1850 bus from the microcontroller CPU. This register is  
buffered to allow for writing of a second data byte while the first  
data byte is being shifted out.  
8-3  
           
8XC196LX SUPPLEMENT  
Table 8-2. Control and Status Registers (Continued)  
Mnemonic  
INT_MASK  
Address  
Description  
0008H Interrupt Mask  
Bits 6 and 7 in this register enable and disable the J1850 receive  
and transmit interrupt requests, respectively.  
INT_MASK1  
INT_PEND  
INT_PEND1  
PTSSEL  
0013H Interrupt Mask 1  
Bit 0 in this register enables and disables the J1850 bus error  
interrupt request.  
0009H Interrupt Pending  
Bits 6 and 7 in this register, when set, indicate pending J1850  
receive and transmit interrupt requests, respectively.  
0012H Interrupt Pending 1  
Bit 0 in this register, when set, indicates a pending J1850 bus  
error interrupt request.  
0004H PTS Select  
Bits 6, 7, and 8 of this word register select either a PTS service  
request or a standard interrupt service request for J1850TX,  
J1850RX, and J1850ST interrupts, respectively.  
PTSSRV  
0006H PTS Service  
Bits 6, 7, and 8 of this word register are set by hardware to  
request an end-of-PTS interrupt for the J1850.  
8.3 J1850 CONTROLLER OPERATION  
This section describes the control state machine (which contains the cyclic redundancy check  
generator) and the symbol synchronization and timing circuitry for J1850 transmissions and re-  
ceptions.  
8.3.1 Control State Machine  
The control state machine (CSM) represents the engine of the digital circuitry portion of the  
J1850 communications controller. The CSM handles all message framing for standard and in-  
frame response (IFR) messaging, data validation, bus contention, bit arbitration, and error detec-  
tion.  
8.3.1.1  
Cyclic Redundancy Check Generator  
The cyclic redundancy check (CRC) generator circuitry calculates and checks the CRC byte gen-  
erated for both transmitted and received standard messages as specified by SAE J1850 protocol  
specification for class B in-vehicle networks. The CRC calculation is a code byte of information  
that verifies the proper reception or transmission of your message. The calculated CRC code byte  
is always appended as the last byte of your transmitted message. On reception, the calculated  
CRC checksum byte always results in a value of C4H for valid messages. An invalid CRC check-  
sum during reception signals the presence of an error in your incoming message, which immedi-  
ately sets the J1850 bus error (J1850BE) bit in the J_STAT register (Figure 8-19 on page 8-21).  
8-4  
       
J1850 COMMUNICATIONS CONTROLLER  
8.3.1.2  
Bus Contention  
Bus contention arises when multiple nodes attempt to access and transmit message frames across  
the J1850 bus simultaneously. This creates a conflict on the bus. The recognition of conflicting  
symbols or bits on the bus is referred to as contention detection. For example, if a node observes  
a difference between a symbol it transmits to the J1850 bus and the symbol that it detects on the  
bus, that node has detected contention to the transmission of its message frame. Only one message  
frame from one node vying for the bus wins arbitration on each symbol or bit of its frame. This  
winning message frame does not experience or detect contention. The message frames that were  
not awarded arbitration will experience contention.  
8.3.1.3  
Bit Arbitration  
A bit arbitration scheme is used to resolve such conflicts as bus contention. The J1850 protocol  
uses the carrier sense multiple access (CSMA) bit arbitration scheme. Bit arbitration is the pro-  
cess of settling conflicts that occur when multiple nodes attempt to transmit one bit or symbol at  
a time across a single bus. A symbol is simply a timing-level formatted bit. By definition, a node  
that detects contention has lost arbitration and will discontinue transmitting any further symbols  
remaining in its message frame. Remaining nodes vying for the bus will continue to send their  
symbols until the next instance of contention is detected or arbitration is awarded. This process  
continues until a complete message frame from one node has been transmitted. For details on this  
arbitration scheme, refer to the “Bit Arbitration Example” on page 8-7.  
8.3.1.4  
Error Detection  
The J1850 controller’s error detection logic monitors the bus for four error conditions, and sets  
the J1850BE interrupt pending bit in the J_STAT register if an error occurs. The following list  
describes each error type:  
CRC error — the calculated CRC checksum received on incoming messages has a value  
other than C4H (the expected value for all received message frames).  
bus symbol timing error — the symbol stream on the J1850 bus contains an invalid symbol.  
An invalid symbol is any signal that is between 8 µs and 34 µs in duration.  
incomplete byte error — an EOD/EOF symbol occurred,but was not on a byte boundary;  
the number of bits recieved was not a multiple of eight.  
no echo — the message is transmitted; however, the transmission’s echo back through the  
feedback loop to the receiver has not been detected within the allowable 60 µs window.  
8.3.2 Symbol Synchronization and Timing Circuitry  
The symbol synchronization and timing (SST) circuitry consists of a clock prescaler, digital filter,  
delay compensation circuitry, and synchronization and symbol encoding/decoding circuitry. The  
SST supports Huntzicker encoding of symbols, which entails 10.4 Kb/s variable pulse-width  
(VPW) operation for valid edge detection on message receptions.  
8-5  
       
8XC196LX SUPPLEMENT  
8.3.2.1  
Clock Prescaler  
Because the 87C196LB microcontroller can operate at a variety of input frequencies (FXTAL1), the  
clock prescaler circuitry is used to provide a single, internal clock frequency (f/2) to ensure that  
the J1850 peripheral is clocked at the proper operating frequency. This is accomplished through  
the programmable clock prescaler bits, PRE1:0 in the J_CFG register (Figure 8-17 on page 8-18).  
The prescale bits support input frequencies of 8, 12, 16, and 20 MHz on the XTAL1 pin. With  
the phase-locked loop (PLL) circuitry enabled, the prescale bits can support input frequencies of  
4, 6, 8, and 10 MHz on the XTAL1 pin.  
Table 8-3 details the relationships between the input frequency, the configuration of PLL, the in-  
ternal clock frequency, and the prescaler bits.  
Table 8-3. Relationships Between Input Frequency, PLL, and Prescaler Bits  
FXTAL1  
Internal Clock Frequency  
PRE1  
PRE0  
PLL  
PLL  
Enabled  
(f/2)  
Disabled  
8 MHz  
12 MHz  
16 MHz  
20 MHz  
4 MHz  
6 MHz  
8 MHz  
10 MHz  
4 MHz  
6 MHz  
8 MHz  
10 MHz  
0
0
1
1
0
1
0
1
8.3.2.2  
Digital Filter  
To automatically reject noise spikes of 8 µs or less in duration, the J1850 controller uses a digital  
filter between the RXJ1850 input pin and the symbol synchronization logic.  
A noise spike is defined as an active or passive state pulse that is shorter in duration than a valid  
receive symbol at that state. A valid receive symbol is at least 34 µs in duration. Any symbol cap-  
tured on the bus between 8 µs and 34 µs in duration is considered invalid and is flagged by the  
J_STAT register as a bus-symbol timing error.  
8.3.2.3  
Delay Compensation  
Because the digital portion of the J1850 protocol is integrated onto the microcontroller and phys-  
ically separated from the transceiver and J1850 bus, control over critical timing parameters of  
various manufacturers’ remote transceivers is required. The delay compensation circuitry ad-  
dresses this requirement by providing the flexibility to compensate for propagation delay and  
pulse-width variations among various transceivers. The compensation circuitry synchronizes it-  
self to the leading edge of each input symbol, which allows for accurate detection of bus conten-  
tion during bit arbitration. The delay compensation is programmable through the J_DLY register  
(Figure 8-18 on page 8-20).  
8.3.2.4  
Symbol Encoding and Decoding  
The J1850 protocol supports the Huntzicker encoding method, which is based on variable pulse-  
width (VPW) bus modulation. VPW modulation is a forced high/low symbol transition formatting  
scheme that tracks the duration between two consecutive transitions and the level of the bus, ac-  
tive or passive (Figure 8-3).  
8-6  
           
J1850 COMMUNICATIONS CONTROLLER  
64µS  
1
1
0
128µS  
or  
or  
0
"passive 1"  
"active 1"  
128µS  
1
1
0
64µS  
0
"passive 0"  
"active 0"  
A5219-01  
Figure 8-3. Huntzicker Symbol Definition for J1850  
A symbol is defined as a timing-level formatted bit. The VPW symbol timing requirements stip-  
ulate that there is one symbol per transition and one transition per symbol. This ensures that a  
message frame will always result in a uniform square waveform of varying level durations. Fig-  
ure 8-4 depicts a typical Huntzicker formatted data byte of hex value CCH.  
"1"  
B7  
"1"  
B6  
"0"  
B5  
"0"  
B4  
"1"  
B3  
"1"  
B2  
"0"  
B1  
"0"  
B0  
A5222-01  
Figure 8-4. Typical VPW Waveform  
Bits 7 and 3 carry logic level 1 data; however, they are represented by a passive-level symbol in  
keeping with the VPW requirements. Bits 4 and 0 carry logic level 0 data and are represented by  
an active-level symbol.  
8.3.3 Bit Arbitration Example  
The drive capacity of each symbol establishes the priority for arbitration. By definition, an active  
bus level is a driven state, and a passive bus level is a non-driven, or idle, state. A driven bus state  
is always given priority over an idle bus in arbitration. An “active 0” state has priority over an  
“active 1” state in arbitration, because the “active 0” state is driven over a longer duration, 128  
µs versus the “active 1” state’s drive time of 64 µs. Similarly, a “passive 0” state has priority over  
a “passive 1” state, because the “passive 0” state comes out of its idle state in a shorter period of  
time, 64 µs versus the “passive 1” state’s idle time of 128 µs.  
For example, Figure 8-5 illustrates four nodes vying for the bus. Node B is the first node to dis-  
continue transmitting when it attempts to transmit a “passive 1” symbol onto the bus. At the point  
8-7  
           
8XC196LX SUPPLEMENT  
of arbitration, nodes A, C, and D are all transmitting an “active 0” symbol, thus the idle state of  
the “passive 1” symbol is overruled in favor of the driven state of the “active 0” symbol.  
Node C is the next node to discontinue transmitting when it attempts to take control of the bus by  
transmitting an “active 1” symbol. However, nodes A and D maintain control by continuing to  
drive the bus with an “active 0” symbol.  
Finally, node D discontinues transmitting when its attempt to hold the bus in an idle state is over-  
ruled by the driven state of the “active 1” symbol on node A. Thus, node A is awarded arbitration.  
The busline signal, detected on the bus by the receiver, reflects node A’s message, as this is the  
only node that did not experience contention.  
"0"  
"0"  
"0"  
"0"  
"0"  
"0"  
"0"  
"0"  
"0"  
"0"  
"1"  
"0"  
"0"  
"1"  
Node A  
Node B  
Node C  
Node D  
Busline  
"1"  
Point of  
Arbitration  
Point of  
Arbitration  
"0"  
"0"  
"0"  
"0"  
"1"  
"1"  
"1"  
"0"  
"1"  
Point of  
Arbitration  
A5223-01  
Figure 8-5. Bit Arbitration Example  
8.4 MESSAGE FRAMES  
A message transmission or reception is transferred within a message frame that adds control and  
error-detection bits to the content of the message. The frame for an IFR message differs slightly  
from that for a standard message, but they contain similar information (Figure 8-6).  
8-8  
     
J1850 COMMUNICATIONS CONTROLLER  
Standard Frame  
S
O
F
E
O
D
E
O
F
I
F
S
1 Byte  
CRC  
1-3 Bytes  
Header  
1-11 Bytes  
Data  
In-frame Response (IFR) Frame  
S
O
F
E
O
D
E
O
D
E
O
F
I
F
S
1 Byte  
CRC  
0-1 Byte  
CRC  
1-32 Bytes  
IFR Data  
1-3 Bytes  
Header  
1-11 Bytes  
Data  
N
B
The number of data bytes to be transferred is unspecified if 0EH is written to J_CMD3:0.  
A5225-01  
Figure 8-6. J1850 Message Frames  
A standard message frame is initiated by the responder and contains no more than 11 data bytes  
to be transmitted. An IFR message is a request initiating the recipient(s) to respond by transmit-  
ting data within the same frame. The following subsections describe each of the messaging forms.  
8.4.1 Standard Messaging  
A standard message frame can best be described as a “send mode only” format that is initiated by  
the responder either to request information or to reply to a received message from a remote node.  
In addition to the actual data that is being transmitted, the standard message is composed of a  
header (1–3 bytes), a CRC byte, and a series of start and end symbols.  
8.4.1.1  
Header  
The header provides general information on the physical network and the necessary interface re-  
quirements. For a complete description of the header, refer to theSociety of Automotive Engineer-  
ing (SAE) J1850 specifications (revised May 1994).  
8.4.1.2  
CRC Byte  
The CRC byte, calculated through the cyclic redundancy check generator, is a checksum value  
that verifies the accuracy of the data message transmitted onto the bus. The CRC byte is appended  
to all data messages and optionally appended to IFR response messages. Upon reception, the  
CRC byte is compared with the value C4H. If the values match, the transmitted message is valid;  
otherwise, it is invalid, and an error flag in the J_STAT register is set.  
8.4.1.3  
Normalization Bit  
The normalization bit (NB), found only in IFR messaging, defines the start of the IFR message  
response data. The NB is triggered by bit J_CMD.6 and is transmitted after an end-of-data (EOD)  
symbol is detected on the bus. The timing format of the NB is assigned by the J_CFG register  
8-9  
           
8XC196LX SUPPLEMENT  
(J_CFG.7) and considers whether the IFR message response has a CRC byte appended. Figure  
8-7 depicts the SAE preferred, active-level state bit format timing for the NB.  
64µS  
128µS  
1
0
1
0
or  
NB for IFR without CRC  
NB for IFR with CRC  
A5220-01  
Figure 8-7. Huntzicker Symbol Definition for the Normalization Bit  
Start and End Message Frame Symbols  
8.4.1.4  
Five symbols are used to mark the start and end of a message frame and to allow the J1850 bus  
to properly recognize the interruption of a message transmission or reception. Figure 8-8 illus-  
trates the formats and their respective timing.  
The following is a description of each symbol:  
start of frame (SOF) — this symbol signals the start of a message frame. This is an active-  
level state symbol only and appears once per frame.  
end of data (EOD) — this symbol signals the end of the data transmission. This is a passive-  
level state symbol only. It appears twice in IFR messaging: at the end of the initial request  
data field and at the end of the IFR data field.  
end of frame (EOF) — this symbol signals the end of a message frame and returns the bus  
to an idle state. This is a passive-level state symbol only. It appears once per frame.  
in-frame separation (IFS) — the timing of this symbol allows for proper synchronization of  
multiple nodes during back-to-back transmissions. Nodes contending for the bus must  
comply with one of two conditions before transmitting:  
— wait for the IFS minimum timing to expire  
— wait for a rising edge on the bus after the EOF minimum timing has expired  
break (BRK) — this symbol signals an interruption during a bus transmission. At the point  
of termination, all nodes are reset. This is an active-level state symbol.  
8-10  
     
J1850 COMMUNICATIONS CONTROLLER  
200µS  
1
0
"Start of Frame (SOF)"  
1
0
200µS  
"End of Data (EOD)"  
1
0
280µS  
"End of Frame (EOF)"  
1
0
300µS+  
"In-frame Separation (IFS)"  
768µS+  
1
0
"Break Signal (BRK)"  
A5221-01  
Figure 8-8. Definition for Start and End of Frame Symbols  
Table 8-4 details the symbol timing characteristics supported by the 87C196LB.  
Table 8-4. Huntzicker Symbol Timing Characteristics  
Name  
Symbol Bus Level TTXmin TTXnom TTXmax TRXmin TRXmax Units  
Passive  
Active  
60  
122  
122  
60  
64  
128  
128  
64  
68  
134  
134  
68  
34  
96  
<96  
<163  
<163  
<96  
µs  
µs  
µs  
µs  
µs  
µs  
µs  
µs  
µs  
Logic Level 0  
0
Passive  
Active  
96  
Logic Level 1  
1
34  
Start of Frame  
End of Data  
SOF  
EOD  
EOF  
IFS  
Active  
193  
193  
271  
>300  
768  
200  
200  
280  
207  
207  
289  
163  
163  
239  
>300  
>239  
<239  
<239  
<300  
Passive  
Passive  
Passive  
Active  
End of Frame  
In-frame Separation  
Break  
BRK  
NOTE: Timings are based on the standard bus rate of 10.4 Kb/s. When operating in 4x mode, the bus  
rate becomes 41.6 Kb/s and all symbol timings are one fourth that shown.  
8-11  
       
8XC196LX SUPPLEMENT  
8.4.2 In-frame Response Messaging  
There are three types of in-frame response (IFR) message framings: type 1 (a single byte from a  
single responder), type 2 (a single byte from multiple responders), and type 3 (multiple bytes from  
a single responder). Like the standard message frame, the IFR frame is composed of header, data,  
and CRC bytes, and a series of start and end symbols. Unlike the standard message frame, the  
actual length of the IFR message frame will differ based on the desired response.  
Consider the following example: a system’s controller (the requestor) requests an information up-  
date from each of four nodes (the responders) in the system. With type 1 messaging, the controller  
can receive a limited information update if it sends out four separate transmissions. With type 2  
messaging, the controller can receive a limited information update by sending one message. With  
type 3 messaging, the controller can receive unlimited information; however, it will require four  
separate transmissions. The following subsections detail this example for the three IFR messag-  
ing types.  
8.4.2.1  
IFR Messaging Type 1: Single Byte, Single Responder  
No IFR messaging type carries a distinct advantage or disadvantage over the other messaging  
types. IFR messaging type 1 (Figure 8-9) is ideal for use when requesting small amounts of in-  
formation from a single source in your system. In the above example, suppose you want to know  
how many pounds of pressure each of the four remote node sites experienced after the controller  
sent out a request to each node sensor to exert a given amount of pressure. If you use type 1 mes-  
saging, the controller will send four separate serial messages to the remote node sites in the sys-  
tem and wait for their responses. Keeping the data timing a constant, the CPU overhead of  
transmitting these messages alone amounts to a minimum of 4.96 ms (refer to Table 8-4 on page  
8-11 for all symbol timings).  
In-frame Response (IFR) Frame  
S
O
F
E
O
D
E
O
D
E
O
F
I
F
S
1 Byte  
CRC  
0-1 Byte  
CRC  
1Byte  
IFR Data  
1-3 Bytes  
Header  
1-11 Bytes  
Data  
N
B
The number of data bytes to be transferred is unspecified if 0EH is written to J_CMD3:0.  
Figure 8-9. IFR Type 1 Message Frame  
8.4.2.2  
IFR Messaging Type 2: Single Byte, Multiple Responders  
When response time is the highest consideration, IFR messaging type 2 is desirable. IFR type 2  
messaging can monitor up to 32 remote nodes on a given request (see Figure 8-10). While it al-  
lows only one byte of information per response, in many cases a single byte of information is  
more than adequate. In our example, suppose that each node sensor detected a pressure of 75  
P.S.I. (pounds per square inch). The response (the value 75) would take a single byte, 46H, to  
communicate the reply. The maximum overhead required is 1.24 ms, or one fourth the time it  
would take type 1 messaging to achieve the same results.  
8-12  
           
J1850 COMMUNICATIONS CONTROLLER  
††  
IFR Data Field  
In-frame Response (IFR) Frame  
S
O
F
E
O
D
E
O
D
E
O
F
I
F
S
1 Byte  
CRC  
0-1 Byte  
CRC  
1-3 Bytes  
Header  
1-11 Bytes  
Data  
N
B
D
D
. . . . . . . . . .  
D
31  
0
1
The number of data bytes to be transferred is unspecified if 0EH is written to J_CMD3:0.  
††  
X
A5227-01  
Figure 8-10. IFR Type 2 Message Frame  
8.4.2.3  
IFR Messaging Type 3: Multiple Bytes, Single Responder  
IFR messaging type 3 (Figure 8-11) is ideal for requesting large amounts of information from a  
single source in your system. You can compile up to 12 bytes of data from a remote node on a  
single request. In our example, for the same amount of CPU overhead as IFR type 1 messaging  
exhausted (4.96 ms), you can gather up to twelve times as much information.  
In-frame Response (IFR) Frame  
S
O
F
E
O
D
E
O
D
E
O
F
I
F
S
1 Byte  
CRC  
0-1 Byte  
CRC  
1-12 Bytes  
IFR Data  
1-3 Bytes  
Header  
1-11 Bytes  
Data  
N
B
The number of data bytes to be transferred is unspecified if 0EH is written to J_CMD3:0.  
A5228-01  
Figure 8-11. IFR Type 3 Message Frame  
8.5 TRANSMITTING AND RECEIVING MESSAGES  
The J1850 controller can transmit and receive messages in either standard or IFR form.  
8.5.1 Transmitting Messages  
To transmit a standard message, prepare the message in register RAM and then write it to the  
J1850 transmit (J_TX) register (Figure 8-12) one byte at a time.  
8-13  
             
8XC196LX SUPPLEMENT  
J_TX  
Address:  
Reset State:  
1F50H  
00H  
The J1850 transmitter (J_TX) register transfers data in byte increments to the J1850 bus from the  
microcontroller CPU. This register is buffered to allow for transmission of a second data byte while the  
first data byte is being shifted out. This byte register can be read or written, and is addressable  
through windowing.  
7
0
Transmit Byte  
Bit  
Bit  
Function  
Number Mnemonic  
7:0 DB7:0  
Data Bits  
These eight bits compose the data byte to be transmitted to the J1850 bus.  
Figure 8-12. J1850 Transmitter (J_TX) Register  
Transmitting the message requires that you first program the J1850 command (J_CMD) register  
to specify the number of bytes you want to transfer across the J1850 bus. The number of bytes  
specified must include the header byte(s). After the start of frame (SOF) symbol is put on the bus,  
the first header byte is transferred to J_TX for transmission. This byte will automatically be trans-  
ferred into the J1850 transmit buffer (JTX_BUF) and the second byte of the message frame will  
be written to J_TX. The transfer of the first byte to JTX_BUF triggers the transmission process  
and generates the J1850 transmission (J1850TX) interrupt (if it is enabled), signaling that J_TX  
is available for another byte (Figure 8-13).  
CPU  
J_TX  
Message transmit  
interrupt (J1850TX) set  
JTX_BUF  
J1850 Bus  
A5235-01  
Figure 8-13. J1850 Transmit Message Structure  
After the byte in JTX_BUF is transmitted, the byte residing in J_TX is automatically shifted into  
JTX_BUF, freeing J_TX for another byte. This process continues until the CSM has resolved the  
number of message bytes (MSG3:0) programmed into the J_CMD register.  
If the last message byte being transmitted is shifted out before the MSGx count expires, a  
J1850ST core interrupt is generated and the OVR_UNDR (J_STAT.3) bit records a transmitter  
underflow error in the J_STAT register.  
8-14  
         
J1850 COMMUNICATIONS CONTROLLER  
NOTE  
An overrun condition can occur on transmission if the transmit buffer,  
JTX_BUF, is overwritten.  
8.5.2 Receiving Messages  
For a message reception, after a SOF is detected on the bus, the controller starts to shift data sym-  
bols into the J1850 receive buffer (JRX_BUF) until an entire data byte has been received. This  
byte is automatically transferred into the J1850 receive (J_RX) register (Figure 8-14) and the sub-  
sequent byte is written into the empty JRX_BUF.  
Address:  
Reset State:  
1F52H  
00H  
J_RX  
The J1850 receiver (J_RX) register transfers received data in byte increments from the J1850 bus to  
the microcontroller CPU. This register is buffered to allow for reception of a second data byte while  
the first data byte is being read. This byte register can be read or written, and is addressable through  
windowing.  
7
0
Receive Byte  
Bit  
Bit  
Function  
Number Mnemonic  
7:0 DB7:0  
Data Bits  
These eight bits compose the last data byte received from the J1850 bus.  
Figure 8-14. J1850 Receiver (J_RX) Register  
The transfer of the first byte to J_RX triggers the reception process and generates the J1850 re-  
ception (J1850RX) interrupt (if it is enabled), signaling that JRX_BUF is available for another  
byte (Figure 8-15).  
J1850 Bus  
JRX_BUF  
Message receive  
interrupt (J1850RX) set  
J_RX  
CPU  
A5236-01  
Figure 8-15. J1850 Receive Message Structure  
After J_RX is read, the byte residing in JRX_BUF is automatically shifted into J_RX, freeing  
JRX_BUF for another reception. This process continues until an end of data (EOD) symbol is en-  
countered.  
8-15  
           
8XC196LX SUPPLEMENT  
If a third byte is received before J_RX is read, a J1850ST core interrupt is generated and the  
OVR_UNDR (J_STAT.3) bit records a receiver overrun error in the J_STAT register.  
8.5.3 IFR Messages  
In-frame response (IFR) messaging is identical in setup to standard messaging for both transmis-  
sion and reception. It uses the same registers to configure, communicate, and control data. The  
difference is that the requestor initiating the IFR message sequence writes the message specifying  
a response from either one or more nodes in the system. Framing a message in this manner by-  
passes needless CPU overhead that can result from lengthy EOF symbols, and it gives you a faster  
response to the information you are accessing from remote sites in your system. (Refer to “In-  
frame Response Messaging” on page 8-12 for a detailed explanation).  
8.6 PROGRAMMING THE J1850 CONTROLLER  
This section explains how to configure the J1850 controller. Several registers combine to control  
the configuration: the command register, the configuration register, the delay compensation reg-  
ister, and the status register.  
Programming the J1850 controller requires that you first program the configuration and delay  
registers during initialization. You need to program these two registers only once per initializa-  
tion sequence.  
After initialization, you must first program the command register, followed by either the receive  
or transmit register, and then the status register.  
8.6.1 Programming the J1850 Command (J_CMD) Register  
The J1850 command register (Figure 8-16) determines the messaging type, specifies the number  
of bytes to be transmitted in the next message frame, and updates the status of the message trans-  
mission in progress.  
8-16  
     
J1850 COMMUNICATIONS CONTROLLER  
Address:  
Reset State:  
1F51H  
00H  
J_CMD  
The J1850 command (J_CMD) register determines the messaging type, specifies the number of bytes  
to be transmitted in the next message frame, and updates the status of the message transmission in  
progress. This byte register can be directly addressed through windowing. You must write to this  
register prior to transmitting every message.  
7
0
AUTO  
IFR  
IGNORE  
ABORT  
MSG3  
MSG2  
MSG1  
MSG0  
Bit  
Bit  
Function  
Number Mnemonic  
7
AUTO  
Automatic Transmit Retry  
This bit, when arbitration is lost on the first byte of your message, prompts  
the transmitter to automatically retry until the byte is successfully  
transmitted. Automatic retry applies only to the first byte.  
0 = normal operation  
1 = enable automatic retry  
6
IFR  
In-frame Response Indicator  
This bit signals that a normalization bit (NB) is to be sent after an end-of-  
data symbol is detected on the bus and that the subsequent byte written to  
the J1850 transmitter (J_TX) register is an in-frame response (IFR).  
0 = standard messaging  
1 = next byte written to J_TX is an IFR  
5
4
IGNORE  
ABORT  
Ignore Incoming Message  
This bit instructs the bus to ignore the incoming message until an EOF  
symbol is detected. The bit is cleared after an EOF symbol is detected.  
0 = normal operation  
1 = ignore incoming message  
Abort Transmission  
This bit aborts any transmission in progress and flushes the transmit buffer  
(JTX_BUF). To prevent another node from mistakenly assuming that the  
last byte was a CRC byte, two extra ‘1’s are appended.  
0 = normal operation  
1 = abort transmission in progress  
3:0  
MSG3:0  
Message  
These four bits specify the number of bytes to be transmitted in the next  
message frame. This number includes the header, but not the CRC byte. In  
normal messaging, the maximum number of bytes you can transmit in a  
message frame is eleven.  
MSG3:0  
Operation  
Purpose  
FH  
Termination byte  
Terminate block transmission  
EH  
Block transmission Transmit unspecified number of bytes  
DH  
CH  
B:0H  
Reserved  
Reserved  
Normal messaging Transmit specified number of bytes  
Figure 8-16. J1850 Command (J_CMD) Register  
8-17  
     
8XC196LX SUPPLEMENT  
8.6.2 Programming the J1850 Configuration (J_CFG) Register  
The J1850 configuration register (Figure 8-17) selects the proper oscillator prescaler, initiates a  
transmission break for debugging, invokes clock quadrupling operation, and selects the normal-  
ization bit format.  
Address:  
Reset State:  
1F54H  
00H  
J_CFG  
The J1850 configuration (J_CFG) register selects the proper oscilator prescaler, initiates transmission  
break for debug, invokes clock quadrupling operation, and selects the normalizartion bit format. This  
byte register can be directly addressed through windowing. All J1850 bus activity is ignored until you  
first write to this register.  
7
0
NBF  
IFR3  
4XM  
TXBRK  
RXPOL  
PRE1  
PRE0  
Bit  
Bit  
Function  
Number Mnemonic  
7
NBF  
Normalization Bit Format  
This bit specifies which normalization bit (NB) format is to be used.  
IFR with CRC Byte  
IFR without CRC Byte  
0 =  
1 =  
active long NB  
active short NB  
0 =  
1 =  
active short NB  
active long NB  
6
5
4
3
IFR3  
Type 3 IFR Messaging  
This bit selects type 3 IFR messaging, which supports the in-frame transfer  
of an unspecified number of data bytes.  
0 = normal operation  
1 = type 3 IFR messaging  
4XM  
Oscillator Quadruple (4x) Mode  
This bit allows the J1850 peripheral to operate at four times the normal bit  
transfer rate (41.6 Kb/s versus 10.4 Kb/s).  
0 = normal operation  
1 = 4x mode operation  
TXBRK  
RXPOL  
Transmission Break  
This bit will terminate any transmission in progress by writing a break (BRK)  
symbol to the bus.  
0 = normal operation  
1 = transmit BRK symbol onto bus  
Receive Polarity  
This bit changes the polarity of the receive symbol.  
0 = normal operation – Rx input inverted  
1 = receive polarity enabled – Rx input non-inverted  
Figure 8-17. J1850 Configuration (J_CFG) Register  
8-18  
       
J1850 COMMUNICATIONS CONTROLLER  
Address:  
Reset State:  
1F54H  
00H  
J_CFG  
The J1850 configuration (J_CFG) register selects the proper oscilator prescaler, initiates transmission  
break for debug, invokes clock quadrupling operation, and selects the normalizartion bit format. This  
byte register can be directly addressed through windowing. All J1850 bus activity is ignored until you  
first write to this register.  
7
0
NBF  
IFR3  
4XM  
TXBRK  
RXPOL  
PRE1  
PRE0  
Bit  
Bit  
Function  
Number Mnemonic  
2
Reserved; for compatibility with future devices, write zero to this bit.  
J1850 Oscillator Prescaler  
1:0  
PRE1:0  
These bits ensure proper operation of the J1850 peripheral at the supported  
input frequencies (FXTAL1).  
PRE1  
PRE0  
FXTAL1  
0
0
1
1
0
1
0
1
8 MHz  
12 MHz  
16 MHz  
20 MHz  
Figure 8-17. J1850 Configuration (J_CFG) Register (Continued)  
8.6.3 Programming the J1850 Delay Compensation (J_DLY) Register  
The J1850 delay compensation register (Figure 8-18) allows you to program the necessary delay  
time through the external transceiver to compensate for the inherent propagation delays and to  
accurately resolve bus contention during arbitration.  
8-19  
 
8XC196LX SUPPLEMENT  
J_DLY  
Address:  
Reset State:  
1F58H  
00H  
The J1850 delay (J_DLY) register allows you compensate for the inherent propagation delays and to  
accurately resolve bus contention during arbitration. This byte register can be directly addressed  
through windowing.  
7
0
DLY4  
DLY3  
DLY2  
DLY1  
DLY0  
Bit  
Bit  
Function  
Number Mnemonic  
7:5  
Reserved; for compatibility with future devices, write zeros to these bits.  
Delay Time  
4:0  
DLY4:0  
These five bits specify the desired propagation delay between the J1850  
controller circuitry and the off-chip transceiver device, in units of  
microseconds (µs).  
Figure 8-18. J1850 Delay (J_DLY) Register  
8-20  
     
J1850 COMMUNICATIONS CONTROLLER  
8.6.4 Programming the J1850 Status (J_STAT) Register  
The J1850 status register (Figure 8-19) provides the current status of the message and the four  
interrupt sources associated with the J1850 protocol.  
Address:  
Reset State:  
1F53H  
00H  
J_STAT  
The J1850 status (J_STAT) register provides the current status of the message transfer, the receive  
and transmit buffers, and the four interrupt sources associated with the J1850 protocol. This byte  
register can be directly addressed through windowing. You must write to this register before  
transmitting each message. Reading this register clears all bits except BUS_STAT.  
7
0
IFR_RCV  
BUS_CONT  
BUS_STAT BRK_RCV  
OVR_UNDR  
MSG_TX  
MSG_RX  
J1850BE  
Bit  
Bit  
Function  
Number Mnemonic  
7
6
5
4
3
IFR_RCV  
In-frame Response Received  
This bit indicates whether the IFR byte has been received and is ready to  
be read from the J1850 receiver (J_RX) register.  
0 = no action  
1 = IFR byte received  
BUS_CONT J1850 Bus Contention  
This bit indicates whether bus contention has been detected and arbitration  
has been lost.  
0 = no action  
1 = bus contention  
BUS_STAT  
BRK_RCV  
J1850 Bus Status  
This bit indicates whether a transmission or reception is in progress on the  
J1850 bus.  
0 = J1850 bus idle  
1 = J1850 bus busy  
Break Received  
This bit indicates whether a BRK symbol has been detected on the J1850  
bus.  
0 = no action  
1 = BRK symbol detected  
OVR_UNDR Receive Overrun/Transmit Underflow Interrupt  
This bit indicates whether a receive buffer overrun (OVR) or transmit buffer  
underflow (UNDR) has occurred. An overrun occurs when a symbol is  
received while both J_RX and JRX_BUF contain unread bytes. An  
underflow occurs when a transmission is attempted while both J_TX and  
JTX_BUF are empty.  
0 = normal operation  
1 = OVR or UNDR detected  
Figure 8-19. J1850 Status (J_STAT) Register  
8-21  
         
8XC196LX SUPPLEMENT  
J_STAT  
Address:  
Reset State:  
1F53H  
00H  
The J1850 status (J_STAT) register provides the current status of the message transfer, the receive  
and transmit buffers, and the four interrupt sources associated with the J1850 protocol. This byte  
register can be directly addressed through windowing. You must write to this register before  
transmitting each message. Reading this register clears all bits except BUS_STAT.  
7
0
IFR_RCV  
BUS_CONT  
BUS_STAT BRK_RCV  
OVR_UNDR  
MSG_TX  
MSG_RX  
J1850BE  
Bit  
Bit  
Function  
Number Mnemonic  
2
1
0
MSG_TX  
MSG_RX  
J1850BE  
Message Transmit Interrupt  
This bit signals the successful transmission of a message upon detecting  
the EOD symbol.  
0 = no action  
1 = message transmitted  
Message Receive Interrupt  
This bit signals the successful reception of a message upon detecting the  
EOD symbol.  
0 = no action  
1 = message received  
J1850 Bus Error Interrupt  
This bit is set if one or more of the following conditions occur:  
the calculated CRC for a received message does not equal C4H  
an incomplete byte is received on the bus  
an invalid bus symbol is detected on the bus  
a transmission occurs and the feedback through the receiver is not  
detected within 60 µs  
Figure 8-19. J1850 Status (J_STAT) Register (Continued)  
8-22  
9
Minimum Hardware  
Considerations  
CHAPTER 9  
MINIMUM HARDWARE CONSIDERATIONS  
This chapter discusses the major hardware consideration differences between the 8XC196Lx and  
the 8XC196Kx. The 8XC196Lx has implemented a reset source SFR that reveals the source of  
the most recent reset request.  
9.1 IDENTIFYING THE RESET SOURCE  
The reset source (RSTSRC) register indicates the source of the last reset that the microcontroller  
encountered (Figure 9-1). If more than one reset occurs at the same time, all of the corresponding  
RSTSRC bits are set. Reading this SFR clears all the register bits.  
Address:  
Reset State:  
1F92H  
XXH  
RSTSRC  
(1)  
The reset source (RSTSRC) register indicates the source(s) of the last reset that the microcontroller  
encountered.  
7
0
CFDRST WDTRST  
SFWRST EXTRST  
Bit  
Number  
Bit  
Mnemonic  
Function  
7:4  
Reserved; for compatibility with future devices, write zeros to these bits.  
3
2
1
CFDRST  
WDTRST  
SFWRST  
Clock Failure Detection Reset  
When set, this bit indicates that a failed clock caused the last reset.  
Watchdog Timer Reset  
When set, this bit indicates that the watchdog timer caused the last reset.  
Software Reset  
When set, this bit indicates that either the RST instruction or the IDLPD  
instruction used with an illegal key caused the last reset.  
0
EXTRST  
External Reset  
When set, this bit indicates that the RESET# pin being asserted caused the  
last reset.  
NOTE:  
1. The State of the RSTSRC register is inderterminate on a V power up condition. All other reset  
CC  
states will have the corresponding reset event bit set in the register.  
Figure 9-1. Reset Source (RSTSRC) Register  
9-1  
           
8XC196LX SUPPLEMENT  
9.2 DESIGN CONSIDERATIONS FOR 8XC196LA, LB, AND LD  
With the exception of a few new multiplexed functions, the 8XC196Lx microcontrollers are pin  
compatible with the 8XC196Jx microcontrollers. The 8XC196Jx microcontrollers are 52-lead  
versions of 8XC196Kx microcontrollers.  
Follow these recommendations to help maintain hardware and software compatibility between  
the 8XC196Lx, 8XC196Kx, and future microcontrollers.  
Bus width. Since the 8XC196Lx has neither a WRH# nor a BUSWIDTH pin, the  
microcontroller cannot dynamically switch between 8- and 16-bit bus widths. Program the  
CCBs to select 8-bit bus mode.  
Wait states. Since the 8XC196Lx has no READY pin, the microcontroller cannot rely on a  
READY signal to control wait states. Program the CCBs to limit the number of wait states  
(0, 1, 2, or 3).  
EPA6–EPA7. These functions exist in the 8XC196Lx, but the associated pins are omitted.  
You can use these functions as software timers, to start A/D conversions (on 87C196LA  
and LB only), or to reset the timers.  
Slave port. Since the 8XC196Lx has no P5.1/SLPCS and P5.4/SLPINT pins, you cannot  
use the slave port.  
ONCE mode. On the 8XC196Lx, the ONCE mode entry function is multiplexed with P2.6  
(and TXJ1850 on the 87C196LB) rather than with P5.4 as it is on the 8XC196Kx  
(P5.4/SLPINT/ONCE).  
NMI. Since the 8XC196Lx has no NMI pin, the nonmaskable interrupt is not supported.  
Initialize the NMI vector (at location 203EH) to point to a RET instruction. This method  
provides glitch protection only.  
I/O ports. The following port pins do not exist in the 8XC196Lx: P0.0–P0.1, P1.4–P1.7,  
P2.3 and P2.5, P5.1 and P5.4–P5.7, P6.2 and P6.3. Software can still read and write the  
associated Px_REG, Px_MODE, and Px_DIR registers. Configure the registers for the  
omitted pins as follows:  
— Clear the corresponding Px_DIR bits. (Configures pins as complementary outputs.)  
— Clear the corresponding Px_MODE bits. (Selects I/O port function.)  
— Write either “0” or “1” to the corresponding Px_REG bits. (Effectively ties signals low  
or high.)  
Do not use the bits associated with the omitted port pins for conditional branch instructions.  
Treat these bits as reserved.  
Auto programming. During auto programming, the 8XC196Lx supports only a 16-bit,  
zero-wait-state bus configuration.  
9-2  
   
10  
Special Operating  
Modes  
CHAPTER 10  
SPECIAL OPERATING MODES  
The 8XC196Lx’s idle and powerdown modes are the same as those of the 8XC196Kx. However,  
the clock circuitry has changed, and the on-circuit emulation (ONCE) special-purpose mode op-  
eration has changed slightly because of the new reset state pin levels that have been implemented.  
10.1 INTERNAL TIMING  
The 87C196LA and LB clock circuitry (Figure 10-1) implements a phase-locked loop and clock  
multiplier circuitry, which can substantially increase the CPU clock rate while using a lower-fre-  
quency input clock.  
10-1  
       
8XC196LX SUPPLEMENT  
Disable  
PLL  
(Powerdown)  
Phase  
Comparator  
Filter  
FXTAL1  
XTAL1  
Phase-locked  
Oscillator  
Phase-locked Loop  
Clock Multiplier  
PLLEN  
XTAL2  
1
0
Disable Oscillator  
(Powerdown)  
f
Disable Clock Input (Powerdown)  
To reset logic  
Divide by two  
Circuit  
f/2  
Disable Clocks (Idle, Powerdown)  
CPU Clocks (PH1, PH2)  
Clock  
Failure  
Detection  
Clock  
Generators  
Peripheral Clocks (PH1, PH2)  
f/2  
Programmable  
Divider  
(CLK1:0)  
OSC  
0
CLKOUT  
1
Disable Clocks (Powerdown)  
A5290-01  
Figure 10-1. Clock Circuitry (87C196LA, LB Only)  
10.2 ENTERING AND EXITING ONCE MODE  
ONCE mode isolates the device from other components in the system to allow printed-circuit-  
board testing or debugging with a clip-on emulator. During ONCE mode, all pins except XTAL1,  
XTAL2, VSS, and VCC are weakly pulled either high or low. During ONCE mode, RESET# must  
be held high or the device will exit ONCE mode and enter the reset state.  
On the 87C196LA and LB, the reset state level of all 41 general-purpose I/O pins has changed  
from a weak logic “1” (wk1) to a weak logic “0” (wk0). ONCE shares a package with port pin  
2.6. Asserting and holding the ONCE signal high during the rising edge of RESET# causes the  
device to enter ONCE mode. To prevent accidental entry into ONCE mode, configure this pin as  
10-2  
       
SPECIAL OPERATING MODES  
an output. If you choose to configure this pin as an input, always hold it low during reset and en-  
sure that your system meets the VIH specification to prevent inadvertent entry into ONCE mode.  
10-3  
11  
Programming the  
Nonvolatile Memory  
CHAPTER 11  
PROGRAMMING THE NONVOLATILE MEMORY  
The 87C196LA and LB microcontrollers contain 24 Kbytes (2000–7FFFH) of one-time-pro-  
grammable read-only memory (OTPROM). OTPROM is similar to EPROM, but it comes in a  
windowless package and cannot be erased. You have the option of programming the OTPROM  
yourself or having the factory program it as a quick-turn ROM product (the latter option may not  
be available for all devices).  
NOTE  
In this supplement, OTPROM refers to the device’s internal read-only  
memory, whether it is EPROM or OTPROM, and EPROM refers specifically  
to EPROM devices.  
The 87C196LA and LB programming signals, registers, and procedures are the same as those of  
the 87C196Kx. This chapter describes the differences in memory mapping and programming cir-  
cuits for the 87C196LA and LB.  
11.1 SIGNATURE WORD AND PROGRAMMING VOLTAGE VALUES  
The 8XC196Lx’s programming voltage values are the same as those of the 8XC196Kx; however,  
the signature word value differs. Table 11-1 lists the signature word and programming voltage  
values.  
Table 11-1. Signature Word and Programming Voltage Values  
Signature Word  
Location Value  
Programming VCC Programming VPP  
Device  
Location  
Value Location Value  
87C196LA  
87C196LB  
0070H  
0070H  
871BH  
871BH  
0072H  
0072H  
40H  
40H  
0073H  
0073H  
0A0H  
0A0H  
11.2 OTPROM ADDRESS MAP  
The OTPROM contains customer-specified special-purpose and program memory (Table 11-2).  
The 128-byte special-purpose address partition is used for interrupt vectors, the chip configura-  
tion bytes (CCBs), and the security key. Several locations are reserved for testing or for use in  
future products. Write the value (20H or FFH) indicated in Table 11-2 to each reserved location.  
The remainder of the OTPROM is available for code storage.  
11-1  
               
8XC196LX SUPPLEMENT  
Table 11-2. 87C196LA, LB OTPROM Address Map  
Address Range  
(Hex)  
Description  
7FFF  
2080  
Program memory  
207F  
205E  
Reserved (each location must contain FFH)  
PTS vectors  
205D  
2040  
203F  
2030  
Upper interrupt vectors  
202F  
2020  
Security key  
201F  
201C  
Reserved (each location must contain FFH)  
201B  
201A  
2019  
2018  
Reserved (must contain 20H)  
CCB1  
Reserved (must contain 20H)  
CCB0  
2017  
2016  
OFD flag for QROM or MROM codes  
2015  
2014  
Reserved (each location must contain FFH)  
Lower interrupt vectors  
2013  
2000  
Intel manufacturing uses this location to determine whether to program the OFD bit.  
Customers with quick-ROM (QROM) or masked-ROM (MROM) codes who desire oscillator  
failure detection should equate this location to the value 0CDEH.  
11.3 SLAVE PROGRAMMING CIRCUIT AND ADDRESS MAP  
Figure 11-1 shows the circuit diagram and Table 11-3 details the address map for slave program-  
ming of the 87C196LA and LB devices.  
11-2  
     
PROGRAMMING THE NONVOLATILE MEMORY  
CLOCK  
VCC  
XTAL1  
VCC  
VCC  
VSS  
RESET#  
RESET#  
PBUS  
0.1 µF  
10kΩ  
P4.7:0  
P3.7:0  
Pullups Required  
P4.7 - P3.0  
EA#  
VPP  
EA#  
VPP  
P2.6  
P2.4  
P2.2  
P2.1  
P2.0  
CPVER  
AINC#  
PROG#  
PALE#  
PVER  
VCC  
VREF  
P0.7/PMODE.3  
P0.6/PMODE.2  
P0.5/PMODE.1  
P0.4/PMODE.0  
ANGND  
87C196LA, LB  
A5277-01  
Figure 11-1. Slave Programming Circuit  
Table 11-3. Slave Programming Mode Address Map  
Description  
Address  
Comments  
OTPROM  
2000–7FFFH OTPROM Cells  
0778H OTPROM Cell  
0758H UPROM Cell  
0718H UPROM Cell  
0218H Test EPROM  
0072H Read Only  
OFD  
DED  
DEI  
PCCB  
Programming VCC  
Programming VPP  
0073H Read Only  
Signature word  
0070H Read Only  
These bits program the UPROM cells. Once these bits are programmed, they cannot be erased, and  
dynamic failure analysis of the device is impossible.  
11-3  
       
8XC196LX SUPPLEMENT  
11.4 SERIAL PORT PROGRAMMING CIRCUIT AND ADDRESS MAP  
Figure 11-2 shows the circuit and Table 11-4 details the address map for serial port programming.  
30 pF  
30 pF  
XTAL1  
VREF  
XTAL2  
VCC  
RESET#  
10 µF  
P0.7/PMODE.3  
P0.6/PMODE.2  
P0.5/PMODE.1  
P0.4/PMODE.0  
ANGND  
VCC  
VPP  
VCC  
EA#  
VPP  
P2.1/RXD  
P2.0/TXD  
A
B C  
0.01 µF  
87C196LA, LB  
RXD  
TXD  
VCC  
5
9
4
8
3
7
2
6
1
2N2222A  
1.8kΩ  
1N914  
RXD  
TXD  
1.8kΩ  
2N2907  
1.8kΩ  
1.8kΩ  
1.8kΩ  
1N914  
10µF  
A5278-01  
Figure 11-2. Serial Port Programming Circuit  
11-4  
     
PROGRAMMING THE NONVOLATILE MEMORY  
Table 11-4. Serial Port Programming Mode Address Map  
Address Range  
Description  
Normal Operation  
Serial Port Programming Mode  
Internal OTPROM  
2000–7FFFH  
A000–FFFFH  
4000–9FFFH  
2400–3FFFH  
2000–23FFH  
External memory  
Do not address  
Test ROM and RISM  
11-5  
   
A
Signal Descriptions  
APPENDIX A  
SIGNAL DESCRIPTIONS  
This appendix provides reference information for the pin functions of the 8XC196Lx microcon-  
trollers.  
A.1 FUNCTIONAL GROUPINGS OF SIGNALS  
Tables A-1, A-2, and A-3 list the signal assignments for the 8XC196Lx microcontrollers, grouped  
by function. A diagram of each microcontroller shows the pin location of each signal.  
A-1  
     
8XC196LX SUPPLEMENT  
Table A-1. 87C196LA Signals Arranged by Functional Categories  
Addr & Data  
Input/Output (Cont’d)  
Name Pin  
P2.1 / RXD  
Program Control  
Name  
AINC#  
Processor Control  
Name  
Pin  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
10  
9
Pin  
30  
31  
32  
28  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
10  
9
Name  
EA#  
Pin  
24  
29  
6
AD0  
28  
29  
30  
31  
32  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
10  
9
AD1  
P2.2  
P2.4  
P2.6  
P2.7  
P3.0  
P3.1  
P3.2  
P3.3  
P3.4  
P3.5  
P3.6  
P3.7  
P4.0  
P4.1  
P4.2  
P4.3  
P4.4  
P4.5  
P4.6  
P4.7  
P5.0  
P5.2  
P5.3  
CPVER  
PACT#  
EXTINT  
PLLEN  
RESET#  
XTAL1  
AD2  
AD3  
PALE#  
23  
52  
51  
AD4  
PBUS.0  
PBUS.1  
PBUS.2  
PBUS.3  
PBUS.4  
PBUS.5  
PBUS.6  
PBUS.7  
PBUS.8  
PBUS.9  
PBUS.10  
PBUS.11  
PBUS.12  
PBUS.13  
PBUS.14  
PBUS.15  
PMODE.0  
PMODE.1  
PMODE.2  
PMODE.3  
PROG#  
PVER  
AD5  
XTAL2  
AD6  
AD7  
Bus Cont & Status  
AD8  
Name  
ADV# / ALE  
CLKOUT  
RD#  
Pin  
2
AD9  
AD10  
AD11  
AD12  
AD13  
AD14  
AD15  
32  
5
WR# / WRL#  
6
8
Power & Ground  
7
Name  
ANGND  
VCC  
Pin  
39  
26  
4
Input/Output  
Name  
Pin  
33  
34  
35  
36  
37  
38  
8
V
PP  
P0.2 / ACH2  
P0.3 / ACH3  
P0.4 / ACH4  
P0.5 / ACH5  
P0.6 / ACH6  
P0.7 / ACH7  
8
7
VREF  
VSS  
40  
3
7
35  
36  
37  
38  
29  
27  
2
VSS1  
VSS1  
1
6
25  
5
P6.0 / EPA8 / COMP0 45  
P6.1 / EPA9 / COMP1 46  
P1.0 / EPA0 / T2CLK 44  
P1.1 / EPA1  
43  
42  
41  
27  
P6.4 / SC0  
P6.5 / SD0  
P6.6 / SC1  
P6.7 / SD1  
47  
48  
49  
50  
P1.2 / EPA2 / T2DIR  
P1.3 / EPA3  
P2.0 / TXD  
A-2  
   
SIGNAL DESCRIPTIONS  
AD14 / P4.6 / PBUS.14  
AD13 / P4.5 / PBUS.13  
AD12 / P4.4 / PBUS.12  
AD11 / P4.3 / PBUS.11  
AD10 / P4.2 / PBUS.10  
AD9 / P4.1 / PBUS.9  
AD8 / P4.0 / PBUS.8  
AD7 / P3.7 / PBUS.7  
AD6 / P3.6 / PBUS.6  
AD5 / P3.5 / PBUS.5  
AD4 / P3.4 / PBUS.4  
AD3 / P3.3 / PBUS.3  
AD2 / P3.2 / PBUS.2  
8
9
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
P6.1 / EPA9 / COMP1  
P6.0 / EPA8 / COMP0  
P1.0 / EPA0 / T2CLK  
P1.1 / EPA1  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
xx87C196LA20  
P1.2 / EPA2 / T2DIR  
P1.3 / EPA3  
V
REF  
ANGND  
View of component as  
mounted on PC board  
P0.7 / ACH7 / PMODE.3  
P0.6 / ACH6 / PMODE.2  
P0.5 / ACH5 / PMODE.1  
P0.4 / ACH4 / PMODE.0  
P0.3 / ACH3  
A3419-03  
Figure A-1. 87C196LA 52-pin PLCC Package  
A-3  
 
8XC196LX SUPPLEMENT  
Table A-2. 87C196LB Signals Arranged by Functional Categories  
Addr & Data  
Input/Output (Cont’d)  
Name Pin  
P2.1 / RXD  
Program Control  
Name  
AINC#  
Processor Control  
Name  
Pin  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
10  
9
Pin  
30  
31  
32  
28  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
10  
9
Name  
EA#  
Pin  
24  
29  
6
AD0  
28  
29  
30  
31  
32  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
10  
9
AD1  
P2.2  
CPVER  
PACT#  
EXTINT  
PLLEN  
RESET#  
XTAL1  
AD2  
P2.4 / RXJ1850  
P2.6 / TXJ1850  
P2.7  
AD3  
PALE#  
23  
52  
51  
AD4  
PBUS.0  
PBUS.1  
PBUS.2  
PBUS.3  
PBUS.4  
PBUS.5  
PBUS.6  
PBUS.7  
PBUS.8  
PBUS.9  
PBUS.10  
PBUS.11  
PBUS.12  
PBUS.13  
PBUS.14  
PBUS.15  
PMODE.0  
PMODE.1  
PMODE.2  
PMODE.3  
PROG#  
PVER  
AD5  
P3.0  
XTAL2  
AD6  
P3.1  
AD7  
P3.2  
Bus Cont & Status  
AD8  
P3.3  
Name  
ADV# / ALE  
CLKOUT  
RD#  
Pin  
2
AD9  
P3.4  
AD10  
AD11  
AD12  
AD13  
AD14  
AD15  
P3.5  
32  
5
P3.6  
P3.7  
WR# / WRL#  
6
P4.0  
8
P4.1  
Power & Ground  
7
P4.2  
Name  
ANGND  
VCC  
Pin  
39  
26  
4
P4.3  
Input/Output  
Name  
P4.4  
Pin  
33  
34  
35  
36  
37  
38  
P4.5  
8
V
PP  
P0.2 / ACH2  
P0.3 / ACH3  
P0.4 / ACH4  
P0.5 / ACH5  
P0.6 / ACH6  
P0.7 / ACH7  
P4.6  
8
7
VREF  
VSS  
40  
3
P4.7  
7
35  
36  
37  
38  
29  
27  
P5.0  
2
VSS1  
VSS1  
1
P5.2  
6
25  
P5.3  
5
P6.0 / EPA8 / COMP0 45  
P6.1 / EPA9 / COMP1 46  
P1.0 / EPA0 / T2CLK 44  
P1.1 / EPA1  
43  
42  
41  
27  
P6.4 / SC0  
P6.5 / SD0  
P6.6 / SC1  
P6.7 / SD1  
47  
48  
49  
50  
P1.2 / EPA2 / T2DIR  
P1.3 / EPA3  
P2.0 / TXD  
A-4  
   
SIGNAL DESCRIPTIONS  
AD14 / P4.6 / PBUS.14  
AD13 / P4.5 / PBUS.13  
AD12 / P4.4 / PBUS.12  
AD11 / P4.3 / PBUS.11  
AD10 / P4.2 / PBUS.10  
AD9 / P4.1 / PBUS.9  
AD8 / P4.0 / PBUS.8  
AD7 / P3.7 / PBUS.7  
AD6 / P3.6 / PBUS.6  
AD5 / P3.5 / PBUS.5  
AD4 / P3.4 / PBUS.4  
AD3 / P3.3 / PBUS.3  
AD2 / P3.2 / PBUS.2  
8
9
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
P6.1 / EPA9 / COMP1  
P6.0 / EPA8 / COMP0  
P1.0 / EPA0 / T2CLK  
P1.1 / EPA1  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
xx87C196LB20  
P1.2 / EPA2 / T2DIR  
P1.3 / EPA3  
V
REF  
ANGND  
View of component as  
mounted on PC board  
P0.7 / ACH7 / PMODE.3  
P0.6 / ACH6 / PMODE.2  
P0.5 / ACH5 / PMODE.1  
P0.4 / ACH4 / PMODE.0  
P0.3 / ACH3  
A3361-03  
Figure A-2. 87C196LB 52-pin PLCC Package  
A-5  
 
8XC196LX SUPPLEMENT  
Table A-3. 83C196LD Signals Arranged by Functional Categories  
Addr & Data  
Name Pin  
AD0  
Input/Output  
Input/Output (Cont’d)  
Name Pin  
Processor Control  
Name Pin  
CLKOUT  
Name  
P1.0/EPA0/T2CLK  
P1.1/EPA1  
P1.2/EPA2/T2DIR  
P1.3/EPA3  
P2.0/TXD  
P2.1/RXD  
P2.2  
Pin  
44  
43  
42  
41  
27  
28  
29  
30  
31  
32  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
10  
9
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
10  
9
P4.7  
P5.0  
P5.2  
P5.3  
7
2
32  
24  
29  
31  
23  
52  
51  
AD1  
EA#  
AD2  
6
EXTINT  
ONCE#  
RESET#  
XTAL1  
XTAL2  
AD3  
5
AD4  
P6.0/EPA8  
P6.1/EPA9  
P6.4/SC0  
P6.5/SD0  
P6.6/SC1  
P6.7/SD1  
45  
46  
47  
48  
49  
50  
AD5  
AD6  
AD7  
P2.4  
AD8  
P2.6  
Bus Control & Status  
AD9  
P2.7  
Name  
ADV#/ALE  
RD#  
Pin  
2
AD10  
AD11  
AD12  
AD13  
AD14  
AD15  
P3.0  
P3.1  
Power & Ground  
Name  
5
P3.2  
Pin  
26  
40  
4
WR#/WRL#  
6
P3.3  
VCC  
VCC  
VPP  
VSS  
VSS  
VSS  
VSS  
8
P3.4  
7
P3.5  
P3.6  
1
Input  
Name  
P3.7  
3
Pin  
33  
34  
35  
36  
37  
38  
P4.0  
25  
39  
P0.2  
P0.3  
P0.4  
P0.5  
P0.6  
P0.7  
P4.1  
P4.2  
P4.3  
P4.4  
P4.5  
P4.6  
8
A-6  
   
SIGNAL DESCRIPTIONS  
AD14 / P4.6  
AD13 / P4.5  
AD12 / P4.4  
AD11 / P4.3  
AD10 / P4.2  
AD9 / P4.1  
AD8 / P4.0  
AD7 / P3.7  
AD6 / P3.6  
AD5 / P3.5  
AD4 / P3.4  
AD3 / P3.3  
AD2 / P3.2  
8
9
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
P6.1 / EPA9  
P6.0 / EPA8  
P1.0 / EPA0 / T2CLK  
P1.1 / EPA1  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
xx83C196LD  
P1.2 / EPA2 / T2DIR  
P1.3 / EPA3  
V
CC  
V
SS  
View of component as  
mounted on PC board  
P0.7  
P0.6  
P0.5  
P0.4  
P0.3  
A3403-02  
Figure A-3. 83C196LD 52-pin PLCC Package  
A.2 DEFAULT CONDITIONS  
Table A-5 lists the values of the signals for the 87C196LA and 87C196LB during various oper-  
ating conditions. Table A-6 lists the same information for the 83C196LD. Table A-4 defines the  
symbols used to represent the pin status. Refer to the DC characteristics table in the datasheet for  
actual specifications for VOL, VIL, VOH, and VIH.  
Table A-4. Definition of Status Symbols  
Symbol  
Definition  
Symbol  
MD0  
Definition  
Medium pull-down  
0
Voltage less than or equal to VOL, VIL  
Voltage greater than or equal to VOH, VIH  
High impedance  
1
MD1  
WK0  
WK1  
ODIO  
Medium pull-up  
Weak pull-down  
Weak pull-up  
HiZ  
LoZ0  
LoZ1  
Low impedance; strongly driven low  
Low impedance; strongly driven high  
Open-drain I/O  
A-7  
       
8XC196LX SUPPLEMENT  
Table A-5. 87C196LA, LB Default Signal Conditions  
Upon RESET#  
Inactive  
Port  
Signals  
Alternate  
Functions  
During RESET#  
Active  
Power-  
down  
Idle  
(Note 6)  
P0.7:2  
P1.0  
P1.1  
P1.2  
P1.3  
P2.0  
P2.1  
P2.2  
P2.4  
P2.6  
P2.7  
ACH7:2  
HiZ  
HiZ  
HiZ  
EPA0/T2CLK  
EPA1  
WK0  
WK0  
WK0  
WK0  
WK0  
WK0  
WK0  
WK0  
MD0  
WK0  
WK0  
WK0  
WK0  
WK0  
WK0  
WK0  
WK0  
MD0  
(Note 1)  
(Note 1)  
(Note 1)  
(Note 1)  
(Note 1)  
(Note 1)  
(Note 1)  
(Note 1)  
(Note 1)  
(Note 1)  
(Note 1)  
EPA2/T2DIR  
EPA3  
TXD  
RXD  
EXTINT  
RXJ1850 (LB only)  
ONCE/TXJ1850 (LB only)  
CLKOUT  
CLKOUT active, CLKOUT active,  
LoZ0/1  
LoZ0/1  
P3.7:0  
P4.7:0  
P5.0  
P5.2  
P5.3  
P6.0  
P6.1  
P6.4  
P6.5  
P6.6  
P6.7  
AD7:0  
WK0  
HiZ  
(Note 4)  
(Note 4)  
(Note 1)  
(Note 1)  
(Note 1)  
(Note 1)  
(Note 1)  
(Note 1)  
(Note 1)  
(Note 1)  
(Note 1)  
WK1  
(Note 1)  
(Note 1)  
(Note 1)  
(Note 1)  
(Note 1)  
(Note 1)  
WK1  
AD15:8  
ALE/ADV#  
WR#/WRL#  
RD#  
WK0  
HiZ  
WK0  
WK0  
WK0  
WK0  
WK0  
WK0  
WK0  
WK0  
WK0  
WK1  
MD1  
HiZ  
WK0  
WK0  
EPA8/COMP0  
EPA9/COMP1  
SC0  
WK0  
WK0  
WK0  
SD0  
WK0  
SC1  
WK0  
SD1  
WK0  
EA#  
WK1 (Note 5)  
LoZ0  
RESET#  
VPP  
MD1  
MD1  
HiZ  
LoZ1  
LoZ1  
XTAL1  
Osc input,  
HiZ  
Osc input,  
HiZ  
Osc input, HiZ  
Osc input, HiZ  
XTAL2  
Osc output,  
LoZ0/1  
Osc output,  
LoZ0/1  
Osc output,  
LoZ0/1  
(Note 3)  
NOTES:  
1. If Px_MODE.y = 0, port is as programmed.  
If Px_MODE.y = 1, pin is as specified by Px_DIR and the associated peripheral.  
2. If P2_MODE.7 = 0, pin is as programmed. If P2_MODE.7 = 1, pin is LoZ0.  
3. If XTAL1 = 0, pin is LoZ1. If XTAL1 = 1, pin is LoZ0.  
4. If EA# = 0, port is HiZ. If EA# = 1, port is open-drain I/O.  
5. Although EA# is weakly pulled high, do not allow it to float. Always tie EA# to VCC if it is not connected  
to an external device.  
6. The values in this column are valid until your software writes to Px_MODE.  
A-8  
                                       
SIGNAL DESCRIPTIONS  
Table A-6. 83C196LD Default Signal Conditions  
Upon RESET#  
Inactive  
Port  
Signals  
Alternate  
Functions  
During RESET#  
Active  
Power-  
down  
Idle  
(Note 6)  
P0.7:2  
P1.0  
P1.1  
P1.2  
P1.3  
P2.0  
P2.1  
P2.2  
P2.4  
P2.6  
P2.7  
HiZ  
HiZ  
HiZ  
EPA0/T2CLK  
EPA1  
WK1  
WK1  
WK1  
WK1  
WK1  
WK1  
WK1  
WK1  
MD1  
WK1  
WK1  
WK1  
WK1  
WK1  
WK1  
WK1  
WK1  
MD1  
(Note 1)  
(Note 1)  
(Note 1)  
(Note 1)  
(Note 1)  
(Note 1)  
(Note 1)  
(Note 1)  
(Note 1)  
(Note 1)  
(Note 1)  
EPA2/T2DIR  
EPA3  
TXD  
RXD  
EXTINT  
ONCE  
CLKOUT  
CLKOUT active, CLKOUT active,  
LoZ0/1  
LoZ0/1  
P3.7:0  
P4.7:0  
P5.0  
P5.2  
P5.3  
P6.0  
P6.1  
P6.4  
P6.5  
P6.6  
P6.7  
AD7:0  
AD15:8  
ALE/ADV#  
WR#/WRL#  
RD#  
WK1  
HiZ  
(Note 4)  
(Note 4)  
(Note 1)  
(Note 1)  
(Note 1)  
(Note 1)  
(Note 1)  
(Note 1)  
(Note 1)  
(Note 1)  
(Note 1)  
WK1  
(Note 1)  
(Note 1)  
(Note 1)  
(Note 1)  
(Note 1)  
(Note 1)  
WK1  
WK1  
HiZ  
WK1  
WK1  
WK1  
WK1  
WK1  
WK1  
WK1  
WK1  
WK1  
WK1  
MD1  
HiZ  
WK1  
WK1  
EPA8  
WK1  
EPA9  
WK1  
SC0  
WK1  
SD0  
WK1  
SC1  
WK1  
SD1  
WK1  
EA#  
WK1 (Note 5)  
LoZ0  
RESET#  
VPP  
MD1  
MD1  
HiZ  
LoZ1  
LoZ1  
XTAL1  
Osc input,  
HiZ  
Osc input,  
HiZ  
Osc input, HiZ  
Osc input, HiZ  
XTAL2  
Osc output,  
LoZ0/1  
Osc output,  
LoZ0/1  
Osc output,  
LoZ0/1  
(Note 3)  
NOTES:  
1. If Px_MODE.y = 0, port is as programmed.  
If Px_MODE.y = 1, pin is as specified by Px_DIR and the associated peripheral.  
2. If P2_MODE.7 = 0, pin is as programmed. If P2_MODE.7 = 1, pin is LoZ0.  
3. If XTAL1 = 0, pin is LoZ1. If XTAL1 = 1, pin is LoZ0.  
4. If EA# = 0, port is HiZ. If EA# = 1, port is open-drain I/O.  
5. Although EA# is weakly pulled high, do not allow it to float. Always tie EA# to VCC if it is not connected  
to an external device.  
6. The values in this column are valid until your software writes to Px_MODE.  
A-9  
                                       
Glossary  
GLOSSARY  
This glossary defines acronyms, abbreviations, and terms that have special meaning in this man-  
ual. (Chapter 1 discusses notational conventions and general terminology.)  
absolute error  
The maximum difference between corresponding  
actual and ideal code transitions. Absolute error  
accounts for all deviations of an actual A/D converter  
from an ideal converter.  
accumulator  
A register or storage location that forms the result of  
an arithmetic or logical operation.  
actual characteristic  
A graph of output code versus input voltage of an  
actual A/D converter. An actual characteristic may  
vary with temperature, supply voltage, and frequency  
conditions.  
A/D converter  
ALU  
Analog-to-digital converter. An internal peripheral  
that converts an analog input to a digital value.  
Arithmetic-logic unit. The part of the RALU that  
processes arithmetic and logical operations.  
assert  
The act of making a signal active (enabled). The  
polarity (high or low) is defined by the signal name.  
Active-low signals are designated by a pound symbol  
(#) suffix; active-high signals have no suffix. To  
assert RD# is to drive it low; to assert ALE is to drive  
it high.  
attenuation  
bit  
A decrease in amplitude; voltage decay.  
A binary digit.  
BIT  
A single-bit operand that can take on the Boolean  
values, “true” and “false.”  
bit arbitration  
The process of settling conflicts that occur when  
multiple nodes attempt to transmit a bit or symbol  
across a single bus at the same time.  
break-before-make  
The property of a multiplexer which guarantees that a  
previously selected channel is deselected before a  
new channel is selected. (That is, break-before-make  
ensures that the A/D converter will not short inputs  
together.)  
Glossary-1  
 
8XC196LX SUPPLEMENT  
byte  
Any 8-bit unit of data.  
BYTE  
An unsigned, 8-bit variable with values from 0  
through 28–1.  
CCBs  
CCRs  
Chip configuration bytes. The chip configuration  
registers (CCRs) are loaded with the contents of the  
CCBs after a reset.  
Chip configuration registers. Registers that define the  
environment in which the microcontroller will be  
operating. The chip configuration registers are loaded  
with the contents of the CCBs after a reset.  
channel-to-channel matching error  
The difference between corresponding code  
transitions of actual characteristics taken from  
different A/D converter channels under the same  
temperature, voltage, and frequency conditions. This  
error is caused by differences in DC input leakage and  
on-channel resistance from one multiplexer channel  
to another.  
characteristic  
chip-select unit  
clear  
A graph of output code versus input voltage; the  
transfer function of an A/D converter.  
The integrated module that selects an external  
memory device during an external bus cycle.  
The “0” value of a bit or the act of giving it a “0”  
value. See also set.  
code  
1) A set of instructions that perform a specific  
function; a program.  
2) The digital value output by the A/D converter.  
code center  
The voltage corresponding to the midpoint between  
two adjacent code transitions on the A/D converter.  
code transition  
The point at which the A/D converter’s output code  
changes from “Q” to “Q+1.” The input voltage corre-  
sponding to a code transition is defined as the voltage  
that is equally likely to produce either of two adjacent  
codes.  
code width  
The voltage change corresponding to the difference  
between two adjacent code transitions. Code width  
deviations cause differential nonlinearity and nonlin-  
earity errors.  
Glossary-2  
GLOSSARY  
contention  
The detection of conflicting symbols or bits on the  
bus.  
crosstalk  
See off-isolation.  
DC input leakage  
Leakage current from an analog input pin to ground or  
to the reference voltage (VREF).  
deassert  
The act of making a signal inactive (disabled). The  
polarity (high or low) is defined by the signal name.  
Active-low signals are designated by a pound symbol  
(#) suffix; active-high signals have no suffix. To  
deassert RD# is to drive it high; to deassert ALE is to  
drive it low.  
demultiplexed bus  
The configuration in which the microcontroller uses  
separate lines for address and data (address on A20:0;  
data on AD15:0 for a 16-bit bus or AD7:0 for an 8-bit  
bus). See also multiplexed bus.  
differential nonlinearity  
The difference between the actual code width and the  
ideal one-LSB code width of the terminal-based  
characteristic of an A/D converter. It provides a  
measure of how much the input voltage may have  
changed in order to produce a one-count change in the  
conversion result. Differential nonlinearity is a  
measure of local code-width error; nonlinearity is a  
measure of overall code-transition error.  
doping  
The process of introducing a periodic table Group III  
or Group V element into a Group IV element (e.g.,  
silicon). A Group III impurity (e.g., indium or  
gallium) results in a p-type material. A Group V  
impurity (e.g., arsenic or antimony) results in an n-  
type material.  
double-word  
Any 32-bit unit of data.  
DOUBLE-WORD  
An unsigned, 32-bit variable with values from 0  
through 232–1.  
EPA  
ESD  
Event processor array. An integrated peripheral that  
provides high-speed input/output capability.  
Electrostatic discharge.  
Glossary-3  
8XC196LX SUPPLEMENT  
external address  
A 21-bit address is presented on the microcontroller’s  
pins. The address decoded by an external device  
depends on how many of these address pins the  
external system uses. See also internal address.  
f
Lowercase “f” represents the frequency of the internal  
clock.  
far constants  
far data  
feedthrough  
Constants that can be accessed only with extended  
instructions. See also near constants.  
Data that can be accessed only with extended instruc-  
tions. See also near data.  
The attenuation from an input voltage on the selected  
channel to the A/D output after the sample window  
closes. The ability of the A/D converter to reject an  
input on its selected channel after the sample window  
closes.  
FET  
Field-effect transistor.  
full-scale error  
The difference between the ideal and actual input  
voltage corresponding to the final (full-scale) code  
transition of an A/D converter.  
hold latency  
The time it takes the microcontroller to assert HLDA#  
after an external device asserts HOLD#.  
ideal characteristic  
The characteristic of an ideal A/D converter. An ideal  
characteristic is unique: its first code transition occurs  
when the input voltage is 0.5 LSB, its full-scale (final)  
code transition occurs when the input voltage is 1.5  
LSB less than the full-scale reference, and its code  
widths are all exactly 1.0 LSB. These properties result  
in a conversion without zero-offset, full-scale, or  
linearity errors. Quantizing error is the only error  
seen in an ideal A/D converter.  
input leakage  
Current leakage from an input pin to power or ground.  
input series resistance  
The effective series resistance from an analog input  
pin to the sample capacitor of an A/D converter.  
integer  
Any member of the set consisting of the positive and  
negative whole numbers and zero.  
INTEGER  
A 16-bit, signed variable with values from –215  
through +215–1.  
Glossary-4  
GLOSSARY  
internal address  
The 24-bit address that the microcontroller generates.  
See also external address.  
interrupt controller  
The module responsible for handling interrupts that  
are to be serviced by interrupt service routines that  
you provide. Also called the programmable interrupt  
controller (PIC).  
interrupt latency  
The total delay between the time that an interrupt is  
generated (not acknowledged) and the time that the  
microcontroller begins executing the interrupt service  
routine or PTS routine. Determine the instruction in  
your code that has the longest execution time and use  
that execution time in calculating interrupt latency.  
interrupt service routine  
interrupt vector  
J1850  
A software routine that you provide to service a  
standard interrupt request.  
A location in special-purpose memory that holds the  
starting address of an interrupt service routine.  
An integrated communications controller peripheral  
that supports the 10.4 Kb/s variable pulse-width  
(VPW) medium-speed, class B, in-vehicle network  
protocol.  
ISR  
See interrupt service routine.  
linearity errors  
LONG-INTEGER  
See differential nonlinearity and nonlinearity.  
A 32-bit, signed variable with values from –231  
through +231–1.  
LSB  
1) Least-significant bit of a byte or least-significant  
byte of a word.  
2) In an A/D converter, the reference voltage divided  
by 2n, where n is the number of bits to be converted.  
For a 10-bit converter with a reference voltage of 5.12  
volts, one LSB is equal to 5.0 millivolts (5.12 ÷ 210).  
LSW  
Least-significant word of a double-word or quad-  
word.  
Glossary-5  
8XC196LX SUPPLEMENT  
maskable interrupts  
All interrupts except stack overflow, unimplemented  
opcode, and software trap. Maskable interrupts can be  
disabled (masked) by the individual mask bits in the  
interrupt mask registers, and their servicing can be  
disabled by the DI (disable interrupt service)  
instruction. Each maskable interrupt can be assigned  
to the PTS for processing.  
monotonic  
The property of successive approximation converters  
which guarantees that increasing input voltages  
produce adjacent codes of increasing value, and that  
decreasing input voltages produce adjacent codes of  
decreasing value. (In other words, a converter is  
monotonic if every code change represents an input  
voltage change in the same direction.) Large differ-  
ential nonlinearity errors can cause the converter to  
exhibit nonmonotonic behavior.  
MSB  
Most-significant bit of a byte or most-significant byte  
of a word.  
MSW  
Most-significant word of a double-word or quad-  
word.  
multiplexed bus  
The configuration in which the microcontroller uses  
both A20:0 and AD15:0 for address and also uses  
AD15:0 for data. See also demultiplexed bus.  
n-channel FET  
A field-effect transistor with an n-type conducting  
path (channel).  
n-type material  
Semiconductor material with introduced impurities  
(doping) causing it to have an excess of negatively  
charged carriers.  
near constants  
Constants that can be accessed with nonextended  
instructions. Constants in page 00H are near  
constants. See also far constants.  
near data  
Data that can be accessed with nonextended instruc-  
tions. Data in page 00H is near data. See also far data.  
no missing codes  
An A/D converter has no missing codes if, for every  
output code, there is a unique input voltage range  
which produces that code only. Large differential  
nonlinearity errors can cause the converter to miss  
codes.  
Glossary-6  
GLOSSARY  
nonlinearity  
The maximum deviation of code transitions of the  
terminal-based characteristic from the corre-  
sponding code transitions of the ideal characteristic.  
nonmaskable interrupts  
Interrupts that cannot be masked (disabled) and  
cannot be assigned to the PTS for processing. The  
nonmaskable interrupts are stack overflow, unimple-  
mented opcode, software trap, and NMI. The DI  
(disable interrupt service) and EI (enable interrupt  
service) instructions have no effect on nonmaskable  
interrupts.  
npn transistor  
off-isolation  
A transistor consisting of one part p-type material and  
two parts n-type material.  
The ability of an A/D converter to reject (isolate) the  
signal on a deselected (off) output.  
p-channel FET  
p-type material  
A field-effect transistor with a p-type conducting  
path.  
Semiconductor material with introduced impurities  
(doping) causing it to have an excess of positively  
charged carriers.  
PC  
Program counter.  
phase-locked loop  
A component of the clock generation circuitry. The  
phase-locked loop (PLL) and the input pin (PLLEN)  
combine to enable the microcontroller to attain its  
maximum operating frequency with an external clock  
whose frequency is either equal to or one-half that  
maximum frequency or with an external oscillator  
whose frequency is one-half that maximum  
frequency.  
PIC  
Programmable interrupt controller. The module  
responsible for handling interrupts that are to be  
serviced by interrupt service routines that you  
provide. Also called simply the interrupt controller.  
PIH  
PLL  
Peripheral interrupt handler. An integrated module  
that provides interrupt vectors for specific EPA  
interrupt requests to the interrupt controller or PTS.  
See phase-locked loop.  
Glossary-7  
8XC196LX SUPPLEMENT  
prioritized interrupt  
NMI, stack overflow, or any maskable interrupt. Two  
of the nonmaskable interrupts (unimplemented  
opcode and software trap) are not prioritized; they  
vector directly to the interrupt service routine when  
executed.  
program memory  
A partition of memory where instructions can be  
stored for fetching and execution.  
protected instruction  
An instruction that prevents an interrupt from being  
acknowledged until after the next instruction  
executes. The protected instructions are DI, EI,  
DPTS, EPTS, POPA, POPF, PUSHA, and PUSHF.  
PSW  
Processor status word. The high byte of the PSW is  
the status byte, which contains one bit that globally  
enables or disables servicing of all maskable  
interrupts, one bit that enables or disables the PTS,  
and six Boolean flags that reflect the state of the  
current program. The low byte of the PSW is the  
INT_MASK register. A PUSHA or POPA instruction  
saves or restores both bytes (PSW + INT_MASK); a  
PUSHF or POPF saves or restores only the PSW.  
PTS  
Peripheral transaction server. The microcoded  
hardware interrupt processor.  
PTSCB  
See PTS control block.  
PTS control block  
A block of data required for each PTS interrupt. The  
microcode executes the proper PTS routine based on  
the contents of the PTS control block.  
PTS cycle  
The microcoded response to a single PTS interrupt  
request.  
PTS interrupt  
PTS mode  
Any maskable interrupt that is assigned to the PTS for  
interrupt processing.  
A microcoded response that enables the PTS to  
complete a specific task quickly.  
PTS routine  
The entire microcoded response to multiple PTS  
interrupt requests. The PTS routine is controlled by  
the contents of the PTS control block.  
PTS transfer  
The movement of a single byte or word from the  
source memory location to the destination memory  
location.  
Glossary-8  
GLOSSARY  
PTS vector  
A location in special-purpose memory that holds the  
starting address of a PTS control block.  
QUAD-WORD  
An unsigned, 64-bit variable with values from 0  
through 264–1. The QUAD-WORD variable is  
supported only as the operand for the EBMOVI  
instruction.  
quantizing error  
An unavoidable A/D conversion error that results  
simply from the conversion of a continuous voltage to  
its integer digital representation. Quantizing error is  
always ± 0.5 LSB and is the only error present in an  
ideal A/D converter.  
RALU  
Register arithmetic-logic unit. A part of the CPU that  
consists of the ALU, the PSW, the master PC, the  
microcode engine, a loop counter, and six registers.  
repeatability error  
The variation in code transitions when comparing a  
number of actual characteristics from the same  
converter on the same channel with the same temper-  
ature, voltage, and frequency conditions. The amount  
of repeatability error depends on the comparator’s  
ability to resolve very similar voltages and the extent  
to which random noise contributes to the error.  
reserved memory  
resolution  
A memory location that is reserved for factory use or  
for future expansion. Do not use a reserved memory  
location except to initialize it.  
The number of input voltage levels that an A/D  
converter can unambiguously distinguish between.  
The number of useful bits of information that the  
converter can return.  
sample capacitor  
sample delay  
A small (2–3 pF) capacitor used in the A/D converter  
circuitry to store the input voltage on the selected  
input channel.  
The time period between the time that A/D converter  
receives the “start conversion” signal and the time  
that the sample capacitor is connected to the selected  
channel.  
sample delay uncertainty  
sample time  
The variation in the sample delay.  
The period of time that the sample window is open.  
(That is, the length of time that the input channel is  
actually connected to the sample capacitor.)  
Glossary-9  
8XC196LX SUPPLEMENT  
sample time uncertainty  
sample window  
The variation in the sample time.  
The period of time that begins when the sample  
capacitor is attached to a selected channel of an A/D  
converter and ends when the sample capacitor is  
disconnected from the selected channel.  
sampled inputs  
All input pins, with the exception of RESET#, are  
sampled inputs. The input pin is sampled one state  
time before the read buffer is enabled. Sampling  
occurs during PH1 (while CLKOUT is low) and  
resolves the value (high or low) of the pin before it is  
presented to the internal bus. If the pin value changes  
during the sample time, the new value may or may not  
be recorded during the read.  
RESET# is a level-sensitive input. EXTINT is  
normally a sampled input; however, the powerdown  
circuitry uses EXTINT as a level-sensitive input  
during powerdown mode.  
SAR  
set  
Successive approximation register. A component of  
the A/D converter.  
The “1” value of a bit or the act of giving it a “1”  
value. See also clear.  
SFR  
Special-function register.  
SHORT-INTEGER  
An 8-bit, signed variable with values from –27  
through +27–1.  
sign extension  
A method for converting data to a larger format by  
filling the upper bit positions with the value of the  
sign. This conversion preserves the positive or  
negative value of signed integers.  
sink current  
Current flowing into a device to ground. Always a  
positive value.  
source current  
Current flowing out of a device from VCC. Always a  
negative value.  
SP  
Stack pointer.  
special interrupt  
Any of the three nonmaskable interrupts (unimple-  
mented opcode, software trap, or NMI).  
Glossary-10  
GLOSSARY  
special-purpose memory  
standard interrupt  
A partition of memory used for storing the interrupt  
vectors, PTS vectors, chip configuration bytes, and  
several reserved locations.  
Any maskable interrupt that is assigned to the  
interrupt controller for processing by an interrupt  
service routine.  
state time (or state)  
The basic time unit of the microcontroller; the  
combined period of the two internal timing signals,  
PH1 and PH2. Because the microcontroller can  
operate at many frequencies, this manual defines time  
requirements in terms of state times rather than in  
specific units of time.  
successive approximation  
An A/D conversion method that uses a binary search  
to arrive at the best digital representation of an analog  
input.  
t
Lowercase “t” represents the period of the internal  
clock.  
temperature coefficient  
temperature drift  
Change in the stated variable for each degree  
Centigrade of temperature change.  
The change in a specification due to a change in  
temperature. Temperature drift can be calculated by  
using the temperature coefficient for the specification.  
terminal-based characteristic  
An actual characteristic that has been translated and  
scaled to remove zero-offset error and full-scale  
error. A terminal-based characteristic resembles an  
actual characteristic with zero-offset error and full-  
scale error removed.  
transfer function  
A graph of output code versus input voltage; the  
characteristic of the A/D converter.  
transfer function errors  
Errors inherent in an analog-to-digital conversion  
process: quantizing error, zero-offset error, full-scale  
error, differential nonlinearity, and nonlinearity.  
Errors that are hardware-dependent, rather than being  
inherent in the process itself, include feedthrough,  
repeatability, channel-to-channel matching, off-  
isolation, and VCC rejection errors.  
UART  
Universal asynchronous receiver and transmitter. A  
part of the serial I/O port.  
Glossary-11  
8XC196LX SUPPLEMENT  
VCC rejection  
The property of an A/D converter that causes it to  
ignore (reject) changes in VCC so that the actual  
characteristic is unaffected by those changes. The  
effectiveness of VCC rejection is measured by the ratio  
of the change in VCC to the change in the actual  
characteristic.  
VPW  
Variable pulse-width. A forced high/low symbol  
transition formatting scheme that tracks the duration  
between two consecutive transitions and the level of  
the bus, active or passive.  
wait state  
Time spent waiting for an operation to take place.  
Wait states are added to external bus cycles to allow a  
slow memory device to respond to a request from the  
microcontroller.  
watchdog timer  
WDT  
An internal timer that resets the microcontroller if  
software fails to respond before the timer overflows.  
Watchdog timer. An internal timer that resets the  
microcontroller if software fails to respond before the  
timer overflows.  
word  
Any 16-bit unit of data.  
WORD  
An unsigned, 16-bit variable with values from 0  
through 216–1.  
zero extension  
A method for converting data to a larger format by  
filling the upper bit positions with zeros.  
zero-offset error  
An ideal A/D converter’s first code transition occurs  
when the input voltage is 0.5 LSB. Zero-offset error is  
the difference between 0.5 LSB and the actual input  
voltage that triggers an A/D converter’s first code  
transition.  
Glossary-12  
Index  
FXTAL1, 2-4  
A
Address map, 3-1  
Address partitions  
H
map, 3-1  
OTPROM, 11-1  
program memory, 11-1  
special-purpose memory, 11-1  
ALE, idle, powerdown, reset status, A-8, A-9  
I
Idle mode pin status, A-8, A-9  
Internal timing, 2-2, 10-1  
B
Block diagram  
8XC196Lx, 2-2  
pending 1 register, 4-6  
priorities, 4-2  
C
CLKOUT  
sources, 4-2  
vectors, 4-2  
and internal timing, 2-2–2-4  
output frequency, 2-5  
Clock circuitry, 2-3, 10-2  
in-frame response  
D
interrupt status register, 8-21  
configuration register, 8-18  
registers, 8-3–8-4  
delay register, 8-20  
Design considerations, 9-2  
Device pin reset status, A-8, A-9  
Documents, related, 1-2  
E
signals, 8-3  
EPA  
interrupt mask 1 register, 7-4  
interrupt mask register, 7-4  
interrupt pending 1 register, 7-5  
ESD protection, 5-2, 5-5  
M
Manual contents, summary, 1-1–1-2  
F
O
Formulas  
ONCE mode, entering and exiting, 10-2  
OTPROM address map, 11-1  
clock period (t), 2-4  
PH1 and PH2 frequency, 2-4  
state time, 2-4  
Index-1  
INT_PEND, 4-5  
J_CFG, 8-18  
J_CMD, 8-17  
J_DLY, 8-20  
P
Period (t), 2-4  
Port 0  
idle, powerdown, reset status, A-8, A-9  
overview, 5-1  
Port 1  
configuring, 5-3  
idle, powerdown, reset status, A-8, A-9  
overview, 5-1  
J_STAT, 8-21  
J_TX, 8-14  
PTSSEL, 4-7  
SSIO0_CLK, 6-1  
Port 2  
configuring, 5-3  
overview, 5-1  
P2.7 reset status, 5-2  
Port 3  
internal structure, 5-5  
overview, 5-1  
pin status, A-8, A-9  
status of CLKOUT/P2.7, 5-2  
Port 4  
idle, powerdown, reset status, A-8, A-9  
internal structure, 5-5  
overview, 5-1  
Port 5  
Serial port programming mode, 11-5  
configuring, 5-3  
overview, 5-1  
Port 6  
default conditions, A-8, A-9  
status symbols defined, A-7  
configuring, 5-3  
idle, powerdown, reset status, A-8, A-9  
overview, 5-1  
Symbols, signal status, A-7  
Synchronous serial port 0 clock register, 6-1  
Synchronous serial port 1 clock register, 6-2  
Ports, input buffers, 5-2  
Powerdown mode, pin status, A-8, A-9  
PTS select register, 4-7  
PTS service register, 4-8  
U
R
Register file  
and address-mapped SFRs, 3-6  
WSR values and direct addresses, 3-6  
WR#, idle, powerdown, reset status, A-8, A-9  
and windowing, 3-2  
description, 3-3  
Registers  
EPA_MASK, 7-4  
EPA_MASK1, 7-4  
EPA_PEND, 7-5  
EPA_PEND1, 7-5  
EPAIPV, 7-6  
INT_MASK, 4-3  
Index-2  

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