Cypress NoBL CY7C1357C User Manual

CY7C1355C

CY7C1357C

9-Mbit (256K x 36/512K x 18)

Flow-Through SRAM with NoBL™ Architecture

Functional Description^[1]

Features

• No Bus Latency™ (NoBL™) architecture eliminates

dead cycles between write and read cycles

The CY7C1355C/CY7C1357C is a 3.3V, 256K x 36/512K x 18

Synchronous Flow-through Burst SRAM designed specifically

to support unlimited true back-to-back Read/Write operations

• Can support up to 133-MHz bus operations with zero

wait states

without

the

insertion

wait

states.

The

CY7C1355C/CY7C1357C is equipped with the advanced No

Bus Latency (NoBL) logic required to enable consecutive

Read/Write operations with data being transferred on every

clock cycle. This feature dramatically improves the throughput

of data through the SRAM, especially in systems that require

frequent Write-Read transitions.

— Data is transferred on every clock

• Pin compatible and functionally equivalent to ZBT™

devices

• Internally self-timed output buffer control to eliminate

the need to use OE

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. The clock input is qualified by

the Clock Enable (CEN) signal, which when deasserted

suspends operation and extends the previous clock cycle.

Maximum access delay from the clock rise is 6.5 ns (133-MHz

device).

• Registered inputs for flow-through operation

• Byte Write capability

• 3.3V/2.5V I/O power supply (V

• Fast clock-to-output times

)

DDQ

— 6.5 ns (for 133-MHz device)

Write operations are controlled by the two or four Byte Write

Select (BW ) and a Write Enable (WE) input. All writes are

conducted with on-chip synchronous self-timed write circuitry.

• Clock Enable (CEN) pin to enable clock and suspend

operation

Three synchronous Chip Enables (CE , CE , CE ) and an

• Synchronous self-timed writes

• Asynchronous Output Enable

asynchronous Output Enable (OE) provide for easy bank

selection and output tri-state control. In order to avoid bus

contention, the output drivers are synchronously tri-stated

during the data portion of a write sequence.

• Available in JEDEC-standard and lead-free 100-Pin

TQFP, lead-free and non lead-free 119-Ball BGA

package and 165-Ball FBGA package

• Three chip enables for simple depth expansion.

• Automatic Power-down feature available using ZZ

mode or CE deselect

• IEEE 1149.1 JTAG-Compatible Boundary Scan

• Burst Capability—linear or interleaved burst order

• Low standby power

Selection Guide

133 MHz

6.5

100 MHz

7.5

Unit

Maximum Access Time

Maximum Operating Current

Maximum CMOS Standby Current

250

180

Note:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

Cypress Semiconductor Corporation

Document #: 38-05539 Rev. *E

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised September 14, 2006

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CY7C1355C

CY7C1357C

Pin Configurations

100-Pin TQFP Pinout

DQP_C

DQ_C

V_DDQ

V_SS

DQP_B

DQ_B

V_DDQ

V_SS

DQ_C

DQ_B

BYTE C

BYTE B

DQ_B

DQ_C

V_SS

DQ_B

V_SS

V_DDQ

DQ_C

Vss/DNU

V_DD

V_DDQ

DQ_B

V_SS

CY7C1355C

V_DD

V_SS

DQ_D

V_DDQ

V_SS

DQ_A

V_DDQ

V_SS

DQ_D

DQ_A

DQ_D

DQ_A

BYTE D

BYTE A

DQ_A

DQ_D

V_SS

DQ_A

V_SS

V_DDQ

DQ_D

DQP_D

V_DDQ

DQ_A

DQP_A

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CY7C1357C

Pin Configurations (continued)

100-Pin TQFP Pinout

V_DDQ

V_SS

DQ_B

V_DDQ

V_SS

DQP_A

DQ_A

V_SS

V_DDQ

DQ_A

V_SS

DQ_B

V_SS

V_DDQ

DQ_B

Vss/DNU

V_DD

CY7C1357C

BYTE A

BYTE B

V_DD

V_SS

DQ_B

V_DDQ

V_SS

DQ_A

V_DDQ

V_SS

DQ_A

DQ_B

DQP_B

V_SS

V_DDQ

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CY7C1357C

Pin Configurations (continued)

119-Ball BGA Pinout (3 Chip Enables with JTAG)

CY7C1355C (256K x 36)

NC/18M

DDQ

NC/576M

NC/1G

ADV/LD

DQP

DDQ

CLK

DDQ

CEN

DDQ

DQP

NC/144M

MODE

NC/288M

NC/72M

TMS

NC/36M

TDI

TCK

TDO

DDQ

CY7C1357C (512K x 18)

NC/18M

ADV/LD

DDQ

NC/576M

NC/1G

DQP

DDQ

CLK

DDQ

CEN

DDQ

DQP

NC/144M

NC/72M

MODE

NC/288M

NC/36M

TCK

TMS

TDI

TDO

DDQ

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CY7C1357C

Pin Configurations (continued)

165-Ball FBGA Pinout (3 Chip enable with JTAG)

CY7C1355C (256K x 36)

CE₁

BW_C

BW_B

NC/576M

NC/1G

DQP_C

DQ_C

CEN

V_SS

ADV/LD

CE2

V_DDQ

BW_D

V_SS

BW_A

V_SS

CLK

V_SS

V_DD

NC/18M

V_DDQ

DQ_C

DQP_B

DQ_B

V_DD

V_DDQ

DQ_B

DQ_C

V_DDQ

V_DD

V_SS

V_DD

V_DDQ

DQ_B

DQ_C

V_SS

DQ_B

DQ_D

V_DDQ

DQ_A

DQ_D

V_DDQ

V_DD

V_SS

V_DD

V_SS

V_DDQ

DQ_A

DQP_A

DQP_D

NC/144M NC/72M

TDI

TDO

NC/288M

MODE

NC/36M

TMS

TCK

CY7C1357C (512K x 18)

NC/576M

NC/1G

CE₁

BW_B

CEN

V_SS

ADV/LD

CE2

V_DDQ

V_SS

V_DD

BW_A

V_SS

CLK

V_SS

V_DD

NC/18M

V_DDQ

DQ_B

DQP_A

DQ_A

V_DDQ

DQ_B

V_DDQ

V_DD

V_SS

V_DD

V_DDQ

DQ_A

V_SS

DQ_A

DQ_B

V_DDQ

DQ_A

DQ_B

V_DDQ

V_DD

V_SS

V_DD

V_SS

V_DDQ

DQ_A

DQP_B

NC/144M NC/72M

MODE NC/36M

TDI

TDO

NC/288M

TMS

TCK

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CY7C1355C

CY7C1357C

Pin Definitions

Name

I/O

Description

Address Inputs used to select one of the address locations. Sampled at the rising edge

are fed to the two-bit burst counter.

A , A , A

Input-

Synchronous of the CLK. A

[1:0]

BW , BW

Input-

Byte Write Inputs, active LOW. Qualified with WEto conduct Writes to the SRAM. Sampled

BW , BW

Synchronous on the rising edge of CLK.

Input-

Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW.

Synchronous This signal must be asserted LOW to initiate a write sequence.

ADV/LD

Input-

Advance/Load Input. Used to advance the on-chip address counter or load a new address.

Synchronous When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW,

a new address can be loaded into the device for an access. After being deselected, ADV/LD

should be driven LOW in order to load a new address.

CLK

Input-

Clock

Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with

CEN. CLK is only recognized if CEN is active LOW.

Input-

Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction

Synchronous with CE , and CE to select/deselect the device.

Input-

Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction

Synchronous with CE and CE to select/deselect the device.

Input-

Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction

Synchronous with CE and CE to select/deselect the device.

Input-

Output Enable, asynchronous input, active LOW. Combined with the synchronous logic

Asynchronous block inside the device to control the direction of the I/O pins. When LOW, the I/O pins are

allowed to behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as

input data pins. OE is masked during the data portion of a write sequence, during the first

clock when emerging from a deselected state, when the device has been deselected.

CEN

Input-

Clock Enable Input, active LOW. When asserted LOW the Clock signal is recognized by

Synchronous the SRAM. When deasserted HIGH the Clock signal is masked. Since deasserting CEN

does not deselect the device, CEN can be used to extend the previous cycle when required.

Input-

ZZ “Sleep” Input. This active HIGH input places the device in a non-time critical “sleep”

Asynchronous condition with data integrity preserved. For normal operation, this pin has to be LOW or left

floating. ZZ pin has an internal pull-down.

I/O-

Synchronous triggered by the rising edge of CLK. As outputs, they deliver the data contained in the

memory location specified by the addresses presented during the previous

Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is

clock rise of the

Read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the

pins behave as outputs. When HIGH, DQ and DQP are placed in a tri-state condition.The

outputs are automatically tri-stated during the data portion of a Write sequence, during the

first clock when emerging from a deselected state, and when the device is deselected,

regardless of the state of OE.

I/O-

Bidirectional Data Parity I/O Lines. Functionally, these signals are identical to DQ .During

DQP

Synchronous Write sequences, DQP is controlled by BW correspondingly.

MODE

Input Strap Pin Mode Input. Selects the burst order of the device. When tied to Gnd selects linear burst

sequence. When tied to V or left floating selects interleaved burst sequence.

Power Supply Power supply inputs to the core of the device.

I/O Power

Supply

Power supply for the I/O circuitry.

DDQ

Ground

Ground for the device.

TDO

JTAG serial output Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the JTAG

Synchronous feature is not being utilized, this pin should be left unconnected. This pin is not available on

TQFP packages.

TDI

JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature

Synchronous is not being utilized, this pin can be left floating or connected to V through a pull up resistor.

This pin is not available on TQFP packages.

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CY7C1355C

CY7C1357C

Pin Definitions (continued)

Name

I/O

Description

TMS

JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature

Synchronous is not being utilized, this pin can be disconnected or connected to V . This pin is not

available on TQFP packages.

TCK

JTAG

Clock

Clock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin must

be connected to V . This pin is not available on TQFP packages.

–

No Connects. Not internally connected to the die. 18 Mbit, 36 Mbit, 72 Mbit, 144 Mbit, 288

Mbit, 576 Mbit and 1G are address expansion pins and are not internally connected to the

die.

/DNU

Ground/DNU This pin can be connected to Ground or should be left floating.

Burst Read Accesses

The CY7C1355C/CY7C1357C has an on-chip burst counter

that allows the user the ability to supply a single address and

conduct up to four Reads without reasserting the address

inputs. ADV/LD must be driven LOW in order to load a new

address into the SRAM, as described in the Single Read

Access section above. The sequence of the burst counter is

determined by the MODE input signal. A LOW input on MODE

selects a linear burst mode, a HIGH selects an interleaved

burst sequence. Both burst counters use A0 and A1 in the

burst sequence, and will wrap around when incremented suffi-

ciently. A HIGH input on ADV/LD will increment the internal

burst counter regardless of the state of chip enable inputs or

WE. WE is latched at the beginning of a burst cycle. Therefore,

the type of access (Read or Write) is maintained throughout

the burst sequence.

Functional Overview

The CY7C1355C/CY7C1357C is a synchronous flow-through

burst SRAM designed specifically to eliminate wait states

during Write-Read transitions. All synchronous inputs pass

through input registers controlled by the rising edge of the

clock. The clock signal is qualified with the Clock Enable input

signal (CEN). If CEN is HIGH, the clock signal is not recog-

nized and all internal states are maintained. All synchronous

operations are qualified with CEN. Maximum access delay

from the clock rise (t

) is 6.5 ns (133-MHz device).

CDV

Accesses can be initiated by asserting all three Chip Enables

(CE , CE , CE ) active at the rising edge of the clock. If Clock

Enable (CEN) is active LOW and ADV/LD is asserted LOW,

the address presented to the device will be latched. The

access can either be a Read or Write operation, depending on

Single Write Accesses

the status of the Write Enable (WE). BW can be used to

conduct Byte Write operations.

Write access are initiated when the following conditions are

satisfied at clock rise: (1) CEN is asserted LOW, (2) CE , CE ,

Write operations are qualified by the Write Enable (WE). All

writes are simplified with on-chip synchronous self-timed Write

circuitry.

and CE are ALL asserted active, and (3) the Write signal WE

is asserted LOW. The address presented to the address bus

is loaded into the address register. The write signals are

latched into the Control Logic block. The data lines are

automatically tri-stated regardless of the state of the OE input

signal. This allows the external logic to present the data on

Three synchronous Chip Enables (CE , CE , CE ) and an

asynchronous Output Enable (OE) simplify depth expansion.

All operations (Reads, Writes, and Deselects) are pipelined.

ADV/LD should be driven LOW once the device has been

deselected in order to load a new address for the next

operation.

DQs and DQP .

On the next clock rise the data presented to DQs and DQP

(or a subset for byte write operations, see Truth Table for

details) inputs is latched into the device and the write is

complete. Additional accesses (Read/Write/Deselect) can be

initiated on this cycle.

Single Read Accesses

A read access is initiated when the following conditions are

satisfied at clock rise: (1) CEN is asserted LOW, (2) CE , CE ,

The data written during the Write operation is controlled by

and CE are ALL asserted active, (3) the Write Enable input

BW signals. The CY7C1355C/CY7C1357C provides byte

signal WE is deasserted HIGH, and 4) ADV/LD is asserted

LOW. The address presented to the address inputs is latched

into the address register and presented to the memory array

and control logic. The control logic determines that a read

access is in progress and allows the requested data to

propagate to the output buffers. The data is available within 7.5

ns (133-MHz device) provided OE is active LOW. After the first

clock of the read access, the output buffers are controlled by

OE and the internal control logic. OE must be driven LOW in

order for the device to drive out the requested data. On the

subsequent clock, another operation (Read/Write/Deselect)

can be initiated. When the SRAM is deselected at clock rise

by one of the chip enable signals, its output will be tri-stated

immediately.

write capability that is described in the Truth Table. Asserting

the Write Enable input (WE) with the selected Byte Write

Select input will selectively write to only the desired bytes.

Bytes not selected during a byte write operation will remain

unaltered. A synchronous self-timed Write mechanism has

been provided to simplify the Write operations. Byte Write

capability has been included in order to greatly simplify

Read/Modify/Write sequences, which can be reduced to

simple Byte Write operations.

Because the CY7C1355C/CY7C1357C is a common I/O

device, data should not be driven into the device while the

outputs are active. The Output Enable (OE) can be deasserted

HIGH before presenting data to the DQs and DQP inputs.

Doing so will tri-state the output drivers. As a safety

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CY7C1357C

precaution, DQs and DQP are automatically tri-stated during

the data portion of a write cycle, regardless of the state of OE.

Interleaved Burst Address Table

(MODE = Floating or VDD)

Burst Write Accesses

First

Second

Address

A1: A0

Third

Address

A1: A0

Fourth

Address

A1: A0

Address

A1: A0

The CY7C1355C/CY7C1357C has an on-chip burst counter

that allows the user the ability to supply a single address and

conduct up to four Write operations without reasserting the

address inputs. ADV/LD must be driven LOW in order to load

the initial address, as described in the Single Write Access

section above. When ADV/LD is driven HIGH on the subse-

quent clock rise, the Chip Enables (CE , CE , and CE ) and

WE inputs are ignored and the burst counter is incremented.

Linear Burst Address Table (MODE = GND)

The correct BW inputs must be driven in each cycle of the

burst write, in order to write the correct bytes of data.

First

Second

Address

A1: A0

Third

Address

A1: A0

Fourth

Address

A1: A0

Address

A1: A0

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ

places the SRAM in a power conservation “sleep” mode. Two

clock cycles are required to enter into or exit from this “sleep”

mode. While in this mode, data integrity is guaranteed.

Accesses pending when entering the “sleep” mode are not

considered valid nor is the completion of the operation

guaranteed. The device must be deselected prior to entering

the “sleep” mode. CE , CE , and CE , must remain inactive

for the duration of t

after the ZZ input returns LOW.

ZZREC

ZZ Mode Electrical Characteristics

Parameter

Description

Sleep mode standby current

Device operation to ZZ

Test Conditions

ZZ > V – 0.2V

Min.

Max.

Unit

DDZZ

ZZ > V – 0.2V

ZZS

CYC

ZZ recovery time

ZZ < 0.2V

ZZREC

ZZI

CYC

ZZ active to sleep current

ZZ Inactive to exit sleep current

This parameter is sampled

CYC

RZZI

Truth Table^{[2, 3, 4, 5, 6, 7, 8]}

Address

Used CE CE CE ZZ ADV/LD WE BW OE CEN CLK

Operation

Deselect Cycle

None

L->H

Tri-State

Deselect Cycle

None

Continue Deselect Cycle

READ Cycle (Begin Burst)

READ Cycle (Continue Burst)

NOP/DUMMY READ (Begin Burst)

DUMMY READ (Continue Burst)

WRITE Cycle (Begin Burst)

None

External

L->H Data Out (Q)

External

L->H

Tri-State

External

L->H Data In (D)

WRITE Cycle (Continue Burst)

Notes:

2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW. BWx = L signifies at least one Byte Write Select is active, BWx = Valid signifies that the desired Byte Write

Selects are asserted, see Truth Table for details.

3. Write is defined by BW , and WE. See Truth Table for Read/Write.

4. When a Write cycle is detected, all I/Os are tri-stated, even during Byte Writes.

5. The DQs and DQP pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.

6. CEN = H, inserts wait states.

7. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE.

8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a Read cycle DQs and DQP = Tri-state when OE

is inactive or when the device is deselected, and DQs and DQP = data when OE is active.

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CY7C1357C

Truth Table^{[2, 3, 4, 5, 6, 7, 8]}

Address

Used CE CE CE ZZ ADV/LD WE BW OE CEN CLK

Operation

Tri-State

–

NOP/WRITE ABORT (Begin Burst)

WRITE ABORT (Continue Burst)

IGNORE CLOCK EDGE (Stall)

SLEEP MODE

None

L->H

Current

None

Tri-State

Partial Truth Table for Read/Write^{[2, 3, 9]}

Function (CY7C1355C)

Read

Write No bytes written

Write Byte A – (DQ and DQP )

Write Byte B – (DQ and DQP )

Write Byte C – (DQ and DQP )

Write Byte D – (DQ and DQP )

Write All Bytes

Truth Table for Read/Write^{[2, 3,9]}

Function (CY7C1357C)

Read

Write - No bytes written

Write Byte A – (DQ and DQP )

Write Byte B – (DQ and DQP )

Write All Bytes

Note:

9. Table only lists a partial listing of the byte write combinations. Any combination of BW is valid. Appropriate write will be done based on which byte write is active.

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CY7C1357C

Test MODE SELECT (TMS)

IEEE 1149.1 Serial Boundary Scan (JTAG)

The TMS input is used to give commands to the TAP controller

and is sampled on the rising edge of TCK. It is allowable to

leave this ball unconnected if the TAP is not used. The ball is

pulled up internally, resulting in a logic HIGH level.

The CY7C1355C/CY7C1357C incorporates a serial boundary

scan test access port (TAP) in the BGA package only. The

TQFP package does not offer this functionality. This part

operates in accordance with IEEE Standard 1149.1-1900, but

doesn’t have the set of functions required for full 1149.1

compliance. These functions from the IEEE specification are

excluded because their inclusion places an added delay in the

critical speed path of the SRAM. Note the TAP controller

functions in a manner that does not conflict with the operation

of other devices using 1149.1 fully compliant TAPs. The TAP

operates using JEDEC-standard 3.3V or 2.5V I/O logic levels.

Test Data-In (TDI)

The TDI ball is used to serially input information into the

registers and can be connected to the input of any of the

registers. The register between TDI and TDO is chosen by the

instruction that is loaded into the TAP instruction register. TDI

is internally pulled up and can be unconnected if the TAP is

unused in an application. TDI is connected to the most signif-

icant bit (MSB) of any register. (See Tap Controller Block

Diagram.)

The CY7C1355C/CY7C1357C contains a TAP controller,

instruction register, boundary scan register, bypass register,

and ID register.

Test Data-Out (TDO)

Disabling the JTAG Feature

The TDO output ball is used to serially clock data-out from the

registers. The output is active depending upon the current

state of the TAP state machine. The output changes on the

falling edge of TCK. TDO is connected to the least significant

bit (LSB) of any register. (See Tap Controller State Diagram.)

It is possible to operate the SRAM without using the JTAG

feature. To disable the TAP controller, TCK must be tied

LOW(VSS) to prevent clocking of the device. TDI and TMS are

internally pulled up and may be unconnected. They may alter-

nately be connected to VDD through a pull-up resistor. TDO

should be left unconnected. Upon power-up, the device will

come up in a reset state which will not interfere with the

operation of the device.

TAP Controller Block Diagram

Bypass Register

TAP Controller State Diagram

TEST-LOGIC

Selection

Circuitry

RESET

Instruction Register

31 30 29

Identification Register

Selection

Circuitry

TDI

TDO

RUN-TEST/

IDLE

SELECT

DR-SCAN

SELECT

IR-SCAN

CAPTURE-DR

CAPTURE-IR

Boundary Scan Register

SHIFT-DR

SHIFT-IR

TCK

TMS

EXIT1-DR

EXIT1-IR

TAP CONTROLLER

PAUSE-DR

PAUSE-IR

Performing a TAP Reset

A RESET is performed by forcing TMS HIGH (VDD) for five

rising edges of TCK. This RESET does not affect the operation

of the SRAM and may be performed while the SRAM is

operating.

EXIT2-DR

EXIT2-IR

UPDATE-DR

UPDATE-IR

At power-up, the TAP is reset internally to ensure that TDO

comes up in a High-Z state.

TAP Registers

The 0/1 next to each state represents the value of TMS at the

rising edge of the TCK.

Registers are connected between the TDI and TDO balls and

allow data to be scanned into and out of the SRAM test

circuitry. Only one register can be selected at a time through

the instruction register. Data is serially loaded into the TDI ball

on the rising edge of TCK. Data is output on the TDO ball on

the falling edge of TCK.

Test Access Port (TAP)

Test Clock (TCK)

The test clock is used only with the TAP controller. All inputs

are captured on the rising edge of TCK. All outputs are driven

from the falling edge of TCK.

Instruction Register

Three-bit instructions can be serially loaded into the instruction

TDI and TDO balls as shown in the Tap Controller Block

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CY7C1357C

Diagram. Upon power-up, the instruction register is loaded

with the IDCODE instruction. It is also loaded with the IDCODE

instruction if the controller is placed in a reset state as

described in the previous section.

SAMPLE Z

The SAMPLE Z instruction causes the boundary scan register

to be connected between the TDI and TDO pins when the TAP

controller is in a Shift-DR state. The SAMPLE Z command puts

the output bus into a High-Z state until the next command is

given during the “Update IR” state.

When the TAP controller is in the Capture-IR state, the two

least significant bits are loaded with a binary “01” pattern to

allow for fault isolation of the board-level serial test data path.

SAMPLE/PRELOAD

Bypass Register

SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When

the SAMPLE/PRELOAD instructions are loaded into the in-

struction register and the TAP controller is in the Capture-DR

state, a snapshot of data on the inputs and output pins is cap-

tured in the boundary scan register.

To save time when serially shifting data through registers, it is

sometimes advantageous to skip certain chips. The bypass

TDI and TDO balls. This allows data to be shifted through the

SRAM with minimal delay. The bypass register is set LOW

(VSS) when the BYPASS instruction is executed.

The user must be aware that the TAP controller clock can only

operate at a frequency up to 20 MHz, while the SRAM clock

operates more than an order of magnitude faster. Because

there is a large difference in the clock frequencies, it is possi-

ble that during the Capture-DR state, an input or output will

undergo a transition. The TAP may then try to capture a signal

while in transition (metastable state). This will not harm the

device, but there is no guarantee as to the value that will be

captured. Repeatable results may not be possible.

Boundary Scan Register

The boundary scan register is connected to all the input and

bidirectional balls on the SRAM.

The boundary scan register is loaded with the contents of the

RAM I/O ring when the TAP controller is in the Capture-DR

state and is then placed between the TDI and TDO balls when

the controller is moved to the Shift-DR state. The EXTEST,

SAMPLE/PRELOAD and SAMPLE Z instructions can be used

to capture the contents of the I/O ring.

To guarantee that the boundary scan register will capture the

correct value of a signal, the SRAM signal must be stabilized

long enough to meet the TAP controller's capture set-up plus

hold times (t and t ). The SRAM clock input might not be

The Boundary Scan Order tables show the order in which the

bits are connected. Each bit corresponds to one of the bumps

on the SRAM package. The MSB of the register is connected

to TDI, and the LSB is connected to TDO.

captured correctly if there is no way in a design to stop (or

slow) the clock during a SAMPLE/PRELOAD instruction. If this

is an issue, it is still possible to capture all other signals and

simply ignore the value of the CK and CK# captured in the

boundary scan register.

Identification (ID) Register

The ID register is loaded with a vendor-specific, 32-bit code

during the Capture-DR state when the IDCODE command is

loaded in the instruction register. The IDCODE is hardwired

into the SRAM and can be shifted out when the TAP controller

is in the Shift-DR state. The ID register has a vendor code and

other information described in the Identification Register

Definitions table.

Once the data is captured, it is possible to shift out the data by

putting the TAP into the Shift-DR state. This places the bound-

ary scan register between the TDI and TDO pins.

PRELOAD allows an initial data pattern to be placed at the

latched parallel outputs of the boundary scan register cells pri-

or to the selection of another boundary scan test operation.

The shifting of data for the SAMPLE and PRELOAD phases

can occur concurrently when required—that is, while data

captured is shifted out, the preloaded data can be shifted in.

TAP Instruction Set

Overview

BYPASS

Eight different instructions are possible with the three bit

instruction register. All combinations are listed in the

Instruction Codes table. Three of these instructions are listed

as RESERVED and should not be used. The other five instruc-

tions are described in detail below.

When the BYPASS instruction is loaded in the instruction

advantage of the BYPASS instruction is that it shortens the

boundary scan path when multiple devices are connected

together on a board.

Instructions are loaded into the TAP controller during the

Shift-IR state when the instruction register is placed between

TDI and TDO. During this state, instructions are shifted

through the instruction register through the TDI and TDO balls.

To execute the instruction once it is shifted in, the TAP

controller needs to be moved into the Update-IR state.

EXTEST

The EXTEST instruction enables the preloaded data to be

driven out through the system output pins. This instruction also

selects the boundary scan register to be connected for serial

access between the TDI and TDO in the shift-DR controller

state.

IDCODE

The IDCODE instruction causes a vendor-specific, 32-bit code

to be loaded into the instruction register. It also places the

instruction register between the TDI and TDO balls and allows

the IDCODE to be shifted out of the device when the TAP

controller enters the Shift-DR state.The IDCODE instruction is

loaded into the instruction register upon power-up or

whenever the TAP controller is given a test logic reset state.

Reserved

These instructions are not implemented but are reserved for

future use. Do not use these instructions.

Document #: 38-05539 Rev. *E

Page 12 of 28

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CY7C1355C

CY7C1357C

TAP Timing

Test Clock

(TCK)

CYC

TMSS

TDIS

TMSH

Test Mode Select

(TMS)

TDIH

Test Data-In

(TDI)

TDOV

TDOX

Test Data-Out

(TDO)

DON’T CARE

UNDEFINED

[10, 11]

TAP AC Switching Characteristics Over the Operating Range

Parameter

Clock

Description

Min.

Max.

Unit

TCK Clock Cycle Time

TCK Clock Frequency

TCK Clock HIGH Time

TCK Clock LOW Time

MHz

TCYC

Output Times

TCK Clock LOW to TDO Valid

TCK Clock LOW to TDO Invalid

TDOV

TDOX

Set-up Times

TMS Set-Up to TCK Clock Rise

TDI Set-Up to TCK Clock Rise

Capture Set-Up to TCK Rise

TMSS

TDIS

Hold Times

TMS Hold after TCK Clock Rise

TDI Hold after Clock Rise

TMSH

TDIH

Capture Hold after Clock Rise

Notes:

10. t and t refer to the set-up and hold time requirements of latching data from the boundary scan register.

11. Test conditions are specified using the load in TAP AC Test Conditions. t /t = 1 ns.

Document #: 38-05539 Rev. *E

Page 13 of 28

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CY7C1355C

CY7C1357C

3.3V TAP AC Test Conditions

2.5V TAP AC Test Conditions

Input pulse levels ................................................ V to 3.3V

Input pulse levels.................................................V to 2.5V

Input rise and fall times................................................... 1 ns

Input timing reference levels...........................................1.5V

Output reference levels...................................................1.5V

Test load termination supply voltage...............................1.5V

Input rise and fall time .....................................................1 ns

Input timing reference levels......................................... 1.25V

Output reference levels ................................................ 1.25V

Test load termination supply voltage ............................ 1.25V

3.3V TAP AC Output Load Equivalent

2.5V TAP AC Output Load Equivalent

1.5V

1.25V

50Ω

TDO

Z_O= 50Ω

20pF

TAP DC Electrical Characteristics And Operating Conditions (0°C < T < +70°C; V = 3.3V ± 0.165V unless

[12]

otherwise noted)

Parameter

Description

Conditions

Min.

2.4

2.0

2.9

2.1

Max.

Unit

Output HIGH Voltage

= –4.0 mA, V

= –1.0 mA, V

= 3.3V

= 2.5V

OH1

OH2

OL1

OL2

DDQ

Output HIGH Voltage

Output LOW Voltage

Input HIGH Voltage

Input LOW Voltage

Input Load Current

= –100 µA

= 3.3V

= 2.5V

= 3.3V

= 2.5V

= 3.3V

= 2.5V

= 3.3V

= 2.5V

= 3.3V

= 2.5V

DDQ

= 8.0 mA

= 100 µA

0.4

0.2

2.0

1.7

+ 0.3

–0.5

–0.3

–5

0.7

GND < V < V

DDQ

µA

Identification Register Definitions

CY7C1355C

(256Kx36)

CY7C1357C

(512Kx18)

Instruction Field

Revision Number (31:29)

Device Depth (28:24)

Description

010

01010

010

Describes the version number

Reserved for Internal Use

01010

001001

010110

Device Width (23:18)

001001

100110

00000110100

Defines memory type and architecture

Defines width and density

Cypress Device ID (17:12)

Cypress JEDEC ID Code (11:1)

ID Register Presence Indicator (0)

00000110100 Allows unique identification of SRAM vendor

Indicates the presence of an ID register

Note:

12. All voltages referenced to V (GND).

Document #: 38-05539 Rev. *E

Page 14 of 28

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CY7C1355C

CY7C1357C

Scan Register Sizes

Bit Size (x36)

Bit Size (x18)

Instruction

Bypass

Boundary Scan Order (119-ball BGA package)

Boundary Scan Order (165-ball FBGA package)

Identification Codes

Instruction

EXTEST

Code

Description

000

Captures I/O ring contents. Places the boundary scan register between TDI and TDO.

Forces all SRAM outputs to High-Z state. This instruction is not 1149.1 compliant.

IDCODE

001

010

Loads the ID register with the vendor ID code and places the register between TDI and

TDO. This operation does not affect SRAM operations.

SAMPLE Z

Captures I/O ring contents. Places the boundary scan register between TDI and TDO.

Forces all SRAM output drivers to a High-Z state.

RESERVED

011

100

Do Not Use: This instruction is reserved for future use.

SAMPLE/PRELOAD

Captures I/O ring contents. Places the boundary scan register between TDI and TDO.

Does not affect SRAM operation. This instruction does not implement 1149.1 preload

function and is therefore not 1149.1 compliant.

RESERVED

BYPASS

101

110

111

Do Not Use: This instruction is reserved for future use.

Places the bypass register between TDI and TDO. This operation does not affect SRAM

operations.

Document #: 38-05539 Rev. *E

Page 15 of 28

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CY7C1355C

CY7C1357C

119-ball BGA Boundary Scan Order

CY7C1355C (256K x 36)

CY7C1357C (512K x 18)

Signal

Name

Signal

Name

Bit# ball ID

Name

CLK

CEN

Bit#

ball ID

Bit#

ball Id

Name

CLK

Bit#

ball Id

CEN

ADV/LD

MODE

ADV/LD

MODE

Internal

DQP

Internal

DQP

Internal

DQP

Internal

DQP

Internal

DQP

Internal

BWB

Internal

Document #: 38-05539 Rev. *E

Page 16 of 28

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CY7C1355C

CY7C1357C

165-ball FBGA Boundary Scan Order

CY7C1355C (256K x 36)

CY7C1357C (512K x 18)

Signal

Name

Signal

Name

Signal

Name

Bit# ball ID

Name

CLK

CEN

Bit#

ball ID

Bit#

ball ID

Bit#

ball ID

CLK

CEN

ADV/LD

MODE

ADV/LD

MODE

Internal

DQP

Internal

B10

A10

C11

E10

F10

G10

D10

D11

E11

F11

G11

H11

J10

K10

L10

M10

J11

K11

L11

M11

N11

R11

R10

P10

B10

A10

DQP

A11

Internal

C11

Internal

DQP

D11

Internal

E11

Internal

F11

G11

H11

J10

K10

Internal

L10

M10

Internal

R11

Internal

DQP

Internal

DQP

Internal

R10

P10

Internal

Document #: 38-05539 Rev. *E

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CY7C1355C

CY7C1357C

DC Input Voltage ................................... –0.5V to V + 0.5V

Maximum Ratings

Current into Outputs (LOW)......................................... 20 mA

(Above which the useful life may be impaired. For user guide-

lines, not tested.)

Static Discharge Voltage...........................................> 2001V

(per MIL-STD-883, Method 3015)

Storage Temperature .................................–65°C to +150°C

Latch-up Current....................................................> 200 mA.

Ambient Temperature with

Power Applied.............................................–55°C to +125°C

Operating Range

Supply Voltage on V Relative to GND........ –0.5V to +4.6V

Ambient

Supply Voltage on V

Relative to GND ......–0.5V to +V

Range

Temperature

DDQ

DC Voltage Applied to Outputs

in Tri-State........................................... –0.5V to V

Commercial 0°C to +70°C 3.3V – 5%/+10% 2.5V – 5%

+ 0.5V

to V

DDQ

Industrial

–40°C to +85°C

[13, 14]

Electrical Characteristics Over the Operating Range

Parameter

Description

Power Supply Voltage

I/O Supply Voltage

Test Conditions

Min.

3.135

2.375

2.4

Max.

Unit

3.6

for 3.3V I/O

for 2.5V I/O

DDQ

2.625

Output HIGH Voltage

Output LOW Voltage

for 3.3V I/O, I = −4.0 mA

for 2.5V I/O, I = −1.0 mA

2.0

for 3.3V I/O, I = 8.0 mA

0.4

for 2.5V I/O, I = 1.0 mA

[13]

Input HIGH Voltage

for 3.3V I/O

for 2.5V I/O

for 3.3V I/O

for 2.5V I/O

2.0

1.7

+ 0.3V

[13]

Input LOW Voltage

–0.3

–5

0.8

0.7

Input Leakage Current GND ≤ V ≤ V

except ZZ and MODE

µA

DDQ

Input Current of MODE Input = V

–30

–5

µA

Input = V

Input Current of ZZ

Input = V

Output Leakage Current GND ≤ V ≤ V

Output Disabled

–5

DDQ,

Operating Supply

f = f

= Max., I

= 0 mA,

7.5-ns cycle, 133 MHz

10-ns cycle, 100 MHz

250

180

110

OUT

= 1/t

MAX CYC

Current

Automatic CE

V = Max, Device Deselected, All speeds

SB1

Power-down

Current—TTL Inputs

f = f

≥ V or V ≤ V

IH IN IL

, inputs switching

MAX

Automatic CE

Power-down

Current—CMOS Inputs f = 0, inputs static

V = Max, Device Deselected, All speeds

100

SB2

SB3

SB4

≤ 0.3V or V > V – 0.3V,

Automatic CE

Power-down

Current—CMOS Inputs f = f

V =Max, DeviceDeselected, or All speeds

≤ 0.3V or V > V – 0.3V

DDQ

, inputs switching

MAX

Automatic CE

Power-down

Current—TTL Inputs

V = Max, Device Deselected, All Speeds

≥ V or V ≤ V , f = 0, inputs

IH IN IL

static

Notes:

13. Overshoot: V (AC) < V +1.5V (Pulse width less than t

/2), undershoot: V (AC) > –2V (Pulse width less than t /2).

CYC

14. T

: Assumes a linear ramp from 0V to V (min.) within 200 ms. During this time V < V and V

< V

Power-up

DDQ

Document #: 38-05539 Rev. *E

Page 18 of 28

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CY7C1355C

CY7C1357C

Capacitance^[15]

100 TQFP

Max.

119 BGA 165 FBGA

Parameter

Description

Input Capacitance

Test Conditions

T = 25°C, f = 1 MHz,

Max.

Unit

= 3.3V.

= 2.5V

Clock Input Capacitance

Input/Output Capacitance

CLK

I/O

DDQ

Thermal Resistance^[15]

100 TQFP

Package

119 BGA

Package

165 FBGA

Package

Parameter

Description

Test Conditions

Unit

Thermal Resistance

(Junction to Ambient)

Test conditions follow standard

test methods and procedures

for measuring thermal

29.41

34.1

16.8

°C/W

Thermal Resistance

(Junction to Case)

6.31

14.0

3.0

°C/W

impedance, per EIA/JESD51.

AC Test Loads and Waveforms

3.3V I/O Test Load

R = 317Ω

3.3V

OUTPUT

R = 50Ω

OUTPUT

ALL INPUT PULSES

90%

V_DDQ

90%

10%

Z = 50Ω

10%

GND

5 pF

R = 351Ω

≤ 1 ns

V = 1.5V

INCLUDING

JIG AND

SCOPE

(c)

(a)

(b)

2.5V I/O Test Load

R = 1667Ω

2.5V

OUTPUT

R = 50Ω

OUTPUT

ALL INPUT PULSES

90%

V_DDQ

GND

90%

10%

Z = 50Ω

10%

5 pF

R = 1538Ω

≤ 1 ns

INCLUDING

JIG AND

SCOPE

V = 1.25V

(a)

(b)

(c)

Note:

15. Tested initially and after any design or process change that may affect these parameters

Document #: 38-05539 Rev. *E

Page 19 of 28

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CY7C1355C

CY7C1357C

[16, 17]

Switching Characteristics Over the Operating Range

–133

–100

Parameter

Description

Min.

Max.

Min.

Max.

Unit

[18]

(Typical) to the First Access

POWER

Clock

Clock Cycle Time

Clock HIGH

7.5

3.0

4.0

CYC

Clock LOW

Output Times

Data Output Valid after CLK Rise

Data Output Hold after CLK Rise

6.5

7.5

CDV

DOH

CLZ

2.0

[19, 20, 21]

Clock to Low-Z

[19, 20, 21]

Clock to High-Z

3.5

CHZ

OEV

OELZ

OEHZ

OE LOW to Output Valid

[19, 20, 21]

OE LOW to Output Low-Z

[19, 20, 21]

OE HIGH to Output High-Z

3.5

Set-up Times

Address Set-up before CLK Rise

ADV/LD Set-up before CLK Rise

1.5

ALS

WES

CENS

WE, BW Set-up before CLK Rise

CEN Set-up before CLK Rise

Data Input Set-up before CLK Rise

Chip Enable Set-Up before CLK Rise

CES

Hold Times

Address Hold after CLK Rise

ADV/LD Hold after CLK Rise

0.5

ALH

WEH

CENH

WE, BW Hold after CLK Rise

CEN Hold after CLK Rise

Data Input Hold after CLK Rise

Chip Enable Hold after CLK Rise

CEH

Notes:

16. Timing reference level is 1.5V when V

= 3.3V and is 1.25V when V

= 2.5V.

DDQ

17. Test conditions shown in (a) of AC Test Loads unless otherwise noted.

18. This part has a voltage regulator internally; t

is the time that the power needs to be supplied above V (minimum) initially, before a Read or Write operation

POWER

can be initiated.

19. t

, t

, and t

are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.

OEHZ

CHZ CLZ OELZ

20. At any given voltage and temperature, t

is less than t

and t

is less than t

to eliminate bus contention between SRAMs when sharing the same

OEHZ

OELZ

CHZ

CLZ

data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed

to achieve High-Z prior to Low-Z under the same system conditions.

21. This parameter is sampled and not 100% tested.

Document #: 38-05539 Rev. *E

Page 20 of 28

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CY7C1355C

CY7C1357C

Switching Waveforms

[22, 23, 24]

Read/Write Waveforms

CYC

CLK

CENS

CES

CENH

CEH

CEN

ADV/LD

BWX

ADDRESS

CDV

DOH

OEV

CLZ

CHZ

D(A1)

D(A2)

D(A2+1)

Q(A3)

Q(A4)

Q(A4+1)

D(A5)

Q(A6)

D(A7)

OEHZ

DOH

OELZ

COMMAND

WRITE

D(A1)

WRITE

D(A2)

BURST

WRITE

READ

Q(A3)

READ

Q(A4)

BURST

READ

WRITE

D(A5)

READ

Q(A6)

WRITE

D(A7)

DESELECT

D(A2+1)

Q(A4+1)

DON’T CARE

UNDEFINED

Notes:

For this waveform ZZ is tied LOW.

22.

23. When CE is LOW, CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH, CE is HIGH or CE is LOW or CE is HIGH.

24. Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved). Burst operations are optional.

Document #: 38-05539 Rev. *E

Page 21 of 28

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CY7C1355C

CY7C1357C

Switching Waveforms (continued)

[22, 23, 25]

NOP, STALL and DESELECT Cycles

CYC

CLK

CEN

CENS

CES

CENH

CEH

ADV/LD

BWX

ADDRESS

CDV

DOH

OEV

CLZ

CHZ

D(A1)

D(A2)

D(A2+1)

Q(A3)

Q(A4)

Q(A4+1)

D(A5)

Q(A6)

D(A7)

OEHZ

DOH

OELZ

COMMAND

WRITE

D(A1)

WRITE

D(A2)

BURST

WRITE

READ

Q(A3)

READ

Q(A4)

BURST

READ

WRITE

D(A5)

READ

Q(A6)

WRITE

D(A7)

DESELECT

D(A2+1)

Q(A4+1)

DON’T CARE

UNDEFINED

Note:

25. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrates CEN being used to create a pause. A write is not performed during this cycle.

Document #: 38-05539 Rev. *E

Page 22 of 28

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CY7C1355C

CY7C1357C

Switching Waveforms (continued)

[26, 27]

ZZ Mode Timing

CLK

ZZREC

ZZI

SUPPLY

DDZZ

RZZI

ALL INPUTS

(except ZZ)

DESELECT or READ Only

Outputs (Q)

High-Z

DON’T CARE

Notes:

26. Device must be deselected when entering ZZ mode. See truth table for all possible signal conditions to deselect the device.

27. DQs are in high-Z when exiting ZZ sleep mode.

Document #: 38-05539 Rev. *E

Page 23 of 28

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CY7C1355C

CY7C1357C

Ordering Information

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or

visit www.cypress.com for actual products offered.

Speed

(MHz)

Package

Diagram

Operating

Range

Ordering Code

Part and Package Type

133 CY7C1355C-133AXC

CY7C1357C-133AXC

CY7C1355C-133BGC

CY7C1357C-133BGC

CY7C1355C-133BGXC

CY7C1357C-133BGXC

CY7C1355C-133BZC

CY7C1357C-133BZC

CY7C1355C-133BZXC

CY7C1357C-133BZXC

CY7C1355C-133AXI

CY7C1357C-133AXI

CY7C1355C-133BGI

CY7C1357C-133BGI

CY7C1355C-133BGXI

CY7C1357C-133BGXI

CY7C1355C-133BZI

CY7C1357C-133BZI

CY7C1355C-133BZXI

CY7C1357C-133BZXI

100 CY7C1355C-100AXC

CY7C1357C-100AXC

CY7C1355C-100BGC

CY7C1357C-100BGC

CY7C1355C-100BGXC

CY7C1357C-100BGXC

CY7C1355C-100BZC

CY7C1357C-100BZC

CY7C1355C-100BZXC

CY7C1357C-100BZXC

CY7C1355C-100AXI

CY7C1357C-100AXI

CY7C1355C-100BGI

CY7C1357C-100BGI

CY7C1355C-100BGXI

CY7C1357C-100BGXI

CY7C1355C -100BZI

CY7C1357C-100BZI

CY7C1355C-100BZXI

CY7C1357C-100BZXI

51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free

Commercial

51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)

51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free

51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)

51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free

51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free

51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)

lndustrial

51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free

51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)

51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free

51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free

51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)

Commercial

51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free

51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)

51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free

51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free

51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)

lndustrial

51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free

51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)

51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free

Document #: 38-05539 Rev. *E

Page 24 of 28

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CY7C1355C

CY7C1357C

Package Diagrams

100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) (51-85050)

16.00 0.20

14.00 0.10

1.40 0.05

100

0.30 0.08

0.65

TYP.

12° 1°

(8X)

SEE DETAIL

0.20 MAX.

1.60 MAX.

R 0.08 MIN.

0.20 MAX.

0° MIN.

SEATING PLANE

STAND-OFF

0.05 MIN.

0.15 MAX.

NOTE:

1. JEDEC STD REF MS-026

0.25

GAUGE PLANE

2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH

MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE

R 0.08 MIN.

0.20 MAX.

BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH

3. DIMENSIONS IN MILLIMETERS

0°-7°

0.60 0.15

0.20 MIN.

51-85050-*B

1.00 REF.

DETAIL

Document #: 38-05539 Rev. *E

Page 25 of 28

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CY7C1355C

CY7C1357C

Package Diagrams (continued)

119-Ball BGA (14 x 22 x 2.4 mm) (51-85115)

Ø0.05 M C

Ø0.25 M C A B

A1 CORNER

Ø0.75 0.15(119X)

Ø1.00(3X) REF.

1.27

0.70 REF.

3.81

12.00

7.62

14.00 0.20

0.15(4X)

30° TYP.

51-85115-*B

SEATING PLANE

Document #: 38-05539 Rev. *E

Page 26 of 28

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CY7C1355C

CY7C1357C

Package Diagrams (continued)

165 FBGA 13 x 15 x 1.40 MM BB165D/BW165D

165-Ball FBGA (13 x 15 x 1.4 mm) (51-85180)

BOTTOM VIEW

PIN 1 CORNER

TOP VIEW

Ø0.05 M C

Ø0.25 M C A B

PIN 1 CORNER

-0Ø.060.25 M C A B

Ø0.50 (165X)

+0.14

-0.06

Ø0.50₃

(165X)

11 10

+0.14

11 10

1.00

5.00

1.00

5.00

10.00

13.00 0.10

0.15(4X)

NOTES :

SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD)

PACKAGE WEIGHT : 0.475g

SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD)

JEDEC REFERENCE : MO-216 / DESIGN 4.6C

PACKAGE WEIGHT : 0.475g

PACKAJEGDEECCORDEEFE:RBEBN0ACEC: MO-216 / DESIGN 4.6C

PACKAGE CODE : BB0AC

SEATING PLANE

51-85180-*A

NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device

Technology, Inc. All product and company names mentioned in this document are the trademarks of their respective holders

Document #: 38-05539 Rev. *E

Page 27 of 28

of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be

used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its

products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

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CY7C1355C

CY7C1357C

Document History Page

Document Title: CY7C1355C/CY7C1357C 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL™ Architecture

Document Number: 38-05539

Orig. of

REV.

ECN NO.

242032

332059

Issue Date Change

Description of Change

See ECN

RKF

PCI

New data sheet

Changed Boundary Scan Order to match the B rev of these devices

Removed description on Extest Output Bus Tri-state

Removed 117 MHz Speed Bin

Changed I

from 35 mA to 50 mA on Pg # 9

DDZZ

and I

from 40 mA to 110 and 100 mA respectively

SB1

SB3

Address expansion pins/balls in the pinouts for all packages are modified as

per JEDEC standard

Modified V

Corrected I

test conditions

OL, OH

Test Condition from (V ≥ V – 0.3V or V ≤ 0.3V) to (V ≥ V

SB4

or V ≤ V ) in the Electrical Characteristic Table on Pg #18

Changed Θ and Θ for TQFP Package from 25 and 9 °C/W to 29.41 and

6.13 °C/W

respectively

Changed Θ and Θ for BGA Package from 25 and 6 °C/W to 34.1 and 14.0

°C/W

respectively

Changed Θ and Θ for FBGA Package from 27 and 6 °C/W to 16.8 and 3.0

°C/W respectively

Added lead-free information for 100-pin TQFP, 119 BGA and 165 FBGA

Packages

Updated Ordering Information Table

Changed from Preliminary to Final

351895

See ECN

PCI

Changed I

Updated Ordering Information Table

from 30 to 40 mA

SB2

377095

408298

See ECN

PCI

Modified test condition in note# 14 from V < V to V < V

RXU

Changed address of Cypress Semiconductor Corporation on Page# 1 from

“3901 North First Street” to “198 Champion Court”

Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the

Electrical Characteristics Table

Changed three-state to tri-state

Replaced Package Name column with Package Diagram in the Ordering

Information table

Updated Ordering Information Table

501793

See ECN

VKN

Added the Maximum Rating for Supply Voltage on V

Relative to GND

DDQ

Changed t , t from 25 ns to 20 ns and t

from 5 ns to 10 ns in TAP AC

TH TL

TDOV

Switching Characteristics table.

Updated the Ordering Information table.

Document #: 38-05539 Rev. *E

Page 28 of 28

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