Cypress Perform CY14E108N User Manual

ADVANCE  
CY14E108L, CY14E108N  
8 Mbit (1024K x 8/512K x 16) nvSRAM  
Features  
Functional Description  
20 ns, 25 ns, and 45 ns access times  
The Cypress CY14E108L/CY14E108N is a fast static RAM, with  
a nonvolatile element in each memory cell. The memory is  
Internally organized as 1024K x 8 (CY14E108L) or 512K x 16  
(CY14E108N)  
organized as 1024K words of 8 bits each or 512K words of 16  
bits each. The embedded nonvolatile elements incorporate  
QuantumTrap technology, producing the world’s most reliable  
nonvolatile memory. The SRAM provides infinite read and write  
cycles, while independent nonvolatile data resides in the highly  
reliable QuantumTrap cell. Data transfers from the SRAM to the  
nonvolatile elements (the STORE operation) takes place  
automatically at power down. On power up, data is restored to  
the SRAM (the RECALL operation) from the nonvolatile memory.  
Both the STORE and RECALL operations are also available  
under software control.  
Hands off automatic STORE on power down with only a small  
capacitor  
®
STORE to QuantumTrap nonvolatile elements initiated by  
®
software, device pin, or AutoStore on power down  
RECALL to SRAM initiated by software or power up  
Infinite read, write, and recall cycles  
200,000 STORE cycles to QuantumTrap  
20 year data retention  
Single 5V +10% operation  
Commercial and industrial temperatures  
48-pin FBGA, 44 and 54-pin TSOP II packages  
Pb-free and RoHS compliance  
Logic Block Diagram  
V
V
CC  
CAP  
[1]  
A - A  
Address  
0
19  
[1]  
DQ0 - DQ7  
CE  
CY14E108L  
CY14E108N  
OE  
WE  
HSB  
BHE  
BLE  
V
SS  
Note  
1. Address A - A and Data DQ0 - DQ7 for x8 configuration, Address A - A and Data DQ0 - DQ15 for x16 configuration.  
0
19  
0
18  
Cypress Semiconductor Corporation  
Document Number: 001-45524 Rev. *A  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised June 24, 2008  
 
ADVANCE  
CY14E108L, CY14E108N  
Pin Definitions  
Pin Name  
IO Type  
Input  
Description  
A – A  
Address Inputs Used to Select One of the 1,048,576 bytes of the nvSRAM for x8 Configuration.  
0
19  
18  
A – A  
Address Inputs Used to Select One of the 524, 288 bytes of the nvSRAM for x16 Configuration.  
0
DQ0 – DQ7 Input/Output Bidirectional Data IO Lines for x8 Configuration. Used as input or output lines depending on  
operation.  
DQ0 – DQ15  
WE  
Bidirectional Data IO Lines for x16 Configuration. Used as input or output lines depending on  
operation.  
Input  
Write Enable Input, Active LOW. When selected LOW, data on the IO pins is written to the address  
location latched by the falling edge of CE.  
Input  
Input  
Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.  
CE  
OE  
Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read  
cycles. IO pins are tri-stated on deasserting OE high.  
Input  
Input  
Byte High Enable, Active LOW. Controls DQ15 - DQ8.  
Byte Low Enable, Active LOW. Controls DQ7 - DQ0.  
BHE  
BLE  
V
Ground  
Ground for the Device. Must be connected to the ground of the system.  
SS  
V
Power Supply Power Supply Inputs to the Device.  
CC  
Input/Output Hardware Store Busy (HSB). When LOW this output indicates that a hardware store is in progress.  
When pulled LOW external to the chip it initiates a nonvolatile STORE operation. A weak internal pull  
up resistor keeps this pin HIGH if not connected (connection optional).  
HSB  
V
Power Supply AutoStore Capacitor. Supplies power to the nvSRAM during power loss to store data from the SRAM  
CAP  
to nonvolatile elements.  
NC  
No Connect No Connect. Do not connect this pin to the die.  
Document Number: 001-45524 Rev. *A  
Page 3 of 20  
ADVANCE  
CY14E108L, CY14E108N  
To reduce unnecessary nonvolatile stores, AutoStore and  
Hardware Store operations are ignored unless at least one  
WRITE operation has taken place since the most recent STORE  
or RECALL cycle. Software initiated STORE cycles are  
performed regardless of whether a WRITE operation has taken  
place. Monitor the HSB signal by the system to detect if an  
AutoStore cycle is in progress.  
Device Operation  
The CY14E108L/CY14E108N nvSRAM is made up of two  
functional components paired in the same physical cell. They are  
an SRAM memory cell and a nonvolatile QuantumTrap cell. The  
SRAM memory cell operates as a standard fast static RAM. Data  
in the SRAM is transferred to the nonvolatile cell (the STORE  
operation), or from the nonvolatile cell to the SRAM (the RECALL  
operation). Using this unique architecture all cells are stored and  
recalled in parallel. During the STORE and RECALL operations  
SRAM read and write operations are inhibited. The  
CY14E108L/CY14E108N supports infinite reads and writes  
similar to a typical SRAM. In addition, it provides infinite RECALL  
operations from the nonvolatile cells and up to 200K STORE  
operations.  
Figure 3. AutoStore Mode  
Vcc  
0.1uF  
Vcc  
SRAM Read  
The CY14E108L/CY14E108N performs a READ cycle when CE  
and OE are LOW and WE and HSB are HIGH. The address  
WE  
VCAP  
specified on pins A  
or A  
determines which of the  
0-19  
0-18  
1,048,576 data bytes or 524,288 words of 16 bits each is  
accessed. When the read is initiated by an address transition,  
VCAP  
the outputs are valid after a delay of t . If the read is initiated by  
VSS  
AA  
CE or OE, the outputs are valid at t  
or at t  
, whichever is  
ACE  
DOE  
later. The data outputs repeatedly respond to address changes  
within the t access time without the need for transitions on any  
AA  
control input pins. This remains valid until another address  
change or until CE or OE is brought HIGH, or WE or HSB is  
brought LOW.  
Hardware STORE Operation  
SRAM Write  
The CY14B108L/CY14B108N provides the HSB pin to control  
and acknowledge the STORE operations. Use the HSB pin to  
request a hardware STORE cycle. When the HSB pin is driven  
LOW, the CY14B108L/CY14B108N conditionally initiates a  
A WRITE cycle is performed when CE and WE are LOW and  
HSB is HIGH. The address inputs must be stable before entering  
the WRITE cycle and must remain stable until either CE or WE  
goes high at the end of the cycle. The data on the common IO  
STORE operation after t  
. An actual STORE cycle only  
DELAY  
begins if a WRITE to the SRAM took place since the last STORE  
or RECALL cycle. The HSB pin also acts as an open drain driver  
that is internally driven LOW to indicate a busy condition while  
the STORE (initiated by any means) is in progress.  
pins DQ  
are written into the memory if the data is valid t  
0–15  
SD  
before the end of a WE controlled WRITE or before the end of a  
CE controlled WRITE. It is recommended that OE be kept HIGH  
during the entire WRITE cycle to avoid data bus contention on  
common IO lines. If OE is left LOW, internal circuitry turns off the  
SRAM READ and WRITE operations that are in progress when  
HSB is driven LOW by any means are given time to complete  
before the STORE operation is initiated. After HSB goes LOW,  
the CY14B108L/CY14B108N continues SRAM operations for  
output buffers t  
after WE goes LOW.  
HZWE  
AutoStore Operation  
t
. During t  
, multiple SRAM READ operations may take  
The CY14B108L/CY14B108N stores data to the nvSRAM using  
one of the following three storage operations: Hardware Store  
activated by HSB; Software Store activated by an address  
sequence; AutoStore on device power down. The AutoStore  
operation is a unique feature of QuantumTrap technology and is  
enabled by default on the CY14B108L/CY14B108N.  
DELAY  
DELAY  
place. If a WRITE is in progress when HSB is pulled low it is  
allowed a time, t to complete. However, any SRAM WRITE  
cycles requested after HSB goes LOW is inhibited until HSB  
DELAY  
returns HIGH.  
During any STORE operation, regardless of how it was initiated,  
the CY14B108L/CY14B108N continues to drive the HSB pin  
LOW, releasing it only when the STORE is complete.Upon  
During a normal operation, the device draws current from V to  
CC  
charge a capacitor connected to the V  
pin. This stored  
CAP  
completion  
of  
the  
STORE  
operation,  
the  
charge is used by the chip to perform a single STORE operation.  
If the voltage on the V pin drops below V , the part  
CY14B108L/CY14B108N remains disabled until the HSB pin  
returns HIGH. Leave the HSB unconnected if it is not used.  
CC  
SWITCH  
automatically disconnects the V  
pin from V . A STORE  
CAP  
CC  
operation is initiated with power provided by the V  
capacitor.  
CAP  
Hardware RECALL (Power Up)  
During power up or after any low power condition  
Figure 3 shows the proper connection of the storage capacitor  
(V ) for automatic store operation. Refer to the section DC  
CAP  
(V < V  
), an internal RECALL request is latched. When  
.
CC  
SWITCH  
CAP  
V
again exceeds the sense voltage of V  
, a RECALL  
SWITCH  
CC  
cycle is automatically initiated and takes t  
to complete.  
HRECALL  
Document Number: 001-45524 Rev. *A  
Page 4 of 20  
 
ADVANCE  
CY14E108L, CY14E108N  
is disabled. It is important to use READ cycles and not WRITE  
cycles in the sequence, although it is not necessary that OE be  
Software STORE  
Transfer data from the SRAM to the nonvolatile memory with a  
software address sequence. The CY14B108L/CY14B108N  
software STORE cycle is initiated by executing sequential CE  
controlled READ cycles from six specific address locations in  
exact order. During the STORE cycle an erase of the previous  
nonvolatile data is first performed, followed by a program of the  
nonvolatile elements. After a STORE cycle is initiated, further  
input and output are disabled until the cycle is completed.  
LOW for a valid sequence. After the t  
cycle time is fulfilled,  
STORE  
the SRAM is activated again for the READ and WRITE operation.  
Software RECALL  
Transfer the data from the nonvolatile memory to the SRAM with  
a software address sequence. A software RECALL cycle is  
initiated with a sequence of READ operations in a manner similar  
to the software STORE initiation. To initiate the RECALL cycle,  
the following sequence of CE controlled READ operations must  
be performed.  
Because a sequence of READs from specific addresses is used  
for STORE initiation, it is important that no other READ or WRITE  
accesses intervene in the sequence. If there are intervening  
READ or WRITE accesses, the sequence is aborted and no  
STORE or RECALL takes place.  
1. Read Address 0x4E38 Valid READ  
2. Read Address 0xB1C7 Valid READ  
3. Read Address 0x83E0 Valid READ  
4. Read Address 0x7C1F Valid READ  
5. Read Address 0x703F Valid READ  
6. Read Address 0x4C63 Initiate RECALL Cycle  
To initiate the software STORE cycle, the following READ  
sequence must be performed.  
1. Read Address 0x4E38 Valid READ  
2. Read Address 0xB1C7 Valid READ  
3. Read Address 0x83E0 Valid READ  
4. Read Address 0x7C1F Valid READ  
5. Read Address 0x703F Valid READ  
6. Read Address 0x8FC0 Initiate STORE Cycle  
Internally, RECALL is a two step procedure. First, the SRAM data  
is cleared and then the nonvolatile information is transferred into  
the SRAM cells. After the t  
cycle time, the SRAM is again  
RECALL  
ready for READ and WRITE operations. The RECALL operation  
does not alter the data in the nonvolatile elements.  
The software sequence may be clocked with CE controlled  
READs or OE controlled READs. After the sixth address in the  
sequence is entered, the STORE cycle commences and the chip  
Table 1. Mode Selection  
A15 - A0  
Mode  
IO  
Power  
CE  
WE  
OE  
H
X
X
X
Not Selected  
Output High Z  
Standby  
L
L
L
H
L
L
X
L
X
X
Read SRAM  
Write SRAM  
Output Data  
Input Data  
Active  
Active  
[3,4,5]  
H
0x4E38  
0xB1C7  
0x83E0  
0x7C1F  
0x703F  
0x8B45  
Read SRAM  
Read SRAM  
Read SRAM  
Read SRAM  
Read SRAM  
AutoStore  
Output Data  
Output Data  
Output Data  
Output Data  
Output Data  
Output Data  
Active  
Disable  
[3,4,5]  
L
H
L
0x4E38  
0xB1C7  
0x83E0  
0x7C1F  
0x703F  
0x4B46  
Read SRAM  
Read SRAM  
Read SRAM  
Read SRAM  
Read SRAM  
AutoStore Enable  
Output Data  
Output Data  
Output Data  
Output Data  
Output Data  
Output Data  
Active  
Notes  
3. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a nonvolatile cycle.  
4. While there are 20/19 address lines on the CY14B108L/CY14B108N, only the lower 16 lines are used to control software modes.  
5. IO state depends on the state of OE, BHE, and BLE. The IO table shown assumes OE, BHE, and BLE LOW.  
Document Number: 001-45524 Rev. *A  
Page 5 of 20  
     
ADVANCE  
CY14E108L, CY14E108N  
Table 1. Mode Selection (continued)  
A15 - A0  
Mode  
IO  
Power  
Active I  
CC2  
CE  
L
WE  
H
OE  
L
0x4E38  
0xB1C7  
0x83E0  
0x7C1F  
0x703F  
0x8FC0  
Read SRAM  
Read SRAM  
Read SRAM  
Read SRAM  
Read SRAM  
Output Data  
Output Data  
Output Data  
Output Data  
Output Data  
Nonvolatile Store Output High Z  
[3,4,5]  
L
H
L
0x4E38  
0xB1C7  
0x83E0  
0x7C1F  
0x703F  
0x4C63  
Read SRAM  
Read SRAM  
Read SRAM  
Read SRAM  
Read SRAM  
Nonvolatile  
Recall  
Output Data  
Output Data  
Output Data  
Output Data  
Output Data  
Output High Z  
Active  
If the AutoStore function is disabled or re-enabled a manual  
STORE operation (hardware or software) must be issued to save  
the AutoStore state through subsequent power down cycles. The  
part comes from the factory with AutoStore enabled.  
Preventing AutoStore  
The AutoStore function is disabled by initiating an AutoStore  
disable sequence. A sequence of read operations is performed  
in a manner similar to the software STORE initiation. To initiate  
the AutoStore disable sequence, the following sequence of CE  
controlled read operations must be performed:  
Data Protection  
The CY14E108L/CY14E108N protects data from corruption  
during low voltage conditions by inhibiting all externally initiated  
STORE and write operations. The low voltage condition is  
1. Read address 0x4E38 Valid READ  
2. Read address 0xB1C7 Valid READ  
3. Read address 0x83E0 Valid READ  
4. Read address 0x7C1F Valid READ  
5. Read address 0x703F Valid READ  
6. Read address 0x8B45 AutoStore Disable  
detected when V < V  
. If the CY14E108L/CY14E108N  
CC  
SWITCH  
is in a write mode (both CE and WE LOW) at power up, after a  
RECALL or STORE, the write is inhibited until a negative  
transition on CE or WE is detected. This protects against  
inadvertent writes during power up or brown out conditions.  
The AutoStore is re-enabled by initiating an AutoStore enable  
sequence. A sequence of read operations is performed in a  
manner similar to the software RECALL initiation. To initiate the  
AutoStore enable sequence, the following sequence of CE  
controlled read operations must be performed:  
Noise Considerations  
1. Read address 0x4E38 Valid READ  
2. Read address 0xB1C7 Valid READ  
3. Read address 0x83E0 Valid READ  
4. Read address 0x7C1F Valid READ  
5. Read address 0x703F Valid READ  
6. Read address 0x4B46 AutoStore Enable  
Document Number: 001-45524 Rev. *A  
Page 6 of 20  
ADVANCE  
CY14E108L, CY14E108N  
Package Power Dissipation  
Maximum Ratings  
Capability (T = 25°C) ................................................... 1.0W  
A
Exceeding maximum ratings may impair the useful life of the  
device. These user guidelines are not tested.  
Surface Mount Pb Soldering  
Temperature (3 Seconds).......................................... +260°C  
Storage Temperature ................................. –65°C to +150°C  
Output Short Circuit Current .................................... 15 mA  
Ambient Temperature with  
Power Applied ............................................ –55°C to +150°C  
Static Discharge Voltage.......................................... > 2001V  
(per MIL-STD-883, Method 3015)  
Supply Voltage on V Relative to GND ..........–0.5V to 7.0V  
CC  
Latch Up Current ................................................... > 200 mA  
Voltage Applied to Outputs  
in High-Z State.......................................0.5V to V + 0.5V  
Operating Range  
CC  
Range  
Commercial  
Industrial  
Ambient Temperature  
0°C to +70°C  
V
CC  
Input Voltage.............................................–0.5V to Vcc+0.5V  
Transient Voltage (<20 ns) on  
4.5V to 5.5V  
4.5V to 5.5V  
Any Pin to Ground Potential ..................2.0V to V + 2.0V  
CC  
–40°C to +85°C  
DC Electrical Characteristics  
Over the Operating Range (V = 2.7V to 3.6V)  
CC  
Parameter  
Description  
Average V Current  
Test Conditions  
Min  
Max  
Unit  
I
t
t
t
= 20 ns  
= 25 ns  
= 45 ns  
Commercial  
70  
70  
55  
mA  
mA  
mA  
CC1  
CC  
RC  
RC  
RC  
Dependent on output loading and cycle  
rate.Values obtained without output loads.  
Industrial  
75  
75  
57  
mA  
mA  
mA  
I
= 0 mA  
OUT  
I
I
Average V Current All Inputs Don’t Care, V = Max  
12  
mA  
CC2  
CC  
CC  
During STORE  
Average current for duration t  
STORE  
AverageV Currentat WE > (V – 0.2). All other I/P cycling.  
38  
mA  
CC3  
CC  
CC  
t
= 200 ns, 5V, 25°C Dependent on output loading and cycle rate. Values obtained  
RC  
typical  
without output loads.  
I
I
Average V  
Current All Inputs Don’t Care, V = Max  
12  
6
mA  
mA  
CC4  
CAP  
CC  
During AutoStore Cycle Average current for duration t  
STORE  
V
Standby Current CE > (V – 0.2). All others V < 0.2V or > (V – 0.2V).  
CC IN CC  
SB  
CC  
Standby current level after nonvolatile cycle is complete.  
Inputs are static. f = 0 MHz.  
I
Input Leakage Current V = Max, V < V < V  
(except HSB)  
–2  
–200  
–2  
+2  
+2  
+2  
μA  
μA  
μA  
IX  
CC  
SS  
IN  
CC  
Input Leakage Current V = Max, V < V < V  
(For HSB)  
CC  
CC  
SS  
IN  
CC  
I
Off-State Output  
Leakage Current  
V
= Max, V < V < V , CE or OE > V  
SS IN CC IH  
OZ  
V
V
V
V
V
Input HIGH Voltage  
Input LOW Voltage  
Output HIGH Voltage  
Output LOW Voltage  
Storage Capacitor  
2.0  
V
+ 0.5  
CC  
V
V
IH  
V
– 0.5  
ss  
0.8  
IL  
I
I
= –2 mA  
= 4 mA  
2.4  
V
OH  
OL  
OUT  
0.4  
V
OUT  
Between V  
pin and V , 5V Rated  
122  
164  
μF  
CAP  
CAP  
SS  
Notes  
6. Outputs shorted for no more than one second. No more than one output shorted at a time.  
7. Typical conditions for the active current shown on the front page of the data sheet are average values at 25°C (room temperature) and V = 5V. Not 100% tested.  
CC  
8. The HSB pin has I  
=-10uA for V of 2.4V. This parameter is characterized but not tested.  
OUT  
OH  
Document Number: 001-45524 Rev. *A  
Page 7 of 20  
       
ADVANCE  
CY14E108L, CY14E108N  
Capacitance  
In the following table, the capacitance parameters are listed  
Parameter Description  
Input Capacitance  
Output Capacitance  
.
Test Conditions  
Max  
14  
Unit  
pF  
C
C
T = 25°C, f = 1 MHz,  
IN  
A
V
= 0 to 3.0V  
CC  
14  
pF  
OUT  
Thermal Resistance  
In the following table, the thermal resistance parameters are listed  
[9]  
.
Parameter  
Description  
Test Conditions  
Test conditions follow standard test methods  
48-FBGA 44-TSOP II 54-TSOP II Unit  
ΘJA  
Thermal Resistance  
(Junction to Ambient) and procedures for measuring thermal  
28.82  
31.11  
30.73  
°C/W  
impedance, in accordance with EIA/JESD51.  
ΘJC  
Thermal Resistance  
(Junction to Case)  
7.84  
5.56  
6.08  
°C/W  
Figure 4. AC Test Loads  
963Ω  
R1  
for tri-state specs  
963Ω  
5.0V  
OUTPUT  
5.0V  
OUTPUT  
R1  
R2  
512Ω  
R2  
512Ω  
5 pF  
30 pF  
AC Test Conditions  
Input Pulse Levels ....................................................0V to 3V  
Input Rise and Fall Times (10% - 90%)........................ <5 ns  
Input and Output Timing Reference Levels .................... 1.5V  
Note  
9. These parameters are guaranteed but not tested.  
Document Number: 001-45524 Rev. *A  
Page 8 of 20  
 
ADVANCE  
CY14E108L, CY14E108N  
AC Switching Characteristics  
In the following table, the AC switching characteristics are listed.  
Parameters  
Description  
20 ns  
25 ns  
45 ns  
Unit  
Cypress  
Alt  
Min  
Max  
Min  
Max  
Min  
Max  
Parameters  
Parameters  
SRAM Read Cycle  
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Chip Enable Access Time  
20  
25  
45  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ACE  
RC  
ACS  
RC  
AA  
Read Cycle Time  
20  
25  
45  
Address Access Time  
20  
10  
25  
12  
45  
20  
AA  
Output Enable to Data Valid  
Output Hold After Address Change  
Chip Enable to Output Active  
Chip Disable to Output Inactive  
Output Enable to Output Active  
Output Disable to Output Inactive  
Chip Enable to Power Active  
Chip Disable to Power Standby  
Byte Enable to Data Valid  
DOE  
OHA  
LZCE  
OE  
OH  
LZ  
3
3
3
3
3
3
8
8
10  
10  
15  
15  
HZCE  
HZ  
0
0
0
0
0
0
LZOE  
OLZ  
OHZ  
PA  
HZOE  
PU  
PD  
20  
10  
25  
12  
45  
20  
PS  
-
-
-
DBE  
Byte Enable to Output Active  
Byte Disable to Output Inactive  
0
0
0
LZBE  
HZBE  
8
10  
15  
SRAM Write Cycle  
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Write Cycle Time  
20  
15  
15  
8
25  
20  
20  
10  
0
45  
30  
30  
15  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
WC  
PWE  
SCE  
SD  
WC  
WP  
CW  
DW  
DH  
Write Pulse Width  
Chip Enable To End of Write  
Data Setup to End of Write  
Data Hold After End of Write  
Address Setup to End of Write  
Address Setup to Start of Write  
Address Hold After End of Write  
Write Enable to Output Disable  
Output Active after End of Write  
Byte Enable to End of Write  
0
HD  
15  
0
20  
0
30  
0
AW  
AW  
AS  
SA  
0
0
0
HA  
WR  
WZ  
OW  
[12,13]  
8
10  
15  
HZWE  
3
3
3
LZWE  
BW  
-
15  
20  
30  
Notes  
10. WE must be HIGH during SRAM read cycles.  
11. Device is continuously selected with CE and OE both LOW.  
12. Measured ±200 mV from steady state output voltage.  
13. If WE is LOW when CE goes LOW, the output goes into high impedance state.  
Document Number: 001-45524 Rev. *A  
Page 9 of 20  
       
ADVANCE  
CY14E108L, CY14E108N  
AutoStore and Power Up RECALL  
CY14E108L/CY14E108N  
Parameters  
Description  
Unit  
Min  
Max  
20  
t
t
Power Up RECALL Duration  
STORE Cycle Duration  
Low Voltage Trigger Level  
VCC Rise Time  
ms  
ms  
V
HRECALL  
15  
STORE  
V
t
4.4  
SWITCH  
150  
μs  
VCCRISE  
Software Controlled STORE and RECALL Cycle  
In the following table, the software controlled STORE/RECALL cycle parameters are listed.  
20ns  
25ns  
45ns  
Parameters  
Description  
Unit  
Min  
20  
0
Max  
Min  
Max  
Min  
45  
0
Max  
t
t
t
t
t
t
STORE/RECALL Initiation Cycle Time  
Address Setup Time  
25  
0
ns  
ns  
ns  
ns  
μs  
μs  
RC  
AS  
Clock Pulse Width  
15  
1
20  
1
30  
1
CW  
Address Hold Time  
GHAX  
RECALL Duration  
200  
70  
200  
70  
200  
70  
RECALL  
Soft Sequence Processing Time  
SS  
Hardware STORE Cycle  
CY14E108L/CY14E108N  
Parameters  
Description  
Unit  
Min  
1
Max  
t
t
Time allowed to complete SRAM cycle  
Hardware STORE pulse width  
70  
μs  
DELAY  
15  
ns  
HLHX  
Switching Waveforms  
Figure 5. SRAM Read Cycle #1: Address Controlled  
tRC  
ADDRESS  
tAA  
tOHA  
DQ (DATA OUT)  
DATA VALID  
Notes  
14. t  
starts from the time V rises above V  
CC SWITCH.  
HRECALL  
15. If an SRAM Write has not taken place since the last nonvolatile cycle, no STORE takes place.  
16. The software sequence is clocked with CE controlled or OE controlled reads.  
17. The six consecutive addresses must be read in the order listed in the mode selection table. WE must be HIGH during all six consecutive cycles.  
18. This is the amount of time it takes to take action on a soft sequence command.Vcc power must remain HIGH to effectively register command.  
19. Commands such as STORE and RECALL lock out IO until operation is complete which further increases this time. See the specific command  
20. On a hardware STORE initiation, SRAM operation continues to be enabled for time t  
21. HSB must remain HIGH during READ and WRITE cycles.  
to allow read and write cycles to complete.  
DELAY  
Document Number: 001-45524 Rev. *A  
Page 10 of 20  
               
ADVANCE  
CY14E108L, CY14E108N  
Switching Waveforms (continued)  
[10, 21, 23]  
Figure 6. SRAM Read Cycle #2: CE and OE Controlled  
tRC  
ADDRESS  
CE  
tACE  
tPD  
tLZCE  
tHZCE  
OE  
tHZOE  
tDOE  
tLZOE  
BHE , BLE  
tHZCE  
tHZBE  
tDBE  
tLZBE  
DQ (DATA OUT)  
DATA VALID  
ACTIVE  
tPU  
STANDBY  
ICC  
Figure 7. SRAM Write Cycle #1: WE Controlled  
tWC  
ADDRESS  
CE  
tHA  
tSCE  
tAW  
tSA  
tPWE  
WE  
tBW  
BHE , BLE  
tHD  
tSD  
DATA VALID  
DATA IN  
tHZWE  
tLZWE  
HIGH IMPEDANCE  
PREVIOUS DATA  
DATA OUT  
Notes  
22. CE or WE must be >V during address transitions.  
IH  
23. BHE and BLE are applicable for x16 configuration only.  
Document Number: 001-45524 Rev. *A  
Page 11 of 20  
   
ADVANCE  
CY14E108L, CY14E108N  
Switching Waveforms (continued)  
Figure 8. SRAM Write Cycle #2: CE Controlled  
tWC  
ADDRESS  
CE  
tSA  
tSCE  
tHA  
tAW  
tPWE  
WE  
tBW  
tSD  
BHE , BLE  
tHD  
DATA IN  
DATA VALID  
HIGH IMPEDANCE  
DATA OUT  
Figure 9. AutoStore or Power Up RECALL  
No STORE occurs  
without atleast one  
SRAM write  
STORE occurs only  
if a SRAM write  
has happened  
V
CC  
V
SWITCH  
tVCCRISE  
AutoStore  
tSTORE  
tSTORE  
POWER-UP RECALL  
Read & Write Inhibited  
tHRECALL  
tHRECALL  
Note  
24. Read and Write cycles are ignored during STORE, RECALL, and while VCC is below V  
.
SWITCH  
Document Number: 001-45524 Rev. *A  
Page 12 of 20  
 
ADVANCE  
CY14E108L, CY14E108N  
Switching Waveforms (continued)  
Figure 10. CE Controlled Software STORE/RECALL Cycle  
Figure 11. OE Controlled Software STORE/RECALL Cycle  
tRC  
tRC  
ADDRESS # 1  
ADDRESS # 6  
ADDRESS  
CE  
OE  
tAS  
tCW  
tGHAX  
t
STORE / tRECALL  
HIGH IMPEDANCE  
DATA VALID  
DQ (DATA)  
DATA VALID  
Document Number: 001-45524 Rev. *A  
Page 13 of 20  
ADVANCE  
CY14E108L, CY14E108N  
Switching Waveforms (continued)  
Figure 12. Hardware STORE Cycle  
Figure 13. Soft Sequence Processing  
tSS  
tSS  
Document Number: 001-45524 Rev. *A  
Page 14 of 20  
ADVANCE  
CY14E108L, CY14E108N  
Ordering Information  
Speed  
Package  
Operating  
Range  
Ordering Code  
Package Type  
44-pin TSOP II  
(ns)  
Diagram  
51-85087  
51-85087  
51-85087  
51-85128  
51-85128  
51-85128  
51-85160  
51-85160  
51-85160  
51-85128  
51-85128  
51-85128  
51-85160  
51-85160  
51-85160  
51-85087  
51-85087  
51-85087  
51-85128  
51-85128  
51-85128  
51-85160  
51-85160  
51-85160  
51-85128  
51-85128  
51-85128  
51-85160  
51-85160  
51-85160  
20  
CY14E108L-ZS20XCT  
CY14E108L-ZS20XIT  
CY14E108L-ZS20XI  
Commercial  
Industrial  
44-pin TSOP II  
44-pin TSOP II  
48-ball FBGA  
48-ball FBGA  
48-ball FBGA  
54-pin TSOP II  
54-pin TSOP II  
54-pin TSOP II  
48-ball FBGA  
48-ball FBGA  
48-ball FBGA  
54-pin TSOP II  
54-pin TSOP II  
54-pin TSOP II  
44-pin TSOP II  
44-pin TSOP II  
44-pin TSOP II  
48-ball FBGA  
48-ball FBGA  
48-ball FBGA  
54-pin TSOP II  
54-pin TSOP II  
54-pin TSOP II  
48-ball FBGA  
48-ball FBGA  
48-ball FBGA  
54-pin TSOP II  
54-pin TSOP II  
54-pin TSOP II  
CY14E108L-BA20XCT  
CY14E108L-BA20XIT  
CY14E108L-BA20XI  
CY14E108L-ZSP20XCT  
CY14E108L-ZSP20XIT  
CY14E108L-ZSP20XI  
CY14E108N-BA20XCT  
CY14E108N-BA20XIT  
CY14E108N-BA20XI  
CY14E108N-ZSP20XCT  
CY14E108N-ZSP20XIT  
CY14E108N-ZSP20XI  
CY14E108L-ZS25XCT  
CY14E108L-ZS25XIT  
CY14E108L-ZS25XI  
Commercial  
Industrial  
Commercial  
Industrial  
Commercial  
Industrial  
Commercial  
Industrial  
25  
Commercial  
Industrial  
CY14E108L-BA25XIT  
CY14E108L-BA25XI  
CY14E108N-BA25XCT  
CY14E108L-ZSP25XCT  
CY14E108L-ZSP25XIT  
CY14E108L-ZSP25XI  
CY14E108N-BA25XCT  
CY14E108N-BA25XIT  
CY14E108N-BA25XI  
CY14E108N-ZSP25XCT  
CY14E108N-ZSP25XIT  
CY14E108N-ZSP25XI  
Industrial  
Commercial  
Commercial  
Industrial  
Commercial  
Industrial  
Commercial  
Industrial  
Document Number: 001-45524 Rev. *A  
Page 15 of 20  
ADVANCE  
CY14E108L, CY14E108N  
Ordering Information (continued)  
Speed  
Package  
Operating  
Range  
Ordering Code  
(ns)  
Package Type  
44-pin TSOP II  
Diagram  
51-85087  
51-85087  
51-85087  
51-85128  
51-85128  
51-85128  
51-85160  
51-85160  
51-85160  
51-85128  
51-85128  
51-85128  
51-85160  
51-85160  
51-85160  
45  
CY14E108L-ZS45XCT  
CY14E108L-ZS45XIT  
CY14E108L-ZS45XI  
Commercial  
Industrial  
44-pin TSOP II  
44-pin TSOP II  
48-ball FBGA  
48-ball FBGA  
48-ball FBGA  
54-pin TSOP II  
54-pin TSOP II  
54-pin TSOP II  
48-ball FBGA  
48-ball FBGA  
48-ball FBGA  
54-pin TSOP II  
54-pin TSOP II  
54-pin TSOP II  
CY14E108L-BA45XCT  
CY14E108L-BA45XIT  
CY14E108L-BA45XI  
CY14E108L-ZSP45XCT  
CY14E108L-ZSP45XIT  
CY14E108L-ZSP45XI  
CY14E108N-BA45XCT  
CY14E108N-BA45XIT  
CY14E108N-BA45XI  
CY14E108N-ZSP45XCT  
CY14E108N-ZSP45XIT  
CY14E108N-ZSP45XI  
Commercial  
Industrial  
Commercial  
Industrial  
Commercial  
Industrial  
Commercial  
Industrial  
All parts are Pb-free. The above table contains Advance information. Please contact your local Cypress sales representative for availability of these parts.  
Part Numbering Nomenclature  
CY 14 E 108 L - ZS P 20 X C T  
Option:  
T - Tape & Reel  
Blank - Std.  
Temperature:  
C - Commercial (0 to 70°C)  
I - Industrial (–40 to 85°C)  
Speed:  
Pb-Free  
20 - 20ns  
25 - 25 ns  
45 - 45 ns  
Package:  
P - 54 Pin  
Blank - 44 Pin  
BA - 48 FBGA  
ZS - TSOP II  
Data Bus:  
L - x8  
N - x16  
Density:  
108 - 8 Mb  
Voltage:  
E - 5.0V  
NVSRAM  
14 - Auto Store + Software Store + Hardware Store  
Cypress  
Document Number: 001-45524 Rev. *A  
Page 16 of 20  
ADVANCE  
CY14E108L, CY14E108N  
Package Diagrams  
Figure 14. 44-Pin TSOP II (51-85087)  
DIMENSION IN MM (INCH)  
MAX  
MIN.  
PIN 1 I.D.  
22  
1
R
O
E
K
A
X
S G  
EJECTOR PIN  
23  
44  
TOP VIEW  
BOTTOM VIEW  
10.262 (0.404)  
10.058 (0.396)  
0.400(0.016)  
0.300 (0.012)  
0.800 BSC  
(0.0315)  
BASE PLANE  
0.10 (.004)  
0.210 (0.0083)  
0.120 (0.0047)  
0°-5°  
18.517 (0.729)  
18.313 (0.721)  
0.597 (0.0235)  
0.406 (0.0160)  
SEATING  
PLANE  
51-85087-*A  
Document Number: 001-45524 Rev. *A  
Page 17 of 20  
ADVANCE  
CY14E108L, CY14E108N  
Package Diagrams (continued)  
Figure 15. 48-ball FBGA - 6 mm x 10 mm x 1.2 mm (51-85128)  
BOTTOM VIEW  
A1 CORNER  
TOP VIEW  
Ø0.05 M C  
Ø0.25 M C A B  
A1 CORNER  
Ø0.30 0.05(48X)  
1
2
3
4
5
6
6
5
4
3
2
1
A
A
B
C
D
B
C
D
E
E
F
F
G
G
H
H
1.875  
A
A
0.75  
B
6.00 0.10  
3.75  
B
6.00 0.10  
0.15(4X)  
SEATING PLANE  
C
51-85128-*D  
Document Number: 001-45524 Rev. *A  
Page 18 of 20  
ADVANCE  
CY14E108L, CY14E108N  
Package Diagrams (continued)  
Figure 16. 54-Pin TSOP II (51-85160)  
51-85160-**  
Document Number: 001-45524 Rev. *A  
Page 19 of 20  
ADVANCE  
CY14E108L, CY14E108N  
Document History Page  
Document Title: CY14E108L/CY14E108N 8 Mbit (1024K x 8/512K x 16) nvSRAM  
Document Number: 001- 45524  
Submission  
Date  
Orig. of  
Change  
REV.  
ECN NO.  
Description of Change  
**  
**  
2428826  
2520023  
See ECN  
06/23/08  
GVCH  
New Data Sheet  
GVCH/PYRS Updated I  
for tRC=20ns, 25ns and 45ns access speed for both  
CC1  
industrial and Commecial temperature Grade  
Updated Thermal resistance values for 48-FBGA,44-TSOP II and  
54-TSOP II packages  
Changed t  
value from 16ns to 15ns  
CW  
Sales, Solutions, and Legal Information  
Worldwide Sales and Design Support  
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office  
closest to you, visit us at cypress.com/sales.  
Products  
PSoC  
PSoC Solutions  
General  
psoc.cypress.com/solutions  
psoc.cypress.com/low-power  
psoc.cypress.com/precision-analog  
psoc.cypress.com/lcd-drive  
psoc.cypress.com/can  
psoc.cypress.com  
clocks.cypress.com  
wireless.cypress.com  
memory.cypress.com  
image.cypress.com  
Low Power/Low Voltage  
Precision Analog  
LCD Drive  
Clocks & Buffers  
Wireless  
Memories  
CAN 2.0b  
Image Sensors  
USB  
psoc.cypress.com/usb  
© Cypress Semiconductor Corporation, 2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any  
circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical,  
life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical  
components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems  
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),  
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,  
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress  
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without  
the express written permission of Cypress.  
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES  
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not  
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where  
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer  
assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
Use may be limited by and subject to the applicable Cypress software license agreement.  
Document Number: 001-45524 Rev. *A  
Revised June 24, 2008  
Page 20 of 20  
AutoStore and QuantumTrap are registered trademarks of Simtek Corporation. All products and company names mentioned in this document are the trademarks of their respective holders.  

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