Cypress CY7C1231H User Manual

CY7C1231H  
2-Mbit (128K x 18) Flow-Through SRAM  
with NoBL™ Architecture  
Functional Description[1]  
Features  
• Can support up to 133-MHz bus operations with zero  
wait states  
The CY7C1231H is a 3.3V/2.5V, 128K x 18 Synchronous  
Flow-through Burst SRAM designed specifically to support  
unlimited true back-to-back Read/Write operations without the  
insertion of wait states. The CY7C1231H is equipped with the  
advanced No Bus Latency™ (NoBL™) logic required to  
enable consecutive Read/Write operations with data being  
transferred on every clock cycle. This feature dramatically  
improves the throughput of data through the SRAM, especially  
in systems that require frequent Write-Read transitions.  
— Data is transferred on every clock  
• Pin compatible and functionally equivalent to ZBT™  
devices  
• Internally self-timed output buffer control to eliminate  
the need to use OE  
• Registered inputs for flow-through operation  
• Byte Write capability  
All synchronous inputs pass through input registers controlled  
by the rising edge of the clock. The clock input is qualified by  
the Clock Enable (CEN) signal, which when deasserted  
suspends operation and extends the previous clock cycle.  
Maximum access delay from the clock rise is 6.5 ns (133-MHz  
device).  
• 128K x 18 common I/O architecture  
• 3.3V core power supply  
• 3.3V/2.5V I/O operation  
• Fast clock-to-output times  
Write operations are controlled by the two Byte Write Select  
(BW  
) and a Write Enable (WE) input. All writes are  
— 6.5 ns (133-MHz device)  
[A:B]  
conducted with on-chip synchronous self-timed write circuitry.  
• Clock Enable (CEN) pin to suspend operation  
• Synchronous self-timed write  
• Asynchronous Output Enable  
Three synchronous Chip Enables (CE , CE , CE ) and an  
1
2
3
asynchronous Output Enable (OE) provide for easy bank  
selection and output tri-state control. In order to avoid bus  
contention, the output drivers are synchronously tri-stated  
during the data portion of a write sequence.  
• Offered in JEDEC-standard lead-free 100-pin TQFP  
package  
• Burst Capability—linear or interleaved burst order  
• Low standby power  
Logic Block Diagram  
ADDRESS  
REGISTER  
A0, A1, A  
A1  
A1'  
A0'  
D1  
A0  
Q1  
Q0  
D0  
MODE  
BURST  
LOGIC  
CE  
ADV/LD  
C
CLK  
CEN  
C
WRITE ADDRESS  
REGISTER  
O
U
T
P
U
T
D
A
T
S
E
N
S
ADV/LD  
BWA  
A
B
U
F
MEMORY  
ARRAY  
WRITE  
DRIVERS  
E
WRITE REGISTRY  
AND DATA COHERENCY  
CONTROL LOGIC  
S
T
E
E
R
I
DQs  
DQPA  
DQPB  
BWB  
A
M
P
F
E
R
S
S
WE  
E
N
G
INPUT  
REGISTER  
E
OE  
READ LOGIC  
CE1  
CE2  
CE3  
SLEEP  
CONTROL  
ZZ  
Note:  
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 001-00207 Rev. *B  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised April 26, 2006  
CY7C1231H  
Pin Definitions  
Name  
I/O  
Input-  
Synchronous the CLK. A  
Description  
Address Inputs used to select one of the 128K address locations. Sampled at the rising edge of  
are fed to the two-bit burst counter.  
A , A , A  
0
1
[1:0]  
BW  
Input-  
Byte Write Inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on the  
[A:B]  
Synchronous rising edge of CLK.  
WE  
Input-  
Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This  
Synchronous signal must be asserted LOW to initiate a write sequence.  
ADV/LD  
Input-  
Advance/Load Input. Used to advance the on-chip address counter or load a new address. When  
Synchronous HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address  
can be loaded into the device for an access. After being deselected, ADV/LD should be driven LOW  
in order to load a new address.  
CLK  
Input-Clock Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK  
is only recognized if CEN is active LOW.  
CE  
CE  
CE  
Input-  
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with  
1
2
3
Synchronous CE , and CE to select/deselect the device.  
2
3
Input-  
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with  
Synchronous CE and CE to select/deselect the device.  
1
3
Input-  
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with  
Synchronous CE and CE to select/deselect the device.  
1
2
OE  
Input-  
Output Enable, asynchronous input, active LOW. Combined with the synchronous logic block  
Asynchronous inside the device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave  
as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. OE is masked  
during the data portion of a write sequence, during the first clock when emerging from a deselected  
state, when the device has been deselected.  
CEN  
ZZ  
Input-  
Clock Enable Input, active LOW. When asserted LOW the Clock signal is recognized by the SRAM.  
Synchronous When deasserted HIGH the Clock signal is masked. Since deasserting CEN does not deselect the  
device, CEN can be used to extend the previous cycle when required.  
Input-  
ZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition  
Asynchronous with data integrity preserved. During normal operation, this pin has to be low or left floating. ZZ pin has  
an internal pull-down.  
DQ  
I/O-  
Bidirectional Data I/O Lines. As inputs, they feed into an on-chip data register that is triggered by  
s
Synchronous the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified  
by address during the clock rise of the read cycle. The direction of the pins is controlled by OE and  
the internal control logic. When OE is asserted LOW, the pins can behave as outputs. When HIGH,  
DQ and DQP  
are placed in a tri-state condition. The outputs are automatically tri-stated during  
s
[A:B]  
the data portion of a write sequence, during the first clock when emerging from a deselected state,  
and when the device is deselected, regardless of the state of OE.  
DQP  
I/O-  
Bidirectional Data Parity I/O Lines. Functionally, these signals are identical to DQ . During write  
[A:B]  
s
Synchronous sequences, DQP  
is controlled by BW correspondingly.  
[A:B]  
x
Mode  
Input  
Strap Pin  
Mode Input. Selects the burst order of the device. When tied to Gnd selects linear burst sequence. When  
tied to V or left floating selects interleaved burst sequence.  
DD  
V
V
Power Supply Power supply inputs to the core of the device.  
DD  
I/O Power Power supply for the I/O circuitry.  
Supply  
DDQ  
V
Ground  
Ground for the device.  
SS  
NC  
No Connects. Not Internally connected to the die. 4M, 9M, 18M, 36M, 72M, 144M, 288M, 576M, and  
1G are address expansion pins and are not internally connected to the die.  
Document #: 001-00207 Rev. *B  
Page 3 of 12  
CY7C1231H  
Single Write Accesses  
Write accesses are initiated when the following conditions are  
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE , CE ,  
Functional Overview  
The CY7C1231H is a synchronous flow-through burst SRAM  
designed specifically to eliminate wait states during  
Write-Read transitions. All synchronous inputs pass through  
input registers controlled by the rising edge of the clock. The  
clock signal is qualified with the Clock Enable input signal  
(CEN). If CEN is HIGH, the clock signal is not recognized and  
all internal states are maintained. All synchronous operations  
are qualified with CEN. Maximum access delay from the clock  
1
2
and CE are ALL asserted active, and (3) the Write signal WE  
3
is asserted LOW. The address presented to the address bus  
is loaded into the Address Register. The write signals are  
latched into the Control Logic block. The data lines are  
automatically tri-stated regardless of the state of the OE input  
signal. This allows the external logic to present the data on  
DQs and DQP  
.
[A:B]  
rise (t  
) is 6.5 ns (133-MHz device).  
CDV  
On the next clock rise the data presented to DQs and DQP  
[A:B]  
Accesses can be initiated by asserting all three Chip Enables  
(CE , CE , CE ) active at the rising edge of the clock. If Clock  
(or a subset for Byte Write operations, see Truth Table for  
details) inputs is latched into the device and the write is  
complete. Additional accesses (Read/Write/Deselect) can be  
initiated on this cycle.  
1
2
3
Enable (CEN) is active LOW and ADV/LD is asserted LOW,  
the address presented to the device will be latched. The  
access can either be a read or write operation, depending on  
the status of the Write Enable (WE). BW  
conduct Byte Write operations.  
The data written during the Write operation is controlled by  
can be used to  
[A:B]  
BW  
signals. The CY7C1231H provides Byte Write  
[A:B]  
capability that is described in the Truth Table. Asserting the  
Write Enable input (WE) with the selected Byte Write Select  
input will selectively write to only the desired bytes. Bytes not  
selected during a Byte Write operation will remain unaltered.  
A synchronous self-timed write mechanism has been provided  
to simplify the Write operations. Byte Write capability has been  
included in order to greatly simplify Read/Modify/Write  
sequences, which can be reduced to simple byte write opera-  
tions.  
Write operations are qualified by the Write Enable (WE). All  
writes are simplified with on-chip synchronous self-timed write  
circuitry.  
Three synchronous Chip Enables (CE , CE , CE ) and an  
1
2
3
asynchronous Output Enable (OE) simplify depth expansion.  
All operations (Reads, Writes, and Deselects) are pipelined.  
ADV/LD should be driven LOW once the device has been  
deselected in order to load a new address for the next  
operation.  
Because the CY7C1231H is a common I/O device, data  
should not be driven into the device while the outputs are  
active. The Output Enable (OE) can be deasserted HIGH  
Single Read Accesses  
A read access is initiated when the following conditions are  
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE , CE ,  
before presenting data to the DQs and DQP  
inputs. Doing  
[A:B]  
so will tri-state the output drivers. As a safety precaution, DQs  
1
2
and CE are ALL asserted active, (3) the Write Enable input  
and DQP .are automatically tri-stated during the data  
3
[A:B]  
signal WE is deasserted HIGH, and 4) ADV/LD is asserted  
LOW. The address presented to the address inputs is latched  
into the Address Register and presented to the memory array  
and control logic. The control logic determines that a read  
access is in progress and allows the requested data to  
propagate to the output buffers. The data is available within 6.5  
ns (133-MHz device) provided OE is active LOW. After the first  
clock of the read access, the output buffers are controlled by  
OE and the internal control logic. OE must be driven LOW in  
order for the device to drive out the requested data. On the  
subsequent clock, another operation (Read/Write/Deselect)  
can be initiated. When the SRAM is deselected at clock rise  
by one of the chip enable signals, its output will be tri-stated  
immediately.  
portion of a write cycle, regardless of the state of OE.  
Burst Write Accesses  
The CY7C1231H has an on-chip burst counter that allows the  
user the ability to supply a single address and conduct up to  
four Write operations without reasserting the address inputs.  
ADV/LD must be driven LOW in order to load the initial  
address, as described in the Single Write Access section  
above. When ADV/LD is driven HIGH on the subsequent clock  
rise, the Chip Enables (CE , CE , and CE ) and WE inputs are  
1
2
3
ignored and the burst counter is incremented. The correct  
BW inputs must be driven in each cycle of the burst write,  
[A:B]  
in order to write the correct bytes of data.  
Sleep Mode  
Burst Read Accesses  
The ZZ input pin is an asynchronous input. Asserting ZZ  
places the SRAM in a power conservation “sleep” mode. Two  
clock cycles are required to enter into or exit from this “sleep”  
mode. While in this mode, data integrity is guaranteed.  
Accesses pending when entering the “sleep” mode are not  
considered valid nor is the completion of the operation  
guaranteed. The device must be deselected prior to entering  
the “sleep” mode. CE1, CE2, and CE3, must remain inactive for  
The CY7C1231H has an on-chip burst counter that allows the  
user the ability to supply a single address and conduct up to  
four Reads without reasserting the address inputs. ADV/LD  
must be driven LOW in order to load a new address into the  
SRAM, as described in the Single Read Access section above.  
The sequence of the burst counter is determined by the MODE  
input signal. A LOW input on MODE selects a linear burst  
mode, a HIGH selects an interleaved burst sequence. Both  
burst counters use A0 and A1 in the burst sequence, and will  
wrap around when incremented sufficiently. A HIGH input on  
ADV/LD will increment the internal burst counter regardless of  
the state of Chip Enable inputs or WE. WE is latched at the  
beginning of a burst cycle. Therefore, the type of access (Read  
or Write) is maintained throughout the burst sequence.  
the duration of t  
after the ZZ input returns LOW.  
ZZREC  
Document #: 001-00207 Rev. *B  
Page 4 of 12  
CY7C1231H  
Interleaved Burst Sequence  
Linear Burst Address Table (MODE = GND)  
First  
Second  
Third  
Fourth  
Address  
First  
Address  
A1, A0  
Second  
Address  
A1, A0  
Third  
Address  
A1, A0  
Fourth  
Address  
A1, A0  
Address  
Address  
Address  
A1, A0  
10  
A1, A0  
00  
A1, A0  
01  
A1, A0  
11  
00  
01  
10  
11  
01  
10  
11  
00  
10  
11  
00  
01  
11  
00  
01  
10  
01  
00  
11  
10  
10  
11  
00  
01  
11  
10  
01  
00  
ZZ Mode Electrical Characteristics  
Parameter  
Description  
Sleep mode standby current  
Device operation to ZZ  
ZZ recovery time  
Test Conditions  
Min.  
Max.  
40  
Unit  
mA  
ns  
I
t
t
t
t
ZZ > V 0.2V  
DD  
ZZ > V 0.2V  
ZZ < 0.2V  
DDZZ  
2t  
ZZS  
DD  
CYC  
2t  
ns  
ZZREC  
ZZI  
CYC  
ZZ Active to sleep current  
ZZ inactive to exit sleep current  
This parameter is sampled  
This parameter is sampled  
2t  
ns  
CYC  
0
ns  
RZZI  
Truth Table[2, 3, 4, 5, 6, 7, 8]  
Address  
Used CE CE2 CE ZZ ADV/LD WE BW OE CEN CLK  
Operation  
Deselect Cycle  
DQ  
1
3
X
None  
None  
H
X
X
X
L
X
X
L
X
H
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
X
X
X
X
H
X
H
X
L
X
X
X
X
X
X
X
X
L
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
H
X
L->H  
L->H  
L->H  
L->H  
Tri-State  
Tri-State  
Tri-State  
Tri-State  
Deselect Cycle  
Deselect Cycle  
None  
L
Continue Deselect Cycle  
READ Cycle (Begin Burst)  
READ Cycle (Continue Burst)  
NOP/DUMMY READ (Begin Burst)  
DUMMY READ (Continue Burst)  
WRITE Cycle (Begin Burst)  
WRITE Cycle (Continue Burst)  
NOP/WRITE ABORT (Begin Burst)  
WRITE ABORT (Continue Burst)  
IGNORE CLOCK EDGE (Stall)  
Sleep MODE  
None  
X
H
X
H
X
H
X
H
X
X
X
H
L
External  
Next  
L->H Data Out (Q)  
L->H Data Out (Q)  
X
L
X
L
H
L
L
External  
Next  
H
H
X
X
X
X
X
X
L->H  
L->H  
Tri-State  
Tri-State  
X
L
X
L
H
L
External  
Next  
L->H Data In (D)  
L->H Data In (D)  
X
L
X
L
H
L
X
L
L
None  
H
H
X
X
L->H  
L->H  
L->H  
X
Tri-State  
Tri-State  
Next  
X
X
X
X
X
X
H
X
X
X
X
X
Current  
None  
Tri-State  
Truth Table for Read/Write [2, 3]  
WE  
H
L
BW  
BW  
Function  
A
B
Read  
X
H
H
H
L
X
H
H
H
L
Write – No bytes written  
Write Byte A – (DQ and DQP )  
L
A
A
Write Byte B – (DQ and DQP )  
L
B
B
Write All Bytes  
L
Notes:  
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW. BWx = 0 signifies at least one Byte Write Select is active, BWx = Valid signifies that the desired byte write  
selects are asserted, see Truth Table for details.  
3. Write is defined by BW  
, and WE. See Truth Table for Read/Write.  
[A:B]  
4. When a write cycle is detected, all I/Os are tri-stated, even during byte writes.  
5. The DQs and DQP pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.  
[A:B]  
6. CEN = H, inserts wait states.  
7. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE.  
8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQP  
= Tri-state when  
[A:B]  
OE is inactive or when the device is deselected, and DQs and DQP  
= data when OE is active.  
[A:B]  
Document #: 001-00207 Rev. *B  
Page 5 of 12  
CY7C1231H  
DC Input Voltage ................................... –0.5V to V + 0.5V  
Maximum Ratings  
DD  
Current into Outputs (LOW)......................................... 20 mA  
(Above which the useful life may be impaired. For user guide-  
lines, not tested.)  
Static Discharge Voltage.......................................... > 2001V  
(per MIL-STD-883, Method 3015)  
Storage Temperature .................................65°C to +150°C  
Latch-up Current.................................................... > 200 mA  
Ambient Temperature with  
Power Applied.............................................55°C to +125°C  
Operating Range  
Supply Voltage on V Relative to GND........ –0.5V to +4.6V  
DD  
Ambient  
Supply Voltage on V  
Relative to GND ......0.5V to +V  
Range  
Commercial  
Industrial  
Temperature (T )  
V
V
DDQ  
DDQ  
DD  
A
DD  
DC Voltage Applied to Outputs  
in Tri-State........................................... –0.5V to V  
0°C to +70°C  
3.3V –  
5%/+10%  
2.5V – 5% to  
+ 0.5V  
V
DDQ  
DD  
-40°C to +85°C  
[9,10]  
Electrical Characteristics Over the Operating Range  
Parameter  
Description  
Power Supply Voltage  
I/O Supply Voltage  
Test Conditions  
Min.  
Max.  
Unit  
V
3.135  
3.135  
2.375  
2.4  
3.6  
V
V
V
V
DD  
V
V
V
V
V
I
for 3.3V I/O  
for 2.5V I/O  
V
DD  
DDQ  
2.625  
Output HIGH Voltage  
Output LOW Voltage  
Input HIGH Voltage  
for 3.3V I/O, I = –4.0 mA  
OH  
OH  
OL  
IH  
for 2.5V I/O, I = –1.0 mA  
2.0  
OH  
for 3.3V I/O, I = 8.0 mA  
0.4  
0.4  
V
V
OL  
for 2.5V I/O, I = 1.0 mA  
OL  
for 3.3V I/O  
for 2.5V I/O  
for 3.3V I/O  
for 2.5V I/O  
2.0  
1.7  
V
V
+ 0.3V  
+ 0.3V  
0.8  
DD  
DD  
[9]  
Input LOW Voltage  
–0.3  
–0.3  
–5  
V
IL  
0.7  
Input Leakage Current GND V V  
except ZZ and MODE  
5
µA  
X
I
DDQ  
Input Current of MODE Input = V  
–30  
–5  
µA  
µA  
µA  
µA  
µA  
mA  
SS  
Input = V  
5
DD  
Input Current of ZZ  
Input = V  
Input = V  
SS  
DD  
30  
5
I
I
Output Leakage Current GND V V  
, Output Disabled  
–5  
OZ  
I
DDQ  
V
Operating Supply  
V = Max., I  
DD  
= 0 mA,  
7.5-ns cycle, 133 MHz  
225  
DD  
DD  
OUT  
Current  
f = f  
= 1/t  
MAX CYC  
I
I
I
I
Automatic CE  
Power-down  
Current—TTL Inputs  
V
= Max, DeviceDeselected, 7.5-ns cycle, 133 MHz  
DD  
90  
mA  
mA  
mA  
mA  
SB1  
V
V or V V , f = f  
,
IN  
IH  
IN  
IL  
MAX  
inputs switching  
Automatic CE  
Power-down  
Current—CMOS Inputs f = 0, inputs static  
V = Max, DeviceDeselected, 7.5-ns cycle, 133 MHz  
DD  
40  
75  
45  
SB2  
SB3  
SB4  
V
V – 0.3V or V 0.3V,  
IN  
DD  
IN  
Automatic CE  
Power-down  
Current—CMOS Inputs f = f  
V = Max, DeviceDeselected, 7.5-ns cycle, 133 MHz  
DD  
V
V  
MAX  
– 0.3V or V 0.3V,  
IN  
DDQ  
IN  
, inputs switching  
Automatic CE  
Power-down  
Current—TTL Inputs  
V = Max, DeviceDeselected, 7.5-ns cycle, 133 MHz  
DD  
V
V – 0.3V or V 0.3V,  
IN  
DD IN  
f = 0, inputs static  
Notes:  
9. Overshoot: V (AC) < V +1.5V (Pulse width less than t  
/2), undershoot: V (AC)> –2V (Pulse width less than t /2).  
CYC  
DD  
CYC  
IL  
IH  
10. T  
: Assumes a linear ramp from 0V to V (min.) within 200 ms. During this time V < V and V  
< V  
.
Power-up  
DD  
IH  
DD  
DDQ  
DD  
Document #: 001-00207 Rev. *B  
Page 6 of 12  
CY7C1231H  
Capacitance[11]  
100 TQFP  
Max.  
Parameter  
Description  
Input Capacitance  
Clock Input Capacitance  
I/O Capacitance  
Test Conditions  
T = 25°C, f = 1 MHz,  
Unit  
pF  
C
C
C
5
5
5
IN  
A
V
= 3.3V  
= 2.5V  
DD  
pF  
CLOCK  
I/O  
V
DDQ  
pF  
Thermal Resistance[11]  
100 TQFP  
Package  
Parameters  
Description  
Test Conditions  
Unit  
Θ
Thermal Resistance  
(Junction to Ambient)  
Test conditions follow standard test methods and  
procedures for measuring thermal impedance,  
per EIA/JESD51  
30.32  
°C/W  
JA  
Θ
Thermal Resistance  
(Junction to Case)  
6.85  
°C/W  
JC  
AC Test Loads and Waveforms  
3.3V I/O Test Load  
R = 317Ω  
3.3V  
OUTPUT  
ALL INPUT PULSES  
90%  
VDDQ  
GND  
OUTPUT  
90%  
10%  
Z = 50Ω  
0
10%  
R = 50Ω  
L
5 pF  
R = 351Ω  
1 ns  
1 ns  
INCLUDING  
JIG AND  
SCOPE  
V = 1.5V  
L
(a)  
(b)  
(c)  
2.5V I/O Test Load  
R = 1667Ω  
2.5V  
OUTPUT  
R = 50Ω  
OUTPUT  
ALL INPUT PULSES  
90%  
VDDQ  
GND  
90%  
10%  
Z = 50Ω  
0
10%  
L
5 pF  
R =1538Ω  
1 ns  
1 ns  
INCLUDING  
V = 1.25V  
T
JIG AND  
SCOPE  
(a)  
(b)  
(c)  
Note:  
11. Tested initially and after any design or process change that may affect these parameters.  
Document #: 001-00207 Rev. *B  
Page 7 of 12  
CY7C1231H  
[12, 13]  
Switching Characteristics Over the Operating Range  
-133  
Parameter  
Description  
Min.  
Max.  
Unit  
[14]  
t
V
(Typical) to the first Access  
1
ms  
POWER  
DD  
Clock  
t
t
t
Clock Cycle Time  
Clock HIGH  
7.5  
2.5  
2.5  
ns  
ns  
ns  
CYC  
CH  
Clock LOW  
CL  
Output Times  
t
t
t
t
t
t
t
Data Output Valid after CLK Rise  
Data Output Hold after CLK Rise  
6.5  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
CDV  
DOH  
CLZ  
2.0  
0
[15, 16, 17]  
Clock to Low-Z  
[15, 16, 17]  
Clock to High-Z  
3.5  
3.5  
CHZ  
OEV  
OELZ  
OEHZ  
OE LOW to Output Valid  
[15, 16, 17]  
OE LOW to Output Low-Z  
0
[15, 16, 17]  
OE HIGH to Output High-Z  
3.5  
Set-up Times  
t
Address Set-up before CLK Rise  
ADV/LD Set-up before CLK Rise  
1.5  
ns  
AS  
t
t
t
t
t
1.5  
1.5  
1.5  
1.5  
1.5  
ns  
ns  
ns  
ns  
ns  
ALS  
WES  
CENS  
DS  
WE, BW  
Set-up before CLK Rise  
[A:B]  
CEN Set-up before CLK Rise  
Data Input Set-up before CLK Rise  
Chip Enable Set-up before CLK Rise  
CES  
Hold Times  
t
Address Hold after CLK Rise  
ADV/LD Hold after CLK Rise  
0.5  
ns  
AH  
t
t
t
t
t
0.5  
0.5  
0.5  
0.5  
0.5  
ns  
ns  
ns  
ns  
ns  
ALH  
WEH  
CENH  
DH  
WE, BW  
Hold after CLK Rise  
[A:B]  
CEN Hold after CLK Rise  
Data Input Hold after CLK Rise  
Chip Enable Hold after CLK Rise  
CEH  
Notes:  
12. Timing reference level is 1.5V when V  
= 3.3V and 1.25V when V  
= 2.5V.  
DDQ  
DDQ  
13. Test conditions shown in (a) of AC Test Loads, unless otherwise noted.  
14. This part has a voltage regulator internally; t  
is the time that the power needs to be supplied above V minimum initially before a read or write operation  
POWER  
DD  
can be initiated.  
15. t  
, t  
, t  
, and t  
are specified with AC test conditions shown in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.  
CHZ CLZ OELZ  
OEHZ  
16. At any given voltage and temperature, t  
is less than t  
and t  
is less than t  
to eliminate bus contention between SRAMs when sharing the same  
CLZ  
OEHZ  
OELZ  
CHZ  
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed  
to achieve tri-state prior to Low-Z under the same system conditions.  
17. This parameter is sampled and not 100% tested.  
Document #: 001-00207 Rev. *B  
Page 8 of 12  
CY7C1231H  
Switching Waveforms  
[18, 19, 20]  
Read/Write Waveforms  
t
1
2
3
4
5
6
7
8
9
10  
CYC  
t
CLK  
t
t
t
t
t
CENS  
CES  
CENH  
CEH  
CL  
CH  
CEN  
CE  
ADV/LD  
WE  
BW[A:B]  
A1  
A2  
A4  
A3  
A5  
A6  
A7  
ADDRESS  
DQ  
t
CDV  
t
t
AS  
AH  
t
t
t
t
DOH  
OEV  
CLZ  
CHZ  
D(A1)  
t
D(A2)  
D(A2+1)  
Q(A3)  
Q(A4)  
Q(A4+1)  
D(A5)  
Q(A6)  
D(A7)  
t
OEHZ  
t
DS  
DH  
t
DOH  
t
OELZ  
OE  
COMMAND  
WRITE  
D(A1)  
WRITE  
D(A2)  
BURST  
WRITE  
READ  
Q(A3)  
READ  
Q(A4)  
BURST  
READ  
WRITE  
D(A5)  
READ  
Q(A6)  
WRITE  
D(A7)  
DESELECT  
D(A2+1)  
Q(A4+1)  
DON’T CARE  
UNDEFINED  
Notes:  
For this waveform ZZ is tied LOW.  
18.  
19. When CE is LOW, CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH, CE is HIGH or CE is LOW or CE is HIGH.  
1
2
3
1
2
3
20. Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved). Burst operations are optional.  
Document #: 001-00207 Rev. *B  
Page 9 of 12  
CY7C1231H  
Switching Waveforms (continued)  
[18, 19, 21]  
NOP, STALL and Deselect Cycles  
1
2
3
4
5
6
7
8
9
10  
CLK  
CEN  
CE  
ADV/LD  
WE  
BW[A:B]  
ADDRESS  
A1  
A2  
A3  
A4  
A5  
t
CHZ  
D(A1)  
Q(A2)  
Q(A3)  
D(A4)  
Q(A5)  
DOH  
DQ  
t
COMMAND  
WRITE  
D(A1)  
READ  
Q(A2)  
STALL  
READ  
Q(A3)  
WRITE  
D(A4)  
STALL  
NOP  
READ  
Q(A5)  
DESELECT  
CONTINUE  
DESELECT  
DON’T CARE  
UNDEFINED  
[22, 23]  
ZZ Mode Timing  
CLK  
t
t
ZZ  
ZZREC  
ZZ  
t
ZZI  
I
SUPPLY  
I
DDZZ  
t
RZZI  
ALL INPUTS  
(except ZZ)  
DESELECT or READ Only  
Outputs (Q)  
High-Z  
DON’T CARE  
Notes:  
21. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle.  
22. Device must be deselected when entering ZZ mode. See Truth Table for all possible signal conditions to deselect the device.  
23. I/Os are in tri-state when exiting ZZ sleep mode.  
Document #: 001-00207 Rev. *B  
Page 10 of 12  
CY7C1231H  
Ordering Information  
“Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or  
visit www.cypress.com for actual products offered”.  
Speed  
(MHz)  
Package  
Diagram  
Operating  
Range  
Ordering Code  
Package Type  
133 CY7C1231H-133AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free  
CY7C1231H-133AXI 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free  
Commercial  
Industrial  
Package Diagram  
100-pin TQFP (14 x 20 x 1.4 mm) (51-85050)  
16.00 0.20  
14.00 0.10  
1.40 0.05  
100  
81  
80  
1
0.30 0.08  
0.65  
TYP.  
12° 1°  
(8X)  
SEE DETAIL  
A
30  
51  
31  
50  
0.20 MAX.  
1.60 MAX.  
R 0.08 MIN.  
0.20 MAX.  
0° MIN.  
SEATING PLANE  
STAND-OFF  
0.05 MIN.  
0.15 MAX.  
NOTE:  
1. JEDEC STD REF MS-026  
0.25  
GAUGE PLANE  
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH  
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE  
R 0.08 MIN.  
0.20 MAX.  
BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH  
3. DIMENSIONS IN MILLIMETERS  
0°-7°  
0.60 0.15  
1.00 REF.  
0.20 MIN.  
51-85050-*B  
DETAIL  
A
NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device  
Technology, Inc. All product and company names mentioned in this document are the trademarks of their respective holders.  
Document #: 001-00207 Rev. *B  
Page 11 of 12  
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be  
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its  
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
CY7C1231H  
Document History Page  
Document Title: CY7C1231H 2-Mbit (128K x 18) Flow-Through SRAM with NoBL™ Architecture  
Document Number: 001-00207  
Orig. of  
REV.  
**  
ECN NO. Issue Date Change  
Description of Change  
347377  
428408  
See ECN  
See ECN  
PCI  
New Data Sheet  
Converted from Preliminary to Final.  
*A  
NXR  
Changed address of Cypress Semiconductor Corporation on Page# 1 from  
“3901 North First Street” to “198 Champion Court”  
Removed 100 MHz Speed-bin  
Changed Three-State to Tri-State.  
Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the  
Electrical Characteristics Table.  
Modified test condition from V  
< V to V  
< V  
DDQ  
DD  
DDQ DD  
Replaced Package Name column with Package Diagram in the Ordering  
Information table.  
Updated the Ordering Information Table.  
Replaced Package Diagram of 51-85050 from *A to *B  
*B  
459347  
See ECN  
NXR  
Included 2.5V I/O option  
Updated the Ordering Information table.  
Document #: 001-00207 Rev. *B  
Page 12 of 12  

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