Cypress CY7C1170V18 User Manual

CY7C1166V18, CY7C1177V18  
CY7C1168V18, CY7C1170V18  
18-Mbit DDR-II+ SRAM 2-Word Burst  
Architecture (2.5 Cycle Read Latency)  
Features  
Functional Description  
18 Mbit density (2M x 8, 2M x 9, 1M x 18, 512K x 36)  
300 MHz to 400 MHz clock for high bandwidth  
2-Word burst for reducing address bus frequency  
The CY7C1166V18, CY7C1177V18, CY7C1168V18, and  
CY7C1170V18 are 1.8V Synchronous Pipelined SRAMs  
equipped with DDR-II+ architecture. The DDR-II+ consists of an  
SRAM core with an advanced synchronous peripheral circuitry.  
Addresses for read and write are latched on alternate rising  
edges of the input (K) clock. Write data is registered on the rising  
edges of both K and K. Read data is driven on the rising edges  
of K and K. Each address location is associated with two 8-bit  
words (CY7C1166V18), or 9-bit words (CY7C1177V18), or 18-bit  
words (CY7C1168V18), or 36-bit words (CY7C1170V18) that  
burst sequentially into or out of the device.  
Double Data Rate (DDR) interfaces  
(data transferred at 800 MHz) at 400 MHz  
Read latency of 2.5 clock cycles  
Two input clocks (K and K) for precise DDR timing  
SRAM uses rising edges only  
Asynchronous inputs include output impedance matching input  
Echo clocks (CQ and CQ) simplify data capture in high-speed  
systems  
(ZQ). Synchronous data outputs (Q, sharing the same physical  
pins as the data inputs D) are tightly matched to the two output  
echo clocks CQ/CQ, eliminating the need for separately  
capturing data from each individual DDR SRAM in the system  
design.  
Data valid pin (QVLD) to indicate valid data on the output  
Synchronous internally self-timed writes  
Core V = 1.8V ± 0.1V; IO V  
= 1.4V to V  
DD  
DD  
DDQ  
All synchronous inputs pass through input registers controlled by  
the K or K input clocks. All data outputs pass through output  
registers controlled by the K or K input clocks. Writes are  
conducted with on-chip synchronous self-timed write circuitry.  
HSTL inputs and Variable drive HSTL output buffers  
Available in 165-Ball FBGA package (13 x 15 x 1.4 mm)  
Offered in both Pb-free and non Pb-free packages  
JTAG 1149.1-compatible test access port  
Delay Lock Loop (DLL) for accurate data placement  
Configurations  
With Read Cycle Latency of 2.5 cycles:  
CY7C1166V18 – 2M x 8  
CY7C1177V18 – 2M x 9  
CY7C1168V18 – 1M x 18  
CY7C1170V18 – 512K x 36  
Selection Guide  
Description  
400 MHz  
400  
375 MHz  
375  
333 MHz  
333  
300 MHz  
300  
Unit  
MHz  
mA  
Maximum Operating Frequency  
Maximum Operating Current  
1080  
1020  
920  
850  
Note  
1. The QDR consortium specification for V  
is 1.5V + 0.1V. The Cypress QDR devices exceed the QDR consortium specification and are capable of supporting  
DDQ  
V
= 1.4V to V  
.
DDQ  
DD  
Cypress Semiconductor Corporation  
Document Number: 001-06620 Rev. *D  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised March 06, 2008  
 
CY7C1166V18, CY7C1177V18  
CY7C1168V18, CY7C1170V18  
Logic Block Diagram (CY7C1168V18)  
Write  
Reg  
Write  
Reg  
19  
A
(18:0)  
Address  
Register  
LD  
18  
K
K
Output  
Logic  
Control  
CLK  
Gen.  
R/W  
DOFF  
Read Data Reg.  
36  
CQ  
CQ  
V
18  
REF  
18  
18  
Reg.  
Reg.  
Reg.  
Control  
Logic  
R/W  
DQ  
[17:0]  
18  
BWS  
18  
[1:0]  
QVLD  
Logic Block Diagram (CY7C1170V18)  
Write  
Reg  
Write  
Reg  
18  
A
(17:0)  
Address  
Register  
LD  
36  
K
K
Output  
Logic  
Control  
CLK  
Gen.  
R/W  
DOFF  
Read Data Reg.  
72  
36  
CQ  
CQ  
V
REF  
36  
36  
Reg.  
Reg.  
Reg.  
Control  
Logic  
R/W  
DQ  
[35:0]  
36  
BWS  
36  
[3:0]  
QVLD  
Document Number: 001-06620 Rev. *D  
Page 3 of 27  
CY7C1166V18, CY7C1177V18  
CY7C1168V18, CY7C1170V18  
Pin Configurations  
165-Ball FBGA (13 x 15 x 1.4 mm) Pinout  
CY7C1166V18 (2M x 8)  
1
2
3
A
4
5
6
7
8
9
A
10  
NC/36M  
11  
CQ  
DQ3  
NC  
NC/72M  
NC/144M  
A
B
C
D
CQ  
NC  
R/W  
A
NWS1  
K
K
LD  
A
NC  
NC  
NC  
NC  
NC  
NC  
NC/288M  
NC  
NC  
NC  
NC  
NC  
NC  
NWS0  
A
NC  
NC  
NC  
NC  
NC  
VSS  
VSS  
A
A
VSS  
VSS  
VSS  
VSS  
VSS  
NC  
NC  
NC  
DQ4  
NC  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VSS  
VDD  
VDD  
VDD  
VDD  
VDD  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
NC  
NC  
NC  
NC  
DQ2  
E
F
VDD  
VDD  
VDD  
VDD  
VDD  
VSS  
NC  
NC  
ZQ  
NC  
DQ5  
VDDQ  
NC  
NC  
NC  
G
H
J
VREF  
NC  
VDDQ  
NC  
VREF  
DQ1  
NC  
DOFF  
NC  
NC  
NC  
DQ0  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
K
L
DQ6  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
VSS  
VSS  
VSS  
A
VSS  
A
VSS  
A
VSS  
VSS  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
M
N
P
DQ7  
A
QVLD  
A
A
A
A
A
A
A
TDO  
TCK  
A
A
TMS  
TDI  
R
NC  
CY7C1177V18 (2M x 9)  
1
2
3
A
4
5
NC  
6
K
7
NC/144M  
BWS0  
A
8
9
A
10  
NC/36M  
11  
CQ  
DQ3  
NC  
NC/72M  
A
B
C
D
R/W  
A
CQ  
NC  
NC  
NC  
NC  
NC  
NC  
LD  
A
NC  
NC  
NC  
NC  
NC  
NC  
NC/288M  
K
NC  
NC  
NC  
NC  
NC  
NC  
VSS  
VSS  
A
A
VSS  
VSS  
VSS  
VSS  
VSS  
NC  
NC  
NC  
DQ4  
NC  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VSS  
VDD  
VDD  
VDD  
VDD  
VDD  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
NC  
NC  
NC  
NC  
DQ2  
E
F
VDD  
VDD  
VDD  
VDD  
VDD  
VSS  
NC  
NC  
ZQ  
NC  
DQ5  
VDDQ  
NC  
NC  
NC  
G
H
J
VREF  
NC  
VDDQ  
NC  
VREF  
DQ1  
NC  
DOFF  
NC  
NC  
NC  
DQ0  
NC  
NC  
NC  
NC  
NC  
K
L
DQ6  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
VSS  
VSS  
VSS  
A
VSS  
A
VSS  
A
VSS  
VSS  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
M
N
P
DQ7  
A
QVLD  
A
DQ8  
A
A
A
A
A
A
TDO  
TCK  
A
A
TMS  
TDI  
R
NC  
Document Number: 001-06620 Rev. *D  
Page 4 of 27  
CY7C1166V18, CY7C1177V18  
CY7C1168V18, CY7C1170V18  
Pin Configurations (continued)  
165-Ball FBGA (13 x 15 x 1.4 mm) Pinout  
CY7C1168V18 (1M x 18)  
1
2
3
A
4
5
6
K
7
8
9
A
10  
NC/36M  
11  
CQ  
DQ8  
NC  
NC/72M  
NC/144M  
A
B
C
D
CQ  
NC  
R/W  
A
BWS1  
NC/288M  
A
LD  
A
DQ9  
NC  
NC  
NC  
K
NC  
NC  
NC  
NC  
DQ7  
NC  
BWS0  
A
NC  
NC  
NC  
NC  
NC  
VSS  
VSS  
NC  
VSS  
VSS  
VSS  
NC  
DQ10  
VSS  
VSS  
NC  
NC  
DQ12  
NC  
DQ11  
NC  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VSS  
VDD  
VDD  
VDD  
VDD  
VDD  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
NC  
NC  
NC  
NC  
DQ6  
E
F
VDD  
VDD  
VDD  
VDD  
VDD  
VSS  
DQ5  
NC  
DQ13  
VDDQ  
NC  
NC  
NC  
G
H
J
VREF  
NC  
VDDQ  
NC  
VREF  
DQ4  
NC  
ZQ  
DOFF  
NC  
NC  
NC  
NC  
NC  
DQ14  
NC  
NC  
DQ3  
DQ2  
K
L
DQ15  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
VSS  
VSS  
VSS  
A
VSS  
A
VSS  
A
VSS  
VSS  
NC  
NC  
NC  
DQ1  
NC  
NC  
NC  
M
N
P
DQ16  
DQ17  
A
QVLD  
A
NC  
DQ0  
A
A
A
A
A
NC  
A
TDO  
TCK  
A
A
TMS  
TDI  
R
CY7C1170V18 (512K x 36)  
1
2
3
4
5
6
K
7
8
9
A
10  
NC/72M  
11  
CQ  
NC/144M NC/36M  
A
B
C
D
R/W  
A
BWS2  
BWS3  
A
LD  
A
CQ  
NC  
BWS1  
BWS0  
A
DQ27  
NC  
DQ18  
DQ28  
DQ19  
K
NC  
NC  
NC  
NC  
DQ17  
NC  
DQ8  
DQ7  
DQ16  
NC  
NC  
NC  
NC  
NC  
VSS  
VSS  
NC  
VSS  
VSS  
VSS  
DQ29  
VSS  
VSS  
NC  
DQ30  
DQ31  
VREF  
NC  
DQ20  
DQ21  
DQ22  
VDDQ  
DQ32  
DQ23  
DQ24  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VSS  
VDD  
VDD  
VDD  
VDD  
VDD  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
NC  
NC  
DQ15  
NC  
DQ6  
E
F
VDD  
VDD  
VDD  
VDD  
VDD  
VSS  
DQ5  
DQ14  
ZQ  
NC  
NC  
G
H
J
VDDQ  
NC  
VREF  
DQ13  
DQ12  
NC  
DOFF  
NC  
DQ4  
DQ3  
DQ2  
NC  
NC  
NC  
NC  
K
L
DQ33  
NC  
NC  
NC  
NC  
NC  
DQ35  
NC  
DQ34  
DQ25  
DQ26  
VSS  
VSS  
VSS  
A
VSS  
A
VSS  
A
VSS  
VSS  
NC  
NC  
NC  
DQ11  
NC  
DQ1  
DQ10  
DQ0  
M
N
P
A
QVLD  
A
DQ9  
A
A
A
A
A
A
TDO  
TCK  
A
NC  
A
TMS  
TDI  
R
Document Number: 001-06620 Rev. *D  
Page 5 of 27  
CY7C1166V18, CY7C1177V18  
CY7C1168V18, CY7C1170V18  
Pin Definitions  
Pin Name  
IO  
Pin Description  
DQ  
Input Output- Data Input Output Signals. Inputs are sampled on the rising edge of K and K clocks during valid  
Synchronous write operations. These pins drive out the requested data when a read operation is active. Valid data  
is driven out on the rising edge of both the K and K clocks during read operations. When read access  
is deselected, Q[x:0] are automatically tri-stated.  
[x:0]  
CY7C1166V18 DQ  
[7:0]  
CY7C1177V18 DQ  
[8:0]  
CY7C1168V18 DQ  
CY7C1170V18 DQ  
[17:0]  
[35:0]  
LD  
Input-  
Synchronous Load. This input is brought LOW when a bus cycle sequence is to be defined. This  
Synchronous definition includes address and read/write direction. All transactions operate on a burst of two data.  
LD must meet the setup and hold times around edge of K. LD must meet the setup and hold times  
around edge of K.  
,
1
Input-  
Synchronous and K clocks during write operations. It is used to select the nibble that is written into the device  
NWS controls D and NWS controls D  
Nibble Write Select 0, 1 Active LOW.(CY7C1166V18 Only) Sampled on the rising edge of the K  
NWS , NWS  
0
.
[7:4]  
0
[3:0]  
1
All the Nibble Write Selects are sampled on the same edge as the data. Deselecting a Nibble Write  
Select ignores the corresponding nibble of data and not written into the device.  
BWS BWS  
Input-  
Byte Write Select 0, 1, 2, and 3 Active LOW. Sampled on the rising edge of the K and K clocks  
,
0
,
1
Synchronous during Write operations. It is used to select the byte that is written into the device during the current  
portion of the write operations. Bytes not written remain unaltered.  
CY7C1177V18 BWS controls D  
BWS , BWS  
2
3
0
[8:0]  
CY7C1168V18 BWS controls D  
and BWS controls D  
0
[8:0],  
1
[17:9].  
, BWS controls D  
CY7C1170V18 BWS controls D  
, BWS controls D  
, and BWS  
[26:18] 3  
0
[8:0]  
1
[17:9]  
2
controls D  
.
[35:27]  
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select  
ignores the corresponding byte of data and not written into the device.  
A
Input-  
Address Inputs. Sampled on the rising edge of the K clock during active read and write operations.  
Synchronous These address inputs are multiplexed for both read and write operations. Internally, the device is  
organized as 2M x 8 (two arrays each of1M x 8) for CY7C1166V18, 2M x 9 (two arrays each of 1M  
x 9) for CY7C1177V18, 1M x 18 (two arrays each of 512K x 18) for CY7C1168V18, and 512K x 36  
(two arrays each of 256K x 18) for CY7C1170V18. All the address inputs are ignored when the  
appropriate port is deselected.  
R/W  
Input-  
Synchronous  
Synchronous Read/Write Input. When LD is LOW, this input designates the access type (read  
when R/W is HIGH, write when R/W is LOW) for loaded address. R/W must meet the setup and hold  
times around edge of K.  
QVLD  
K
Valid Output Valid Output Indicator. The Q Valid indicates valid output data. QVLD is edge aligned with CQ and  
Indicator  
CQ.  
Input-  
Clock  
Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device  
and to drive out data through Q  
edge of K.  
when in single clock mode. All accesses are initiated on the rising  
[x:0]  
K
Input-  
Clock  
Negative Input Clock Input. K is used to capture synchronous inputs being presented to the device  
and to drive out data through Q when in single clock mode.  
[x:0]  
CQ  
Clock Output Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input  
clock (K) of the DDR-II+. The timings for the echo clocks are shown in the “Switching Characteristics”  
CQ  
Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input  
clock (K) of the DDR-II+. The timings for the echo clocks are shown in the “Switching Characteristics”  
Clock Output  
Document Number: 001-06620 Rev. *D  
Page 6 of 27  
CY7C1166V18, CY7C1177V18  
CY7C1168V18, CY7C1170V18  
Pin Definitions (continued)  
Pin Name  
ZQ  
IO  
Pin Description  
Input  
Output Impedance Matching Input. This input is used to tune the device outputs to the system data  
bus impedance. CQ, CQ, and Q output impedance are set to 0.2 x RQ, where RQ is a resistor  
[x:0]  
connected between ZQ and ground. Alternatively, this pin can be connected directly to V  
, which  
DDQ  
enables the minimum impedance mode. This pin cannot be connected directly to GND or left uncon-  
nected.  
DOFF  
Input  
DLL Turn Off Active LOW. Connecting this pin to ground turns off the DLL inside the device. The  
timings in the DLL turned off operation is different from those listed in this data sheet. For normal  
operation, this pin can be connected to a pull up through a 10KΩ or less pull up resistor. The device  
behaves in DDR-I mode when the DLL is turned off. In this mode, the device can be operated at a  
frequency of up to 167 MHz with DDR-I timing.  
TDO  
Output  
Input  
Input  
Input  
N/A  
TDO for JTAG.  
TCK  
TCK Pin for JTAG.  
TDI  
TDI Pin for JTAG.  
TMS  
TMS Pin for JTAG.  
NC  
Not Connected to the Die. Tie to any voltage level.  
Not Connected to the Die. Tie to any voltage level.  
Not Connected to the Die. Tie to any voltage level.  
Not Connected to the Die. Tie to any voltage level.  
Not Connected to the Die. Tie to any voltage level.  
Reference Voltage Input. Static input used to set the reference level for HSTL inputs, outputs, and  
NC/36M  
NC/72M  
NC/144M  
NC/288M  
N/A  
N/A  
N/A  
N/A  
V
Input-  
REF  
Reference AC measurement points.  
V
V
V
Power Supply Power Supply Inputs to the Core of the Device.  
DD  
Ground  
Ground for the Device.  
SS  
Power Supply Power Supply Inputs for the Outputs of the Device.  
DDQ  
Document Number: 001-06620 Rev. *D  
Page 7 of 27  
CY7C1166V18, CY7C1177V18  
CY7C1168V18, CY7C1170V18  
Byte Write Operations  
Functional Overview  
Byte Write operations are supported by the CY7C1168V18. A  
Write operation is initiated as described in the Write Operations  
The CY7C1166V18, CY7C1177V18, CY7C1168V18, and  
CY7C1170V18 are synchronous pipelined Burst SRAMs  
equipped with a DDR interface.  
section. The bytes that are written are determined by BWS and  
0
BWS which are sampled with each set of 18-bit data word.  
1
Accesses are initiated on the rising edge of the positive input  
clock (K). All synchronous input and output timing are referenced  
to the rising edge of the Input clocks (K/K).  
Asserting the appropriate Byte Write Select input during the data  
portion of a write enables the data being presented to be latched  
and written into the device. Deasserting the Byte Write Select  
input during the data portion of a write enables the data stored in  
the device for that byte to remain unaltered. This feature can be  
used to simplify read/modify/write operations to a Byte Write  
operation.  
All synchronous data inputs (D  
) pass through input registers  
[x:0]  
controlled by the rising edge of the input clocks (K and K). All  
synchronous data outputs (Q ) pass through output registers  
[x:0]  
controlled by the rising edge of the input clocks (K and K) also.  
All synchronous control (R/W, LD, BWS ) inputs pass through  
input registers controlled by the rising edge of the input clock  
(K/K).  
Double Data Rate Operation  
[0:X]  
The CY7C1168V18 enables high-performance operation  
through high clock frequencies (achieved through pipelining) and  
double data rate mode of operation. The CY7C1168V18 requires  
two No Operation (NOP) cycle when transitioning from a read to  
a write cycle. At higher frequencies, some applications may  
require a third NOP cycle to avoid contention.  
CY7C1168V18 is described in the following sections. The same  
basic descriptions apply to CY7C1166V18, CY7C1177V18, and  
CY7C1170V18.  
Read Operations  
If a read occurs after a write cycle, then the address and data for  
the write are stored in registers. The write information must be  
stored because the SRAM cannot perform the last word write to  
the array without conflicting with the read. The data stays in this  
register until the next write cycle occurs. On the first write cycle  
after the read(s), the stored data from the earlier write is written  
into the SRAM array. This is called a Posted Write.  
The CY7C1168V18 is organized internally as a single array of  
1M x 18. Accesses are completed in a burst of two sequential  
18-bit data words. Read operations are initiated by asserting  
R/W HIGH and LD LOW at the rising edge of the positive input  
clock (K). The address presented to address inputs is stored in  
the read address register. Following the next two K clock rise, the  
corresponding 18-bit word of data from this address location is  
If a read is performed on the same address on which a write is  
performed in the previous cycle, the SRAM reads out the most  
current data. The SRAM does this by bypassing the memory  
array and reading the data from the registers.  
driven onto the Q  
using K as the output timing reference. On  
[17:0]  
the subsequent rising edge of K the next 18-bit data word from  
the address location generated by the burst counter is driven  
onto the Q  
. The requested data is valid 0.45 ns from the  
[17:0]  
rising edge of the input clock (K/K). In order to maintain the  
internal logic, each read access must be allowed to complete.  
Read accesses can be initiated on every rising edge of the  
positive input clock (K).  
Depth Expansion  
Depth expansion requires replicating the LD control signal for  
each bank. All other control signals can be common between  
banks as appropriate.  
When read access is deselected, the CY7C1168V18 first  
completes the pending read transactions. Synchronous internal  
circuitry automatically tri-states the outputs following the next  
rising edge of the negative Input clock (K). This enables for a  
seamless transition between devices without the insertion of wait  
states in a depth expanded memory.  
Programmable Impedance  
An external resistor, RQ, must be connected between the ZQ pin  
on the SRAM and V to enable the SRAM to adjust its output  
SS  
driver impedance. The value of RQ must be 5x the value of the  
intended line impedance driven by the SRAM. The allowable  
range of RQ to guarantee impedance matching with a tolerance  
of ±15% is between 175Ω and 350Ω, with V  
output impedance is adjusted every 1024 cycles upon power up  
to account for drifts in supply voltage and temperature.  
Write Operations  
= 1.5V. The  
DDQ  
Write operations are initiated by asserting R/W LOW and LD  
LOW at the rising edge of the positive input clock (K). The  
address presented to address inputs is stored in the write  
address register. On the following K clock rise the data presented  
Echo Clocks  
to D  
is latched and stored into the 18-bit Write Data register  
[17:0]  
Echo clocks are provided on the DDR-II+ to simplify data capture  
on high-speed systems. Two echo clocks are generated by the  
DDR-II+. CQ is referenced with respect to K and CQ is refer-  
enced with respect to K. These are free-running clocks and are  
synchronized to the input clock of the DDR-II+. The timings for  
the echo clocks are shown in the “Switching Characteristics” on  
provided BWS  
are both asserted active. On the subsequent  
[1:0]  
rising edge of the Negative Input Clock (K) the information  
presented to D is also stored into the Write Data register  
provided BWS  
is then written into the memory array at the specified location.  
Write accesses can be initiated on every rising edge of the  
positive input clock (K). This pipelines the data flow such that 18  
bits of data can be transferred into the device on every rising  
edge of the input clocks (K and K).  
[17:0]  
are both asserted active. The 36 bits of data  
[1:0]  
Valid Data Indicator (QVLD)  
QVLD is provided on the DDR-II+ to simplify data capture on high  
speed systems. The QVLD is generated by the DDR-II+ device  
along with data output. This signal is also edge-aligned with the  
When write access is deselected, the device ignores all inputs  
after the pending write operations are completed.  
Document Number: 001-06620 Rev. *D  
Page 8 of 27  
 
CY7C1166V18, CY7C1177V18  
CY7C1168V18, CY7C1170V18  
echo clock and follows the timing of any data pin. This signal is  
asserted half a cycle before valid data arrives.  
DDR-I mode (with 1.0 cycle latency and a longer access time).  
For more information, refer to the application note, “DLL Consid-  
erations in QDRII/DDRII/QDRII+/DDRII+”. The DLL can also be  
reset by slowing or stopping the input clocks K and K for a  
minimum of 30 ns. However, it is not necessary for the DLL to be  
reset to lock to the desired frequency. During power up, when the  
DOFF is tied HIGH, the DLL gets locked after 2048 cycles of  
stable clock.  
DLL  
These chips use a Delay Lock Loop (DLL) that is designed to  
function between 120 MHz and the specified maximum clock  
frequency. The DLL may be disabled by applying ground to the  
DOFF pin. When the DLL is turned off, the device behaves in  
Application Example  
Figure 1 shows two DDR-II+ used in an application.  
Figure 1. Application Example  
ZQ  
CQ/CQ  
K
K
ZQ  
CQ/CQ  
K
K
SRAM#1  
LD R/W  
SRAM#2  
DQ  
A
DQ  
A
R = 250ohms  
R = 250ohms  
LD R/W  
DQ  
Addresses  
Cycle Start  
R/W  
Source CLK  
Source CLK  
BUS  
MASTER  
(CPU or ASIC)  
Echo Clock1/Echo Clock1  
Echo Clock2/Echo Clock2  
Truth Table  
The truth table for the CY7C1166V18, CY7C1177V18, CY7C1168V18, and CY7C1170V18 follows.  
Operation  
K
LD R/W  
DQ  
DQ  
Write Cycle:  
L-H  
L
L
L
D(A) at K (t + 1) ↑  
D(A + 1) at K (t + 1) ↑  
Load address; wait one cycle; input write data on consecutive  
K and K rising edges.  
Read Cycle: (2.5 Cycle Latency)  
Load address; wait two and a half cycle; read data on consec-  
utive K and K rising edges.  
L-H  
H
Q(A) at K (t + 2)↑  
Q(A + 1) at K (t + 3) ↑  
NOP: No Operation  
L-H  
H
X
X
X
High-Z  
High-Z  
Standby: Clock Stopped  
Stopped  
Previous State  
Previous State  
Notes  
2. X = “Don’t Care,” H = Logic HIGH, L = Logic LOW, represents rising edge.  
3. Device powers up deselected and the outputs in a tri-state condition.  
4. “A” represents address location latched by the devices when transaction was initiated and A + 1 represents the addresses sequence in the burst.  
5. “t” represents the cycle at which a Read/Write operation is started. t + 1, t + 2, and t + 3 are the first, second, and third clock cycles succeeding the “t” clock cycle.  
6. Data inputs are registered at K and K rising edges. Data outputs are delivered on K and K rising edges.  
7. Do K = K = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically.  
Document Number: 001-06620 Rev. *D  
Page 9 of 27  
             
CY7C1166V18, CY7C1177V18  
CY7C1168V18, CY7C1170V18  
Write Cycle Descriptions  
The write cycle descriptions of CY7C1166V18 and CY7C1168V18 follows.  
BWS / BWS /  
0
1
K
Comments  
K
NWS  
NWS  
1
0
L
L
L
L
L–H  
During the Data portion of a write sequence:  
CY7C1166V18 both nibbles (D  
) are written into the device.  
[7:0]  
CY7C1168V18 both bytes (D  
) are written into the device.  
[17:0]  
L–H  
L-H During the Data portion of a write sequence:  
CY7C1166V18 both nibbles (D  
) are written into the device.  
) are written into the device.  
[7:0]  
CY7C1168V18 both bytes (D  
[17:0]  
L
H
H
L
During the Data portion of a write sequence:  
CY7C1166V18 only the lower nibble (D  
) is written into the device, D  
remains unaltered.  
remains unaltered.  
[3:0]  
[7:4]  
CY7C1168V18 only the lower byte (D  
) is written into the device, D  
[8:0]  
[17:9]  
L
L–H During the Data portion of a write sequence:  
CY7C1166V18 only the lower nibble (D  
) is written into the device, D  
remains unaltered.  
remains unaltered.  
[3:0]  
[7:4]  
CY7C1168V18 only the lower byte (D  
) is written into the device, D  
[8:0]  
[17:9]  
H
H
L–H  
During the Data portion of a write sequence:  
CY7C1166V18 only the upper nibble (D  
) is written into the device, D  
remains unaltered.  
remains unaltered.  
[7:4]  
[3:0]  
[8:0]  
CY7C1168V18 only the upper byte (D  
) is written into the device, D  
[17:9]  
L
L–H During the Data portion of a write sequence:  
CY7C1166V18 only the upper nibble (D  
) is written into the device, D  
) is written into the device, D  
remains unaltered.  
remains unaltered.  
[7:4]  
[3:0]  
[8:0]  
CY7C1168V18 only the upper byte (D  
[17:9]  
H
H
H
H
L–H  
No data is written into the devices during this portion of a write operation.  
L–H No data is written into the devices during this portion of a write operation.  
The write cycle descriptions of CY7C1177V18 follows.  
BWS  
K
L-H  
K
Comments  
0
L
L
During the Data portion of a Write sequence, the single byte (D  
) is written into the device.  
[8:0]  
L-H During the Data portion of a Write sequence, the single byte (D  
) is written into the device.  
[8:0]  
H
H
L-H  
No data is written into the device during this portion of a Write operation.  
L-H No data is written into the device during this portion of a Write operation.  
Note  
8. Is based on a write cycle was initiated in accordance with the Write Cycle Description Truth Table. Alter NWS , NWS , BWS , BWS , BWS , and BWS on different  
0
1
0
1
2
3
portions of a write cycle, as long as the setup and hold requirements are achieved.  
Document Number: 001-06620 Rev. *D  
Page 10 of 27  
 
CY7C1166V18, CY7C1177V18  
CY7C1168V18, CY7C1170V18  
The write cycle descriptions of CY7C1170V18 follows.  
BWS  
BWS  
BWS  
BWS  
3
K
K
Comments  
0
1
2
L
L
L
L
L-H  
During the data portion of a write sequence, all four bytes (D  
the device.  
) are written into  
) are written into  
[35:0]  
L
L
L
H
H
L
L
H
H
H
H
L
L
H
H
H
H
H
H
L
L-H  
L-H During the data portion of a write sequence, all four bytes (D  
the device.  
[35:0]  
During the data portion of a write sequence, only the lower byte (D  
) is written  
) is written  
[8:0]  
[8:0]  
into the device. D  
remains unaltered.  
[35:9]  
L
L-H During the data portion of a write sequence, only the lower byte (D  
into the device. D remains unaltered.  
[35:9]  
H
H
H
H
H
H
L-H  
During the data portion of a write sequence, only the byte (D  
) is written into  
[17:9]  
the device. D  
and D  
remains unaltered.  
[8:0]  
[35:18]  
L
L-H During the data portion of a write sequence, only the byte (D  
the device. D and D remains unaltered.  
) is written into  
[17:9]  
[8:0]  
[35:18]  
H
H
H
H
L-H  
During the data portion of a write sequence, only the byte (D  
) is written into  
) is written into  
) is written into  
) is written into  
[26:18]  
[26:18]  
[35:27]  
[35:27]  
the device. D  
and D  
remains unaltered.  
[17:0]  
[35:27]  
L
L-H During the data portion of a write sequence, only the byte (D  
the device. D and D remains unaltered.  
[17:0]  
[35:27]  
H
H
L-H  
During the data portion of a write sequence, only the byte (D  
the device. D remains unaltered.  
[26:0]  
L
L-H During the data portion of a write sequence, only the byte (D  
the device. D remains unaltered.  
[26:0]  
H
H
H
H
H
H
H
H
L-H  
No data is written into the device during this portion of a write operation.  
L-H No data is written into the device during this portion of a write operation.  
Document Number: 001-06620 Rev. *D  
Page 11 of 27  
CY7C1166V18, CY7C1177V18  
CY7C1168V18, CY7C1170V18  
IEEE 1149.1 Serial Boundary Scan (JTAG)  
Instruction Register  
These SRAMs incorporate a serial boundary scan test access  
port (TAP) in the FBGA package. This part is fully compliant with  
IEEE Standard #1149.1-2001. The TAP operates using JEDEC  
standard 1.8V IO logic levels.  
Load three-bit instructions serially into the instruction register.  
This register is loaded when it is placed between the TDI and  
page 15. Upon power up, the instruction register is loaded with  
the IDCODE instruction. It is also loaded with the IDCODE  
instruction if the controller is placed in a reset state as described  
in the previous section.  
Disabling the JTAG Feature  
It is possible to operate the SRAM without using the JTAG  
feature. To disable the TAP controller, TCK must be tied LOW  
(V ) to prevent clocking of the device. TDI and TMS are inter-  
nally pulled up and may be unconnected. They may alternately  
When the TAP controller is in the Capture IR state, the two least  
significant bits are loaded with a binary “01” pattern to allow fault  
isolation of the board level serial test path.  
SS  
be connected to V through a pull up resistor. TDO must be left  
DD  
unconnected. Upon power up, the device comes up in a reset  
state which does not interfere with the operation of the device.  
Bypass Register  
To save time when serially shifting data through registers, it is  
sometimes advantageous to skip certain chips. The bypass  
register is a single-bit register that can be placed between TDI  
and TDO pins. This enables data to be shifted through the SRAM  
Test Access Port—Test Clock  
The test clock is used only with the TAP controller. All inputs are  
captured on the rising edge of TCK. All outputs are driven from  
the falling edge of TCK.  
with minimal delay. The bypass register is set LOW (V ) when  
SS  
the BYPASS instruction is executed.  
Test Mode Select  
Boundary Scan Register  
The TMS input is used to give commands to the TAP controller  
and is sampled on the rising edge of TCK. It is allowable to leave  
this pin unconnected if the TAP is not used. The pin is pulled up  
internally, resulting in a logic HIGH level.  
The boundary scan register is connected to all of the input and  
output pins on the SRAM. Several no connect (NC) pins are also  
included in the scan register to reserve pins for higher density  
devices.  
Test Data-In (TDI)  
The boundary scan register is loaded with the contents of the  
RAM Input and Output ring when the TAP controller is in the  
Capture-DR state and is then placed between the TDI and TDO  
pins when the controller is moved to the Shift-DR state. Use the  
EXTEST, SAMPLE/PRELOAD, and SAMPLE Z instructions to  
capture the contents of the input and output ring.  
The TDI pin is used to serially input information into the registers  
and connect to the input of any of the registers. The register  
between TDI and TDO is chosen by the instruction that is loaded  
into the TAP instruction register. For more information about  
loading the instruction register, see “TAP Controller State  
Diagram” on page 14. TDI is internally pulled up and uncon-  
nected if the TAP is not used in an application. TDI is connected  
to the most significant bit (MSB) on any register.  
The “Boundary Scan Order” on page 18 show the order in which  
the bits are connected. Each bit corresponds to one of the bumps  
on the SRAM package. The MSb of the register is connected to  
TDI, and the LSb is connected to TDO.  
Test Data-Out (TDO)  
The TDO output pin is used to serially clock data-out from the  
registers. The output is active depending upon the current state  
of the TAP state machine (see “Instruction Codes” on page 17).  
The output changes on the falling edge of TCK. TDO is  
connected to the least significant bit (LSb) of any register.  
Identification (ID) Register  
The ID register is loaded with a vendor-specific 32-bit code  
during the Capture-DR state when the IDCODE command is  
loaded in the instruction register. The IDCODE is hardwired into  
the SRAM and can be shifted out when the TAP controller is in  
the Shift-DR state. The ID register has a vendor code and other  
Performing a TAP Reset  
A Reset is performed by forcing TMS HIGH (V ) for five rising  
DD  
edges of TCK. This RESET does not affect the operation of the  
SRAM and may be performed while the SRAM is operating. At  
power up, the TAP is reset internally to ensure that TDO comes  
up in a high-Z state.  
TAP Instruction Set  
Eight different instructions are possible with the three-bit  
instruction register. All combinations are listed in the “Instruction  
Codes” on page 17. Three of these instructions are listed as  
RESERVED and must not be used. The other five instructions  
are described in this section.  
TAP Registers  
Registers are connected between the TDI and TDO pins and  
enable data to be scanned into and out of the SRAM test circuitry.  
Select only one register at a time through the instruction  
registers. Data is serially loaded into the TDI pin on the rising  
edge of TCK. Data is output on the TDO pin on the falling edge  
of TCK.  
Instructions are loaded into the TAP controller during the Shift-IR  
state when the instruction register is placed between TDI and  
TDO. During this state, instructions are shifted through the  
instruction register through the TDI and TDO pins. To execute  
the instruction after it is shifted in, the TAP controller must be  
moved into the Update-IR state.  
Document Number: 001-06620 Rev. *D  
Page 12 of 27  
CY7C1166V18, CY7C1177V18  
CY7C1168V18, CY7C1170V18  
IDCODE  
PRELOAD enables an initial data pattern to be placed at the  
latched parallel outputs of the boundary scan register cells be-  
fore the selection of another boundary scan test operation.  
The IDCODE instruction causes a vendor-specific 32-bit code to  
be loaded into the instruction register. It also places the  
instruction register between the TDI and TDO pins and enables  
the IDCODE to be shifted out of the device when the TAP  
controller enters the Shift-DR state. The IDCODE instruction is  
loaded into the instruction register upon power up or whenever  
the TAP controller is supplied a test logic reset state.  
The shifting of data for the SAMPLE and PRELOAD phases can  
occur concurrently when required—that is, while data captured  
is shifted out, the preloaded data can be shifted in.  
BYPASS  
When the BYPASS instruction is loaded in the instruction register  
and the TAP is placed in a Shift-DR state, the bypass register is  
placed between the TDI and TDO pins. The advantage of the  
BYPASS instruction is that it shortens the boundary scan path  
when multiple devices are connected together on a board.  
SAMPLE Z  
The SAMPLE Z instruction causes the boundary scan register to  
be connected between the TDI and TDO pins when the TAP  
controller is in a Shift-DR state. The SAMPLE Z command puts  
the output bus into a High-Z state until the next command is  
supplied during the Update IR state.  
EXTEST  
The EXTEST instruction enables the preloaded data to be driven  
out through the system output pins. This instruction also selects  
the boundary scan register to be connected for serial access  
between the TDI and TDO in the shift-DR controller state.  
SAMPLE/PRELOAD  
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When  
the SAMPLE/PRELOAD instructions are loaded into the instruc-  
tion register and the TAP controller is in the Capture-DR state, a  
snapshot of data on the inputs and output pins is captured in the  
boundary scan register.  
EXTEST Output Bus Tri-State  
IEEE Standard 1149.1 mandates that the TAP controller is able  
to put the output bus into a tri-state mode.  
The user must be aware that the TAP controller clock can only  
operate at a frequency up to 20 MHz, while the SRAM clock  
operates more than an order of magnitude faster. Because there  
is a large difference in the clock frequencies, it is possible that  
during the Capture-DR state, an input or output undergoes a  
transition. The TAP may then try to capture a signal while in  
transition (metastable state). This does not harm the device, but  
there is no guarantee as to the value that is captured.  
Repeatable results may not be possible.  
The boundary scan register has a special bit located at bit #47.  
When this scan cell, called the “extest output bus tri-state”, is  
latched into the preload register during the Update-DR state in  
the TAP controller, it directly controls the state of the output  
(Q-bus) pins, when the EXTEST is entered as the current  
instruction. When HIGH, it enables the output buffers to drive the  
output bus. When LOW, this bit places the output bus into a  
High-Z condition.  
To guarantee that the boundary scan register captures the cor-  
rect value of a signal, the SRAM signal must be stabilized long  
enough to meet the TAP controller's capture setup plus hold  
times (t and t ). The SRAM clock input might not be captured  
correctly if there is no way in a design to stop (or slow) the clock  
during a SAMPLE/PRELOAD instruction. If this is an issue, it is  
still possible to capture all other signals and simply ignore the  
value of the CK and CK captured in the boundary scan register.  
Set this bit by entering the SAMPLE/PRELOAD or EXTEST  
command, and then shifting the desired bit into that cell, during  
the Shift-DR state. During Update-DR, the value loaded into that  
shift-register cell latches into the preload register. When the  
EXTEST instruction is entered, this bit directly controls the output  
Q-bus pins. Note that this bit is preset HIGH to enable the output  
when the device is powered up, and also when the TAP controller  
is in the Test-Logic-Reset state.  
CS  
CH  
After the data is captured, it is possible to shift out the data by  
putting the TAP into the Shift-DR state. This places the boundary  
scan register between the TDI and TDO pins.  
Reserved  
These instructions are not implemented but are reserved for  
future use. Do not use these instructions.  
Document Number: 001-06620 Rev. *D  
Page 13 of 27  
CY7C1166V18, CY7C1177V18  
CY7C1168V18, CY7C1170V18  
TAP Controller State Diagram  
[9]  
Figure 2 shows the tap controller state diagram.  
Figure 2. Tap Controller State Diagram  
TEST-LOGIC  
RESET  
1
0
0
1
1
1
TEST-LOGIC/  
IDLE  
SELECT  
DR-SCAN  
SELECT  
IR-SCAN  
0
0
1
1
CAPTURE-DR  
CAPTURE-IR  
0
0
SHIFT-DR  
0
1
SHIFT-IR  
0
1
1
EXIT1-DR  
0
1
EXIT1-IR  
0
0
0
PAUSE-DR  
1
PAUSE-IR  
1
0
0
EXIT2-DR  
1
EXIT2-IR  
1
UPDATE-DR  
UPDATE-IR  
1
1
0
0
Note  
9. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.  
Document Number: 001-06620 Rev. *D  
Page 14 of 27  
     
CY7C1166V18, CY7C1177V18  
CY7C1168V18, CY7C1170V18  
TAP Controller Block Diagram  
Figure 3. Tap Controller Block Diagram  
0
Bypass Register  
Selection  
TDI  
Selection  
Circuitry  
2
1
0
0
0
TDO  
Circuitry  
Instruction Register  
29  
31 30  
.
.
2
1
Identification Register  
.
106 .  
.
.
2
1
Boundary Scan Register  
TCK  
TMS  
TAP Controller  
TAP Electrical Characteristics  
The Tap Electrical Characteristics table over the operating range follows.  
Parameter  
Description  
Output HIGH Voltage  
Test Conditions  
= 2.0 mA  
Min  
1.4  
1.6  
Max  
Unit  
V
V
V
V
V
V
V
I
I
I
I
I
OH1  
OH2  
OL1  
OL2  
IH  
OH  
OH  
OL  
OL  
Output HIGH Voltage  
Output LOW Voltage  
Output LOW Voltage  
Input HIGH Voltage  
= 100 μA  
= 2.0 mA  
V
0.4  
0.2  
V
= 100 μA  
V
0.65 V  
V
+ 0.3  
V
DD  
DD  
Input LOW Voltage  
–0.3  
0.35 V  
5
V
IL  
DD  
Input and Output Load Current  
GND V V  
DD  
5  
μA  
X
I
Notes  
10. These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics Table.  
11. Overshoot: V (AC) < V + 0.35V (pulse width less than t /2).  
/2), undershoot: V (AC) > 0.3V (pulse width less than t  
IH  
DDQ  
CYC  
IL  
CYC  
12. All voltage refer to ground.  
Document Number: 001-06620 Rev. *D  
Page 15 of 27  
       
CY7C1166V18, CY7C1177V18  
CY7C1168V18, CY7C1170V18  
TAP AC Switching Characteristics  
The Tap AC Switching Characteristics over the operating range follows.  
Parameter  
Description  
Min  
Max  
Unit  
ns  
t
t
t
t
TCK Clock Cycle Time  
TCK Clock Frequency  
TCK Clock HIGH  
50  
TCYC  
20  
MHz  
ns  
TF  
TH  
TL  
20  
20  
TCK Clock LOW  
ns  
Setup Times  
t
t
t
TMS Setup to TCK Clock Rise  
TDI Setup to TCK Clock Rise  
Capture Setup to TCK Rise  
5
5
5
ns  
ns  
ns  
TMSS  
TDIS  
CS  
Hold Times  
t
t
t
TMS Hold after TCK Clock Rise  
TDI Hold after Clock Rise  
5
5
5
ns  
ns  
ns  
TMSH  
TDIH  
CH  
Capture Hold after Clock Rise  
Output Times  
t
t
TCK Clock LOW to TDO Valid  
TCK Clock LOW to TDO Invalid  
10  
ns  
ns  
TDOV  
TDOX  
0
TAP Timing and Test Condition  
The Tap Timing and Test Conditions for the CY7C1166V18, CY7C1177V18, CY7C1168V18, and CY7C1170V18 follows.  
Figure 4. TAP Timing and Test Conditions  
0.9V  
ALL INPUT PULSES  
50Ω  
1.8V  
TDO  
0.9V  
0V  
Z = 50  
0
Ω
C = 20 pF  
L
tTL  
tTH  
GND  
(a)  
Test Clock  
TCK  
tTCYC  
tTMSH  
tTMSS  
Test Mode Select  
TMS  
tTDIS  
tTDIH  
Test Data In  
TDI  
Test Data Out  
TDO  
tTDOV  
tTDOX  
Notes  
13. t and t refer to the setup and hold time requirements of latching data from the boundary scan register.  
CS  
CH  
14. Test conditions are specified using the load in TAP AC test conditions. t /t = 1 ns  
R
F
Document Number: 001-06620 Rev. *D  
Page 16 of 27  
   
CY7C1166V18, CY7C1177V18  
CY7C1168V18, CY7C1170V18  
Identification Register Definitions  
Value  
Instruction Field  
Description  
CY7C1166V18  
CY7C1177V18  
000  
CY7C1168V18  
000  
CY7C1170V18  
Revision Number  
(31:29)  
000  
000  
Version number.  
Cypress Device ID 11010111000000101 11010111000001101 11010111000010101 11010111000100101 Defines the type of  
(28:12)  
SRAM.  
Cypress JEDEC ID  
(11:1)  
00000110100  
1
00000110100  
1
00000110100  
1
00000110100  
1
Allows unique  
identification of  
SRAM vendor.  
ID Register  
Presence (0)  
Indicates the  
presence of an ID  
register.  
Scan Register Sizes  
Register Name  
Bit Size  
Instruction  
Bypass  
3
1
ID  
32  
107  
Boundary Scan  
Instruction Codes  
Instruction  
EXTEST  
Code  
000  
Description  
Captures the input output ring contents.  
IDCODE  
001  
Loads the ID register with the vendor ID code and places the register between TDI  
and TDO. This operation does not affect SRAM operation.  
SAMPLE Z  
010  
Captures the Input Output contents. It places the boundary scan register between  
TDI and TDO. This forces all SRAM output drivers to a High-Z state.  
RESERVED  
011  
100  
Do Not Use: This instruction is reserved for future use.  
SAMPLE/PRELOAD  
Captures the input output ring contents. It places the boundary scan register between  
TDI and TDO. This operation does not affect the SRAM operation.  
RESERVED  
RESERVED  
BYPASS  
101  
110  
111  
Do Not Use: This instruction is reserved for future use.  
Do Not Use: This instruction is reserved for future use.  
Places the bypass register between TDI and TDO. This operation does not affect  
SRAM operation.  
Document Number: 001-06620 Rev. *D  
Page 17 of 27  
   
CY7C1166V18, CY7C1177V18  
CY7C1168V18, CY7C1170V18  
Boundary Scan Order  
Bit #  
0
Bump ID  
6R  
Bit #  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
Bump ID  
11H  
10G  
9G  
Bit #  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
76  
77  
78  
79  
80  
Bump ID  
7B  
6B  
6A  
5B  
5A  
4A  
5C  
4B  
3A  
1H  
1A  
2B  
3B  
1C  
1B  
3D  
3C  
1D  
2C  
3E  
2D  
2E  
1E  
2F  
Bit #  
81  
Bump ID  
3G  
2G  
1J  
1
6P  
82  
2
6N  
83  
3
7P  
11F  
11G  
9F  
84  
2J  
4
7N  
85  
3K  
3J  
5
7R  
86  
6
8R  
10F  
11E  
10E  
10D  
9E  
87  
2K  
1K  
2L  
7
8P  
88  
8
9R  
89  
9
11P  
10P  
10N  
9P  
90  
3L  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
91  
1M  
1L  
10C  
11D  
9C  
92  
93  
3N  
3M  
1N  
2M  
3P  
2N  
2P  
1P  
3R  
4R  
4P  
5P  
5N  
5R  
10M  
11N  
9M  
94  
9D  
95  
11B  
11C  
9B  
96  
9N  
97  
11L  
11M  
9L  
98  
10B  
11A  
Internal  
9A  
99  
100  
101  
102  
103  
104  
105  
106  
10L  
11K  
10K  
9J  
8B  
7C  
9K  
6C  
3F  
10J  
11J  
8A  
1G  
1F  
7A  
Document Number: 001-06620 Rev. *D  
Page 18 of 27  
 
CY7C1166V18, CY7C1177V18  
CY7C1168V18, CY7C1170V18  
Power Up Sequence in DDR-II+ SRAM  
DLL Constraints  
DDR-II+ SRAMs must be powered up and initialized in a  
predefined manner to prevent undefined operations. During  
power up, when the DOFF is tied HIGH, the DLL gets locked after  
2048 cycles of stable clock.  
DLL uses K clock as its synchronizing input. The input must  
have low phase jitter, which is specified as t  
.
KC Var  
The DLL functions at frequencies down to 120 MHz.  
If the input clock is unstable and the DLL is enabled, then the  
DLL may lock onto an incorrect frequency, causing unstable  
SRAM behavior. To avoid this, provide 2048 cycles stable clock  
to relock to the desired clock frequency.  
Power Up Sequence  
Apply power with DOFF tied HIGH (all other inputscan be HIGH  
or LOW)  
Apply V before V  
DD  
DDQ  
Apply V  
before V  
or at the same time as V  
DDQ  
REF REF  
Provide stable power and clock (K, K) for 2048 cycles to lock  
the DLL.  
Power Up Waveforms  
Figure 5. Power Up Waveforms  
K
K
Start Normal  
Operation  
Unstable Clock  
> 2048 Stable Clock  
Clock Start (Clock Starts after V /V  
DD DDQ  
is Stable)  
V
/V  
+
V
/V Stable (< 0.1V DC per 50 ns)  
DD DDQ  
DD DDQ  
Fix HIGH (tie to V  
DDQ  
)
DOFF  
Document Number: 001-06620 Rev. *D  
Page 19 of 27  
CY7C1166V18, CY7C1177V18  
CY7C1168V18, CY7C1170V18  
Current into Outputs (LOW)......................................... 20 mA  
Static Discharge Voltage (MIL-STD-883, M 3015).... >2001V  
Latch up Current..................................................... >200 mA  
Maximum Ratings  
Exceeding maximum ratings may shorten the useful life of the  
device. User guidelines are not tested.  
Storage Temperature ................................ –65°C to + 150°C  
Ambient Temperature with Power Applied. –55°C to + 125°C  
Operating Range  
Ambient  
Supply Voltage on V Relative to GND .......–0.5V to + 2.9V  
V
DDQ  
DD  
Range  
Commercial  
Industrial  
Temperature  
0°C to +70°C  
–40°C to +85°C  
V
DD  
Supply Voltage on V  
Relative to GND..... –0.5V to + V  
DD  
DDQ  
1.8 ± 0.1V  
1.4V to  
DC Applied to Outputs in High-Z .........–0.5V to V  
+ 0.3V  
V
DDQ  
DD  
DC Input Voltage ...............................0.5V to V + 0.3V  
DD  
Electrical Characteristic  
The DC Electrical Characteristics over the operating range follows.  
Parameter  
Description  
Power Supply Voltage  
IO Supply Voltage  
Test Conditions  
Min  
1.7  
1.4  
Typ  
1.8  
1.5  
Max  
Unit  
V
1.9  
V
V
DD  
V
V
V
V
V
V
V
I
V
DD  
DDQ  
OH  
Output HIGH Voltage  
Output LOW Voltage  
Output HIGH Voltage  
Output LOW Voltage  
Input HIGH Voltage  
Input LOW Voltage  
V
V
/2 – 0.12  
/2 – 0.12  
V
V
/2 + 0.12  
/2 + 0.12  
V
DDQ  
DDQ  
DDQ  
V
OL  
DDQ  
I
= –0.1 mA, Nominal Impedance  
= 0.1 mA, Nominal Impedance  
V
V
– 0.2  
V
V
OH(LOW)  
OL(LOW)  
IH  
OH  
OL  
DDQ  
DDQ  
I
V
0.2  
V
SS  
+ 0.1  
V
+ 0.15  
– 0.1  
REF  
V
REF  
DDQ  
–0.15  
V
V
IL  
Input Leakage Current  
Output Leakage Current  
Input Reference Voltage  
GND V V  
–2  
–2  
2
μA  
μA  
V
X
I
DDQ  
I
GND V V  
Output Disabled  
2
OZ  
I
DDQ,  
V
Typical Value = 0.75V  
0.68  
0.75  
0.95  
850  
920  
1020  
1080  
250  
260  
290  
300  
REF  
I
V
Operating Supply  
V
= Max, I  
= 0 mA, 300 MHz  
333 MHz  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
DD  
DD  
DD  
OUT  
CYC  
f = f  
= 1/t  
max  
375 MHz  
400 MHz  
I
Automatic Power Down Current Max V  
,
300 MHz  
SB1  
DD  
Both Ports Deselected,  
333 MHz  
375 MHz  
400 MHz  
V
V or V V  
IN  
IH  
IN  
IL  
f = f  
= 1/t  
,
max  
CYC  
Inputs Static  
AC Input Requirements  
Over the operating range  
Parameter  
Description  
Input HIGH Voltage  
Input LOW Voltage  
Test Conditions  
Min  
Typ  
Max  
Unit  
V
V
V
+ 0.2  
V
+ 0.24  
DDQ  
IH  
IL  
REF  
V
–0.24  
V
– 0.2  
V
REF  
Notes  
15. Power up: Is based on a linear ramp from 0V to V (min) within 200 ms. During this time V < V and V  
< V  
DD.  
DD  
IH  
DD  
DDQ  
16. Outputs are impedance controlled. I = –(V  
/2)/(RQ/5) for values of 175Ω < RQ < 350Ω.  
OH  
DDQ  
17. Outputs are impedance controlled. I = (V  
/2)/(RQ/5) for values of 175Ω < RQ < 350Ω  
OL  
DDQ  
18. V  
(min) = 0.68V or 0.46V  
, whichever is larger, V  
(max) = 0.95V or 0.54V  
, whichever is smaller.  
DDQ  
REF  
DDQ  
REF  
19. The operation current is calculated with 50% read cycle and 50% write cycle.  
Document Number: 001-06620 Rev. *D  
Page 20 of 27  
         
CY7C1166V18, CY7C1177V18  
CY7C1168V18, CY7C1170V18  
Capacitance  
Tested initially and after any design or process change that may affect these parameters.  
Parameter Description Test Conditions  
Input Capacitance T = 25°C, f = 1 MHz,  
Max  
Unit  
pF  
C
5
6
7
IN  
A
V
= 1.8V  
DD  
V
C
Clock Input Capacitance  
Output Capacitance  
pF  
CLK  
O
= 1.5V  
DDQ  
C
pF  
Thermal Resistance  
Tested initially and after any design or process change that may affect these parameters.  
165 FBGA  
Package  
Parameter  
Description  
Test Conditions  
Unit  
Θ
Thermal Resistance  
(junction to ambient)  
Test conditions follow standard test methods and  
procedures for measuring thermal impedance, in  
accordance with EIA/JESD51.  
17.2  
°C/W  
JA  
Θ
Thermal Resistance  
(junction to case)  
4.15  
°C/W  
JC  
AC Test Loads and Waveforms  
Figure 6. AC Test loads and Waveforms  
VREF = 0.75V  
0.75V  
VREF  
VREF  
0.75V  
R = 50Ω  
OUTPUT  
[20]  
ALL INPUT PULSES  
Z = 50Ω  
0
DEVICE  
R = 50Ω  
L
OUTPUT  
1.25V  
0.75V  
UNDER  
DEVICE  
UNDER  
0.25V  
TEST  
5 pF  
VREF = 0.75V  
SLEW RATE= 2 V/ns  
ZQ  
TEST  
ZQ  
RQ =  
RQ =  
250Ω  
250Ω  
INCLUDING  
JIG AND  
SCOPE  
(a)  
(b)  
Note  
20. Unless otherwise noted, test conditions are based on a signal transition time of 2V/ns, timing reference levels of 0.75V, V  
= 0.75V, RQ = 250Ω, V  
= 1.5V, input  
REF  
DDQ  
pulse levels of 0.25V to 1.25V, and output loading of the specified I /I and load capacitance shown in (a) of AC Test Loads and Waveforms.  
OL OH  
Document Number: 001-06620 Rev. *D  
Page 21 of 27  
   
CY7C1166V18, CY7C1177V18  
CY7C1168V18, CY7C1170V18  
Switching Characteristics  
Over the operating range  
400 MHz  
375 MHz  
333 MHz  
300 MHz  
Cypress Consortium  
Parameter Parameter  
Description  
Unit  
Min Max Min Max Min Max Min Max  
t
t
t
t
t
V
(Typical) to the first Access  
1
1
1
1
ms  
ns  
POWER  
CYC  
KH  
DD  
t
t
t
t
K Clock Cycle Time  
2.50 8.40 2.66 8.40 3.0 8.40 3.3 8.40  
KHKH  
KHKL  
KLKH  
KHKH  
Input Clock (K/K) HIGH  
Input Clock (K/K) LOW  
0.4  
0.4  
0.4  
0.4  
0.4  
0.4  
0.4  
0.4  
t
t
CYC  
KL  
CYC  
K Clock Rise to K Clock Rise  
(rising edge to rising edge)  
1.06  
1.13  
1.28  
1.40  
ns  
KHKH  
Setup Times  
t
t
t
t
t
t
Address Setup to K Clock Rise  
0.4  
0.4  
0.4  
0.4  
0.4  
0.4  
0.4  
0.4  
ns  
ns  
ns  
SA  
AVKH  
IVKH  
IVKH  
Control Setup to K Clock Rise (LD, R/W)  
SC  
Double Data Rate Control Setup to Clock (K/K) 0.28  
Rise (BWS , BWS , BWS , BWS )  
0.28  
0.28  
0.28  
SCDDR  
0
1
2
3
t
t
D Setup to Clock (K/K) Rise  
[X:0]  
0.28  
0.28  
0.28  
0.28  
ns  
SD  
DVKH  
Hold Times  
t
t
t
t
t
t
0.4  
0.4  
0.4  
0.4  
0.4  
0.4  
0.4  
0.4  
ns  
ns  
ns  
Address Hold after K Clock Rise  
Control Hold after K Clock Rise (LD, R/W)  
HA  
KHAX  
KHIX  
KHIX  
HC  
Double Data Rate Control Hold after Clock (K/K) 0.28  
Rise (BWS , BWS , BWS , BWS )  
0.28  
0.28  
0.28  
HCDDR  
0
1
2
3
t
t
D Hold after Clock (K/K) Rise  
[X:0]  
0.28  
0.28  
0.28  
0.28  
ns  
HD  
KHDX  
Output Times  
t
t
t
t
K/K Clock Rise to Data Valid  
0.45  
0.45  
0.45  
0.45  
ns  
ns  
CO  
CHQV  
CHQX  
Data Output Hold after K/K Clock Rise  
(Active to Active)  
–0.45  
–0.45  
–0.45  
–0.45  
DOH  
t
t
t
t
t
t
t
t
t
t
t
t
K/ Clock Rise to Echo Clock Valid  
0.45  
0.45  
0.45  
0.45  
ns  
ns  
ns  
ns  
ns  
ns  
CCQO  
CQOH  
CQD  
CHCQV  
CHCQX  
CQHQV  
CQHQX  
CQHCQL  
CQHCQH  
K
Echo Clock Hold after K/K Clock Rise  
Echo Clock High to Data Valid  
–0.45  
–0.45  
–0.45  
–0.45  
0.2  
0.2  
0.2  
0.2  
Echo Clock High to Data Invalid  
–0.2  
0.81  
0.81  
–0.2  
0.88  
0.88  
–0.2  
1.03  
1.03  
–0.2  
1.15  
1.15  
CQDOH  
CQH  
Output Clock (CQ/CQ) HIGH  
CQ Clock Rise to CQ Clock Rise  
CQHCQH  
(rising edge to rising edge)  
t
t
t
t
t
t
Clock (K/K) Rise to High-Z (Active to High-Z)  
0.45  
0.45  
0.45  
0.45  
ns  
ns  
ns  
CHZ  
CLZ  
CHQZ  
CHQX1  
QVLD  
Clock (K/K) Rise to Low-Z  
–0.45  
–0.45  
–0.45  
–0.45  
Echo Clock High to QVLD Valid  
–0.20 0.20 –0.20 0.20 –0.20 0.20 –0.20 0.20  
QVLD  
DLL Timing  
t
t
t
t
t
t
Clock Phase Jitter  
DLL Lock Time (K)  
0.20  
0.20  
0.20  
0.20  
ns  
KC Var  
KC Var  
2048  
30  
2048  
30  
2048  
30  
2048  
30  
Cycles  
ns  
KC lock  
KC Reset  
KC lock  
KC Reset  
K Static to DLL Reset  
Notes  
21. When a part with a maximum frequency above 300 MHz is operating at a lower clock frequency, it requires the input timings of the frequency range in which it is being  
operated and outputs data with the output timings of that frequency range.  
22. This part has a voltage regulator internally; t  
initiated.  
23. These parameters are extrapolated from the input timing parameters (t  
is the time that the power must be supplied above V minimum initially before a read or write operation can be  
POWER  
DD  
- 250 ps, where 250 ps is the internal jitter. An input jitter of 200 ps (t  
) is already  
KHKH  
KC Var  
included in the t  
). These parameters are only guaranteed by design and are not tested in production.  
KHKH  
24. t  
, t  
, are specified with a load capacitance of 5 pF as in (b) of “AC Test Loads and Waveforms” on page 21. Transition is measured ± 100 mV from steady-state  
CHZ CLZ  
voltage.  
25. At any voltage and temperature t  
is less than t  
and t  
less than t  
.
CHZ  
CLZ  
CHZ  
CO  
26. t  
spec is applicable for both rising and falling edges of QVLD signal.  
QVLD  
27. Hold to >V or <V .  
IH  
IL  
Document Number: 001-06620 Rev. *D  
Page 22 of 27  
               
CY7C1166V18, CY7C1177V18  
CY7C1168V18, CY7C1170V18  
Switching Waveform  
Read/Write/Deselect Sequence  
Figure 7. Waveform for 2.5 Cycle Read Latency  
NOP  
1
READ  
2
READ  
3
NOP  
5
NOP  
6
WRITE  
7
WRITE  
8
NOP  
11  
NOP  
4
READ  
9
NOP  
10  
12  
K
t
t
t
t
KH  
KL  
KHKH  
CYC  
K
LD  
t
t
HC  
SC  
R/W  
A
A2  
A3  
A0  
A4  
A1  
t
QVLD  
t
t
t
t
SA HA  
QVLD  
QVLD  
QVLD  
t
t
HD  
HD  
SD  
t
t
SD  
D21 D30 D31  
Q00 Q01 Q10 Q11  
D20  
Q40  
DQ  
t
t
DOH  
t
CHZ  
CLZ  
t
t
t
CO  
CQD  
(Read Latency = 2.5 Cycles)  
t
CQDOH  
CCQO  
CQOH  
t
CQ  
CQ  
t
CQH  
t
CQHCQH  
t
CCQO  
t
CQOH  
DON’T CARE  
UNDEFINED  
Notes  
28. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, i.e., A0 + 1.  
29. Outputs are disabled (High-Z) one clock cycle after a NOP.  
Document Number: 001-06620 Rev. *D  
Page 23 of 27  
   
CY7C1166V18, CY7C1177V18  
CY7C1168V18, CY7C1170V18  
Ordering Information  
Not all of the speed, package and temperature ranges are available. Contact your local sales representative or visit www.cypress.com  
for actual products offered.  
Speed  
(MHz)  
Package  
Diagram  
Operating  
Range  
Ordering Code  
Package Type  
400 CY7C1166V18-400BZC  
CY7C1177V18-400BZC  
CY7C1168V18-400BZC  
CY7C1170V18-400BZC  
CY7C1166V18-400BZXC  
CY7C1177V18-400BZXC  
CY7C1168V18-400BZXC  
CY7C1170V18-400BZXC  
CY7C1166V18-400BZI  
CY7C1177V18-400BZI  
CY7C1168V18-400BZI  
CY7C1170V18-400BZI  
CY7C1166V18-400BZXI  
CY7C1177V18-400BZXI  
CY7C1168V18-400BZXI  
CY7C1170V18-400BZXI  
375 CY7C1166V18-375BZC  
CY7C1177V18-375BZC  
CY7C1168V18-375BZC  
CY7C1170V18-375BZC  
CY7C1166V18-375BZXC  
CY7C1177V18-375BZXC  
CY7C1168V18-375BZXC  
CY7C1170V18-375BZXC  
CY7C1166V18-375BZI  
CY7C1177V18-375BZI  
CY7C1168V18-375BZI  
CY7C1170V18-375BZI  
CY7C1166V18-375BZXI  
CY7C1177V18-375BZXI  
CY7C1168V18-375BZXI  
CY7C1170V18-375BZXI  
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)  
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free  
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)  
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free  
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)  
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free  
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)  
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free  
Commercial  
Industrial  
Commercial  
Industrial  
Document Number: 001-06620 Rev. *D  
Page 24 of 27  
CY7C1166V18, CY7C1177V18  
CY7C1168V18, CY7C1170V18  
Ordering Information (continued)  
Not all of the speed, package and temperature ranges are available. Contact your local sales representative or visit www.cypress.com  
for actual products offered.  
Speed  
(MHz)  
Package  
Diagram  
Operating  
Range  
Ordering Code  
Package Type  
333 CY7C1166V18-333BZC  
CY7C1177V18-333BZC  
CY7C1168V18-333BZC  
CY7C1170V18-333BZC  
CY7C1166V18-333BZXC  
CY7C1177V18-333BZXC  
CY7C1168V18-333BZXC  
CY7C1170V18-333BZXC  
CY7C1166V18-333BZI  
CY7C1177V18-333BZI  
CY7C1168V18-333BZI  
CY7C1170V18-333BZI  
CY7C1166V18-333BZXI  
CY7C1177V18-333BZXI  
CY7C1168V18-333BZXI  
CY7C1170V18-333BZXI  
300 CY7C1166V18-300BZC  
CY7C1177V18-300BZC  
CY7C1168V18-300BZC  
CY7C1170V18-300BZC  
CY7C1166V18-300BZXC  
CY7C1177V18-300BZXC  
CY7C1168V18-300BZXC  
CY7C1170V18-300BZXC  
CY7C1166V18-300BZI  
CY7C1177V18-300BZI  
CY7C1168V18-300BZI  
CY7C1170V18-300BZI  
CY7C1166V18-300BZXI  
CY7C1177V18-300BZXI  
CY7C1168V18-300BZXI  
CY7C1170V18-300BZXI  
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)  
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free  
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)  
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free  
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)  
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free  
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)  
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free  
Commercial  
Industrial  
Commercial  
Industrial  
Document Number: 001-06620 Rev. *D  
Page 25 of 27  
CY7C1166V18, CY7C1177V18  
CY7C1168V18, CY7C1170V18  
Package Diagram  
Figure 8. 165-Ball FBGA (13 x 15 x 1.4 mm), 51-85180  
BOTTOM VIEW  
PIN 1 CORNER  
TOP VIEW  
Ø0.05 M C  
Ø0.25 M C A B  
-0.06  
PIN 1 CORNER  
Ø0.50  
(165X)  
+0.14  
1
2
3
4
5
6
7
8
9
10  
11  
11 10  
9
8
7
6
5
4
3
2
1
A
B
A
B
C
D
C
D
E
E
F
F
G
G
H
J
H
J
K
K
L
L
M
M
N
P
R
N
P
R
A
A
1.00  
5.00  
10.00  
13.00 0.10  
B
13.00 0.10  
B
0.15(4X)  
NOTES :  
SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD)  
PACKAGE WEIGHT : 0.475g  
JEDEC REFERENCE : MO-216 / DESIGN 4.6C  
PACKAGE CODE : BB0AC  
SEATING PLANE  
C
51-85180-*A  
Document Number: 001-06620 Rev. *D  
Page 26 of 27  
CY7C1166V18, CY7C1177V18  
CY7C1168V18, CY7C1170V18  
Document History Page  
Document Title: CY7C1166V18/CY7C1177V18/CY7C1168V18/CY7C1170V18, 18-Mbit DDR-II+ SRAM 2-Word Burst  
Architecture (2.5 Cycle Read Latency)  
Document Number: 001-06620  
Orig. of  
Change  
REV.  
ECN No. Issue Date  
Description of Change  
**  
430351  
461654  
See ECN  
See ECN  
NXR  
New data sheet  
*A  
NXR  
Revised the MPNs from  
CY7C1177BV18 to CY7C1166V18  
CY7C1168BV18 to CY7C1177V18  
CY7C1170BV18 to CY7C1168V18  
Changed t and t from 40 ns to 20 ns, changed t  
, t  
, t , t  
, t  
,
TH  
TL  
TMSS TDIS CS TMSH TDIH  
t
from 10 ns to 5 ns and changed t  
from 20 ns to 10 ns in TAP AC  
CH  
TDOV  
Switching Characteristics table  
Modified Power Up waveform  
*B  
497629  
See ECN  
NXR  
Changed the V  
operating voltage to 1.4V to V in the Features section, in  
DDQ DD  
Operating Range table and in the DC Electrical Characteristics table  
Added foot note in page 1  
Changed the Maximum rating of Ambient Temperature with Power Applied from  
–10°C to +85°C to –55°C to +125°C  
Changed V  
(max) spec from 0.85V to 0.95V in the DC Electrical Character-  
REF  
istics table and in the note below the table  
Updated foot note 21 to specify Overshoot and Undershoot Spec  
Updated Θ and Θ values  
JA  
JC  
Removed x9 part and its related information  
Updated foot note 24  
*C  
1175245  
See ECN VKN/KKVTMP Converted from preliminary to final  
Added x8 and x9 parts  
Updated logic block diagram for x18 and x36 parts  
Changed I values from 830 mA to 1080 mA for 400 MHz, 794 mA to 1020 mA  
DD  
for 375 MHz, 733 mA to 920 mA for 333 MHz, 685 mA to 850 mA for 300 MHz  
Changed I values from 235 mA to 300 mA for 400 MHz, 227 mA to 290 mA  
SB  
for 375 MHz, 212 mA to 260 mA for 333 MHz, 201 mA to 250 mA for 300 MHz  
Changed t  
spec to 8.4 ns for all speed bins  
CYC(max)  
Changed Θ value from 13.48 °C/W to 17.2 °C/W  
JA  
Updated Ordering Information table  
*D  
2199066 See ECN  
VKN/AESA Added footnote# 19 related to I  
DD  
© Cypress Semiconductor Corporation, 2006-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of  
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for  
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as  
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems  
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),  
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,  
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress  
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without  
the express written permission of Cypress.  
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES  
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not  
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where  
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer  
assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
Use may be limited by and subject to the applicable Cypress software license agreement.  
Document Number: 001-06620 Rev. *D  
Revised March 06, 2008  
Page 27 of 27  
QDR™ is a trademark of Cypress Semiconductor Corp. QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All  
product and company names mentioned in this document are the trademarks of their respective holders.  

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