Cypress CY62167DV18 User Manual

CY62167DV18 MoBL®  
16-Mbit (1M x 16) Static RAM  
consumption by more than 99% when deselected (CE HIGH  
Features  
1
or CE LOW or both BHE and BLE are HIGH). The input and  
2
• Very high speed: 55 ns  
output pins (IO through IO ) are placed in a high impedance  
state when:  
0
15  
• Wide voltage range: 1.65V–1.95V  
• Ultra low active power  
• Deselected (CE HIGH or CE LOW)  
1
2
• Outputs are disabled (OE HIGH)  
— Typical active current: 1.5 mA @ f = 1 MHz  
• Both Byte High Enable (BHE) and Byte Low Enable (BLE)  
are disabled (BHE, BLE HIGH)  
— Typical active current: 15 mA @ f = f  
• Ultra low standby power  
max  
• Write operation is active (CE LOW, CE HIGH and WE  
1
2
• Easy memory expansion with CE , CE , and OE features  
LOW)  
1
2
• Automatic power down when deselected  
• CMOS for optimum speed and power  
• Available in Pb-free 48-ball VFBGA package  
To write to the device, take Chip Enables (CE LOW and CE  
1
2
HIGH) and Write Enable (WE) input LOW. If BLE is LOW, then  
data from IO pins (IO through IO ) is written into the location  
0
7
specified on the address pins (A through A ). If BHE is LOW  
0
19  
Functional Description[1]  
8
15  
then data from IO pins (IO through IO ) is written into the  
location specified on the address pins (A through A ).  
0
19  
The CY62167DV18 is a high performance CMOS static RAM  
organized as 1M words by 16 bits. This device features  
advanced circuit design to provide ultra low active current.  
To read from the device, take Chip Enables (CE LOW and  
1
CE HIGH) and OE LOW while forcing the WE HIGH. If BLE  
2
is LOW, then data from the memory location specified by the  
®
This is ideal for providing More Battery Life(MoBL ) in  
address pins appear on IO to IO . If BHE is LOW, then data  
0
7
portable applications such as cellular telephones. The device  
also has an automatic power down feature that significantly  
reduces power consumption by 99% when addresses are not  
toggling. Placing the device into standby mode reduces power  
from memory appears on IO to IO . See the “Truth Table” on  
8
15  
page 9 for a complete description of read and write modes.  
Logic Block Diagram  
DATA IN DRIVERS  
A
A
A
A
A
A
A
A
A
A
A
10  
9
8
7
6
1M × 16  
RAM Array  
5
4
3
2
1
0
IO –IO  
0
7
IO –IO  
8
15  
COLUMN DECODER  
BYTE  
BHE  
WE  
CE2  
CE1  
OE  
PowerDown  
Circuit  
BLE  
CE2  
CE1  
BHE  
BLE  
Note  
1. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” at http://www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 38-05326 Rev. *C  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised April 25, 2007  
 
CY62167DV18 MoBL®  
DC Input Voltage  
........................–0.2V to V  
+ 0.2V  
Maximum Ratings  
CCmax  
Output Current into Outputs (LOW)............................. 20 mA  
Exceeding the maximum ratings may impair the useful life of  
the device. These user guidelines are not tested.  
Static Discharge Voltage.......................................... > 2001V  
(MIL-STD-883, Method 3015)  
Storage Temperature .................................65°C to +150°C  
Latch up Current.....................................................> 200 mA  
Ambient Temperature with  
Power Applied.............................................55°C to +125°C  
Operating Range  
Supply Voltage to Ground Potential. 0.2V to V  
+ 0.2V  
CCmax  
Ambient  
V
CC  
Range  
DC Voltage Applied to Outputs  
Temperature  
in High-Z State  
........................... –0.2V to V  
+ 0.2V  
CCmax  
Industrial  
–40°C to +85°C  
1.65V to 1.95V  
DC Electrical Characteristics (Over the Operating Range)  
55 ns  
Parameter  
Description  
Output HIGH Voltage  
Output LOW Voltage  
Input HIGH Voltage  
Test Conditions  
= 0.1 mA  
Min  
Typ  
Max  
Unit  
V
I
I
1.4  
V
V
OH  
OH  
OL  
V
V
V
I
= 0.1 mA  
0.2  
OL  
IH  
IL  
1.4  
–0.2  
–1  
V
+ 0.2  
V
CC  
Input LOW Voltage  
0.4  
+1  
+1  
30  
5
V
Input Leakage Current  
Output Leakage Current  
GND < V < V  
CC  
µA  
µA  
mA  
IX  
I
I
GND < V < V , Output Disabled  
–1  
OZ  
O
CC  
I
V
Operating Supply Current  
f = f  
= 1/t  
V
= 1.95V, I = 0 mA,  
OUT  
15  
1.5  
2.5  
CC  
CC  
MAX  
RC  
CC  
CMOS level  
f = 1 MHz  
I
Automatic CE Power down  
Current CMOS Inputs  
CE > V 0.2V, CE < 0.2V,  
20  
µA  
SB1  
1
CC  
2
V
> V 0.2V, V < 0.2V,  
IN  
CC IN  
f = f  
(Address and Data Only),  
MAX  
f = 0 (OE, WE, BHE and BLE)  
I
Automatic CE Power down  
Current CMOS Inputs  
CE > V 0.2V, CE < 0.2V,  
2.5  
20  
µA  
SB2  
1
CC  
2
V
> V 0.2V or V < 0.2V,  
IN  
CC IN  
f = 0, V =1.95V  
CC  
Capacitance [7]  
Parameter  
Description  
Input Capacitance  
Test Conditions  
T = 25°C, f = 1 MHz, V = V  
CC(typ)  
Max  
6
Unit  
C
C
pF  
pF  
IN  
A
CC  
Output Capacitance  
8
OUT  
Notes  
4.  
5.  
V
V
= –2.0V for pulse durations less than 20 ns.  
IL(min)  
= V + 0.75V for pulse durations less than 20 ns.  
IH(max)  
CC  
6. Full device AC operation requires linear V ramp from 0 to V  
7. Tested initially and after any design or process changes that may affect these parameters.  
and V must be stable at V for 500 µs.  
CC(min)  
CC  
CC(min)  
CC  
Document #: 38-05326 Rev. *C  
Page 3 of 11  
       
CY62167DV18 MoBL®  
Thermal Resistance [7]  
Parameter  
Description  
Test Conditions  
VFBGA  
Unit  
Θ
Thermal Resistance  
(Junction to Ambient)  
Still Air, soldered on a 3 × 4.5 inch,  
two-layer printed circuit board  
55  
°C/W  
JA  
Θ
Thermal Resistance  
(Junction to Case)  
16  
°C/W  
JC  
AC Test Loads and Waveforms  
R1  
ALL INPUT PULSES  
90%  
10%  
V
CC  
V
CC  
OUTPUT  
90%  
10%  
Rise Time = 1 V/ns  
GND  
R2  
30 pF  
Fall Time = 1 V/ns  
INCLUDING  
JIG AND  
SCOPE  
Equivalent to:  
OUTPUT  
THEVENIN EQUIVALENT  
R
TH  
V
Parameters  
1.8V  
13500  
10800  
6000  
0.80  
Unit  
R1  
R2  
R
TH  
TH  
V
V
Data Retention Characteristics (Over the Operating Range)  
Parameter  
Description  
Conditions  
Min Typ  
Max Unit  
V
V
for Data Retention  
1.0  
1.95  
10  
V
DR  
CC  
V
V
= 1.0V,  
CE > V – 0.2V, CE < 0.2V,  
I
Data Retention Current  
µA  
CC  
CCDR  
1
CC  
2
> V – 0.2V or V < 0.2V  
IN  
CC  
IN  
t
t
Chip Deselect to Data Retention Time  
Operation Recovery Time  
0
ns  
ns  
CDR  
R
t
RC  
Data Retention Waveform[9]  
DATA RETENTION MODE  
V
, min  
V
> 1.0V  
V
V
, min  
CC  
CC  
CC  
DR  
t
t
CDR  
R
CE or  
1
BHE,BLE  
or  
CE  
2
Notes  
8. Full device operation requires linear V ramp from V to V  
9. BHE.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling the chip enable signals or by disabling both BHE and BLE.  
> 100 µs or stable at V > 100 µs.  
CC(min)  
CC  
DR  
CC(min)  
Document #: 38-05326 Rev. *C  
Page 4 of 11  
     
CY62167DV18 MoBL®  
Switching Characteristics (Over the Operating Range)  
55 ns  
Parameter  
Read Cycle  
Description  
Unit  
Min  
55  
Max  
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Read Cycle Time  
ns  
RC  
Address to Data Valid  
55  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
AA  
Data Hold from Address Change  
CE LOW and CE HIGH to Data Valid  
10  
OHA  
ACE  
DOE  
LZOE  
HZOE  
LZCE  
HZCE  
PU  
55  
25  
1
2
OE LOW to Data Valid  
OE LOW to LOW Z  
5
10  
0
OE HIGH to High Z  
CE LOW and CE HIGH to Low Z  
20  
20  
1
2
CE HIGH and CE LOW to High Z  
1
2
CE LOW and CE HIGH to Power up  
1
2
CE HIGH and CE LOW to Power down  
55  
55  
PD  
1
2
BLE/BHE LOW to Data Valid  
DBE  
LZBE  
HZBE  
BLE/BHE LOW to Low Z  
5
BLE/BHE HIGH to HIGH Z  
20  
Write Cycle  
t
t
t
t
t
t
t
t
t
t
t
Write Cycle Time  
55  
40  
40  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
WC  
CE LOW and CE HIGH to Write End  
SCE  
AW  
1
2
Address Setup to Write End  
Address Hold from Write End  
Address Setup to Write Start  
WE Pulse Width  
HA  
0
SA  
40  
45  
25  
0
PWE  
BW  
BLE/BHE LOW to Write End  
Data Setup to Write End  
Data Hold from Write End  
SD  
HD  
WE LOW to High-  
20  
HZWE  
LZWE  
WE HIGH to Low-Z  
10  
Notes  
10. Test conditions for all parameters other than tri-state parameters assume signal transition time of 1 ns/V, timing reference levels of V  
/2, input pulse levels  
CC(typ)  
of 0 to V  
, and output loading of the specified I /I as shown in “AC Test Loads and Waveforms” on page 4.  
CC(typ)  
OL OH  
11. At any given temperature and voltage condition, t  
is less than t  
, t  
is less than t  
, t  
is less than t  
, and t  
is less than t  
for any  
HZCE  
LZCE HZBE  
LZBE HZOE  
LZOE  
HZWE  
LZWE  
given device.  
12. t  
, t  
, t  
, and t  
transitions are measured when the outputs enter a high impedance state.  
HZOE HZCE HZBE  
HZWE  
13. The internal write time of the memory is defined by the overlap of WE, CE = V , BHE, BLE or both = V , and CE = V . All signals must be ACTIVE to initiate  
1
IL  
IL  
2
IH  
a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that  
terminates the write.  
Document #: 38-05326 Rev. *C  
Page 5 of 11  
       
CY62167DV18 MoBL®  
Switching Waveforms  
Read Cycle 1 (Address Transition Controlled)  
t
RC  
ADDRESS  
t
AA  
t
OHA  
DATA OUT  
PREVIOUS DATA VALID  
DATA VALID  
Read Cycle 2 (OE Controlled)  
ADDRESS  
tRC  
CE1  
CE2  
tPD  
t
HZCE  
tACE  
BHE/BLE  
OE  
tDBE  
tHZBE  
tLZBE  
tHZOE  
tDOE  
tLZOE  
HIGH  
IMPEDANCE  
HIGH IMPEDANCE  
DATA OUT  
VCC  
SUPPLY  
CURRENT  
DATA VALID  
tLZCE  
ICC  
ISB  
tPU  
50%  
50%  
Notes  
14. The device is continuously selected. OE, CE = V , BHE and/or BLE = V , and CE = V .  
IH  
1
IL  
IL  
2
15. WE is HIGH for read cycle.  
16. Address valid before or similar to CE , BHE, BLE transition LOW and CE transition HIGH.  
1
2
Document #: 38-05326 Rev. *C  
Page 6 of 11  
     
CY62167DV18 MoBL®  
Switching Waveforms (continued)  
Write Cycle 1 (WE Controlled)  
tWC  
ADDRESS  
CE1  
tSCE  
CE2  
tAW  
tHA  
tSA  
tPWE  
WE  
tBW  
BHE/BLE  
OE  
tHD  
tSD  
DATA IO  
NOTE 19  
VALID DATA  
tHZOE  
[13, 17, 18]  
Write Cycle 2 (CE or CE Controlled)  
1
2
tWC  
ADDRESS  
CE1  
tSCE  
CE2  
tSA  
tAW  
tHA  
tPWE  
WE  
tBW  
BHE/BLE  
OE  
tHD  
tSD  
DATA IO  
VALID DATA  
tHZOE  
Notes  
17. Data IO is high impedance if OE = V  
.
IH  
18. If CE goes HIGH and CE goes LOW simultaneously with WE = V , the output remains in a high impedance state.  
1
2
IH  
19. During this period, the IOs are in output state. Do not apply input signals.  
Document #: 38-05326 Rev. *C  
Page 7 of 11  
     
CY62167DV18 MoBL®  
Switching Waveforms (continued)  
Write Cycle 3 (WE Controlled, OE LOW)  
tWC  
ADDRESS  
CE1  
tSCE  
CE2  
tBW  
BHE/BLE  
tAW  
tHA  
tSA  
tPWE  
WE  
tSD  
tHD  
DATA IO  
VALID DATA  
tLZWE  
t
HZWE  
Write Cycle 4 (BHE/BLE Controlled, OE LOW)  
tWC  
ADDRESS  
CE1  
CE2  
tSCE  
tAW  
tHA  
tBW  
BHE/BLE  
tSA  
tPWE  
WE  
tSD  
tHD  
DATA IO  
VALID DATA  
Document #: 38-05326 Rev. *C  
Page 8 of 11  
CY62167DV18 MoBL®  
Truth Table  
CE  
H
X
CE  
WE  
X
OE  
X
BHE  
X
BLE  
X
Inputs/Outputs  
High Z  
Mode  
Deselect/Power Down  
Deselect/Power Down  
Deselect/Power Down  
Read  
Power  
Standby (I  
Standby (I  
Standby (I  
1
2
X
)
SB  
L
X
X
X
X
High Z  
High Z  
)
SB  
X
X
X
X
H
H
)
SB  
L
H
H
H
L
L
L
Data Out (IO –IO  
)
Active (I  
Active (I  
)
CC  
0
15  
L
H
L
H
L
High Z (IO –IO );  
Read  
)
CC  
8
15  
Data Out (IO –IO )  
0
7
L
H
H
L
L
H
Data Out (IO –IO );  
Read  
Active (I  
)
CC  
8
15  
High Z (IO –IO )  
0
7
L
L
H
H
L
L
X
X
L
L
L
Data In (IO –IO  
)
Write  
Write  
Active (I  
Active (I  
)
CC  
0
15  
H
High Z (IO –IO );  
)
CC  
8
15  
Data In (IO –IO )  
0
7
L
H
L
X
L
H
Data In (IO –IO );  
Write  
Active (I  
)
CC  
8
15  
High Z (IO –IO )  
0
7
L
L
L
H
H
H
H
H
H
H
H
H
L
H
L
H
L
L
High Z  
High Z  
High Z  
Output Disabled  
Output Disabled  
Output Disabled  
Active (I  
Active (I  
Active (I  
)
CC  
)
CC  
)
CC  
Ordering Information  
Speed  
(ns)  
Package  
Diagram  
Operating  
Range  
Ordering Code  
Package Type  
55  
CY62167DV18LL-55BVXI 51-85178 48-ball Fine Pitch BGA (8 x 9.5 x 1 mm) (Pb-free)  
Industrial  
Document #: 38-05326 Rev. *C  
Page 9 of 11  
 
CY62167DV18 MoBL®  
Package Diagrams  
Figure 1. 48-Ball VFBGA (8 x 9.5 x 1 mm), 51-85178  
BOTTOM VIEW  
A1 CORNER  
TOP VIEW  
Ø0.05 M C  
Ø0.25 M C A B  
Ø0.30 0.05(48X)  
A1 CORNER  
1
2
3
4
5
6
6
5
4
3
2
1
A
A
B
C
D
B
C
D
E
E
F
F
G
G
H
H
1.875  
A
A
0.75  
B
8.00 0.10  
3.75  
B
8.00 0.10  
0.15(4X)  
SEATING PLANE  
C
51-85178-**  
MoBL is a registered trademark, and More Battery Life is a trademark of Cypress Semiconductor. All product and company names  
mentioned in this document are the trademarks of their respective holders.  
Document #: 38-05326 Rev. *C  
Page 10 of 11  
© Cypress Semiconductor Corporation, 2002-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the  
use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to  
be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its  
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
CY62167DV18 MoBL®  
Document History Page  
®
Document Title: CY62167DV18 MoBL , 16-Mbit (1M x 16) Static RAM  
Document Number: 38-05326  
Orig. of  
Change  
REV.  
ECN NO. Issue Date  
Description of Change  
**  
118406  
123690  
09/30/02  
02/11/03  
GUG  
New Data Sheet  
*A  
DPM  
Changed Advance to Preliminary  
Added package diagram  
*B  
*C  
126554  
04/25/03  
DPM  
VKN  
Minor Change: Changed sunset owner from DPM to HRT  
1015643 See ECN  
Converted from preliminary to final  
Removed “L” parts  
Removed 70 ns speed bin  
Updated footnote #3  
Updated Ordering Information table  
Document #: 38-05326 Rev. *C  
Page 11 of 11  

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