Cypress CY62138FV30 User Manual

CY62138FV30 MoBL®  
2-Mbit (256K x 8) Static RAM  
Features  
Functional Description [1]  
• Very high speed: 45 ns  
The CY62138FV30 is a high performance CMOS static RAM  
organized as 256K words by 8 bits. This device features  
advanced circuit design to provide ultra low active current.  
• Wide voltage range: 2.20V–3.60V  
• Pin compatible with CY62138CV25/30/33  
• Ultra low standby power  
®
This is ideal for providing More Battery Life™ (MoBL ) in  
portable applications such as cellular telephones. The device  
also has an automatic power down feature that significantly  
reduces power consumption. Place the device into standby  
— Typical standby current: 1 µA  
— Maximum standby current: 5 µA  
• Ultra low active power  
mode reducing power consumption when deselected (CE  
1
HIGH or CE LOW).  
2
— Typical active current: 1.6 mA @ f = 1 MHz  
To write to the device, take Chip Enable (CE LOW and CE  
HIGH) and Write Enable (WE) inputs LOW. Data on the eight  
1
2
• Easy memory expansion with CE , CE and OE features  
1
2,  
IO pins (IO through IO ) is then written into the location  
0
7
• Automatic power down when deselected  
• CMOS for optimum speed and power  
specified on the address pins (A through A ).  
0
17  
To read from the device, take Chip Enable (CE LOW and CE  
1
2
• Offered in Pb-free 36-ball VFBGA, 32-pin TSOP II, 32-pin  
SOIC, 32-pin TSOP I and 32-pin STSOP packages  
HIGH) and Output Enable (OE) LOW while forcing Write  
Enable (WE) HIGH. Under these conditions, the contents of  
the memory location specified by the address pins appear on  
the IO pins.  
The eight input and output pins (IO through IO ) are placed  
0
7
in a high impedance state when the device is deselected (CE  
1
HIGH or CE LOW), the outputs are disabled (OE HIGH), or  
2
during a write operation (CE LOW and CE HIGH and WE  
1
2
LOW).  
Logic Block Diagram  
IO  
DATA IN DRIVERS  
0
A
A
A
A
A
A
A
A
A
0
1
2
3
4
5
6
7
8
IO  
IO  
IO  
IO  
IO  
IO  
IO  
1
2
3
4
5
6
7
256K x 8  
ARRAY  
A
A
A
9
10  
11  
CE  
CE  
1
2
POWER  
DOWN  
COLUMN DECODER  
WE  
OE  
Note  
1. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” at http://www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 001-08029 Rev. *E  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised March 26, 2007  
 
CY62138FV30 MoBL®  
DC Input Voltage  
.......................................–0.3V to 3.9V  
Maximum Ratings  
Output Current into Outputs (LOW)............................. 20 mA  
Exceeding maximum ratings may impair the useful life of the  
device. These user guidelines are not tested.  
Static Discharge Voltage.......................................... > 2001V  
(MIL-STD-883, Method 3015)  
Storage Temperature ..................................65°C to +150°C  
Latch-up Current .................................................... > 200 mA  
Ambient Temperature with  
Power Applied...............................................55°C to +125°C  
Ambient  
Product  
Range  
V
CC  
Supply Voltage to Ground  
Potential........................................................... –0.3V to 3.9V  
Temperature  
CY62138FV30LL Industrial –40°Cto+85°C 2.2V to 3.6V  
DC Voltage Applied to Outputs  
in High-Z State  
.......................................... –0.3V to 3.9V  
Electrical Characteristics (Over the Operating Range)  
45 ns  
Parameter  
Description  
Test Conditions  
= –0.1 mA  
Unit  
Min  
2.0  
2.4  
Typ  
Max  
V
Output HIGH Voltage  
I
I
I
I
V
V
OH  
OL  
IH  
OH  
OH  
OL  
OL  
= –1.0 mA, V > 2.70V  
CC  
V
V
V
Output LOW Voltage  
Input HIGH Voltage  
Input LOW Voltage  
= 0.1 mA  
0.4  
0.4  
V
= 2.1 mA, V > 2.70V  
V
CC  
V
V
V
V
V
= 2.2V to 2.7V  
1.8  
2.2  
V
V
+ 0.3V  
V
CC  
CC  
CC  
CC  
CC  
CC  
CC  
= 2.7V to 3.6V  
+ 0.3V  
0.6  
V
= 2.2V to 2.7V For BGA package  
= 2.7V to 3.6V  
–0.3  
–0.3  
–0.3  
–1  
V
IL  
0.8  
V
= 2.2V to 3.6V For other packages  
0.6  
V
I
Input Leakage Current  
Output Leakage Current  
GND < V < V  
CC  
+1  
µA  
µA  
IX  
I
I
GND < V < V ,  
CC  
–1  
+1  
OZ  
O
output disabled  
I
V
Operating Supply Current f = f = 1/t  
V
= V  
CCmax  
= 0 mA  
13  
18  
mA  
CC  
CC  
max  
RC  
CC  
I
OUT  
f = 1 MHz  
1.6  
2.5  
CMOS levels  
I
I
Automatic CE Power Down  
Current CMOS Inputs  
CE > V – 0.2V or CE < 0.2V,  
1
5
µA  
SB1  
1
CC  
2
V
> V – 0.2V, V < 0.2V),  
CC IN  
IN  
f = f  
(address and data only),  
max  
f = 0 (OE, and WE), V = 3.60V  
CC  
[7]  
Automatic CE Power Down  
Current CMOS Inputs  
CE > V – 0.2V or CE < 0.2V,  
1
5
µA  
SB2  
1
CC  
2
V
> V – 0.2V or V < 0.2V,  
CC IN  
IN  
f = 0, V = 3.60V  
CC  
Capacitance (For all packages)  
Parameter  
Description  
Test Conditions  
T = 25°C, f = 1 MHz,  
Max  
Unit  
C
C
Input Capacitance  
Output Capacitance  
10  
10  
pF  
pF  
IN  
OUT  
A
V
= V  
CC  
CC(typ.)  
Notes  
4.  
5.  
V
V
= 2.0V for pulse durations less than 20 ns.  
IL(min)  
= V +0.75V for pulse durations less than 20 ns.  
IH(max)  
CC  
6. Full device AC operation assumes a 100 µs ramp time from 0 to V (min) and 200 µs wait time after V stabilization.  
CC  
CC  
7. Only chip enables (CE and CE ) must be at CMOS level to meet the I / I spec. Other inputs can be left floating.  
SB2 CCDR  
1
2
8. Tested initially and after any design or process changes that may affect these parameters.  
Document #: 001-08029 Rev. *E  
Page 3 of 13  
         
CY62138FV30 MoBL®  
Thermal Resistance [8]  
Parameter  
Description  
Test Conditions  
SOIC  
VFBGA TSOP II STSOP TSOP I Unit  
Θ
Thermal Resistance Still air, soldered on a 3 x 4.5  
(Junction to Ambient) inch, two layer printed circuit  
44.53  
38.49  
44.16  
59.72  
50.19 °C/W  
JA  
board  
Θ
Thermal Resistance  
(Junction to Case)  
24.05  
17.66  
11.97  
15.38  
14.59 °C/W  
JC  
AC Test Loads and Waveforms  
R1  
ALL INPUT PULSES  
90%  
V
CC  
V
OUTPUT  
CC  
90%  
10%  
10%  
R2  
GND  
Rise Time = 1 V/ns  
30 pF  
Fall Time = 1 V/ns  
INCLUDING  
JIG AND  
SCOPE  
Equivalent to:  
THEVENIN EQUIVALENT  
R
TH  
OUTPUT  
V
Parameters  
2.5V (2.2V to 2.7V)  
3.0V (2.7V to 3.6V)  
Unit  
R1  
R2  
16667  
15385  
8000  
1.20  
1103  
1554  
645  
R
TH  
V
1.75  
V
TH  
Data Retention Characteristics (Over the Operating Range)  
Parameter  
Description  
Conditions  
Min  
Typ  
Max  
Unit  
V
V
I
V
for Data Retention  
1.5  
DR  
CC  
[7]  
Data Retention Current  
V
= 1.5V,  
CC  
1
4
µA  
CCDR  
CE > V 0.2V or CE < 0.2V,  
1
CC  
2
V
> V 0.2V or V < 0.2V  
CC IN  
IN  
t
t
Chip Deselect to Data Retention Time  
Operation Recovery Time  
0
ns  
ns  
CDR  
R
t
RC  
Data Retention Waveform [10]  
DATA RETENTION MODE  
> 1.5V  
V
V
CC(min)  
V
CC(min)  
VCC  
CE  
DR  
t
t
R
CDR  
Notes:  
9. Full device AC operation requires linear V ramp from V to V  
> 100 µs or stable at V  
> 100 µs.  
CC  
DR  
CC(min)  
CC(min)  
10. CE is the logical combination of CE and CE . When CE is LOW and CE is HIGH, CE is LOW; when CE is HIGH or CE is LOW, CE is HIGH.  
1
2
1
2
1
2
Document #: 001-08029 Rev. *E  
Page 4 of 13  
     
CY62138FV30 MoBL®  
Switching Characteristics (Over the Operating Range)  
45 ns  
Parameter  
Read Cycle  
Description  
Unit  
Min  
Max  
t
t
t
t
t
t
t
t
t
t
t
Read Cycle Time  
45  
10  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
RC  
Address to Data Valid  
45  
AA  
Data Hold from Address Change  
CE LOW and CE HIGH to Data Valid  
OHA  
ACE  
DOE  
LZOE  
HZOE  
LZCE  
HZCE  
PU  
45  
22  
1
2
OE LOW to Data Valid  
OE LOW to Low-Z  
5
10  
0
OE HIGH to High-Z  
18  
18  
45  
CE LOW and CE HIGH to Low Z  
1
2
CE HIGH or CE LOW to High-Z  
1
2
CE LOW and CE HIGH to Power Up  
1
2
CE HIGH or CE LOW to Power Down  
PD  
1
2
Write Cycle  
t
t
t
t
t
t
t
t
t
t
Write Cycle Time  
45  
35  
35  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
WC  
CE LOW and CE HIGH to Write End  
SCE  
AW  
1
2
Address Setup to Write End  
Address Hold from Write End  
Address Setup to Write Start  
WE Pulse Width  
HA  
0
SA  
35  
25  
0
PWE  
SD  
Data Setup to Write End  
Data Hold from Write End  
HD  
WE LOW to High-Z  
18  
HZWE  
LZWE  
WE HIGH to Low-Z  
10  
Notes  
11. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less (1 V/ns), timing reference levels of V  
/2, input  
CC(typ)  
pulse levels of 0 to V  
, and output loading of the specified I /I as shown in the ““AC Test Loads and Waveforms” on page 4” .  
CC(typ)  
OL OH  
12. At any given temperature and voltage condition, t  
is less than t  
, t  
is less than t  
, and t  
is less than t  
for any given device.  
HZCE  
LZCE HZOE  
LZOE  
HZWE  
LZWE  
13. t  
, t  
, and t  
transitions are measured when the output enters a high impedance state.  
HZOE HZCE  
HZWE  
14. The internal write time of the memory is defined by the overlap of WE, CE = V , and CE = V . All signals must be ACTIVE to initiate a write and any of these  
1
IL  
2
IH  
signals can terminate a write by going INACTIVE. Reference the data input setup and hold timing to the edge of the signal that terminates the write.  
Document #: 001-08029 Rev. *E  
Page 5 of 13  
       
CY62138FV30 MoBL®  
Switching Waveforms  
Read Cycle 1 (Address transition controlled)  
tRC  
ADDRESS  
t
AA  
t
OHA  
DATA OUT  
PREVIOUS DATA VALID  
DATA VALID  
[10, 16, 17]  
Read Cycle No. 2 (OE controlled)  
ADDRESS  
t
RC  
CE  
OE  
t
ACE  
t
HZOE  
t
DOE  
t
HZCE  
t
LZOE  
HIGH  
IMPEDANCE  
HIGH IMPEDANCE  
DATA VALID  
DATA OUT  
t
LZCE  
t
PD  
ICC  
t
V
CC  
PU  
50%  
SUPPLY  
CURRENT  
50%  
ISB  
Write Cycle No. 1 (WE controlled)  
t
WC  
ADDRESS  
CE  
t
SCE  
t
t
HA  
AW  
t
SA  
t
PWE  
WE  
OE  
t
t
SD  
HD  
DATA IO  
NOTE  
DATA VALID  
t
HZOE  
Notes:  
15. The device is continuously selected. OE, CE = V , CE = V  
.
1
IL  
2
IH  
16. WE is HIGH for read cycle.  
17. Address valid before or similar to CE transition LOW and CE transition HIGH.  
1
2
18. Data IO is high impedance if OE = V  
.
IH  
19. If CE goes HIGH or CE goes LOW simultaneously with WE HIGH, the output remains in high impedance state.  
1
2
20. During this period, the IOs are in output state. Do not apply input signals.  
Document #: 001-08029 Rev. *E  
Page 6 of 13  
           
CY62138FV30 MoBL®  
Switching Waveforms (continued)  
Write Cycle No. 2 (CE1 or CE2 controlled)  
t
WC  
ADDRESS  
CE  
t
SCE  
t
SA  
t
t
AW  
HA  
t
PWE  
WE  
t
t
HD  
SD  
DATA IO  
DATA VALID  
Write Cycle No. 3 (WE controlled, OE LOW)  
t
WC  
ADDRESS  
CE  
t
SCE  
t
t
HA  
AW  
t
SA  
t
PWE  
WE  
t
t
HD  
SD  
NOTE  
DATA VALID  
DATA IO  
t
t
LZWE  
HZWE  
Truth Table  
CE  
H
X
CE  
WE  
X
OE  
X
Inputs/Outputs  
Mode  
Power  
1
2
X
High-Z  
High-Z  
Deselect/Power Down  
Deselect/Power Down  
Read  
Standby (I  
Standby (I  
)
SB  
SB  
L
X
X
)
L
H
H
L
Data Out  
High-Z  
Active (I  
Active (I  
Active (I  
)
)
)
CC  
CC  
CC  
L
H
H
H
X
Output Disabled  
Write  
L
H
L
Data in  
Document #: 001-08029 Rev. *E  
Page 7 of 13  
CY62138FV30 MoBL®  
Ordering Information  
Speed  
(ns)  
Package  
Diagram  
Operating  
Range  
Ordering Code  
Package Type  
45  
CY62138FV30LL-45BVXI 51-85149 36-ball VFBGA (Pb-free)  
CY62138FV30LL-45ZSXI 51-85095 32-pin TSOP II (Pb-free)  
CY62138FV30LL-45ZAXI 51-85094 32-pin STSOP (Pb-free)  
Industrial  
CY62138FV30LL-45ZXI  
CY62138FV30LL-45SXI  
51-85056 32-pin TSOP I (Pb-free)  
51-85081 32-pin SOIC (Pb-free)  
Package Diagrams  
Figure 1. 36-ball VFBGA (6 x 8 x 1 mm), 51-85149  
BOTTOM VIEW  
A1 CORNER  
TOP VIEW  
Ø0.05 M C  
Ø0.25 M C A B  
Ø0.30 0.05(36X)  
A1 CORNER  
1
2
3
4
5
6
6
5
4
3
2
1
A
A
B
C
D
B
C
D
E
E
F
F
G
G
H
H
1.875  
A
A
0.75  
B
6.00 0.10  
3.75  
B
6.00 0.10  
0.15(4X)  
SEATING PLANE  
C
51-85149-*C  
Document #: 001-08029 Rev. *E  
Page 8 of 13  
CY62138FV30 MoBL®  
Package Diagrams (continued)  
Figure 2. 32-pin TSOP II, 51-85095  
51-85095-**  
Document #: 001-08029 Rev. *E  
Page 9 of 13  
CY62138FV30 MoBL®  
Package Diagrams (continued)  
Figure 3. 32-pin (450 Mil) Molded SOIC, 51-85081  
16  
1
0.546[13.868]  
0.566[14.376]  
0.440[11.176]  
0.450[11.430]  
17  
32  
0.793[20.142]  
0.817[20.751]  
0.006[0.152]  
0.012[0.304]  
0.101[2.565]  
0.111[2.819]  
0.118[2.997]  
MAX.  
0.004[0.102]  
0.047[1.193]  
0.004[0.102]  
0.063[1.600]  
0.023[0.584]  
0.039[0.990]  
0.050[1.270]  
MIN.  
BSC.  
0.014[0.355]  
0.020[0.508]  
SEATING PLANE  
51-85081-*B  
Document #: 001-08029 Rev. *E  
Page 10 of 13  
CY62138FV30 MoBL®  
Package Diagrams (continued)  
Figure 4. 32-pin TSOP I (8 x 20 mm), 51-85056  
51-85056-*D  
Document #: 001-08029 Rev. *E  
Page 11 of 13  
CY62138FV30 MoBL®  
Package Diagrams (continued)  
Figure 5. 32-pin STSOP (8 x 13.4 mm), 51-85094  
51-85094-*D  
MoBL is a registered trademark, and More Battery Life is a trademark of Cypress Semiconductor. All product and company names  
mentioned in this document may be the trademarks of their respective holders.  
Document #: 001-08029 Rev. *E  
Page 12 of 13  
© Cypress Semiconductor Corporation, 2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be  
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its  
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
CY62138FV30 MoBL®  
Document History Page  
®
Document Title: CY62138FV30 MoBL , 2-Mbit (256K x 8) Static RAM  
Document Number: 001-08029  
Issue  
Date  
Orig. of  
Change  
REV.  
ECN NO.  
Description of Change  
**  
463660  
467351  
See ECN  
See ECN  
NXR  
NXR  
New data sheet  
Added 32-pin TSOP II package, 32 pin TSOP I and 32 pin STSOP packages  
*A  
Changed ball A3 from NC to CE in 36-ball FBGA pin out  
2
*B  
566724  
See ECN  
NXR  
Converted from Preliminary to Final  
Corrected typo in 32 pin TSOP II pin configuration diagram on page #2 (changed  
pin 24 from CE to OE and pin 22 from CE to CE )  
1
1
Changed the I  
Changed the I  
Changed the I  
Changed the I  
µA to 4 µA  
value from 2.25 mA to 2.5 mA for test condition f=1 MHz  
CC(max)  
SB2(typ)  
SB2(max)  
CCDR(typ)  
value from 0.5 µA to 1 µA  
value from 2.5 µA to 5 µA  
value from 0.5 µA to 1 µA and I  
value from 2.5  
CCDR(max)  
*C  
797956  
See ECN  
VKN  
Added 32-pin SOIC package  
Updated VIL spec for SOIC, TSOP-II, TSOP-I, and STSOP packages on Electrical  
characteristics table  
*D  
*E  
809101  
940341  
See ECN  
See ECN  
VKN  
VKN  
Corrected typo in the Ordering Information table  
Added footnote #7 related to I  
and I  
CCDR  
SB2  
Document #: 001-08029 Rev. *E  
Page 13 of 13  

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