Analog Devices AD9883A User Manual
110 MSPS/140 MSPS Analog Interface for  
Flat Panel Displays  
a
AD9883A  
FEATURES  
FUNCTIONAL BLOCK DIAGRAM  
140 MSPS Maximum Conversion Rate  
300 MHz Analog Bandwidth  
0.5 V to 1.0 V Analog Input Range  
500 ps p-p PLL Clock Jitter at 110 MSPS  
3.3 V Power Supply  
Full Sync Processing  
Sync Detect for ”Hot Plugging”  
Midscale Clamping  
8
R
G
A/D  
A/D  
A/D  
R
OUTA  
CLAMP  
CLAMP  
CLAMP  
AIN  
8
8
AIN  
G
OUTA  
Power-Down Mode  
B
AIN  
B
OUTA  
Low Power: 500 mW Typical  
4:2:2 Output Format Mode  
MIDSCV  
HSYNC  
DTACK  
HSOUT  
VSOUT  
SOGOUT  
SYNC  
APPLICATIONS  
COAST  
CLAMP  
PROCESSING  
AND CLOCK  
GENERATION  
RGB Graphics Processing  
LCD Monitors and Projectors  
Plasma Display Panels  
Scan Converters  
Microdisplays  
Digital TV  
FILT  
REF  
BYPASS  
REF  
SCL  
SDA  
SERIAL REGISTER  
AND  
POWER MANAGEMENT  
AD9883A  
A
0
range from 12 MHz to 140 MHz. PLL clock jitter is 500 ps p-p  
typical at 140 MSPS. When the COAST signal is presented,  
the PLL maintains its output frequency in the absence of  
HSYNC. A sampling phase adjustment is provided. Data,  
HSYNC and Clock output phase relationships are maintained.  
The AD9883A also offers full sync processing for composite  
sync and sync-on-green applications.  
GENERAL DESCRIPTION  
The AD9883A is a complete 8-bit, 140 MSPS monolithic analog  
interface optimized for capturing RGB graphics signals from  
personal computers and workstations. Its 140 MSPS encode  
rate capability and full power analog bandwidth of 300 MHz  
supports resolutions up to SXGA (1280 × 1024 at 75 Hz).  
The AD9883A includes a 140 MHz triple ADC with internal  
1.25 V reference, a PLL, and programmable gain, offset, and  
clamp control. The user provides only a 3.3 V power supply,  
analog input, and HSYNC and COAST signals. Three-state  
CMOS outputs may be powered from 2.5 V to 3.3 V.  
A clamp signal is generated internally or may be provided by the  
user through the CLAMP input pin. This interface is fully pro-  
grammable via a 2-wire serial interface.  
Fabricated in an advanced CMOS process, the AD9883A is  
provided in a space-saving 80-lead LQFP surface mount plastic  
package and is specified over the 0°C to 70°C temperature range.  
The AD9883A’s on-chip PLL generates a pixel clock from  
HSYNC and COAST inputs. Pixel clock output frequencies  
REV. 0  
Information furnished by Analog Devices is believed to be accurate and  
reliable. However, no responsibility is assumed by Analog Devices for its  
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat  
may result from its use. No license is granted by implication or otherwise  
under any patent or patent rights of Analog Devices.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781/329-4700  
Fax: 781/326-8703  
www.analog.com  
© Analog Devices, Inc., 2001  
AD9883A  
Test  
AD9883AKST-110  
AD9883AKST-140  
Parameter  
Temp Level Min  
Typ  
Max  
Min  
Typ  
Max  
Unit  
DIGITAL OUTPUTS  
Output Voltage, High (VOH  
)
Full  
Full  
Full  
VI  
VI  
IV  
VD – 0.1  
45  
VD – 0.1  
45  
V
V
%
Output Voltage, Low (VOL  
Duty Cycle DATACK  
Output Coding  
)
0.1  
55  
0.1  
55  
50  
Binary  
50  
Binary  
POWER SUPPLY  
VD Supply Voltage  
VDD Supply Voltage  
PVD Supply Voltage  
Full  
Full  
Full  
25°C  
25°C  
25°C  
Full  
Full  
Full  
IV  
IV  
IV  
V
V
V
VI  
VI  
VI  
3.0  
2.2  
3.0  
3.3  
3.3  
3.3  
132  
19  
8
525  
5
3.6  
3.6  
3.6  
3.15  
2.2  
3.0  
3.3  
3.3  
3.3  
180  
26  
11  
650  
5
3.6  
3.6  
3.6  
V
V
V
mA  
mA  
mA  
mW  
mA  
mW  
I
D Supply Current (VD)  
2
IDD Supply Current (VDD  
IPVD Supply Current (PVD  
Total Power Dissipation  
Power-Down Supply Current  
Power-Down Dissipation  
)
)
650  
10  
33  
800  
10  
33  
16.5  
16.5  
DYNAMIC PERFORMANCE  
Analog Bandwidth, Full Power 25°C  
V
V
V
V
V
300  
2
1.5  
44  
43  
300  
2
1.5  
43  
42  
MHz  
ns  
ns  
dB  
dB  
Transient Response  
Overvoltage Recovery Time  
Signal-to-Noise Ratio (SNR)  
(Without Harmonics)  
fIN = 40.7 MHz  
25°C  
25°C  
25°C  
Full  
Crosstalk  
Full  
V
55  
55  
dBc  
THERMAL CHARACTERISTICS  
θ
JC Junction-to-Case  
Thermal Resistance  
V
V
16  
35  
16  
35  
°C/W  
θJA Junction-to-Ambient  
Thermal Resistance  
°C/W  
NOTES  
1VCO Range = 10, Charge Pump Current = 110, PLL Divider = 1693.  
2DATACK Load = 15 pF, Data Load = 5 pF.  
Specifications subject to change without notice.  
–3–  
REV. 0  
AD9883A  
ABSOLUTE MAXIMUM RATINGS*  
EXPLANATION OF TEST LEVELS  
Test Level  
I. 100% production tested.  
VD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 V  
VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 V  
Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . VD to 0.0 V  
VREF IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VD to 0.0 V  
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 V to 0.0 V  
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 20 mA  
Operating Temperature . . . . . . . . . . . . . . . . . –25°C to +85°C  
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C  
Maximum Junction Temperature . . . . . . . . . . . . . . . . . 150°C  
Maximum Case Temperature . . . . . . . . . . . . . . . . . . . . 150°C  
*Stresses above those listed under Absolute Maximum Ratings may cause perma-  
nent damage to the device. This is a stress rating only; functional operation of the  
device at these or any other conditions outside of those indicated in the operation  
sections of this specification is not implied. Exposure to absolute maximum ratings  
for extended periods may affect device reliability.  
II. 100% production tested at 25°C and sample tested at  
specified temperatures.  
III. Sample tested only.  
IV. Parameter is guaranteed by design and characterization testing.  
V. Parameter is a typical value only.  
VI. 100% production tested at 25°C; guaranteed by design and  
characterization testing.  
ORDERING GUIDE  
Temperature  
Range  
Package  
Description  
Package  
Option  
Model  
AD9883AKST-140  
AD9883AKST-110  
AD9883A/PCB  
0°C to 70°C  
0°C to 70°C  
25°C  
Thin Plastic Quad Flatpack  
Thin Plastic Quad Flatpack  
Evaluation Board  
ST-80  
ST-80  
CAUTION  
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily  
accumulate on the human body and test equipment and can discharge without detection. Although  
the AD9883A features proprietary ESD protection circuitry, permanent damage may occur on  
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are  
recommended to avoid performance degradation or loss of functionality.  
WARNING!  
ESD SENSITIVE DEVICE  
–4–  
REV. 0  
AD9883A  
PIN CONFIGURATION  
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61  
1
2
GND  
GREEN <7>  
GREEN <6>  
GREEN <5>  
GREEN <4>  
GREEN <3>  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
GND  
PIN 1  
IDENTIFIER  
V
D
3
REF BYPASS  
4
SDA  
SCL  
A0  
5
6
7
GREEN <2>  
GREEN <1>  
GREEN <0>  
GND  
R
AIN  
8
GND  
9
V
D
AD9883A  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
V
TOP VIEW  
D
(Not to Scale)  
V
GND  
DD  
BLUE <7>  
BLUE <6>  
BLUE <5>  
BLUE <4>  
BLUE <3>  
BLUE <2>  
BLUE <1>  
BLUE <0>  
GND  
SOGIN  
G
AIN  
GND  
V
D
V
D
GND  
B
AIN  
V
D
GND  
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40  
Table I. Complete Pinout List  
Pin  
Type  
Pin  
Number  
Mnemonic  
Function  
Value  
I
nputs  
RAIN  
GAIN  
BAIN  
HSYNC  
VSYNC  
SOGIN  
CLAMP  
COAST  
Analog Input for Converter R  
Analog Input for Converter G  
Analog Input for Converter B  
Horizontal SYNC Input  
Vertical SYNC Input  
Input for Sync-on-Green  
0.0 V to 1.0 V  
0.0 V to 1.0 V  
0.0 V to 1.0 V  
3.3 V CMOS  
3.3 V CMOS  
0.0 V to 1.0 V  
3.3 V CMOS  
3.3 V CMOS  
54  
48  
43  
30  
31  
49  
38  
29  
Clamp Input (External CLAMP Signal)  
PLL COAST Signal Input  
Outputs  
Red [7:0]  
Green [7:0]  
Blue [7:0]  
DATACK  
HSOUT  
VSOUT  
SOGOUT  
Outputs of Converter “Red,” Bit 7 is the MSB  
Outputs of Converter “Green,” Bit 7 is the MSB  
Outputs of Converter “Blue,” Bit 7 is the MSB  
Data Output Clock  
HSYNC Output (Phase-Aligned with DATACK)  
VSYNC Output (Phase-Aligned with DATACK)  
Sync on Green Slicer Output  
3.3 V CMOS  
3.3 V CMOS  
3.3 V CMOS  
3.3 V CMOS  
3.3 V CMOS  
3.3 V CMOS  
3.3 V CMOS  
70–77  
2–9  
12–19  
67  
66  
64  
65  
References  
REF BYPASS Internal Reference Bypass  
1.25 V  
58  
37  
33  
MIDSCV  
Internal Midscale Voltage Bypass  
Connection for External Filter Components for Internal PLL  
FILT  
Power Supply VD  
Analog Power Supply  
3.3 V  
3.3 V  
26, 27, 39, 42,  
45, 46, 51, 52,  
59, 62  
VDD  
Output Power Supply  
11, 22, 23, 69,  
78, 79  
PVD  
GND  
PLL Power Supply  
Ground  
3.3 V  
0 V  
34, 35  
1, 10, 20, 21,  
24, 25, 28, 32,  
36, 40, 41, 44,  
47, 50, 53, 60,  
61, 63, 68, 80  
Control  
SDA  
SCL  
A0  
Serial Port Data I/O  
Serial Port Data Clock (100 kHz Maximum)  
Serial Port Address Input 1  
3.3 V CMOS  
3.3 V CMOS  
3.3 V CMOS  
57  
56  
55  
–5–  
REV. 0  
AD9883A  
PIN FUNCTION DESCRIPTIONS  
Pin Name  
Function  
OUTPUTS  
HSOUT  
Horizontal Sync Output  
A reconstructed and phase-aligned version of the Hsync input. Both the polarity and duration of this output can be  
programmed via serial bus registers. By maintaining alignment with DATACK, and Data, data timing with respect  
to horizontal sync can always be determined.  
VSOUT  
Vertical Sync Output  
A reconstructed and phase-aligned version of the video Vsync. The polarity of this output can be controlled via a  
serial bus bit. The placement and duration in all modes is set by the graphics transmitter.  
SOGOUT  
Sync-On-Green Slicer Output  
This pin outputs either the signal from the Sync-on-Green slicer comparator or an unprocessed but delayed version  
of the Hsync input. See the Sync Processing Block Diagram (Figure 12) to view how this pin is connected.  
(Note: Besides slicing off SOG, the output from this pin gets no other additional processing on the AD9883A.  
Vsync separation is performed via the sync separator.)  
SERIAL PORT  
(Two-Wire)  
SDA  
Serial Port Data I/O  
SCL  
Serial Port Data Clock  
A0  
Serial Port Address Input 1  
For a full description of the two-wire serial register and how it works, refer to the Two-Wire Serial Control Port section.  
DATA OUTPUTS  
RED  
Data Output, RED Channel  
GREEN  
BLUE  
Data Output, GREEN Channel  
Data Output, BLUE Channel  
The main data outputs. Bit 7 is the MSB. The delay from pixel sampling time to output is fixed. When the sampling  
time is changed by adjusting the PHASE register, the output timing is shifted as well. The DATACK and HSOUT  
outputs are also moved, so the timing relationship among the signals is maintained. For exact timing information, refer  
to Figures 7 and 8.  
DATA CLOCK OUTPUT  
DATACK  
Data Output Clock  
This is the main clock output signal used to strobe the output data and HSOUT into external logic. It is produced by  
the internal clock generator and is synchronous with the internal pixel sampling clock. When the sampling time is  
changed by adjusting the PHASE register, the output timing is shifted as well. The Data, DATACK, and HSOUT  
outputs are all moved, so the timing relationship among the signals is maintained.  
INPUTS  
RAIN  
Analog Input for RED Channel  
GAIN  
BAIN  
Analog Input for GREEN Channel  
Analog Input for BLUE Channel  
High-impedance inputs that accept the RED, GREEN, and BLUE channel graphics signals, respectively. (The  
three channels are identical, and can be used for any colors, but colors are assigned for convenient reference.) They  
accommodate input signals ranging from 0.5 V to 1.0 V full scale. Signals should be ac-coupled to these pins to  
support clamp operation.  
HSYNC  
Horizontal Sync Input  
This input receives a logic signal that establishes the horizontal timing reference and provides the frequency  
reference for pixel clock generation. The logic sense of this pin is controlled by serial register 0Eh Bit 6 (Hsync  
Polarity). Only the leading edge of Hsync is active, the trailing edge is ignored. When Hsync Polarity = 0, the falling  
edge of Hsync is used. When Hsync Polarity = 1, the rising edge is active. The input includes a Schmitt trigger  
for noise immunity, with a nominal input threshold of 1.5 V.  
VSYNC  
SOGIN  
Vertical Sync Input  
This is the input for vertical sync.  
Sync-on-Green Input  
This input is provided to assist with processing signals with embedded sync, typically on the GREEN channel. The pin  
is connected to a high-speed comparator with an internally generated threshold. The threshold level can be programmed  
in 10 mV steps to any voltage between 10 mV and 330 mV above the negative peak of the input signal. The default voltage  
threshold is 150 mV. When connected to an ac-coupled graphics signal with embedded sync, it will produce a  
noninverting digital output on SOGOUT. (This is usually a composite sync signal, containing both vertical and horizontal sync  
information that must be separated before passing the horizontal sync signal to Hsync.) When not used, this input should be left  
unconnected. For more details on this function and how it should be configured, refer to the Syncon-Green section.  
–6–  
REV. 0  
AD9883A  
PIN FUNCTION DESCRIPTIONS (continued)  
Pin Name  
Function  
CLAMP  
External Clamp Input  
This logic input may be used to define the time during which the input signal is clamped to ground. It should be  
exercised when the reference dc level is known to be present on the analog input channels, typically during the back  
porch of the graphics signal. The CLAMP pin is enabled by setting control bit Clamp Function to 1, (register 0FH,  
Bit 7, default is 0). When disabled, this pin is ignored and the clamp timing is determined internally by counting a  
delay and duration from the trailing edge of the HSYNC input. The logic sense of this pin is controlled by Clamp  
Polarity register 0FH, Bit 6. When not used, this pin must be grounded and Clamp Function programmed to 0.  
COAST  
Clock Generator Coast Input (Optional)  
This input may be used to cause the pixel clock generator to stop synchronizing with Hsync and continue producing a  
clock at its current frequency and phase. This is useful when processing signals from sources that fail to produce  
horizontal sync pulses during the vertical interval. The COAST signal is generally not required for PC-generated  
signals. The logic sense of this pin is controlled by Coast Polarity (register 0FH, Bit 3). When not used, this pin  
may be grounded and Coast Polarity programmed to 1, or tied HIGH (to VD through a 10 kΩ resistor) and Coast  
Polarity programmed to 0. Coast Polarity defaults to 1 at power-up.  
REF BYPASS Internal Reference BYPASS  
Bypass for the internal 1.25 V bandgap reference. It should be connected to ground through a 0.1 µF capacitor.  
The absolute accuracy of this reference is 4%, and the temperature coefficient is 50 ppm, which is adequate for  
most AD9883A applications. If higher accuracy is required, an external reference may be employed instead.  
MIDSCV  
FILT  
Midscale Voltage Reference BYPASS  
Bypass for the internal midscale voltage reference. It should be connected to ground through a 0.1 µF capacitor.  
The exact voltage varies with the gain setting of the Blue channel.  
External Filter Connection  
For proper operation, the pixel clock generator PLL requires an external filter. Connect the filter shown in Figure 6  
to this pin. For optimal performance, minimize noise and parasitics on this node.  
POWER SUPPLY  
VD  
Main Power Supply  
These pins supply power to the main elements of the circuit. They should be as quiet and filtered as possible.  
VDD  
Digital Output Power Supply  
A large number of output pins (up to 25) switching at high speed (up to 110 MHz) generates a lot of power supply  
transients (noise). These supply pins are identified separately from the VD pins so special care can be taken to minimize  
output noise transferred into the sensitive analog circuitry. If the AD9883A is interfacing with lower voltage logic,  
VDD may be connected to a lower supply voltage (as low as 2.5 V) for compatibility.  
PVD  
Clock Generator Power Supply  
The most sensitive portion of the AD9883A is the clock generation circuitry. These pins provide power to the clock PLL  
and help the user design for optimal performance. The designer should provide “quiet,” noise-free power to these pins.  
GND  
Ground  
The ground return for all circuitry on chip. It is recommended that the AD9883A be assembled on a single solid  
ground plane, with careful attention to ground current paths.  
DESIGN GUIDE  
With a typical power dissipation of only 500 mW and an operating  
General Description  
temperature range of 0°C to 70°C, the device requires no special  
The AD9883A is a fully integrated solution for capturing analog  
RGB signals and digitizing them for display on flat panel monitors  
or projectors. The circuit is ideal for providing a computer interface  
for HDTV monitors or as the front end to high-performance video  
scan converters.  
environmental considerations.  
Digital Inputs  
All digital inputs on the AD9883A operate to 3.3 V CMOS levels.  
However, all digital inputs are 5 V tolerant. (Applying 5 V to  
them will not cause any damage.)  
Implemented in a high-performance CMOS process, the interface  
can capture signals with pixel rates of up to 110 MHz.  
Input Signal Handling  
The AD9883A has three high-impedance analog input pins  
for the Red, Green, and Blue channels. They will accommodate  
signals ranging from 0.5 V to 1.0 V p-p.  
The AD9883A includes all necessary input buffering, signal dc  
restoration (clamping), offset and gain (brightness and contrast)  
adjustment, pixel clock generation, sampling phase control, and  
output data formatting. All controls are programmable via a 2-wire  
serial interface. Full integration of these sensitive analog functions  
makes system design straightforward and less sensitive to the  
physical and electrical environment.  
Signals are typically brought onto the interface board via a  
DVI-I connector, a 15-pin D connector, or via BNC connectors.  
The AD9883A should be located as close as practical to the input  
connector. Signals should be routed via matched-impedance  
traces (normally 75 Ω) to the IC input pins.  
REV. 0  
–7–  
AD9883A  
producing a black output (code 00h) when the known black  
input is present. The offset then remains in place when other  
signal levels are processed, and the entire signal is shifted to elimi-  
nate offset errors.  
At that point the signal should be resistively terminated (75 Ω  
to the signal ground return) and capacitively coupled to the  
AD9883A inputs through 47 nF capacitors. These capacitors  
form part of the dc restoration circuit.  
In most PC graphics systems, black is transmitted between  
active video lines. With CRT displays, when the electron beam  
has completed writing a horizontal line on the screen (at the  
right side), the beam is deflected quickly to the left side of the  
screen (called horizontal retrace) and a black signal is provided  
to prevent the beam from disturbing the image.  
In an ideal world of perfectly matched impedances, the best perfor-  
mance can be obtained with the widest possible signal bandwidth.  
The ultrawide bandwidth inputs of the AD9883A (300 MHz)  
can track the input signal continuously as it moves from one pixel  
level to the next, and digitize the pixel during a long, flat pixel  
time. In many systems, however, there are mismatches, reflections,  
and noise, which can result in excessive ringing and distortion of  
the input waveform. This makes it more difficult to establish a  
sampling phase that provides good image quality. It has been  
shown that a small inductor in series with the input is effec-  
tive in rolling off the input bandwidth slightly, and providing  
a high quality signal over a wider range of conditions. Using a  
Fair-Rite #2508051217Z0 High-Speed Signal Chip Bead  
inductor in the circuit of Figure 1 gives good results in most  
applications.  
In systems with embedded sync, a blacker-than-black signal  
(Hsync) is produced briefly to signal the CRT that it is time to  
begin a retrace. For obvious reasons, it is important to avoid  
clamping on the tip of Hsync. Fortunately, there is virtually  
always a period following Hsync called the back porch where a  
good black reference is provided. This is the time when clamp-  
ing should be done.  
The clamp timing can be established by simply exercising the  
CLAMP pin at the appropriate time (with External Clamp = 1).  
The polarity of this signal is set by the Clamp Polarity bit.  
47nF  
R
AIN  
RGB  
INPUT  
G
B
AIN  
A simpler method of clamp timing employs the AD9883A internal  
clamp timing generator. The Clamp Placement register is pro-  
grammed with the number of pixel times that should pass after  
the trailing edge of HSYNC before clamping starts. A second  
register (Clamp Duration) sets the duration of the clamp.  
These are both 8-bit values, providing considerable flexibility in  
clamp generation. The clamp timing is referenced to the trailing  
edge of Hsync because, though Hsync duration can vary widely,  
the back porch (black reference) always follows Hsync. A good  
starting point for establishing clamping is to set the clamp place-  
ment to 09h (providing 9 pixel periods for the graphics signal to  
stabilize after sync) and set the clamp duration to 14h (giving  
the clamp 20 pixel periods to reestablish the black reference).  
AIN  
75⍀  
Figure 1. Analog Input Interface Circuit  
Hsync, Vsync Inputs  
The interface also takes a horizontal sync signal, which is used  
to generate the pixel clock and clamp timing. This can be either  
a sync signal directly from the graphics source, or a preprocessed  
TTL or CMOS level signal.  
The Hsync input includes a Schmitt trigger buffer for immunity  
to noise and signals with long rise times. In typical PC-based  
graphic systems, the sync signals are simply TTL-level drivers  
feeding unshielded wires in the monitor cable. As such, no ter-  
mination is required.  
Clamping is accomplished by placing an appropriate charge on  
the external input coupling capacitor. The value of this capaci-  
tor affects the performance of the clamp. If it is too small, there  
will be a significant amplitude change during a horizontal line  
time (between clamping intervals). If the capacitor is too large,  
then it will take excessively long for the clamp to recover from a  
large change in incoming signal offset. The recommended value  
(47 nF) results in recovering from a step error of 100 mV to  
within 1/2 LSB in 10 lines with a clamp duration of 20 pixel  
periods on a 60 Hz SXGA signal.  
Serial Control Port  
The serial control port is designed for 3.3 V logic. If there are 5 V  
drivers on the bus, these pins should be protected with 150 Ω series  
resistors placed between the pull-up resistors and the input pins.  
Output Signal Handling  
The digital outputs are designed and specified to operate from a  
3.3 V power supply (VDD). They can also work with a VDD as  
low as 2.5 V for compatibility with other 2.5 V logic.  
YUV Clamping  
YUV graphic signals are slightly different from RGB signals in  
that the dc reference level (black level in RGB signals) can be at  
the midpoint of the graphics signal rather than the bottom. For  
these signals it can be necessary to clamp to the midscale range  
of the A/D converter range (80h) rather than bottom of the A/D  
converter range (00h).  
Clamping  
RGB Clamping  
To properly digitize the incoming signal, the dc offset of the input  
must be adjusted to fit the range of the on-board A/D converters.  
Most graphics systems produce RGB signals with black at  
ground and white at approximately 0.75 V. However, if sync  
signals are embedded in the graphics, the sync tip is often at  
ground and black is at 300 mV. Then white is at approximately  
1.0 V. Some common RGB line amplifier boxes use emitter-  
follower buffers to split signals and increase drive capability.  
This introduces a 700 mV dc offset to the signal, which must be  
removed for proper capture by the AD9883A.  
Clamping to midscale rather than ground can be accomplished  
by setting the clamp select bits in the serial bus register. Each of  
the three converters has its own selection bit so that they can be  
clamped to either midscale or ground independently. These bits  
are located in register 10h and are Bits 0–2. The midscale refer-  
ence voltage that each A/D converter clamps to is provided on  
the MIDSCV pin, (Pin 37). This pin should be bypassed to  
ground with a 0.1 µF capacitor, (even if midscale clamping is  
not required).  
The key to clamping is to identify a portion (time) of the signal  
when the graphic system is known to be producing black. An  
offset is then introduced which results in the A/D converters  
–8–  
REV. 0  
AD9883A  
Clock Generation  
OFFSET = 7Fh  
A Phase Locked Loop (PLL) is employed to generate the pixel  
clock. In this PLL, the Hsync input provides a reference fre-  
quency. A Voltage Controlled Oscillator (VCO) generates a  
much higher pixel clock frequency. This pixel clock is divided  
by the PLL divide value (registers 01H and 02H) and phase  
compared with the Hsync input. Any error is used to shift the  
VCO frequency and maintain lock between the two signals.  
OFFSET = 3Fh  
1.0  
OFFSET = 00h  
OFFSET = 7Fh  
0.5  
0.0  
The stability of this clock is a very important element in provid-  
ing the clearest and most stable image. During each pixel time,  
there is a period during which the signal is slewing from the old  
pixel amplitude and settling at its new value. Then there is a  
time when the input voltage is stable, before the signal must  
slew to a new value (Figure 4). The ratio of the slewing time to  
the stable time is a function of the bandwidth of the graphics  
DAC and the bandwidth of the transmission system (cable  
and termination). It is also a function of the overall pixel rate.  
Clearly, if the dynamic characteristics of the system remain  
fixed, then the slewing and settling time is likewise fixed. This  
time must be subtracted from the total pixel period, leaving the  
stable period. At higher pixel frequencies, the total cycle time is  
shorter, and the stable pixel time becomes shorter as well.  
OFFSET = 3Fh  
OFFSET = 00h  
00h  
FFh  
GAIN  
Figure 2. Gain and Offset Control  
Gain and Offset Control  
The AD9883A can accommodate input signals with inputs  
ranging from 0.5 V to 1.0 V full scale. The full-scale range is set  
in three 8-bit registers (Red Gain, Green Gain, and Blue Gain).  
Note that increasing the gain setting results in an image with  
less contrast.  
PIXEL CLOCK  
INVALID SAMPLE TIMES  
The offset control shifts the entire input range, resulting in a  
change in image brightness. Three 7-bit registers (Red Offset,  
Green Offset, Blue Offset) provide independent settings for  
each channel.  
The offset controls provide a 63 LSB adjustment range. This  
range is connected with the full-scale range, so if the input range  
is doubled (from 0.5 V to 1.0 V) then the offset step size is also  
doubled (from 2 mV per step to 4 mV per step).  
Figure 2 illustrates the interaction of gain and offset controls.  
The magnitude of an LSB in offset adjustment is proportional  
to the full-scale range, so changing the full-scale range also  
changes the offset. The change is minimal if the offset setting in  
near midscale. When changing the offset, the full-scale range is  
not affected, but the full-scale level is shifted by the same amount  
as the zero scale level.  
Figure 4. Pixel Sampling Times  
Any jitter in the clock reduces the precision with which the  
sampling time can be determined, and must also be subtracted  
from the stable pixel time.  
Considerable care has been taken in the design of the AD9883A’s  
clock generation circuit to minimize jitter. As indicated in Fig-  
ure 5, the clock jitter of the AD9883A is less than 5% of the  
total pixel time in all operating modes, making the reduction  
in the valid sampling time due to jitter negligible.  
Sync-on-Green  
The Sync-on-Green input operates in two steps. First, it sets a  
baseline clamp level off of the incoming video signal with a  
negative peak detector. Second, it sets the sync trigger level to a  
programmable level (typically 150 mV) above the negative peak.  
The Sync-on-Green input must be ac-coupled to the green  
analog input through its own capacitor as shown below in  
Figure 3. The value of the capacitor must be 1 nF 20%. If  
Sync-on-Green is not used, this connection is not required.  
(Note: The Sync-on-Green signal is always negative polarity.)  
14  
12  
10  
8
47nF  
R
B
AIN  
47nF  
47nF  
1nF  
6
AIN  
G
AIN  
4
SOG  
2
0
Figure 3. Typical Clamp Configuration  
0
31.5 36.0 36.0 50.0 56.25  
75.0 85.5  
110.0  
FREQUENCY – MHz  
Figure 5. Pixel Clock Jitter vs. Frequency  
REV. 0  
–9–  
AD9883A  
4. The 5-Bit Phase Adjust Register. The phase of the generated  
sampling clock may be shifted to locate an optimum sampling  
point within a clock cycle. The Phase Adjust register provides  
32 phase-shift steps of 11.25° each. The Hsync signal with  
an identical phase shift is available through the HSOUT pin.  
The PLL characteristics are determined by the loop filter design,  
by the PLL Charge Pump Current and by the VCO range setting.  
The loop filter design is illustrated in Figure 6. Recommended  
settings of VCO range and charge pump current for VESA  
standard display modes are listed in Table V.  
The COAST pin is used to allow the PLL to continue to run  
at the same frequency, in the absence of the incoming HSYNC  
signal or during disturbances in Hsync (such as equalization  
pulses). This may be used during the vertical sync period, or  
any other time that the HSYNC signal is unavailable. The  
polarity of the COAST signal may be set through the Coast  
Polarity Register. Also, the polarity of the HSYNC signal  
may be set through the HSYNC Polarity Register. For both  
HSYNC and COAST, a value of “1” is active high.  
PV  
D
0.039␮F C  
C
0.0039␮F  
Z
P
3.3k⍀ R  
Z
FILT  
Figure 6. PLL Loop Filter Detail  
Four programmable registers are provided to optimize the per-  
formance of the PLL. These registers are:  
Power Management  
The AD9883A uses the activity detect circuits, the active inter-  
face bits in the serial bus, the active interface override bits, and  
the power-down bit to determine the correct power state. There  
are three power states, full-power, seek mode, and power-down.  
Table IV summarizes how the AD9883A determines what power  
mode to be in and what circuitry is powered on/off in each of  
these modes. The power-down command has priority and then  
the automatic circuitry.  
1. The 12-Bit Divisor Register. The input Hsync frequencies  
range from 15 kHz to 110 kHz. The PLL multiplies the  
frequency of the Hsync signal, producing pixel clock  
frequencies in the range of 12 MHz to 110 MHz. The  
Divisor Register controls the exact multiplication factor.  
This register may be set to any value between 221 and 4095.  
(The divide ratio that is actually used is the programmed  
divide ratio plus one.)  
2. The 2-Bit VCO Range Register. To improve the noise  
performance of the AD9883A, the VCO operating frequency  
range is divided into three overlapping regions. The VCO  
Range Register sets this operating range. The frequency  
ranges for the lowest and highest regions are shown in Table II.  
Table IV. Power-Down Mode Descriptions  
Inputs  
Power-  
Sync  
Powered On or  
Comments  
Mode  
Down1  
Detect2  
Full-Power  
Seek Mode  
1
1
1
0
Everything  
Table II. VCO Frequency Ranges  
Serial Bus, Sync  
Activity Detect,  
Pixel Clock Range  
(MHz)  
KVCO Gain  
(MHz/V)  
PV1  
PV0  
SOG,  
0
0
1
1
0
1
0
1
12–36  
36–72  
72–110  
110-140  
150  
150  
150  
150  
Bandgap Reference  
Power-Down  
0
X
Serial Bus, Sync  
Activity Detect, SOG,  
Bandgap Reference  
NOTES  
1Power-Down is controlled via Bit 1 in serial bus register 0Fh.  
3. The 3-Bit Charge Pump Current register. This register  
allows the current that drives the low pass loop filter to be  
varied. The possible current values are listed in Table III.  
2Sync Detect is determined by OR-ing Bits 7, 4, and 1 in serial bus register 14h.  
Table III. Charge Pump Current/Control Bits  
Ip2  
Ip1  
Ip0  
Current (␮A)  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
50  
100  
150  
250  
350  
500  
750  
1500  
–10–  
REV. 0  
AD9883A  
Table V. Recommended VCO Range and Charge Pump Current Settings for Standard Display Formats  
Refresh  
Rate  
Horizontal  
Frequency  
Standard  
Resolution  
Pixel Rate  
VCORNGE  
Current  
VGA  
640 × 480  
60 Hz  
72 Hz  
75 Hz  
85 Hz  
31.5 kHz  
37.7 kHz  
37.5 kHz  
43.3 kHz  
25.175 MHz  
31.500 MHz  
31.500 MHz  
36.000 MHz  
00  
00  
00  
00  
101  
110  
110  
110  
SVGA  
XGA  
800 × 600  
56 Hz  
60 Hz  
72 Hz  
75 Hz  
85 Hz  
35.1 kHz  
37.9 kHz  
48.1 kHz  
46.9 kHz  
53.7 kHz  
36.000 MHz  
40.000 MHz  
50.000 MHz  
49.500 MHz  
56.250 MHz  
00  
01  
01  
01  
01  
110  
100  
100  
100  
101  
1024 × 768  
1280 × 1024  
60 Hz  
70 Hz  
75 Hz  
80 Hz  
85 Hz  
48.4 kHz  
56.5 kHz  
60.0 kHz  
64.0 kHz  
68.3 kHz  
65.000 MHz  
75.000 MHz  
78.750 MHz  
85.500 MHz  
94.500 MHz  
01  
10  
10  
10  
10  
110  
100  
100  
100  
100  
SXGA  
60 Hz  
75 Hz  
64.0 kHz  
80.0 kHz  
108.000 MHz  
135.000 MHz  
10  
11  
110  
101  
Timing  
Three things happen to Horizontal Sync in the AD9883A. First,  
the polarity of Hsync input is determined and will thus have a  
known output polarity. The known output polarity can be pro-  
grammed either active high or active low (register 0EH, Bit 5).  
Second, HSOUT is aligned with DATACK and data outputs.  
Third, the duration of HSOUT (in pixel clocks) is set via regis-  
ter 07H. HSOUT is the sync signal that should be used to drive  
the rest of the display system.  
The following timing diagrams show the operation of the  
AD9883A.  
The Output Data Clock signal is created so that its rising edge  
always occurs between data transitions, and can be used to latch  
the output data externally.  
There is a pipeline in the AD9883A, which must be flushed  
before valid data becomes available. This means four data sets  
are presented before valid data is available.  
Coast Timing  
In most computer systems, the Hsync signal is provided con-  
tinuously on a dedicated wire. In these systems, the COAST  
input and function are unnecessary, and should not be used and  
the pin should be permanently connected to the inactive state.  
tPER  
tCYCLE  
In some systems, however, Hsync is disturbed during the  
Vertical Sync period (Vsync). In some cases, Hsync pulses  
disappear. In other systems, such as those that employ Compos-  
ite Sync (Csync) signals or embedded Sync-on-Green (SOG),  
Hsync includes equalization pulses or other distortions during  
Vsync. To avoid upsetting the clock generator during Vsync,  
it is important to ignore these distortions. If the pixel clock  
PLL sees extraneous pulses, it will attempt to lock to this new  
frequency, and will have changed frequency by the end of the  
Vsync period. It will then take a few lines of correct Hsync tim-  
ing to recover at the beginning of a new frame, resulting in a  
“tearing” of the image at the top of the display.  
DATACK  
tSKEW  
DATA  
HSOUT  
Figure 7. Output Timing  
Hsync Timing  
Horizontal Sync (Hsync) is processed in the AD9883A to elimi-  
nate ambiguity in the timing of the leading edge with respect to  
the phase-delayed pixel clock and data.  
The COAST input is provided to eliminate this problem. It is  
an asynchronous input that disables the PLL input and allows  
the clock to free-run at its then-current frequency. The PLL can  
free-run for several lines without significant frequency drift.  
The Hsync input is used as a reference to generate the pixel  
sampling clock. The sampling phase can be adjusted, with respect  
to Hsync, through a full 360° in 32 steps via the Phase Adjust  
register (to optimize the pixel sampling time). Display systems  
use Hsync to align memory and display write cycles, so it is  
important to have a stable timing relationship between Hsync  
output (HSOUT) and data clock (DATACK).  
REV. 0  
–11–  
AD9883A  
RGB  
P0  
P1  
P2  
P3  
P4  
P5  
P6  
P7  
IN  
HSYNC  
PxCK  
HS  
5-PIPE DELAY  
ADCCK  
DATACK  
D
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
OUTA  
HSOUT  
VARIABLE DURATION  
Figure 8. 4:4:4 Mode (For RGB and YUV)  
RGB  
IN  
P0  
P1  
P2  
P3  
P4  
P5  
P6  
P7  
HSYNC  
PxCK  
HS  
5-PIPE DELAY  
ADCCK  
DATACK  
G
Y0  
Y1  
Y2  
U2  
Y3  
V3  
Y4  
U4  
Y5  
V5  
Y6  
U6  
Y7  
V7  
OUTA  
R
U0  
V1  
OUTA  
HSOUT  
Figure 9. 4:2:2 Mode (For YUV Only)  
–12–  
REV. 0  
AD9883A  
2-Wire Serial Register Map  
The AD9883A is initialized and controlled by a set of registers, which determine the operating modes. An external controller is  
employed to write and read the Control Registers through the 2-line serial interface port.  
Table VI. Control Register Map  
Write and  
Read or  
Read Only  
Hex  
Address  
Default  
Value  
Register  
Name  
Bits  
Function  
00H  
RO  
7:0  
Chip Revision An 8-bit register that represents the silicon revision level.  
Revision 0 = 0000 0000  
01H  
R/W  
7:0  
01101001  
PLL Div MSB This register is for Bits [11:4] of the PLL divider. Larger values mean  
the PLL operates at a faster rate. This register should be loaded first  
whenever a change is needed. (This will give the PLL more time to  
lock.) See Note 1 .  
02H  
03H  
R/W  
7:4  
7:3  
1101****  
PLL Div LSB Bits [7:4] LSBs of the PLL divider word. See Note 1.  
R/W  
01******  
Bits [7:6] VCO Range. Selects VCO frequency range. (See PLL  
description.)  
**001***  
01000***  
10000000  
10000000  
00100000  
10000000  
Bits [5:3] Charge Pump Current. Varies the current that drives the  
low-pass filter. (See PLL description.)  
04H  
05H  
06H  
07H  
08H  
R/W  
R/W  
R/W  
R/W  
R/W  
7:3  
7:0  
7:0  
7:0  
7:0  
Phase Adjust  
ADC Clock Phase Adjustment. Larger values mean more delay.  
(1 LSB = T/32.)  
Clamp  
Placement  
Places the Clamp signal an integer number of clock periods after the trail-  
ing edge of the HSYNC signal.  
Clamp  
Duration  
Number of clock periods that the Clamp signal is actively clamping.  
Hsync Output Sets the number of pixel clocks that HSOUT will remain active.  
Pulsewidth  
Red Gain  
Controls ADC input range (Contrast) of each respective channel.  
Bigger values give less contrast.  
09H  
0AH  
0BH  
R/W  
R/W  
R/W  
7:0  
7:0  
7:1  
10000000  
10000000  
1000000*  
Green Gain  
Blue Gain  
Red Offset  
Controls dc offset (Brightness) of each respective channel. Bigger  
values decrease brightness.  
0CH  
0DH  
0EH  
R/W  
R/W  
R/W  
7:1  
7:1  
7:0  
1000000*  
1000000*  
0*******  
Green Offset  
Blue Offset  
Sync Control  
Bit 7 – Hsync Polarity Override. (Logic 0 = Polarity determined by  
chip, Logic 1 = Polarity set by Bit 6 in register 0Eh.)  
*1******  
**0*****  
***0****  
Bit 6 – Hsync Input Polarity. Indicates polarity of incoming HSYNC  
signal to the PLL. (Logic 0 = Active Low, Logic 1 = Active High.)  
Bit 5 – Hsync Output Polarity. (Logic 0 = Logic High Sync, Logic 1 =  
Logic Low Sync.)  
Bit 4 – Active Hsync Override. If set to Logic 1, the user can select  
the Hsync to be used via Bit 3. If set to Logic 0, the active interface  
is selected via Bit 6 in register 14H.  
****0***  
Bit 3 – Active Hsync Select. Logic 0 selects Hsync as the active  
sync. Logic 1 selects Sync-on-Green as the active sync. Note: The  
indicated Hsync will be used only if Bit 4 is set to Logic 1 or if both  
syncs are active, (Bits 1, 7 = Logic 1 in register 14H).  
*****0**  
Bit 2 – Vsync Output Invert. (Logic 0 = No Invert, Logic 1 = Invert.)  
******0*  
Bit 1 – Active Vsync Override. If set to Logic 1, the user can select  
the Vsync to be used via Bit 0. If set to Logic 0, the active interface  
is selected via Bit 3 in register 14H.  
*******0  
Bit 0 – Active Vsync Select. Logic 0 selects Raw Vsync as the output  
Vsync. Logic 1 selects Sync Separated Vsync as the output Vsync.  
Note: The indicated Vsync will be used only if Bit 1 is set to Logic 1.  
REV. 0  
–13–  
AD9883A  
Table VI. Control Register Map (continued)  
Register  
Write and  
Read or  
Read Only  
Hex  
Address  
Default  
Value  
Bits  
Name  
Function  
0FH  
R/W  
7:1  
0*******  
Bit 7 – Clamp Function. Chooses between HSYNC for Clamp  
signal or another external signal to be used for clamping.  
(Logic 0 = HSYNC, Logic 1 = Clamp.)  
*1******  
**0*****  
***0****  
****1***  
*****1**  
******1*  
Bit 6 – Clamp Polarity. Valid only with external Clamp signal.  
(Logic 0 = active high, Logic 1 select active low.)  
Bit 5 – Coast Select. Logic 0 selects the coast input pins to be used  
for the PLL coast. Logic 1 selects Vsync to be used for the PLL coast.  
Bit 4 – Coast Polarity Override. (Logic 0 = Polarity determined by  
chip, Logic 1 = Polarity set by Bit 3 in register 0Fh.)  
Bit 3 – Coast Polarity. Changes polarity of external COAST signal.  
(Logic = 0 = active high, Logic 1 = active low.)  
Bit 2 – Seek Mode Override. (Logic 1 = allow low-power mode,  
Logic 0 = disallow low-power mode.)  
Bit 1 – PWRDN. Full Chip Power Down, active low. (Logic 0 =  
Full Chip Power-Down, Logic 1 = normal.)  
10H  
11H  
R/W  
7:3  
7:0  
10111***  
Sync-on-Green  
Threshold  
Sync-on-Green Threshold – Sets the voltage level of the Sync-on-  
Green slicer’s comparator.  
Bit 2 – Red Clamp Select – Logic 0 selects clamp to ground. Logic  
1 selects clamp to midscale (voltage at Pin 37).  
Bit 1 – Green Clamp Select – Logic 0 selects clamp to ground.  
Logic 1 selects clamp to midscale (voltage at Pin 37).  
Bit 0 – Blue Clamp Select – Logic 0 selects clamp to ground.  
Logic 1 selects clamp to midscale (voltage at Pin 37).  
Sync Separator Threshold – Sets how many internal 5 MHz clock  
periods the sync separator will count to before toggling high or  
low. This should be set to some number greater than the maxi-  
mum Hsync or equalization pulsewidth.  
*****0**  
******0*  
*******0  
00100000  
R/W  
Sync Separator  
Threshold  
12H  
13H  
14H  
R/W  
R/W  
RO  
7:0  
7:0  
7:0  
00000000  
00000000  
Pre-Coast  
Pre-Coast – Sets the number of Hsync periods that coast becomes  
active prior to Vsync.  
Post-Coast  
Sync Detect  
Post-Coast – Sets the number of Hsync periods that coast stays  
active following Vsync.  
Bit 7 – Hsync detect. It is set to Logic 1 if Hsync is present on the  
analog interface; otherwise it is set to Logic 0.  
Bit 6 – AHS: Active Hsync. This bit indicates which analog Hsync  
is being used. (Logic 0 = Hsync input pin, Logic 1 = Hsync from  
Sync-on-Green.)  
Bit 5 – Input Hsync Polarity Detect. (Logic 0 = Active Low,  
Logic 1 = Active High.)  
Bit 4 – Vsync detect. It is set to Logic 1 if V-sync is present on the  
analog interface; otherwise it is set to Logic 0.  
Bit 3 – AVS: Active Vsync. This bit indicates which analog Vsync  
is being used. (Logic 0 = Vsync input pin, Logic 1 = Vsync from  
sync separator.)  
Bit 2 – Output Vsync Polarity Detect. (Logic 0 = Active Low,  
Logic 1 = Active High.)  
Bit 1 – Sync-on-Green detect. It is set to Logic 1 if sync is present  
on the green video input; otherwise it is set to 0.  
Bit 0 – Input Coast Polarity Detect. (Logic 0 = active low, Logic 1 =  
active high.)  
–14–  
REV. 0  
AD9883A  
Table VI. Control Register Map (continued)  
Register  
Write and  
Read or  
Read Only  
Hex  
Address  
Default  
Value  
Bits  
Name  
Function  
15H  
R/W  
7:0  
Test Register  
Bits [7:2] Reserved for future use.  
Bit 1 – 4:2:2 Output Formatting Mode.  
Bit 0 – Must be set to 0 for proper operation.  
16H  
17H  
R/W  
RO  
7:0  
7:0  
7:0  
Test Register  
Test Register  
Test Register  
Reserved for future use.  
Reserved for future use.  
Reserved for future use.  
18H  
RO  
NOTE  
1The AD9883A only updates the PLL divide ratio when the LSBs are written to (register 02h).  
The AD9883A updates the full divide ratio only when this  
register is written to.  
TWO-WIRE SERIAL CONTROL REGISTER DETAIL  
CHIP IDENTIFICATION  
00  
7–0 Chip Revision  
CLOCK GENERATOR CONTROL  
An 8-bit register which represents the silicon revision.  
Revision 0 = 0000 0000, Revision 1 = 0000 0001,  
Revision 2 = 0000 0010.  
03  
7–6 VCO Range Select  
Two bits that establish the operating range of the clock  
generator.  
PLL DIVIDER CONTROL  
VCORNGE must be set to correspond with the desired  
operating frequency (incoming pixel rate).  
01  
7–0 PLL Divide Ratio MSBs  
The eight most significant bits of the 12-bit PLL divide ratio  
The PLL gives the best jitter performance at high fre-  
quencies. For this reason, in order to output low pixel  
rates and still get good jitter performance, the PLL actu-  
ally operates at a higher frequency but then divides down  
the clock rate afterwards. Table VII shows the pixel rates  
for each VCO range setting. The PLL output divisor is  
automatically selected with the VCO range setting.  
PLLDIV. (The operational divide ratio is PLLDIV + 1.)  
The PLL derives a master clock from an incoming Hsync  
signal. The master clock frequency is then divided by an  
integer value, such that the output is phase-locked to  
Hsync. This PLLDIV value determines the number of  
pixel times (pixels plus horizontal blanking overhead) per  
line. This is typically 20% to 30% more than the number  
of active pixels in the display.  
Table VII. VCO Ranges  
The 12-bit value of the PLL divider supports divide ratios  
from 2 to 4095. The higher the value loaded in this regis-  
ter, the higher the resulting clock frequency with respect  
to a fixed Hsync frequency.  
VCORNGE  
Pixel Rate Range  
00  
01  
10  
10  
12–36  
36–72  
72–110  
110–140  
VESA has established some standard timing specifications,  
which will assist in determining the value for PLLDIV as  
a function of horizontal and vertical display resolution and  
frame rate (Table V).  
The power-up default value is 01.  
However, many computer systems do not conform pre-  
cisely to the recommendations, and these numbers should  
be used only as a guide. The display system manufacturer  
should provide automatic or manual means for optimizing  
PLLDIV. An incorrectly set PLLDIV will usually produce  
one or more vertical noise bars on the display. The greater  
the error, the greater the number of bars produced.  
03  
5–3 CURRENT Charge Pump Current  
Three bits that establish the current driving the loop filter  
in the clock generator.  
Table VIII. Charge Pump Currents  
CURRENT  
Current (␮A)  
The power-up default value of PLLDIV is 1693  
(PLLDIVM = 69h, PLLDIVL = Dxh).  
000  
001  
010  
011  
100  
101  
110  
111  
50  
100  
150  
250  
350  
500  
750  
1500  
The AD9883A updates the full divide ratio only when the  
LSBs are changed. Writing to the MSB by itself will not  
trigger an update.  
02  
7–4 PLL Divide Ratio LSBs  
The four least significant bits of the 12-bit PLL divide ratio  
PLLDIV. The operational divide ratio is PLLDIV + 1.  
CURRENT must be set to correspond with the desired  
operating frequency (incoming pixel rate).  
The power-up default value of PLLDIV is 1693  
(PLLDIVM = 69h, PLLDIVL = Dxh).  
The power-up default value is CURRENT = 001.  
REV. 0  
–15–  
AD9883A  
04  
7–3 Clock Phase Adjust  
INPUT OFFSET  
0B 7–1 Red Channel Offset Adjust  
A 5-bit value that adjusts the sampling phase in 32 steps  
across one pixel time. Each step represents an 11.25° shift  
in sampling phase.  
A 7-bit offset binary word that sets the dc offset of the RED  
channel. One LSB of offset adjustment equals approximately  
one LSB change in the ADC offset. Therefore, the absolute  
magnitude of the offset adjustment scales as the gain of the  
channel is changed. A nominal setting of 63 results in the  
channel nominally clamping the back porch (during the  
clamping interval) to Code 00. An offset setting of 127 results  
in the channel clamping to Code 64 of the ADC. An offset  
setting of 0 clamps to Code –63 (off the bottom of the  
range). Increasing the value of Red Offset decreases the  
brightness of the channel.  
The power-up default value is 16.  
CLAMP TIMING  
05 7–0 Clamp Placement  
An 8-bit register that sets the position of the internally  
generated clamp.  
When Clamp Function (Register 0Fh, Bit 7) = 0, a clamp  
signal is generated internally, at a position established by  
the clamp placement and for a duration set by the clamp  
duration. Clamping is started (Clamp Placement) pixel  
periods after the trailing edge of Hsync. The clamp place-  
ment may be programmed to any value between 1 and  
255. Values of 0, 1, 2, 4, 8, 16, 32, 64, and 128 are not  
supported.  
0C  
7–1 Green Channel Offset Adjust  
A 7-bit offset binary word that sets the dc offset of the  
GREEN channel. See REDOFST (0B).  
0D 7–1 Blue Channel Offset Adjust  
A 7-bit offset binary word that sets the dc offset of the  
GREEN channel. See REDOFST (0B).  
The clamp should be placed during a time that the input  
signal presents a stable black-level reference, usually the  
back porch period between Hsync and the image.  
MODE CONTROL 1  
When Clamp Function = 1, this register is ignored.  
0E  
7
Hsync Input Polarity Override  
This register is used to override the internal circuitry  
that determines the polarity of the Hsync signal going  
into the PLL.  
06  
7–0 Clamp Duration  
An 8-bit register that sets the duration of the internally  
generated clamp.  
For the best results, the clamp duration should be set to  
include the majority of the black reference signal time that  
follows the Hsync signal trailing edge. Insufficient clamp-  
ing time can produce brightness changes at the top of the  
screen, and a slow recovery from large changes in the Average  
Picture Level (APL), or brightness.  
Table IX. Hsync Input Polarity Override Settings  
Override Bit  
Function  
0
1
Hsync Polarity Determined by Chip  
Hsync Polarity Determined by User  
When Clamp Function = 1, this register is ignored.  
The default for Hsync polarity override is 0 (polarity  
determined by chip).  
Hsync PULSEWIDTH  
07 7–0 Hsync Output Pulsewidth  
0E  
6
HSPOL Hsync Input Polarity  
An 8-bit register that sets the duration of the Hsync  
output pulse.  
A bit that must be set to indicate the polarity of the  
Hsync signal that is applied to the PLL Hsync input.  
The leading edge of the Hsync output is triggered by the  
internally generated, phase-adjusted PLL feedback clock.  
The AD9883A then counts a number of pixel clocks equal  
to the value in this register. This triggers the trailing edge  
of the Hsync output, which is also phase adjusted.  
Table X. Hsync Input Polarity Settings  
HSPOL  
Function  
0
1
Active LOW  
Active HIGH  
INPUT GAIN  
08  
7–0 Red Channel Gain Adjust  
Active LOW means the leading edge of the Hsync pulse  
is negative going. All timing is based on the leading  
edge of Hsync, which is the falling edge. The rising  
edge has no effect.  
An 8-bit word that sets the gain of the RED channel.  
The AD9883A can accommodate input signals with a  
full scale range of between 0.5 V and 1.5 V p-p. Setting  
REDGAIN to 255 corresponds to an input range of  
1.0 V. A REDGAIN of 0 establishes an input range of  
0.5 V. Note that INCREASING REDGAIN results in the  
picture having LESS CONTRAST (the input signal  
uses fewer of the available converter codes). See Figure 2.  
Active high is inverted from the traditional Hsync, with  
a positive-going pulse. This means that timing will be  
based on the leading edge of Hsync, which is now the  
rising edge.  
The device will operate if this bit is set incorrectly, but the  
internally generated clamp position, as established by  
Clamp Placement (Register 05h), will not be placed as  
expected, which may generate clamping errors.  
09  
7–0 Green Channel Gain Adjust  
An 8-bit word that sets the gain of the GREEN channel.  
See REDGAIN (08).  
0A  
7–0 Blue Channel Gain Adjust  
An 8-bit word that sets the gain of the BLUE channel.  
See REDGAIN (08).  
The power-up default value is HSPOL = 1.  
–16–  
REV. 0  
AD9883A  
0E  
0E  
0E  
5
Hsync Output Polarity  
0E  
0
Active Vsync Select  
One bit that determines the polarity of the Hsync output  
and the SOG output. Table XI shows the effect of this  
option. SYNC indicates the logic state of the sync pulse.  
This bit is used to select the active Vsync when the over-  
ride bit is set (Bit 1).  
Table XVI. Active Vsync Select Settings  
Table XI. Hsync Output Polarity Settings  
Select  
Result  
Setting  
SYNC  
0
1
Vsync Input  
Sync Separator Output  
0
1
Logic 1 (Positive Polarity)  
Logic 0 (Negative Polarity)  
The default for this register is 0.  
7 Clamp Input Signal Source  
A bit that determines the source of clamp timing.  
The default setting for this register is 0.  
Active Hsync Override  
0F  
4
This bit is used to override the automatic Hsync selection,  
To override, set this bit to Logic 1. When overriding, the  
active Hsync is set via Bit 3 in this register.  
Table XVII. Clamp Input Signal Source Settings  
Clamp Function  
Function  
Table XII. Active Hsync Override Settings  
Override Result  
0
1
Internally Generated Clamp  
Externally Provided Clamp Signal  
A 0 enables the clamp timing circuitry controlled by clamp  
placement and clamp duration. The clamp position and  
duration is counted from the leading edge of Hsync.  
0
1
Auto Determines the Active Interface  
Override, Bit 3 Determines the Active Interface  
The default for this register is 0.  
Active Hsync Select  
A 1 enables the external CLAMP input pin. The three  
channels are clamped when the CLAMP signal is active.  
The polarity of CLAMP is determined by the Clamp  
Polarity bit (Register 0Fh, Bit 6).  
3
This bit is used under two conditions. It is used to select  
the active Hsync when the override bit is set, (Bit 4). Alter-  
nately, it is used to determine the active Hsync when not  
overriding but both Hsyncs are detected.  
The power-up default value is Clamp Function = 0.  
0F  
6
Clamp Input Signal Polarity  
A bit that determines the polarity of the externally pro-  
vided CLAMP signal.  
Table XIII. Active HSYNC Select Settings  
Select  
Result  
Table XVIII. Clamp Input Signal Polarity Settings  
0
1
HSYNC Input  
Sync-on-Green Input  
Clamp Function  
Function  
1
0
Active LOW  
Active HIGH  
The default for this register is 0.  
Vsync Output Invert  
0E  
2
One bit that can invert the polarity of the Vsync output.  
Table XIV shows the effect of this option.  
A Logic 1 means that the circuit will clamp when CLAMP is  
HIGH, and it will pass the signal to the ADC when CLAMP  
is LOW.  
Table XIV. Vsync Output Invert Settings  
A Logic 0 means that the circuit will clamp when CLAMP  
is LOW, and it will pass the signal to the ADC when  
CLAMP is HIGH.  
Setting  
Vsync Output  
1
0
No Invert  
Invert  
The power-up default value is Clamp Polarity = 1.  
0F  
5
Coast Select  
The default setting for this register is 1.  
Active Vsync Override  
This bit is used to override the automatic Vsync selection.  
To override, set this bit to Logic 1. When overriding, the  
active interface is set via Bit 0 in this register.  
This bit is used to select the active coast source. The  
choices are the coast input pin or Vsync. If Vsync is selected  
the additional decision of using the Vsync input pin or the  
output from the sync separator needs to be made (Reg-  
ister 0E, Bits 1, 0).  
0E  
1
Table XIX. Power-Down Settings  
Table XV. Active Vsync Override Settings  
Select  
Result  
Override  
Result  
0
1
Coast Input Pin  
Vsync (See above Text)  
0
1
Auto Determine the Active Vsync  
Override, Bit 0 Determines the Active Vsync  
The default for this register is 0.  
REV. 0  
–17–  
AD9883A  
0F  
4
Coast Input Polarity Override  
steps of 10 mV, with the minimum setting equaling 10 mV  
(11111) and the maximum setting equaling 330 mV (00000).  
This register is used to override the internal circuitry that  
determines the polarity of the coast signal going into  
the PLL.  
The default setting is 23 and corresponds to a threshold  
value of 0.15 V.  
10  
2
Red Clamp Select  
Table XX. Coast Input Polarity Override Settings  
A bit that determines whether the RED channel is clamped  
to ground or to midscale. For RGB video, all three  
channels are referenced to ground. For YcbCr (or YUV),  
the Y channel is referenced to ground, but the CbCr  
channels are referenced to midscale. Clamping to midscale  
actually clamps to Pin 37.  
Override Bit  
Result  
0
1
Coast Polarity Determined by Chip  
Coast Polarity Determined by User  
The default for coast polarity override is 0.  
3 Coast Input Polarity  
A bit to indicate the polarity of the COAST signal that is  
applied to the PLL COAST input.  
0F  
Table XXIV. Red Clamp Select Settings  
Clamp  
Function  
0
1
Clamp to Ground  
Clamp to Midscale (Pin 37)  
Table XXI. Coast Input Polarity Settings  
Coast Polarity  
Function  
The default setting for this register is 0.  
1 Green Clamp Select  
A bit that determines whether the GREEN channel is  
clamped to ground or to midscale.  
0
1
Active LOW  
Active HIGH  
10  
10  
11  
Active LOW means that the clock generator will ignore  
Hsync inputs when COAST is LOW, and continue  
operating at the same nominal frequency until COAST  
goes HIGH.  
Table XXV. Green Clamp Select Settings  
Clamp  
Function  
Active HIGH means that the clock generator will ignore  
Hsync inputs when COAST is HIGH, and continue  
operating at the same nominal frequency until COAST  
goes LOW.  
0
1
Clamp to Ground  
Clamp to Midscale (Pin 37)  
The default setting for this register is 0.  
Blue Clamp Select  
This function needs to be used along with the COAST  
polarity override bit (Bit 4).  
0
A bit that determines whether the BLUE channel is  
clamped to ground or to midscale.  
The power-up default value is 1.  
0F  
0F  
10  
2
Seek Mode Override  
Table XXVI. Blue Clamp Select Settings  
This bit is used to either allow or disallow the low-power  
mode. The low-power mode (seek mode) occurs when  
there are no signals on any of the Sync inputs.  
Clamp  
Function  
0
1
Clamp to Ground  
Clamp to Midscale (Pin 37)  
Table XXII. Seek Mode Override Settings  
Select  
Result  
The default setting for this register is 0.  
7:0 Sync Separator Threshold  
1
0
Allow Seek Mode  
Disallow Seek Mode  
This register is used to set the responsiveness of the sync  
separator. It sets how many internal 5 MHz clock periods  
the sync separator must count to before toggling high or  
low. It works like a low-pass filter to ignore Hsync pulses  
in order to extract the Vsync signal. This register should  
be set to some number greater than the maximum Hsync  
pulsewidth. Note: the sync separator threshold uses an  
internal dedicated clock with a frequency of approxi-  
mately 5 MHz.  
The default for this register is 1.  
PWRDN  
1
This bit is used to put the chip in full power-down. See  
the section on power management for details of which  
blocks are actually powered down.  
Table XXIII. Power-Down Settings  
The default for this register is 32.  
Select  
Result  
12  
7-0 Pre-Coast  
0
1
Power-Down  
Normal Operation  
This register allows the coast signal to be applied prior to  
the Vsync signal. This is necessary in cases where pre-  
equalization pulses are present. The step size for this  
control is one Hsync period.  
The default for this register is 1.  
7-3 Sync-on-Green Slicer Threshold  
This register allows the comparator threshold of the Sync-  
on-Green slicer to be adjusted. This register adjusts it in  
The default is 0.  
–18–  
REV. 0  
AD9883A  
13  
14  
7-0 Post-Coast  
Table XXX. Vsync Detection Results  
This register allows the coast signal to be applied follow-  
ing to the Vsync signal. This is necessary in cases where  
post-equalization pulses are present. The step size for this  
control is one Hsync period.  
Detect  
Function  
0
1
No Activity Detected  
Activity Detected  
The default is 0.  
The Sync Processing Block Diagram (Figure 12) shows  
where this function is implemented.  
7
Hsync Detect  
This bit is used to indicate when activity is detected on  
the Hsync input pin (Pin 30). If Hsync is held high or  
low, activity will not be detected.  
14  
3
AVS – Active Vsync  
This bit indicates which Vsync source is being used; the  
Vsync input or output from the sync separator. Bit 4 in this  
register determines which is active. If both Vsync and  
SOG are detected, the user can determine which has  
priority via Bit 0 in register 0EH. The user can override this  
function via Bit 1 in register 0EH. If the override bit is set  
to Logic 1, this bit will be forced to whatever the state of Bit 0  
in register 0EH is set.  
Table XXVII. Hsync Detection Results  
Detect  
Function  
0
1
No Activity Detected  
Activity Detected  
The sync processing block diagram shows where this  
function is implemented.  
Table XXXI. Active Vsync Results  
Bit 5  
14  
6
AHS – Active Hsync  
(Vsync Detect)  
Override  
AVS  
This bit indicates which Hsync input source is being used  
by the PLL (Hsync input or Sync-on-Green). Bits 7 and 1  
in this register are what determine which source is used. If  
both Hsync and SOG are detected, the user can determine  
which has priority via Bit 3 in register 0EH. The user can  
override this function via Bit 4 in register 0EH. If the  
override bit is set to Logic 1, then this bit will be forced to  
whatever the state of Bit 3 in register 0EH is set to.  
0
1
X
0
0
1
0
1
Bit 0 in 0EH  
AVS = 0 means Vsync input.  
AVS = 1 means Sync separator.  
The override bit is in register 0EH, Bit 1.  
Table XXVIII. Active Hsync Results  
14  
2 Detected Vsync Output Polarity Status  
This bit reports the status of the Vsync output polarity  
detection circuit. It can be used to determine the polarity  
of the Vsync output. The detection circuit’s location is  
shown in the Sync Processing Block Diagram.  
Bit 7  
(Hsync  
Detect) Detect)  
Bit 1  
(SOG  
Bit 4, Reg  
0EH  
(Override)  
AHS  
0
0
1
1
X
0
1
0
1
X
0
0
0
0
1
Bit 3 in 0EH  
1
0
Bit 3 in 0EH  
Bit 3 in 0EH  
Table XXXII. Detected Vsync Output Polarity Status  
Vsync Polarity Status  
Result  
0
1
Vsync Polarity Is Active Low  
Vsync Polarity Is Active High  
AHS = 0 means use the Hsync pin input for Hsync.  
AHS = 1 means use the SOG pin input for Hsync.  
14  
1
Sync-on-Green Detect  
This bit is used to indicate when sync activity is detected  
on the Sync-on-Green input pin (Pin 49).  
The override bit is in register 0EH, Bit 4.  
14  
5
Detected Hsync Input Polarity Status  
This bit reports the status of the Hsync input polarity  
detection circuit. It can be used to determine the polarity  
of the Hsync input. The detection circuit’s location is  
shown in the Sync Processing Block Diagram (Figure 12).  
Table XXXIII. Sync-on-Green Detection Results  
Detect  
Function  
0
1
No Activity Detected  
Activity Detected  
Table XXIX. Detected Hsync Input Polarity Status  
Hsync Polarity Status Result  
The sync processing block diagram shows where this  
function is implemented.  
0
1
Hsync Polarity Is Negative  
Hsync Polarity Is Positive  
14  
0
Detected COAST Polarity Status  
This bit reports the status of the coast input polarity  
detection circuit. It can be used to determine the polarity  
of the coast input. The detection circuit’s location is shown  
in the Sync Processing Block Diagram (Figure 12).  
14  
4
Vsync Detect  
This bit is used to indicate when activity is detected on  
the Vsync input pin (Pin 31). If Vsync is held high or low,  
activity will not be detected.  
REV. 0  
–19–  
AD9883A  
Table XXXIV. Detected Coast Input Polarity Status  
There are five components to serial bus operation:  
• Start Signal  
Hsync Polarity Status  
Result  
• Slave Address Byte  
• Base Register Address Byte  
• Data Byte to Read or Write  
• Stop Signal  
0
1
Coast Polarity Negative  
Coast Polarity Positive  
15  
7
4:2:2 Output Mode Select  
When the serial interface is inactive (SCL and SDA are high)  
communications are initiated by sending a start signal. The start  
signal is a high-to-low transition on SDA while SCL is high.  
This signal alerts all slaved devices that a data transfer sequence  
is coming.  
A bit that configures the output data in 4:2:2 mode.  
This mode can be used to reduce the number of data  
lines used from 24 down to 16 for applications using  
YUV, VCbCr, or PbPr graphics signals. A timing dia-  
gram for this mode is shown in Figure 9.  
The first eight bits of data transferred after a start signal com-  
prising a 7-bit slave address (the first seven bits) and a single R/W  
bit (the eighth bit). The R/W bit indicates the direction of data  
transfer, read from (1) or write to (0) the slave device. If the  
transmitted slave address matches the address of the device (set by  
the state of the SA1-0 input pins in Table XXXIV, the AD9883A  
acknowledges by bringing SDA LOW on the 9th SCL pulse. If  
the addresses do not match, the AD9883A does not acknowledge.  
Recommended input and output configurations are  
shown in Table XXXV. In 4:2:2 mode, the red and  
blue channels can be interchanged to help satisfy board  
layout or timing requirements, but the green channel  
must be configured for Y.  
Table XXXV. 4:2:2 Output Mode Select  
Select  
Output Mode  
Table XXXVII. Serial Port Addresses  
0
1
4:4:4  
4:2:2  
Bit 7  
A6  
Bit 6 Bit 5  
Bit 4  
A3  
Bit 3  
A2  
Bit 2  
A1  
Bit 1  
A0  
A5  
A4  
(MSB)  
Table XXXVI. 4:2:2 Input/Output Configuration  
Input  
1
1
0
0
0
0
1
1
1
1
0
0
0
1
Channel  
Connection  
Output Format  
Data Transfer via Serial Interface  
For each byte of data read or written, the MSB is the first bit of  
the sequence.  
Red  
Green  
Blue  
V
Y
U
U/V  
Y
High Impedance  
If the AD9883A does not acknowledge the master device during  
a write sequence, the SDA remains high so the master can  
generate a stop signal. If the master device does not acknowledge  
the AD9883A during a read sequence, the AD9883A interprets  
this as “end of data.” The SDA remains high so the master  
can generate a stop signal.  
2-WIRE SERIAL CONTROL PORT  
A 2-wire serial interface control interface is provided. Up to four  
AD9883A devices may be connected to the 2-wire serial inter-  
face, with each device having a unique address.  
The 2-wire serial interface comprises a clock (SCL) and a bidi-  
rectional data (SDA) pin. The Analog Flat Panel Interface acts  
as a slave for receiving and transmitting data over the serial inter-  
face. When the serial interface is not active, the logic levels on  
SCL and SDA are pulled high by external pull-up resistors.  
Writing data to specific control registers of the AD9883A requires  
that the 8-bit address of the control register of interest be written  
after the slave address has been established. This control register  
address is the base address for subsequent write operations. The  
base address autoincrements by one for each byte of data written  
after the data byte intended for the base address. If more bytes  
are transferred than there are available addresses, the address will  
not increment and remains at its maximum value of 14h. Any base  
address higher than 14h will not produce an acknowledge signal.  
Data received or transmitted on the SDA line must be stable for  
the duration of the positive-going SCL pulse. Data on SDA must  
change only when SCL is low. If SDA changes state while SCL  
is high, the serial interface interprets that action as a start or  
stop sequence.  
SDA  
t
BUFF  
t
t
DSU  
DHO  
t
STOSU  
t
STASU  
t
STAH  
t
DAL  
SCL  
t
DAH  
Figure 10. Serial Port Read/Write Timing  
–20–  
REV. 0  
AD9883A  
Data is read from the control registers of the AD9883A in a similar  
manner. Reading requires two data transfer operations:  
➥ Base Address Byte  
➥ Data Byte to Base Address  
➥ Data Byte to (Base Address + 1)  
➥ Data Byte to (Base Address + 2)  
➥ Data Byte to (Base Address + 3)  
➥ Stop Signal  
The base address must be written with the R/W bit of the slave  
address byte LOW to set up a sequential read operation.  
Reading (the R/W bit of the slave address byte high) begins at  
the previously established base address. The address of the read  
register autoincrements after each byte is transferred.  
Read from one control register  
➥ Start Signal  
➥ Slave Address Byte (R/W Bit = LOW)  
➥ Base Address Byte  
To terminate a read/write sequence to the AD9883A, a stop  
signal must be sent. A stop signal comprises a low-to-high tran-  
sition of SDA while SCL is high.  
➥ Start Signal  
➥ Slave Address byte (R/W bit = HIGH)  
➥ Data Byte from Base Address  
➥ Stop Signal  
A repeated start signal occurs when the master device driving  
the serial interface generates a start signal without first generat-  
ing a stop signal to terminate the current communication. This  
is used to change the mode of communication (read, write)  
between the slave and master without releasing the serial inter-  
face lines.  
Read from four consecutive control registers  
➥ Start Signal  
➥ Slave Address Byte (R/W Bit = LOW)  
➥ Base Address Byte  
➥ Start Signal  
Serial Interface Read/Write Examples  
Write to one control register  
➥ Start Signal  
➥ Slave Address Byte (R/W Bit = LOW)  
➥ Base Address Byte  
➥ Data Byte to Base Address  
➥ Stop Signal  
➥ Slave Address Byte (R/W Bit = HIGH)  
➥ Data Byte from Base Address  
➥ Data Byte from (Base Address + 1)  
➥ Data Byte from (Base Address + 2)  
➥ Data Byte from (Base Address + 3)  
➥ Stop Signal  
Write to four consecutive control registers  
➥ Start Signal  
➥ Slave Address Byte (R/W Bit = LOW)  
SDA  
SCL  
BIT 6 BIT 5 BIT 4  
BIT 3 BIT 2 BIT 1 BIT 0  
ACK  
BIT 7  
Figure 11. Serial Interface—Typical Byte Transfer  
ACTIVITY  
DETECT  
SYNC STRIPPER  
SYNC SEPARATOR  
NEGATIVE PEAK  
CLAMP  
COMP  
SYNC  
INTEGRATOR  
1/S  
VSYNC  
SOG  
MUX 1  
HSYNC IN  
SOG OUT  
PLL  
ACTIVITY  
DETECT  
POLARITY  
DETECT  
HSYNC OUT  
PIXEL CLOCK  
HSYNC  
HSYNC OUT  
CLOCK  
GENERATOR  
MUX 2  
MUX 3  
COAST  
COAST  
POLARITY  
DETECT  
AD9883A  
VSYNC IN  
VSYNC OUT  
ACTIVITY  
DETECT  
POLARITY  
DETECT  
MUX 4  
Figure 12. Sync Processing Block Diagram  
–21–  
REV. 0  
AD9883A  
Table XXXVIII. Control of the Sync Block Muxes via the  
Serial Register  
Analog Interface Inputs  
Using the following layout techniques on the graphics inputs is  
extremely important.  
Control  
Minimize the trace length running into the graphics inputs. This  
is accomplished by placing the AD9883A as close as possible  
to the graphics VGA connector. Long input trace lengths are  
undesirable because they will pick up more noise from the board  
and other external sources.  
Mux  
Nos.  
Serial Bus  
Control Bit State  
Bit  
Result  
1 and 2  
0EH: Bit 3  
0FH: Bit 5  
0EH: Bit 0  
0
1
0
1
0
1
Pass Hsync  
Pass Sync-on-Green  
Pass Coast  
Pass Vsync  
Pass Vsync  
3
4
Place the 75 Ω termination resistors (see Figure 1) as close to the  
AD9883A chip as possible. Any additional trace length between  
the termination resistors and the input of the AD9883A increases  
the magnitude of reflections, which will corrupt the graphics signal.  
Pass Sync Separator Signal  
Sync Slicer  
Use 75 Ω matched impedance traces. Trace impedances other  
The purpose of the sync slicer is to extract the sync signal from  
the green graphics channel. A sync signal is not present on all  
graphics systems, only those with “sync-on-green”. The sync  
signal is extracted from the green channel in a two-step process.  
First, the SOG input is clamped to its negative peak, (typically  
0.3 V below the black level). Next, the signal goes to a com-  
parator with a variable trigger level, nominally 0.15 V above the  
clamped level. The “sliced” sync is typically a composite sync  
signal containing both Hsync and Vsync.  
than 75 Ω will also increase the chance of reflections.  
The AD9883A has very high input bandwidth, (500 MHz). While  
this is desirable for acquiring a high-resolution PC graphics  
signal with fast edges, it means that it will also capture any high-  
frequency noise present. Therefore, it is important to reduce the  
amount of noise that gets coupled to the inputs. Avoid running  
any digital traces near the analog inputs.  
Due to the high bandwidth of the AD9883A, sometimes low-  
pass filtering the analog inputs can help to reduce noise. (For  
many applications, filtering is unnecessary.) Experiments have  
shown that placing a series ferrite bead prior to the 75 Ω termi-  
nation resistor is helpful in filtering out excess noise.  
Sync Separator  
A sync separator extracts the Vsync signal from a composite  
sync signal. It does this through a low-pass filter-like or integrator-  
like operation. It works on the idea that the Vsync signal stays  
active for a much longer time than the Hsync signal, so it  
rejects any signal shorter than a threshold value, which is some-  
where between an Hsync pulsewidth and a Vsync pulsewidth.  
Specifically, the part used was the # 2508051217Z0 from Fair-  
Rite, but each application may work best with a different bead  
value. Alternately, placing a 100 Ω to 120 Ω ohm resistor between  
the 75 Ω termination resistor and the input coupling capacitor  
can also benefit.  
The sync separator on the AD9883A is simply an 8-bit digital  
counter with a 5 MHz clock. It works independently of the  
polarity of the composite sync signal. (Polarities are determined  
elsewhere on the chip.) The basic idea is that the counter counts  
up when Hsync pulses are present. But since Hsync pulses are  
relatively short in width, the counter only reaches a value of N  
before the pulse ends. It then starts counting down eventually  
reaching 0 before the next Hsync pulse arrives. The specific  
value of N will vary for different video modes, but will always be  
less than 255. For example with a 1 µs width Hsync, the counter  
will only reach 5 (1 µs/200 ns = 5). Now, when Vsync is present  
on the composite sync the counter will also count up. However,  
since the Vsync signal is much longer, it will count to a higher  
number M. For most video modes, M will be at least 255. So,  
Vsync can be detected on the composite sync signal by detecting  
when the counter counts to higher than N. The specific count  
that triggers detection (T) can be programmed through the  
serial register (0fh).  
Power Supply Bypassing  
It is recommended to bypass each power supply pin with a  
0.1 µF capacitor. The exception is in the case where two or  
more supply pins are adjacent to each other. For these group-  
ings of powers/grounds, it is only necessary to have one bypass  
capacitor. The fundamental idea is to have a bypass capacitor  
within about 0.5 cm of each power pin. Also, avoid placing the  
capacitor on the opposite side of the PC board from the AD9883A,  
as that interposes resistive vias in the path.  
The bypass capacitors should be physically located between the  
power plane and the power pin. Current should flow from the  
power plane to the capacitor to the power pin. Do not make the  
power connection between the capacitor and the power pin.  
Placing a via underneath the capacitor pads, down to the power  
plane, is generally the best approach.  
It is particularly important to maintain low noise and good  
stability of PVD (the clock generator supply). Abrupt changes in  
PVD can result in similarly abrupt changes in sampling clock  
phase and frequency. This can be avoided by careful attention  
to regulation, filtering, and bypassing. It is highly desirable to  
provide separate regulated supplies for each of the analog cir-  
cuitry groups (VD and PVD).  
Once Vsync has been detected, there is a similar process to detect  
when it goes inactive. At detection, the counter first resets to 0,  
then starts counting up when Vsync goes away. Similar to the  
previous case, it will detect the absence of Vsync when the  
counter reaches the threshold count (T). In this way, it will  
reject noise and/or serration pulses. Once Vsync is detected to  
be absent, the counter resets to 0 and begins the cycle again.  
Some graphic controllers use substantially different levels of  
power when active (during active picture time) and when idle  
(during horizontal and vertical sync periods). This can result in  
a measurable change in the voltage supplied to the analog supply  
regulator, which can in turn produce changes in the regulated  
analog supply voltage. This can be mitigated by regulating the  
analog supply, or at least PVD, from a different, cleaner power  
source (for example, from a 12 V supply).  
PCB LAYOUT RECOMMENDATIONS  
The AD9883A is a high precision, high speed analog device. As  
such, to get the maximum performance out of the part it is  
important to have a well laid-out board. The following is a guide  
for designing a board using the AD9883A.  
–22–  
REV. 0  
AD9883A  
It is also recommended to use a single ground plane for the entire  
board. Experience has repeatedly shown that the noise perfor-  
mance is the same or better with a single ground plane. Using  
multiple ground planes can be detrimental because each separate  
ground plane is smaller, and long ground loops can result.  
Outputs (Both Data and Clocks)  
Try to minimize the trace length that the digital outputs have to  
drive. Longer traces have higher capacitance, which requires more  
current, which causes more internal digital noise.  
Shorter traces reduce the possibility of reflections.  
In some cases, using separate ground planes is unavoidable. For  
those cases, it is recommended to at least place a single  
ground plane under the AD9883A. The location of the split  
should be at the receiver of the digital outputs. For this case it  
is even more important to place components wisely because the  
current loops will be much longer (current takes the path of  
least resistance). An example of a current loop:  
Adding a series resistor of value 50 Ω to 200 Ω can suppress reflec-  
tions, reduce EMI, and reduce the current spikes inside of the  
AD9883A. If series resistors are used, place them as close to the  
AD9883A pins as possible (although try not to add vias or extra  
length to the output trace in order to get the resistors closer).  
If possible, limit the capacitance that each of the digital outputs  
drives to less than 10pF. This can easily be accomplished by  
keeping traces short and by connecting the outputs to only one  
device. Loading the outputs with excessive capacitance will  
increase the current transients inside of the AD9883A creating  
more digital noise on its power supplies.  
LA  
Digital Inputs  
The digital inputs on the AD9883A were designed to work with  
3.3 V signals, but are tolerant of 5.0 V signals. So, no extra  
components need to be added if using 5.0 V logic.  
R
D
D
Any noise that gets onto the Hsync input trace will add jitter to  
the system. Therefore, minimize the trace length and do not run  
any digital or other high-frequency traces near it.  
Figure 13. Current Loop  
Voltage Reference  
PLL  
Bypass with a 0.1 µF capacitor. Place as close to the AD9883A  
pin as possible. Make the ground connection as short as possible.  
Place the PLL loop filter components as close to the FILT pin  
as possible.  
Do not place any digital or other high-frequency traces near  
these components.  
Use the values suggested in the data sheet with 10% tolerances  
or less.  
REV. 0  
–23–  
AD9883A  
OUTLINE DIMENSIONS  
Dimensions shown in inches and (mm).  
80-Lead LQFP  
(ST-80)  
0.063 (1.60)  
MAX  
0.630 (16.00) BSC SQ  
0.551 (14.00) BSC SQ  
0.030 (0.75)  
0.024 (0.60)  
0.018 (0.45)  
80  
61  
1
60  
SEATING  
PLANE  
PIN 1  
TOP VIEW  
(PINS DOWN)  
COPLANARITY  
0.004 (0.10)  
MAX  
20  
41  
21  
40  
0.006 (0.15)  
0.002 (0.05)  
0.057 (1.45)  
0.055 (1.40)  
0.053 (1.35)  
0.008 (0.20)  
0.004 (0.09)  
0.0256 (0.65)  
BSC  
0.015 (0.38)  
0.013 (0.32)  
0.009 (0.22)  
7؇  
3.5؇  
0؇  
CONTROLLING DIMENSIONS IN MILLIMETERS.  
CENTER FIGURES ARE NOMINAL UNLESS OTHERWISE NOTED.  
–24–  
REV. 0  

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