Cypress Perform CY62136EV30 User Manual

CY62136EV30  
MoBL®  
2-Mbit (128K x 16) Static RAM  
Features  
Functional Description[1]  
• Very high speed: 45 ns  
The CY62136EV30 is a high-performance CMOS static RAM  
organized as 128K words by 16 bits. This device features  
advanced circuit design to provide ultra-low active current.  
• Wide voltage range: 2.20V–3.60V  
• Pin-compatible with CY62136CV30  
• Ultra low standby power  
®
This is ideal for providing More Battery Life™ (MoBL ) in  
portable applications such as cellular telephones. The device  
also has an automatic power-down feature that significantly  
reduces power consumption by 80% when addresses are not  
toggling. The device can also be put into standby mode  
reducing power consumption by more than 99% when  
— Typical standby current: 1µA  
— Maximum standby current: 7µA  
• Ultra-low active power  
deselected (CE HIGH). The input/output pins (I/O through  
0
— Typical active current: 2 mA @ f = 1 MHz  
• Easy memory expansion with CE, and OE features  
• Automatic power-down when deselected  
• CMOS for optimum speed/power  
I/O ) are placed in a high-impedance state when: deselected  
15  
(CE HIGH), outputs are disabled (OE HIGH), both Byte High  
Enable and Byte Low Enable are disabled (BHE, BLE HIGH),  
or during a write operation (CE LOW and WE LOW).  
Writing to the device is accomplished by taking Chip Enable  
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable  
• Offered in a Pb-free 48-ball VFBGA and 44-pin TSOP II  
packages  
(BLE) is LOW, then data from I/O pins (I/O through I/O ), is  
0
7
written into the location specified on the address pins (A  
0
through A ). If Byte High Enable (BHE) is LOW, then data  
16  
from I/O pins (I/O through I/O ) is written into the location  
8
15  
specified on the address pins (A through A ).  
0
16  
Reading from the device is accomplished by taking Chip  
Enable (CE) and Output Enable (OE) LOW while forcing the  
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,  
then data from the memory location specified by the address  
pins will appear on I/O to I/O . If Byte High Enable (BHE) is  
0
7
LOW, then data from memory will appear on I/O to I/O . See  
8
15  
the truth table at the back of this data sheet for a complete  
description of read and write modes.  
Logic Block Diagram  
DATA IN DRIVERS  
A10  
A9  
A8  
A7  
A6  
A5  
A4  
A3  
A2  
128K x 16  
RAM Array  
I/O0–I/O7  
I/O8–I/O15  
A1  
A0  
COLUMN DECODER  
BHE  
WE  
CE  
OE  
BLE  
Note:  
Cypress Semiconductor Corporation  
Document #: 38-05569 Rev. *B  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised January 6, 2006  
CY62136EV30  
MoBL®  
[5,6]  
DC Input Voltage  
............ –0.3V to 3.9V (V  
+ 0.3V)  
Maximum Ratings  
CC MAX  
Output Current into Outputs (LOW) ............................ 20 mA  
(Above which the useful life may be impaired. For user guide-  
lines, not tested.)  
Static Discharge Voltage ......................................... > 2001V  
(per MIL-STD-883, Method 3015)  
Storage Temperature ................................65°C to + 150°C  
Latch-up Current ....................................................> 200 mA  
Ambient Temperature with  
Power Applied ...........................................55°C to + 125°C  
Operating Range[7]  
Ambient  
Supply Voltage to Ground  
Potential ..............................0.3V to 3.9V (V  
[7]  
Device  
Range  
Temperature  
V
CC  
+ 0.3V)  
+ 0.3V)  
CC MAX  
CY62136EV30LL Industrial –40°Cto+85°C 2.2V - 3.6V  
DC Voltage Applied to Outputs  
[5,6]  
in High-Z State  
................0.3V to 3.9V (V  
CC MAX  
[5, 6, 7]  
Electrical Characteristics Over the Operating Range  
45 ns  
[4]  
Parameter  
Description  
Output HIGH  
Voltage  
Test Conditions  
Min.  
2.0  
Typ.  
Max.  
Unit  
V
V
V
V
V
I
I
I
I
I
= –0.1 mA  
= –1.0 mA  
= 0.1 mA  
= 2.1mA  
V
V
V
V
= 2.20V  
= 2.70V  
= 2.20V  
= 2.70V  
OH  
OL  
IH  
OH  
OH  
OL  
OL  
CC  
CC  
CC  
CC  
2.4  
V
Output LOW  
Voltage  
0.4  
0.4  
V
V
Input HIGH Voltage V = 2.2V to 2.7V  
1.8  
2.2  
V
V
+ 0.3  
V
CC  
CC  
CC  
V
V
V
= 2.7V to 3.6V  
= 2.2V to 2.7V  
= 2.7V to 3.6V  
+ 0.3  
V
CC  
CC  
CC  
Input LOW Voltage  
–0.3  
–0.3  
–1  
0.6  
V
IL  
0.8  
+1  
V
Input Leakage  
Current  
GND < V < V  
CC  
µA  
IX  
I
I
Output Leakage  
Current  
GND < V < V , Output Disabled  
–1  
+1  
µA  
OZ  
O
CC  
I
V
Operating  
f = f  
= 1/t  
V
= V = 0 mA  
I
15  
2
20  
2.5  
7
mA  
CC  
CC  
MAX  
RC  
CC  
CCmax, OUT  
Supply Current  
CMOS levels  
f = 1 MHz  
CE > V 0.2V,  
I
Automatic CE  
Power-down  
1
µA  
SB1  
CC  
V >V –0.2V, V <0.2V)  
IN  
CC  
IN  
Current — CMOS f = f  
(Address and Data Only),  
MAX  
Inputs  
f = 0 (OE, and WE),  
V
= 3.60V  
CC  
I
Automatic CE  
Power-down  
Current — CMOS  
Inputs  
CE > V – 0.2V,  
1
7
µA  
SB2  
CC  
V
V
> V – 0.2V or V < 0.2V, f = 0,  
IN  
CC IN  
= 3.60V  
CC  
[8]  
Capacitance (for all packages)  
Parameter  
Description  
Test Conditions  
Max.  
10  
Unit  
pF  
C
C
Input Capacitance  
Output Capacitance  
T = 25°C, f = 1 MHz,  
IN  
A
V
= V  
CC  
CC(typ)  
10  
pF  
OUT  
Notes:  
5. V  
6. V  
= –2.0V for pulse durations less than 20 ns.  
IL(min.)  
=V +0.75V for pulse durations less than 20ns.  
IH(max)  
CC  
7. Full Device AC operation assumes a 100 µs ramp time from 0 to Vcc(min) and 200 µs wait time after V stabilization.  
CC  
8. Tested initially and after any design or process changes that may affect these parameters.  
Document #: 38-05569 Rev. *B  
Page 3 of 12  
CY62136EV30  
MoBL®  
Thermal Resistance[8]  
VFBGA  
Package  
TSOP II  
Package  
Parameter  
Description  
Test Conditions  
Unit  
Θ
Thermal Resistance  
(Junction to Ambient)  
Still Air, soldered on a 3 × 4.5 inch, two-layer  
printed circuit board  
75  
77  
°C/W  
JA  
[8]  
Θ
Thermal Resistance  
(Junction to Case)  
10  
13  
°C/W  
JC  
[8]  
AC Test Loads and Waveforms  
R1  
ALL INPUT PULSES  
90%  
10%  
V
V
CC  
CC  
90%  
OUTPUT  
10%  
GND  
Rise Time = 1 V/ns  
R2  
30 pF  
Fall Time = 1 V/ns  
INCLUDING  
JIG AND  
SCOPE  
Equivalent to: THÉVENIN EQUIVALENT  
R
TH  
OUTPUT  
V
TH  
Parameters  
2.50V  
16667  
15385  
8000  
3.0V  
1103  
1554  
645  
Unit  
R1  
R2  
R
TH  
TH  
V
1.20  
1.75  
V
[8, 9]  
Data Retention Characteristics (Over the Operating Range)  
[4]  
Parameter  
Description  
Conditions  
Min.  
Typ.  
Max.  
Unit  
V
V
I
V
for Data Retention  
1.0  
DR  
CC  
Data Retention Current  
V
= 1.0V  
0.8  
3
µA  
CCDR  
CC  
CE > V – 0.2V,  
CC  
V
> V – 0.2V or V < 0.2V  
IN  
CC  
IN  
[8]  
t
t
Chip Deselect to Data  
Retention Time  
0
ns  
ns  
CDR  
[9]  
R
Operation Recovery  
Time  
t
RC  
Data Retention Waveform  
DATA RETENTION MODE  
V
V
CC(min)  
CC(min)  
V
> 1.0 V  
V
CC  
DR  
t
t
R
CDR  
CE  
Notes:  
9. Full device operation requires linear V ramp from V to V  
> 100 µs or stable at V  
> 100 µs.  
CC(min.)  
CC  
DR  
CC(min.)  
Document #: 38-05569 Rev. *B  
Page 4 of 12  
CY62136EV30  
MoBL®  
[10, 11, 12, 13]  
Switching Characteristics Over the Operating Range  
45 ns  
Parameter  
Read Cycle  
Description  
Min.  
45  
Max.  
Unit  
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Read Cycle Time  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
RC  
Address to Data Valid  
45  
AA  
Data Hold from Address Change  
CE LOW to Data Valid  
10  
OHA  
ACE  
DOE  
LZOE  
HZOE  
LZCE  
HZCE  
PU  
45  
22  
OE LOW to Data Valid  
[11]  
OE LOW to LOW Z  
5
10  
0
[11, 12]  
OE HIGH to High Z  
18  
18  
[11]  
CE LOW to Low Z  
[11, 12]  
CE HIGH to High Z  
CE LOW to Power-Up  
CE HIGH to Power-Down  
BLE/BHE LOW to Data Valid  
45  
22  
PD  
DBE  
LZBE  
HZBE  
[11]  
BLE/BHE LOW to Low Z  
5
[11, 12]  
BLE/BHE HIGH to HIGH Z  
18  
[13]  
Write Cycle  
t
t
t
t
t
t
t
t
t
t
t
Write Cycle Time  
45  
35  
35  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
WC  
CE LOW to Write End  
SCE  
AW  
Address Set-Up to Write End  
Address Hold from Write End  
Address Set-Up to Write Start  
WE Pulse Width  
HA  
0
SA  
35  
35  
25  
0
PWE  
BW  
BLE/BHE LOW to Write End  
Data Set-Up to Write End  
Data Hold from Write End  
SD  
HD  
[11, 12]  
WE LOW to High-Z  
18  
HZWE  
LZWE  
[11]  
WE HIGH to Low-Z  
10  
Notes:  
10. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns (1V/ns) or less, timing reference levels of V  
/2, input  
CC(typ)  
pulse levels of 0 to V  
, and output loading of the specified I /I as shown in the “AC Test Loads and Waveforms” section.  
CC(typ.)  
OL OH  
11. At any given temperature and voltage condition, t  
is less than t  
, t  
is less than t  
, t  
is less than t  
, and t  
is less than t  
for any  
HZCE  
LZCE HZBE  
LZBE HZOE  
LZOE  
HZWE  
LZWE  
given device.  
12. t  
, t  
, t  
, and t  
transitions are measured when the outputs enter a high impedence state.  
HZOE HZCE HZBE  
HZWE  
13. The internal Write time of the memory is defined by the overlap of WE, CE = V , BHE and/or BLE = V . All signals must be ACTIVE to initiate a write and any  
IL  
IL  
of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates  
the write.  
Document #: 38-05569 Rev. *B  
Page 5 of 12  
CY62136EV30  
MoBL®  
Switching Waveforms [14, 15]  
[14, 15]  
Read Cycle 1 (Address Transition Controlled)  
t
RC  
ADDRESS  
t
AA  
t
OHA  
DATA OUT  
PREVIOUS DATA VALID  
DATA VALID  
[15, 16]  
Read Cycle No. 2 (OE Controlled)  
ADDRESS  
CE  
t
RC  
t
PD  
HZCE  
t
t
ACE  
OE  
t
HZOE  
t
DOE  
BHE/BLE  
t
LZOE  
t
HZBE  
t
DBE  
t
LZBE  
HIGH  
IMPEDANCE  
HIGH IMPEDANCE  
DATA OUT  
DATA VALID  
t
LZCE  
t
PU  
V
I
CC  
CC  
SUPPLY  
CURRENT  
50%  
50%  
I
SB  
Notes:  
14. The device is continuously selected. OE, CE= V , BHE and/or BLE = V  
.
IL  
IL  
15. WE is HIGH for read cycle.  
16. Address valid prior to or coincident with CE and BHE, BLE transition LOW.  
Document #: 38-05569 Rev. *B  
Page 6 of 12  
CY62136EV30  
MoBL®  
[14, 15]  
Switching Waveforms (continued)  
[13, 17, 18]  
Write Cycle No. 1 (WE Controlled)  
t
WC  
ADDRESS  
CE  
tSCE  
t
t
HA  
AW  
t
SA  
t
PWE  
WE  
t
BW  
BHE/BLE  
OE  
t
SD  
t
HD  
DATAIN  
DATA I/O  
NOTE19  
t
HZOE  
[13, 17, 18]  
Write Cycle No. 2 (CE Controlled)  
t
WC  
ADDRESS  
CE  
t
SCE  
t
SA  
t
t
HA  
AW  
tPWE  
WE  
t
BW  
BHE/BLE  
OE  
t
t
SD  
HD  
DATAIN  
DATA I/O  
NOTE 19  
t
HZOE  
Notes:  
17. Data I/O is high impedance if OE = V  
.
IH  
18. If CE goes HIGH simultaneously with WE = V , the output remains in a high-impedance state.  
IH  
19. During this period, the I/Os are in output state and input signals should not be applied.  
Document #: 38-05569 Rev. *B  
Page 7 of 12  
CY62136EV30  
MoBL®  
[14, 15]  
Switching Waveforms (continued)  
[18]  
Write Cycle No. 3 (WE Controlled, OE LOW)  
t
WC  
ADDRESS  
CE  
t
SCE  
t
BW  
BHE/BLE  
t
t
HA  
AW  
t
SA  
t
PWE  
WE  
t
HD  
t
SD  
NOTE 19  
DATAI/O  
DATAIN  
t
HZWE  
t
LZWE  
[18]  
Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)  
t
WC  
ADDRESS  
CE  
t
SCE  
t
t
HA  
AW  
tBW  
BHE/BLE  
t
SA  
tPWE  
WE  
tHZWE  
tHD  
t
SD  
DATA I/O  
DATAIN  
NOTE 19  
tLZWE  
Document #: 38-05569 Rev. *B  
Page 8 of 12  
CY62136EV30  
MoBL®  
Truth Table  
CE  
WE  
OE  
BHE  
BLE  
Inputs/Outputs  
High Z  
High Z  
Data Out (I/O –I/O  
Mode  
Power  
H
X
X
X
X
Deselect/Power-down  
Standby (I  
)
SB  
L
L
L
X
H
H
X
L
L
H
L
H
L
L
Output Disabled  
Read  
Active (I  
Active (I  
Active (I  
)
)
)
CC  
CC  
CC  
)
15  
O
H
Data Out (I/O –I/O );  
Read  
O
7
I/O –I/O in High Z  
8
15  
L
H
L
L
H
Data Out (I/O –I/O );  
Read  
Active (I  
)
8
15  
CC  
I/O –I/O in High Z  
0
7
L
L
L
L
L
H
H
H
L
H
H
H
X
X
L
H
L
L
L
H
L
L
High Z  
Output Disabled  
Output Disabled  
Output Disabled  
Write  
Active (I  
Active (I  
Active (I  
Active (I  
Active (I  
)
)
)
)
)
CC  
CC  
CC  
CC  
CC  
High Z  
High Z  
L
Data In (I/O –I/O  
)
O
15  
L
H
Data In (I/O –I/O );  
Write  
O
7
I/O –I/O in High Z  
8
15  
L
L
X
L
H
Data In (I/O –I/O );  
Write  
Active (I  
)
8
15  
CC  
I/O –I/O in High Z  
0
7
Ordering Information  
Speed  
(ns)  
Package  
Diagram  
Operating  
Range  
Ordering Code  
Package Type  
45  
CY62136EV30LL-45BVXI  
CY62136EV30LL-45ZSXI  
51-85150 48-ball Very Fine Pitch Ball Grid Array (Pb-free)  
51-85087 44-pin Thin Small Outline Package II (Pb-free)  
Industrial  
Please contact your local Cypress sales representative for availability of other parts  
Document #: 38-05569 Rev. *B  
Page 9 of 12  
CY62136EV30  
MoBL®  
Package Diagrams  
48-pin VFBGA (6 x 8 x 1 mm) (51-85150)  
BOTTOM VIEW  
A1 CORNER  
TOP VIEW  
Ø0.05 M C  
Ø0.25 M C A B  
A1 CORNER  
Ø0.30 0.05(48X)  
1
2
3
4
5
6
6
5
4
3
2
1
A
A
B
C
D
B
C
D
E
E
F
F
G
G
H
H
1.875  
A
A
0.75  
B
6.00 0.10  
3.75  
B
6.00 0.10  
0.15(4X)  
51-85150-*D  
SEATING PLANE  
C
Document #: 38-05569 Rev. *B  
Page 10 of 12  
CY62136EV30  
MoBL®  
Package Diagrams (continued)  
44-pin TSOP II (51-85087)  
51-85087-*A  
MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor. All product and company  
names mentioned in this document may be the trademarks of their respective holders.  
Document #: 38-05569 Rev. *B  
Page 11 of 12  
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be  
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its  
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
CY62136EV30  
MoBL®  
Document History Page  
®
Document Title: CY62136EV30 MoBL 2-Mbit (128K x 16) Static RAM  
Document Number: 38-05569  
Orig. of  
REV.  
**  
ECN NO. Issue Date Change  
Description of Change  
237432  
419988  
See ECN  
See ECN  
AJU  
New Data Sheet  
*A  
RXU  
Converted from Advanced Information to Final.  
Changed the address of Cypress Semiconductor Corporation on Page #1  
from “3901 North First Street” to “198 Champion Court”  
Removed 35ns Speed Bin  
Removed “L” version of CY62136EV30  
Changed I (Max) value from 2 mA to 2.5 mA and I (Typ) value from  
CC  
CC  
1.5 mA to 2 mA at f=1 MHz  
Changed I (Typ) value from 12 mA to 15 mA at f = f  
CC  
max  
Changed I  
and I  
Typ. values from 0.7 µA to 1 µA and Max. values from  
SB1  
SB2  
2.5 µA to 7 µA.  
Changed the AC test load capacitance from 50pF to 30pF on Page# 4  
Changed V from 1.5V to 1V on Page# 4.  
DR  
Changed I  
Added I  
from 2.5 µA to 3 µA.  
CCDR  
typical value.  
CCDR  
Changed t  
Changed t  
Changed t  
Changed t  
Changed t  
Changed t  
t
and t  
from 6 ns to 10 ns  
OHA , LZCE  
LZWE  
from 6 ns to 5 ns  
LZBE  
LZOE  
from 3 ns to 5 ns  
and t  
t
t
from 15 ns to 18 ns  
HZWE  
from 40 ns to 35 ns  
HZOE, HZCE, HZBE  
t
t
SCE, AW and BW  
from 30 ns to 35 ns  
PWE  
Changed t from 20 ns to 25 ns  
SD  
Corrected typo in the Truth Table on Page# 9  
Updated the package diagram 48-pin VFBGA from *B to *D  
Updated the ordering Information table and replaced the Package Name  
column with Package Diagram.  
*B  
427817  
See ECN  
NXR  
Minor change: Moved datasheet to external web  
Document #: 38-05569 Rev. *B  
Page 12 of 12  

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