Panasonic MN101C00 User Manual
MICROCOMPUTER MN101C00  
MN101C115/117  
LSI User’s Manual  
Pub. No. 21411-011E  
PanaXSeries is a trademark of Matsushita Electric Industrial Co., Ltd.  
The other corporation names,logotype and product names written in this book are trademarks or registered trademarks of their  
corresponding corporations.  
Request for your special attention and precautions in using the technical  
information and semiconductors described in this book  
(1)  
(2)  
An export permit needs to be obtained from the competent authorities of the Japanese Government if any  
of the products or technologies described in this book and controlled under the "Foreign Exchange and  
Foreign Trade Control Law" is to be exported or taken out of Japan.  
The contents of this book are subject to change without notice in matters of improved function. When  
finalizing your design,therefore,ask for the most up-to-date version in advance in order to check for any  
changes.  
(3)  
(4)  
(5)  
We are not liable for any damage arising out of the use of the contents of this book, or for any  
infringement of patents or any other rights owned by a third party.  
No part of this book may be reprinted or reproduced by any means without written permission from our  
company.  
This book deals with standard specifications. Ask for the latest individual Product Standards or Specifications  
in advance for more detailed information required for your design,purchasing and applications.  
If you have any inquiries or questions about this book or our semiconductors, please contact one of  
our sales offices listed at the back of this book or Matsushita Electronics Corporation's Sales  
Department.  
How to Read This Manual  
The MN101C11x incorporates more than one ROM/RAM to meet a variety of applications. An EPROM version as  
well as a Mask ROM version is available so users can write a program by themselves.  
ROM  
RAM  
8K  
MN101C115*1  
MN101C117  
MN101CP117  
256  
16K  
16K  
512  
512  
*1 : Under plannin  
Unit Byte  
■ Organization  
In this LSI manual, the MN101C117 functions are presented in the following order: overview, CPU basic functions,  
port functions, timer functions, serial functions, and other peripheral hardware functions.  
How to Read This Manual–1  
■ Manual Configuration  
Each section of this manual consists of a title, summary, main text, supplemental information, precautions and  
warnings. The layout and definition of each section are shown below.  
Chapter 4 Timer Functions  
Subtitle  
4-3 16-bit Timer Operation (timer 4)  
Sub-subtitle  
Summary  
Introduction to the  
section.  
The smallest block  
in this manual.  
4-3-1 Overview  
Timer 4 is a 16-bit programmable counter that can be used as an event counter.  
A signal with frequency of 1/2 of the timer 4 overflow signal can be output from the  
TM4IO pin. An input capture function and added pulse PWM output function can  
also be used.  
■ Timer Operation  
Main text  
Settings for timer operation are listed below.  
Supplementary  
information  
(1)  
(2)  
(3)  
Set the TM4EN flag of the timer 4 mode register (TM4MD) to "0" so that the count  
When servicing an interrupt, reset  
the timer interrupt request flag  
before operating timer 4.  
operation of timer 4 is stopped.  
4
Supplementary  
information for the  
main text. An  
explanation of  
terminology is also  
included.  
Set the TM4CK2~0 flags of the TM4MD register to select fosc, fs/4, or fs/16 as the  
clock source.  
During  
a
count operation, be  
Set the TM4PWM flag of the TM4MD register to "0" so that 16-bit timer operation is  
selected.  
careful if the value set in TM4OCH  
and TM4OCL is smaller than the  
value of binary counter 4, since  
the count-up operation will  
continue until overflow occurs.  
Clock  
TM4EN  
Write to registers  
TM4OCH, TM4OCL  
Binary  
counter 4  
04  
05  
06  
07  
08  
09  
00  
Figure 4-3-1 Binary Counter 4 (TM4BC) Count Timing  
Precautions and  
warnings  
Precautions are  
listed in case of lost  
functionality or  
damage.  
Key information  
Important  
information from  
the text.  
If the TM4EN flag of the TM4MD register is changed  
simultaneously with other bits, the switching operation may cause  
binary counter 4 to be incremented.  
If the value of TM4OCH and TM4OCL registers is overwritten while  
timer 4 has stopped counting, binary counter 4 will be reset to  
X'0000'.  
Be sure to read.  
16-bit Timer Operation (timer 4)  
83  
How to Read This Manual–2  
■ Finding Desired Information  
This manual provides four methods for finding desired information quickly and easily.  
(1) Consult the index at the front of the manual to locate the beginning of each section.  
(2) Consult the table of contents at the front of the manual to locate desired titles.  
(3) Consult the list of figures at the front of the manual to locate illustrations and charts by title name.  
(4) Chapter names are located at the top outer corner of each page, and section titles are located at the bottom  
outer corner of each page.  
■ Related Manuals  
The following manuals are also available from Panasonic as part of the MN101C00 series.  
MN101C00 Series LSI Manual  
<Device Hardware Description>  
MN101C00 Series Command Manual  
<Command Descriptions>  
MN101C00 Series Cross Assembler User's Manual  
<Assembler Syntax and Entry Methods>  
MN101C00 Series C Compiler User's Manual  
Operation  
<C Compiler Installation, Startup, Option Descriptions>  
MN101C00 Series C Compiler User's Manual  
Language  
<C Language Syntax Description>  
MN101C00 Series C Compiler User's Manual  
Library  
<C Compiler Standard Library Description>  
MN101C00 Series C Source Code Debugger User's Manual  
<C Source Code Debugger Usage Methods>  
MN101C00 Series PanaX Series Installation Manual  
<Installation of C Compiler, Cross Assembler, C Source Code Debugger; In-circuit  
Emulator>  
■ Where to Send Inquires  
Please send any inquires or questions concerning the contents of this manual to the Panasonic semiconductor design  
center closest to you. A list of addresses is provided at the end of this manual for your convenience.  
How to Read This Manual–3  
Contents  
0
1
2
3
4
5
6
7
8
Chapter 1  
Chapter 2  
Chapter 3  
Chapter 4  
Chapter 5  
Chapter 6  
Chapter 7  
Overview  
Basic CPU Functions  
Port Functions  
Timer Functions  
Serial Functions  
A/D Conversion  
Functions  
AC Zero-Cross  
Circuit/Noise Filter  
Appendices  
Contents  
0
Contents  
Chapter 1 Overview  
1-1 Product Overview...........................................................................................................2  
1-1-1 Overview ..........................................................................................................2  
1-1-2 Product Summary .............................................................................................2  
1-2 Hardware Functions .......................................................................................................3  
1-3 Pins.................................................................................................................................5  
1-3-1 Pin Diagram......................................................................................................5  
1-3-2 Pin Function Summary .....................................................................................8  
1-4 Overview of Functions.................................................................................................12  
1-4-1 Block Diagram................................................................................................12  
1-5 Electrical Characteristics..............................................................................................13  
1-5-1 Absolute Maximum Ratings...........................................................................13  
1-5-2 Operating Conditions......................................................................................14  
1-5-3 DC Characteristics.........................................................................................17  
1-5-4 A/D Converter Characteristics........................................................................21  
1-6 Option...........................................................................................................................22  
1-6-1 ROM Option...................................................................................................22  
1-6-2 Option Check List...........................................................................................23  
1-7 Outline Drawings .........................................................................................................24  
Chapter 2 Basic CPU Functions  
2-1 Overview......................................................................................................................28  
2-2 Address Space  
2-2-1 Memory Configuration...................................................................................28  
2-2-2 Special Function Registers .............................................................................28  
2-3 Bus Interface ................................................................................................................29  
2-3-1 Overview .......................................................................................................30  
2-3-2 Control Register..............................................................................................30  
2-4 Interrupts ......................................................................................................................31  
2-4-1 Accepting and Returning from Interrupts.......................................................31  
2-4-2 Interrupt Sources and Vector Addresses.........................................................33  
2-4-3 Interrupt Control Registers .............................................................................34  
2-5 Reset.............................................................................................................................36  
<Contents 1>  
Chapter 3 Port Functions  
3-1 Overview......................................................................................................................38  
3-2 Port Control Registers..................................................................................................41  
3-2-1 Overview ........................................................................................................41  
3-2-2 I/O Port Control Registers ..............................................................................45  
3-3 I/O Port Configuration and Functions..........................................................................47  
Chapter 4 Timer Functions  
4-1 Overview......................................................................................................................56  
4-2 8-bit Timer Operation (timers 2, 3)..............................................................................62  
4-2-1 Overview ........................................................................................................62  
4-2-2 Operation ........................................................................................................63  
4-3 16-bit Timer Operation (timer 4)..................................................................................69  
4-3-1 Overview ........................................................................................................69  
4-3-2 Operation ........................................................................................................69  
4-4 8-bit Timer Operation (timer 5)....................................................................................76  
4-4-1 Overview ........................................................................................................76  
4-4-2 Operation ........................................................................................................76  
4-5 Time Base Operation....................................................................................................77  
4-5-1 Overview ........................................................................................................77  
4-5-2 Operation ........................................................................................................77  
4-6 Watchdog Timer Operation..........................................................................................78  
4-6-1 Overview ........................................................................................................78  
4-6-2 Setup and Operation .......................................................................................78  
4-7 Remote Control Output Operation...............................................................................79  
4-7-1 Overview ........................................................................................................79  
4-7-2 Setup and Operation .......................................................................................79  
4-8 Buzzer Output ..............................................................................................................80  
4-8-1 Buzzer Output Setup and Operation...............................................................80  
4-9 Timer Function Control Registers................................................................................81  
4-9-1 Overview ........................................................................................................81  
4-9-2 Programmable Timer/Counters ......................................................................82  
4-9-3 Timer Mode Registers ....................................................................................85  
4-9-4 Timer Control Registers .................................................................................89  
<Contents 2>  
Chapter 5 Serial Functions  
5-1 Overview......................................................................................................................92  
5-2 Synchronous Serial Interface .......................................................................................94  
5-2-1 Overview ........................................................................................................94  
5-2-2 Setup and Operation .......................................................................................94  
5-2-3 Serial Interface Transfer Timing.....................................................................99  
5-3 Half-duplex UART Serial Interface ...........................................................................101  
5-3-1 Overview ......................................................................................................101  
5-3-2 Setup and Operation .....................................................................................101  
5-3-3 How to Use the Baud Rate Timer.................................................................105  
5-4 Serial Interface Control Registers ..............................................................................106  
5-4-1 Overview ......................................................................................................106  
5-4-2 Transmit/Receive Shift Registers, Receive Data Buffer ..............................107  
5-4-3 Serial Interface Mode Registers ...................................................................108  
5-4-4 Serial Interface Control Register ..................................................................112  
Chapter 6 A/D Conversion Functions  
6-1 Overview ....................................................................................................................114  
6-2 A/D Conversion..........................................................................................................115  
6-3 A/D Converter Control Registers...............................................................................117  
6-3-1 Overview.......................................................................................................117  
6-3-2 A/D Control Register (ANCTR)...................................................................118  
6-3-3 A/D Buffers (ANBUF) .................................................................................120  
Chapter 7 AC Zero-Cross Circuit/Noise Filter  
7-1 Overview....................................................................................................................122  
7-2 AC Zero-Cross Circuit Operation ..............................................................................123  
7-2-1 Setup and Operation .....................................................................................123  
7-3 Noise Filter.................................................................................................................124  
7-3-1 Overview ......................................................................................................124  
7-3-2 Example Input and Output Waveforms for Noise Filter...............................125  
7-4 AC Zero-Cross Control Register................................................................................126  
7-4-1 Overview ......................................................................................................126  
7-4-2 Noise Filter Control Register (NFCTR) .......................................................127  
<Contents 3>  
Appendices  
8-1 EPROM Versions .......................................................................................................130  
8-1-1 Overview ......................................................................................................130  
8-1-2 Cautions on Use............................................................................................131  
8-1-3 Erasing Written Data in Windowed Packages..............................................132  
(PX-AP101C11-SDC, PX-AP101C11-FBC)  
8-1-4 Characteristics of EPROM Versions.............................................................133  
8-1-5 Writing to Internal EPROM..........................................................................134  
8-1-6 Cautions on Handling the ROM Writer........................................................136  
8-1-7 Option Bit .....................................................................................................137  
8-1-8 Writing Adapter Connection.........................................................................138  
8-2 Instruction Sets...........................................................................................................141  
8-3 Instruction Maps.........................................................................................................147  
8-4 Special Function Registers.........................................................................................149  
<Contents 4>  
Chapter 1  
Overview  
1
1
Chapter 1 Overview  
1-1 Product Overview  
1-1-1 Overview  
The MN101C00 series of 8-bit single-chip microcomputers incorporate several types of  
peripheral functions. This chip series is well suited for VCR, MD, TV, CD, LD, printer,  
telephone, home automation, pager, air conditioner, PPC, remote control, fax machine,  
musical instrument, and other applications.  
The MN101C117 has an internal 16 KB of ROM and 512 bytes of RAM. Peripheral  
functions include four sets of timers, one set of serial interfaces, an A/D converter, and  
remote control output. The configuration of this microcomputer is well suited for applications  
as a system controller in a VCR selection timer, CD player, MD, or portable terminal.  
With two oscillation systems (max. 20 MHz/32 kHz) contained on the chip of 48-pin QFP  
package, the system clock can be switched between high and low speed.  
When the oscillation source (fosc) is 8 MHz, a machine cycle lasts for 250 ns. When fosc is  
20 MHz, a machine cycle is 100 ns. The package are available with three types of 42-pin  
SDIP, 44-pin QFP and 48-pin QFH.  
1-1-2 Product Summary  
This manual describes the following models of the MN101C11 series. These products have  
identical functions.  
Table 1-1-1 Product Summary  
Model  
ROM Size  
8 KB  
RAM Size  
256 bytes  
512 bytes  
512 bytes  
Classification  
Mask ROM version  
Mask ROM version  
EPROM version  
1
MN101C115*  
MN101C117  
16 KB  
MN101CP117  
16 KB  
∗1 Under development  
2
Product Overview  
Chapter 1 Overview  
1-2 Hardware Functions  
∗2 Differs depending upon the  
model.  
ROM/RAM Size:  
<Single chip mode>  
[☞ 1-1-2 "Product Summary"]  
Internal ROM∗2  
Internal RAM∗2  
16,384×8-bit*  
512×8-bit  
3
*3 Bit 8 of the last address for  
the built-in ROM of MN101C11X  
is an optional bit; therefore, this  
cannot be used as an ordinary  
ROM.  
Machine Cycles:  
High speed mode 0.10µs/20MHz (4.5V to 5.5V)  
0.25µs/8MHz(2.7V to 5.5V)  
1.00µs/2MHz(2.0V to 5.5V)  
4
Low speed mode 125µs/32KHz(2.0V to 5.5V)*  
*4 Exclusive for a 48-pin QFH  
product.  
Interrupts:  
12 interrupts(11 interrupts except for 48-pin QFH package)  
<External interrupts>  
The active edge can be selected for all external interrupts  
IRQ0 External interrupt (can be connected to noise filter)  
IRQ1 External interrupt (can determine zero crossings, can be  
connected to noise filter)  
IRQ2 External interrupt  
4
IRQ3 External interrupt *  
<Timer interrupts>  
TM2IRQ Timer 2 (8-bit timer)  
TM3IRQ Timer 3 (8-bit timer)  
TM4IRQ Timer 4 (16-bit timer)  
TM5IRQ Timer 5 (8-bit timer)  
TBIRQ Clock timer interrupts  
<Serial communication interrupt>  
SC0IRQ Serial 0 (synchronous + simple UART  
<A/D conversion complete interrupt>  
ADIRQ A/D conversion complete  
<Watchdog timer interrupt>  
NMI Overflow of watchdog timer  
Timer/Counters:five timers, all can generate interrupts  
Timer 2 8-bit timer  
Square wave output, 8-bit PWM output are possible,  
4
Clock source: fs, fs/4, fx* , TM2IO pin input  
Timer 3 8-bit timer  
Square wave output, synchronous serial/UART baud rate  
timer  
Clock source: fosc, fs/4, fs/16, TM3IO pin input  
Remote control carrier can be generated.  
Hardware Functions  
3
Chapter 1 Overview  
Timers 2 and 3 can be cascaded.  
Timer 4 16-bit timer  
Square wave output, 16-bit PWM output are possible.  
Clock source: fosc, fs/4, fs/16, TM4IO pin input  
Input capture function  
Time base timer  
4
13  
4
13  
Clock source: fosc, fs/4, fx* , fx/2 * or fosc/2  
4
XIOat 32kHz, can be set to measure one minute intervals*  
Can operate independently as timer 5 (8-bit timer).  
Watchdog timer  
16  
18  
20  
Selected by the mask option as fs/2 , fs/2 , or fs/2  
Remote control Based on the timer output, a remote control carrier with duty ratio  
carrier output:  
Buzzer output:  
Serial interface:  
of 1/2, 1/3 can be output.  
9
10  
11  
12  
Output frequency can be selected from fs/2 , fs/2 , fs/2 or fs/2 .  
Synchronous/ Simple UART (half-duplex)  
Transfer clock: fs/2, fs/4, fs/16, 1/2 of timer 3 output  
When using timer 3, the transfer rates for a 12MHz  
oscillation are 19200/9600/4800/2400/1200/300 bps.  
MSB or LSB can be selected as the first bit for transfer. An  
arbitrary transfer size of 1 to 8 bits can be selected.  
A/D converter:  
10 bits x 8 channels  
LED driver function:8 pins  
5
Ports:  
I/O ports  
25 ports (8 have dual functions)*  
LED (large current) driver ports:  
8 ports (push-pull configuration)  
11 ports (all have dual functions) *  
∗5  
26 ports for 44-QFP  
27 ports for 48-QFH  
6
Input ports  
7
Number of pins with dual function for external interrupts: 3*  
(One of which can also be used for zero-cross input.)  
∗
6
12 ports for 48-QFH  
4 ports for 48-QFH  
Number of pins with dual function for A/D input:  
8
1
1
Operation mode input pin:  
Reset input pin:  
∗7  
Operation modes: NORMAL mode  
4
SLOW mode*  
HALT mode  
STOP mode  
4
and switches operating clock*  
Package:  
42-SDIP, 44-QFP, 48-QFH  
4
Hardware Functions  
Chapter 1 Overview  
1-3 Pins  
1-3-1 Pin Diagram  
TXD,SBO0,P00  
RXD,SBI0,P01  
SBT0,P02  
BUZZER, P06  
RM OUT,P10  
P11  
1
2
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
VSS  
OSC1  
3
OSC2  
4
VDD  
5
PA7,AN7  
PA6,AN6  
PA5,AN5  
PA4,AN4  
PA3,AN3  
PA2,AN2  
PA1,AN1  
PA0,AN0  
P80,LED0  
P81,LED1  
P82,LED2  
P83,LED3  
P84,LED4  
P85,LED5  
P86,LED6  
P87,LED7  
M M OD  
6
TM 2IO,P12  
TM 3IO,P13  
TM 4IO,P14  
IRQ0,P20  
IRQ1,P21  
IRQ2,P22  
P60  
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
P61  
P62  
P63  
P64  
P65  
P66  
P67  
NRST, P27  
Figure 1-3-1 Pin Diagram (42-SDIP: TOP VIEW)  
Pins  
5
Chapter 1 Overview  
44 43 42 41 40 39 38 37 36 35 34  
1
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
LED3,P83  
P63  
P62  
2
3
LED2,P82  
LED1,P81  
LED0,P80  
AN0,PA0  
AN1,PA1  
AN2,PA2  
AN3,PA3  
AN4,PA4  
AN5,PA5  
AN6,PA6  
P61  
P60  
4
5
P22,IRQ2  
P21,IRQ1,SENS  
P20,IRQ0  
P14,TM 4IO  
P13,TM 3IO  
P12,TM 2IO  
P11  
M N101C117/115  
４４-ＱＦＰ  
6
7
8
9
10  
11  
12 13 14 15 16 17 18 19 20 21 22  
Figure 1-3-2 Pin Diagram (44-QFP: TOP VIEW)  
6
Pins  
Chapter 1 Overview  
48 47 46 45 44 43 42 41 40 39 38 37  
1
2
3
4
5
6
7
8
9
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
LED3,P83  
LED2,P82  
LED1,P81  
LED0,P80  
NC  
P63  
P62  
P61  
P60  
P23,IRQ3  
P22,IRQ2  
P21,IRQ1,SENS  
P20,IRQ0  
P14,TM 4IO  
P13,TM 3IO  
P12,TM 2IO  
P11  
AN0,PA0  
AN1,PA1  
AN2,PA2  
AN3,PA3  
AN4,PA4  
AN5,PA5  
AN6,PA6  
M N101C117/115  
４８-ＱＦＨ  
10  
11  
12  
13 14 15 16 17 18 19 20 21 22 23 24  
Figure 1-3-3 Pin Diagram (48-QFH: TOP VIEW)  
Pins  
7
Chapter 1 Overview  
1-3-2 Pin Function Summary  
*The pin numbers in the list correspond to the QFH package(Refer  
to Figure 1-3-3 Pin connection.) Be careful when using SDIP and  
QFP packages.  
Table 1-3-1 Pin Function Summary (1/4)  
Pin No.  
17  
Name  
Type  
Dual Function  
Function  
Description  
VSS  
–
Power supply pins Apply 2.0V to 5.5V to VDD and 0V to VSS.  
14  
VDD  
16  
15  
OSC1  
OSC2  
Input  
Clock input pin  
Clock output pin  
Connect these oscillation pins to ceramic or crystal oscillators for high-  
Output  
speed clock operation.  
If the clock is an external input, connect it to OSC1 and leave OSC2  
open. The chip will not operate with an external clock when using either  
the STOP or SLOW modes.  
18  
19  
XI  
Input  
Clock input pin  
Clock output pin  
Connect these oscillation pins to ceramic or crystal oscillators for low-  
speed clock operation.  
XO  
Output  
If the clock is an external input, connect it to XI and leave XO open.  
The chip will not operate with an external clock when using the STOP  
mode. If these pins are not used, connect XI to VSS and leave XO open.  
*42-SDIP and 44-QFP packages have no pins of this kind.  
43  
RST  
I/O  
P27  
Reset pin  
This pin resets the chip when power is turned on, is allocated as P27 and  
contains an internal pull-up resistor (Typ. 35 kΩ).  
Setting this pin low initializes, the internal state of the device  
is initialized. Thereafter, setting the input to an"H"level release the reset  
The hardware waits for the system clock to stabilize, and then  
processes the reset interrupt.  
Also, if "0" is written to P27 and the reset is initiated by software, a low  
level will be output. The output has an n-channel open-drain configuration.  
If a capacitor is to be inserted between RST and VDD, it is  
recommended that a discharge diode be placed between RST and VDD.  
20 to 23  
P00 to P02 I/O  
P06  
SBO0(TXD), I/O port 0  
SBI0(RXD),  
SBT0,  
4-bit CMOS tri-state I/O port.  
Each bit can be set individually as either an input or output by the  
P0DIR register. A pull-up resistor for each bit can be selected  
individually by the P0PLU register.  
DK  
(BUZZER)  
At reset, the input mode is selected and pull-up resistors are disabled  
(high impedance output).  
8
Pins  
Chapter 1 Overview  
Table 1-3-1 Pin Function Summary (2/4)  
Pin No.  
Name  
Type  
Dual Function  
Function  
I/O port 1  
Description  
24 to 28  
P10 to P14 I/O  
RMOUT,  
TM2IO to  
TM4IO  
5-bit CMOS tri-state I/O port.  
Each bit can be set individually as either an input or output by  
theP1DIR register. A pull-up resistor for each bit can be selected  
individually by the P1PLU register. At reset, the input mode is  
selected and pull-up resistors are disabled (high impedance output).  
4-bit input port. A pull-up resistor for each bit can be selected  
individually by the P2PLU register. At reset, the input mode is  
selected and pull-up resistors are disabled (high impedance output).  
P23 pin does not exist for 42-SDIP, 44-QFP packages.  
Port P27 has an n-channel open-drain configuration. When "0" is  
written and the reset is initiated by software, a low level will be  
output.  
29 to 32  
P20 to P23  
P27  
Input  
IRQ0,  
Input port 2  
IRQ1(SENS),  
IRQ2 to 3  
43  
Input  
RST  
Input port 2  
I/O port 6  
33 to 40  
P60 to P67 I/O  
8-bit CMOS tri-state I/O port.  
Each bit can be set individually as either an input or output by the P6DIR  
register. A pull-up resistor for each bit can be selected individually by the  
P6PLU register. At reset, the input mode is selected and pull-up resistors  
for P60 to P67 are disabled (high impedance output).  
41 to 42  
P70 to P71 I/O  
I/O port 7  
2-bit CMOS tri-state I/O port.  
Each individual bit can be switched to an input or output by the P7DIR  
register. A pull-up or pull-down resistor for each bit can be selected  
individually by the P7PLUD register.  
However, pull-up and pull-down resistors cannot be mixed.  
At reset, the input mode is selected and pull-up resistors are disabled (high  
impedance output).  
P70 and P71 pins do not exist for 42-SDIP package. P71 pin does not exist  
for 44-QFP package, either.  
8-bit CMOS tri-state I/O port.  
1 to 4  
P80 to P87 I/O  
LED0 to 7  
I/O port 8  
Each individual bit can be switched to an input or output by the P8DIR  
register. A pull-up resistor for each bit can be selected individually by  
the P8PLU register. When configured as outputs, these pins can drive  
LED segments, directly.  
45 to 48  
At reset, the input mode is selected and pull-up resistors for P80 to P87  
are disabled (high impedance output).  
6 to 13  
PA0 to PA7 Input  
AN0 to AN7  
Input port A  
8-bit input port.  
A pull-up or pull-down resistor for each bit can be selected  
individually by the PAPLUD register. However, pull-up and pull-  
down resistors cannot be mixed.  
At reset, the PA0 to PA7 input mode is selected and pull-up resistors  
are disabled.  
Pins  
9
Chapter 1 Overview  
Table 1-3-1 Pin Function Summary (3/4)  
Pin No.  
20  
Name  
Type  
Dual Function  
Function  
Description  
TXD  
RXD  
Output  
SBO0(P00)  
UART transmit  
data output pin  
UART receive  
data input pin  
In the serial interface in UART mode, these pins are configured as  
the receive data input pin and transmit data output pin.  
21  
Input  
SBI0(P01)  
A push-pull or n-channel open-drain configuration can be selected for  
TXD by the SC0MD1 register.  
Pull-up resistors can be selected by the P0PLU register. The TXD  
and RXD pins are also allocated as P00 and P01 respectively. When  
not used as serial/UART pins, these can be used as normal I/O pins.  
20  
SBO0  
Output  
TXD(P00)  
Serial interface  
transmit data  
output pin  
Transmit data output pin for serial interfaces 0. The output  
configuration, either CMOS push-pull or n-channel open-drain, and  
pull-up resistors can be selected by the software. Set these pins to the  
output mode by the P0DIR register.  
SBO0 is allocated as P00. This may be used as normal I/O pin when  
the serial interface is not used.  
Receive data input pin for serial interfaces 0. Pull-up resistor can be  
selected by the P0PLU register.  
Serial interface  
receive data input  
pin  
21  
22  
SBI0  
Input  
I/O  
RXD(P01)  
Set these pins to the input mode by the P0DIR register.  
SBI0 is allocated as P01. This can be used as normal I/O pin when the  
serial interface is not used.  
Clock I/O pin for serial interface 0. The output configuration, either  
CMOS push-pull or n-channel open-drain output, can be selected by  
the software. The direction of SBT0 is selected by the P0DIR register  
in accordance with the communication mode. Pull-up resistors can be  
selected by the P0PLU register. SBT0 is allocated as P02. This can be  
used as normal I/O pin when the serial interface is not used.  
SBT0  
P02  
Serial interface  
clock I/O pin  
22  
Buzzer  
I/O  
P06  
Buzzer output  
Piezoelectric buzzer driver pin. The driving frequency can be  
selected in the range of fs/2 to fs/2 by the DLYCTR register. Select  
output mode by the P0DIR register and select buzzer output by the  
DLYCTR register. When not used for buzzer output, this pin can be  
used as a normal I/O pin.  
24  
RMOUT  
I/O  
I/O  
P10  
Remote control transmit  
signal output pin  
Output pin for remote control transmit signal with a carrier signal.  
Can be used as a normal I/O pin when remote control is not used.  
26 to 28  
TM2IO to  
TM4IO  
P12 to P14  
Timer I/O pins  
Event counter clock input pins, overflow pulse output pins and PWM  
signal output pins for timer 2 to 4.  
To use these pins as event clock inputs, configure them as inputs by  
the P1DIR register. For overflow pulse and PWM output, configure  
these pins as outputs by the P1DIR register. When the pins are used as  
inputs, pull-up resistors can be specified by the P1PLU register. When  
not used for timer I/O, these can be used as normal I/O pins.  
Pins  
10  
Chapter 1 Overview  
Table 1-3-1 Pin Function Summary (4/4)  
Pin No.  
44  
Name  
Type  
Dual Function  
Function  
Description  
This pin sets the test mode.  
Test mode  
switch input pin Must be set to L.  
MMOD  
Input  
The valid edge for these external interrupt input pins can be selected  
with the IRQnICR registers.  
29 to 32  
IRQ0 to  
IRQ3  
Input  
P20,  
External interrupt  
P21(SENS), input pins  
P22,P23  
IRQ1 is an external interrupt pin that is able to determine AC zero  
crossings. It can also be used as a normal external interrupt.  
When IRQ0 to 3 are not used for interrupts, these can be used as normal  
I/O pins.  
Analog input pins for an 8-channel, 10-bit A/D converter.  
When not used for analog input, these pins can be used as normal I/O  
pins.  
6 to 13  
30  
AN0 to AN7 Input  
PA0 to PA7  
IRQ1(P21)  
Analog input pins  
SENS is an input pin for an AC zero-cross detection circuit. The AC zero-  
cross circuit outputs a high level when the input is at an intermediate level. It  
outputs a low level at all other times. SENS is connected to the P21 input  
circuit and the IRQ1 interrupt circuit. When the AC zero-cross detection  
circuit is not used, this pin can be used as a normal P21 input. The P21IM flag  
of the FLOAT1 register sets which input is selected.  
SENS  
Input  
AC zero-cross  
detection input pin  
11  
Pins  
Chapter 1 Overview  
1-4 Overview of Functions  
1-4-1 Block Diagram  
TXD,SBO0,P00  
RXD,SBI0,P01  
SBT0,P02  
P06  
RMOUT,P10  
P11  
TM2IO,P12  
TM3IO,P13  
TM4IO,P14  
IRQ0,P20  
SENS,IRQ1,P21  
IRQ2,P22  
IRQ3,P23  
RST,P27  
P60  
P61  
P62  
P63  
P64  
P65  
P66  
P67  
P70  
P71  
System  
clock  
oscillator  
CPU  
MN101C00  
Sub-clock  
oscillator  
ROM  
16 KB  
RAM  
512 bytes  
External interrupt  
Serial interface 0  
Time base timer 5  
8-bit timer 2  
8-bit timer 3  
16-bit timer 4  
AN7,PA7  
P80,LED0  
P81,LED1  
P82,LED2  
P83,LED3  
P84,LED4  
P85,LED6  
P86,LED6  
P87,LED7  
AN6,PA6  
AN5,PA5  
AN4,PA4  
AN3,PA3  
AN2,PA2  
AN1,PA1  
AN0,PA0  
A/D conversion  
Watchdog timer  
Figure 1-4-1 Block Diagram of Functions)  
12  
Overview of Function  
Chapter 1 Overview  
1-5 Electrical Characteristics  
Model  
MN101C117/115  
Contents  
Classification  
CMOS integrated circuit  
General purpose  
Use  
Function  
CMOS, 8-bit, single-chip microcomputer  
This LSI manual describes  
standard specifications.  
Before using the LSI, please  
obtain product specifications  
from the sales office.  
∗2 ∗3  
1-5-1 Absolute Maximum Ratings  
Parameter  
Symbol  
Rating  
–0.3 to +7.0  
Unit  
V
1
Supply voltage  
VDD  
2
Input clamp current (SENS) IC  
–500 to 500  
µA  
V
3
Input pin voltage  
Output pin voltage  
I/O pin voltage  
VI  
–0.3 to VDD+0.3  
4
VO  
VIO1  
–0.3 to VDD+0.3  
V
5
–0.3 to VDD+0.3  
V
30  
20  
P8  
6
I
I
I
I
OL1 (peak)  
OL2 (peak)  
OH (peak)  
OL1 (avg)  
Peak output  
current  
Except P8  
All pins  
P8  
7
–10  
8
mA  
20  
9
Average output  
current*1  
15  
10  
11  
12  
13  
14  
Other than P8 I OL2 (avg)  
All pins  
OH (avg)  
PD  
–5  
I
400  
Tolerable loss  
mW  
°C  
–40 to 85  
–55 to +125  
Ambient operating temperature Topr  
Storage temperature Tstg  
°C  
∗1  
Note: Applicable even for an interval of 100ms.  
*2  
Insert at least one bypass capacitor of 0.1  
and GND to prevent from latchup.  
µF or more between a power source pin  
*3  
Absolute maximum ratings indicate the allowable limit to which applied voltage  
does not damage a chip, not guarantee the operation.  
13  
Electrical Characteristics  
Chapter 1 Overview  
1-5-2 Operating Conditions  
Ta=–40 to +85°C VDD=2.0 to 5.5V VSS=0V  
Rating  
Parameter  
Symbol  
Conditions  
Unit  
MIN  
TYP  
MAX  
Supply voltage  
1
VDD1  
VDD2  
fosc ≤20.0MHz  
fosc ≤8.39MHz  
fosc ≤2.00MHz  
fx = 32.768kHz  
STOP mode  
4.5  
2.7  
2.0  
2.0  
1.8  
5.5  
5.5  
5.5  
5.5  
5.5  
2
3
4
5
Supply voltage  
during operation  
V
VDD3  
1
VDD4  
*
Voltage to maintain RAM data VDD5  
Operating speed ∗2  
6
tc1  
VDD=4.5 to 5.5V  
VDD=2.7 to 5.5V  
VDD=2.0 to 5.5V  
VDD=2.0 to 5.5V  
0.100  
0.238  
1.00  
40  
7
8
9
tc2  
µs  
Instruction execution time  
tc3  
tc4 *1  
125  
Fig. 1-5-1  
Crystal oscillator 1  
10 Crystal frequency  
fxtal 1  
VDD=4.5 to 5.5V  
1.0  
20.0 MHz  
11  
C11  
C12  
20  
20  
External capacitors  
12  
pF  
13 Internal feedback resistor RF10  
700  
kΩ  
Fig. 1-5-2*1  
Crystal oscillator 2  
14 Crystal frequency  
fxtal 2  
C21  
32.768  
20  
kHz  
pF  
15  
External capacitors  
16  
C22  
20  
17 Internal feedback resistor RF20  
4.0  
MΩ  
Note:  
*1. Only for 48-QFH package  
∗2  
t , t c2, t c3: OSC1 is the CPU clock  
c1  
t c4: XI is the CPU clock  
OSC1  
fxtal1  
XI  
700kΩ  
Typ  
4.0MΩ  
Typ  
fxtal2  
MN101C  
MN101C  
OSC2  
XO  
C12  
C11  
C22  
C21  
The instruction cycle is four times the clock cycle.  
The feedback resistor is built-in.  
The instruction cycle is twice the clock cycle.  
The feedback resistor is built-in.  
Figure 1-5-2 Crystal Oscillator 2 *1  
Figure 1-5-1 Crystal Oscillator 1  
14  
Electrical Characteristics  
Chapter 1 Overview  
Rating  
TYP  
Parameter  
Symbol  
Conditions  
Unit  
MIN  
MAX  
External clock input 1 OSC1 (OSC2 is unconnected)  
18 Clock frequency  
fOSC  
1.0  
20.0 MHz  
19 High level pulse width∗ twh 1  
20 Low level pulse width∗ twl 1  
20.0  
20.0  
30.0  
ns  
30.0  
∗1  
Fig. 1-5-3  
Fig. 1-5-3  
21 Rise time  
22 Fall time  
twr 1  
twf 1  
5.0  
ns  
5.0  
External clock input 2 XI (XO is unconnected)*2  
23 Clock frequency  
fx  
32.768  
3.5  
100 kHz  
µs  
24 High level pulse width∗ twh 2  
25 Low level pulse width∗ twl 2  
∗1  
Fig. 1-5-4  
Fig. 1-5-4  
3.5  
26 Rise time  
27 Fall time  
∗1  
twr 2  
twf 2  
20  
ns  
20  
Set the clock duty ratio to 45 to 55%.  
*2 Applicable only for 48-pin QFH package  
15  
Electrical Characteristics  
Chapter 1 Overview  
0.9VDD  
0.1VDD  
twh1  
twl1  
twr1  
twf1  
Figure 1-5-3 OSC1 Timing Chart  
0.9VDD  
0.1VDD  
twh2  
twr2  
twl2  
twf2  
Figure 1-5-4 XI Timing Chart  
16  
Electrical Characteristics  
Chapter 1 Overview  
1-5-3 DC Characteristics  
Ta=–40 to +85°C VDD=2.0 to 5.5V VSS=0V  
Rating  
TYP  
Unit  
Parameter  
Symbol  
Conditions  
MIN  
MAX  
Supply current (no load at output)∗1  
fosc=20.0MHz,VDD=5V  
1
Supply current  
IDD1  
25  
10  
60  
25  
100  
8
mA  
2
3
during operation  
IDD2  
fosc=8.39MHz,VDD=5V  
fx =32.768kHz,VDD=3V  
*2  
*2  
IDD3  
4
IDD5  
fx =32.768kHz,VDD=3V  
Ta=25  
Supply current during HALT mode  
*2  
5
6
7
IDD6  
IDD7  
IDD8  
Ta=-40 to 85˚C  
µA  
18  
2
VDD=5V, Ta=25˚C  
VDD=5V, Ta=-40 to 85˚C  
0
0
Supply current during STOP mode  
20  
∗1  
Notes:  
Measured under conditions of Ta=25°C and no load.  
The supply current during operation, IDD1 (IDD2), is measured under the  
following conditions: After all I/O pins are set to input mode and the oscillation  
is set to <NORMAL mode>, the MMOD pin is fixed at VSS, the input pins are  
fixed at VDD, and a 20MHz (8.39MHz) square wave of amplitude VDD,VSS is input  
to the OSC1 pin.  
The supply current during operation, IDD3, is measured under the following  
conditions: After all I/O pins are set to input mode and the oscillation is set to  
<SLOW mode>, the MMOD pin is fixed at VSS, the input pins are fixed at VDD,  
and a 32.768kHz square wave of amplitude VDD,VSS is input to the XI pin.  
The supply current during HALT mode, IDD5(IDD6), is measured under the  
following conditions: After all I/O pins are set to input mode and the oscillation  
is set to <HALT mode>, the MMOD pin is fixed at VSS, the input pins are fixed  
at VDD, and an 32.768kHz square wave of amplitude VDD,VSS is input to the XI  
pin.  
The supply current during STOP mode IDD7(IDD8) is measured under the following  
conditions: After the oscillation mode is set to <STOP mode>, the MMOD pin is  
fixed at VSS, the input pins are fixed at VDD, and the OSC1 and XI pins are  
unconnected.  
*2  
The items IDD5(IDD6) and IDD7(IDD8) are applicable only for 48-pin QFH package.  
17  
Electrical Characteristics  
Chapter 1 Overview  
Ta=–40 to +85°C VDD=2.0 to 5.5V VSS=0V  
Rating  
Parameter  
Symbol  
Conditions  
Unit  
MIN  
TYP  
MAX  
Input pin 1 MMOD  
8
Input high voltage 1  
Input high voltage 2  
VIH1  
0.8VDD  
VDD  
VDD  
V
V
9
VIH2  
VIL1  
VIL2  
ILK1  
VDD=4.5 to 5.5V  
0.7VDD  
10 Input low voltage 1  
11 Input low voltage 2  
12 Input leakage current  
0
0
0.2VDD  
0.3VDD  
±10  
V
VDD=4.5 to 5.5V  
VIN = 0 to VDD  
V
µA  
Input pin 2 P20, P22~P23 (Schmitt trigger input)  
13 Input high voltage  
14 Input low voltage  
15 Input leakage current  
16 Input high current  
VIH3  
VIL3  
ILK3  
IIH3  
0.8VDD  
0
VDD  
0.2VDD  
±10  
V
V
VIN=0 to VDD  
µA  
VDD=5V, VIN=1.5V  
Pull-up resistor ON  
–30  
–100  
–300 µA  
Input pin 3—1 P21 (Schmitt trigger input)  
17 Input high voltage  
18 Input low voltage  
19 Input leakage current  
20 Input high current  
VIH4  
VIL4  
ILK4  
IIH4  
0.8VDD  
0
VDD  
0.2VDD  
±10  
V
V
VIN=0 to VDD  
µA  
VDD=5V, VIN=1.5V  
Pull-up resistor ON  
–30  
–100  
–300 µA  
Input pin 3—2 P21 (when used as SENS)  
21 Input high voltage 1  
22 Input low voltage 1  
23 Input high voltage 2  
24 Input low voltage 2  
25 Input leakage current  
26 Input clamp current  
VDHH  
VDLH  
VDHL  
VDLL  
ILK10  
IC10  
VDD=5.0V  
4.5  
VSS  
1.5  
VSS  
VDD  
V
3.5  
Fig. 1-5-5  
VDD  
V
0.5  
VIN=0V to VDD  
±10  
µA  
±400  
VDD=5.0V  
VIN>VDD, VIN<0V  
18  
Electrical Characteristics  
Chapter 1 Overview  
SENS pin  
27  
28  
Rise time  
Fall time  
trs  
tfs  
30  
30  
Fig. 1-5-5  
µs  
← trs→  
← tfs →  
VDD  
Input voltage level 1→  
VDHH  
VDLH  
(Input)  
VDHL  
VDLL  
VSS  
Input voltage level 2→  
(Output)  
Figure 1-5-5 Operation of AC Zero-Cross Detection Circuit  
Ta=–40 to +85°C VDD=2.0 to 5.5V VSS=0V  
Rating  
Parameter  
Symbol  
Conditions  
Unit  
MIN  
TYP  
MAX  
Input pin 4 PA0~PA7  
29 Input high voltage 1  
30 Input high voltage 2  
31 Input low voltage 1  
32 Input low voltage 2  
33 Input leakage current  
34 Input high current  
35 Input low current  
VIH5  
0.8VDD  
VDD  
VDD  
V
V
VIH6  
VIL5  
VIL6  
ILK5  
IIH5  
VDD=4.5 to 5.5V  
0.7VDD  
0
0
0.2VDD  
0.3VDD  
±2  
V
VDD=4.5 to 5.5V  
VIN=0 to VDD  
V
µA  
VDD=5V, VIN=1.5V  
Pull-up resistor ON  
–30  
80  
–100  
180  
–300 µA  
400 µA  
VDD=5V, VIN=3.5V  
Pull-down resistor ON  
IIL5  
19  
Electrical Characteristics  
Chapter 1 Overview  
Ta=–40 to +85°C VDD=2.0 to 5.5V VSS=0V  
Rating  
Parameter  
Symbol  
Conditions  
Unit  
MIN  
TYP  
-100  
–100  
MAX  
I/O pin 5 P27 (RST)  
36 Input high voltage  
37 Input low voltage  
38 Input leakage current  
39 Input high current  
VIH7  
0.9VDD  
0
VDD  
0.2VDD  
±10  
V
V
VIL7  
ILK7  
Iih  
VIN = 0 to VDD  
VDD=5V, VIN=1.5V  
µA  
-30  
-300 µA  
Pull-up resistor built in  
I/O pin 6 P00 to P06, P10 to P14 (Schmitt trigger input)  
40 Input high voltage  
41 Input low voltage  
42 Input leakage current  
43 Input high current  
44 Output high voltage  
45 Output low voltage  
I/O pin 7 , P60 to P67  
46 Input high voltage 1  
47 Input high voltage 2  
48 Input low voltage 1  
49 Input low voltage 2  
50 Input leakage current  
51 Input high current  
52 Output high voltage  
53 Output low voltage  
I/O pin 8 P70 to P71  
54 Input high voltage 1  
55 Input high voltage 2  
56 Input low voltage 1  
57 Input low voltage 2  
58 Input leakage current  
59 Input high current  
60 Input low current  
VIH8  
VIL8  
ILK8  
0.8VDD  
0
VDD  
0.2VDD  
±10  
V
V
VIN=0 to VDD  
µA  
VDD=5V, VIN=1.5V  
Pull-up resistor ON  
IIH8  
–30  
4.5  
–300 µA  
V
VOH8  
VOL8  
VDD = 5V, IOH = –0.5mA  
VDD = 5V, IOL = 1.0mA  
0.5  
V
VIH9  
VIH10  
VIL9  
VIL10  
ILK9  
0.8VDD  
VDD  
VDD  
V
V
VDD=4.5 to 5.5V  
0.7VDD  
0
0
0.2VDD  
0.3VDD  
±10  
V
VDD=4.5 to 5.5V  
VIN=0 to VDD  
V
µA  
VDD=5V, VIN=1.5V  
Pull-up resistor ON  
IIH9  
–30  
4.5  
–100  
–300 µA  
V
VOH9  
VOL9  
VDD = 5V, IOH = -0.5mA  
VDD = 5V, IOL = 1.0mA  
0.5  
V
VIH11  
VIH12  
VIL11  
VIL12  
ILK11  
IIH11  
0.8VDD  
VDD  
VDD  
V
V
VDD=4.5 to 5.5V  
0.7VDD  
0
0
0.2VDD  
0.3VDD  
±10  
V
VDD=4.5 to 5.5V  
VIN = 0 to VDD  
V
µA  
VDD=5V, VIN=1.5V  
Pull-up resistor ON  
–30  
30  
–100  
100  
–300 µA  
VDD=5V, VIN=3.5V  
Pull-down resistor ON  
IIL11  
300  
µA  
V
61 Output high voltage  
62 Output low voltage  
VOH11  
VOL11  
VDD = 5V, IOH = –0.5mA  
VDD = 5V, IOL = 1.0mA  
4.5  
0.5  
V
20  
Electrical Characteristics  
Chapter 1 Overview  
Ta=–40 to +85°C VDD=2.0 to 5.5V VSS=0V  
Rating  
Parameter  
Symbol  
Conditions  
Unit  
MIN  
TYP  
MAX  
I/O pin 9 P80~P87  
63 Input high voltage 1  
64 Input high voltage 2  
65 Input low voltage 1  
66 Input low voltage 2  
67 Input leakage current  
68 Input high current  
69 Output high voltage  
70 Output low voltage  
VIH13  
VIH14  
VIL113  
VIL14  
ILK13  
0.8VDD  
VDD  
VDD  
V
V
VDD=4.5 to 5.5V  
0.7VDD  
0
0
0.2VDD  
0.3VDD  
±10  
V
VDD=4.5 to 5.5V  
VIN=0 to VDD  
V
µA  
VDD=5V, VIN=1.5V  
Pull-up resistor ON  
IIH13  
–30  
4.5  
–100  
–300 µA  
V
VOH13  
VOL13  
VDD = 5V, IOH = –0.5mA  
VDD = 5V, IOL = 15mA  
1.0  
V
1-5-4 A/D Converter Characteristics  
Ta=–40 to+85°C VDD=2.0 to 5.5V VSS=0V  
Rating  
Parameter  
Resolution  
Symbol  
Conditions  
Unit  
MIN  
TYP  
MAX  
1
2
3
4
5
6
10  
Bits  
VDD = 5.0V, VSS = 0V  
VREF+=5.0V, VREF–=0V  
TAD = 800ns  
Nonlinear error 1  
±3 LSB  
±3 LSB  
±5 LSB  
±5 LSB  
100 mV  
Differential linear error 1  
Nonlinear error 2  
VDD = 5.0V, VSS = 0V  
VREF–=5.0V, VREF–=0V  
fx = 32.768kHz  
Differential linear error 2  
Zero traction voltage  
30  
30  
VDD = 5.0V, VSS = 0V  
VREF+=5.0V, VREF–=0V  
TAD = 800ns  
7
Full-scale transition voltage  
100 mV  
µs  
8
TAD = 800ns  
9.6  
1.0  
A/D conversion time  
Sampling time  
9
fx = 32.768kHz  
183  
36  
µs  
µs  
10  
11  
fOSC = 8MHz  
fx = 32.768kHz  
30.5  
µs  
12 Analog input leakage current  
When VDAIN = 0 to 5V is off  
±2  
µA  
21  
Electrical Characteristics  
Chapter 1 Overview  
1-6 Option  
1-6-1 ROM Option  
The product equipped with this LSI or an EPROM with this LSI controls the oscillation  
mode after resetting as well as the runaway-detection watchdog timer, using bits 2 to  
0 of the last address of the built-in ROM.  
■ Option bits  
7
6
5
4
3
2
1
0
PKG  
SEL2  
PKG  
SEL1  
－
－
－
WDSEL2 WDSEL1 NSSTRT  
Selection of oscillation mode  
after resetting  
NSSTRT  
SLOW mode  
0
1
NORMAL mode  
WDSEL2  
Watchdog timer cycle setting  
fs/216  
WDSEL1  
0
1
0
1
fs/218  
fs/220  
Ｘ
Packages  
PKGSEL2 PKGSEL1  
Ｘ
0
SDIP042-P-0600  
QFP044-P-1010  
QFH048-P-0707  
0
1
1
Figure 1-6 ROM Option ( Address:X'7FFF' )  
22  
Option  
Chapter 1 Overview  
1-6-2 Option Form  
Date:  
SE No.  
Model  
MN101C  
Name  
Approval  
Customer  
1. Oscillation mode  
Type B  
Type A  
Note: Type A: Operation begins from the reset cycle in the NORMAL mode.  
Type B: Operation begins from the reset cycle in the SLOW mode.  
2. Watchdog timer period setting  
3. Package selection  
Selection  
Detection Period  
fs/216  
Selection  
Package  
SDIP042-P-0600  
fs/218  
fs/220  
QFP044-P-1010  
QFH048-P-0707  
Not used  
Contents of mask option are subject to change.  
When placing an order for masks, please request the most recent option  
list from the sales office.  
Option of this product is used a part of the built-in ROM.  
When placing an order for programme, please sed data on the address  
of the option.  
Chapter 1 Overview 23  
Chapter 1 Overview  
1-7 Outline Drawings  
Package code: SDIP042-P-0600  
Unit: mm  
Body Material: Epoxy Resin Lead Material:Fe Ni Lead Finish Method:Soldering dip  
Figure 1-7-1 42-SDIP  
The external dimensions of the package are subject to change. Before  
using this product, please obtain product specifications from the sales  
office.  
24  
External Dimensions  
Chapter 1 Overview  
Package code: QFP044-P-1010  
Unit: mm  
Body Material: Epoxy Resin Lead Material:Fe Ni Lead Finish Method:Soldering dip  
Figure 1-7-2 44-QFP  
The external dimensions of the package are subject to change. Before  
using this product, please obtain product specifications from the sales  
office.  
External Dimensions)  
25  
Chapter 1 Overview  
Package code: QFH048-P-0707  
Unit: mm  
Material: Epoxy Resin Lead Material:Fe Ni-42 Alloy  
Lead Finish Method:Soldering dip  
Figure 1-7-3 48-QFH  
The external dimensions of the package are subject to change. Before  
using this product, please obtain product specifications from the sales  
office.  
External Dimensions  
26  
Chapter 2  
Basic CPU Functions  
2
27  
Chapter 2 Basic CPU Functions  
2-1 Overview  
Basic CPU functions are in conformance with the MN101C00 series manual  
(architecture manual). This chapter describes specifications unique to the  
MN101C117/115.  
2-2 Address Space  
2-2-1 Memory Configuration  
X'00000'  
Abs 8 addressing  
256 bytes  
access area  
∗
Internal  
512 bytes  
RAM space  
X'00100'  
Data  
X'00200'  
X'03F00'  
X'04000'  
Special function registers  
256 bytes  
Interrupt  
vector table  
128 bytes  
64 bytes  
X'04080'  
X'040C0'  
Subroutine  
vector table  
∗
Internal  
ROM space  
16 KB  
Instruction code/  
table data  
X'07FFF'  
Figure 2-2-1 Memory Map  
∗ Differs depending upon the model.  
MN101C115  
Internal RAM  
X'00000' to X'000FF'  
X'04000' to X'05FFF'  
X'00000' to X'001FF'  
X'04000' to X'01FFF'  
256 bytes  
Internal ROM  
8 KB  
MN101CP117 Internal RAM  
EP ROM  
512 bytes  
16 KB  
28  
Overview/Address Space  
Chapter 2 Basic CPU Functions  
2-2-2 Special Function Registers  
Memory control register(MEMCTR) is a 4-bit register which set up the base  
Table 2-2-1 Register Map  
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
CPUM MEMCTR WDCTR DLYCTR  
P0OUT P1OUT P2OUT  
P0IN P1IN P2IN  
P0DIR P1DIR  
CPU mode, memory control  
Port output  
03F0X  
03F1X  
03F2X  
03F3X  
03F4X  
03F5X  
03F6X  
03F7X  
03F8X  
03F9X  
03FAX  
03FBX  
03FCX  
03FDX  
03FEX  
03FFX  
P6OUT P7OUT P8OUT  
Port input  
P6IN P7IN P8IN  
PAIN  
I/O mode control  
Resistor control  
P6DIR P7DIR P8DIR P1OMD PAIMD  
FLOAT1  
PAPLUD  
P0PLU P1PLU P2PLU  
P6PLU P7PLUD P8PLU  
SC0MD2  
SC0MD0 SC0MD1  
SC0MD3 SC0CTR SC0TRB SC0RXB  
Serial interface control  
TM2BC TM3BC TM4BCL TM4BCH TM4ICL TM4ICH TM5BC  
Timer control  
TM2OC TM3OC TM4OCL TM4OCH  
TM2MD TM3MD TM4MD  
TM5OC  
TM5MD RMCTR NFCTR  
ANCTR0 ANCTR1 ANBUF0 ANBUF1  
A/D control  
Reserved  
NMICR IRQ0ICR IRQ1ICR  
TM5ICR  
TM2ICR TBICR SC0ICR  
ADICR IRQ2ICR  
TM3ICR TM4ICR  
Interrupt control  
Address Space  
29  
Chapter 2 Basic CPU Functions  
2-3 Bus Interface  
2-3-1 Overview  
The MN101C117, unlike other MN101C series microcomputers, does not  
support memory expansion mode and processor mode.  
2-3-2 Control Registers  
The memory control register is a four-bit register that sets up wait-count at a  
time of access to a base address of interrupt vector table and a special  
register zone.  
(1) Memory control register(MEMCTR)  
7
6
5
4
3
2
1
0
(at reset: 11001011)  
IVBA  
IOW1 IOW0  
IRWE  
MEMCTR  
Must be set to 11.  
IRWE  
Set software write for interrupt request flag  
Software write disable  
Even if data is written to each interrupt control  
register (xxxICR), the state of the interrupt  
request flag (xxxIR) will not change.  
0
1
Software write enable  
Must be set to 1.  
Must be set to 0  
Base address setting for interrupt vector table  
IVBA  
0
1
Interrupt vector base = X'04000'  
Interrupt vector base = X'00100'  
Bus cycle at  
20MHz oscillation  
Number of wait cycles set when  
accessing special register area  
IOW1 to 0  
No wait cycles  
1 wait cycle  
100ns  
150ns  
200ns  
250ns  
00  
01  
10  
11  
2 wait cycles  
3 wait cycles  
Figure 2-3-1 Memory Control Register MEMCTR:X'03F01'R/W  
30  
Bus Interface  
Chapter 2 Basic CPU Functions  
2-4 Interrupts  
2-4-1 Accepting and Returning from Interrupts  
In the MN101C00 series, when an interrupt is accepted, the hardware  
pushes the program's return address and the PSW, on to the stack, and  
branches to the beginning address of the interrupt program specified by the  
interrupt vector table.  
■ Operation when Interrupt is Accepted  
1. The stack pointer (SP) contents are update. (SP–6 → SP)  
2. The handy address register (HA) is pushed on to the stack.  
HA upper byte → (SP+5)  
HA lower byte → (SP+4)  
3. The program counter (PC = return address) contents are pushed on to the stack.  
PC (bit 18 to bit 17, bit 0) → (SP+3)  
PC (bit 16 to bit 9) → (SP+2)  
PC (bit 8 to bit 1) → (SP+1)  
4. The PSW is pushed on to the stack.  
PSW → (SP)  
5. xxxLVn of the accepted interrupt is copied to IM of the PSW.  
Interrupt level → IM  
6. Execution branches to vector table.  
7
0
Low  
New SP  
PSW  
(after interrupt is accepted)  
PC8 to 1  
PC16 to 9  
Address  
PC18,17  
PC0  
HA7 to 0  
High  
HA15 to 8  
Old SP  
(before interrupt is accepted)  
Figure 2-4-1 Stack Status during an Interrupt  
Since the contents of data and address registers are not saved, use PUSH  
instructions in the program to save these values as necessary on the  
stack.  
Interrupts  
31  
Chapter 2 Basic CPU Functions  
■ Operation when Returning from Interrupt  
After the program POPs the register and other values saved by the interrupt service  
routine, an RTI instruction is implemented to return to the program that was being  
executed when the interrupt was received.  
The processing sequence for the return from interrupt instruction, RTI, is listed  
below.  
1. The processor status word (PSW) is pulled from the stack. (SP)  
2. The program counter(PC = return address) is pulled from the stack. (SP+1 to 3)  
3. The handy address register (HA) is pulled from the stack. (SP+4, 5)  
4. The SP is pulled. (SP+6 → SP)  
5. Execution branches to the address indicated by the PC.  
Interrupts  
32  
Chapter 2 Basic CPU Functions  
2-4-2 Interrupt Sources and Vector Addresses  
In addition to reset, there are 20 interrupt vectors that indicate the starting  
addresses of interrupt programs. These vectors are located in the 80-byte  
ROM address area X'04004' to X'04053'.  
Table 2-4-1 Interrupt Control Registers  
Control Register  
Interrupt Source  
Vector Number  
Vector Address  
X'04000'  
X'04004'  
X'04008'  
X'0400C'  
X'04010'  
X'04014'  
X'04018'  
X'0401C'  
X'04020'  
X'04024'  
X'04028'  
X'0402C'  
X'04030'  
X'04034'  
X'04038'  
X'0403C'  
X'04040'  
X'04044'  
X'04048'  
X'0404C'  
X'04050'  
(address)  
Reset  
0
1
(X'03FE1')  
NMICR  
Non-maskable interrupt (NMI)  
External interrupt 0 (IRQ0)  
(X'03FE2')  
(X'03FE3')  
(X'03FE4')  
(X'03FE5')  
(X'03FE6')  
(X'03FE7')  
(X'03FE8')  
(X'03FE9')  
(X'03FEA')  
(X'03FEB')  
(X'03FEC')  
(X'03FED')  
(X'03FEE')  
(X'03FEF')  
(X'03FF0')  
(X'03FF1')  
(X'03FF2')  
(X'03FF3')  
(X'03FF4')  
IRQ0ICR  
IRQ1ICR  
2
3
External interrupt 1 (IRQ1)  
Reserved  
4
Reserved  
5
TM2ICR  
TBICR  
6
Timer 2 compare-match (TM2IRQ)  
Time base period (TBIRQ)  
SC0 transfer complete (SC0IRQ)  
Reserved  
7
SC0ICR  
8
9
ADICR  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
A/D conversion complete (ADIRQ)  
External interrupt 2 (IRQ2)  
External interrupt 3 (IRQ3)*  
Reserved  
IRQ2ICR  
IRQ3ICR  
*IRQ31CR cannot be used  
except for 48-pin QFH  
package.  
TM3ICR  
TM4ICR  
TM5ICR  
Timer 3 compare-match (TM3IRQ)  
Timer 4 compare-match (TM4IRQ)  
Timer 5 compare-match (TM5IRQ)  
Reserved  
Reserved  
Reserved  
Reserved  
Set the vector addresses for reserved and unused interrupts to  
an address containing an RTI instruction.  
Interrupts  
33  
Chapter 2 Basic CPU Functions  
2-4-3 Interrupt Control Registers  
Interrupt control registers consist of the following: a non-maskable interrupt control  
register (NMICR), external interrupt control registers (IRQnICR), and internal  
interrupt control registers (TMnICR, TBICR, SCnICR, ATCICR, ADICR).  
Be sure to use the MIE flag of  
the PSW register to write to all  
interrupt control registers.  
■ Non-maskable Interrupt Control Register (NMICR)  
Non-maskable interrupt factors are stored in the non-maskable interrupt control  
register (NMICR), and are used when a non-maskable interrupt is generated.  
7
6
5
4
3
2
1
0
(at reset: ------0-)  
WDIR  
NMICR  
Watchdog interrupt request flag  
WDIR  
0
1
No interrupt request  
Happens interrupt request  
Figure 2-4-2 Non-maskable Interrupt Control Register (NMICR: X'03FE1', R/W)  
■ External Interrupt Control Registers (IRQnICR)  
The external interrupt control registers (IRQnICR) control the interrupt level, valid  
edge, and request/enable.  
7
6
5
4
3
2
1
0
By setting xxxLVn to '11' (level  
3), the corresponding interrupt  
vector will be disabled,  
regardless of the state of the  
interrupt enable and interrupt  
request flags.  
(at reset: 000---00)  
xxxLV1xxxLV0 REDGn  
—
—
—
xxxIE xxxIR  
IRQnICR  
External interrupt request flag  
xxxIR  
0
1
No interrupt request  
Happens interrupt request  
External interrupt enable flag  
xxxIE  
0
1
Disable interrupt  
Enable interrupt  
REDGn∗  
External interrupt valid edge flag  
0
1
Falling edge  
Rising edge  
Interrupt level flag for external interrupt  
xxxLV1 xxxLV0  
The CPU has interrupt levels from 0 to 3.  
This flag sets the interrupt level for interrupt requests.  
∗ n=0,1,2,3,4  
Figure 2-4-3 External Interrupt Control Register  
(IRQnICR: X'03FE2' to X'03FE3', X'03FEB' to X'03FED', R/W)  
34  
Interrupts  
Chapter 2 Basic CPU Functions  
■Internal Interrupt Control Registers (TMnICR, TBICR, SCOICR, ATCICR, ADICR)  
The internal interrupt control registers (TMnICR, TBICR, SCnICR, ATCICR,  
ADICR) control the interrupt levels of internal interrupts, timer interrupts, serial  
interrupts, A/D conversion complete interrupts, and interrupt request/enable.  
Be sure to disable all interrupts before writing to these registors.  
By setting xxxLVn to '11' (level  
3), the corresponding interrupt  
vector will be disabled,  
regardless of the state of the  
interrupt enable and interrupt  
request flags.  
7
6
5
–
4
–
3
–
2
–
1
0
TMnICR, TBICR, SCnICR,  
ATCICR, ADICR  
(at reset: 00----00)  
xxxLV1xxxLV0  
xxxIE xxxIR  
Interrupt request flag  
xxxIR  
0
1
No interrupt request  
Happens interrupt request  
Interrupt enable flag  
xxxIE  
0
1
Disable interrupt  
Enable interrupt  
Interrupt level flag  
xxxLV1 xxxLV0  
This 2-bit flag sets the interrupt level by  
assigning an interrupt level of 0 to 3 to  
interrupt requests.  
Figure 2-4-4 Internal Interrupt Control Registers (TMnICR, TBICR,  
SC0ICR,ADICR: X'03FE6' to X'03FEA', X'03FEA' to X'03FF0', R/W)  
Interrupts  
35  
Chapter 2 Basic CPU Functions  
2-5 Reset  
The CPU contents are reset and registers are initialized when the RST pin is  
pulled to low.  
■ Initiating a Reset  
There are two methods to initiate a reset.  
(1) Drive the RST pin low for at least four clock cycles.  
For the reset to be stable, the  
low pulse must be maintained  
for at least four clock cycles.  
However, it is important to  
minimize noise, since a reset  
may occur in a smaller number  
of clock cycles.  
RST pin  
4 clock cycles  
(200ns for a 20MHz oscillation)  
Figure 2-5-1 Minimum Reset Pulse Width  
(2) Set bit 7 (P2OUT7 flags) of the P2OUT register to "0." After reset is released,  
the P2OUT flag will be "1."  
■ Releasing the Reset  
When the RST pin changes from low to high, an internal 15-bit counter begins  
counting at the oscillation clock frequency. The interval from when this counter  
begins counting until it overflows is known as the stabilization wait time. After  
waiting for this amount of time, the internal reset is released and the CPU begins  
operation.  
RST pin  
Peripheral  
register  
CPU  
internal reset  
Oscillation  
stabilization wait time  
215/fosc  
Figure 2-5-2 Reset Release Sequence  
When returning from the STOP mode is terminating, the  
software can use the DLYCTR register to select an  
7
11  
oscillation stabilization wait time of 0, 2 /fosc, 2 /fosc, or  
15  
2 /fosc.  
36  
Reset  
Chapter 3  
Port Functions  
3
37  
Chapter 3 Port Functions  
3-1 Overview  
A total of 39 pins on the MN101C117, including those shared with special  
function pins, are allocated for the 7 ports of P0 to P2, P6 to P8, and PA.  
Each I/O port is assigned according to the special function register area in  
memory. I/O ports are operated in byte or bit units in the same way as RAM.  
For each I/O port, the PnOUT register (port n output  
register) that sets the output value is assigned to memory  
address X'3F1n', and the PnIN register (port n input  
register) from which the input value is monitored is  
assigned to memory address X'3F2n'.  
• This I/O control is valid even when special functions are selected for the dual function pins.  
•Table 3-1-1 Status When Port Is Reset (single-chip mode)  
Port  
I/O Port or Special Function  
I/O port  
I/O Mode  
Input mode  
Input mode  
Pull-up/Pull-down Resistor  
No pull-up resistor  
Port 0  
Port 1  
No pull-up resistor  
I/O port  
No pull-up resistor  
No pull-up resistor  
I/O port  
I/O port  
Port 2  
Port 6  
Input mode  
Input mode  
Port 7  
Port 8  
Port A  
No pull-up/pull-down resistors  
No pull-up/pull-down resistors  
No pull-up/pull-down resistors  
Input mode  
Input mode  
I/O port  
I/O port  
I/O port  
Input mode  
■ Port 0 (P0)  
4-bit CMOS tri-state I/O port.  
Table 3-1-2 Port 0 Functions  
Pin Name Type  
P00 to P02 I/O  
P06  
Dual Function  
Description  
SBO0(TXD),  
SBI0(RXD),  
SBT0  
Each bit can be set individually as either an input or  
output by the P0DIR register. A pull-up resistor for each  
bit can be selected individually by the P0PLU register.  
At reset, the input mode is selected and pull-up resistors  
are disabled (high impedance output).  
BUZZER  
38  
Overview  
Chapter 3 Port Functions  
■ Port 1 (P1)  
5-bit CMOS tri-state I/O port.  
Table 3-1-3 Port 1 Functions  
Pin Name Type  
Dual Function  
Description  
P10 to P14 I/O  
RMOUT,  
Each bit can be set individually as either an input or  
output by the P1DIR register. A pull-up resistor for each  
bit can be selected individually by the P1PLU register.  
At reset, the input mode is selected and pull-up resistors  
are disabled (high impedance output).  
TM2IO to TM4IO  
■ Port 2 (P2)  
4-bit CMOS tri-state input port.  
Table 3-1-4 Port 2 Functions  
Pin Name Type  
Dual Function  
Description  
A pull-up resistor for each bit can be selected individually  
by the P2PLU register. At reset, the input mode pull-up  
resisters are disabled (high impedance output).  
Only 48-QFH has P23.  
P20 to P23 Input  
IRQ0,  
IRQ1(SENS),  
IRQ2 to 3  
■ Port 6 (P6)  
8-bit CMOS tri-state I/O port.  
Table 3-1-5 Port 6 Functions  
Pin Name Type  
Dual Function  
Description  
P60 to P67 I/O  
Each bit can be set individually as either an input or  
output by the P6DIR register. A pull-up resistor for each  
bit can be selected individually by the P6PLU register. At  
reset, the input mode pull-up resisters are disabled (high  
impedance output).  
Overview  
39  
Chapter 3 Port Functions  
■ Port 7 (P7)  
8-bit CMOS tri-state I/O port.  
Table 3-1-6 Port 7 Functions  
Pin Name Type  
Dual Function  
Description  
P70 to P71 I/O  
Each individual bit can be switched to an input or output  
by the P7DIR register. A pull-up or pull-down resistor for  
each bit can be selected individually by the P7PLU  
register.  
However, pull-up and pull-down resistors cannot be  
mixed. At reset, the input mode pull-up resisters are  
disabled  
. 42-SDIP has no pins of P70,P71. 44-QFP has no pin of  
p71.  
■ Port 8 (P8)  
8-bit CMOS tri-state I/O port.  
Table 3-1-7 Port 8 Functions  
Pin Name Type  
Dual Function  
Description  
Each individual bit can be switched to an input or output  
by the P8DIR register. A pull-up resistor for each bit can  
be selected individually by the P8PLU register. When  
configured as outputs, it is possible to LED.  
P80 to P87 I/O  
LED0 to 7  
At reset, when single chip mode is selected, the input  
mode pull-up resisters for P80 to P87 are disabled (high  
impedance output).  
■ Port A (PA)  
8-bit CMOS tri-state input port.  
Table 3-1-8 Port A Functions  
Pin Name Type  
Dual Function  
Description  
PA0 to PA7 Input  
AN0 to AN7  
A pull-up or pull-down resistor for each bit can be  
selected individually by the PAPLUD register. However,  
pull-up and pull-down resistors cannot be mixed.  
At reset, the input mode pull-up resisters for PA0 to PA7  
are disabled.  
40  
Overview  
Chapter 3 Port Functions  
3-2 Port Control Registers  
3-2-1 Overview  
28 registers control the I/O ports. See table 3-2-1.  
Table 3-2-1 I/O Port Control Registers (1/2)  
Name  
Address  
X'03F10'  
X'03F11'  
X'03F12'  
X'03F16'  
X'03F17'  
X'03F18'  
X'03F20'  
X'03F21'  
X'03F22'  
X'03F26'  
X'03F27'  
X'03F28'  
X'03F2A'  
X'03F30'  
X'03F31'  
R/W  
Function  
Port 0 output register  
Port 1 output register  
Port 2 output register  
Port 6 output register  
Port 7 output register  
Port 8 output register  
Port 0 input register  
Port 1 input register  
Port 2 input register  
Port 6 input register  
Port 7 input register  
Port 8 input register  
Port A input register  
Port 0 direction control register  
Port 1 direction control register  
P0OUT  
P1OUT  
P2OUT  
P6OUT  
P7OUT  
P8OUT  
P0IN  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R
P1IN  
R
P2IN  
R
P6IN  
R
P7IN  
R
P8IN  
R
PAIN  
R
P0DIR  
P1DIR  
R/W  
R/W  
41  
Port Control Registers  
Chapter 3 Port Functions  
Table 3-2-1 I/O Port Control Registers (2/2)  
Name  
Address  
X'03F36'  
X'03F37'  
X'03F38'  
X'03F39'  
X'03F3A'  
X'03F40'  
X'03F41'  
X'03F42'  
X'03F46'  
X'03F47'  
X'03F48'  
X'03F4A'  
X'03F4B'  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
Function  
P6DIR  
Port 6 direction control register  
Port 7 direction control register  
Port 8 direction control register  
Port 1 output mode register  
Port A input mode register  
P7DIR  
P8DIR  
P1OMD  
PAIMD  
P0PLU  
P1PLU  
P2PLU  
P6PLU  
P7PLUD  
P8PLU  
PAPLUD  
FLOAT1  
Port 0 pull-up control register  
Port 1 pull-up control register  
Port 2 pull-up control register  
Port 6 pull-up control register  
Port 7 pull-up/pull-down control register  
Port 8 pull-up control register  
Port A pull-up/pull-down control register  
Pin control register 1  
42  
Port Control Registers  
Chapter 3 Port Functions  
7
6
5
4
3
2
1
0
P0OUT6  
P0OUT2 P0OUT1 P0OUT0  
P0OUT  
P1OUT  
P2OUT  
P0IN  
(at reset: -0---000)  
(at reset: ---00000)  
(at reset: 1-------)  
P1OUT4 P1OUT3 P1OUT2 P1OUT1 P1OUT0  
P2OUT7  
P0IN6  
P0DIR6  
P0PLU6  
P0IN2 P0IN1 P0IN0  
P1IN4 P1IN3 P1IN2 P1IN1 P1IN0  
P2IN2 P2IN1 P2IN0  
(at reset: -X---XXX)  
(at reset: ---XXXXX)  
(at reset: ----XXX)  
(at reset: -0---000)  
(at reset: ---00000)  
(at reset: ---00000)  
(at reset: -0---000)  
(at reset: ---00000)  
(at reset: -----000)  
(at reset: 00000000)  
P1IN  
P2IN  
P0DIR2 P0DIR1 P0DIR0  
P0DIR  
P1DIR  
P1OMD  
P0PLU  
P1PLU  
P2PLU  
P6OUT  
P1DIR4 P1DIR3 P1DIR2 P1DIR1 P1DIR0  
P14TCO P13TCO P12TCO  
P10TCO  
P0PLU2 P0PLU1 P0PLU0  
P1PLU4 P1PLU3 P1PLU2 P1PLU1 P1PLU0  
P2PLU2 P2PLU1 P2PLU0  
P6OUT4 P6OUT3 P6OUT2 P6OUT1 P6OUT0  
P6OUT7 P6OUT6 P6OUT5  
P6IN  
P6IN7 P6IN6 P6IN5 P6IN4 P6IN3 P6IN2 P6IN1 P6IN0  
P6DIR7 P6DIR6 P6DIR5 P6DIR4 P6DIR3 P6DIR2 P6DIR1 P6DIR0  
(at reset: XXXXXXXX)  
(at reset: 00000000)  
P6DIR  
P6PLU  
P6PLU4 P6PLU3 P6PLU2 P6PLU1 P6PLU0  
P6PLU7 P6PLU6 P6PLU5  
(at reset: 00000000)  
Figure 3-2-1 Port Control Registers (1/2)  
43  
Port Control Registers  
Chapter 3 Port Functions  
7
6
5
4
3
2
1
0
P7OUT1 P7OUT0  
P7OUT  
(at reset: - - - - - - 00)  
(at reset: 00000000)  
(at reset: - - - - - - XX)  
(at reset: XXXXXXXX)  
(at reset: XXXXXXXX)  
(at reset: - - - - - - 00)  
P8OUT7 P8OUT6 P8OUT5 P8OUT4 P8OUT3 P8OUT2 P8OUT1 P8OUT0  
P7IN1 P7IN0  
P8OUT  
P7IN  
P8IN7 P8IN6 P8IN5 P8IN4 P8IN3 P8IN2 P8IN1 P8IN0  
PAIN7 PAIN6 PAIN5 PAIN4 PAIN3 PAIN2 PAIN1 PAIN0  
P7DIR1 P7DIR0  
P8IN  
PAIN  
P7DIR  
P8DIR  
PAIMD  
P7PLUD  
P8PLU  
PAPLUD  
P8DIR7 P8DIR6 P8DIR5 P8DIR4 P8DIR3 P8DIR2 P8DIR1 P8DIR0 (at reset: 00000000)  
PAAIN7 PAAIN6 PAAIN5 PAAIN4 PAAIN3 PAAIN2 PAAIN1 PAAIN0  
P7PLUD1 P7PLUD0  
(at reset: 00000000)  
(at reset: - - - - - - 00)  
(at reset: 00000000)  
(at reset: 00000000)  
P8PLU7 P8PLU6 P8PLU5 P8PLU4 P8PLU3 P8PLU2 P8PLU1 P8PLU0  
PAPLUD7 PAPLUD6 PAPLUD5 PAPLUD4 PAPLUD3 PAPLUD2 PAPLUD1 PAPLUD0  
Figure 3-2-1 Port Control Registers (2/2)  
44  
Port Control Registers  
Chapter 3 Port Functions  
3-2-2 I/O Port Control Registers  
This section describes the special function registers that control the  
MN101C117's I/O ports.  
■ Data Registers  
• PnOUT registers  
Data registers to output to the ports.  
Data written to these registers is output from the ports.  
Low (Vss level) is output.  
High (Vdd level) is output.  
0
1
• PnIN registers  
Data registers to input data from the ports.  
The value of data at the pins can be input by reading these registers.  
These are read-only registers.  
Pin is low.  
Pin is high.  
0
1
Input and output registers are mapped to separate addresses.  
To use these ports for I/O, configure them as I/O ports in the PnOMD/PnIMD registers,  
described in this section.  
■ Direction Control Registers  
• PnDIR registers  
Input mode  
0
1
Output mode  
These registers set the port for use as an input or output.  
■ Pull-up/Pull-down Resistor Control Registers  
• PnPLU registers  
These register settings determine whether internal pull-up resistors are added to the ports.  
No pull-up / pull-down resistor  
Pull-up / Pull down resistor  
0
1
• PnPLUD registers  
These register settings determine whether internal pull-up or pull-down resistors are  
added to the ports.  
No pull-up / pull-down resistor  
Pull-up / Pull down resistor  
0
1
45  
Port Control Registers  
Chapter 3 Port Functions  
■ Port Output/Input Mode Registers  
• PnOMD/PnIMD registers  
These register settings determine whether the port pins(P10 to P14, PA0 to PA5) are used  
as I/O ports or as special function pins (dual function).  
If the special (dual) functions used, the PnDIR, PnPLU, PnPLUD, and other registers  
must be set.  
Setting the PAIMD register  
prevents unnecessary current  
from flowing in a pin when an  
intermediate voltage (analog  
voltage) is applied to the pin.  
I/O port  
0
1
Special function pin  
■ Pin Control Registers  
• FLOAT1 registers  
This register specifies whether the resistors-attached to pins P7 and PA are pull-up  
resistors or pull-down resistors.  
In addition, this register selects either zero cross input or Schmitt trigger input for pin  
P21.  
7
6
5
4
3
2
1
0
(at reset: -----000)  
P21IM  
PARDWN P7RDWN  
FLOAT1  
P7 pull-up/pull-down  
resistor selection  
P7RDWN  
0
1
pull-up resistor  
pull-down resistor  
PA pull-up/pull-down  
resistor selection  
PARDWN  
0
1
pull-up resistor  
pull-down resistor  
P21 input mode selection  
P21IM  
0
1
Schmitt trigger input  
SENS input  
Figure 3-2-2 Pin Control Register 1(FLOAT1: X'03F4B',R/W)  
46  
Port Control Registers  
Chapter 3 Port Functions  
3-3 I/O Port Configuration and Functions  
■ P00,P02,P10 to P14  
Reset  
R
Pull-up resistor control  
I/O direction control  
D
Q
L
Write  
Write  
Write  
Read  
Read  
Read  
Reset  
R
D
Q
L
Reset  
R
Port output data  
Port input data  
D
Q
L
Schmidt trigger input  
Read  
Special function input data  
Special function output control  
Special function output data  
P00  
P0PLU0  
P02  
P10  
P11  
P12  
P13  
P14  
Pull-up  
resistor  
control  
P1PLU1  
Control bit  
Register  
(address)  
P0PLU2  
P1PLU0  
P1PLU2  
P1PLU4  
P1PLU3  
P0PLU  
(X'03F40')  
P1PLU  
(X'03F41')  
I/O  
direction  
control  
P1DIR0  
P0DIR0 P0DIR2  
P1DIR1  
P1OUT1  
P1IN1  
P1DIR2  
P1DIR  
(X'03F31')  
P1DIR3  
P1OUT3  
P1IN3  
P1DIR4  
P1OUT4  
P1IN4  
Control bit  
Register  
(address)  
P0DIR  
(X'03F30')  
P0OUT0  
P0OUT  
(X'03F10')  
P0IN0 P0IN2  
P0OUT2 P1OUT0  
P1OUT2  
Control bit  
Register  
(address)  
Port  
output  
P1OUT  
(X'03F11')  
P1IN0  
P1IN2  
Control bit  
Register  
(address)  
Port  
input  
P1IN  
(X'03F21')  
P0IN  
(X'03F20')  
Output  
format  
control  
Control bit SC0SBOM SC0SBTM  
SC0MD3  
Register  
(address)  
(X'03F53')  
Special function  
Special function input  
TM2I  
SBT0  
SBT0  
TM3I  
TM4I  
TM4O  
Special  
function  
TM2O  
Special  
function  
output  
RMOUT  
P10TCO  
TM3O  
SBO0(TXD)  
Control bit  
P12TCO  
P14TCO  
P13TCO  
SC0SBOS SC0SBTS  
control (1)  
P1OMD  
(X'03F39')  
Register  
(address)  
SC0MD3  
(X'03F53')  
Special  
function  
Special  
function  
output  
SBO0/TXD  
RMOUT  
RMOEN  
Control bit  
SC0CMD  
control (2)  
Register  
(address)  
SC0CTR  
(X'03F54')  
RMCTR  
(X'3F89)  
∗ Both The TM0RM flag of the RMCTR register and the P10TCO flag of the P10MD register  
are used to switch between remote control output and timer output.  
I/O Port Configuration and Functions  
47  
Chapter 3 Port Functions  
■ P01  
Reset  
R
D
Q
Pull-up resistor control  
L
Write  
Read  
Read  
Read  
Reset  
R
D
Q
I/O direction control  
Port output data  
L
Write  
Write  
Reset  
R
D
Q
L
Schmitt trigger input  
Port input data  
Read  
Special function input data  
P01  
Control bit  
Register  
(address)  
P0PLU1  
P0PLU  
(X'03F40')  
Pull-up  
resistor  
control  
P0DIR1  
Control bit  
Register  
(address)  
I/O direction  
control  
P0DIR  
(X'03F30')  
Control bit  
P0OUT1  
Port output  
Register  
(address)  
P0OUT  
(X'03F10')  
P0IN1  
Control bit  
Port input  
Register  
(address)  
P0IN  
(X'03F20')  
Special function  
Special function input  
SBI0/RXD  
Figure 3-3-2 Configuration and Functions of P01  
48  
I/O Port Configuration and Functions  
Chapter 3 Port Functions  
■ PA0 to PA7  
Reset  
R
D
Q
Pull-up/pull-down resistor control  
L
Write  
Write  
Read  
Read  
Reset  
R
D
Q
Pull-up/pull-down resistor selection  
L
Read  
Port input data  
Reset  
R
Input mode control  
D
Q
L
Write  
Read  
Analog input  
PA0  
PA1  
PA2  
PA3  
PA4  
PA5  
PA6  
PA7  
Control bit PAPLUD0 PAPLUD1 PAPLUD2 PAPLUD3 PAPLUD4 PAPLUD5 PAPLUD6 PAPLUD7  
Pull-up  
resistor  
control  
Register  
PAPLUD  
(X'03F4A')  
(address)  
Pull-up/  
pull-down  
resistor  
PARDWN  
Control bit  
Register  
(address)  
FLOAT1  
(X'03F4B')  
control  
Control bit PAAIN0 PAAIN1 PAAIN2 PAAIN3 PAAIN4 PAAIN5 PAAIN6 PAAIN7  
Input mode  
control  
Register  
PAIMD  
(X'03F3A')  
(address)  
Control bit PAIN0 PAIN1 PAIN2 PAIN3 PAIN4 PAIN5 PAIN6 PAIN7  
Port input  
Register  
PAIN  
(address)  
(X'03F2A')  
Special function  
input  
Special function AN0  
AN1  
AN2  
AN3  
AN4  
AN5  
AN6  
AN7  
Figure 3-3-3 Configuration and Functions of PA0 to PA7  
I/O Port Configuration and Functions  
49  
Chapter 3 Port Functions  
■ Pin Configuration for P20, P22 to P23  
Reset  
R
Pull-up resistor control  
D
Q
L
Write  
Read  
Schmitt trigger input  
Port input data  
Read  
Special function input data  
P23  
P20  
P22  
P2PLU3  
P2PLU0 P2PLU2  
Control bit  
Register  
(address)  
Pull-up  
resistor  
control  
P2PLU  
(X'03F42')  
*P23 is only for  
48-pin package.  
P2IN3  
IRQ3  
P2IN0  
IRQ0  
P2IN2  
Control bit  
Register  
(address)  
Port input  
P2IN  
(X'03F22')  
Special function  
input  
IRQ2  
Interrupt input  
Figure 3-3-4 Configuration and Functions of P20, P22, P23  
50  
I/O Port Configuration and Functions  
Chapter 3 Port Functions  
■ P21  
Reset  
R
Pull-up resistor control  
D
Q
L
Read  
Read  
Read  
Read  
Reset  
R
D
Q
Special function input data  
Port input data  
L
Read  
AC zero-cross detection circuit  
Special function input data  
Schmitt trigger input  
P21  
P2PLU1  
P2PLU  
(x'03F42')  
Control bit  
Register  
(address)  
Pull-up  
resistor  
control  
P2IN1  
Control bit  
Port input  
Register  
(address)  
P2IN  
(x'03F22')  
SENS  
P21IM  
FLOAT1  
(x'03F4B')  
Special function  
Special  
function  
input  
Control bit  
Register  
(address)  
selection  
Figure 3-3-5 Configuration and Functions of P21  
I/O Port Configuration and Functions  
51  
Chapter 3 Port Functions  
■ P27  
Schmitt trigger input  
Reset signal input  
Reset  
S
Port output data  
D
Q
L
Write  
P27  
RST  
Special input  
Special function  
Soft reset output  
P2OUT7  
Special  
function  
output  
Control bit  
Register  
(address)  
P2OUT  
(x'03F12')  
Figure 3-3-6 Configuration and Functions of P27  
52  
I/O Port Configuration and Functions  
Chapter 3 Port Functions  
■ P70 to P71  
Reset  
R
D
Q
Pull-up/pull-down resistor control  
Pull-up/pull-down resistor selection  
L
Write  
Write  
Write  
Read  
Read  
Read  
Reset  
R
Q
D
L
Reset  
R
D
Q
I/O direction control  
L
Reset  
R
Port output data  
D
Q
L
Write  
Read  
Port input data  
Read  
P70  
P71  
Pull-up/  
pull-down  
resistor control  
P7PLUD0  
Control bit  
Register  
(address)  
P7PLUD1  
P7PLUD  
(X'03F47')  
Control bit  
Pull-up/  
pull-down  
resistor control  
P7RDWN  
FLOAT1  
(X'03F4B')  
Register  
(address)  
P7DIR1  
P7IN1  
P7DIR0  
P7IN0  
Control bit  
Register  
(address)  
I/O direction  
control  
P7DIR  
(X'03F37')  
Control bit  
Port input  
P7IN  
(X'03F27')  
Register  
(address)  
P7OUT0  
Control bit  
Register  
(address)  
P7OUT1  
Port output  
P7OUT  
(X'03F17')  
Figure 3-3-7 Configuration and Functions of P70  
I/O Port Configuration and Functions  
53  
Chapter 3 Port Functions  
■P60 to P67,P80 to P87  
Reset  
R
Pull-up resistor control  
I/O direction control  
Port output data  
D
Q
L
Write  
Write  
Write  
Read  
Read  
Read  
Reset  
R
D
Q
L
Reset  
R
D
Q
L
Schmidt trigger input  
Port input data  
Read  
P65  
P66  
P67  
P60  
P61  
P62  
P63  
P64  
P6PLU5 P6PLU6 P6PLU7  
P6DIR5 P6DIR6 P6DIR7  
P6OUT5 P6OUT6 P6OUT7  
P6IN5 P6IN6 P6IN7  
P6PLU0 P6PLU1 P6PLU2 P6PLU3 P6PLU4  
Pull-up  
resistor  
control  
Control bit  
P6PLU  
(x'03F46')  
Register  
(address)  
P6DIR0 P6DIR1 P6DIR2 P6DIR3 P6DIR4  
Control bit  
I/O  
direction  
control  
P6DIR  
(x'03F36')  
Register  
(address)  
P6OUT0 P6OUT1 P6OUT2 P6OUT3 P6OUT4  
Control bit  
Port output  
Port input  
P6OUT  
(x'03F16')  
Register  
(address)  
P6IN0 P6IN1 P6IN2 P6IN3 P6IN4  
Control bit  
P6IN  
(x'03F26')  
Register  
(address)  
Figure 3-3-8 Configuration and Functions of P60 to P67  
P85  
P86  
P87  
P80  
P81  
P82  
P83  
P84  
P8PLU5 P8PLU6 P8PLU7  
P8DIR5 P8DIR6 P8DIR7  
P8OUT5 P8OUT6 P8OUT7  
P8IN5 P8IN6 P8IN7  
P8PLU0 P8PLU1 P8PLU2 P8PLU3 P8PLU4  
Pull-up  
resistor  
control  
Control bit  
P8PLU  
(x'03F48')  
Register  
(address)  
P8DIR0 P8DIR1 P8DIR2 P8DIR3 P8DIR4  
Control bit  
I/O  
direction  
control  
P8DIR  
(x'03F38')  
Register  
(address)  
P8OUT0 P8OUT1 P8OUT2 P8OUT3 P8OUT4  
Control bit  
Port output  
Port input  
P8OUT  
(x'03F18')  
Register  
(address)  
P8IN0 P8IN1 P8IN2 P8IN3 P8IN4  
Control bit  
P8IN  
(x'03F28')  
Register  
(address)  
Figure 3-3-9 Configuration and Functions of P80 to P87  
54  
I/O Port Configuration and Functions  
Chapter 4  
Timer Functions  
4
55  
Chapter 4 Timer Functions  
4-1 Overview  
The MN101C117 contains three 8-bit timers, one 16-bit timer, a watchdog  
timer, a time base timer, and circuits for remote control output and buzzer  
output.  
Table 4-1-1 Summary of Timer Functions  
Timer 2  
(8-bit)  
Timer 3  
(8-bit)  
Timer 4  
(16-bit)  
Timer 5  
(8-bit)  
Time Base  
TBIRQ  
Interrupt  
TM2IRQ  
TM3IRQ  
TM4IRQ  
TM5IRQ  
Timer operation  
Event counter  
×
×
×
×
×
Timer pulse output  
Serial  
transmission clock  
×
×
×
×
×
×
×
×
×
×
×
×
×
PWM output  
Cascade  
connection  
Capture function  
0
fs  
fs/4  
fx  
fosc  
fs/4  
fosc  
fs/4  
fosc  
fs/4  
fx  
fosc  
fx  
1
2
3
Clock  
source  
fs/16  
fs/16  
TM2IO input TM3IO input TM4IO input fosc,fx/213  
Not  
Remote  
control  
carrier pulse  
generation  
Pulse  
added  
type  
possible to  
temporarily  
halt BC  
Other  
PWM  
56  
Overview  
Chapter 4 Timer Functions  
Figure 4-1-1 Timers 2, 3 Block Diagram  
Overview  
57  
Chapter 4 Timer Functions  
Figure 4-1-2 Timer 4 Block Diagram  
58  
Overview  
Chapter 4 Timer Functions  
Figure 4-1-3 Timer 5/Time Base Block Diagram  
Overview  
59  
Chapter 4 Timer Functions  
Refer to the aragraph  
[1-6-1 ROM option]  
Figure 4-1-4 Watchdog Timer, Buzzer Block Diagram  
60  
Overview  
Chapter 4 Timer Functions  
Figure 4-1-5 Remote Control Transmission Block Diagram  
Overview  
61  
Chapter 4 Timer Functions  
4-2 8-bit Timer Operation (timers 2, 3)  
4-2-1 Overview  
Functions for timers 2 and 3 are listed below.  
Table 4-2-1 Summary of 8-bit Timer Functions  
Timer 2 Timer 3  
(8-bit)  
(8-bit)  
Interrupt  
TM2IRQ TM3IRQ  
Timer operation  
Event counter  
Timer pulse output  
Serial  
transmission clock  
×
(SIF0)  
×
PWM output  
Cascade  
connection  
Remote control  
carrier pulse  
generation  
×
62  
8-bit Timer Operation (timers 2, 3)  
Chapter 4 Timer Functions  
When servicing an interrupt, reset  
the timer 2 interrupt request flag  
before starting timer 2.  
4-2-2 Operation  
During a count operation, be  
careful if the value set in TM2OC  
is smaller than the value of binary  
counter 2, since the count-up  
operation will continue until  
overflow occurs.  
■ Timer Operation (timers 2, 3)  
Settings for timer operation are listed below. Timer 2 is used as an example.  
(1)  
Set the TM2EN flag of the timer 2 mode register (TM2MD) to "0" to stop the count  
operation of timer 2.  
If fx is to be selected as the clock  
source and the value of binary  
counter 2 is to be read during  
operation, select synchronized fx  
in order to avoid reading data that  
may be incomplete during count-  
up transitions. However, with  
synchronized fx, it is not possible  
to return from STOP/HALT modes.  
(2)  
(3)  
Set the TM2CK2  
0 flags of the TM2MD register to select fs, fs/4, fx, or  
synchronized fx as the clock source.  
Set the TM2PWM flag of the TM2MD register to "0" so that normal timer operation  
is selected.  
(4)  
(5)  
(6)  
Set a value in compare register 2 (TM2OC).  
Set the TM2EN flag of the TM2MD register to "1" to start the timer.  
When timer 2 begins operation, binary counter 2 (TM2BC) will count upward from  
X'00'.  
(7)  
When the value of binary counter 2 matches that of the TM2OC register, the timer 2  
interrupt request flag is set, and the binary counter 2 is reset to X'00' and begins to  
count upward again.  
Clock  
TM4EN  
Write to registers  
TM4OCH, TM4OCL  
Binary  
counter 4  
04  
05  
06  
07  
08  
09  
00  
Figure 4-2-1 Binary Counter 2 (TM2BC) Count Timing  
If the TM2EN flag of TM2MD register is changed simultaneously with  
other bits, the switching operation may cause binary counter 2 to be  
incremented.  
If the value of TM2OC register is overwritten while timer 2 has  
stopped counting, binary counter 2 will be reset to X'00' at the edge  
of next count clock.  
The value of TM3CK0~2 of T3MD register is unsettled. If timer2/  
timer 3 is independently used, any mode except cascade  
connection should be set.  
8-bit Timer Operation (timers 2, 3)  
63  
Chapter 4 Timer Functions  
If TM2IO input is selected as the  
clock source and the value of  
binary counter 2 is to be read  
■ Event Count Function (timers 2, 3)  
Settings for the event count function are listed below. Timer 2 is used as an example.  
during  
operation,  
select  
synchronized TM2IO input to avoid  
reading data that may be  
incomplete during count-up  
transitions. However, with  
synchronized TM2IO input, it is not  
(1)  
(2)  
(3)  
Set the TM2EN flag of the timer 2 mode register (TM2MD) to "0" to stop the count  
operation of timer 2.  
Use the TM2CK2 to 0 flags of the TM2MD register to select TM2IO input or  
synchronous TM2IO input as the clock source.  
possible  
to  
return  
from  
Set the TM2PWM flag of the TM2MD register to "0" so that normal timer operation is  
selected.  
STOP/HALT modes.  
(4)  
(5)  
(6)  
(7)  
Set a value in compare register 2 (TM2OC).  
Set the TM2EN flag of the TM2MD register to "1" to start the timer.  
When timer 2 begins operation, binary counter 2 will count upward from X'00'.  
When the value of binary counter 2 matches that of the TM2OC register, the timer 2  
interrupt request flag is set, and the binary counter 2 is reset to X'00' and begins to count  
upward again.  
When synchronized TM2IO is selected, the timer 2 clock source is synchronized with the system  
clock after a transition of the TM2IO input signal. Binary counter 2 counts upward based on a  
signal synchronized to the system clock. Therefore, correct values can be read from binary counter  
2.  
CPU system clock  
(fs)  
TM4IO input  
Synchronous  
circuit output  
Binary counter  
n
n+1  
Figure 4-2-2 Timer 2 Event Counter Timing  
(when synchronous TM2IO input is selected)  
64  
8-bit Timer Operation (timers 2, 3)  
Chapter 4 Timer Functions  
The period of a signal output to the  
port is 1/2 of the period set in the  
TM2OC register.  
■ Timer Pulse Output Function (timers 2, 3)  
Settings for the timer pulse output function are listed below. Timer 2 is used as an  
example.  
If port 1 is to be used as a pulse  
output pin, it is necessary to set  
the port 1 output direction control  
register (P1DIR) and the port 1  
pull-up/pull-down resistor control  
register (P1PLU).  
(1)  
(2)  
(3)  
(4)  
Set the TM2EN flag of the timer 2 mode register (TM2MD) to "0" to stop the count  
operation of timer 2.  
Set bit 2 of the port 1 output/input mode register (P1OMD) to "1" to set the special  
function pin. Bit 2 of port 1 will be specified as the pulse output pin.  
Set the TM2CK2 to 0 flags of the TM2MD register to select fs, fs/4, fx, or  
synchronized fx as the clock source.  
Set the TM2PWM flag of the TM2MD register to "0" so that normal timer operation  
is selected.  
(5)  
(6)  
(7)  
(8)  
Set a value in compare register 2 (TM2OC).  
Set the TM2EN flag of the TM2MD register to "1" to start the timer.  
When timer 2 begins operation, binary counter 2 will count upward from X'00'.  
When the value of binary counter 2 matches that of the TM2OC register, the timer 2  
interrupt request flag is set, and the binary counter 2 is reset to X'00' and begins to  
count upward again.  
Matches compare register  
Binary counter  
TM2OUT  
Figure 4-2-3 Timer Pulse Output Timing  
8-bit Timer Operation (timers 2, 3)  
65  
Chapter 4 Timer Functions  
If the TM3PWM flag of the TM3MD  
register is set to "1" and timer 2  
PWM output is selected, the PWM  
output of timer 2 will also be output  
from the TM3IO pin.  
■ PWM Output Function (Timer 2)  
Settings for the PWM output function are listed below.  
(1)  
(2)  
(3)  
Set the TM2EN flag of the timer 2 mode register (TM2MD) to "0" to stop the count  
operation of timer 2.  
If port 1 is to be used as a PWM  
output pin, the P1DIR and P1PLU  
registers must be set.  
Set bit 2 of the port 1 output/input mode register (P1OMD) to the special function  
pin setting. Bit 2 of port 1 will be specified as the PWM output pin.  
Set the TM2CK2 to 0 flags of the TM2MD register to select fs, fs/4, fx, or  
synchronous fx as the clock source. The period of the output waveform is determined  
based on the clock source.  
(4)  
(5)  
Set the TM2PWM flag of the TM2MD register to "1" so that PWM operation is  
selected.  
Set a value in compare register 2 (TM2OC). The high interval of the output  
waveform is determined based on the value of the TM2OC compare register.  
Set the TM2EN flag of the TM2MD register to "1" to start the timer.  
When timer 2 begins operation, binary counter 2 will count upward from X'00'.  
A high-level signal is output from the port beginning when binary counter 2 starts  
counting at X'00' and ending when the value of binary counter 2 matches the value  
set in the TM2OC register.  
(6)  
(7)  
(8)  
(9)  
When the value of binary counter 2 matches that of the TM2OC register, a low-level  
signal is output from the port.  
(10) Binary counter 2 continues to count upward until X'FF' is reached. At the next count-  
up cycle, the value of binary counter 2 is reset to X'00', a high-level signal is output  
from the port, and counting begins again.  
Overflow  
Matches TM2OC  
register  
Binary  
counter 2  
PWM output  
Time specified by TM2OC register  
Time until binary counter 2 reaches X'FF'  
Figure 4-2-4 PWM Output Timing  
66  
8-bit Timer Operation (timers 2, 3)  
Chapter 4 Timer Functions  
Clock  
PWM output  
Figure 4-2-5 PWM Output Timing (when TM2OC register is X'00')  
Matches TM2OC register  
Overflow  
Binary  
counter 2  
PWM output  
Figure 4-2-6 PWM Output Timing (when TM2OC register is X'FF')  
8-bit Timer Operation (timers 2, 3)  
67  
Chapter 4 Timer Functions  
The clock source for the serial  
interface has a frequency that is  
1/2 of the overflow output of timer  
3.  
■ Serial Transfer Clock Function(timer 3)  
Settings for the serial transfer clock function are listed below.  
(1)  
(2)  
(3)  
Set the TM3EN flag of the timer 3 mode register (TM3MD) to "0" to stop the count  
operation of timer 3.  
For serial interface settings, refer  
to the chapter on serial functions.  
Set the SC0CK1 and SC0CK0 flags of the serial interface 0 mode register 1  
(SC0MD1) to select 1/2 of the timer 3 overflow frequency as the clock source.  
Set the TM3CK2 to 0 flags of the TM3MD register to select fosc, fs, fs/4, or fs/16 as  
the clock source.  
(4)  
(5)  
(6)  
Set the TM3PWM flag of the TM3MD register to "0" to select timer 3 output.  
Set a value in compare register 3 (TM3OC).  
Set the TM3EN flag of the TM3MD register to "1" to start the timer.  
(7)  
(8)  
When timer 3 begins operation, binary counter 3 counts upward from X'00'.  
When the value of binary counter 3 matches that of the TM3OC register, the timer 3  
interrupt request flag is set, the value of binary counter 3 is reset to X'00', and  
counting begins again.  
■ Cascade Connection Function (timer 2 + timer 3)  
Settings for the cascade connection function are listed below. Timer 2 and timer 3  
are connected to operate as a 16-bit timer.  
(1)  
(2)  
(3)  
(4)  
(5)  
Set the TM2EN flag of the timer 2 mode register (TM2MD) to "0" to stop the count  
operation of timer 2.  
Set the TM3EN flag of the timer 3 mode register (TM3MD) to "0" to stop the count  
operation of timer 3.  
Set the TM2CK2 to 0 flags of the TM2MD register to select fs, fs/4, fx, or  
synchronized fx as the clock source.  
Use the TM3CK2 to 0 flags of the TM3MD register to set the clock source as a  
cascade connection with timer 2.  
Set the TM2PWM flag of the TM2MD register to "0" to select normal timer  
operation.  
(6)  
(7)  
(8)  
(9)  
Set values in compare register 2 (TM2OC) and compare register 3 (TM3OC).  
Set the TM2EN flag of the TM2MD register to "1" to start the timer.  
Set the TM3EN flag of the TM3MD register to "1" to start the timer.  
When timers 2 and 3 begin operation, the binary counters begin counting upward  
from X'0000' as a 16-bit counter.  
Disable the timer 2 interrupt.  
(10) When the value of the 16-bit binary counter matches that of the 16-bit register  
(TM3OC+TM2OC), the timer 3 interrupt request flag is set, the value of the 16-bit  
binary counter is reset to X'0000', and counting begins again.  
Use a 16-bit access instruction to set the (TM3OC+TM2OC) register.  
68  
8-bit Timer Operation (timers 2, 3)  
Chapter 4 Timer Functions  
4-3 16-bit Timer Operation (timer 4)  
4-3-1 Overview  
Timer 4 is a 16-bit programmable counter that can be used as an event counter.  
A signal with a frequency of 1/2 of the timer 4 overflow signal can be output from the  
TM4IO pin. An input capture function and pulse added type PWM output function can  
also be used.  
4-3-2 Operation  
■ Timer Operation  
When servicing an interrupt, reset  
the timer 4 interrupt request flag  
before operating timer 4.  
Settings for timer operation are listed below.  
(1)  
(2)  
Set the TM4EN flag of the timer 4 mode register (TM4MD) to "0" to stop the count  
operation of timer 4.  
During a count operation, be  
careful if the value set in TM4OCH  
and TM4OCL is smaller than the  
value of binary counter 4, since  
the count-up operation will  
continue until overflow occurs.  
Set the TM4CK2 to 0 flags of the TM4MD register to select fosc, fs/4, or fs/16 as the  
clock source.  
(3)  
(4)  
(5)  
(6)  
(7)  
Set the TM4PWM flag of the TM4MD register to "0" to select 16-bit timer operation.  
Set a value in compare register 4 (TM4OCH, TM4OCL).  
Set the TM4EN flag of the TM4MD register to "1" to start the timer.  
When timer 4 begins operation, binary counter 4 counts upward from X'0000'.  
When the value of binary counter 4 matches that of the TM4OCH and TM4OCL  
registers, the timer 4 interrupt request flag is set, the value of binary counter 4 is reset  
to X'0000', and counting begins again.  
16-bit Timer Operation (timer 4)  
69  
Chapter 4 Timer Functions  
Clock  
TM4EN  
Write to registers  
TM4OCH, TM4OCL  
Binary  
counter 4  
04  
05  
06  
07  
08  
09  
00  
Figure 4-3-1 Binary Counter 4 (TM4BC) Count Timing  
If the TM4EN flag of the TM4MD register is changed simultaneously  
with other bits, the switching operation may cause binary counter 4  
to be incremented.  
If the value of the TM4OCH, TM4OCL register is overwritten while  
timer 4 has stopped counting, binary counter 4 will be reset to  
X'0000'.  
70  
16-bit Timer Operation (timer 4)  
Chapter 4 Timer Functions  
■ Event Count Function  
If TM4IO input is selected as the  
clock source and the value of  
binary counter 4 is to be read  
Settings for the event count function are listed below.  
(1)  
(2)  
(3)  
Set the TM4EN flag of the timer 4 mode register (TM4MD) to "0" to stop the count  
operation of timer 4.  
during  
operation,  
select  
synchronized TM4IO input to avoid  
reading data that may be  
incomplete during count-up  
transitions. However, with  
synchronized TM4IO input, it is not  
Use the TM4CK2 to 0 flags of the TM4MD register to select TM4IO input or  
synchronized TM4IO input as the clock source.  
Set the TM4PWM flag of the TM4MD register to "0" so that 16-bit timer operation  
is selected.  
possible  
to  
return  
from  
STOP/HALT modes.  
(4)  
(5)  
(6)  
(7)  
Set a value in compare register 4 (TM4OCH, TM4OCL).  
Set the TM4EN flag of the TM4MD register to "1" to start the timer.  
When timer 4 begins operation, binary counter 4 will count upward from X'0000'.  
When the value of binary counter 4 matches that of the TM4OCH and TM4OCL  
registers, the timer 4 interrupt request flag is set, and the binary counter 4 is reset to  
X'0000' and begins to count upward again.  
When synchronized TM4IO is selected, the timer 4 clock source is synchronized with the system  
clock after a transition of the TM4IO input signal. Timer 4 counts upward based on a signal  
synchronized to the system clock. Therefore, correct values can be read from binary counter 4.  
Figure 4-3-2 Timer 4 Event Counter Timing (when synchronous TM4IO  
CPU system clock  
(fs)  
TM4IO input  
Synchronous  
circuit output  
Binary counter  
n
n+1  
input is selected)  
16-bit Timer Operation (timer 4)  
71  
Chapter 4 Timer Functions  
The period of the output signal  
from the port is 1/2 of the period  
set in the TM4OCH, TM4OCL  
register.  
■ Timer Pulse Output Function  
Settings for the timer pulse output function are listed below.  
(1)  
(2)  
(3)  
(4)  
Set the TM4EN flag of the timer 4 mode register (TM4MD) to "0" so that the count  
operation of timer 4 is stopped.  
Set bit 4 of the port 1 output/input mode register (P1OMD) to the special  
function pin setting. Bit 4 of port 1 will be specified as the pulse output pin.  
Use the TM4CK2 to 0 flags of the TM4MD register to select fosc, fs/4, or fs/16 as the  
clock source.  
Set the TM4PWM flag of the TM4MD register to "0" so that 16-bit timer operation  
is selected.  
(5)  
(6)  
(7)  
(8)  
Set a value in compare register 4 (TM4OCH, TM4OCL).  
Set the TM4EN flag of the TM4MD register to "1" to start the timer.  
When timer 4 begins operation, binary counter 4 will count upward from X'0000'.  
When the value of binary counter 4 matches that of the TM4OCH and TM4OCL  
registers, the timer 4 interrupt request flag is set, and the binary counter 4 is reset to  
X'0000' and begins to count upward again.  
Matches TM4OCH, TM4OCL register  
Binary  
counter 4  
TM4OUT  
Figure 4-3-3 Timer Pulse Output Timing  
72  
16-bit Timer Operation (timer 4)  
Chapter 4 Timer Functions  
If bit 4 of port 1 is to be used as a  
PWM output pin, set the P1DIR  
and P1PLU registers.  
■ Pulse Added Type PWM Output Function  
In the pulse added method, a 1-bit output is appended to the basic component of the 8-bit  
PWM output. Precise control is possible based on the number of PWM repetitions (256  
times) to which this bit is appended. Settings for the pulse added type PWM output function  
are listed below.  
(1)  
(2)  
(3)  
(4)  
(5)  
Set the TM4EN flag of the timer 4 mode register (TM4MD) to "0" to stop the count  
operation of timer 4.  
Set bit 4 of the port 1 output/input mode register (P1OMD) to the special function  
pin setting. Bit 4 of port 1 will be specified as the PWM output pin.  
Use the TM4CK2 to 0 flags of the TM4MD register to select fosc, fs/4, or fs/16 as the  
clock source. The period of the output waveform is determined based on the clock source.  
Set the TM4PWM flag of the TM4MD register to "1" so that PWM operation is  
selected.  
Set a value in the lower 8 bits of compare register 4 (TM4OCL). The high interval of  
the output waveform is determined based on the value of the lower 8 bits of compare  
register 4 (TM4OCL).  
(6)  
Set the position of the added pulse in the upper 8 bits of compare register 4  
(TM4OCH).  
PWM4 output is fixed at L with  
X'FF' set at the lower  
8
(7)  
(8)  
(9)  
Set the TM4EN flag of the TM4MD register to "1" to start the timer.  
When timer 4 begins operation, binary counter 4 will count upward from X'00'.  
A high-level signal is output from the port beginning when binary counter 4 starts  
counting from X'00' and ending when the value of binary counter 4 matches the  
value set in the TM4OCL register.  
bits(TM40CL) of compare register.  
Use of timer 4 at PWM mode  
disables setting of X'FF' att  
TM4OCL register.  
(10) When the value of binary counter 4 matches that of the TM4OCL register, a low-  
level signal is output from the port.  
(11) Binary counter 4 continues to count upward until X'FF' is reached. At the next count-  
up cycle, the value of binary counter 4 is reset to X'00', and counting begins again.  
A high-level signal is output from the port.  
Use a 16-bit access instruction to set the TM4OCH, TM4OCL  
register.  
Basic PWM components  
Added pulse  
: Added pulse  
Tn=X'04'  
Tn=X'FF'  
Tn=X'00'  
Tn=X'01'  
Tn=X'02'  
Tn=X'03'  
Repeated 256 times  
Figure 4-3-4 Pulse Added Type PWM Output  
16-bit Timer Operation (timer 4)  
73  
Chapter 4 Timer Functions  
[☞ 5-2-3 "Serial Interface  
■ Setting the Added Pulse Position  
Transfer Timing"]  
The upper 8 bits of compare register 4 (TM4OCH) set the position of the added pulse. If the  
TM4OCH register is set to X'00', an additional bit is not appended to the basic PWM  
component. If the TM4OCH register is set to X'FF', an additional bit is repeatedly appended  
to the 255 basic PWM components during the period. The relation between the value set in  
the TM4OCH register and the added pulse is shown in the table below. If X'03' is set in the  
TM4OCH register, bits are appended to pulse positions for X'01' and X'02', shown in table  
4-3-1. The relation between the value set in the TM4OCH register and the position of the  
added bit is shown in figure 4-3-5.  
Table 4-3-1 Pulse-Added PWM OutputFigure  
Value Set in TM4OCH Register  
Added Pulse Position (value of Tn)  
0 0 0 0 0 0 0 0  
0 0 0 0 0 0 0 1  
0 0 0 0 0 0 1 0  
0 0 0 0 0 1 0 0  
0 0 0 0 1 0 0 0  
0 0 0 1 0 0 0 0  
0 0 1 0 0 0 0 0  
0 1 0 0 0 0 0 0  
1 0 0 0 0 0 0 0  
X'80'  
X'40',X'C0'  
X'20',X'60',X'A0',X'E0'  
X'10',X'30',X'50',X'70',X'90',X'B0',X'D0',X'F0'  
X'08',X'18',X'28',X'38',X'48',X'58' . . . . .,X'E8',X'F8'  
X'04',X'0C',X'14',X'1C',X'24',X'2C' . . . . .,X'F4',X'FC'  
X'02',X'06',X'0A',X'0E',X'12',X'16' . . . . .,X'FA',X'FE'  
X'01',X'03',X'05',X'07',X'09',X'0B' . . . . .,X'FD',X'FF'  
(MSB)  
(LSB)  
Repeated 256 times  
X '80'  
TM4OCH  
Register setting  
0
X '40'  
X 'C0'  
X 'FF'  
Position of  
added pulse  
value  
X '00'  
X '01'  
X '02'  
X '04'  
X '08'  
X '10'  
PWM basic component  
Position of added pulse X'87'  
Position of added pulse X'88'  
Figure 4-3-5 Pulse Added Type PWM Output  
74  
16-bit Timer Operation (timer 4)  
Chapter 4 Timer Functions  
■ Capture Function  
Settings for the capture function are listed below.  
(1)  
(2)  
(3)  
(4)  
(5)  
Set the TM4EN flag of the timer 4 mode register (TM4MD) to "0" to stop the count  
operation of timer 4.  
Use the TM4CK2 to 0 flags of the TM4MD register to select fosc, fs/4, or fs/16 as the  
clock source.  
Use the T4ICTS1 and T4ICTS0 flags of the TM4MD register to select IRQ2,  
IRQ1, or IRQ0 as the input capture trigger.  
Set the REDGn flag of the external interrupt control register to specify the valid edge  
for the interrupt selected as the TM4 input capture trigger.  
Set the TM4PWM flag of the TM4MD register to "1" to select 16-bit timer  
operation.  
Setting a value in compare register  
4, clears binary counter 4.  
(6)  
(7)  
(8)  
Set a value in compare register 4 (TM4OCH, TM4OCL).  
Set the TM4EN flag of the TM4MD register to "1" to start the timer.  
When timer 4 begins operation, binary counter 4 will count upward from X'0000'  
until it reaches the value set in compare register 4.  
(9)  
If the binary counter is to be used as a free-running counter that counts from  
X'0000' to X'FFFF', set the compare register 4 to X'FFFF'.  
When the value of binary counter 4 matches that of the TM4OCH, TM4OCL  
register, the timer 4 interrupt request flag is set, binary counter 4 is reset to X'0000',  
and counting begins again.  
(10) If the external interrupt selected as the TM4 input capture trigger is received during  
timer 4 operation, the value of binary counter 4 will be written into the input capture  
register (TM4ICH, TM4ICL).  
If the event occurs before a read,  
that data will be overwritten.  
16-bit Timer Operation (timer 4)  
75  
Chapter 4 Timer Functions  
4-4 8-bit Timer Operation (timer 5)  
4-4-1 Overview  
Timer 5 is an 8-bit timer that can have fosc, fs/4, fx, or time base output as  
its clock source.  
4-4-2 Operation  
■ Timer Operation  
Settings for timer operation are listed below.  
When servicing an interrupt, reset  
the timer 5 interrupt request flag  
before starting timer 5.  
(1)  
(2)  
Set the TM5CLRS flag of the timer 5 mode register (TM5MD) to "0."  
Use the TM5CK3 to 1 flags of the TM5MD register to select fosc, fs/4, fx,  
synchronized fx, time base timer output, or time base timer synchronized output as  
the clock source.  
When choosing either time base  
timer output or time base timer  
synchronized output for the timer 5  
clock source, the time base must  
be set up.  
(3)  
Set a value in compare register 5 (TM5OC). At this time, if the TM5CLRS flag is  
"0," binary counter 5 will be initialized to X'00'.  
(4)  
(5)  
Binary counter 5 (TM5OC) counts upward from X'00'.  
During a count operation, be  
careful if the value set in TM5OC  
is smaller than the value of binary  
counter 5, since the count-up  
operation will continue until  
overflow occurs.  
When the value of binary counter 5 matches that of the TM5OC register, the timer 5  
interrupt request flag is set, the binary counter is reset to X'00', and counting begins  
again.  
If the TM5CLRS flag of the TM5MD register is set to "0," binary  
counter 5 will be initialized every time data in the TM5OC register is  
overwritten. Timer 5 interrupts are disabled in this mode. If timer 5  
interrupts are to be used, the TM5CLRS flag must be reset to "1"  
after writing to the TM5OC register.  
If fx input is selected as the clock  
source and the value of binary  
counter 5 is to be read during  
operation, select synchronized fx  
input to avoid reading data that  
may be incomplete during count-  
up transitions. However, with  
synchronized fx input, it is not  
possible  
to  
return  
from  
STOP/HALT modes.  
Timer 5 operation cannot be halted.  
76  
8-bit Timer Operation (timers 2, 3)  
Chapter 4 Timer Functions  
4-5 Time Base Operation  
4-5-1 Overview  
The clock source for the time base timer can be set to fosc or fx. Also, the interrupt  
7
8
9
10  
13  
period for time base timer (TBIRQ) can be set to 1/2 , 1/2 , 1/2 , 1/2 , or 1/2 of the  
clock source.  
4-5-2 Operation  
■ Time Base Function  
Settings for the time base function are listed below.  
(1)  
(2)  
(3)  
Use the TM5CK0 flag of the timer 5 mode register (TM5MD) to select fosc or fx as  
the clock source.  
Use the TM5IR2 to 0 flags of the TM5MD register to select the time base timer  
interrupt source.  
When the selected time interval passes, the interrupt request flag of the time base  
interrupt control register (TBICR) is set.  
Time base operation cannot be halted.  
Table 4-5-1 Base Time Settings  
000  
001  
010  
011  
1XX  
TM5IR2 to 0  
Clock Source  
1
1
1
1
1
27  
28  
29  
210  
213  
20MHz  
8.38MHz  
32.768kHz  
6.4µs  
15.2µs  
3.9ms  
12.8µs  
30.5µs  
7.8ms  
25.6µs  
61.0µs  
15.6ms  
51.2µs  
122.0µs  
31.2ms  
409.6µs  
976.4µs  
250ms  
fosc  
fx  
Time Base Operation  
77  
Chapter 4 Timer Functions  
4-6 Watchdog Timer Operation  
4-6-1 Overview  
The watchdog timer is controlled by the watchdog control register (WDCTR) and can  
be used for runaway program detection.  
4-6-2 Setup and Operation  
(1)  
(2)  
Set the WDEN flag of the watchdog timer control register (WDCTR) to "1" to start  
the watchdog timer.  
The upper 2 bits of the watchdog  
timer are cleared when the WDEN  
flag is set to "0." Therefore, if  
WDEN flag is set to 0 when an  
uppermost bit of a watchdog timer  
is 1, WDT interrupt occurs  
depending on the timing of this  
clear the watchdog timer may be  
reset at 1/4TWD. If the WDEN bit is  
Operate the watchdog timer by clearing the WDEN flag to "0" within the fixed  
amount of time (TWD), and then resetting the WDEN flag to "1."  
If the WDEN flag is not cleared, a WDT interrupt will be generated after the fixed  
amount of time passes.  
(3)  
When an illegal operation is detected, the program encoded at the location of the  
WDT interrupt routine is executed.  
16  
18  
20  
to be repeatedly cleared and set at  
regular intervals, those operations  
should be performed within 1/4 of  
the TWD period.  
TWD is set by the ROM option as fs/2 , fs/2 , or fs/2 .  
Illegal operation detection period vs. WDEN clear period is shown by the following formula:  
Illegal operation detection period > [WDEN clear period] x 4  
When software resetting is not triggered by WDT interrupt,  
hardware resetting (low level output at the reset terminal) takes  
place at the next WDT interrupt.  
78  
Watchdog Timer Operation  
Chapter 4 Timer Functions  
4-7 Remote Control Output Operation  
4-7-1 Overview  
A remote control carrier pulse can be generated using the overflow of timer 3. Two  
duty ratios of 1/2 or 1/3 can be selected.  
4-7-2 Setup and Operation  
(1)  
(2)  
Set the RMOEN flag of the remote control carrier output control register (RMCTR)to  
"0" so that the remote control carrier output is switched off.  
Set timer 3 to select the base period of the remote control carrier (the  
width that the remote control carrier output pulse is held at a high level).  
Set the RMDTY0 flag of the RMCTR register to select the carrier duty.  
Set the P10 output data to "0" and set P10 to the output mode. And select the remote  
control carrier output by setting the TMORM flag of the RMCTR register to "0".  
The RMOEN flag of the RMCTR register controls whether the remote control carrier  
output is on or off.  
Set bit 0 of the P1OMD register to  
"1" at the same time the remote  
control output is switched on, and  
to "0" at the same time the remote  
control output is switched off.  
(3)  
(4)  
(5)  
Even if the carrier output is at a high level, and the RMOEN flag is set to "0"  
(off), the carrier waveform will be maintained by the synchronous circuit  
Base period  
set by TM3  
RMOEN Output on  
Output off  
RMOUT  
(1/3 duty)  
Figure 4-7-1 Remote Control Carrier Output Waveform  
Remote Control Output Operation  
79  
Chapter 4 Timer Functions  
4-8 Buzzer Output  
4-8-1 Buzzer Output Setup and Operation  
9
12  
The square wave having a frequency 1/2 to 1/2 of the system clock can be  
output from the P06/BUZZER pin.  
(1)  
(2)  
(3)  
(4)  
Set the BUZOE flag of the oscillation stabilization wait control register (DLYCTR)  
to "0" so that the buzzer output is turned off.  
Set the buzzer output frequency with the BUZCK1 and BUZCK0 flags of the  
DLYCTR.  
Set the BUZOE flag of the DLYCTR register to "1" and set P06 to the buzzer output  
mode.  
The BUZOE flag of the DLYCTR register controls whether the buzzer output is ON  
or OFF.  
80  
Buzzer Output  
Chapter 4 Timer Functions  
4-9 Timer Function Control Registers  
4-9-1 Overview  
19 registers control the timers. See table 4-9-1.  
Table 4-9-1 Timer Control Registers  
Name  
TM2OC  
TM2BC  
TM2MD  
TM3OC  
TM3BC  
TM3MD  
TM4OCL  
TM4OCH  
TM4BCL  
TM4BCH  
TM4ICL  
TM4ICH  
TM4MD  
TM5OC  
TM5BC  
TM5MD  
WDCTR  
DLYCTR  
RMCTR  
Function  
Address  
X’03F72’  
X’03F62’  
X’03F82’  
X’03F73’  
X’03F63’  
X’03F83’  
X’03F74’  
X’03F75’  
X’03F64’  
X’03F65’  
X’03F66’  
X’03F67’  
X’03F84’  
X’03F78’  
X’03F68’  
X’03F88’  
X’03F02’  
X’03F03’  
X’03F89’  
R/W  
R/W  
R
Compare register 2  
Binary counter 2  
R/W  
R/W  
R
Timer 2 mode register  
Compare register 3  
Binary counter 3  
R/W  
R/W  
R/W  
R
Timer 3 mode register  
Compare register 4 (lower 8 bits)  
Compare register 4 (upper 8 bits)  
Binary counter 4 (lower 8 bits)  
Binary counter 4 (upper 8 bits)  
Input capture register (lower 8 bits)  
Input capture register (upper 8 bits)  
Timer 4 mode register  
R
R
R
R/W  
R/W  
R
Compare register 5  
Binary counter 5  
R/W  
R/W  
R/W  
R/W  
Timer 5 mode register  
Watchdog timer control register  
Oscillation stabilization wait control register  
Remote control carrier output control register  
R/W: Readable and writable  
R: Read only  
Overview  
81  
Chapter 4 Timer Functions  
4-9-2 Programmable Timer/Counters  
Timers 2~5 all contain a programmable 8-bit timer/counter (16-bit in timer 4).  
Programmable timer/counters consist of a compare register and a binary  
counter.  
(1) Compare register 2 (TM2OC)  
7
6
5
4
3
2
1
0
TM2OC7 TM2OC6 TM2OC5 TM2OC4 TM2OC3 TM2OC2 TM2OC1 TM2OC0  
(at reset: undefined)  
Figure 4-9-1 Compare Register 2 (TM2OC: X'03F72', R/W)  
(2) Binary counter 2 (TM2BC)  
7
6
5
4
3
2
1
0
TM2BC7 TM2BC6 TM2BC5 TM2BC4 TM2BC3 TM2BC2 TM2BC1 TM2BC0  
(at reset: 00000000)  
Figure 4-9-2 Binary Counter 2 (TM2BC: X'03F62', R)  
(3) Compare register 3 (TM3OC)  
7
6
5
4
3
2
1
0
TM3OC7 TM3OC6 TM3OC5 TM3OC4 TM3OC3 TM3OC2 TM3OC1 TM3OC0  
(at reset: undefined)  
Figure 4-9-3 Compare Register 3 (TM3OC: X'03F73', R/W)  
(4) Binary counter 3 (TM3BC)  
7
6
5
4
3
2
1
0
TM3BC7 TM3BC6 TM3BC5 TM3BC4 TM3BC3 TM3BC2 TM3BC1 TM3BC0  
(at reset: 00000000)  
Figure 4-9-4 Binary Counter 3 (TM3BC: X'03F63', R)  
82  
Timer Function Control Registers  
Chapter 4 Timer Functions  
(5) Compare register 4 (TM4OCL) (lower 8 bits)  
7
6
5
4
3
2
1
0
TM4OCL7 TM4OCL6 TM4OCL5 TM4OCL4 TM4OCL3 TM4OCL2 TM4OCL1 TM4OCL0  
(at reset: undefined)  
Figure 4-9-5 Compare Register 4 (TM4OCL: X'03F74', R/W)  
(6) Compare register 4 (TM4OCH) (upper 8 bits)  
7
6
5
4
3
2
1
0
TM4OCH7TM4OCH6TM4OCH5TM4OCH4TM4OCH3TM4OCH2TM4OCH1 TM4OCH0  
(at reset: undefined)  
Figure 4-9-6 Compare Register 4 (TM4OCH: X'03F75', R/W)  
(7) Binary counter 4 (TM4BCL) (lower 8 bits)  
7
6
5
4
3
2
1
0
TM4BCL7 TM4BCL6 TM4BCL5 TM4BCL4 TM4BCL3 TM4BCL2 TM4BCL1 TM4BCL0  
(at reset: 00000000)  
Figure 4-9-7 Binary Counter 4 (TM4BCL: X'03F64', R)  
(8) Binary counter 4 (TM4BCH) (upper 8 bits)  
7
6
5
4
3
2
1
0
TM4BCH7 TM4BCH6 TM4BCH5 TM4BCH4 TM4BCH3 TM4BCH2TM4BCH1 TM4BCH0  
(at reset: 00000000)  
Figure 4-9-8 Binary Counter 4 (TM4BCH: X'03F65', R)  
Timer Function Control Registers  
83  
Chapter 4 Timer Functions  
(9) Input capture register (TM4ICL) (lower 8 bits)  
7
6
5
4
3
2
1
0
TM4ICL7 TM4ICL6 TM4ICL5 TM4ICL4 TM4ICL3 TM4ICL2 TM4ICL1 TM4ICL0  
(at reset: undefined)  
Figure 4-9-9 Input Capture Register (TM4ICL: X'03F66', R)  
(10) Input capture register (TM4ICH) (upper 8 bits)  
7
6
5
4
3
2
1
0
TM4ICH7 TM4ICH6 TM4ICH5 TM4ICH4 TM4ICH3 TM4ICH2 TM4ICH1 TM4ICH0  
(at reset: undefined)  
Figure 4-9-10 Input Capture Register (TM4ICH: X'03F67', R)  
(11) Compare register 5 (TM5OC)  
7
6
5
4
3
2
1
0
TM5OC7 TM5OC6 TM5OC5 TM5OC4 TM5OC3 TM5OC2 TM5OC1 TM5OC0  
(at reset: undefined)  
Figure 4-9-11 Compare Register 5 (TM5OC: X'03F78', R/W)  
(12) Binary counter 5 (TM5BC)  
7
6
5
4
3
2
1
0
TM5BC7 TM5BC6 TM5BC5 TM5BC4 TM5BC3 TM5BC2 TM5BC1 TM5BC0  
(at reset: 00000000)  
Figure 4-9-12 Binary Counter 5 (TM5BC: X'03F68', R)  
84  
Timer Function Control Registers  
Chapter 4 Timer Functions  
4-9-3 Timer Mode Registers  
Four readable and writable 6-byte timer mode registers. Control timers 2, 3, 4, 5, and  
the time base.  
(1) Timer 2 mode register (TM2MD)  
7
6
–
5
–
4
3
2
1
0
–
(at reset: ---00XXX)  
TM2EN  
TM2PWM TM2CK2 TM2CK1 TM2CK0  
TM2MD  
Clock source selection  
TM2CK2 TM2CK1 TM2CK0  
0
fs  
X
0
0
1
1
0
1
0
1
fs/4  
fx *  
TM2IO input  
Synchronous fx *  
Synchronous TM2IO input  
1
1
* 48QFH package only  
TM2 operation mode selection  
TM2PWM  
0
1
Normal timer operation  
PWM operation  
TM2EN  
TM2 count control  
0
1
Halt the count  
Operate the count  
Figure 4-9-13 Timer 2 Mode Register (TM2MD: X'03F82', R/W)  
Timer Function Control Registers  
85  
Chapter 4 Timer Functions  
(2) Timer 3 mode register (TM3MD)  
7
6
–
5
–
4
3
2
1
0
(at reset: ---00XXX)  
–
TM3EN  
TM3PWM  
TM3CK2  
TM3CK1  
TM3CK0  
TM3MD  
Clock source selection  
TM3CK2  
TM3CK1  
TM3CK0  
0
1
0
1
x
1
fosc  
0
fs/4  
0
fs/16  
1
TM3IO input  
Cascade connection with timer 2  
Synchronous TM3IO input  
0
1
1
P13 output selection  
during TM2 PWM operation  
TM3PWM  
0
1
Timer 3 output  
Timer 2 PWM output  
TM3 count control  
TM3EN  
0
1
Halt the count  
Operate the count  
Figure 4-9-14 Timer 3 Mode Register (TM3MD: X'03F83', R/W)  
86  
Timer Function Control Registers  
Chapter 4 Timer Functions  
(3) Timer 4 mode register (TM4MD)  
7
–
6
5
4
3
2
1
0
(at reset: -0000XXX)  
TM4EN  
TM4PWM  
T4ICTS1  
T4ICTS0  
TM4CK2  
TM4CK1  
TM4CK0  
TM4MD  
Clock source selection  
TM4CK2  
TM4CK1  
TM4CK0  
0
1
0
fosc  
fs/4  
0
0
1
fs/16  
1
1
1
1
TM4IO input  
Synchronous TM4IO input  
TM4 input capture trigger selection  
T4ICTS1  
T4ICTS0  
Disable input capture operation  
0
1
0
1
0
IRQ0  
IRQ1  
IRQ2  
1
TM4PWM  
TM4 operation mode selection  
0
1
16-bit timer operation  
PWM operation  
TM4 count control  
TM4EN  
0
1
Halt the count  
Operate the count  
Figure 4-9-15 Timer 4 Mode Register (TM4MD: X'03F84', R/W)  
Timer Function Control Registers  
87  
Chapter 4 Timer Functions  
(4) Timer 5 mode register (TM5MD)  
7
6
5
4
3
2
1
0
(at reset: 0XXXXXX0)  
TM5MD  
TM5CLRS TM5IR2  
TM5IR1  
TM5IR0  
TM5CK3  
TM5CK2  
TM5CK1  
TM5CK0  
Time base timer  
clock source selection  
TM5CK0  
0
1
fosc  
(Use Prohibited) fx *  
* 48QFH package only  
Timer 5 clock source selection  
TM5CK3 TM5CK2 TM5CK1  
0
fosc  
X
0
1
0
1
1
fs/4  
0
1
0
1
(Use Prohibited)  
Output of time base timer  
(Use Prohibited)  
Synchronous time base timer output  
Time base timer  
interrupt period selection  
TM5IR2  
TM5IR1 TM5IR0  
0
1/27 of the clock source  
1/28 of the clock source  
1/29 of the clock source  
1/210 of the clock source  
1/213 of the clock source  
0
1
0
1
0
1
1
x
x
Binary counter 5  
clear selection flag  
TM5CLRS  
Enable initialization of  
TM5BC during a write to TM5OC  
0
1
Disable initialization of  
TM5BC during a write to TM5OC  
∗If TM5CLRS=0, TM5IRQ is disabled.  
Figure 4-9-16 Timer 5 Mode Register (TM5MD: X'03F88', R/W)  
88  
Timer Function Control Registers  
Chapter 4 Timer Functions  
4-9-4 Timer Control Registers  
(1) Watchdog timer control register (WDCTR)  
7
–
6
–
5
–
4
–
3
–
2
–
1
–
0
(at reset: -------0)  
WDEN  
WDCTR  
WDEN  
Watchdog timer enable  
0
1
Clear watchdog timer/disable operation  
Enable WDT timer  
Figure 4-9-17 Watchdog Timer Control Register (WDCTR: X'03F02', R/W)  
(2) Oscillation stabilization wait control register (DLYCTR)  
7
6
5
4
–
3
–
2
–
1
0
(at reset: 0XX---00)  
BUZOE BUZCK1 BUZCK0  
DLYS1 DLYS0  
DLYCTR  
Oscillation stabilization  
wait period setting  
DLYS1 DLYS0  
1/214 of the system clock (fs)  
1/210 of the system clock (fs)  
1/26 of the system clock (fs)  
Disable use  
0
0
1
1
1
0
1
∗After reset is released, the oscillation  
stabilization wait period is fixed at 1/215.  
Buzzer output  
frequency selection  
BUZCK1 BUZCK0  
1/212 of the system clock (fs)  
1/211 of the system clock (fs)  
1/210 of the system clock (fs)  
1/29 of the system clock (fs)  
0
1
0
1
0
1
P06 output selection  
BUZOE  
0
1
P06 port output  
P06 buzzer output  
Figure 4-9-18 Oscillation Stabilization Wait Counter Control Register  
(DLYCTR: X'03F03', R/W)  
Timer Function Control Registers  
89  
Chapter 4 Timer Functions  
(3) Remote control carrier output control register (RMCTR)  
7
–
6
–
5
–
4
–
3
2
–
1
0
–
(at reset: ---00XX0)  
RMOEN  
RMDTY0  
RMCTR  
Must be set to "0."  
RMDTY0  
Remote control carrier  
output duty selection  
0
1
1/2 duty  
1/3 duty  
Must be set to "0."  
Enable remote control  
carrier output  
RMOEN  
0
1
Output low level  
Output remote control carrier  
Must be set to "0."  
Figure 4-9-19 Remote Control Carrier Control Register  
(RMCTR: X'03F89', R/W)  
90  
Timer Function Control Registers  
Chapter 5  
Serial Functions  
5
91  
Chapter 5 Serial Functions  
5-1 Overview  
The MN101C117 contains a serial interface that can operate in synchronous  
and simple UART modes.  
An overview of serial functions is shown below.  
Table 5-1-1 Overview of Serial Functions  
Serial 0  
Interrupt  
SC0ICR  
Synchronous  
Simple UART  
fs/2  
fs/4  
Clock selection  
fs/16  
BC3X1/2  
External  
1/8 period of clock  
92  
Overview  
Chapter 5 Serial Functions  
Figure 5-1-1 Serial 0 Block Diagram  
Overview  
93  
Chapter 5 Serial Functions  
5-2 Synchronous Serial Interface  
5-2-1 Overview  
A serial interface begins operation when data is written to the shift buffer. A bit  
counter is incremented at each 1-bit transfer. The transfer is complete when the  
counter overflows.  
Bit transfers of an arbitrary 1 to 8 bits can be performed. The transfer bit count must  
be set before performing the transfer.  
5-2-2 Setup and Operation  
■ Transmission  
(1)  
(2)  
Select the synchronous serial interface by setting the SC0CMD flag of the  
serial interface 0 control register (SC0CTR) to "0."  
Select the transfer bit count with the SC0LNG2 to 0 flags of the serial  
interface 0 mode register 0 (SC0MD0). The transfer bit count can be  
set as 1 to 8 bits.  
(3)  
(4)  
(5)  
(6)  
Specify whether the start condition is enabled or disabled with the SC0STE  
flag of the SC0MD0 register.  
Specify the first bit to be transferred (MSB first or LSB first) with the  
SC0DIR flag of the SC0MD0 register.  
Select the valid edge of the clock signal with the SC0CE1 to 0 flags of the  
SC0MD0 register.  
[☞ Section 5-2-3, "Serial  
Interface Transfer Timing"]  
When the clock source is an internal clock:  
• Select the clock source with the SC0CK1 to 0 flags of serial interface 0  
mode register 1 (SC0MD1).  
• Set the SC0CKM flag of the SC0MD1 register specify whether or not the  
clock source frequency will be divided by 8.  
• Select serial clock operation by setting the SC0SBTS flag of the serial  
interface 0 mode register 3 (SC0MD3) to "1."  
• Set the SC0SBTM flag of the SC0MD3 register.  
• Set bit 0 of the port 0 direction control register (P0DIR) to the output  
mode.  
• Set bit 0 of the port 0 pull-up resistor control register (P0PLU).  
94  
Synchronous Serial Interface  
Chapter 5 Serial Functions  
When the serial port is enabled  
and the SC0CE1 to 0 flags of  
the SC0MD0 register are  
changed, the transfer bit count  
in the SC0LNG2 to 0 flags of  
the SC0MD0 register may be  
incremented.  
When the clock source is an external clock (SBT0 pin input):  
•
•
•
Set the SC0SBTM flag of the SC0MD3 register.  
Set bit 2 of the P0DIR register to input mode.  
Set the P0PLU register, if necessary.  
(7)  
(8)  
(9)  
Select the SC0SBOM flag of the SC0MD3 register.  
Select the SC0IOM flag of the SC0MD3 register.  
Select serial communication by setting the SC0SBOS flag of the  
SC0MD3 register to "1."  
Enabling the start condition  
drives the SBO0 pin high for a  
fixed time interval (1/2 the  
clock source cycle) after the  
transmission is completed. If  
the start condition is disabled,  
the SBO0 pin will remain at the  
value of the of the last data bit.  
(10) Set transmit data to serial interface 0 transmit/receive shift register  
(SC0TRB). This will start the serial transmission.  
(11) When serial transmission begins, the SC0BSY flag of the SC0CTR register  
is set to "1," indicating that a serial transfer is in progress.  
(12) When the serial transmission has completed, the SC0BSY flag of the  
SC0CTR register is cleared to "0" and the SC0 transfer complete interrupt  
request flag is set to "1." The SC0TRI flag of SC0MD1 register 1 is cleared  
to "0."  
If the SC0IOM flag of the  
SC0MD3 register is set for a  
pin connection, the SBI0 pin  
can be used as a port. The  
SBO0 pin receives data during  
the input mode and transmits  
data during the output mode.  
After the transfer is complete, the transfer bit count in the  
SC0LNG2 to 0 flags of the SC0MD0 register will be changed.  
Except in an 8-bit transfer, reset the transfer bit count at the  
time of the next transmission.  
The SC0LNG2 to 0 flags  
change at the opposite edge of  
the transmit data output edge.  
When switching from transmission to reception, set the  
SC0SBOS flag of the SC0MD3 register to "0" and then set  
the SC0SBIS flag to "1." Do not change both of these flags at  
the same time.  
Serial interface  
0
begins  
The SC0SBTS flag of the SC0MD3 register must be set to "1"  
before the SC0SBOS flag of the SC0MD3 register is set to  
"1."  
operation when the SC0SBOS  
flag or the SC0SBIS flag is set  
to "1." Set the SC0SBOS flag  
or the SC0SBIS flag after all  
conditions have been set.  
Synchronous Serial Interface  
95  
Chapter 5 Serial Functions  
SBT  
SBO  
Clock  
ts  
Start condition  
enabled  
SBO  
Start condition  
disabled  
Interrupt  
SC0BSY  
0
1
2
3
4
5
6
7
0
SC0LNG2 to 0  
Figure 5-2-1 Synchronous Serial Interface Transmission Timing (falling edge)  
Clock  
SBT  
SBO  
Start condition  
enabled  
SBO  
Start condition  
disabled  
Interrupt  
SC0BSY  
0
1
2
3
4
5
6
7
0
SC0LNG2 to 0  
Figure 5-2-2 Synchronous Serial Interface Transmission Timing (rising edge)  
96  
Synchronous Serial Interface  
Chapter 5 Serial Functions  
■ Reception  
When the serial port is enabled  
and the SC0CE1 to 0 flags of  
the SC0MD0 register are  
changed, the transfer bit count  
in the SC0LNG2 to 0 flags of  
the SC0MD0 register may by  
incremented.  
(1)  
(2)  
Select the synchronous serial interface by setting the SC0CMD flag of the  
serial interface 0 control register (SC0CTR) to "0."  
Select the transfer bit count with the SC0LNG2 to 0 flags of the serial  
interface 0 mode register 0 (SC0MD0). The transfer bit count can be set as  
1 to 8 bits.  
(3)  
(4)  
(5)  
(6)  
Specify whether the start condition is enabled or disabled with the SC0STE  
flag of the SC0MD0 register.  
Specify the first bit to be transferred (MSB first or LSB first) with the  
SC0DIR flag of the SC0MD0 register.  
Select the valid edge of the clock signal with the SC0CE1 to 0 flags of the  
SC0MD0 register.  
[☞ Section 5-2-3, "Serial  
When the clock source is an internal clock:  
Interface Transfer Timing"]  
•
•
•
Select the clock source with the SC0CK1 to 0 flags of serial interface 0  
mode register 1 (SC0MD1).  
If the start condition is enabled,  
the SC0LNG2 to 0 flags of the  
SC0MD0 register will be  
cleared when the start  
condition is received. In this  
case, the receive bit count is  
fixed at 8 bits.  
Set the SC0CKM flag of the SC0MD1 register to specify whether or not  
the clock source frequency will be divided by 8.  
Select serial clock pin operation by setting the SC0SBTS flag of the  
serial interface 0 mode register 3 (SC0MD3) to "1."  
Set the SC0SBTM flag of the SC0MD3 register.  
•
•
Set bit 2 of the port 0 direction control register (P0DIR) to the output  
mode (P02/SBT0 output mode).  
The SC0SBTS flag of the  
SC0MD3 register must be set  
to "1" before setting the  
SC0SBIS flag of the SC0MD3  
register to "1."  
•
If necessary, set bit 2 of the port 0 pull-up resistor control register  
(P0PLU) to add the pull-up resistor.  
When the clock source is an external clock (SBT0 pin input):  
•
•
Set bit 2 of the P0DIR register to the input mode.  
If necessary, set bit 2 of the P0PLU register.  
(7)  
(8)  
Select the SC0IOM flag of the SC0MD3 register.  
If the internal clock is selected  
as the clock source, after  
setting the SC0SBIS flag of the  
SC0MD3 register to "1," write  
dummy data to the SC0TRB  
register. If there is to be  
another reception, write  
dummy data again to the  
SC0TRB register.  
Select serial communication by setting the SC0SBIS flag of the SC0MD3  
register to "1." (Reception data wait.)  
(9)  
When the serial reception begins, the SC0BSY flag of the serial interface 0  
control register (SC0CTR) is set to "1," indicating that a serial transfer is in  
progress.  
(10) When the serial reception is complete, the SC0BSY flag of the SC0CTR  
register is cleared to "0" and the SC0 transfer complete interrupt request flag  
is set to "1." The SC0TRI flag of the SC0MD1 register is set to "1."  
The SC0LNG2 to 0 flags  
change at the opposite edge of  
the transmit data output edge.  
After the transfer is complete, the transfer bit count in the  
SC0LNG2 to 0 flags of the SC0MD0 register will be  
changed. Except in an 8-bit transfer count, reset the  
transfer bit count at the time of the next reception.  
Serial interface  
0
begins  
operation when the SC0SBOS  
flag or the SC0SBIS flag is set  
to "1." Set the SC0SBOS flag  
or the SC0SBIS flag after all  
conditions have been set.  
When switching from reception to transmission, set the  
SC0SBIS flag of the SC0MD3 register to "0" and then set  
the SC0SBOS flag to "1." Do not change both of these  
flags at the same time.  
Synchronous Serial Interface  
97  
Chapter 5 Serial Functions  
Clock  
Start condition  
enabled  
Start condition  
disabled  
Interrupt  
SC0BSY start  
condition  
enabled  
SC0BSY start  
condition  
disabled  
0
1
2
3
4
5
6
7
0
SC0LNG2 to 0  
Figure 5-2-3 Synchronous Serial Interface Reception Timing  
(reception at rising edge)  
Clock  
Start condition  
enabled  
Start condition  
disabled  
Interrupt  
SC0BSY start  
condition  
enabled  
SC0BSY start  
condition  
disabled  
0
1
2
3
4
5
6
7
0
SC0LNG2 to 0  
Figure 5-2-4 Synchronous Serial Interface Reception Timing  
(reception at falling edge)  
98  
Synchronous Serial Interface  
Chapter 5 Serial Functions  
5-2-3 Serial Interface Transfer Timing  
Serial interface 0 uses the SC0CE0 and SC0CE1 flags of serial interface 0 mode  
register 0 (SC0MD0), to control the edge at which transmission data is output and  
the edge at which reception data is input.  
During transmission, when the SCnCE1 flag is "0," data output is synchronized to  
the falling edge of the clock.  
During reception, when the SCnCE0 flag is "0," data reception is synchronized to  
the opposite polarity edge of the transmit data edge. When the SCnCE0 flag is "1,"  
data reception is synchronized to the same polarity edge as the transmit data edge.  
Table 5-2-1 Serial Data Input Edge and Output Edge (serial interface 0)  
Receive Data Input Edge  
Transmit Data Output Edge  
SC0CE0 SC0CE1  
0
0
0
1
1
0
1
1
Synchronous Serial Interface  
99  
Chapter 5 Serial Functions  
When serial interface 0 is used for simultaneous transmission and reception, set the  
SCnCE0 and SCnCE1 flags of the SCnMD0 register to "00" or "01", so that the  
reception data input edge is opposite in polarity to the transmit data output edge.  
Also, the polarity of the reception data input edge is opposite polarity of the  
transmit data output edge of the other device.  
SBT0  
Data is input in synchronization with the rising edge of the clock.  
SBI0  
Data is output in synchronization with the falling edge of the clock.  
SBO0  
Figure 5-2-5 Synchronous Serial Transmit/Receive Timing  
(data is received at the rising edge and transmitted at the falling edge)  
SBT0  
Data is input in synchronization with the falling edge of the clock.  
SBI0  
Data is output in synchronization with the rising edge of the clock.  
SBO0  
Figure 5-2-6 Synchronous Serial Transmit/Receive Timing  
(data is received at the falling edge and transmitted at the rising edge)  
100 Synchronous Serial Interface  
Chapter 5 Serial Functions  
5-3 Half-duplex UART Serial Interface  
5-3-1 Overview  
Setup and operation of UART transmission and reception are described  
below.  
5-3-2 Setup and Operation  
■ Transmission  
(1)  
(2)  
(3)  
(4)  
(5)  
(6)  
Select UART by setting the SC0CMD flag of the serial interface 0 control  
register (SC0CTR) to "1."  
When the serial port is enabled  
and the SC0CE1 to 0 flags of  
the SC0MD0 register are  
toggled, the transfer bit count  
may change.  
Specify the first bit to be transferred (MSB first or LSB first) with the  
SC0DIR flag of the serial interface 0 mode register 0 (SC0MD0).  
Select the valid edge of the clock signal with the SC0CE1 to 0 flags of the  
SC0MD0 register.  
Select the clock source with the SC0CK1 to 0 flags of serial interface 0  
mode register 1 (SC0MD1).  
Set the SC0CKM flags of the SC0MD1 register to "1" to divide the clock  
source frequency by 8.  
The TXD pin goes to a high  
level after transmission is  
complete.  
Set the SC0NPE flag of the serial interface 0 mode register 2 (SC0MD2) to  
enable or disable parity.  
Setting the SC0FM flag of the SC0MD2 register to frame  
mode automatically sets the SC0LNG2 to 0 flags of the  
SC0MD0 register.  
After the transfer is complete, the SC0LNG2 to 0 flags of the  
SC0MD0 register are automatically set with the transfer bit  
count.  
Set the SC0CKM flag of the SC0MD1 register to "1" to divide  
the clock source frequency by 8.  
Half-duplex UART Serial Interface 101  
Chapter 5 Serial Functions  
(7)  
(8)  
(9)  
If parity is enabled by the SC0NPE flag of the SC0MD2 register, set the  
SC0PM1~0 flags of the SC0MD2 register to specify the added parity bit.  
Set the SC0FM1 to 0 flags of the SC0MD2 register to specify the frame  
mode.  
Set the SC0BRKE flag of the SC0MD2 register to control break status  
transmission.  
Serial interface  
0
begins  
(10) Select the SC0SBOM flag of the SC0MD3 register.  
operation when the SC0SBOS  
flag or the SC0SBIS flag is set  
to "1." Set the SC0SBOS flag  
or the SC0SBIS flag after all  
conditions have been set.  
(11) Select the SC0IOM flag of the SC0MD3 register.  
(12) Set bit 0 of the port 0 direction control register (P0DIR) to the output mode.  
(13) Select serial communication by setting the SC0SBOS flag of the SC0MD3  
register to "1."  
(14) Set transmit data to serial interface 0 transmit/receive shift register  
(SC0TRB). This will start the serial transmission.  
(15) When the serial transmission begins, the SC0BSY flag of the SC0CTR  
register is set to "1," indicating that a serial transfer is in progress.  
(16) When the serial transmission is complete, the SC0BSY flag of the SC0CTR  
register is cleared to "0" and the SC0 transfer complete interrupt request flag  
is set to "1." The SC0TRI flag of the SC0MD1 register is cleared to "0."  
TXD  
Parity Stop Stop  
Parity enabled  
bit  
bit  
bit  
TXD  
Stop  
bit  
Stop  
bit  
Parity disabled  
Interrupt  
Parity enabled  
Interrupt  
Parity disabled  
SC0BSY  
Parity enabled  
SC0BSY  
Parity disabled  
Figure 5-3-1 UART Transmission Timing  
102 Half-duplex UART Serial Interface  
Chapter 5 Serial Functions  
When the serial port is enabled  
and the SC0CE1 to 0 flags of  
the SC0MD0 register are  
toggled, the transfer bit count  
may change.  
■ Reception  
Select UART by setting the SC0CMD flag of the serial interface 0 control  
(1)  
(2)  
(3)  
(4)  
(5)  
(6)  
(7)  
(8)  
(9)  
register (SC0CTR) to "1."  
Specify the first bit to be transferred (MSB first or LSB first) with the  
SC0DIR flag of the serial interface 0 mode register 0 (SC0MD0).  
Select the valid edge of the clock signal with the SC0CE1 to 0 flags of the  
SC0MD0 register.  
The TXD pin goes to a high  
level after reception is  
complete.  
Select the clock source with the SC0CK1~0 flags of serial interface 0 mode  
register 1 (SC0MD1).  
Set the SC0CKM flags of the SC0MD1 register to "1" to divide the clock  
source frequency by 8.  
Set the SC0NPE flag of the serial interface 0 mode register 2 (SC0MD2) to  
enable or disable parity.  
If parity is enabled by the SC0NPE flag of the SC0MD2 register, set the  
SC0PM1 to 0 flags of the SC0MD2 register to specify the added parity bit.  
Set the SC0FM1 to 0 flags of the SC0MD2 register to specify the frame  
mode.  
Select the SC0IOM flag of the SC0MD3 register.  
(10) When the SC0IOM flag of the SC0MD3 register is specified that the pin is  
independent, set bit 1 of the port 0 direction control register (P0DIR) to the  
input mode.  
(11) Set bit 0 of the port 0 pull-up resistor control register (P0PLU).  
(12) Select serial communication by setting the SC0SBIS flag of the SC0MD3  
register to "1."  
Serial interface  
0
begins  
operation when the SC0SBOS  
or SC0SBIS flag is set to "1."  
Set the SC0SBOS or SC0SBIS  
flag after all conditions have  
been set.  
(13) When the serial transmission begins, the SC0BSY flag of the SC0CTR  
register is set to "1," indicating that a serial transfer is in progress.  
(14) When the serial transmission is complete, the SC0BSY flag of the SC0CTR  
register is cleared to "0" and the SC0 transfer complete interrupt request flag  
is set to "1." The SC0TRI flag of the SC0MD1 register is cleared to "1."  
One machine cycle after the  
stop bit has been received, the  
start condition will no longer be  
accepted.  
Therefore,  
Setting the SC0FM flag of the SC0MD2 register to frame  
mode automatically sets the SC0LNG2 to 0 flags of the  
SC0MD0 register.  
consecutive reception must be  
performed carefully.  
After the transfer is complete, the SC0LNG2 to 0 flags of the  
SC0MD0 register are automatically set with the transfer bit  
count.  
Half-duplex UART Serial Interface 103  
Chapter 5 Serial Functions  
RXD  
Parity  
bit  
Stop Stop  
bit bit  
Parity enabled  
RXD  
Stop Stop  
bit bit  
Parity disabled  
Interrupt  
Parity enabled  
Interrupt  
Parity disabled  
SC0BSY  
Parity enabled  
SC0BSY  
Parity disabled  
Figure 5-3-2 UART Reception Timing  
104 Half-duplex UART Serial Interface  
Chapter 5 Serial Functions  
5-3-3 How to Use the Baud Rate Timer  
Refer to the following when using the baud rate timer to set the UART transfer  
speed.  
(1) Specifying the timer clock source  
The clock source is specified by the TM3CKS3 to 1 flags of the timer 3  
mode register (TM3MD).  
(2) Setting the compare register  
The compare register value is set in the timer 3 compare register (TM3OC).  
This set value is computed according to the following formula:  
overflow period = (compare register set value + 1) × timer clock period  
baud rate = 1/(overflow period × 2 × 8)  
↑ SC0MD1(SC0CKM)  
compare register set value = timer clock frequency/(baud rate × 2 × 8) – 1  
Table 5-3-1 UART Transfer Rate  
Set the values from this table  
(minus 1) in the compare  
register.  
Transfer Speed  
fosc  
(MHz)  
300  
1200  
2400  
4800  
9600  
19200  
(bps)  
Set  
Calculated  
Value  
Set  
Value  
Calculated  
Value  
Set  
Value  
Calculated  
Value  
Set  
Value  
Calculated  
Value  
Set  
Value  
Calculated  
Value  
Set  
Value  
Calculated  
Value  
Value  
fosc  
fs/4  
fs/16  
fosc  
fs/4  
fs/16  
fosc  
fs/4  
fs/16  
fosc  
fs/4  
fs/16  
fosc  
fs/4  
fs/16  
fosc  
fs/4  
fs/16 104 300  
fosc  
fs/4  
—
—
208 1202 104 2403 52 4807 26 9615 13 19230  
4.0  
4.19  
8.0  
104 300  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
218 1201 109 2402 55 4761 27 9699  
109 300  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
208 2404 104 4807 52 9615 26 19230  
208 300 52 1201  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
218 2403 109 4805 55 9523 27 19398  
8.38  
12.0  
16.0  
16.76  
20.0  
218 300 55 1190  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
156 4808 78 9615 39 19230  
78 1202 39 2403  
—
—
—
—
—
—
—
—
—
—
—
—
78 300  
—
—
—
—
—
—
—
—
—
—
—
—
208 4808 104 9615 52 19230  
104 1202 52 2404  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
218 4805 109 9610 55 19045  
109 1201 55 2381  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
fs/16 109 300  
fosc  
fs/4  
—
—
—
—
—
—
—
—
—
—
—
—
130 9615 65 19231  
130 1202 65 2404 33 4735  
—
—
—
—
—
—
—
—
fs/16 130 300  
—
—
—
—
—
—
Example:  
The timer 3 clock source is fs/4 (fosc = 8MHz) and a baud rate of 300 bps is  
desired.  
Since fs=fosc/2,  
6
compare register set value = (8 × 10 /2/4)/(300 × 2 × 8) – 1  
=207  
= X'CF'  
Half-duplex UART Serial Interface 105  
Chapter 5 Serial Functions  
5-4 Serial Interface Control Registers  
5-4-1 Overview  
7 registers control the serial interface. See table 5-4-1.  
Table 5-4-1 Serial Interface Registers  
Name  
Address  
X'03F50'  
X'03F51'  
X'03F52'  
X'03F53'  
X'03F54'  
X'03F55'  
X'03F56'  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
W
Function  
SC0MD0  
SC0MD1  
SC0MD2  
SC0MD3  
SC0CTR  
SC0TRB  
SC0RXB  
Serial interface 0 mode register 0  
Serial interface 0 mode register 1  
Serial interface 0 mode register 2  
Serial interface 0 mode register 3  
Serial interface 0 control register  
Serial interface 0 transmit/receive shift register  
Serial interface 0 receive data buffer  
R
106 Serial Interface Control Registers  
Chapter 5 Serial Functions  
5-4-2 Transmit/Receive Shift Registers, Receive Data Buffer  
(1) Serial interface 0 transmit/receive shift register (SC0TRB)  
This 8-bit, writable register shifts the transmission data and the reception data. The  
direction of transfer can be specified as LSB first or MSB first.  
7
6
5
4
3
2
1
0
SC0TRB  
(at reset: undefined)  
SC0TRB7 SC0TRB6 SC0TRB5 SC0TRB4 SC0TRB3 SC0TRB2 SC0TRB1 SC0TRB0  
Figure 5-4-1 Serial Interface 0 Transmit/Receive Shift Register  
(SC0TRB: X'03F55', W)  
(2) Serial interface 0 receive data buffer (SC0RXB)  
7
6
5
4
3
2
1
0
SC0RXB  
(at reset: undefined)  
SC0RXB7 SC0RXB6 SC0RXB5 SC0RXB4 SC0RXB3 SC0RXB2 SC0RXB1 SC0RXB0  
Figure 5-4-2 Serial Interface 0 Receive Data Buffer  
(SC0RXB: X'03F56', R)  
Serial Interface Control Registers 107  
Chapter 5 Serial Functions  
5-4-3 Serial Interface Mode Registers  
(1) Serial interface 0 mode register (SC0MD0)  
7
6
5
4
3
2
1
0
SC0MD0  
–
(at reset: -00XX000)  
SC0CE0 SC0CE1 SC0DIR SC0STE SC0LNG2SC0LNG1SC0LNG0  
Transfer bit count  
SC0LNG2 SC0LNG1 SC0LNG0  
0
8 bit  
7 bit  
6 bit  
5 bit  
0
1
0
0
1
1
0
4 bit  
3 bit  
2 bit  
1 bit  
0
1
1
0
1
1
Selection of synchronous  
serial start condition  
SC0STE  
0
1
Disable start condition  
Enable start condition  
SC0DIR  
First bit to be transferred  
0
1
MSB first  
LSB first  
Receive data  
input edge  
Transmit data  
output edge  
SC0CE SC0CE1  
0
0
1
0
1
Rising  
Falling  
Rising  
Falling  
Rising  
0
0
1
1
Falling  
Falling  
Rising  
Figure 5-4-3 Serial Interface 0 Mode Register 0 (SC0MD0: X'03F50', R/W)  
108 Serial Interface Control Registers  
Chapter 5 Serial Functions  
(2) Serial interface 0 mode register 1 (SC0MD1)  
7
–
6
5
4
3
2
1
0
(at reset: --X00000)  
SC0MD1  
–
SC0CKM SC0CK1  
SC0CK0 SC0BRKF SC0ERESC0TRI  
Transmit/receive  
interrupt request flag  
SC0TRI  
0
1
Transmit interrupt request  
Receive interrupt request  
SC0ERE  
Error monitor  
0
1
No error  
Error  
Break status  
receive monitor  
SC0BRKF  
0
1
Data  
Break  
Clock source  
fs/2  
SC0CK1  
SC0CK0  
0
0
1
1
0
1
0
1
fs/4  
fs/16  
BC3×1/2(1/2 of timer 3 overflow)  
SC0CKM  
Divide clock frequency by 8  
0
1
Do not divide by 8  
Divide by 8  
An external clock can be selected as the clock  
source by setting the SBT0 pin to the input mode.  
Figure 5-4-4 Serial Interface 0 Mode Register 1 (SC0MD1: X'03F51', R/W)  
Serial Interface Control Registers 109  
Chapter 5 Serial Functions  
(3) Serial interface 0 mode register 2 (SC0MD2)  
7
–
6
–
5
4
3
2
1
0
(at reset: --000XXX)  
SC0MD2  
SC0BRKE SC0FM1 SC0FM0 SC0PM1 SC0PM0 SC0NPE  
SC0NPE  
Parity enable  
Parity enabled  
Parity disabled  
0
1
Added bit specification  
SC0PM1 SC0PM0  
Transmission  
Reception  
Check for 0  
Normally add 0  
Normally add 1  
Add odd parity  
Add even parity  
0
0
1
Check for 1  
0
Check for odd parity  
Check for even parity  
1
1
Frame mode specification  
SC0FM1 SC0FM0  
7 data bits + 1 stop bit  
7 data bits + 2 stop bits  
8 data bits + 1 stop bits  
8 data bits + 2 stop bits  
0
0
1
0
1
1
SC0BRKE  
Break status transmit control  
Data  
0
1
Break  
Figure 5-4-5 Serial Interface 0 Mode Register 2 (SC0MD2: X'03F52', R/W)  
110 Serial Interface Control Registers  
Chapter 5 Serial Functions  
(4) Serial interface 0 mode register 3 (SC0MD3)  
7
–
6
–
5
4
3
2
1
0
(at reset: --000000)  
SC0MD3  
SC0IOM SC0SBOM SC0SBTM SC0SBOS SC0SBIS SC0SBTS  
SC0SBTS  
SBT0 pin function selection  
Port  
0
1
Serial clock pin  
SC0SBIS  
SBI0 input control  
"1" input  
0
1
Serial input  
SC0SBOS  
SBO0 pin function selection  
Port  
0
1
Serial communication  
SC0SBTM  
SBT0 pin configuration selection  
Push-pull output  
0
1
N-channel open-drain output  
SC0SBOM  
SBO0 pin configuration selection  
Push-pull output  
0
1
N-channel open-drain output  
SC0IOM  
SBI0/SBO0 pin connection  
Unconnected  
Connected  
0
1
Figure 5-4-6 Serial Interface 0 Mode Register 3 (SC0MD3: X'03F53', R/W)  
Serial Interface Control Registers 111  
Chapter 5 Serial Functions  
5-4-4 Serial Interface Control Register  
(1) Serial interface 0 control register (SC0CTR)  
7
6
5
4
–
3
2
1
0
–
(at reset: 00XX000X)  
SC0CTR  
SC0BSY SC0CMD  
–
SC0FEF SC0PEK SC0ORE  
SC0ORE  
Overrun error detection  
0
1
No Error  
Error  
SC0PEK  
Parity error detection  
0
1
No Error  
Error  
SC0FEF  
Framing error detection  
0
1
No Error  
Error  
Synchronous serial/  
UART selection  
SC0CMD  
0
1
Synchronous serial  
UART  
SC0BSY  
Serial bus status  
0
1
Other use  
Serial transmission in progress  
Figure 5-4-7 Serial Interface 0 Control Register (SC0CTR: X'03F54', R)  
(R/W available with SC0CMD only)  
112 Serial Interface Control Registers  
A/D Conversion  
Functions  
Chapter 6  
6
113  
Chapter 6 A/D Conversion Functions  
6-1 Overview  
The MN101C117 has an internal A/D converter with 10-bit resolution. A  
sample-and-hold circuit is contained on-chip and software can switch the  
analog input between channels 0 to 7 (AN0 to AN7).  
When the A/D converter is stopped, power consumption can be reduced by  
turning off the internal ladder resistors.  
ANCTR1  
0
–
–
–
–
–
–
–
ANBUF0  
ANBUF1  
0
0
ANBUF10  
ANBUF11  
ANBUF12  
ANBUF13  
ANBUF14  
ANBUF15  
ANBUF16  
ANBUF17  
–
–
–
–
–
–
ANCTR0  
ANCHS0  
0
A/D conversion  
control  
ANCHS1  
ANCHS2  
ANLADE  
ANCK0  
ANST  
7
ANBUF06  
ANBUF07  
7
7
ANCK1  
ANSH0  
ANSH1  
7
3
VDD  
AN0  
AN1  
AN2  
AN3  
AN4  
AN5  
AN6  
AN7  
2
2
Upper 8 bits of A/D  
conversion data  
10-bit  
A/D comparator  
MUX  
Sample & hold  
Lower 2 bits of A/D conversion data  
VSS  
fs/2  
fs/4  
1/2  
MUX  
fs/8  
MUX  
1/6  
fx x 2  
1/18  
Figure 6-1-1 A/D Converter Block Diagram  
114 Overview  
Chapter 6 A/D Conversion Functions  
6-2 A/D Conversion  
The procedures for operating the A/D conversion circuit are listed below.  
(1) Set the ANCHS2 to ANCHS0 flags of A/D control register 0 (ANCTR0) to specify one  
of pins AN7 to AN0 (PA7 to PA0) as the analog input.  
(2) Set the ANCK1 and ANCK0 flags of A/D control register 0 to select the A/D  
conversion clock. Make this setting such that the period of the conversion clock  
(TAD), which is based on the oscillator, is greater than 800ns.  
(3) With the ANSH1 and ANSH0 flags of A/D control register 0, set the sample-and-hold  
time. Select a value for the sample and hold time that is suitable for the analog input  
impedance.  
(4) Set the ANLADE flag of A/D control register 0 to "1" so that current flows through  
the ladder resistors and the A/D converter is on standby.  
Start the A/D conversion after the  
current flowing through the ladder  
resistors stabilizes. The time  
constant calculated time from the  
ladder resistance (max. 80 kΩ)  
and the external bypass capacitor  
connected between Vdd and Vss  
should be used as the criteria for  
the wait time.  
Note: Steps 1 to 4 above may performed all at the same time.  
(5) Set the ANST flag of A/D control register 1 (ANCTR1) to "1" to start the A/D  
conversion.  
(6) After the sample-and-hold time set in step 3, the sampled A/D conversion data is  
sequentially compared to determine its value beginning with the MSB.  
(7) When the A/D conversion is complete, the ANST bit is cleared to "0" and conversion  
results are stored in A/D buffers (ANBUF0, 1). At the same time, an A/D complete  
interrupt request (ADIRQ) is generated.  
TAD  
1~2  
3
4
12  
ANST  
A/D conversion start  
A/D conversion complete  
TS  
Sampling  
Hold  
Bit 9  
Bit 8  
Bit 0  
comparison comparison  
comparison  
Determine  
bit 0 value  
Determine Determine  
bit 9 value bit 8 value  
Determine  
bit 1 value  
A/D interrupt  
Figure 6-2-1 A/D Conversion Timing  
A/D Conversion 115  
Chapter 6 A/D Conversion Functions  
The following items must be implemented to maintain the accuracy of the  
A/D converter:  
∗1  
1. Use a maximum input pin impedance, R, of 500kΩ with an external  
capacitor, C, that is minimum 1,000pF and maximum 1µF∗1.  
2. Take the RC time into consideration when setting the A/D conversion  
interval.  
3. Changing the output level of the microcomputer or switching peripheral  
circuitry on or off when the A/D converter is in use may cause the  
analog input pin or current pin to fluctuate resulting in a loss of  
precision. During setup and evaluation, verify the waveform of the  
analog input pin.  
Equivalent circuit of  
analog signal output  
Microcomputer  
A/D input pin  
R
C
Vss  
∗1  
1 µF≥C≥1000pF  
where R≤500kΩ  
∗1 These values are reference values.  
Figure 6-2-2 Recommended Circuit When Using A/D Conversion  
116 A/D Converter Control Registers  
Chapter 6 A/D Conversion Functions  
6-3 A/D Converter Control Registers  
6-3-1 Overview  
Four registers control the A/D converter. See table 6-3-1.  
Table 6-3-1 A/D Converter Control Registers  
Name  
Address  
R/W  
R/W  
R/W  
R
Function  
A/D control register 0  
ANCTR0 X'03F90'  
ANCTR1 X'03F91'  
ANBUF0 X'03F92'  
ANBUF1 X'03F93'  
A/D control register 1  
A/D buffer 0  
R
A/D buffer 1  
A/D Converter Control Registers 117  
Chapter 6 A/D Conversion Functions  
6-3-2 A/D Control Register (ANCTR)  
This readable and writable 8-bit register controls the operation of the A/D  
converter.  
7
6
5
4
3
2
1
0
(at reset: XXXX0XXX)  
ANCK0  
ANSH1 ANSH0  
ANCK1  
ANLADE  
ANCHS2 ANCHS1 ANCHS0  
ANCTR0  
ANCHS2 ANCHS1 ANCHS0 Analog input selection  
0
1
AN0  
AN1  
AN2  
AN3  
AN4  
AN5  
AN6  
AN7  
0
0
1
0
1
0
1
1
0
0
1
1
ANLADE  
A/D ladder resistor control  
0
1
A/D ladder resistors off  
A/D ladder resistors on  
A/D conversion  
clock selection∗1  
ANCK1  
ANCK0  
0
1
0
1
fs/2  
fs/4  
fs/8  
0
1
Use prohibited  
Sample and  
hold time setting∗2  
ANSH1  
ANSH0  
0
1
0
1
TAD × 2  
TAD × 6  
TAD × 18  
Use prohibited  
0
1
(1) A/D control register 0 (ANCTR0)  
∗1:Specify that where the period of the A/D conversion clock  
is greater than 800ns.  
∗2:Sample-and-hold time is determined by the analog input  
impedance. TAD indicates the period of the A/D conversion  
clock.  
Figure 6-3-1 A/D Control Register 0 (ANCTR0: X'03F90', R/W)  
118 A/D Converter Control Registers  
Chapter 6 A/D Conversion Functions  
(2) A/D conversion control register 1 (ANCTR1)  
7
6
5
4
3
2
1
0
(at reset: 0-------)  
ANCTR1  
ANST  
A/D conversion status  
ANST  
0
1
A/D conversion completed or stopped  
A/D conversion started or in progress  
Figure 6-3-2 A/D Control Register 1 (ANCTR1: X'03F91', R/W)  
A/D Converter Control Registers 119  
Chapter 6 A/D Conversion Functions  
6-3-3 A/D Buffers (ANBUF)  
These read-only registers store the A/D conversion results.  
(1) A/D buffer 0 (ANBUF0)  
This register stores the lower 2 bits of the A/D conversion results.  
7
6
5
4
3
2
1
0
(at reset: XX------)  
ANBUF0  
ANBUF07 ANBUF06  
Figure 6-3-3 A/D Buffer 0 (ANBUF0: X'03F92', R)  
(2) A/D buffer 1 (ANBUF1)  
This register stores the upper 8 bits of the A/D conversion results.  
7
6
5
4
3
2
1
0
ANBUF10  
ANBUF15 ANBUF14 ANBUF13 ANBUF12 ANBUF11  
ANBUF17  
ANBUF16  
ANBUF1  
(at reset: XXXXXXXX)  
Figure 6-3-4 A/D Buffer 1 (ANBUF1: X'03F93', R)  
120 A/D Converter Control Registers  
AC Zero-Cross  
Circuit/Noise Filter  
Chapter 7  
7
121  
Chapter 7 AC Zero-Cross Circuit/Noise Filter  
7-1 Overview  
The P21/SENS pin is the input pin for the AC zero-cross detection circuit.  
The AC zero-cross detection circuit outputs a high level when the input is at  
an intermediate level, and a low level at all other times.  
FLOAT1  
0
P7RDWN  
PARDWN  
P21IM  
–
–
–
–
–
7
P21 input/IRQ1  
to noise filter  
AC zero-cross  
detection circuit  
P21/IRQ1/SENS  
MUX  
(See figure 7-3-1.)  
Figure 7-1-1 P21 Input Circuit Block Diagram  
122 Overview  
Chapter 7 AC Zero-Cross Circuit/Noise Filter  
7-2 AC Zero-Cross Circuit Operation  
7-2-1 Setup and Operation  
Settings for zero-cross circuit operation are listed below.  
(1) Set the REDG1 flag of the IRQ1ICR register to select the valid edge for IRQ1.  
(2) Set the NF1EN and NF1CK1 to 0 flags of the NFCTR register to set the noise filter  
and its sampling clock.  
(3) With the P21IM flag of the FLOAT1 register, set the P21 pin to zero-cross  
detection.  
(4) An IRQ1 interrupt is generated by the falling edge or the rising edge of AC  
zero-cross detection output.  
10 ms at 50Hz  
8.3 ms at 60Hz  
AC line waveform  
VDD  
VSS  
Ideal  
IRQ1  
Actual  
IRQ1  
Point A  
Figure 7-2-1 AC Line Waveform and IRQ Generation Timing  
Actual IRQ interrupt requests will be generated multiple times. Therefore, the software must  
filter this signal before making any evaluations.  
When noise filtering is selected for use, the amount of evaluation processing by the software  
will be reduced. However, if the OSC stops, a return from the backup mode will not be  
possible.  
AC Zero-Cross Circuit Operation 123  
Chapter 7 AC Zero-Cross Circuit/Noise Filter  
7-3 Noise Filter  
7-3-1 Overview  
External interrupt pins IRQ0 and IRQ1 contain noise filtering circuit. This  
circuitry can be used for remote control signal reception.  
Data bus  
NFCTR  
0
NF0EN  
NF0CKS0  
NF0CKS1  
NF1EN  
NF1CKS0  
NF1CKS1  
IRQ0: External interrupt 0  
IRQ1: External interrupt 1  
2
2
fs/22  
fs/28  
fs/29  
fs/210  
7
MUX  
Noise filter  
P20/IRQ0  
To IRQ0  
interrupt  
MUX  
fs/22  
fs/28  
fs/29  
fs/210  
MUX  
AC zero-cross  
circuit  
Noise filter  
P21/IRQ1/SENS  
To IRQ1  
interrupt  
MUX  
(Fig.7-1-1)  
Figure 7-3-1 Noise Filtering Circuit Block Diagram  
124 Noise Filter  
Chapter 7 AC Zero-Cross Circuit/Noise Filter  
7-3-2 Example Input and Output Waveforms for Noise Filter  
When the noise filter is used, the waveform input to the IRQ0 pin is sampled based on the  
clock specified by the NF0CKS0 and NF0CKS1 flags of the noise filter control register  
(NFCTR). The waveform input to the IRQ1 pin is also sampled based on the clock specified  
by the NF1CKS0 and NF1CKS1 flags. If the sampled level remains the same for 3  
consecutive samples, it is sent the CPU; otherwise, the previous level is maintained.  
Noise filtering cannot be  
used in the STOP or HALT  
modes.  
Sampling  
Input  
0
0
1
1
1
1
1
0
0
Waveform after  
noise filtering  
Figure 7-3-2 Noise Filter Input and Output Waveform Example  
Noise Filter 125  
Chapter 7 AC Zero-Cross Circuit/Noise Filter  
7-4 AC Zero-Cross Control Register  
7-4-1 Overview  
Four registers control the AC zero-cross circuit.  
Table 7-4-1 AC Zero-Cross Control Register  
[☞ 2-4-3 "Interrupt Control  
Registers ■ External Interrupt  
Control Registers"]  
Name  
Address  
R/W  
R/W  
R/W  
R/W  
R/W  
Function  
External interrupt control register 0  
External interrupt control register 1  
Pin control register 1  
IRQOICR X'03FE2'  
IRQ1ICR X'03FE3'  
[☞ 3-2-2 "I/O Port Control  
FLOAT1  
NFCTR  
X'03F4B'  
X'03F8A'  
Registers  
Registers"]  
■
Pin Control  
Noise filter control register  
126 AC Zero-Cross Control Register  
Chapter 7 AC Zero-Cross Circuit/Noise Filter  
7-4-2 Noise Filter Control Register (NFCTR)  
This 6-bit readable and writable register controls the noise filter.  
7
–
6
–
5
4
3
2
1
0
(at reset: --000000)  
NF1EN  
NF1CKS1 NF1CKS0  
NF0CKS1 NF0CKS0 NF0EN  
NFCTR  
NF0EN  
IRQ0 noise filter setup and operation  
0
1
IRQ0 noise filter off  
IRQ0 noise filter on  
IRQ0 noise filter  
sampling period selection  
NF0CKS1 NF0CKS0  
fs/22  
fs/28  
fs/29  
0
0
1
1
0
fs/210  
1
NF1EN  
IRQ1 noise filter setup and operation  
0
1
IRQ1 noise filter off  
IRQ1 noise filter on  
IRQ1 noise filter  
sampling period selection  
NF1CKS1 NF1CKS0  
fs/22  
fs/28  
fs/29  
fs/210  
0
0
1
1
0
1
Figure 7-4-1 Noise Filter Control Register (NFCTR: X'03F8A', R/W)  
AC Zero-Cross Control Register 127  
Chapter 7 AC Zero-Cross Circuit/Noise Filter  
128  
Appendices  
8
129  
Chapter 8 Appendices  
8-1 EPROM Versions  
8-1-1 Overview  
EPROM version is microcomputer which was replaced with the mask ROM  
of the MN101C11 with an electronically programmable 16-KB EPROM.  
Because the MN101CP117**(**=DP,BF,HP) is sealed in plastic, once data  
is written to the internal PROM it cannot be erased.  
Because the PX-AP101C11-SDC and PX-AP101C11-FBC are sealed in a  
ceramic package that has a window, written data can beerased by  
illumination with ultraviolet light. Plastic package uses a 42-pin shrink DIL  
package, 44-pin flat package, and 48-pin flat package. Ceramic packages  
uses a 42-pin shrink DIL package and 44-pin flat package.  
Setting the EPROM version to EPROM mode, halts microcomputer  
functions, and the internal EPROM can be programmed. Refer to the  
EPROM mode pin diagram in figure 9-4-3 to 5.  
The specification for writing to the internal EPROM are the same as for a  
general-purpose 256Kbit EPROM(Vpp=12.5V, tpw=0.2ms). Therefore,  
by replacing theEPROM Version's 42-pin socket with a special 28-pin  
socket adapter(supplied by Panasonic) having the same configuration as a  
normal EPROM, a general-purpose EPROM writer can be  
used to perform read and write operations.  
The EPROM Version is described on the following items:  
- Cautions on use of the internal EPROM  
- Erasing written Data in Windowed Package(PX-AP101C11-SDC, PX-  
AP101C11-FBC)  
- Characteristics of EPROM Versions  
- Writing to the Microcomputer with Internal EPROM  
- Cautions on operating a ROM writer  
- Option bit  
- Connections of a writing adaptor.  
130  
EPROM Versions  
Chapter 8 Appendices  
8-1-2 Cautions on Use  
EPROM Versions differs from the MN101C11* in some of its electrical  
characteristics. The user should be aware of these differences.  
(1) To prevent data from being erased by ultraviolet light after a program is  
written, affix seals impermeable to UV rays to the glass sections at the  
top and side sections of the CPU.  
(PX-AP101C11-SDC, PX-AP101C11-FBC)  
(2) Due to device characteristics of the MN101CP11XXX, a writing test  
cannot be performed on all bits. Therefore, storage of the written data  
cannot be guaranteed in some cases.  
(3) When a program is written, verify that Vc power supply(6V) is connected  
before applying the Vpp power supply(12.5V). Disconnect the Vpp  
supply before disconnecting the Vcc supply.  
(4) Vpp should never exceed 13.5V including overshoot.  
(5) If a device is removed while a Vpp of +12.5V is applied, device reliability  
may be damaged.  
(6) At CE=VIL, do not change Vpp from VIL to +12.5V or from +12.5V to  
VIL.  
(7) From the time after a program is written until just before mounting,  
storage at a high temperature is recommended.  
Program/Read  
High temperature storage  
125°C - 48H  
Read  
Mounting  
EPROM Versions  
131  
Chapter 8 Appendices  
8-1-3 Erasing Written Data in Windowed Packages  
(PX-AP101C11-SDC, PX-AP101C11-FBC)  
In an internal EPROM with windowed packaging, data is erased("0" →"1")  
when UV light at 253.7nm permeates the window to irradiate the chip.  
2
The recommended exposure is 10W · s/cm . This coverage can be achieved  
by using a commercial UV lamp positioned 2 to 3cm above the package for  
15-20 minutes(when the illumination intensity of the package surface  
2
is12000µW/cm ). Remove any filters attached to the lamp. By installing a  
mirrored reflector plate in the lamp, illumination intensity will increase by  
afactor of 1.4 to 1.8, decreasing the erasure time.  
If the window becomes dirty with oil, adhesive, etc., UV light permeability will  
decrease, causing the erasure time to increase considerably. If this  
happens, clean with alcohol or another solvent that will not harm the  
package. The recommended above provides sufficient leeway, with several  
times the amount of time it takes to erase all the bits. However, this value  
will reliably erase data over all temperature and voltage ranges, and should  
not be altered. The level of illumination should be regularly checked and the  
lamp operation verified.  
Erasure begins when EPROM is exposed to light with a wavelength shorter  
than 400nm. Since fluorescent light and sunlight have wavelengths in this  
range, exposure to these light sources for extended periods of time could  
cause inadvertant erasure. To prevent this, cover the window with an  
opaque label.  
Data is not erased at wavelengths longer than 400 to 500nm. However,  
because of typical semiconductor characteristics, the circuit may  
malfunction if the chip is exposed to an extremely high illumination intensity.  
The chip will operate normally if this exposure is stopped. However, for  
areas where it is continuous, take necessary precautions.  
132  
EPROM Versions  
Chapter 8 Appendices  
8-1-4 Characteristics of EPROM Version  
The MN101C11*(mask ROM version) and the Microcomputer with internal  
EPROM version have the following differences.  
Table 8-1-1 Difference between MN101C*(Mask ROM version) and  
Internal EPROM version)  
Internal EPROM version  
-20 to 85℃  
MN101C11＊（ROM ver.）  
Operating temperature  
Operating voltage  
-40 to 85℃  
4.5 to 5.5V（0.1μs/20MHz）  
4.5 to 5.5V（0.1μs/20MHz）  
2.7 to 5.5v（0.25μs/8MHz）　　　　  
2.7 to 5.5v（0.25μs/8MHz）  
2.0 to 5.5v（1.00μs/2MHz）  
Output current,input current and input judge level are the same.  
2.7 to 5.5v（1.00μs/2MHz）  
Pin DC characteristics  
ROM option  
EPROM option  
Hi-speed,low-speed oscilla-  
tion start control,runaway  
detection period settup  
Package selection  
Internal ROM final address data  
be used as option data.  
EPROM final address data be  
used as option data.  
(Final address =X'07FFF)  
(Final address=X'07FFF)  
There are no other functional differences.  
EPROM Versions  
133  
Chapter 8 Appendices  
8-1-5 Writing to Microcomputer with Internal EPROM  
■ Fit in the writing adapter and position the No.1 pin.  
No.1 pin must be matched to  
this position.  
*The socket of an adapter  
varies according to the  
package types.  
Package type  
42-SDIP  
Product name  
OTP42SD-101CP11  
OTP44QF14-101CP11  
44-QFP  
48-QFH  
2
OTP48FH7-101CP11  
40  
39  
No.1 Pin  
No.1 Pin  
(MN101CP117DP)  
No.1 Pin  
(MN101CP117BF)  
(MN101CP117HP)  
(top view)  
No.1 Pin  
2.297  
0.127  
(top view)  
(PX-AP101C11-FBC)  
(PX-AP101C11-SDC)  
(side view)  
Figure 8-1-1 Mount on the writing adapter and position of No.1 pin.  
134  
EPROM Versions  
Chapter 8 Appendices  
■ ROM writer Selection  
The device names should be set up as listed below.  
Table 8-1-2 Device selection  
Equip. name Vendor  
Remarks  
Device name  
Pecker 30  
Avarl Data  
Hitachi 27C256  
Hitachi 27C256  
Hitachi 27C256  
1890A  
Minato Electronics  
Data I/O  
Do not run ID check and  
pin connection inspection.  
Lab Site  
The above settings are based on the standard samples.  
When you use the other equipment than the ones listed, contact the  
nearest semiconductor design center.(Refer to the sales office table  
attached at the end of the manual.)  
EPROM Versions  
135  
Chapter 8 Appendices  
8-1-6 Cautions on Operating the ROM Writer  
■ Cautions on operating the ROM writer  
(1)The Vpp programming voltage for the EPROM versions is 12.5V.  
Programming with a 21-volt ROM writer can lead to damage. The ROM  
writer specifications must match those for standard 1-megabit  
EPROMS:Vpp=12.5V V;tpw=0.2ms.  
(2)Make sure that the socket adapter matches the ROM writer socket and  
that the chip is correctly mounted in the socket adapter. Faulty  
connections can lead to damage.  
(3)After clearing all memory of the ROM writer, load the program.  
(Write the data X'FF' on the address X'0000' to X'7FFF'.)  
(4)After confirming the device name, write the addresses from the start to  
the final address.  
(5)The option bits for supporting the mask option are prepared at the final  
ROM address.  
This writer has no internal ID codes of Silicon Signature and Intelligent  
Identifier of the auto-device selection command of ROM writer. If the  
auto-device selection command is to be executed for this writer, the  
device is likely damaged. Therefore, never use this command.  
■ When disabling the writing  
When disabling the writing, check the following points.  
(1)Check that the device is mounted correctly on the socket.(pin bending,  
connecting failure).  
(2)Check that the erase check result is no problem.  
(3)Check that the adapter type is identical to the device name.  
(4)Check that the writing mode is set correctly.  
(5)Check that the data is correctly transferred to the ROM writer.  
(6)Recheck the check points (1),(2) and (3) provided on the above  
paragraph of ìCautions on Handling the ROM writerî.  
When the writing is disabled even after the above check points are  
confirmed and the device is replaced with another one, contact the  
nearest semiconductor design center.  
(See the attached sales office table.)  
136  
EPROM Versions  
Chapter 8 Appendices  
8-1-7 Option Bit  
The MN101C117 and the MN101CP117 control the oscillation mode after resetting  
as well as the runaway-detection watch dog timer, using bit 2 to 0 of the last address  
(X'7FFF) of the built-in ROM.  
■
Option bit  
7
6
5
4
3
2
1
0
PKGSEL2 PKGSEL1 W DSEL2 W DSEL1 NSSTRT  
Selectionofoscillationmode  
NSSTRT  
afterresetting  
0
1
Slow m ode  
NORM AL m ode  
W atchdogtimercyclesetting  
W DSEL2 W DSEL1  
fs/216  
fs/218  
fs/220  
0
0
1
1
X
Package  
PKGSEL2 PKGSEL1  
X
0
1
0
1
SDIP042-P-0600  
QFP044-P-1010  
QFH048-P-0707  
Fig. 8-1-2 Option bit(Address: X'07FFF')  
EPROM Versions  
137  
Chapter 8 Appendices  
8-1-8 Writing Adapter Connection  
VSS  
VSS  
NOE  
VSS  
A14  
VSS  
VSS  
VSS  
VSS  
VPP  
VSS  
NCE  
A0  
P00  
P01  
P02  
P06  
P10  
P11  
P12  
P13  
P14  
P20  
P21  
P22  
P60  
P61  
P62  
P63  
P64  
P65  
P66  
P67  
NRST  
1
2
VSS 42  
OSC1 41  
OSC2 40  
VDD 39  
PA7 38  
PA6 37  
PA5 36  
PA4 35  
PA3 34  
PA2 33  
PA1 32  
PA0 31  
P80 30  
P81 29  
P82 28  
P83 27  
P84 26  
P85 25  
P86 24  
P87 23  
M M OD 22  
VSS  
VSS  
VSS  
VCC  
VSS  
VSS  
A13  
A12  
A11  
A10  
A9  
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
A8  
D0  
A1  
D1  
A2  
D2  
A3  
D3  
A4  
D4  
A5  
D5  
A6  
D6  
A7  
D7  
VSS  
VCC  
Package Code SDIP042-P-0600  
Fig. 8-1-3 MN1-1CP117-DP(DC)EPROM Writing Adapter Connections  
Refer to the pin connection drawing of the 256-bit  
EPROM(27C256).  
138  
EPROM Versions  
Chapter 8 Appendices  
1
2
P83  
P82  
P81  
P80  
PA0  
PA1  
PA2  
PA3  
PA4  
PA5  
PA6  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
P63  
P62  
P61  
P60  
P22  
P21  
P20  
P14  
P13  
P12  
P11  
D3  
D2  
A3  
A2  
3
D1  
D0  
A1  
A0  
4
5
A8  
A9  
NCE  
VSS  
VPP  
VSS  
VSS  
VSS  
VSS  
M N101CP117  
４４-ＱＦＰ  
6
7
A10  
A11  
A12  
A13  
VSS  
8
9
10  
11  
Package code: QFP044-P-1010  
Pin pitch: 0.8mm  
Fig. 8-1-4 MN101CP117-BL(BC)EPROM Writing Adapter Connections  
Refer to the pin connection drawing of the 256-bit  
EPROM(27C256).  
EPROM Versions  
139  
Chapter 8 Appendices  
P63  
P62  
P61  
P60  
P23  
P22  
P21  
P20  
P14  
P13  
P12  
P11  
1 P83  
2 P82  
3 P81  
4 P80  
5 NC  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
D3  
D2  
D1  
D0  
A3  
A2  
A1  
A0  
VSS  
NCE  
VSS  
VPP  
VSS  
VSS  
VSS  
VSS  
6 PA0  
A8  
A9  
M N101CP117  
４８-ＱＦＨ  
PA1  
PA2  
PA3  
PA4  
PA5  
PA6  
7
8
A10  
A11  
A12  
A13  
VSS  
9
10  
11  
12  
Package code: QFH048-P-0707  
Pin pitch:  
0.5mm  
Fig. 8-1-5 MN101CP117-HP EPROM Writing Adapter connections  
Refer to the pin connection drawing of the 256-bit  
EPROM(27C256).  
140  
EPROM Versions  
Chapter 10 Appendices  
8-2 Instruction Set  
MN101C00 SERIES INSTRUCTION SET  
Affected Flag  
VF NF CF ZF  
Group  
Mnemonic  
Operation  
CodeCycle Re-  
Machine Code  
NotesPage  
Size  
peat  
Expand 1  
2
3
4
5
6
7
8
9
10  
11  
Data move instructions  
2
4
3
3
2
4
7
3
5
7
4
4
5
7
2
4
7
3
5
7
4
4
5
7
6
6
7
9
2
2
3
3
3
5
5
7
7
4
4
7
7
2
3
3
3
5
5
7
7
4
4
7
7
2
2
4
4
6
1
2
3
2
2
2
4
2
3
4
2
2
2
4
2
2
4
2
3
4
2
2
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4
3
3
3
5
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4
3
3
4
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5
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30  
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41  
42  
42  
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46  
46  
47  
47  
48  
48  
49  
49  
50  
50  
51  
51  
52  
52  
53  
53  
54  
MOV  
–
–
–
–
–
–
–
–
MOV Dn,Dm  
Dn→Dm  
1010 DnDm  
1010 DmDm <#8. ...>  
0010 1001 01Dn  
MOV imm8,Dm  
MOV Dn,PSW  
imm8→Dm  
Dn→PSW  
MOV PSW,Dm  
MOV (An),Dm  
PSW→Dm  
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0010 0001 01Dm  
0100 1ADm  
mem8(An)→Dm  
MOV (d8,An),Dm  
MOV (d16,An),Dm  
MOV (d4,SP),Dm  
MOV (d8,SP),Dm  
MOV (d16,SP),Dm  
MOV (io8),Dm  
mem8(d8+An)→Dm  
mem8(d16+An)→Dm  
mem8(d4+SP)→Dm  
mem8(d8+SP)→Dm  
mem8(d16+SP)→Dm  
mem8(IOTOP+io8)→Dm  
mem8(abs8)→Dm  
mem8(abs12)→Dm  
mem8(abs16)→Dm  
Dn→mem8(Am)  
∗1  
0110 1ADm <d8. ...>  
0010 0110 1ADm <d16 ....  
0110 01Dm <d4>  
....  
....  
...>  
...>  
∗2  
∗3  
0010 0110 01Dm <d8. ...>  
0010 0110 00Dm <d16 ....  
0110 00Dm <io8 ...>  
0100 01Dm <abs 8..>  
MOV (abs8),Dm  
MOV (abs12),Dm  
MOV (abs16),Dm  
MOV Dn,(Am)  
0100 00Dm <abs 12.. ...>  
0010 1100 00Dm <abs 16.. ....  
0101 1aDn  
...>  
...>  
...>  
MOV Dn,(d8,Am)  
MOV Dn,(d16,Am)  
MOV Dn,(d4,SP)  
MOV Dn,(d8,SP)  
MOV Dn,(d16,SP)  
MOV Dn,(io8)  
Dn→mem8(d8+Am)  
Dn→mem8(d16+Am)  
Dn→mem8(d4+SP)  
Dn→mem8(d8+SP)  
Dn→mem8(d16+SP)  
Dn→mem8(IOTOP+io8)  
Dn→mem8(abs8)  
∗1  
0111 1aDn <d8. ...>  
0010 0111 1aDn <d16 ....  
0111 01Dn <d4>  
....  
....  
∗2  
∗3  
0010 0111 01Dn <d8. ...>  
0010 0111 00Dn <d16 ....  
0111 00Dn <io8 ...>  
0101 01Dn <abs 8..>  
MOV Dn,(abs8)  
MOV Dn,(abs12)  
MOV Dn,(abs16)  
MOV imm8,(io8)  
MOV imm8,(abs8)  
MOV imm8,(abs12)  
MOV imm8,(abs16)  
MOV Dn,(HA)  
Dn→mem8(abs12)  
Dn→mem8(abs16)  
imm8→mem8(IOTOP+io8)  
imm8→mem8(abs8)  
imm8→mem8(abs12)  
imm8→mem8(abs16)  
Dn→mem8(HA)  
0101 00Dn <abs 12.. ...>  
0010 1101 00Dn <abs 16.. ....  
...>  
0000 0010 <io8 ...> <#8. ...>  
0001 0100 <abs 8..> <#8. ...>  
0001 0101 <abs 12.. ...> <#8. ...>  
0011 1101 1001 <abs 16.. ....  
1101 00Dn  
...> <#8. ...>  
MOV  
W
MOV  
MOV  
MOV  
MOV  
MOV  
MOV  
MOV  
MOV  
MOV  
MOV  
MOV  
MOV  
MOV  
MOV  
MOV  
MOV  
MOV  
MOV  
MOV  
MOV  
MOV  
MOV  
MOV  
MOV  
MOV  
MOV  
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
(An),DWm  
mem16(An)→DWm  
mem16(An)→Am  
1110 00Ad  
(An),Am  
∗4  
∗2  
∗2  
∗3  
∗3  
0010 1110 10Aa  
(d4,SP),DWm  
(d4,SP),Am  
(d8,SP),DWm  
(d8,SP),Am  
(d16,SP),DWm  
(d16,SP),Am  
(abs8),DWm  
(abs8),Am  
mem16(d4+SP)→DWm  
mem16(d4+SP)→Am  
mem16(d8+SP)→DWm  
mem16(d8+SP)→Am  
mem16(d16+SP)→DWm  
mem16(d16+SP)→Am  
mem16(abs8)→DWm  
mem16(abs8)→Am  
mem16(abs16)→DWm  
mem16(abs16)→Am  
DWn→mem16(Am)  
An→mem16(Am)  
1110 011d <d4>  
1110 010a <d4>  
0010 1110 011d <d8. ...>  
0010 1110 010a <d8. ...>  
0010 1110 001d <d16 ....  
0010 1110 000a <d16 ....  
1100 011d <abs 8..>  
....  
....  
...>  
...>  
1100 010a <abs 8..>  
(abs16),DWm  
(abs16),Am  
DWn,(Am)  
0010 1100 011d <abs 16.. ....  
0010 1100 010a <abs 16.. ....  
1111 00aD  
...>  
...>  
An,(Am)  
∗4  
∗2  
∗2  
∗3  
∗3  
0010 1111 10aA  
DWn,(d4,SP)  
An,(d4,SP)  
DWn,(d8,SP)  
An,(d8,SP)  
DWn,(d16,SP)  
An,(d16,SP)  
DWn,(abs8)  
An,(abs8)  
DWn→mem16(d4+SP)  
An→mem16(d4+SP)  
DWn→mem16(d8+SP)  
An→mem16(d8+SP)  
DWn→mem16(d16+SP)  
An→mem16(d16+SP)  
DWn→mem16(abs8)  
An→mem16(abs8)  
DWn→mem16(abs16)  
An→mem16(abs16)  
DWn→mem16(HA)  
An→mem16(HA)  
1111 011D <d4>  
1111 010A <d4>  
0010 1111 011D <d8. ...>  
0010 1111 010A <d8. ...>  
0010 1111 001D <d16 ....  
0010 1111 000A <d16 ....  
1101 011D <abs 8..>  
....  
....  
...>  
...>  
1101 010A <abs 8..>  
DWn,(abs16)  
An,(abs16)  
DWn,(HA)  
0010 1101 011D <abs 16.. ....  
0010 1101 010A <abs 16.. ....  
1001 010D  
...>  
...>  
An,(HA)  
1001 011A  
MOVW imm8,DWm  
MOVW imm8,Am  
sign(imm8)→DWm  
zero(imm8)→Am  
∗5  
0000 110d <#8. ...>  
0000 111a <#8. ...>  
∗6  
MOVW imm16,DWm  
imm16→DWm  
1100 111d <#16 ....  
....  
...>  
Note: "Page" refers to the corresponding page in the Instruction Manual.  
∗1　d8 sign extended  
∗2　d4 zero extended  
∗3　d8 zero extended  
∗4　A=An, a=Am  
∗5　#8 sign extended  
∗6　#8 zero extended  
Instruction Set 141  
Chapter 10 Appendices  
MN101C00 SERIES INSTRUCTION SET  
Affected Flag  
VF NF CF ZF  
Group  
Mnemonic  
Operation  
CodeCycle Re-  
Machine Code  
NotesPage  
Size  
peat  
Expand 1  
2
3
4
5
6
7
8
9
10  
11  
6
3
3
3
3
3
3
2
2
2
2
3
3
3
3
3
3
3
3
3
5
3
4
3
54  
55  
55  
MOVW imm16,Am  
MOVW SP,Am  
MOVW An,SP  
MOVW DWn,DWm  
MOVW DWn,Am  
MOVW An,DWm  
MOVW An,Am  
PUSH Dn  
imm16→Am  
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
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–
–
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–
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–
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–
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–
–
–
–
–
–
–
–
–
–
1101 111a <#16 ....  
0010 0000 100a  
....  
...>  
SP→Am  
An→SP  
0010 0000 101A  
0010 1000 00Dd  
0010 0100 11Da  
0010 1100 11Ad  
0010 0000 00Aa  
1111 10Dn  
56  
DWn→DWm  
∗1  
56  
57  
DWn→Am  
An→DWm  
57  
An→Am  
∗2  
58  
58  
59  
59  
PUSH  
SP-1→SP,Dn→mem8(SP)  
SP-2→SP,An→mem16(SP)  
mem8(SP)→Dn,SP+1→SP  
mem16(SP)→An,SP+2→SP  
sign(Dn)→DWm  
PUSH An  
0001 011A  
POP  
POP Dn  
1110 10Dn  
POP An  
0000 011A  
60  
EXT  
EXT Dn,DWm  
0010 1001 000d  
∗3  
Arithmetic instructions  
3
3
4
3
3
3
3
5
7
3
4
7
7
3
3
3
2
5
3
3
3
7
7
3
3
3
4
6
7
9
3
3
3
6
6
2
2
2
2
3
3
2
3
4
2
2
4
4
3
3
2
1
3
2
3
3
4
4
8
9
2
2
3
3
5
3
3
3
3
3
61  
ADD  
ADD Dn,Dm  
Dm+Dn→Dm  
0011 0011 DnDm  
∗6  
61  
62  
63  
64  
64  
65  
65  
66  
66  
67  
67  
68  
69  
70  
71  
71  
72  
73  
74  
74  
75  
75  
76  
77  
78  
78  
79  
79  
80  
81  
81  
82  
82  
83  
ADD imm4,Dm  
Dm+sign(imm4)→Dm  
Dm+imm8→Dm  
1000 00Dm <#4>  
0000 10Dm <#8. ...>  
0011 1011 DnDm  
ADD imm8,Dm  
ADDC  
ADDW  
ADDC Dn,Dm  
Dm+Dn+CF→Dm  
DWm+DWn→DWm  
Am+DWn→Am  
∗1  
ADDW DWn,DWm  
ADDW DWn,Am  
ADDW imm4,Am  
ADDW imm8,Am  
ADDW imm16,Am  
ADDW imm4,SP  
ADDW imm8,SP  
ADDW imm16,SP  
ADDW imm16,DWm  
0010 0101 00Dd  
0010 0101 10Da  
∗6  
Am+sign(imm4)→Am  
Am+sign(imm8)→Am  
Am+imm16→Am  
SP+sign(imm4)→SP  
SP+sign(imm8)→SP  
SP+imm16→SP  
1110 110a <#4>  
∗7  
0010 1110 110a <#8. ...>  
0010 0101 011a <#16 ....  
1111 1101 <#4>  
....  
...>  
∗6  
–
–
–
–
–
–
–
–
–
–
–
–
∗7  
1111 1100 <#8. ...>  
0010 1111 1100 <#16 ....  
0010 0101 010d <#16 ....  
0010 1000 1aDn  
....  
....  
...>  
...>  
DWm+imm16→DWm  
Am+zero(Dn)→Am  
Am+sign(Dn)→Am  
∗8  
ADDUW ADDUW Dn,Am  
ADDSW ADDSW Dn,Am  
0010 1001 1aDn  
SUB  
SUB Dn,Dm(when Dn≠Dm) Dm-Dn→Dm  
0010 1010 DnDm  
SUB Dn,Dn  
Dn-Dn→Dn  
0
0
0
1
1000 01Dn  
...>  
SUB imm8,Dm  
Dm-imm8→Dm  
0010 1010 DmDm <#8.  
○
SUBC  
SUBW  
SUBC Dn,Dm  
Dm-Dn-CF→Dm  
0010 1011 DnDm  
∗1  
SUBW DWn,DWm  
SUBW DWn,Am  
SUBW imm16,DWm  
SUBW imm16,Am  
MULU Dn,Dm  
DWm-DWn→DWm  
Am-DWn→Am  
0010 0100 00Dd  
0010 0100 10Da  
DWm-imm16→DWm  
Am-imm16→Am  
0010 0100 010d <#16 ....  
0010 0100 011a <#16 ....  
0010 1111 111D  
....  
....  
...>  
...>  
∗4  
MULU  
DIVU  
CMP  
Dm∗Dn→DWk  
0
∗5　  
DIVU Dn,DWm  
CMP Dn,Dm  
DWm/Dn→DWm-I...DWm-h  
Dm-Dn...PSW  
0010 1110 111d  
0011 0010 DnDm  
CMP imm8,Dm  
CMP imm8,(abs8)  
CMP imm8,(abs12)  
CMP imm8,(abs16)  
CMPW DWn,DWm  
CMPW DWn,Am  
CMPW An,Am  
Dm-imm8...PSW  
1100 00Dm <#8. ...>  
0000 0100 <abs 8..>  
0000 0101 <abs 12..  
0011 1101 1000 <abs 16.. ....  
0010 1000 01Dd  
mem8(abs8)-imm8...PSW  
mem8(abs12)-imm8...PSW  
mem8(abs16)-imm8...PSW  
DWm-DWn...PSW  
Am-DWn...PSW  
<#8. ...>  
...>  
<#8. ...>  
...> <#8. ...>  
CMPW  
∗1  
0010 0101 11Da  
Am-An...PSW  
∗2  
0010 0000 01Aa  
CMPW imm16,DWm  
CMPW imm16,Am  
DWm-imm16...PSW  
Am-imm16...PSW  
1100 110d <#16 ....  
1101 110a <#16 ....  
....  
....  
...>  
...>  
Logical instructions  
3
4
5
3
4
5
3
5
2
2
3
2
2
3
2
3
84  
84  
85  
86  
86  
87  
88  
88  
AND  
AND Dn,Dm  
Dm&Dn→Dm  
0
0
0
0
0011 0111 DnDm  
AND imm8,Dm  
AND imm8,PSW  
OR Dn,Dm  
Dm&imm8→Dm  
PSW&imm8→PSW  
DmIDn→Dm  
0001 11Dm <#8. ...>  
0010 1001 0010 <#8. ...>  
0011 0110 DnDm  
OR  
0
0
0
0
OR imm8,Dm  
OR imm8,PSW  
XOR Dn,Dm  
DmIimm8→Dm  
PSWIimm8→PSW  
Dm^Dn→Dm  
0001 10Dm <#8. ...>  
0010 1001 0011 <#8. ...>  
0011 1010 DnDm  
∗9  
XOR  
0
0
0
0
XOR imm8,Dm  
Dm^imm8→Dm  
0011 1010 DmDm <#8. ...>  
Note: "Page" refers to the corresponding page in the Instruction Manual.  
∗1　D=DWn, d=DWm  
∗2　A=An, a=Am  
∗3　d=DWm  
∗5　D=DWm  
∗9　m≠n  
∗6　#4 sign extended  
∗7　#8 sign extended  
∗8　Dn zero extended  
∗4　D=DWk  
142 Instruction Set  
Chapter 10 Appendices  
MN101C00 SERIES INSTRUCTION SET  
Group Mnemonic  
Affected Flag  
VF NF CF ZF  
Operation  
CodeCycle Re-  
Machine Code  
NotesPage  
Size  
peat  
Expand 1  
2
3
4
5
6
7
8
9
10  
11  
_
3
3
2
2
89  
90  
NOT  
NOT　Dn  
Dn→Dn  
0
0
0
0010 0010 10Dn  
0010 0011 10Dn  
ASR  
LSR  
ROR  
ASR　Dn  
LSR　Dn  
ROR　Dn  
Dn.msb→temp,Dn.lsb→CF  
Dn>>1→Dn,temp→Dn.msb  
Dn.lsb→CF,Dn>>1→Dn  
0→Dn.msb  
–
0
3
3
2
2
91  
92  
0
0
0010 0011 11Dn  
0010 0010 11Dn  
Dn.Isb→temp,Dn>>1→Dn  
CF→Dn.msb,temp→CF  
Bit manipulation instructions  
5
4
7
5
4
7
5
4
6
5
4
6
93  
93  
94  
95  
95  
96  
BSET  
BCLR  
BTST  
BSET (io8)bp  
mem8(IOTOP+io8)&bpdata...PSW 0 ● 0 ●  
0011 1000 0bp. <io8 ...>  
1011 0bp. <abs 8..>  
1→mem8(IOTOP+io8)bp  
BSET (abs8)bp  
BSET (abs16)bp  
BCLR (io8)bp  
mem8(abs8)&bpdata...PSW  
1→mem8(abs8)bp  
0 ● 0 ●  
mem8(abs16)&bpdata...PSW  
1→mem8(abs16)bp  
0 ● 0 ●  
0011 1100 0bp. <abs 16.. ....  
0011 1000 1bp. <io8 ...>  
1011 1bp. <abs 8..>  
...>  
mem8(IOTOP+io8)&bpdata...PSW 0 ● 0 ●  
0→mem8(IOTOP+io8)bp  
BCLR (abs8)bp  
BCLR (abs16)bp  
mem8(abs8)&bpdata...PSW  
0→mem8(abs8)bp  
0 ● 0 ●  
mem8(abs16)&bpdata...PSW  
0→mem8(abs16)bp  
0 ● 0 ●  
0011 1100 1bp. <abs 16.. ....  
...>  
...>  
5
7
3
5
97  
97  
BTST imm8,Dm  
BTST (abs16)bp  
Dm&imm8...PSW  
0 ● 0 ●  
0010 0000 11Dm <#8. ...>  
mem8(abs16)&bpdata...PSW  
0 ● 0 ●  
0011 1101 0bp. <abs 16.. ....  
Branch instructions  
Bcc  
3
4
5
3
4
5
4
5
4
5
4
5
4
2/3  
2/3  
2/3  
2/3  
2/3  
2/3  
2/3  
2/3  
2/3  
2/3  
2/3  
2/3  
2/3  
98  
BEQ label  
BEQ label  
BEQ label  
BNE label  
BNE label  
BNE label  
BGE label  
BGE label  
BCC label  
BCC label  
BCS label  
BCS label  
BLT label  
if(ZF=1), PC+3+d4(label)+H  
→
→
PC  
PC  
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
∗1  
∗2  
∗3  
∗1  
∗2  
∗3  
∗2  
∗3  
∗2  
∗3  
∗2  
∗3  
∗2  
1001 000H <d4>  
if(ZF=0), PC+3→PC  
98  
if(ZF=1), PC+4+d7(label)+H  
if(ZF=0), PC+4→PC  
1000 1010 <d7. ...H  
1001 1010 <d11 .... ...H  
1001 001H <d4>  
99  
if(ZF=1), PC+5+d11(label)+H  
→
PC  
if(ZF=0), PC+5→PC  
100  
100  
101  
102  
102  
103  
103  
104  
104  
105  
if(ZF=0), PC+3+d4(label)+H  
→
PC  
PC  
if(ZF=1), PC+3→PC  
if(ZF=0), PC+4+d7(label)+H  
→
1000 1011 <d7. ...H  
1001 1011 <d11 .... ...H  
1000 1000 <d7. ...H  
1001 1000 <d11 .... ...H  
1000 1100 <d7. ...H  
1001 1100 <d11 .... ...H  
1000 1101 <d7. ...H  
1001 1101 <d11 .... ...H  
1000 1110 <d7. ...H  
if(ZF=1), PC+4→PC  
if(ZF=0), PC+5+d11(label)+H  
→
PC  
if(ZF=1), PC+5→PC  
if((VF^NF)=0),PC+4+d7(label)+H→PC  
if((VF^NF)=1),PC+4→PC  
if((VF^NF)=0),PC+5+d11(label)+H→PC  
if((VF^NF)=1),PC+5→PC  
if(CF=0),PC+4+d7(label)+H  
→
PC  
PC  
PC  
PC  
if(CF=1), PC+4→PC  
if(CF=0), PC+5+d11(label)+H  
→
if(CF=1), PC+5→PC  
if(CF=1),PC+4+d7(label)+H  
→
if(CF=0), PC+4→PC  
if(CF=1), PC+5+d11(label)+H  
→
if(CF=0), PC+5→PC  
if((VF^NF)=1),PC+4+d7(label)+H→PC  
if((VF^NF)=0),PC+4→PC  
5
4
5
5
2/3  
2/3  
2/3  
3/4  
105  
106  
106  
107  
BLT label  
BLE label  
BLE label  
BGT label  
if((VF^NF)=1),PC+5+d11(label)+H→PC  
if((VF^NF)=0),PC+5→PC  
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
∗3  
∗2  
∗3  
∗2  
1001 1110 <d11 .... ...H  
1000 1111 <d7. ...H  
if((VF^NF)|ZF=1),PC+4+d7(label)+H→PC  
if((VF^NF)|ZF=0),PC+4→PC  
if((VF^NF)|ZF=1),PC+5+d11(label)+H→PC  
if((VF^NF)|ZF=0),PC+5→PC  
if((VF^NF)|ZF=0),PC+5+d7(label)+H→PC  
if((VF^NF)|ZF=1),PC+5→PC  
1001 1111 <d11 .... ...H  
0010 0010 0001 <d7. ...H  
Note: "Page" refers to the corresponding page in the Instruction Manual.  
∗1　d4 sign extended  
∗2　d7 sign extended  
∗3　d11 sign extended  
Instruction Set 143  
Chapter 10 Appendices  
MN101C00 SERIES INSTRUCTION SET  
Affected Flag  
VF NF CF ZF  
Group  
Mnemonic  
Operation  
CodeCycle Re-  
Machine Code  
NotesPage  
Size  
peat  
Expand 1  
2
3
4
5
6
7
8
9
10  
11  
6
3/4  
3/4  
3/4  
3/4  
3/4  
3/4  
3/4  
3/4  
3/4  
3/4  
3/4  
3/4  
3/4  
107  
108  
108  
109  
109  
110  
110  
111  
111  
112  
112  
113  
113  
Bcc  
BGT label  
if((VF^NF)|ZF=0),PC+6+d11(label)+H→PC  
–
–
–
–
–
–
–
–
–
–
–
–
–
–
∗3  
∗2  
∗3  
∗2  
∗3  
∗2  
∗3  
∗2  
∗3  
∗2  
∗3  
∗2  
∗3  
0010 0011 0001 <d11 .... ...H  
0010 0010 0010 <d7. ...H  
if((VF^NF)|ZF=1),PC+6→PC  
5
BHI label  
BHI label  
BLS label  
BLS label  
BNC label  
BNC label  
BNS label  
BNS label  
BVC label  
BVC label  
BVS label  
BVS label  
if(CF  
if(CFIZF=1), PC+5  
if(CF ZF=0),PC+6+d11(label)+H  
if(CFIZF=1), PC+6 PC  
if(CF ZF=1),PC+5+d7(label)+H  
if(CFIZF=0), PC+5 PC  
if(CF ZF=1),PC+6+d11(label)+H  
if(CFIZF=0), PC+6 PC  
if(NF=0),PC+5+d7(label)+H  
if(NF=1),PC+5 PC  
if(NF=0),PC+6+d11(label)+H  
if(NF=1),PC+6 PC  
if(NF=1),PC+5+d7(label)+H  
if(NF=0),PC+5 PC  
if(NF=1),PC+6+d11(label)+H  
if(NF=0),PC+6 PC  
if(VF=0),PC+5+d7(label)+H  
if(VF=1),PC+5 PC  
if(VF=0),PC+6+d11(label)+H  
if(VF=1),PC+6 PC  
if(VF=1),PC+5+d7(label)+H  
if(VF=0),PC+5 PC  
if(VF=1),PC+6+d11(label)+H  
if(VF=0),PC+6 PC  
I
ZF=0),PC+5+d7(label)+H→PC  
→
PC  
6
I
→
PC  
– －  
0010 0011 0010 <d11 .... ...H  
0010 0010 0011 <d7. ...H  
→
5
I
→
PC  
–
–
–
–
→
6
I
→
PC  
0010 0011 0011 <d11 .... ...H  
0010 0010 0100 <d7. ...H  
→
5
→
PC – － － －  
→
6
→
PC  
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0010 0011 0100 <d11 .... ...H  
0010 0010 0101 <d7. ...H  
→
5
→
PC  
→
6
→
PC  
0010 0011 0101 <d11 .... ...H  
0010 0010 0110 <d7. ...H  
→
5
→
PC  
→
6
→
PC  
0010 0011 0110 <d11 .... ...H  
0010 0010 0111 <d7. ...H  
→
5
→
PC  
→
6
→
PC  
0010 0011 0111 <d11 .... ...H  
→
3
4
5
6
3
3
114  
114  
115  
116  
BRA label  
PC+3+d4(label)+H→PC  
PC+4+d7(label)+H→PC  
PC+5+d11(label)+H→PC  
–
–
–
–
–
–
–
–
–
–
–
–
∗1  
∗2  
∗3  
∗2  
1110 111H <d4>  
BRA label  
1000 1001 <d7. ...H  
1001 1001 <d11 .... ...H  
3
BRA label  
3/4  
CBEQ  
CBNE  
TBZ  
CBEQ imm8,Dm,label  
if(Dm=imm8),PC+6+d7(label)+H  
→
PC  
1100 10Dm <#8. ...> <d7. ...H  
if(Dm=/imm8),PC+6 PC  
→
8
9
4/5  
6/7  
116  
117  
117  
118  
118  
119  
119  
120  
120  
121  
121  
122  
122  
CBEQ imm8,Dm,label  
if(Dm=imm8),PC+8+d11(label)+H→PC  
∗3  
∗2  
∗3  
∗2  
∗3  
∗2  
∗3  
∗2  
∗3  
∗2  
∗3  
∗2  
∗3  
0010 1100 10Dm <#8. ...> <d11 .... ...H  
if(Dm=/imm8),PC+8 PC  
→
CBEQ imm8,(abs8),label if(mem8(abs8)=imm8),PC+9+d7(label)+H  
→
PC  
0010 1101 1100 <abs 8..> <#8. ...> <d7. ...H  
if(mem8(abs8)=imm8),PC+9→PC  
/
10 6/7  
11 7/8  
12 7/8  
CBEQ imm8,(abs8),label  
if(mem8(abs8)=imm8),PC+10+d11(label)+H→PC  
0010 1101 1101 <abs 8..> <#8. ...> <d11 .... ...H  
if(mem8(abs8)=imm8),PC+10→PC  
/
CBEQ imm8,(abs16),label if(mem8(abs16)=imm8),PC+11+d7(label)+H→PC  
if(mem8(abs16)=imm8),PC+11→PC  
CBEQ imm8,(abs16),label if(mem8(abs16)=imm8),PC+12+d11(label)+H  
if(mem8(abs16)=  
if(Dm=imm8),PC+6+d7(label)+H→PC  
if(Dm=imm8),PC+6→PC  
0011 1101 1100 <abs 16.. ....  
0011 1101 1101 <abs 16.. ....  
...> <#8. ...> <d7. ...H  
/
→
PC  
...> <#8. ...> <d11 .... ...H  
/
imm8),PC+12→PC  
6
8
9
3/4  
4/5  
6/7  
CBNE imm8,Dm,label  
CBNE imm8,Dm,label  
/
1101 10Dm <#8. ...> <d7. ..H>  
if(Dm=/imm8),PC+8+d11(label)+H→PC  
0010 1101 10Dm <#8. ...> <d11 .... ...H  
0010 1101 1110 <abs 8..> <#8. ...> <d7. ...H  
0010 1101 1111 <abs 8..> <#8. ...> <d11 .... ...H  
if(Dm=imm8),PC+8→PC  
CBNE imm8,(abs8),label if(mem8(abs8)=  
/
imm8),PC+9+d7(label)+H→PC  
if(mem8(abs8)=imm8),PC+9→PC  
10 6/7  
11 7/8  
12 7/8  
CBNE imm8,(abs8),label  
if(mem8(abs8)=imm8),PC+10+d11(label)+H→PC  
/
if(mem8(abs8)=imm8),PC+10→PC  
CBNE imm8,(abs16),label if(mem8(abs16)=imm8),PC+11+d7(label)+H→PC  
/
0011 1101 1110 <abs 16.. ....  
0011 1101 1111 <abs 16.. ....  
...> <#8. ...> <d7. ...H  
if(mem8(abs16)=imm8),PC+11→PC  
CBNE imm8,(abs16),label if(mem8(abs16)=imm8),PC+12+d11(label)+H→PC  
/
...> <#8. ...> <d11 .... ...H  
if(mem8(abs16)=imm8),PC+12→PC  
7
8
6/7  
6/7  
TBZ (abs8)bp,label  
TBZ (abs8)bp,label  
if(mem8(abs8)bp=0),PC+7+d7(label)+H→PC  
0
0
0
0
0011 0000 0bp. <abs 8..> <d7. ...H  
if(mem8(abs8)bp=1),PC+7→PC  
if(mem8(abs8)bp=0),PC+8+d11(label)+H→PC  
0011 0000 1bp. <abs 8..> <d11 .... ...H  
if(mem8(abs8)bp=1),PC+8→PC  
Note: "Page" refers to the corresponding page in the Instruction Manual.  
∗1　d4 sign extended  
∗2　d7 sign extended  
∗3　d11 sign extended  
144 Instruction Set  
Chapter 10 Appendices  
MN101C00 SERIES INSTRUCTION SET  
Affected Flag  
VF NF CF ZF  
Group  
Mnemonic  
Operation  
CodeCycle Re-  
Machine Code  
NotesPage  
Size  
peat  
Expand 1  
2
3
4
5
6
7
8
9
10  
11  
123  
123  
124  
124  
125  
125  
126  
126  
127  
127  
TBZ  
∗1  
∗2  
∗1  
∗2  
∗1  
∗2  
∗1  
∗2  
∗1  
∗2  
7
6/7  
TBZ (io8)bp,label  
if(mem8(IOTOP+io8)bp=0),PC+7+d7(label)+H→PC  
0
0
0011 0100 0bp. <io8 ...> <d7. ...H  
if(mem8(IOTOP+io8)bp=1),PC+7→PC  
8
9
6/7  
7/8  
TBZ (io8)bp,label  
if(mem8(IOTOP+io8)bp=0),PC+8+d11(label)+H→PC  
if(mem8(IOTOP+io8)bp=1),PC+8→PC  
if(mem8(abs16)bp=0),PC+9+d7(label)+H→PC  
if(mem8(abs16)bp=1),PC+9→PC  
if(mem8(abs16)bp=0),PC+10+d11(label)+H→PC  
if(mem8(abs16)bp=1),PC+10→PC  
0
0
0
0
0
0
0
0
0011 0100 1bp. <io8 ...> <d11 .... ...H  
TBZ (abs16)bp,label  
TBZ (abs16)bp,label  
0011 1110 0bp. <abs 16.. ....  
0011 1110 1bp. <abs 16.. ....  
...> <d7. ...H  
...> <d11 .... ...H  
10 7/8  
7
6/7  
TBNZ  
TBNZ (abs8)bp,label  
if(mem8(abs8)bp=1),PC+7+d7(label)+H  
→
PC  
0011 0001 0bp. <abs 8..> <d7. ...H  
if(mem8(abs8)bp=0),PC+7→PC  
8
7
6/7  
6/7  
TBNZ (abs8)bp,label  
TBNZ (io8)bp,label  
if(mem8(abs8)bp=1),PC+8+d11(label)+H→PC  
if(mem8(abs8)bp=0),PC+8→PC  
if(mem8(io)bp=1),PC+7+d7(label)+H→PC  
if(mem8(io)bp=0),PC+7→PC  
0
0
0
0
0011 0001 1bp. <abs 8..> <d11 .... ...H  
0011 0101 0bp. <io8 ...> <d7. ...H  
8
9
6/7  
7/8  
TBNZ (io8)bp,label  
if(mem8(io)bp=1),PC+8+d11(label)+H→PC  
if(mem8(io)bp=0),PC+8→PC  
if(mem8(abs16)bp=1),PC+9+d7(label)+H→PC  
if(mem8(abs16)bp=0),PC+9→PC  
if(mem8(abs16)bp=1),PC+10+d11(label)+H→PC  
if(mem8(abs16)bp=0),PC+10→PC  
0
0
0
0
0
0
0011 0101 1bp. <io8 ...> <d11 .... ...H  
TBNZ (abs16)bp,label  
TBNZ (abs16)bp,label  
0011 1111 0bp. <abs 16.. ....  
0011 1111 1bp. <abs 16.. ....  
0010 0001 00A0  
...> <d7. ...H  
10 7/8  
...> <d11 .... ...H  
3
7
3
4
5
7
JMP  
JSR  
JMP　(An)  
JMP　label  
JSR (An)  
0→PC.17~16,An→PC.15~0,0→PC.H  
abs18(label)+H→PC  
–
–
–
–
–
–
–
–
–
–
–
–
128  
128  
129  
∗5  
0011 1001 0aaH <abs 18.b p15～ 0..>  
SP-3→SP,(PC+3).bp7~0→mem8(SP)  
0010 0001 00A1  
(PC+3).bp15~8→mem8(SP+1)  
(PC+3).H→mem8(SP+2).bp7,  
0→mem8(SP+2).bp6~2,  
(PC+3).bp17~16→mem8(SP+2).bp1~0  
0→PC.bp17~16  
An→PC.bp15~0,0→PC.H  
5
6
7
3
6
7
8
9
129  
130  
130  
131  
JSR label  
SP-3→SP,(PC+5).bp7~0→mem8(SP)  
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
∗3  
∗4  
∗5  
0001 000H <d12 ....  
...>  
....  
(PC+5).bp15~8→mem8(SP+1)  
(PC+5).H→mem8(SP+2).bp7,  
0→mem8(SP+2).bp6~2,  
(PC+5).bp17~16→mem8(SP+2).bp1~0  
PC+5+d12(label)+H→PC  
SP-3→SP,(PC+6).bp7~0→mem8(SP)  
JSR label  
0001 001H <d16 ....  
...>  
(PC+6).bp15~8→mem8(SP+1)  
(PC+6).H→mem8(SP+2).bp7,  
0→mem8(SP+2).bp6~2,  
(PC+6).bp17~16→mem8(SP+2).bp1~0  
PC+6+d16(label)+H→PC  
SP-3→SP,(PC+7).bp7~0→mem8(SP)  
JSR label  
0011 1001 1aaH <abs 18.b p15～ 0..>  
(PC+7).bp15~8→mem8(SP+1)  
(PC+7).H→mem8(SP+2).bp7,  
0→mem8(SP+2).bp6~2,  
(PC+7).bp17~16→mem8(SP+2).bp1~0  
abs18(label)+H→PC  
JSRV (tbl4)  
SP-3→SP,(PC+3).bp7~0→mem8(SP)  
1111 1110 <t4>  
(PC+3).bp15~8→mem8(SP+1)  
(PC+3).H→mem8(SP+2).bp7  
0→mem8(SP+2).bp6~2,  
(PC+3).bp17~16→mem8(SP+2).bp1~0  
mem8(x'004080+tbl4<<2)→PC.bp7~0  
mem8(x'004080+tbl4<<2+1)→PC.bp15  
~8  
mem8(x'004080+tbl4<<2+2).bp7→PC.H  
mem8(x'004080+tbl4<<2+2).bp1~0→  
　　　　　　　　　　　PC.bp17~16  
2
1
132  
NOP  
NOP  
PC+2→PC  
–
–
–
–
0000 0000  
Note: "Page" refers to the corresponding page in the Instruction Manual.  
∗1　d7 sign extended  
∗2　d11 sign extended  
∗3　d12 sign extended  
∗4　d16 sign extended  
∗5　aa=abs18.17～16  
Instruction Set 145  
Chapter 10 Appendices  
M N101C00 SERIES INSTRUCTION SET  
Flag  
Group  
M nem onic  
Operation  
CodeCycle Re-  
M achine Code  
7
NotesPage  
Size  
peat  
Expand 1  
2
3
4
5
6
8
9
10  
11  
VF NF CF ZF  
2
7
RTS  
RTS  
m em 8(SP)→(PC).bp7～0  
m em 8(SP+1)→(PC).bp15～8  
m em 8(SP+2).bp7→(PC).H  
m em 8(SP+2).bp1～0→(PC).bp17～16  
－ － － －  
133  
0000 0001  
SP+3→SP  
2
11  
RTI  
RTI  
m em 8(SP)→PSW  
● ● ● ●  
0000 0011  
134  
m em 8(SP+1)→(PC).bp7～0  
m em 8(SP+2)→(PC).bp15～8  
m em 8(SP+3).bp7→(PC).H  
m em 8(SP+3).bp1～0→(PC).bp17～16  
m em 8(SP+4)→HA-l  
m em 8(SP+5)→HA-h  
SP+6→SP  
Control instruction  
REP REP im m 3  
3
2
im m 3→RPC  
－ － － －  
※1  
135  
0010 0001 1rep  
Note: "Page" refers to the corresponding page in the Instruction Manual.  
∗1　Number of repeats is 0 when imm3=0.  
Ver2.0(1997.9.26)  
146 Instruction Set  
Chapter 10 Appendices  
8-3 Instruction Map  
M N101C00 SERIES INSTRUCTION M AP  
1st nibble\2nd nibble  
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0 NOP  
RTS  
M OV #8,(io8)  
RTI  
CM P #8,(abs8)/(abs12) POP An  
ADD #8,Dm  
OR #8,Dm  
M OVW #8,DW m M OVW #8,Am  
AND #8,Dm  
1 JSR d12(label) JSR d16(label) M OV #8,(abs8)/(abs12) PUSH An  
2 W hen the extension code isb'0010'  
3
W hen the extension code isb'0011'  
4 M OV (abs12),Dm  
5 M OV Dn,(abs12)  
6 M OV (io8),Dm  
7 M OV Dn,(io8)  
8 ADD #4,Dm  
M OV (abs8),Dm  
M OV Dn,(abs8)  
M OV (d4,SP),Dm  
M OV Dn,(d4,SP)  
SUB Dn,Dn  
M OV (An),Dm  
M OV Dn,(Am )  
M OV (d8,An),Dm  
M OV Dn,(d8,Am )  
BGE d7 BRA d7 BEQ d7 BNE d7 BCC d7 BCS d7 BLT d7 BLE d7  
9 BEQ d4  
BNE d4  
M OVW DW n,(HA) M OVW An,(HA) BGE d11 BRA d11 BEQ d11 BNE d11 BCC d11 BCS d11 BLT d11 BLE d11  
A
B
C
D
E
M OV Dn,Dm /M OV #8,Dm  
BSET (abs8)bp  
CM P #8,Dm  
BCLR (abs8)bp  
M OVW (abs8),Am M OVW (abs8),DW m CBEQ #8,Dm ,d7  
M OVW An,(abs8) M OVW DW n,(abs8) CBNE #8,Dm ,d7  
M OVW (d4,SP),Am M OVW (d4,SP),DW m POP Dn  
CM PW #16,DW m M OVW #16,DW m  
CM PW #16,Am M OVW #16,Am  
ADDW #4,Am BRA d4  
M OV Dn,(HA)  
M OVW (An),DW m  
F M OVW DW n,(Am )  
M OVW An,(d4,SP) M OVW DW n,(d4,SP) PUSH Dn  
ADDW #8,SP ADDW #4,SP JSRV (tbl4)  
Extension code: b'0010'  
2nd nibble\3rd nibble  
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0 M OVW An,Am  
CM PW An,Am  
M OVW SP,Am M OVW An,SP BTST #8,Dm  
REP #3  
1
2
3
JM P (A0) JSR (A0) JM P (A1) JSR (A1) M OV PSW ,Dm  
BGT d7 BHId7 BLS d7 BNC d7 BNS d7 BVC d7 BVS d7 NOT Dn  
BGT d11 BHId11 BLS d11 BNC d11 BNS d11 BVC d11 BVS d11 ASR Dn  
ROR Dn  
LSR Dn  
4 SUBW DW n,DW m  
5 ADDW DW n,DW m  
6 M OV (d16,SP),Dm  
7 M OV Dn,(d16,SP)  
SUBW #16,DW m SUBW #16,Am SUBW DW n,Am  
ADDW #16,DW m ADDW #16,Am ADDW DW n,Am  
M OVW DW n,Am  
CM PW DW n,Am  
M OV (d8,SP),Dm  
M OV Dn,(d8,SP)  
M OV (d16,An),Dm  
M OV Dn,(d16,Am )  
ADDUW Dn,Am  
ADDSW Dn,Am  
8
M OVW DW n,DW m (NOPL @ n=m ) CM PW DW n,DW m  
9 EXT Dn,DW m  
AND #8,PSW OR #8,PSW M OV Dn,PSW  
A
B
C
D
E
F
SUB Dn,Dm /SUB #8,Dm  
SUBC Dn,Dm  
M OV (abs16),Dm  
M OV Dn,(abs16)  
M OVW (abs16),Am M OVW (abs16),DW m CBEQ #8,Dm ,d12  
M OVW An,(abs16) M OVW DW n,(abs16) CBNE #8,Dm ,d12  
M OVW An,DW m  
CBEQ #8,(abs8),d7/d11  
CBNE #8,(abs8),d7/d11  
M OVW (d16,SP),Am M OVW (d16,SP),DW m M OVW (d8,SP),Am M OVW (d8,SP),DW m M OVW (An),Am  
M OVW An,(d16,SP) M OVW DW n,(d16,SP) M OVW An,(d8,SP) M OVW DW n,(d8,SP) M OVW An,(Am )  
ADDW #8,Am DIVU  
ADDW #16,SP  
M ULU  
Instruction Map 147  
Chapter 10 Appendices  
Extension code: b'0011'  
2nd nibble\3rd nibble  
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0 TBZ (abs8)bp,d7  
1 TBNZ (abs8)bp,d7  
2 CM P Dn,Dm  
TBZ (abs8)bp,d11  
TBNZ (abs8)bp,d11  
3 ADD Dn,Dm  
4 TBZ (io8)bp,d7  
5 TBNZ (io8)bp,d7  
6 OR Dn,Dm  
TBZ (io8)bp,d11  
TBNZ (io8)bp,d11  
7 AND Dn,Dm  
8 BSET (io8)bp  
9 JM P abs18(label)  
BCLR (io8)bp  
JSR abs18(label)  
A
B
C
D
E
XOR Dn,Dm /XOR #8,Dm  
ADDC Dn,Dm  
BSET (abs16)bp  
BTST (abs16)bp  
TBZ (abs16)bp,d7  
BCLR (abs16)bp  
cm p #8,(abs16)  
m ov#8,(abs16)  
CBEQ #8,(abs16),d7/11  
CBNE #8,(abs16),d7/11  
TBZ (abs16)bp,d11  
TBNZ (abs16)bp,d11  
F TBNZ (abs16)bp,d7  
Ver2.0(1997.9.26)  
148 Instruction Map  
Chapter 10 Appendices  
8-4 Summary of Special Function Registers  
BitSym bol  
Reference  
page  
Register  
CPUM  
Address  
Bit7  
Bit6  
Bit5  
Bit4  
Bit3  
Bit2  
Bit1  
Bit0  
OSC0  
STOP  
STOP  
HALT  
HALT  
OSC1  
M N101C00 seriesﾞ  
LSIM anual  
X’3F00’  
X’3F01’  
X’3F02’  
X’3F03’  
X’3F0E’  
X’3F10’  
X’3F11’  
X’3F12’  
X’3F13’  
Mustbeset  
to"0"  
Oscillation control  
transferrequestrtansferrequest  
IOW 1  
IOW 0  
IVBA  
IRW E  
30  
M EM CTR  
W DCTR  
DLYCTR  
Specifiesbaseaddress  
ofinterruptvectortable  
II/0 buswaitvalue set  
W DEN  
89  
89  
W atchdog  
tim ertable  
DLYS1  
DLYS0  
Setsoscillation  
stabilization waitperiod  
EXADV  
P0OUT  
P0OUT6  
P0OUT2 P0OUT1 P0OUT0  
Port0 output  
　41，45  
　41，45  
　41，45  
P1OUT4 P1OUT3 P1OUT2 P1OUT1 P1OUT0  
Port1 output  
P1OUT  
P2OUT  
P2OUT7  
Port2 output  
Disablesto use  
Disablesto use  
X’3F14’  
X’3F15’  
X’3F16’  
X’3F17’  
X’3F18’  
X’3F1F’  
X’3F20’  
X’3F21’  
X’3F22’  
X’3F23’  
Disablesto use  
P6OUT  
P6OUT7 P6OUT6 P6OUT5 P6OUT4 P6OUT3 P6OUT2 P6OUT1 P6OUT0  
　41，45  
　41，45  
　41，45  
Port6 output  
P7OUT0  
P7OUT  
P8OUT  
Disablesto use  
P0IN  
Port7  
output  
P8OUT7 P8OUT6 P8OUT5 P8OUT4 P8OUT3 P8OUT2 P8OUT1 P8OUT0  
Port8 output  
P0IN2  
P1IN2  
P0IN1  
P0IN0  
P1IN0  
P2IN0  
P0IN6  
　41，45  
　41，45  
　41，45  
Port0 input  
P1IN4  
P1IN3  
P1IN1  
P1IN  
Port1 input  
P2IN2  
P2IN1  
P2IN  
Port2input  
Disablesto use  
149  
Summary of Special Function Registers  
Chapter 10 Appendices  
BitSym bol  
Bit4  
Reference  
Page  
Register  
Address  
Bit7  
Bit6  
Bit5  
Bit3  
Bit2  
Bit1  
Bit0  
X’3F24’  
Disablesto use  
Disablesto use  
X’3F25’  
X’3F26’  
X’3F27’  
P6IN2  
P6IN7  
P6IN6  
P6IN5  
P6IN4  
P6IN3  
P8IN3  
P6IN1  
P6IN0  
P7IN0  
41，45  
41，45  
P6IN  
P7IN  
Port6 input  
Port7  
input  
P8IN7  
PAIN7  
P8IN6  
PAIN6  
P0DIR6  
P8IN5  
PAIN5  
P8IN4  
PAIN4  
P8IN2  
PAIN2  
P8IN1  
PAIN1  
P8IN0  
PAIN0  
P8IN  
41，45  
41，45  
41，45  
41，45  
X’3F28’  
X’3F2A’  
X’3F30’  
X’3F31’  
X’3F33’  
Port8 input  
PAIN3  
PAIN  
P0DIR  
Port A input  
P0DIR2  
P0DIR1  
P0DIR0  
Port0 I/O direction control  
P1DIR4 P1DIR3 P1DIR2 P1DIR1 P1DIR0  
Port1 I/O direction control  
P1DIR  
Disablesto use  
Disablesto use  
X’3F34’  
X’3F35’  
X’3F36’  
X’3F37’  
X’3F38’  
X’3F39’  
X’3F3A’  
X’3F3C’  
X’3F40’  
X’3F41’  
Disablesto use  
P6DIR  
P6DIR7 P6DIR6 P6DIR5 P6DIR4 P6DIR3 P6DIR2 P6DIR1 P6DIR0  
Port6 I/O direction control  
41，45  
41，45  
41，45  
41，46  
41，46  
P7DIR0  
P7DIR  
Port7I/O  
directioncontrol  
P8DIR7 P8DIR6 P8DIR5 P8DIR4 P8DIR3 P8DIR2 P8DIR1 P8DIR0  
Port8 I/O direction control  
P8DIR  
P14TCO P13TCO P12TCO  
I/O port/Specialfunction pin control  
P10TCO  
P1OM D  
PAAIN5 PAAIN4 PAAIN3 PAAIN2 PAAIN1 PAAIN0  
I/O port/Specialfunction pin control  
PAIM D  
Disablesto use  
P0PLU  
P0PLU6  
P0PLU2 P0PLU1 P0PLU0  
Port0pull-upresistorON/OFFcontrol  
41，45  
42，45  
P1PLU4 P1PLU3 P1PLU2 P1PLU1 P1PLU0  
Port1 pull-up resistorON/OFF control  
P1PLU  
150  
Summary of Special Function Registers  
Chapter 10 Appendices  
BitSym bol  
Bit3  
Reference  
Page  
Register  
P2PLU  
Address  
Bit7  
Bit6  
Bit5  
Bit4  
Bit2  
Bit1  
Bit0  
P2PLU2 P2PLU1 P2PLU0  
42，45  
X’3F42’  
X’3F43’  
X’3F44’  
X’3F45’  
X’3F46’  
X’3F47’  
X’3F48’  
X’3F4A’  
Port2 pull-up resistorON/OFF control  
Disablesto use  
Disablesto use  
Disablesto use  
P6PLU  
P6PLU7 P6PLU6 P6PLU5 P6PLU4 P6PLU3 P6PLU2 P6PLU1  
Port6 pull-up resistorON/OFF control  
P6PLU0  
42，45  
P7PLUD0  
42，45  
42，45  
42，45  
P7PLUD  
P8PLU  
Portpull-uppulldown  
resistorON/OFFcontrol  
P8PLU7 P8PLU6 P8PLU5 P8PLU4 P8PLU3 P8PLU2 P8PLU1 P8PLU0  
Port8 pull-up resistorON/OFF control  
PAPLUD5 PAPLUD4 PAPLUD3 PAPLUD2 PAPLUD1 PAPLUD0  
PAPLUD7 PAPLUD6  
PortA pull-up pull-down resistorON/OFF control  
P21M PARDW N  
PAPLUD  
FLOAT1  
P7RDW N  
X’3F4B’  
X’3F4C’  
42，46  
P21input PortA pullpﾟPort7pullupﾟ  
modeselectionpulldownsel. pulldownsel.  
Disablesto use  
SC0M D0  
SC0LNG2 SC0LNG1 SC0LNG0  
SC0STE  
SC0CE0 SC0CE1 SC0DIR  
108  
109  
110  
X’3F50’  
X’3F51’  
Synchrounouserial  
starteditionselect  
Receivedatainputedge Startbitsetup  
Transm itdata outputedge fortransmit  
Transferbitcount  
SC0CKM  
SC0CK0 SC0BRKF SC0ERE  
SC0TRI  
SC0CK1  
SC0M D1  
Breakstatus  
rec.monitor  
Trans/recinterrup  
Errormonitor  
requestflag  
Select1/8period Clocksourceselection  
offreq.  
SC0BRKE SC0FM 1 SC0FM 0 SC0PM 1 SC0PM 0 SC0NPE  
X’3F52’  
X’3F53’  
SC0M D2  
Controlbreak  
statustrans.  
Enables  
parity  
Specifiesadded bit  
Specifiesfram e m ode  
SC0IOM SC0SBOM SC0SBTM SC0SBOS SC0SBIS SC0SBTS  
SBI0/SBO0 SBO0pin SelectSBT SelectSBO ControlSBI SelectSBT0  
111  
112  
107  
107  
SC0M D3  
SC0CTR  
SC0TRB  
pin connection selection pin form at pin function  
SC0BSY SC0CM D SC0FEF SC0PEK SC0ORE  
Statusof Selectsync.  
serialbus seroalUART  
SC0TRB7 SC0TRB6 SC0TRB5 SC0TRB4 SC0TRB3  
input  
pin function  
X’3F54’  
X’3F55’  
X’3F56’  
Detectframing Detect parity Detectoverrun  
error error error  
SC0TRB2 SC0TRB1 SC0TRB0  
Serialinterface 0 transm it/receive shiftregister  
SC0RXB3 SC0RXB2 SC0RXB1  
SC0RXB0  
SC0RXB7 SC0RXB6 SC0RXB5 SC0RXB4  
Serialinterface 0 receive data buffer  
SC0RXB  
X’3F57’  
X’3F58’  
Disablesto use  
Disablesto use  
151  
Summary of Special Function Registers  
Chapter 10 Appendices  
BitSym bol  
Bit3  
Reference  
Page  
Address  
Register  
Bit7  
Bit6  
Bit5  
Bit4  
Bit2  
Bit1  
Bit0  
X’3F59’  
X’3F5A’  
X’3F5B’  
X’3F5C’  
X’3F5D’  
X’3F60’  
Disablesto use  
Disablesto use  
Disablesto use  
Disablesto use  
Disablesto use  
Disablesto use  
Disablesto use  
　　－  
　　82  
　82  
X’3F61’  
TM 2BC7 TM 2BC6 TM 2BC5 TM 2BC4 TM 2BC3 TM 2BC2 TM 2BC1 TM 2BC0  
Binarycounter2  
X’3F62’  
X’3F63’  
TM 2BC  
TM 3BC  
TM 3BC7 TM 3BC6 TM 3BC5 TM 3BC4 TM 3BC3 TM 3BC2 TM 3BC1 TM 3BC0  
Binarycounter3  
TM 4BCL7 TM 4BCL6 TM 4BCL5 TM 4BCL4 TM 4BCL3 TM 4BCL2 TM 4BCL1 TM 4BCL0  
X’3F64’  
X’3F65’  
　83  
　83  
Binarycounter4（Lower8 bits）  
TM 4BCH7 TM 4BCH6 TM 4BCH5 TM 4BCH4TM 4BCH3 TM 4BCH2 TM 4BCH1TM 4BCH0  
Binarycounter4 (Upper8 bits）  
TM 4BCL  
TM 4BCH  
TM 4ICL7 TM 4ICL6 TM 4ICL5 TM 4ICL4 TM 4ICL3 TM 4ICL2 TM 4ICL1 TM 4ICL0  
Inputcapture register（Lower8 bits）  
X’3F66’  
TM 4ICL  
84  
TM 4ICH7 TM 4ICH6 TM 4ICH5 TM 4ICH4 TM 4ICH3 TM 4ICH2 TM 4ICH1 TM 4ICH0  
Inputcapture reigster(Upper8 bits)  
X’3F67’  
X’3F68’  
X’3F70’  
TM 4ICH  
TM 5BC  
84  
84  
TM 5BC7 TM 5BC6 TM 5BC5 TM 5BC4 TM 5BC3  
Binarycounter5  
TM 5BC2 TM 5BC1 TM 5BC0  
Disablesto use  
－
－
82  
82  
83  
X’3F71’ Disablesto use  
TM 2OC7 TM 2OC6 TM 2OC5 TM 2OC4 TM 2OC3 TM 2OC2 TM 2OC1 TM 2OC0  
Com pare register2  
X’3F72’  
TM 2OC  
TM 3OC7 TM 3OC6 TM 3OC5 TM 3OC4 TM 3OC3 TM 3OC2 TM 3OC1 TM 3OC0  
Com pare register3  
X’3F73’  
X’3F74’  
TM 3OC  
TM 4OCL7 TM 4OCL6 TM 4OCL5 TM 4OCL4 TM 4OCL3 TM 4OCL2 TM 4OCL1TM 4OCL0  
TM 4OCL  
Com pare register4（Lower8 bits）  
152  
Summary of Special Function Registers  
Chapter 10 Appendices  
BitSym bol  
Bit3  
Reference  
Page  
Register  
Address  
Bit7  
Bit6  
Bit5  
Bit4  
Bit2  
Bit1  
Bit0  
X’3FE0’ Disablesto use  
　　  
W DIR  
NM ICR  
X’3FE1’  
　　34  
W atchdoginterrupt  
requestflag  
IRQ0LV1 IRQ0LV0  
REDG0  
IRQ0IE  
Interrupt  
IRQ0IR  
Interrupt  
X’3FE2’  
X’3FE3’  
X’3FE4’  
X’3FE5’  
X’3FE6’  
X’3FE7’  
X’3FE8’  
X’3FE9’  
X’3FEA’  
IRQ0ICR  
IRQ1ICR  
　　34  
　　34  
Interruplevelflagfor  
externalinterrupt  
Externalinterrupt  
validedgeflag  
enableflag requestflag  
IRQ1LV1 IRQ1LV0 REDG1  
IRQ1IE  
Interrupt  
IRQ1IR  
Interrupt  
Interruptlevelflag  
forexternalinterrupt  
Externalinterrupt  
valudedgeflag  
enableflag requestflag  
Disablesto use  
Disablesto use  
TM 2ICR  
TM 2IE  
TM 2IR  
TM 2LV1 TM 2LV0  
　　35  
　　35  
Interruptlevelflagfor  
timer2interrupt  
Interrupt  
enableflag requestflag  
Interrupt  
TBIE  
TBIR  
TBLV1  
TBLV0  
TBICR  
SC0ICR  
Interruptlevelflagfor  
timebaseinterrupt  
Interrupt  
enableflag requestflag  
Interrupt  
SC0LV1 SC0LV0  
SC0IE  
Interrup  
SC0IR  
　　35  
　
Interruptlevelflagfor  
serial0interrupt  
Interrupt  
enableflag requestflag  
Disablesto use  
ADICR  
ADIE  
ADIR  
ADLV1  
ADLV0  
　　35  
　　34  
Interrupt  
Interrupt  
Interruplevelflagfor  
A/D interrupt  
enableflag requestflag  
ﾞ
REDG2  
IRQ2LV1 IRQ2LV0  
IRQ2IE  
Interrup  
IRQ2IR  
Interrupt  
IRQ2ICR  
X’3FEB’  
X’3FEC’  
X’3FED’  
X’3FEE’  
X’3FEF’  
X’3FF0’  
X’3FF1’  
X’3FF2’  
Interruptlevelflag  
forexternalinterrupt  
Externalinterrupt  
validedgeflag  
enableflag requestflag  
IRQ3ICR  
Disablesto use  
TM 3IE  
　　35  
　　35  
　　35  
TM 3ICR  
TM 4ICR  
Interruptlevelflag  
fortimer3interrupt  
Interrupt  
enableflag requestflag  
Interrupt  
TM 4IE  
Interruptlevelflag  
fortimer4interrupt  
Interrupt  
enableflag requestflag  
Interrupt  
TM 5IE  
TM 5ICR  
Interruptlevelflag  
fortimer5interrupt  
Interrupt  
enableflag requestflag  
Interrupt  
Disablesto use  
Disablesto use  
153  
Summary of Special Function Registers  
Chapter 10 Appendices  
BitSym bol  
Bit3  
Reference  
Page  
Register  
Address  
Bit7  
Bit6  
Bit5  
Bit4  
Bit2  
Bit1  
Bit0  
X’3FE0’ Disablesto use  
　　  
W DIR  
NM ICR  
X’3FE1’  
　　34  
W atchdoginterrupt  
requestflag  
IRQ0LV1 IRQ0LV0  
REDG0  
IRQ0IE  
Interrupt  
IRQ0IR  
Interrupt  
X’3FE2’  
X’3FE3’  
X’3FE4’  
X’3FE5’  
X’3FE6’  
X’3FE7’  
X’3FE8’  
X’3FE9’  
X’3FEA’  
IRQ0ICR  
IRQ1ICR  
　　34  
　　34  
Interruplevelflagfor  
externalinterrupt  
Externalinterrupt  
validedgeflag  
enableflag requestflag  
IRQ1LV1 IRQ1LV0 REDG1  
IRQ1IE  
Interrupt  
IRQ1IR  
Interrupt  
Interruptlevelflag  
forexternalinterrupt  
Externalinterrupt  
valudedgeflag  
enableflag requestflag  
Disablesto use  
Disablesto use  
TM 2ICR  
TM 2IE  
TM 2IR  
TM 2LV1 TM 2LV0  
　　35  
　　35  
Interruptlevelflagfor  
timer2interrupt  
Interrupt  
enableflag requestflag  
Interrupt  
TBIE  
TBIR  
TBLV1  
TBLV0  
TBICR  
SC0ICR  
Interruptlevelflagfor  
timebaseinterrupt  
Interrupt  
enableflag requestflag  
Interrupt  
SC0LV1 SC0LV0  
SC0IE  
Interrup  
SC0IR  
　　35  
　
Interruptlevelflagfor  
serial0interrupt  
Interrupt  
enableflag requestflag  
Disablesto use  
ADICR  
ADIE  
ADIR  
ADLV1  
ADLV0  
　　35  
　　34  
Interrupt  
Interrupt  
Interruplevelflagfor  
A/D interrupt  
enableflag requestflag  
ﾞ
REDG2  
IRQ2LV1 IRQ2LV0  
IRQ2IE  
Interrup  
IRQ2IR  
Interrupt  
IRQ2ICR  
X’3FEB’  
X’3FEC’  
X’3FED’  
X’3FEE’  
X’3FEF’  
X’3FF0’  
X’3FF1’  
X’3FF2’  
Interruptlevelflag  
forexternalinterrupt  
Externalinterrupt  
validedgeflag  
enableflag requestflag  
IRQ3ICR  
Disablesto use  
TM 3IE  
　　35  
　　35  
　　35  
TM 3ICR  
TM 4ICR  
Interruptlevelflag  
fortimer3interrupt  
Interrupt  
enableflag requestflag  
Interrupt  
TM 4IE  
Interruptlevelflag  
fortimer4interrupt  
Interrupt  
enableflag requestflag  
Interrupt  
TM 5IE  
TM 5ICR  
Interruptlevelflag  
fortimer5interrupt  
Interrupt  
enableflag requestflag  
Interrupt  
Disablesto use  
Disablesto use  
154  
Summary of Special Function Registers  
MN101C115 / 117  
LSI User's Manual  
August,1999 1st Edition 1st Printing  
Issued by Matsushita Electric Industrial Co., Ltd.  
Matsushita Electronics Corporation  
©
©
Matsushita Electric Industrial Co., Ltd.  
Matsushita Electronics Corporation  
Semiconductor Company Matsushita Electronics Corporation  
Nagaokakyo, Kyoto, 617-8520 Japan  
Tel: (075) 951-8151  
http://www.mec.panasonic.co.jp  
SALES OFFICES  
■ U.S.A. SALES OFFICE  
■ HONG KONG SALES OFFICE  
Panasonic Industrial Company  
[PIC]  
Panasonic Shun Hing Industrial Sales (Hong Kong)  
● New Jersey Office:  
Co., Ltd.  
[PSI(HK)]  
2 Panasonic Way, Secaucus, New Jersey 07094  
Tel: 201-392-6173  
Fax: 201-392-4652  
11/F, Great Eagle Centre, 23 Harbour Road,  
Wanchai, Hong Kong.  
Tel: 2529-7322  
● Milpitas Office:  
Fax: 2865-3697  
1600 McCandless Drive, Milpitas, California 95035  
Tel: 408-945-5630  
Fax: 408-946-9063  
■ TAIWAN SALES OFFICE  
Panasonic Industrial Sales Taiwan Co.,Ltd.  
● Head Office:  
[PIST]  
● Chicago Office:  
1707 N. Randall Road, Elgin, Illinois 60123-7847  
Tel: 847-468-5829  
Fax: 847-468-5725  
6th Floor, Tai Ping & First Building No.550. Sec.4,  
Chung Hsiao E. Rd. Taipei 10516  
Tel: 2-2757-1900  
● Atlanta Office:  
Fax: 2-2757-1906  
1225 Northbrook Parkway, Suite 1-151,  
Suwanee, Georgia 30174  
Tel: 770-338-6940  
● Kaohsiung Office:  
6th Floor, Hsien 1st Road Kaohsiung  
Tel: 7-223-5815  
Fax: 7-224-8362  
Fax: 770-338-6849  
● San Diego Office:  
9444 Balboa Avenue, Suite 185  
San Diego, California 92123  
Tel: 619-503-2940  
■ SINGAPORE SALES OFFICE  
Panasonic Semiconductor of South Asia  
300 Beach Road # 16-01  
The Concourse Singapore 199555  
Tel: 390-3688  
[PSSA]  
Fax: 619-715-5545  
■ CANADA SALES OFFICE  
Fax: 390-3689  
Panasonic Canada Inc.  
[PCI]  
5700 Ambler Drive Mississauga, Ontario, L4W 2T3  
Tel: 905-624-5010  
Fax: 905-624-9880  
■ MALAYSIA SALES OFFICE  
Panasonic Industrial Company (Malaysia) Sdn. Bhd.  
● Head Office:  
[PICM]  
Tingkat 16B Menara PKNS PJ No.17,Jalan Yong  
Shook Lin 46050 Petaling Jaya Selangor Darul Ehsan  
Malaysia  
Tel: 03-7516606  
Fax: 03-7516666  
■ GERMANY SALES OFFICE  
Panasonic Industrial Europe G.m.b.H.  
● Munich Office:  
[PIEG]  
Hans-Pinsel-Strasse 2 85540 Haar  
Tel: 89-46159-156  
Fax: 89-46159-195  
● Penang Office:  
Suite 20-17,MWE PLAZA No.8,Lebuh Farquhar,10200  
Penang Malaysia  
■ U.K. SALES OFFICE  
Tel: 04-2625550  
Fax: 04-2619989  
● Johore Sales Office:  
Panasonic Industrial Europe Ltd.  
● Electric component Group:  
[PIEL]  
Willoughby Road, Bracknell, Berkshire RG12 8FP  
Tel: 1344-85-3773  
Fax: 1344-85-3853  
39-01 Jaran Sri Perkasa 2/1,Taman Tampoi  
Utama,Tampoi 81200 Johor Bahru,Johor Malaysia  
Tel: 07-241-3822  
Fax: 07-241-3996  
■ FRANCE SALES OFFICE  
■ CHINA SALES OFFICE  
Panasonic Industrial Europe G.m.b.H.  
● Paris Office:  
[PIEG]  
[PIEG]  
Panasonic SH Industrial Sales (Shenzhen)  
270, Avenue de President Wilson  
93218 La Plaine Saint-Denis Cedex  
Tel: 14946-4413  
Co., Ltd.  
[PSI(SZ)]  
7A-107, International Business & Exhibition Centre,  
Futian Free Trade Zone, Shenzhen 518048  
Tel: 755-359-8500  
Fax: 14946-0007  
Fax: 755-359-8516  
Panasonic Industrial (Shanghai) Co., Ltd.  
1F, Block A, Development Mansion, 51 Ri Jing Street,  
Wai Gao Qiao Free Trade Zone, Shanghai 200137  
Tel: 21-5866-6114  
[PICS]  
■ ITALY SALES OFFICE  
Panasonic Industrial Europe G.m.b.H.  
● Milano Office:  
Via Lucini N19, 20125 Milano  
Tel: 2678-8266  
Fax: 21-5866-8000  
Fax: 2668-8207  
■ THAILAND SALES OFFICE  
Panasonic Industrial (Thailand) Ltd.  
[PICT]  
252/133 Muang Thai-Phatra Complex Building,31st  
Fl.Rachadaphisek Rd.,Huaykwang,Bangkok 10320  
Tel: 02-6933407  
Fax: 02-6933423  
080499  

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