Epson SED 1520 Series User Manual

Series  
Technical Manual  
SED1520  
LCD driver with RAM  
NOTICE  
No parts of this material may be reproduced or duplicated in any form or by any means without the written  
permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice.  
Seiko Epson does not assume any liability of any kind aristing out of any inaccuracies contained in this  
material or due to its application or use in any product or circuit and, further, there is no representation that  
this material is applicable to products requiring high level reliability, such as, medical products. Moreover,  
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or copyright infringement of a third party. This material or portions thereof may contain technology or the  
subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Control  
Law of Japan and may require an export licence from teh Ministry of International Trade and Industry or other  
approval from another government agency.  
© Seiko Epson corporation 1998 All right reserved.  
i8088 and i8086 are registered trademarks of Intel Corporation.  
Z80 is registered trademark of Zilog Corporation.  
V20 and V30 are registered trademarks of Nippon Electric Corporation.  
SED1500 Series  
Selection Guide  
LCD drivers with RAM for small-  
and medium-sized displays  
Ultra-low power consumption and on-chip RAM make this series ideal for compact  
LCD-based equipment.  
SED1500 series  
Supply voltage LCD voltage  
Display  
RAM (bits)  
Microprocessor Frequency  
Application/additional  
features  
Part number  
Duty  
1/4  
Segment Common  
Package  
range (V)  
range (V)  
interface  
(KHz)  
SED1510D0C  
SED1510D0B  
SED1510F0C  
SED1510F0E  
SED1511D0A  
SED1520D0A  
SED1520D0B  
SED1520F0A  
SED1520F0C  
SED1520T0A  
SED1520DAA  
SED1520DAB  
SED1520FAA  
SED1520FAC  
SED1520TAA#  
SED1521D0A  
SED1521D0B  
SED1521F0A  
SED1521F0C  
SED1521T0A#  
SED1521DAA  
SED1521DAB  
SED1521FAA  
SED1521FAC  
SED1521TAA#  
SED152AD0A  
SED1522D0A  
SED1522D0B  
SED1522F0A  
SED1522F0C  
SED1522T0A#  
SED1522DAA  
SED1522DAB  
SED1522FAA  
SED1522FAC  
SED1522TAA#  
SED1540D0A  
SED1540D0B  
SED1540F0A  
AI pad chip  
Au bump chip  
QFP12-48pin  
QFP6-60pin  
AI pad chip  
AI pad chip  
Au bump chip  
QFP5-100pin  
QFP15-100pin  
TCP  
Small segment-type LCD  
display. Command and data  
interface  
18 (internal)  
0.9–6.0  
1.8–6.0  
32  
4
128  
Serial  
Small segment-type LCD dislays. Data only  
interface  
18  
(internal,  
external)  
Dot-matrix LCD displays  
Extension driver is the  
SED1521.  
1/16,1/32  
61  
16  
AI pad chip  
Au bump chip  
QFP5-100pin  
QFP15-100pin  
TCP  
2
(external)  
AI pad chip  
Au bump chip  
QFP5-100pin  
QFP15-100pin  
TCP  
18  
(external)  
Extension driver for the  
SED1520 and SED1522  
3.5–13  
1/8–1/32  
80  
AI pad chip  
Au bump chip  
QFP5-100pin  
QFP15-100pin  
TCP  
2,560  
8-bit parallel  
2.4–7.0  
2
(external)  
Al pad chip  
AI pad chip  
Au bump chip  
QFP5-100pin  
QFP15-100pin  
TCP  
P-substrate version of SED1521  
18  
(internal,  
external)  
Dot-matrix LCD displays  
Extension driver is the  
SED1521.  
1/8,1/16  
69  
8
AI pad chip  
Au bump chip  
QFP5-100pin  
QFP15-100pin  
TCP  
2
(external)  
AI pad chip  
Au bump chip  
QFP5-100pin  
18 (internal)  
4 (external)  
3.5–11  
1/3,1/4  
73  
3, 4  
Segment-type displays  
# : Planning TCP : Tape Carrier Package  
Supply voltage LCD voltage  
Display  
RAM (bits)  
Microprocessor Frequency  
Application/additional  
features  
Part number  
Duty  
Segment Common  
Package  
range (V)  
range (V)  
interface  
(KHz)  
SED1560D0A  
SED1560DAA  
SED1560D0B  
SED1560DAB  
SED1560T0B  
SED1560TQA  
SED1561D0A  
SED1561DAA  
SED1561D0B  
SED1561DAB  
SED1561T0B  
SED1561TAB  
SED1561TQA  
SED1562D0A  
SED1562D0B  
SED1562T0B  
SED1562TQA  
SED1565D0B  
SED1565D1B*  
SED1565D2B  
SED1565T0A  
SED1565T0B  
SED1565T0C  
SED1566D0B  
SED1566D1B*  
SED1566D2B  
SED1566T0A  
SED1567D0B  
SED1567D1B*  
SED1567D2B  
SED1567T0B  
SED1567T0C  
SED1568D0B  
SED1569D0B  
SED1569T**  
SED1570D0A  
SED1570D0B  
SED1526D*A  
SED1526D*B  
SED1526F*A  
SED1526T*A  
SED1528D*A  
SED1528D*B  
SED1528F*A  
SED1528T*A  
Al pad chip  
Al pad chip  
Au bump chip  
Au bump chip  
TCP  
1/48, 1/49  
1/64, 1/65  
102  
65  
QTCP  
Al pad chip  
Al pad chip  
Au bump chip  
Au bump chip  
TCP  
Built-in power circuit for LCD  
(voltage tripler)  
SED15600B (1/9 bias)  
SED1560AB (1/7 bias)  
SED15610B (1/7 bias)  
SED1561AB (1/5 bias)  
166×65  
18  
2.4–6.0  
6.0–16.0  
bits  
1/24, 1/25  
1/32, 1/33  
134  
150  
33  
TCP  
QTCP  
Al pad chip  
Au bump chip  
TCP  
1/16, 1/17  
(1/5bias)  
17  
65  
8-bit parallel  
or Serial  
QTCP  
Au bump chip  
Au bump chip  
Au bump chip  
TCP  
1/65  
(1/7, 1/9 bias)  
TCP  
TCP  
Au bump chip  
Au bump chip  
Au bump chip  
TCP  
1/49  
49  
33  
132×65  
Built-in power circuit for LCD  
(DC/DC×4)  
33  
1.8–5.5  
4.5–16.0  
(1/6, 1/8 bias)  
132  
bits  
Au bump chip  
Au bump chip  
Au bump chip  
TCP  
1/33  
(1/5, 1/6 bias)  
TCP  
1/55 (1/6, 1/8 bias)  
1/53  
55  
53  
Au bump chip  
Au bump chip  
TCP  
(1/6, 1/8 bias)  
200×80  
Al pad chip  
Au bump chip  
Al pad chip  
Au bump chip  
QFP5-128pin  
TCP  
2.7–5.5  
2.4–6.0  
8.0–20.0  
3.5–  
1/64–1/200  
4-bit parallel  
Built-in self-refreshing function  
bits  
Built-in power circuit for LCD  
(voltage tripler)  
SED15260  
(VREG)  
SED1526E✽  
(no VREG)  
SED1526A✽  
(redistribution of COMS)  
SED15280✽  
(VREG)  
SED1528E✽  
(no VREG)  
80  
64  
1/8, 1/9  
17  
1/16, 1/17  
80×33  
8-bit parallel  
or Serial  
20  
Supply  
×3  
bits  
Al pad chip  
Au bump chip  
QFP5-128pin  
TCP  
voltage  
1/32, 1/33  
33  
Supply voltage LCD voltage  
Display  
RAM (bits)  
Microprocessor Frequency  
Application/additional  
features  
Part number  
Duty  
Segment Common  
Package  
range (V)  
range (V)  
interface  
(KHz)  
SED1530D0A  
SED1530DAA  
SED1530D0B  
SED1530DAB  
SED1530TAA  
SED1531D0A  
SED1531D0B  
SED1531T0A  
SED1532D0A  
SED1532DBA  
SED1532D0B  
SED1532DBA  
SED1532T0A  
SED1532TBA  
SED1535D0B*  
Al pad chip  
Al pad chip  
Au bump chip  
Au bump chip  
TCP  
1/32, 1/33  
100  
132  
33  
Built-in power circuit for LCD  
(voltage quadrupler)  
SED1530✽  
Al pad chip  
Au bump chip  
TCP  
(Common: Right side)  
SED153A✽  
132×65  
8-bit parallel  
or Serial  
2.4–6.0  
4.5–16.0  
(Common: Both side)  
SED153B✽  
(Common: Left side)  
SED153F✽  
(no VREG)  
bits  
Al pad chip  
Al pad chip  
Au bump chip  
Au bump chip  
TCP  
1/64, 1/65  
100  
98  
33  
35  
TCP  
1/35  
Au bump chip  
TCP : Tape Carrier Package  
2. SED1520 Series  
Contents  
OVERVIEW ..........................................................................................................................................................2-1  
FEATURES ...........................................................................................................................................................2-1  
BLOCK DIAGRAM ................................................................................................................................................2-2  
PACKAGE OUTLINE ............................................................................................................................................2-3  
PAD ......................................................................................................................................................................2-4  
Pad Arrangement .........................................................................................................................................2-4  
PAD ARRANGEMENT .........................................................................................................................................2-5  
PIN DESCRIPTION ..............................................................................................................................................2-6  
(1) Power Pins .............................................................................................................................................2-6  
(2) System Bus Connection Pins .................................................................................................................2-6  
(3) LCD Drive Circuit Signals .......................................................................................................................2-7  
BLOCK DESCRIPTION ........................................................................................................................................2-8  
System Bus ..................................................................................................................................................2-8  
Display Start Line and Line Count Registers ...............................................................................................2-9  
Column Address Counter.............................................................................................................................2-9  
Page Register ..............................................................................................................................................2-9  
Display Data RAM........................................................................................................................................2-9  
Common Timing Generator Circuit ............................................................................................................2-10  
Display Data Latch Circuit..........................................................................................................................2-10  
LCD Driver Circuit ......................................................................................................................................2-10  
Display Timing Generator ..........................................................................................................................2-10  
Oscillator Circuit (SED1520*0A Only) ........................................................................................................2-11  
Reset Circuit ..............................................................................................................................................2-11  
COMMANDS ......................................................................................................................................................2-14  
Summary....................................................................................................................................................2-14  
Command Description ...............................................................................................................................2-15  
SPECIFICATIONS ..............................................................................................................................................2-20  
Absolute Maximum Ratings .......................................................................................................................2-20  
Electrical Specifications .............................................................................................................................2-20  
APPLICATION NOTES .......................................................................................................................................2-26  
MPU Interface Configuration......................................................................................................................2-26  
LCD Drive Interface Configuration .............................................................................................................2-27  
LCD Panel Wiring Example .......................................................................................................................2-29  
Package Dimensions .................................................................................................................................2-30  
– i –  
SED1520 Series  
OVERVIEW  
FEATURES  
The SED1520 family of dot matrix LCD drivers are  
designed for the display of characters and graphics. The  
drivers generate LCD drive signals derived from bit  
mapped data stored in an internal RAM.  
The drivers are available in two configurations  
The SED1520 family drivers incorporate innovative  
circuit design strategies to achieve very low power  
dissipation at a wide range of operating voltages.  
These features give the designer a flexible means of  
implementing small to medium size LCD displays for  
compact, low power systems.  
• Fast 8-bit MPU interface compatible with 80- and 68-  
family microcomputers  
• Many command set  
• Total 80 (segment + common) drive sets  
• Low power — 30 µW at 2 kHz external clock  
• Wide range of supply voltages  
VDD – VSS: –2.4 to –7.0 V  
VDD – V5: –3.5 to –13.0 V  
• Low-power CMOS  
• The SED1520 which is able to drive two lines of  
twelve characters each.  
• The SED1521 which is able to drive 80 segments for  
extention.  
• The SED1522 which is able to drive one line of  
thirteen characters each.  
Line-up  
Number Number  
of SEG of CMOS  
Drivers Drivers  
Clock Frequency  
Product  
Applicable Driver  
SED1520 0 , SED1521  
Duty  
Name  
On-Chip External  
SED1520  
0
0
0
18 kHz  
18 kHz  
18 kHz  
18 kHz  
18 kHz  
2 kHz  
2 kHz  
2 kHz  
0
0
0
61  
80  
69  
61  
80  
69  
16  
0
8
16  
0
8
1/16, 1/32  
1/8 to 1/32  
1/8, 1/16  
1/16, 1/32  
1/8 to 1/32  
1/8, 1/16  
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
SED1521  
SED1522  
SED1520  
SED1521  
SED1522  
SED1520 0 , SED1522  
*
*
*
*
*
*
*
*
SED1522 0 , SED1521  
*
A
A
A
SED1520 A , SED1521  
A
A
A
*
*
SED1520 A , SED1522  
*
*
SED1522 A , SED1521  
*
*
• Package code (For example SED1520)  
SED1520T  
SED1520F A (QFP5-100pin)  
SED1520F**: PKG  
*
SED1520F C (QFP15-100pin)  
*
SED1520D A (Al-pad)  
SED1520D**: Chip  
*
SED1520D B (Au-bump)  
*
EPSON  
2–1  
SED1520 Series  
BLOCK DIAGRAM  
An example of SED1520 AA:  
*
LCD drive circuit  
Common counter  
Display data latch circuit  
Display data RAM  
(2560-bit)  
Column address decoder  
CL  
FR  
Display  
timing  
generator  
circuit  
Column address counter  
Column address register  
Command  
decoder  
Status  
MPU interface  
2–2  
EPSON  
SED1520 Series  
PACKAGE OUTLINE  
QFP5  
CS2  
CS3  
CS4  
CS5  
CS6  
CS7  
SEG22  
SEG23  
SEG24  
SEG25  
SEG26  
SEG27  
SEG28  
SEG29  
SEG30  
SEG31  
SEG32  
SEG33  
SEG34  
SEG35  
SEG36  
SEG37  
SEG38  
SEG39  
SEG40  
SEG41  
85  
90  
95  
45  
V
DD  
RES  
F2  
V5  
40  
35  
V1  
V2  
Index  
M/S  
V4  
V1  
COM0  
COM1  
COM2  
COM3  
COM4  
100  
QFP15  
50  
VSS  
D30  
D31  
D32  
D33  
D34  
D35  
D36  
D37  
VDD  
RES  
F R  
V5  
SEG20  
SEG21  
SEG22  
SEG23  
SEG24  
SEG25  
SEG26  
SEG27  
SEG28  
SEG29  
SEG30  
SEG31  
SEG32  
SEG33  
SEG34  
SEG35  
SEG36  
SEG37  
SEG38  
SEG39  
SEG40  
SEG41  
SEG42  
SEG43  
SEG44  
80  
45  
40  
35  
30  
85  
90  
95  
V3  
V2  
M/S  
V4  
V1  
COM  
0
1
2
3
4
5
6
COM  
COM  
COM  
COM  
COM  
COM  
Index  
Note: This is an example of SED1520F pin assignment. The modified pin names are given below.  
Product  
Name  
Pin/Pad Number  
96 to 100, 1 to 11  
COM0 to COM15*  
SEG76 to SEG61  
74  
OSC1  
CS  
OSC1  
CS  
75  
OSC2  
CL  
OSC2  
CL  
93  
M/S  
SEG79  
M/S  
M/S  
SEG79  
M/S  
94  
V4  
SEG78  
V4  
V4  
SEG78  
V4  
95  
V1  
SEG77  
V1  
V1  
SEG77  
V1  
SED1520F0A  
SED1521F0A  
SED1522F0A  
SED1520FAA  
SED1521FAA  
SED1522FAA  
COM0 to 7, SEG68 to 61  
COM0 to COM15*  
SEG76 to SEG61  
COM0 to 7, SEG68 to 61  
CS  
CS  
CL  
CL  
SED1520: Common outputs COM0 to COM15 of the master LSI correspond to COM31 to COM16 of the  
slave LSI.  
SED1522: Common outputs COM0 to COM15 of the master LSI correspond to COM15 to COM8 of the  
slave LSI.  
EPSON  
2–3  
SED1520 Series  
PAD  
Pad Arrangement  
Chip specifications of AL pad package  
Chip specifications of gold bump package  
Chip size: 4.80×7.04×0.525 mm  
Bump pitch: 199 µm (Min.)  
Bump height: 22.5 µm (Typ.)  
Bump size: 132×111 µm (±20 µm) for mushroom  
model  
Chip size: 4.80×7.04×0.400 mm  
Pad pitch: 100×100 µm  
116×92 µm (±4 µm) for vertical model  
100  
95  
90  
85  
80  
1
5
75  
70  
10  
Y
X
15  
20  
25  
30  
(0, 0)  
65  
60  
55  
35  
40  
4.80 mm  
45  
50  
Note: An example of SED1520DAA die numbers is given. These numbers are the same as the bump  
package.  
2–4  
EPSON  
SED1520 Series  
PAD ARRANGEMENT  
An example of SED1520DA pin names is given. The  
*
asterisk ( ) can be A for AL pad package or B for gold  
bump package.  
*
SED1520DAB Pad Center Coordinates  
Pad  
No.  
Pin  
Name  
Pad  
No.  
Pin  
Name  
Pad  
No.  
Pin  
Name  
X
Y
X
Y
X
Y
1
2
3
4
5
6
7
8
COM5 159 6507  
COM6 159 6308  
COM7 159 6108  
COM8 159 5909  
COM9 159 5709  
COM10 159 5510  
COM11 159 5310  
COM12 159 5111  
COM13 159 4911  
COM14 159 4712  
COM15 159 4512  
SEG60 159 4169  
SEG59 159 3969  
SEG58 159 3770  
SEG57 159 3570  
SEG56 159 3371  
SEG55 159 3075  
SEG54 159 2876  
SEG53 159 2676  
SEG52 159 2477  
SEG51 159 2277  
SEG50 159 2078  
SEG49 159 1878  
SEG48 159 1679  
SEG47 159 1479  
SEG46 159 1280  
SEG45 159 1080  
SEG44 159 881  
SEG43 159 681  
SEG42 159 482  
SEG41 504 159  
SEG40 704 159  
SEG39 903 159  
SEG38 1103 159  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
SEG37 1302 159  
SEG36 1502 159  
SEG35 1701 159  
SEG34 1901 159  
SEG33 2100 159  
SEG32 2300 159  
SEG31 2499 159  
SEG30 2699 159  
SEG29 2898 159  
SEG28 3098 159  
SEG27 3297 159  
SEG26 3497 159  
SEG25 3696 159  
SEG24 3896 159  
SEG23 4095 159  
SEG22 4295 159  
SEG21 4641 482  
SEG20 4641 681  
SEG19 4641 881  
SEG18 4641 1080  
SEG17 4641 1280  
SEG16 4641 1479  
SEG15 4641 1679  
SEG14 4641 1878  
SEG13 4641 2078  
SEG12 4641 2277  
SEG11 4641 2477  
SEG10 4641 2676  
SEG9 4641 2876  
SEG8 4641 3075  
SEG7 4641 3275  
SEG6 4641 3474  
SEG5 4641 3674  
SEG4 4641 3948  
69  
70  
71  
72  
73  
74  
75  
76  
77  
78  
79  
80  
81  
82  
83  
84  
85  
86  
87  
88  
89  
90  
91  
92  
93  
94  
95  
96  
97  
98  
99  
100  
SEG3 4641 4148  
SEG2 4641 4347  
SEG1 4641 4547  
SEG0 4641 4789  
A0  
CS  
CL  
4641 5048  
4641 5247  
4641 5447  
E (RD) 4641 5646  
R/W (WR) 4641 5846  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
VSS  
DB0  
DB1  
DB2  
DB3  
DB4  
DB5  
DB6  
DB7  
VDD  
RES  
FR  
V5  
V3  
V2  
M/S  
V4  
4641 6107  
4641 6307  
4641 6506  
4295 6884  
4095 6884  
3896 6884  
3696 6884  
3497 6884  
3297 6884  
3098 6884  
2898 6884  
2699 6884  
2499 6884  
2300 6884  
2100 6884  
1901 6884  
1701 6884  
1502 6884  
V1  
COM0 1302 6884  
COM1 1103 6884  
COM2  
COM3  
COM4  
903 6884  
704 6884  
504 6884  
The other SED1520 series packages have the different pin names as shown.  
Package/Pad No.  
SED1520D0*  
SED1522D0*  
SED1522DA*  
SED1521D0*  
SED1521DA*  
74  
75  
96 to 100, 1 to 11  
COM0 to COM15 *  
COM0 to 7, SEG68 to 61  
COM0 to 7, SEG68 to 61  
SEG76 to SEG61  
93  
M/S  
M/S  
M/S  
SEG79  
SEG79  
94  
V4  
V4  
V4  
SEG78  
SEG78  
95  
V1  
V1  
V1  
SEG77  
SEG77  
OSC1  
OSC1  
OSC1  
CS  
OSC2  
OSC2  
OSC2  
CL  
CS  
CL  
SEG76 to SEG61  
EPSON  
2–5  
SED1520 Series  
PIN DESCRIPTION  
(1) Power Pins  
Name  
Description  
VDD  
VSS  
Connected to the +5Vdc power. Common to the VCC MPU power pin.  
0 Vdc pin connected to the system ground.  
V1, V2, V3, V4, V5  
Multi-level power supplies for LCD driving. The voltage determined for each liquid  
crystal cell is divided by resistance or it is converted in impedance by the op amp,  
and supplied. These voltages must satisfy the following:  
VDD V1 V2 V3 V4 V5  
(2) System Bus Connection Pins  
D7 to D0  
Three-state I/O.  
The 8-bit bidirectional data buses to be connected to the 8- or 16-bit standard MPU  
data buses.  
A0  
Input.  
Usually connected to the low-order bit of the MPU address bus and used to identify  
the data or a command.  
A0=0: D0 to D7 are display control data.  
A0=1: D0 to D7 are display data.  
RES  
Input.  
When the RES signal goes  
the 68-series MPU is initialized, and when it  
goes , the 80-series MPU is initialized. The system is reset during edge  
sense of the RES signal. The interface type to the 68-series or 80-series MPU is  
selected by the level input as follows:  
High level: 68-series MPU interface  
Low level: 80-series MPU interface  
CS  
Input. Active low. Effective for an external clock operation model only.  
An address bus signal is usually decoded by use of chip select signal, and it is  
entered. If the system has a built-in oscillator, this is used as an input pin to the  
oscillator amp and an Rf oscillator resistor is connected to it. In such case, the RD,  
WR and E signals must be ORed with the CS signals and entered.  
E (RD)  
• If the 68-series MPU is connected:  
Input. Active high.  
Used as an enable clock input of the 68-series MPU.  
• If the 80-series MPU is connected:  
Input. Active low.  
The RD signal of the 80-series MPU is entered in this pin. When this signal is  
kept low, the SED1520 data bus is in the output status.  
R/W (WR)  
• If the 68-series MPU is connected:  
Input.  
Used as an input pin of read control signals (if R/W is high) or write control  
signals (if low).  
• If the 80-series MPU is connected:  
Input. Active low.  
The WR signal of the 80-series MPU is entered in this pin. A signal on the data  
bus is fetched at the rising edge of WR signal.  
2–6  
EPSON  
SED1520 Series  
(3) LCD Drive Circuit Signals  
Name  
Description  
Input. Effective for an external clock operation model only.  
CL  
This is a display data latch signal to count up the line counter and common counter  
at each signal falling and rising edges. If the system has a built-in oscillator, this is  
used as an output pin of the oscillator amp and an Rf oscillator resistor is con-  
nected to it.  
FR  
Input/output.  
This is an I/P pin of LCD AC signals, and connected to the M terminal of common  
driver.  
I/O selection  
• Common oscillator built-in model: Output if M/S is 1;  
Input if M/S is 0.  
• Dedicate segment model:  
Input  
SEGn  
Output.  
The output pin for LCD column (segment) driving. A single level of VDD, V2, V3 and  
V5 is selected by the combination of display RAM contents and RF signal.  
1
0
FR signal  
Data  
1
0
1
0
VDD  
V2  
V5  
V3  
Output level  
COMn  
Output.  
The output pin for LCD common (low) driving. A single level of VDD, V1, V4 and V5  
is selected by the combination of common counter output and RF signal. The  
slave LSI has the reverse common output scan sequence than the master LSI.  
1
0
FR signal  
1
0
1
0
Counter output  
Output level  
V5  
V1  
VDD  
V4  
M/S  
Input.  
The master or slave LSI operation select pin for the SED1520 or SED1522.  
Connected to VDD (to select the master LSI operation mode) or VSS (to select the  
slave LSI operation mode).  
When this M/S pin is set, the functions of FR, COM0 to COM15, OSC1 (CS), and  
OSC2 (CL) pins are changed.  
M/S  
VDD  
VSS  
VDD  
VSS  
FR  
Output  
Input  
Output  
Input  
COM output  
OSC1  
Input  
NC  
Input  
NC  
OSC2  
Output  
Input  
Output  
Input  
SED1520F0A  
SED1522F0A  
COM0 to COM15  
COM31 to COM16  
COM0 to COM7  
COM15 to COM8  
* The slave driver has the reverse common output scan sequence than the master  
driver.  
EPSON  
2–7  
SED1520 Series  
BLOCK DESCRIPTION  
System Bus  
MPU interface  
1. Selecting an interface type  
level after reset (see Table 1).  
The SED1520 series transfers data via 8-bit bidirec-  
tional data buses (D0 to D7). As its Reset pin has the  
MPU interface select function, the 80-series MPU or  
the 68-series MPU can directly be connected to the  
MPU bus by the selection of high or low RES signal  
When the CS signal is high, the SED1520 series is  
disconnected from the MPU bus and set to stand by.  
However, the reset signal is entered regardless of the  
internal setup status.  
Table 1  
A0  
RES signal input level  
Active low  
MPU type  
68-series  
80-series  
E
RD  
R/W  
WR  
CS  
D0 to D7  
Active high  
Data transfer  
The SED1520 and SED1521 drivers use the A0, E (or  
RD) and R/W (or WR) signals to transfer data between  
the system MPU and internal registers. The combina-  
tions used are given in the table blow.  
executes a read cycle to access display RAM the current  
contents of the latch are placed on the system data bus  
while the desired contents of the display RAM are moved  
into the latch.  
In order to match the timing requirements of the MPU  
with those of the display data RAM and control registers  
all data is latched into and out of the driver. This  
introduces a one cycle delay between a read request for  
data and the data arriving. For example when the MPU  
This means that a dummy read cycle has to be executed  
at the start of every series of reads. See Figure 1.  
No dummy cycle is required at the start of a series of  
writes as data is transferred automatically from the input  
latch to its destination.  
Common  
68 MPU  
R/W  
80 MPU  
Function  
A0  
1
1
0
0
RD  
0
1
0
1
WR  
1
0
1
0
1
0
1
0
Read display data  
Write display data  
Read status  
Write to internal register (command)  
2–8  
EPSON  
SED1520 Series  
WRITE  
MPU  
WR  
DATA  
Bus  
N
N + 1  
N + 2  
N + 3  
Internal  
timing  
N
N + 1  
N + 2  
N + 3  
hold  
WR  
READ  
MPU  
WR  
RD  
DATA  
N
N
Dummy read  
n
n + 1  
Address set  
at N  
Data read  
at N  
Data read  
at N + 1  
WR  
RD  
Internal  
timing  
Column  
address  
N
N + 1  
N + 2  
Bus  
hold  
N
n
n + 1  
n + 2  
Figure 1 Bus Buffer Delay  
Busy flag  
Column Address Counter  
When the Busy flag is logical 1, the SED1520 series is  
executing its internal operations. Any command other  
than Status Read is rejected during this time. The Busy  
flag is output at pin D7 by the Status Read command. If  
an appropriate cycle time (tcyc) is given, this flag needs  
not be checked at the beginning of each command and,  
therefore, the MPU processing capacity can greatly be  
enhanced.  
The column address counter is a 7-bit presettable counter  
that supplies the column address for MPU access to the  
display data RAM. See Figure 2. The counter is  
incremented by one every time the driver receives a Read  
or Write Display Data command. Addresses above 50H  
are invalid, and the counter will not increment past this  
value. The contents of the column address counter are set  
with the Set Column Address command.  
Display Start Line and Line Count  
Registers  
The contents of this register form a pointer to a line of  
data in display data RAM corresponding to the first line  
of the display (COM0), and are set by the Display Start  
Line command. See section 3.  
The contents of the display start line register are copied  
into the line count register at the start of every frame, that  
is on each edge of FR. The line count register is  
incremented by the CL clock once for every display line,  
thus generating a pointer to the current line of data, in  
display data RAM, being transferred to the segment  
driver circuits.  
Page Register  
The page resiter is a 2-bit register that supplies the page  
address for MPU access to the display data RAM. See  
Figure 2. The contents of the page register are set by the  
Set Page Register command.  
Display Data RAM  
The display data RAM stores the LCD display data, on a  
1-bit per pixel basis. The relation-ship between display  
data, display address and the display is shown in Figure  
2.  
EPSON  
2–9  
SED1520 Series  
Common Timing Generator Circuit  
Generates common timing signals and FR frame signals  
from the CL basic clock. The 1/16 or 1/32 duty (for  
SED1520) or 1/8 or 1/16 duty (for SED1522) can be  
selected by the Duty Select command. If the 1/32 duty is  
selected for the SED1520 and 1/16 duty is selected for the  
SED1522, the 1/32 and 1/16 duties are provided by two  
chips consisting of the master and slave chips in the  
common multi-chip mode.  
SED1520  
FR signal  
(Master output)  
0
1
2
14 15  
0
1
15  
Master Common  
Slave Common  
16 17  
30 31  
16 17  
31  
SED1522  
FR signal  
(Master output)  
Master Common  
Slave Common  
0
1
2
6
7
0
1
7
8
9
14 15  
8
9
15  
Display Data Latch Circuit  
Display Timing Generator  
This latch stores one line of display data for use by the  
LCD driver interface circuitry. The output of this latch  
is controlled by the Display ON/OFF and Static Drive  
ON/OFF commands.  
This circuit generates the internal display timing signal  
using the basic clock, CL, and the frame signals, FR.  
FR is used to generate the dual frame AC-drive wave-  
form (type B drive) and to lock the line counter and  
common timing generator to the system frame rate.  
CL is used to lock the line counter to the system line scan  
rate. If a system uses both SED1520s or SED1522 and  
SED1521s they must have the same CL frequency rating.  
LCD Driver Circuit  
The LCD driver circuitry generates the 80 4-level signals  
used to drive the LCD panel, using output from the  
display data latch and the common timing generator  
circuitry.  
2–10  
EPSON  
SED1520 Series  
Oscillator Circuit (SED1520 0A Only)  
*
A low power-consumption CR oscillator for adjusting  
the oscillation frequency using Rf oscillation resistor  
only. This circuit generates a display timing signal.  
Some of SED1520 and SED1522 series models have a  
built-in oscillator and others use an external clock. This  
difference must be checked before use.  
Connect the Rf oscillation resistor as follows. To sup-  
press the built-in oscillator circuit and drive the MPU  
using an external clock, enter the clock having the same  
phase as the OSC2 of mater chip into OSC2 of the slave  
chip.  
• MPU having a built-in oscillator  
VDD  
Master chip  
Slave chip  
M/S  
M/S  
(CS)  
(CL)  
(CS)  
(CL)  
OSC1  
OSC2  
OSC1  
OSC2  
VSS  
Rf  
Open  
*2  
*1  
*1 If the parasitic capacitance of this section increases, the oscillation frequency may shift to the lower  
frequency. Therefore, the Rf oscillation frequency must be reduced below the specified level.  
*2 A CMOS buffer is required if the oscillation circuit is connected to two or more slave MPU chips.  
• MPU driven with an external clock  
Y driver  
CL2  
SED1521FAA  
CL  
Reset Circuit  
Detects a rising or falling edge of an RES input and  
initializes the MPU during power-on.  
• Initialization status  
1. Display is off.  
2. Display start line register is set to line 1.  
3. Static drive is turned off.  
The input signal level at RES pin is sensed, and an  
MPU interface mode is selected as shown on Table 1.  
For the 80-series MPU, the RES input is passed  
through the inverter and the active high reset signal  
must be entered. For the 68-series MPU, the active  
low reset signal must be entered.  
4. Column address counter is set to address 0.  
5. Page address register is set to page 3.  
6. 1/32 duty (SED1520) or 1/16 duty (SED1522) is  
selected.  
7. Forward ADC is selected (ADC command D0 is  
1 and ADC status flag is 1).  
As shown for the MPU interface (reference example),  
the RES pin must be connected to the Reset pin and  
reset at the same time as the MPU initialization.  
If the MPU is not initialized by the use of RES pin  
during power-on, an unrecoverable MPU failure may  
occur.  
8. Read-modify-write is turned off.  
When the Reset command is issued, initialization  
EPSON  
2–11  
SED1520 Series  
Column address  
ADC  
SEG pin  
D
0
= "0"  
00  
01  
D
0
= "1"  
4F  
4E  
SEG 0  
H
H
1
2
3
4D  
4C  
4B  
4A  
49  
02  
03  
04  
05  
06  
07  
4
5
6
7
48  
4D  
4E  
4F  
02  
01  
00  
77  
78  
79  
Display area  
Figure 2 Display Data RAM Addressing  
2–12  
EPSON  
SED1520 Series  
1/5 bias, 1/16 duty  
1/6 bias, 1/32 duty  
0
0
1
1
2
2
3
3
15  
31  
0
0
1
1
2
2
3
3
15  
31  
VDD  
FR  
VSS  
VDD  
V1  
V2  
V3  
COM0  
V4  
V5  
COM0  
COM1  
COM2  
COM3  
COM4  
COM5  
COM6  
COM7  
VDD  
V1  
V2  
V3  
V4  
V5  
COM1  
COM2  
VDD  
V1  
V2  
V3  
V4  
V5  
COM8  
COM9  
VDD  
V1  
V2  
V3  
V4  
V5  
COM10  
COM11  
COM12  
COM13  
COM14  
COM15  
SEG0  
SEG1  
VDD  
V1  
V2  
V3  
V4  
V5  
V5  
V4  
V3  
V2  
V1  
VDD  
COM0—SEG0  
-V1  
-V2  
-V3  
-V4  
-V5  
V5  
V4  
V3  
V2  
V1  
COM0—SEG1  
VDD  
-V1  
-V2  
-V3  
-V4  
-V5  
Figure 4 LCD drive waveforms example  
EPSON  
2–13  
SED1520 Series  
COMMANDS  
Summary  
Code  
D5  
Command  
Function  
Turns display on or off.  
A0 RD WR  
D7  
D6  
D4  
D3 D2  
D1  
D0  
Display On/OFF  
Display start line  
Set page address  
0
0
0
0
1
1
1
1
0
0
0
0
1
0
1
0
1
0
1
1
1
0/1  
1: ON, 0: OFF  
Specifies RAM line corresponding to top line  
of display.  
1
1
0
1
0
Display start address (0 to 31)  
Page (0 to 3)  
Column address (0 to 79)  
Sets display RAM page in page address  
register.  
1
1
0
Set column  
Sets display RAM column address in  
column address register.  
Reads the following status:  
(segment) address  
BUSY  
1: Busy  
0: Ready  
ADC  
1: CW output  
0: CCW output  
1: Display off  
0: Display on  
1: Being reset  
0: Normal  
Read status  
0
0
1
Busy ADC ON/OFF Reset  
0
0
0
0
ON/OFF  
RESET  
Write display data  
Read display data  
1
1
0
0
1
0
1
1
0
1
0
0
Write data  
Writes data from data bus into display RAM.  
Reads data from display RAM onto data  
bus.  
Read data  
Select ADC  
Statis drive  
ON/OFF  
1
1
0
0
1
1
0
0
0
0
0
1
0
0
0/1  
0/1  
0: CW output, 1: CCW output  
Selects static driving operation.  
1: Static drive, 0: Normal driving  
Selets LCD duty cycle  
Select duty  
0
1
0
1
0
1
0
1
0
0
0/1  
1: 1/32, 0: 1/16  
Read-Modify-Write  
0
0
0
1
1
1
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
1
0
0
1
0
0
1
1
0
0
0
Read-modify-write ON  
End  
Read-modify-write OFF  
Software reset  
Reset  
2–14  
EPSON  
SED1520 Series  
Command Description  
Table 3 is the command table. The SED1520 series identifies a data bus using a combination of A0 and R/W (RD or WR)  
signals. As the MPU translates a command in the internal timing only (independent from the external clock), its speed  
is very high. The busy check is usually not required.  
Display ON/OFF  
R/W  
WR  
A0  
0
RD  
1
D7  
1
D6  
0
D5  
1
D4  
0
D3  
1
D2  
1
D1  
1
D0  
D
0
AEH, AFH  
This command turns the display on and off.  
• D=1: Display ON  
• D=0: Display OFF  
Display Start Line  
This command specifies the line address shown in Figure 3 and indicates the display line that corresponds to COM0. The  
display area begins at the specified line address and continues in the line address increment direction. This area having  
the number of lines of the specified display duty is displayed. If the line address is changed dynamically by this command,  
the vertical smooth scrolling and paging can be used.  
R/W  
WR  
A0  
0
RD  
1
D7  
1
D6  
1
D5  
0
D4  
A4  
D3  
A3  
D2  
A2  
D1  
A1  
D0  
A0  
0
C0H to DFH  
This command loads the display start line register.  
A4 A3 A2 A1 A0 Line Address  
0
0
0
0
0
0
:
0
0
0
1
0
1
:
:
1
:
31  
1
1
1
1
See Figure 2.  
Set Page Address  
This command specifies the page address that corresponds to the low address of the display data RAM when it is accessed  
by the MPU. Any bit of the display data RAM can be accessed when its page address and column address are specified.  
The display status is not changed even when the page address is changed.  
R/W  
WR  
A0  
0
RD  
1
D7  
1
D6  
0
D5  
1
D4  
1
D3  
1
D2  
0
D1  
A1  
D0  
A0  
0
B8H to BBH  
This command loads the page address register.  
A1 A0 Page  
0
0
1
1
0
1
0
1
0
1
2
3
See Figure 2.  
EPSON  
2–15  
SED1520 Series  
Set Column Address  
This command specifies a column address of the display data RAM. When the display data RAM is accessed by the MPU  
continuously, the column address is incremented by 1 each time it is accessed from the set address. Therefore, the MPU  
can access to data continuously. The column address stops to be incremented at address 80, and the page address is not  
changed continuously.  
R/W  
A0  
0
RD  
1
WR  
D7  
0
D6  
A6  
D5  
A5  
D4  
A4  
D3  
A3  
D2  
A2  
D1  
A1  
D0  
A0  
0
00H to 4FH  
This command loads the column address register.  
A6 A5 A4 A3 A2 A1 A0 Column Address  
0
0
0
0
0
0
0
0
:
0
0
0
0
0
1
0
1
:
:
:
1
0
0
1
1
1
1
79  
Read Status  
R/W  
WR  
A0  
0
RD  
0
D7  
D6  
D5  
D4  
D3  
0
D2  
D1  
0
D0  
0
1
BUSY ADC ON/OFF RESET  
0
Reading the command I/O register (A0=0) yields system status information.  
• The busy bit indicates whether the driver will accept a command or not.  
Busy=1: The driver is currently executing a command or is resetting. No new command will be accepted.  
Busy=0: The driver will accept a new command.  
• The ADC bit indicates the way column addresses are assigned to segment drivers.  
ADC=1: Normal. Column address n segment driver n.  
ADC=0: Inverted. Column address 79-u segment driver u.  
• The ON/OFF bit indicates the current status of the display.  
It is the inverse of the polarity of the display ON/OFF command.  
ON/OFF=1: Display OFF  
ON/OFF=0: Display ON  
• The RESET bit indicates whether the driver is executing a hardware or software reset or if it is in normal operating mode.  
RESET=1: Currently executing reset command.  
RESET=0: Normal operation  
Write Display Data  
R/W  
WR  
A0  
1
RD  
1
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
0
Write data  
Writes 8-bits of data into the display data RAM, at a location specified by the contents of the column address and page  
address registers and then increments the column address register by one.  
2–16  
EPSON  
SED1520 Series  
Read Display Data  
R/W  
WR  
A0  
1
RD  
0
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
1
Read data  
Reads 8-bits of data from the data I/O latch, updates the contents of the I/O latch with display data from the display data  
RAM location specified by the contents of the column address and page address registers and then increments the column  
address register.  
After loading a new address into the column address register one dummy read is required before valid data is obtained.  
Select ADC  
R/W  
WR  
A0  
0
RD  
1
D7  
1
D6  
0
D5  
1
D4  
0
D3  
0
D2  
0
D1  
0
D0  
D
0
A0H, A1H  
This command selects the relationship between display data RAM column addresses and segment drivers.  
D=1: SEG0 column address 4FH, … (inverted)  
D=0: SEG0 column address 00H, … (normal)  
This command is provided to reduce restrictions on the placement of driver ICs and routing of traces during printed circuit  
board design. See Figure 2 for a table of segments and column addresses for the two values of D.  
Static Drive ON/OFF  
R/W  
WR  
A0  
0
RD  
1
D7  
1
D6  
0
D5  
1
D4  
0
D3  
0
D2  
1
D1  
0
D0  
D
0
A4H, A5H  
Forces display on and all common outputs to be selected.  
D=1: Static drive on  
D=0: Static drive off  
Select Duty  
R/W  
WR  
A0  
0
RD  
1
D7  
1
D6  
0
D5  
1
D4  
0
D3  
1
D2  
0
D1  
0
D0  
D
0
A8H, A9H  
This command sets the duty cycle of the LCD drive and is only valid for the SED1520F and SED1522F. It is invalid for  
the SED1521F which performs passive operation. The duty cycle of the SED1521F is determined by the externally  
generated FR signal.  
SED1520  
D=1: 1/32 duty cycle  
D=0: 1/16 duty cycle  
SED1522  
1/16 duty cycle  
1/8 duty cycle  
When using the SED1520F0A, SED1522F0A (having a built-in oscillator) and the SED1521F0A continuously, set the duty  
as follows:  
SED1521F0A  
SED1520F0A  
SED1522F0A  
1/32  
1/16  
1/16  
1/8  
1/32  
1/16  
1/32  
1/16  
EPSON  
2–17  
SED1520 Series  
Read-Modify-Write  
R/W  
WR  
A0  
0
RD  
1
D7  
1
D6  
1
D5  
1
D4  
0
D3  
0
D2  
0
D1  
0
D0  
0
0
E0H  
This command defeats column address register auto-increment after data reads. The current conetents of the column  
address register are saved. This mode remains active until an End command is received.  
• Operation sequence during cursor display  
When the End command is entered, the column address is returned to the one used during input of Read-Modify-Write  
command. This function can reduce the load of MPU when data change is repeated at a specific display area (such as cursor  
blinking).  
* Any command other than Data Read or Write can be used in the Read-Modify-Write mode. However, the Column  
Address Set command cannot be used.  
Set Page Address  
Set Column Address  
Read-Modify-Write  
Dummy Read  
Read Data  
Write Data  
No  
Completed?  
Yes  
End  
End  
R/W  
WR  
A0  
0
RD  
1
D7  
1
D6  
1
D5  
1
D4  
0
D3  
1
D2  
1
D1  
1
D0  
0
0
EEH  
This command cancels read-modify-write mode and restores the contents of the column address register to their value prior  
to the receipt of the Read-Modify-Write command.  
Return  
Column address  
N
N+1  
N+2  
N+3  
N+m  
N
Read-Modify-Write mode is selected.  
End  
2–18  
EPSON  
SED1520 Series  
Reset  
R/W  
WR  
A0  
0
RD  
1
D7  
1
D6  
1
D5  
1
D4  
0
D3  
0
D2  
0
D1  
1
D0  
0
0
E2H  
This command clears  
• the display start line register.  
• and set page address register to 3 page.  
It does not affect the contents of the display data RAM.  
When the power supply is turned on, a Reset signal is entered in the RES pin. The Reset command cannot be used instead  
of this Reset signal.  
Power Save (Combination command)  
The Power Save mode is selected if the static drive is turned ON when the display is OFF. The current consumption can  
be reduced to almost the static current level. In the Power Save mode:  
(a) The LCD drive is stopped, and the segment and common driver outputs are set to the VDD level.  
(b) The external oscillation clock input is inhibited, and the OSC2 is set to the floating mode.  
(c) The display and operation modes are kept.  
The Power Save mode is released when the display is turned ON or when the static drive is turned OFF. If the LCD drive  
voltage is supplied from an external resistance divider circuit, the current passing through this resistor must be cut by the  
Power Save signal.  
VDD  
VDD  
V1  
V2  
SED1520  
SED1522  
V3  
V4  
V5  
Power Save signal  
VSSH  
If the LCD drive power is generated by resistance division, the resistance and capacitance are determined by the LCD panel  
size. After the panel size has been determined, reduce the resistance to the level where the display quality is not affected  
and reduce the power consumption using the divider resistor.  
EPSON  
2–19  
SED1520 Series  
SPECIFICATIONS  
Absolute Maximum Ratings  
Parameter  
Supply voltage (1)  
Symbol  
Rating  
–8.0 to +0.3  
–16.5 to +0.3  
V5 to +0.3  
VSS–0.3 to +0.3  
VSS–0.3 to +0.3  
250  
Unit  
VSS  
V
Supply voltage (2)  
V5  
V
Supply voltage (3)  
V1, V4, V2, V3  
V
V
Input voltage  
VIN  
VO  
Output voltage  
V
Power dissipation  
PD  
mW  
Operating temperature  
Storage temperature  
Soldering temperature time at lead  
Topr  
Tstg  
Tsol  
–40 to +85  
–65 to +150  
260, 10  
deg. C  
deg. C  
deg. C, sec  
Notes: 1. All voltages are specified relative to VDD = 0 V.  
2. The following relation must be always hold  
VDD V1 V2 V3 V4 V5  
3. Exceeding the absolute maximum ratings may cause permanent damage to the device. Functional  
operation under these conditions is not implied.  
4. Moisture resistance of flat packages can be reduced by the soldering process, so care should be taken to  
avoid thermally stressing the package during board assembly.  
Electrical Specifications  
DC Characteristics  
Ta = –20 to 75 deg. C, VDD = 0 V unless stated otherwise  
Rating  
Typ.  
Parameter  
Symbol  
VSS  
Condition  
Unit Applicable Pin  
Min.  
Max.  
Operating Recommended  
voltage (1)  
See note 1. Allowable  
–5.5  
–5.0  
–4.5  
V
VSS  
–7.0  
–2.4  
Recommended  
Operating Allowable  
voltage (2) Allowable  
Allowable  
–13.0  
–13.0  
0.6×V5  
V5  
VSS+2.0  
0.2×VSS  
0.2×VSS  
0.2×VSS  
VSS  
VSS  
VSS  
VSS  
VSS+2.4  
VSS+2.4  
0.2×VSS  
–3.5  
VDD  
0.4×V5  
VDD  
VDD  
V5  
V5  
V
See note 10.  
V1, V2  
V3, V4  
V1, V2  
V3, V4  
VIHT  
VIHC  
VIHT  
VIHC  
VILT  
VILC  
VILT  
VILC  
VOHT IOH = –3.0 mA  
VOHC1 IOH = –2.0 mA  
VOHC2 IOH = –120 µA  
VOHT VSS = –3 V  
VOHC1 VSS = –3 V  
VOHC2 VSS = –3 V  
V
V
See note 2 & 3.  
See note 2 & 3.  
See note 2 & 3.  
See note 2 & 3.  
High-level input voltage  
Low-level input voltage  
VSS = –3 V  
VSS = –3 V  
VDD  
VDD  
V
VSS+0.8  
0.8×VSS  
0.85×VSS  
0.8×VSS  
VSS = –3 V  
VSS = –3 V  
OSC2  
See note 4 & 5.  
V
V
High-level output voltage  
IOH = –2 mA 0.2×VSS  
IOH = –2 mA 0.2×VSS  
IOH = –50 µA 0.2×VSS  
See note 4 & 5.  
OSC2  
(continued)  
2–20  
EPSON  
SED1520 Series  
DC Characteristics (Cont’d)  
Ta = –20 to 75 deg. C, VDD = 0 V unless stated otherwise  
Rating  
Typ.  
Parameter  
Symbol  
Condition  
Unit Applicable Pin  
Min.  
Max.  
VSS+0.4  
VSS+0.4  
0.8×VSS  
0.8×VSS  
0.8×VSS  
0.8×VSS  
1.0  
VOLT IOL = 3.0 mA  
VOLC1 IOL = 2.0 mA  
VOLC2 IOL = 120 µA  
VOLT VSS = –3 V  
VOLC1 VSS = –3 V  
VOLC2 VSS = –3 V  
ILI  
OSC2  
V
See note 4 & 5.  
Low-level output voltage  
IOL = 2 mA  
IOL = 2 mA  
IOL = 50 µA  
See note 4 & 5.  
OSC2  
V
Input leakage current  
Output leakage current  
–1.0  
–3.0  
µA See note 6.  
µA See note 7.  
ILO  
3.0  
V5 = –5.0 V  
V5 = –3.5 V  
5.0  
7.5  
SEG0 to 79,  
kCOM0 to 15,  
See note 11  
LCD driver ON resistance  
Static current dissipation  
RON  
IDDQ  
Ta = 25 deg. C  
10.0  
50.0  
CS = CL = VDD  
0.05  
2.0  
9.5  
5.0  
1.0  
5.0  
15.0  
10.0  
µA VDD  
VDD  
µA See note 12,  
13 & 14.  
fCL = 2 kHz  
Rf = 1 MΩ  
fCL = 18 kHz  
During display  
V5 = –5.0 V  
IDD (1)  
During display fCL = 2 kHz  
V5 = –5 V  
1.5  
4.5  
VDD  
µA  
Dynamic current dissipation  
See note 12 & 13.  
VSS = –3 V  
During access tcyc = 200 kHz  
IDD (2) VSS = –3V,  
During access tcyc = 200 kHz  
Rf = 1 MΩ  
6.0  
300  
150  
5.0  
18  
12.0  
500  
300  
8.0  
µA See note 8.  
Input pin capacitance  
Oscillation frequency  
CIN  
Ta = 25 deg. C, f = 1 MHz  
Rf = 1.0 M±2%,  
VSS = –5.0 V  
Rf = 1.0 M±2%,  
VSS = –3.0 V  
pF All input pins  
15  
21  
fOSC  
kHz See note 9.  
11  
16  
21  
RES  
µS  
Reset time  
tR  
1.0  
See note 15.  
Notes: 1. Operation over the specified voltage range is guaranteed, except where the supply voltage changes  
suddenly during CPU access.  
2. A0, D0 to D7, E (or RD), R/W (or WR) and CS  
3. CL, FR, M/S and RES  
4. D0 to D7  
5. FR  
6. A0, E (or RD), R/W (or WR), CS, CL, M/S and RES  
7. When D0 to D7 and FR are high impedance.  
8. During continual write acess at a frequency of tcyc. Current consumption during access is effectively  
proportional to the access frequency.  
9. See figure below for details  
10. See figure below for details  
11. For a voltage differential of 0.1 V between input (V1, …, V4) and output (COM, SEG) pins. All voltages  
within specified operating voltage range.  
12. SED1520  
A
and SED1521  
A
and SED1522  
A
only. Does not include transient currents due to  
* *  
* *  
* *  
stray and panel capacitances.  
SED1520* * and SED1522* *  
13.  
0
0
only. Does not include transient currents due to stray and panel  
capacitances.  
14. SED1521  
0
only. Does not include transient currents due to stray and panel capacitances.  
* *  
15. tR (Reset time) represents the time from the RES signal edge to the completion of reset of the internal  
circuit. Therefore, the SED1520 series enters the normal operation status after this tR.  
EPSON  
2–21  
SED1520 Series  
Relationship between fOSC, fFR and Rf, and operating bounds on VSS and V5  
*9 • Relationship between oscillation frequency, frames and Rf  
(SED1520F0A), (SED1522F0A)  
OSC1  
Rf  
OSC2  
Same for 1/16 and 1/32 duties  
Ta=25°C VSS =-5V  
Ta=25°C VSS =-5V  
40  
30  
200  
100  
VSS =-5V  
SED1522  
20  
10  
VSS =-3V  
SED1520  
0.5  
0
1.0  
Rf  
1.5  
2.0  
2.5  
0
0.5  
1.0  
Rf  
1.5  
[M]  
2.0  
2.5  
[M]  
Figure 5 (a)  
Figure 5 (b)  
• Relationship between external clocks (fCL) and frames  
(SED1520FAA) , (SED1522FAA)  
duty1/32  
duty1/16  
duty1/8  
200  
100  
0
1
2
3
f CL  
[kHz]  
Figure 5 (c)  
*10 • Operating voltage range of VSS and V5 systems  
–15  
–10  
–5  
Operating voltage  
range  
0
–2  
–4  
–6  
(V)  
–8  
VSS  
Figure 6  
2–22  
EPSON  
SED1520 Series  
AC Characteristics  
• MPU Bus Read/Write I (80-family MPU)  
A0,CS  
t
AW8  
t
CC  
t
AH8  
WR,RD  
t
r
t
CYC8  
t
f
t
DH8  
t
DS8  
D0 to D7  
(WRITE)  
t
OH8  
t
ACC8  
D0 to D7  
(READ)  
Ta = –20 to 75 deg. C, VSS = –5.0 V ±10% unless stated otherwise  
Rating  
Parameter  
Symbol  
Condition  
Unit  
Signal  
A0, CS  
WR, RD  
Min.  
10  
Max.  
Address hold time  
Address setup time  
System cycle time  
Control pulsewidth  
Data setup time  
Data hold time  
RD access time  
Output disable time  
Rise and fall time  
tAH8  
tAW8  
tCYC8  
tCC  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
20  
1000  
200  
80  
tDS8  
tDH8  
tACC8  
tCH8  
tr, tf  
10  
10  
D0 to D7  
90  
60  
15  
CL = 100 pF  
(VSS = –2.7 to –4.5 V, Ta = –20 to +75°C)  
Rating  
Parameter  
Symbol  
Condition  
Unit  
Signal  
A0, CS  
WR, RD  
Min.  
20  
Max.  
Address hold time  
Address setup time  
System cycle time  
Control pulse width  
Data setup time  
Data hold time  
RD access time  
Output disable time  
Rise and fall time  
tAH8  
tAW8  
tCYC8  
tCC  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
40  
2000  
400  
160  
20  
tDS8  
tDH8  
tACC8  
tCH8  
tr, tf  
D0 to D7  
20  
180  
120  
15  
CL = 100 pF  
EPSON  
2–23  
SED1520 Series  
• MPU Bus Read/Write II (68-family MPU)  
t
CYC6  
E
t
EW  
t
r
t
f
t
AW6  
t
DS6  
R/W  
t
t
t
AH6  
DH6  
OH6  
A0,CS  
D0 to D7  
(WRITE)  
t
ACC6  
D0 to D7  
(READ)  
Ta = –20 to 75 deg. C, VSS = –5 V ±10 unless stated otherwise  
Rating  
Parameter  
Symbol  
Condition  
Unit  
Signal  
Min.  
1000  
20  
Max.  
System cycle time  
Address setup time  
Address hold time  
Data setup time  
Data hold time  
tCYC6  
tAW6  
tAH6  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
60  
90  
15  
A0, CS, R/W  
10  
80  
10  
10  
tDS6  
tDH6  
tOH6  
tACC6  
D0 to D7  
Output disable time  
Access time  
CL = 100 pF  
Enable  
pulsewidth  
Read  
Write  
100  
80  
tEW  
E
Rise and fall time  
tr, tf  
(VSS = –2.7 to – 4.5 V, Ta = –20 to +75°C)  
Rating  
Parameter  
Symbol  
Condition  
Unit  
Signal  
Min.  
2000  
40  
Max.  
System cycle time*1  
Address setup time  
Address hold time  
Data setup time  
Data hold time  
tCYC6  
tAW6  
tAH6  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
A0, CS, R/W  
20  
tDS6  
160  
20  
tDH6  
tOH6  
tACC6  
D0 to D7  
Output disable time  
Access time  
20  
120  
180  
CL = 100 pF  
Enable  
pulse width  
Read  
Write  
200  
160  
tEW  
tr, tf  
E
15  
Rise and fall time  
Notes: 1. tCYC6 is the cycle time of CS. E = H, not the cycle time of E.  
2–24  
EPSON  
SED1520 Series  
• Display Control Signal Timing  
t f  
t r  
CL  
t
WLCL  
t
WHCL  
t
DFR  
FR  
Input  
Ta = –20 to 75 deg. C, VSS = –5.0 V ±10% unless stated otherwise  
Rating  
Typ.  
30  
Parameter  
Symbol  
Condition  
Unit  
Signal  
Min.  
35  
35  
Max.  
150  
150  
2.0  
Low-level pulsewidth  
High-level pulsewidth  
Rise time  
Fall time  
FR delay time  
tWLCL  
tWHCL  
tr  
µs  
µs  
ns  
ns  
µs  
CL  
FR  
tf  
30  
0.2  
tDFR  
–2.0  
VSS = –2.7 to –4.5 V, Ta = –20 to +75°C  
Rating  
Typ.  
60  
Parameter  
Symbol  
Condition  
Unit  
Signal  
Min.  
70  
70  
Max.  
300  
300  
4.0  
Low-level pulse width  
High-level pulse width  
Rise time  
Fall time  
FR delay time  
tWLCL  
tWHCL  
tr  
µs  
µs  
ns  
ns  
µs  
CL  
FR  
tf  
60  
0.4  
tDFR  
–4.0  
Note: The listed input tDFR applies to the SED1520 and SED1521 and SED1522 in slave mode.  
Output  
Ta = –20 to 75 deg. C, VSS = –5.0 V ±10% unless stated otherwise  
Rating  
Typ.  
Parameter  
Symbol  
Condition  
Unit  
Signal  
Min.  
Max.  
FR delay time  
tDFR  
CL = 100 pF  
0.2  
0.4  
µs  
FR  
VSS = –2.7 to –4.5 V, Ta = –20 to +75°C  
Rating  
Typ.  
0.4  
Parameter  
Symbol  
Condition  
Unit  
Signal  
Min.  
Max.  
0.8  
FR delay time  
tDFR  
CL = 100 pF  
µs  
FR  
Notes: 1. The listed output tDFR applies to the SED1520 and SED1522 in master mode.  
EPSON  
2–25  
SED1520 Series  
APPLICATION NOTES  
MPU Interface Configuration  
80 Family MPU  
VCC  
A0  
VDD  
A0  
A1 to A7  
Decoder  
CS  
IOQR  
MPU  
SED1520FAA  
D0 to D7  
RD  
D0 to D7  
RD  
WR  
WR  
RES  
GND  
RES  
VSS  
V5  
RESET  
2–26  
EPSON  
SED1520 Series  
LCD Drive Interface Configuration  
SED1520F0A–SED1520F0A  
SED1522F0A–SED1522F0A  
To LCD SEG  
To LCD SEG  
To LCD COM  
SED1520F0A  
To LCD COM  
SED1520F0A  
Slave  
VDD  
Master  
M/S  
M/S  
FR  
VSS  
OSC1  
OSC2  
FR  
OSC1  
OSC2  
Rf  
SED1520FAA–SED1520FAA  
SED1522FAA–SED1522FAA  
To LCD SEG  
To LCD SEG  
To LCD COM  
To LCD COM  
SED1520FAA  
Master  
SED1520FAA  
Slave  
VDD  
M/S  
M/S  
FR  
VSS  
CL  
FR  
CL  
External clock  
SED1520F0A  
SED1522F0A  
)–SED1521F0A (See note 1)  
To LCD SEG  
To LCD SEG  
To LCD COM  
SED1520F0A  
SED1521F0A  
Slave  
Master  
OSC2  
VDD  
M/S  
OSC1  
FR  
OSC1  
OSC2  
FR  
Rf  
*2  
EPSON  
2–27  
SED1520 Series  
SED1520FAA–SED1521FAA  
To LCD SEG  
SED1520FAA  
To LCD SEG  
SED1521FAA  
To LCD COM  
VDD  
M/S  
CL  
FR  
CL  
FR  
External clock  
Notes: 1. The duty cycle of the slave must be the same as that for the master.  
2. If a system has two or more slave drivers a CMOS buffer will be required.  
2–28  
EPSON  
SED1520 Series  
LCD Panel Wiring Example (The full-dot LCD panel displays a character in 6×8 dots.)  
1/16 duty:  
• 10 characters × 2 lines  
1
LCD 16×61  
16  
1
61  
SEG  
SED1520F  
COM  
1/16 duty:  
• 23 characters × 2 lines  
1
LCD 16×141  
1
61  
62  
141  
16  
SEG  
SEG  
SED1520F  
SED1521F  
COM  
1/32 duty:  
• 33 characters × 4 lines  
1
LCD 32×202  
17  
32  
16  
1
61 62  
141 142  
202  
SEG  
SEG  
SEG  
SED1520F  
SED1521F  
*
SED1520F  
COM  
COM  
* The SED1521F can be omitted (the 32×122-dot display mode is selected).  
Note: A combination of AB or AA type chip (that uses internal clocks) and 0B or 0A type chip (that uses external  
clocks) is NOT allowed.  
EPSON  
2–29  
SED1520 Series  
Package Dimensions  
• Plastic QFP5–100 pin  
Dimensions: inches (mm)  
± 0.016  
1.008  
(25.6  
± 0.4  
)
± 0.004  
± 0.1  
)
0.787  
(20  
80  
51  
81  
50  
Index  
100  
31  
± 0.004  
0.026  
(0.65  
1
30  
± 0.1  
)
± 0.004  
0.012  
(0.30  
± 0.1  
)
0~12°  
0.110  
(2.8)  
• Plastic QFP15–100 pin  
± 0.016  
± 0.4  
)
0.630  
(16.0  
(14.0  
± 0.004  
± 0.1  
)
0.551  
75  
51  
76  
50  
Index  
100  
26  
1
25  
± 0.004  
± 0.004  
0.020  
(0.5  
0.007  
(0.18  
± 0.1  
± 0.1  
)
)
0~12°  
± 0.004  
± 0.2  
)
0.020  
(0.5  
0.039(1.0)  
2–30  
EPSON  
SED1520 Series  
( M o l d , m a r k i n g a r e a )  
EPSON  
2–31  

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