CY7B9910
CY7B9920
Low Skew Clock Buffer
The completely integrated PLL enables “zero delay” capability.
External divide capability, combined with the internal PLL, allows
distribution of a low frequency clock that is multiplied by virtually
any factor at the clock destination. This facility minimizes clock
distribution difficulty while allowing maximum system clock
speed and flexibility.
Features
■ All outputs skew <100 ps typical (250 max.)
■ 15 to 80 MHz output operation
■ Zero input to output delay
■ 50% duty cycle outputs
Block Diagram Description
■ Outputs drive 50Ω terminated lines
■ Low operating current
Phase Frequency Detector and Filter
The Phase Frequency Detector and Filter blocks accept inputs
from the reference frequency (REF) input and the feedback (FB)
input and generate correction information to control the
frequency of the Voltage Controlled Oscillator (VCO). These
blocks, along with the VCO, form a Phase Locked Loop (PLL)
that tracks the incoming REF signal.
■ 24-pin SOIC package
■ Jitter:<200 ps peak to peak, <25 ps RMS
Functional Description
The CY7B9910 and CY7B9920 Low Skew Clock Buffers offer
low skew system clock distribution. These multiple output clock
drivers optimize the timing of high performance computer
systems. Each of the eight individual drivers can drive terminated
transmission lines with impedances as low as 50Ω. They deliver
minimal and specified output skews and full swing logic levels
(CY7B9910 TTL or CY7B9920 CMOS).
VCO
The VCO accepts analog control inputs from the PLL filter block
and generates a frequency. The operational range of the VCO is
determined by the FS control pin.
Logic Block Diagram
TEST
VOLTAGE
PHASE
FB
FREQ
DET
FILTER
CONTROLLED
OSCILLATOR
REF
FS
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Cypress Semiconductor Corporation
Document Number: 38-07135 Rev. *B
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised August 07, 2007
CY7B9910
CY7B9920
Static Discharge Voltage............................................>2001V
(MIL-STD-883, Method 3015)
Maximum Ratings
Operating outside these boundaries may affect the performance
and life of the device. These user guidelines are not tested.
Latch Up Current .....................................................>200 mA
Operating Range
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied ............................................–55°C to +125°C
Supply Voltage to Ground Potential................–0.5V to +7.0V
DC Input Voltage ............................................–0.5V to +7.0V
Output Current into Outputs (LOW)............................. 64 mA
Ambient
Range
Commercial
Industrial
Temperature
0°C to +70°C
–40°C to +85°C
V
CC
5V ± 10%
5V ± 10%
Document Number: 38-07135 Rev. *B
Page 3 of 11
CY7B9910
CY7B9920
Electrical Characteristics Over the Operating Range
CY7B9910
CY7B9920
Min Max
Parameter
Description
Test Conditions
= Min, I = –16 mA
Min
Max
Unit
V
Output HIGH Voltage
V
V
V
V
2.4
V
OH
CC
CC
CC
CC
OH
= Min, I =–40 mA
V
–0.75
OH
CC
V
Output LOW Voltage
= Min, I = 46 mA
0.45
V
OL
OL
= Min, I = 46 mA
0.45
OL
V
V
V
V
V
I
Input HIGH Voltage
(REF and FB inputs only)
2.0
V
V
1.35
–
V
CC
V
V
IH
CC
CC
Input LOW Voltage
(REF and FB inputs only)
–0.5
0.8
–0.5
1.35
IL
Three Level Input HIGH
Min ≤ V ≤ Max
V
– 1V
V
V
– 1V
V
V
IHH
IMM
ILL
CC
CC
CC
CC
CC
Voltage (Test, FS)
Three Level Input MID
Min ≤ V ≤ Max
V
/2 –
V
/2 +
V
/2 –
V /2 +
CC
500 mV
V
CC
CC
CC
500 mV
CC
Voltage (Test, FS)
500 mV
500 mV
Three Level Input LOW
Min ≤ V ≤ Max
0.0
1.0
0.0
1.0
V
CC
Voltage (Test, FS)
Input HIGH Leakage Current
(REF and FB inputs only)
V
V
V
V
V
V
= Max, V = Max
10
10
μA
μA
μA
μA
μA
mA
mA
IH
CC
IN
I
I
I
I
I
I
Input LOW Leakage Current
(REF and FB inputs only)
= Max, V = 0.4V
–500
–50
–500
–50
IL
CC
IN
Input HIGH Current
(Test, FS)
= V
CC
200
50
200
50
IHH
IMM
ILL
IN
Input MID Current
(Test, FS)
= V /2
IN
CC
Input LOW Current
(Test, FS)
= GND
–200
–250
–200
N/A
IN
Output Short Circuit
= Max, V
OUT
OS
CC
Current
= GND (25°C only)
Operating Current Used by
Internal Circuitry
V
= V
= Max All Com’l
85
90
85
90
CCQ
CCN
CCQ
Input
Selects Open
Mil/Ind
I
Output Buffer Current per
Output Pair
V
= V = Max
CCQ
= 0 mA
14
19
mA
CCN
CCN
I
OUT
Input Selects Open, f
MAX
[5]
PD
Power Dissipation per
Output Pair
V
= V
= 0 mA
= Max
78
104
mW
CCN
CCQ
I
OUT
Input Selects Open, f
MAX
Notes
4. These inputs are normally wired to VCC, GND, or left unconnected (actual threshold voltages vary as a percentage of VCC). Internal termination resistors hold
unconnected inputs at VCC/2. If these inputs are switched, the function and timing of the outputs may glitch and the PLL may require an additional tLOCK time
before all data sheet limits are achieved.
5. Tested one output at a time, output shorted for less than one second, less than 10% duty cycle. Room temperature only. CY7B9920 outputs are not short circuit
protected.
6. Total output current per output pair is approximated by the following expression that includes device current plus load current:
CY7B9910:
ICCN = [(4 + 0.11F) + [((835 – 3F)/Z) + (.0022FC)]N] x 1.1
CY7B9920:
ICCN = [(3.5+.17F) + [((1160 – 2.8F)/Z) + (.0025FC)]N] x 1.1
Where
F = frequency in MHz
C = capacitive load in pF
Z = line impedance in ohms
N = number of loaded outputs; 0, 1, or 2
FC = F < C.
7. Total power dissipation per output pair is approximated by the following expression that includes device power dissipation plus power dissipation due to the load circuit:
CY7B9910:
PD = [(22 + 0.61F) + [((1550 – 2.7F)/Z) + (.0125FC)]N] x 1.1
CY7B9920:
Document Number: 38-07135 Rev. *B
Page 4 of 11
CY7B9910
CY7B9920
Capacitance
Tested initially and after any design or process changes that may affect these parameters.
Parameter
Description
Test Conditions
Max
Unit
C
Input Capacitance
T = 25°C, f = 1 MHz, V = 5.0V
10
pF
IN
A
CC
AC Test Loads and Waveforms
5V
3.0V
2.0V
=1.5V
0.8V
0.0V
2.0V
=1.5V
0.8V
R1=130
R2=91
R1
R2
V
th
V
th
C = 50 pF (C = 30pF for –5 and – 2 devices)
L
L
C
L
(Includes fixture and probe capacitance)
≤1ns
≤1ns
7B9910–3
7B9910–4
TTL AC Test Load (CY7B9910)
TTL Input Test Waveform (Cy7B9910)
V
CC
V
CC
R1=100
R2=100
80%
CC
20%
0.0V
80%
R1
R2
C = 50 pF (C =30 pF for –5 and – 2devices)
V
th
= V /2
V
th
= V /2
L
L
CC
(Includes fixture and probe capacitance)
20%
C
L
≤ 3ns
≤ 3ns
7B9910–5
7B9910–6
CMOS Input Test Waveform (CY7B9920)
CMOS AC Test Load (CY7B9920)
Switching Characteristics
Over the Operating Range
[8]
[8]
CY7B9910–2
Min Typ
CY7B9920–2
Min Typ
Parameter
Description
FS = LOW
Max
Max
Unit
[1, 2]
f
Operating Clock
15
30
50
80
15
30
50
80
MHz
NOM
Frequency in MHz
FS = MID
25
25
[12]
FS = HIGH
40
40
t
t
t
t
t
t
t
t
t
t
REF Pulse Width HIGH
REF Pulse Width LOW
5.0
5.0
5.0
5.0
ns
ns
ns
ns
ns
ns
ns
ns
ms
ps
ps
RPWH
RPWL
SKEW
DEV
[13, 14]
Zero Output Skew (All Outputs)
0.1
0.25
0.75
+0.25
+0.65
1.2
0.1
0.25
0.75
+0.25
+0.65
2.5
[14, 15]
Device-to-Device Skew
Propagation Delay, REF Rise to FB Rise
–0.25
–0.65
0.15
0.0
0.0
1.0
1.0
–0.25
–0.65
0.5
0.0
0.0
2.0
2.0
PD
[16]
Output Duty Cycle Variation
ODCV
ORISE
OFALL
LOCK
JR
[17, 18]
Output Rise Time
[17, 18]
Output Fall Time
0.15
1.2
0.5
2.5
[19]
PLL Lock Time
0.5
0.5
Cycle-to-Cycle Output Jitter Peak to Peak
RMS
200
25
200
25
Document Number: 38-07135 Rev. *B
Page 5 of 11
CY7B9910
CY7B9920
CY7B9910–5
Typ
CY7B9920–5
Typ
Parameter
Description
FS = LOW
Min
15
Max
Min
15
Max
Unit
f
Operating Clock
30
30
MHz
NOM
Frequency in MHz
FS = MID
25
50
80
25
50
80
FS = HIGH
40
40
t
t
t
t
t
t
t
t
t
t
REF Pulse Width HIGH
REF Pulse Width LOW
5.0
5.0
5.0
5.0
ns
ns
ns
ns
ns
ns
ns
ns
ms
ps
ps
RPWH
RPWL
SKEW
DEV
Zero Output Skew (All Outputs)
0.25
0.5
1.0
+0.5
+1.0
1.5
1.5
0.5
200
25
0.25
0.5
1.0
+0.5
+1.0
3.0
3.0
0.5
200
25
Device-to-Device Skew
Propagation Delay, REF Rise to FB Rise
–0.5
–1.0
0.15
0.15
0.0
0.0
1.0
1.0
–0.5
–1.0
0.5
0.0
0.0
2.0
2.0
PD
Output Duty Cycle Variation
ODCV
ORISE
OFALL
LOCK
JR
Output Rise Time
Output Fall Time
0.5
PLL Lock Time
[8]
Cycle-to-Cycle Output Jitter Peak to Peak
[8]
RMS
Notes
8. Guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect these parameters.
9. CMOS output buffer current and power dissipation specified at 50 MHz reference frequency.
10. Applies to REF and FB inputs only.
11. Test measurement levels for the CY7B9910 are TTL levels (1.5V to 1.5V). Test measurement levels for the CY7B9920 are CMOS levels (VCC/2 to VCC/2). Test
conditions assume signal transition times of 2ns or less and output loading as shown in the AC Test Loads and Waveforms unless otherwise specified.
12. Except as noted, all CY7B9920–2 and –5 timing parameters are specified to 80 MHz with a 30 pF load.
13. tSKEW is defined as the time between the earliest and the latest output transition among all outputs when all are loaded with 50 pF and terminated with 50Ω to
2.06V (CY7B9910) or VCC/2 (CY7B9920).
14. tSKEW is defined as the skew between outputs.
15. tDEV is the output-to-output skew between any two outputs on separate devices operating under the same conditions (VCC, ambient temperature, air flow, and
so on).
16. tODCV is the deviation of the output from a 50% duty cycle.
17. Specified with outputs loaded with 30 pF for the CY7B99X0–2 and –5 devices and 50 pF for the CY7B99X0–7 devices. Devices are terminated through 50Ω to
2.06V (CY7B9910) or VCC/2 (CY7B9920).
18. tORISE and tOFALL measured between 0.8V and 2.0V for the CY7B9910 or 0.8VCC and 0.2VCC for the CY7B9920.
19. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VCC is stable and within normal operating limits. This
parameter is measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits.
Document Number: 38-07135 Rev. *B
Page 6 of 11
CY7B9910
CY7B9920
Switching Characteristics
Over the Operating Range (continued)
CY7B9910–7
Typ
CY7B9920–7
Typ
Parameter
Description
FS = LOW
Min
Max
Min
Max
Unit
f
Operating Clock
15
30
15
30
MHz
NOM
Frequency in MHz
FS = MID
25
40
50
80
25
40
50
[12]
FS = HIGH
80
t
t
t
t
t
t
t
t
t
t
t
REF Pulse Width HIGH
REF Pulse Width LOW
5.0
5.0
5.0
5.0
ns
ns
ns
ns
ns
ns
ns
ns
ms
ps
ps
RPWH
RPWL
SKEW
DEV
Zero Output Skew (All Outputs)
0.3
0.75
1.5
0.3
0.75
1.5
Device-to-Device Skew
Propagation Delay, REF Rise to FB Rise
–0.7
–1.2
0.15
0.15
0.0
0.0
1.5
1.5
+0.7
+1.2
2.5
–0.7
–1.2
0.5
0.0
0.0
3.0
3.0
+0.7
+1.2
5.0
PD
Output Duty Cycle Variation
ODCV
ORISE
OFALL
LOCK
JR
Output Rise Time
Output Fall Time
2.5
0.5
5.0
PLL Lock Time
0.5
0.5
[8]
Cycle-to-Cycle Output Peak to Peak
Jitter
200
25
200
25
[8]
RMS
JR
Document Number: 38-07135 Rev. *B
Page 7 of 11
CY7B9910
CY7B9920
AC Timing Diagrams
Figure 1. AC Timing Diagrams
t
t
RPWL
REF
t
RPWH
REF
t
PD
t
ODCV
t
ODCV
FB
Q
t
JR
t
SKEW
t
SKEW
OTHERQ
Figure 2. Zero Skew and Zero Delay Clock Driver
REF
LOAD
Z
Z
0
FB
SYSTEM
CLOCK
REF
FS
LOAD
LOAD
Q0
Q1
0
Q2
Q3
Q4
Q5
Z
0
Q6
Q7
LOAD
TEST
Z
0
Document Number: 38-07135 Rev. *B
Page 8 of 11
CY7B9910
CY7B9920
Operational Mode Descriptions
buffer. In this mode the 7B9910/9920 is used as the basis for a
low skew clock distribution tree. The outputs are aligned and may
each drive a terminated transmission line to an independent
load. The FB input is tied to any output and the operating
frequency range is selected with the FS pin. The low skew speci-
fication, coupled with the ability to drive terminated transmission
lines (with impedances as low as 50 ohms), enables efficient
printed circuit board design.
construct a zero skew clock distribution tree between boards.
Cascaded clock buffers accumulates low frequency jitter
because of the non-ideal filtering characteristics of the PLL filter.
Do not connect more than two clock buffers in series.
Figure 3. Board-to-Board Clock Distribution
LOAD
LOAD
REF
Z
0
FB
SYSTEM
CLOCK
REF
FS
Z
0
Q0
Q1
Q2
Q3
LOAD
Q4
Q5
Z
0
Q6
Q7
FB
REF
FS
TEST
LOAD
Q0
Q1
Z
0
Q2
Q3
Q4
Q5
LOAD
Q6
Q7
TEST
Document Number: 38-07135 Rev. *B
Page 9 of 11
CY7B9910
CY7B9920
Ordering Information
Accuracy
Operating
Range
Ordering Code
Package Type
24-Pb Small Outline IC
(ps)
250
CY7B9910–2SC
CY7B9910–2SCT
Commercial
24-Pb Small Outline IC - Tape and Reel
24-Pb Small Outline IC
Commercial
Commercial
Commercial
Commercial
Industrial
[20]
CY7B9920–2SC
CY7B9910–5SC
CY7B9910–5SCT
CY7B9910–5SI
CY7B9910–5SIT
CY7B9920–5SC
CY7B9920–5SCT
CY7B9920–5SI
CY7B9910–7SC
500
24-Pb Small Outline IC
24-Pb Small Outline IC - Tape and Reel
24-Pb Small Outline IC
24-Pb Small Outline IC - Tape and Reel
24-Pb Small Outline IC
Industrial
Commercial
Commercial
Industrial
24-Pb Small Outline IC - Tape and Reel
24-Pb Small Outline IC
750
24-Pb Small Outline IC
Commercial
Industrial
[20]
CY7B9910–7SI
24-Pb Small Outline IC
[20]
CY7B9920–7SC
24-Pb Small Outline IC
Commercial
Industrial
[20]
CY7B9920–7SI
24-Pb Small Outline IC
Pb-Free
250
CY7B9910–2SXC
CY7B9910–2SXCT
CY7B9910–5SXC
CY7B9910–5SXCT
CY7B9910–5SXI
CY7B9910–5SXIT
CY7B9910–7SXC
CY7B9910–7SXCT
24-Pb Small Outline IC
Commercial
Commercial
Commercial
Commercial
Industrial
24-Pb Small Outline IC - Tape and Reel
24-Pb Small Outline IC
500
24-Pb Small Outline IC - Tape and Reel
24-Pb Small Outline IC
24-Pb Small Outline IC - Tape and Reel
24-Pb Small Outline IC
Industrial
750
Commercial
Commercial
24-Pb Small Outline IC - Tape and Reel
Package Diagram
Figure 4. 24-Pin (300 Mil) Molded SOIC S13
51-85025-*C
Note
20. Not recommended for new design.
Document Number: 38-07135 Rev. *B
Page 10 of 11
CY7B9910
CY7B9920
Document History
Document Title: CY7B9910/CY7B9920 Low Skew Clock Buffer
Document Number: 38-07135
Orig. of
Change
REV.
ECN NO. Issue Date
Description of Change
**
110244
10/28/01
SZV
Change from Specification number: 38-00437 to 38-07135
*A
1199925
See ECN DPF/AESA Added Pb-free parts in Ordering Information
Added Note 20: Not recommended for the new design
*B
1353343
See ECN AESA
Change status to final
© Cypress Semiconductor Corporation, 2001-2007.The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
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Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-07135 Rev. *B
Revised August 07, 2007
Page 11 of 11
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