High Efficiency Synchronous
Step-Down Switching Regulators
a
ADP1148, ADP1148-3.3, ADP1148-5
FUNCTIO NAL BLO CK D IAGRAM
ADJUSTABLE
FEATURES
Operation From 3.5 V to 18 V Input Voltage
Ultrahigh Efficiency > 95%
Low Shutdow n Current
VERSION
SIGNAL
PWR
GND
V
V
P-DRIVE N-DRIVE
GND SENSE(+)
SENSE(–)
7
IN
FB
Current Mode Operation for Excellent Line and Load
Transient Response
3
1
12
11
8
14
9
ADP1148
High Efficiency Maintained Over Wide Current Range
Logic Controlled Micropow er Shutdow n
Short Circuit Protection
NON-OVERLAP
DRIVE
V
B
2
R
Very Low Dropout Operation
SLEEP
Q
S
1
Synchronous FET Sw itching for High Efficiency
Adaptive Nonoverlap Gate Drives
Q
R
S
C
S
V
TH1
APPLICATIONS
13k⍀
10mV to
150mV
V
TH2
T
G
Notebook and Palm top Com puters
Portable Instrum ents
Battery Operated Digital Devices
Industrial Pow er Distribution
Avionics System s
100k⍀
1.25V
V
IN
OFF-TIME
CONTROL
REFERENCE
SENSE(–)
V
FB
10
5
4
6
I
SHUTDOWN
INT V
CC
C
TH
T
Telecom Pow er Supplies
GPS System s
Cellular Telephones
T he constant off-time architecture maintains constant ripple
current in the inductor, easing the design of wide input range
converters. Current-mode operation provides excellent line and
load transient response. T he operating current level is user
programmable via an external current sense resistor.
GENERAL D ESCRIP TIO N
T he ADP1148 is part of a family of synchronous step-down
switching regulator controllers featuring automatic sleep mode
to maintain high efficiencies at low output currents. T hese
devices drive external complementary power MOSFET s at
switching frequencies up to 250 kHz using a constant off-time
current-mode architecture.
T he ADP1148 incorporates automatic Power Saving Sleep
Mode operation when load currents drop below the level re-
quired for continuous operation. In sleep mode, standby power
is reduced to only about 2 mW at VIN = 10 V. In shutdown,
both MOSFET s are turned off.
TYP ICAL AP P LICATIO NS
V
(5.2V TO 18V)
IN
100
95
90
85
80
+
+
C
IN
1F
V
V
= 6V
100F
IN
V
10nF
IN
INT V
CC
P-CH
IRF7204
P-DRIVE
= 10V
IN
ADP1148
R
**
L*
SENSE
0V = NORMAL
62H
>1.5V = SHUTDOWN
0.05⍀
SHUTDOWN
V
OUT
5V/2A
I
SENSE(+)
TH
1000pF
R
C
C
SENSE(–)
N-DRIVE
T
+
C
OUT
1k⍀
75
70
N-CH
IRF7403
390F
C
T
470pF
FIGURE 1 CIRCUIT
0.02
C
C
C1
S-GND P-GND
3300pF
10BQ040
2
0.2
LOAD CURRENT – A
*COILTRONICS CTX-68-4
**KRL SL-1-C1-0R050L
Figure 1. High Efficiency Step-Down Converter
REV. A
Figure 2. ADP1148-5 Typical Efficiency
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 781/ 329-4700
Fax: 781/ 326-8703
World Wide Web Site: http:/ / w w w .analog.com
© Analog Devices, Inc., 1997
ADP1148, ADP1148-3.3, ADP1148-5
ELECTRICAL CHARACTERISTICS
P aram eter
(–40؇C ≤ T ≤ +85؇C,1 V = 10 V, VSHUTDOWN = 0 V, unless otherwise noted. See Figure 17.)
A
IN
Sym bol
Conditions2
Min
Typ
Max
Units
FEEDBACK VOLT AGE
ADP1148 Only
V10
VIN = 9 V
VIN = 9 V
ILOAD = 700 mA
ILOAD = 700 mA
1.20 1.25 1.30
V
REGULAT ED OUT PUT VOLT AGE
ADP1148-3.3
ADP1148-5
VOUT
3.17 3.33 3.4
4.85 5.05 5.2
V
V
INPUT DC SUPPLY CURRENT3
Normal Mode
Sleep Mode (ADP1148-3)
Sleep Mode (ADP1148-5)
Shutdown
IQ
VIN = 4 V < VIN < 18 V
VIN = 4 V < VIN < 18 V
VIN = 6 V < VIN < 18 V
VSHUT DOWN = 2.1 V,
4 V < VIN < 12 V
1.6
160
160
10
2.6
280
280
24
mA
µA
µA
µA
CURRENT SENSE T HRESHOLD
VOLT AGE4
V8–V7
ADP1148 Only
V9 = VOUT /4 + 25 mV (Forced),
V7 = 5 V
V9 = VOUT /4 – 25 mV (Forced),
V7 = 5 V
0
mV
mV
115
150
175
ADP1148-3.3
ADP1148-5.0
V7 = VOUT + 100 mV (Forced)
V7 = VOUT – 100 mV (Forced)
V7 = VOUT + 100 mV (Forced)
V7 = VOUT – 100 mV (Forced)
0
150
0
mV
mV
mV
mV
115
115
175
175
150
SHUT DOWN PIN T HRESHOLD
ADP1148-3.3, ADP1148-5
V10
0.55 0.8
2
V
OFF-T IME
tOFF
CT = 390 pF, ILOAD = 700 mA
4
5
6.2
µs
NOT ES
1All limits at temperature extremes are guaranteed via correlation using standard Quality Control method.
2T J is calculated from the ambient temperature T A and power dissipation PD according to the following formulas:
ADP1148AR, ADP1148AR-3, ADP1148AR-5: T J = TA + (PD × 110°C/W)
ADP1148AN, ADP1148AN-3, ADP1148AN-5: T J = TA + (PD × 70°C/W)
3Dynamic supply current is higher due to the gate charge being delivered at the switching frequency. T he allowable operating frequency may be limited by power
dissipation at high input voltages.
4T he ADP1148 version is tested with external feedback resistors setting the nominal output voltage to 3.3 V.
Specifications subject to change without notice.
ABSO LUTE MAXIMUM RATINGS
O RD ERING GUID E
Input Supply Voltage (Pin 3) . . . . . . . . . . . . . –0.3 V to +20 V
Continuous Output Currents (Pins 1, 14) . . . . . . . . . . 50 mA
Sense Voltages (Pins 7, 8) . . . . . . . . . . . . . . . . –0.3 V to VCC
Operating T emperature Range . . . . . . . . . . . . 0°C to +70°C
Extended Commercial T emperature Range . . –40°C to +85°C
Junction T emperature . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Storage T emperature Range . . . . . . . . . . . . –65°C to +150°C
Lead T emperature (Soldering, 10 sec) . . . . . . . . . . . . 300°C
O utput P ackage
Voltage D escription
P ackage
O ption
Model
ADP1148AN
ADP1148AR
ADJ
ADJ
Plastic DIP
N-14
Small Outline Package SO-14
Plastic DIP N-14
Small Outline Package SO-14
Plastic DIP N-14
Small Outline Package SO-14
ADP1148AN-3.3 3.3 V
ADP1148AR-3.3 3.3 V
ADP1148AN-5
ADP1148AR-5
5 V
5 V
REV. A
–3–
ADP1148, ADP1148-3.3, ADP1148-5
P IN FUNCTIO N D ESCRIP TIO NS
P in #
Mnem onic
Function
1
P-Channel Drive High Current Gate Drive for T op P-Channel MOSFET . T he voltage swing at Pin 4 is from V to
IN
ground.
2
3
4
NC
VIN
CT
No Connection.
Input Voltage.
External Capacitor CT from Pin 4 to Ground Sets the Operating Frequency. T he frequency is also
dependent on the ratio VOUT /VIN
.
5
Int VCC
Internal Supply Voltage, Nominally 3.3 V. Must be decoupled to signal ground. Do not externally load
this pin.
6
7
IT H
Error Amplifier Decoupling Point. T he current comparator threshold increases with the Pin 7 voltage.
Sense–
Connects to internal resistive divider that sets the output voltage in ADP1148-3.3 and ADP1148-5
versions. Pin 7 is also the (–) input for the current comparator.
8
Sense+
VFB
T he (+) Input for the Current Comparator. A built-in offset between Pins 7 and 8, in conjunction with
RSENSE, sets the current trip threshold.
9
For the ADP1148 adjustable version, Pin 9 serves as the feedback pin from an external resistive divider
used to set the output voltage. On ADP1148-3.3 and ADP1148-5 versions, this pin is not used.
10
Shutdown
T aking Pin 10 of the ADP1148, ADP1148-3.3 or ADP1148-5 high holds both MOSFET s off. Must be
at ground potential for normal operation.
11
12
13
14
Signal GND
Power GND
NC
Small Signal Ground. Must be routed separately from other grounds to the (–) terminal of COUT
.
Driver Power Ground. Connects to source of N-channel MOSFET and the (–) terminal of CIN
No Connection.
.
N-Channel Drive High Current Drive for bottom N-channel MOSFET . T he voltage swing at Pin 13 is from ground to
VIN
.
P IN CO NFIGURATIO NS
14-Lead P lastic D IP
14-Lead P lastic SO
P-DRIVE
NC
N-DRIVE
1
2
3
4
5
6
7
14
13
12
11
10
9
NC
V
POWER GND
SIGNAL GND
SHUTDOWN
IN
ADP1148
TOP VIEW
(Not to Scale)
C
T
INT V
CC
V
*
I
FB
TH
SENSE(–)
8
SENSE(+)
NC = NO CONNECT
*FIXED OUTPUT VERSIONS = SD1
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADP1148, ADP1148-3.3, ADP1148-5 feature proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high energy electrostatic discharges. T herefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. A
–4–
Typical Performance Characteristics–ADP1148, ADP1148-3.3, ADP1148-5
200
150
100
1000
1000
800
600
400
200
0
V
= V = 5V
OUT
SENSE
L = 50H
800
R
= 0.02⍀
SENSE
L = 25H
R
= 0.02⍀
600
SENSE
400
200
0
V
= 12V
IN
V
= 7V
50
0
L = 50H
IN
R
= 0.05⍀
SENSE
V
IN
= 10V
5
4
0
1
2
3
0
100
200
300
0
1
2
3
4
5
FREQUENCY – kHz
MAXIMUM OUTPUT CURRENT – A
(V –V
) VOLTAGE – V
IN OUT
Figure 3. Selecting RSENSE vs. Maxi-
m um Output Current
Figure 4. Operating Frequency vs.
Tim ing Capacitor Value
Figure 5. Selecting Minim um Output
Capacitor vs. (VIN–VOUT) and Inductor
+40
+20
0
100
98
100
2
I R
GATE CHARGE
96
95
94
I
= 1A
LOAD
I
Q
92
90
I
= 0.1A
LOAD
90
85
80
I
= 100mA
LOAD
–20
–40
–60
88
86
84
82
80
I
= 1A
LOAD
FIGURE 1 CIRCUIT
FIGURE 1 CIRCUIT
0.01
0.03
0.1
0.3
1.0
3.0
0
4
6
8
10
12
14
16
0
4
8
12
16
20
OUTPUT CURRENT – A
INPUT VOLTAGE – V
V
IN
Figure 7. Efficiency vs. Input Voltage
Figure 8. ADP1148-5 Output Voltage
Change vs. Input Voltage
Figure 6. Typical Efficiency Losses
30
25
20
1.6
60
FIGURE 1 CIRCUIT
40
1.4
ACTIVE MODE
1.2
1.0
0.8
0.6
20
V
= 2V
SHUTDOWN
V
= 6V
IN
V
0
15
10
–20
–40
–60
0.4
= 12V
IN
SLEEP MODE
0.2
5
0
0.0
4
6
8
10 12
14
16
18
20
0
0.5
1.0
1.5
2.0
2.5
4
6
8
10 12 14
16
18 20
INPUT VOLTAGE – V
LOAD CURRENT – A
INPUT VOLTAGE – V
Figure 10. DC Supply Current
Figure 11. Supply Current in Shutdown
Figure 9. Load Regulation
REV. A
–5–
ADP1148, ADP1148-3.3, ADP1148-5–Typical Performance Characteristics
80
70
60
50
1.8
30
25
20
15
10
5
1.6
0؇C
1.4
1.2
1.0
25؇C
70؇C
Qn+Qp = 100nC
40
30
0.8
0.6
5V
Qn+Qp = 50nC
20
0.4
0.2
0.0
3.3V
10
0
0
20
50
80 110 140 170 200 230 260
OPERATING FREQUENCY – kHz
0.3 0.5 1.0 1.5 2.0 2.5 3.0 3.3 3.5 4.0 4.5 5.0
OUTPUT VOLTAGE – V
1
2
4
6
8
10
12
(V –V
) – V
IN OUT
Figure 13. Gate Charge Supply
Current
Figure 14. Off Tim e vs. VOUT
Figure 12. Operating Frequency vs.
(VIN–VOUT
)
155
150
145
MAXIMUM THRESHOLD
140
135
130
125
120
0
100
85
TEMPERATURE – ؇C
25
70
Figure 15. Current Sense Threshold
Voltage
REV. A
–6–
ADP1148, ADP1148-3.3, ADP1148-5
AP P LICATIO NS
T o prevent both the external MOSFET s from ever being turned
on simultaneously, feedback is incorporated to sense the state of
the driver output pins.
T he ADP1148 uses a current-mode, constant off-time structure
to switch a pair of external complementary N- and P-channel
MOSFET s. T he operating frequency of the device is deter-
mined by the value of the external capacitor connected to the
CT pin.
Before the N drive output can go high, the P drive output must
also be high. Likewise, the P drive output is unable to go low
while the N drive output is high. By utilizing a constant off-time
structure, the device operation is a function of the input voltage.
To limit the effect of frequency variation as the device approaches
dropout, the controller begins to increase the discharge current
as VIN drops below VOUT +1.5 V. While the device is in drop-
out, the P-channel MOSFET is on constantly.
The output voltage is sensed by an internal voltage divider which is
connected to the Sense(–) pin (ADP1148-3.3 and AD1148-5) or
an external voltage divider returned to VFB (ADP1148). A voltage
comparator V, and a gain block G compare the values of the
divided output voltage with a reference voltage of 1.25 V.
To maximize the efficiency, the ADP1148 automatically switches
between two operational modes, power-saving and continuous.
T he Flip-Flop 1 is the main control element when the device is
in its power-saving mode while the gain block is the main con-
trol when the output voltage moves to continuous mode. During
the continuous mode of the PMOS switch on-cycle, the current
comparator C, monitors the voltage between Sense(–) and
Sense(+). When the voltage level reaches the threshold level, the
P drive output is switched to VIN which turns off the P-channel
MOSFET . T he timing capacitor CT is now able to discharge at
a rate determined by the off-time controller. T he discharge
current is made to be proportional to the value of the output
voltage (measured at the Sense(–) pin) to model the inductor
current which decays at a rate which is proportional to the out-
put voltage. While the timing capacitor is discharging, the N
drive output goes to VIN , turning on the N-channel MOSFET .
When the voltage level on the timing capacitor has discharged to
the threshold voltage level VT H1, comparator T switches setting
Flip-Flop 1. T his forces the N drive to go off and the P drive
output low and subsequently turns the P-channel MOSFET on.
T he sequence is then repeated. As load current increases, the
output voltage starts to reduce. T his results in the output of the
gain circuit increasing the level of the current comparator thresh-
old, thus tracking the load current.
RSENSE Selection For O utput Cur r ent
T he choice of RSENSE is based on the required output current.
T he ADP1148 current comparator has a threshold range which
extends from 0 mV to a maximum of 150 mV/RSENSE. T he
current comparator threshold sets the peak of the inductor cur-
rent, yielding a maximum output current IMAX equal to the peak
value less half the peak-to-peak ripple current. T he ADP1148
operates effectively with values of RSENSE from 20 mΩ to
200 mΩ. A graph for selecting RSENSE versus maximum output
current is given in Figure 3. Solving for RSENSE and allowing a
margin for variations in the ADP1148 and external component
values yields:
RSENSE = 100 mV/IMAX
T he peak short circuit current, (ISC(PK)) tracks IMAX. Once
RSENSE has been chosen, ISC(PK) can be predicted from the fol-
lowing equation:
ISC( PK) = 150 mV/RSENSE
T he load current, below which power-saving mode commences
(IPOWER-SAVING) is determined by the offset in comparator B and
the value of the inductor chosen. Comparator B is designed to
have approximately 5 mV offset. T his offset and the inductor
can now be used to predict the power saving mode current as
follows:
At very low load currents the power-saving sequence will be
interrupted by the Set of Flip-Flop 2, by voltage comparator B,
which also monitors the voltage across RSENSE. When the load
current decreases to half the designed inductor ripple current,
the voltage across RSENSE will reverse polarity. When this hap-
pens, comparator B will set the Q-bar output of Flip-Flop 2,
which will go to logic zero state and interrupt the cycle-by-cycle
operation and inhibit the output FET -driver. T he output of the
power supply storage capacitor will slowly be drained by the
load and the output voltage starts decreasing. When this
decreased voltage exceeds the VOS of comparator V, this in turn
will reset Flip-Flop 2, and normal cycle-by-cycle operation will
resume. If the load is very small, it will take a long time for Flip-
Flop 2 to reset, and during that time the oscillator capacitor
may discharge below VT H2. At the point at which the timing
capacitor discharges below VT H2, comparator S trips causing the
internal sleep-bar to go low. T he circuit is now in sleep mode
and the N-channel Power MOSFET remains turned off. While
the circuit remains in this mode, a significant amount of the
circuit of the IC is turned off dropping the ground current from
approximately 1.6 mA to a level of 160 µA. In this state the load
current is supplied by the output capacitor. T he sleep mode is
also terminated by the reset of Flip-Flop 2.
IPOWER-SAVING ~ 5 mV/RSENSE + VO × tOFF /2 L
T he ADP1148 automatically extends tOFF during a short circuit
to provide adequate time for the inductor current to decay be-
tween switch cycles. T he resulting ripple current causes the
average short circuit current, ISC(AVG), to be lowered to approxi-
mately IMAX
.
L and C T Selection for O per ating Fr equency
T he ADP1148 uses a constant off-time architecture with tOFF
determined by an external timing capacitor CT . Each time the
P-channel MOSFET switch turns on, the voltage on CT is reset
to approximately 3.3 V. During the off time, CT is discharged by
a current which is proportional to VOUT . T he voltage on CT is
analogous to the current in inductor L, which likewise decays at
a rate proportional to VOUT . T herefore, the inductor value must
track the timing capacitor value.
T he value of CT is calculated from the preferred continuous
mode operating frequency:
CT = 1/2.6 × 104 × f
Assumes VIN = 2 VOUT (Figure 1 circuit).
A graph for selecting CT versus frequency including the effects
of input voltage is given in Figure 5.
*Component, voltage, current, etc., values are in SI-units (international standard)
unless otherwise indicated.
REV. A
–7–
ADP1148, ADP1148-3.3, ADP1148-5
As the operating frequency is increased, the gate charge losses
will cause reduced efficiency (see Efficiency section). T he full
formula for operating frequency is given by:
components are also available from Coiltronics which do not
increase the component height significantly.
P ower MO SFET
f = ( 1 – VOUT/VIN )/tOFF
where tOFF = 1.3 × 104 × CT × VREG /VOUT .
T wo external power MOSFET s must be selected for use with
the ADP1148, a P-channel MOSFET for the main switch, and
an N-channel MOSFET for the synchronous switch. T he main
selection parameters for the power MOSFET s are the threshold
VREG is the desired output voltage (i.e., 5 V or 3.3 V), VOUT is
the measured output voltage. Thus, VREG/VOUT = 1 in regulation.
voltage VGS(T H) and on resistance RDS(ON)
.
Note that as VIN reduces, the frequency also decreases. When
the input to output voltage differential drops below 1.5 V, the
ADP1148 reduces tOFF by increasing the discharge current in
CT. T his prevents audible operation before the device goes into
dropout.
T he minimum input voltage dictates whether standard threshold
or logic-level threshold MOSFET s must be used. For VIN > 8 V,
standard threshold MOSFET s (VGS(T H) < 4 V) may be used. If
VIN is expected to drop below 8 V, logic-level threshold MOSFETs
(VGS(T H) < 2.5 V) are strongly recommended. When logic-level
MOSFET s are used, the ADP1148 supply voltage must be less
than the absolute maximum VGS rating for the MOSFET s (e.g.,
>±8 V of IRF7304.
Once the frequency has been set by CT , the inductor L must be
chosen to provide no more than 25 mV/RSENSE of peak-to-peak
inductor ripple current. T his is set by the equation:
T he maximum output current IMAX determines the RDS(ON)
requirement for the two power MOSFET s. When the ADP1148
is operating in continuous mode, the simplifying assumption can
be made that one of the two MOSFET s is always conducting
the average load current. T he duty cycles for the MOSFET and
diode are given by:
25 mV
RSENSE
VOUT × tOFF
=
LMIN
or
VOUT × tOFF × RSENSE
LMIN
=
25 mV
P-Channel Duty Cycle = VOUT/VIN
Substituting for tOFF from above gives the minimum required
inductor value of:
N-Channel Duty Cycle = (VIN – VOUT)/VIN
From the duty cycle the required RDS(ON) for each MOSFET
can be derived:
LMIN = 5.1 × 105 × RSENSE × CT × VREG
As the inductor value increases above the minimum value, the
ESR requirements for the output capacitor are relaxed at the
expense of efficiency. If too small an inductor is used, the induc-
tor current will decrease past zero and change polarity. A result
of this occurrence will be that the ADP1148 may not be in
power saving mode operation and efficiency will be significantly
reduced at low currents.
P-Ch RDS(ON) = (VIN × PP)/[VOUT × IMAX2 × (1 + dP)]
2
N-Ch
= (VIN × PN)/[(VIN – VOUT) × IMAX × (1+dN)]
RDS(ON)
where Pp and PN are the allowable power dissipations and dp and
dN are the temperature dependency of RDS(ON). PP and PN will
be determined by efficiency and/or thermal requirements (see
Efficiency). (1+d) is generally given for a MOSFET in the form
of a normalized RDS(ON) vs. temperature curve, but d = 0.007/°C
can be used as an approximation for low voltage MOSFET s.
Inductor Cor e
Once the minimum value for L is known, the selection of the
inductor must be made. High efficiency converters -π generally
cannot accommodate the core loss found in low cost powdered
iron cores, forcing the use of more expensive ferrite, molypermalloy
(MPP), or Kool Mµ® cores. Actual core loss is independent of
core size for a fixed inductor value, but it is very dependent on
inductance selected. As inductance increases, core losses de-
crease. Unfortunately, increased inductance requires more turns
of wire and therefore copper losses will increase.
T he Schottky diode D1 shown in Figure 1 conducts only during
the deadtime between the conduction of the two power
MOSFET s. D1’s purpose is to prevent the body-diode of the
N-channel MOSFET from turning on and storing charge during
the dead time, which could cost as much as 1% in efficiency. D1
should be selected for forward voltage of less than 0.5 V when
conducting IMAX
.
C IN and C O UT Selection
Ferrite designs have very low core loss, so design goals can focus
on copper loss and preventing saturation. Ferrite core material
saturates “hard,” which causes the inductance to collapse
abruptly when the peak design current is exceeded. T his results
in a sharp increase in inductor ripple current and subsequently
output voltage ripple which can cause the power saving mode
operation to be falsely triggered in the ADP1148. T o prevent
this action from occurring, do not allow the core to saturate!
In continuous mode, the source current of the P-channel
MOSFET is a square wave of duty cycle VOUT /VlN . T o prevent
large voltage transients, a low ESR input capacitor sized for the
maximum rms current must be used. T he maximum rms ca-
pacitor current is given by:
CIN required
T his formula has a maximum at VIN = 2 VOUT , where IRMS
IRMS ~ [VOUT(VIN – VOUT)]0.5 × IMAX/VIN
=
IOUT /2. T his simple worst case condition is commonly used for
design because even significant deviations do not offer much
relief. Note that capacitor manufacturer’s ripple current ratings
are often based on only 2000 hours of life. T his makes it advis-
able to further derate the capacitor, or to choose a capacitor
rated at a higher temperature than required. Several capacitors
may also be paralleled to meet size or height requirements in the
design. Always consult the manufacturer if there is any question.
Molypermalloy from Magnetics, Inc., is a very good, low loss
core material for toroids, but it is more expensive than ferrite. A
reasonable compromise from the same manufacturer is Kool
Mµ. T oroids are very space efficient, especially when you can
use several layers of wire. Because they generally lack a bobbin,
mounting is more difficult. Many new designs for surface mount
All trademarks are the property of their respective holders.
REV. A
–8–
ADP1148, ADP1148-3.3, ADP1148-5
An additional 0.1 µF – 1 µF ceramic bypass capacitor is advised
on VIN Pin 3 parallel with CIN . T he selection of COUT is driven
by the required effective series resistance (ESR). T he ESR of
COUT must be less than twice the value of RSENSE for proper
operation of the ADP1148:
Although all dissipative elements in the circuit produce losses,
three main sources usually account for most of the losses in
ADP1148 circuits:
1) ADP1148 dc bias current,
2) MOSFET gate charge currents,
3) I2 × R losses.
COUT required ESR < 2 RSENSE.
1) T he dc supply current is the current which flows into VIN Pin
3 less the gate charge current. For VIN = 10 V the ADP1148
dc supply current is 160 µA for no load, and increases pro-
portionally with load up to a constant 1.6 mA after the
ADP1148 has entered continuous mode. Because the dc bias
current is drawn from VIN , the resulting loss increases with
input voltage. For VIN = 10 V the dc bias losses are generally
less than 1% for load currents over 30 mA. However, at very
low load currents the dc bias current accounts for nearly all
of the loss.
Optimum efficiency is obtained by making the ESR equal to
RSENSE. As the ESR is increased up to 2 RSENSE, the efficiency
degrades by less than 1%.
Manufacturers such as Sprague, and United Chemmicon should
be considered for high performance capacitors. T he OS-CON
semiconductor dielectric capacitor has the lowest ESR for its
size, at a somewhat higher price. Once the ESR requirement for
COUT has been met, the RMS current rating generally far ex-
ceeds the IRIPPLE(P-P) requirement.
In surface-mount applications multiple capacitors may have to
be paralleled to meet the capacitance, ESR, or RMS current
handling requirements of the application. Aluminum electrolytic
and dry tantalum capacitors are both available in surface-mount
configurations. In the case of tantalum, it is critical that the
capacitors are surge tested for use in switching power supplies.
Consult the manufacturer for other specific recommendations.
T he CO output filter capacitor has to be sized correctly to avoid
excessive ripple voltages at low frequencies. See Figure 5 for
output capacitor selection.
2) MOSFET gate charge currents result from switching the gate
capacitance of the power MOSFET s. Each time a MOSFET
gate is switched from low to high to low again, a packet of
charge dQ moves from VIN to ground. T he resulting dQ/dt is
a current out of VIN which is typically much larger than the
dc supply current. In continuous mode, IGATECHG = f (QP +
QN). T he typical gate charge for a 100 mΩ N-channel power
MOSFET is 25 nC and for the P-channel about twice that
value. T his results in IGATECHG = 7.5 mA in 100 kHz continu-
ous operation for a 2% to 3% typical midcurrent loss with
VIN = 10 V.
Tr ansient Response
T he regulator loop response can be checked by looking at the
load transient response. Switching regulators take several cycles
to respond to a step in dc (resistive) load current. When a load
step occurs, VOUT shifts by an amount equal to D1LOAD × ESR,
where ESR is the effective series resistance of COUT . D1LOAD
also begins to charge or discharge COUT until the regulator loop
adapts to the current change and returns VOUT to its steady-
state value. During this recovery time VOUT can be monitored
for overshoot or ringing which would indicate a stability prob-
lem. T he external components on the IT H pin shown in the
Figure 1 circuit will prove adequate compensation for most
applications.
Note that the gate charge loss increases directly with both
input voltage and operating frequency. T his is the principal
reason why the highest efficiency circuits operate at moderate
frequencies. Furthermore, it argues against using a larger
MOSFET than necessary to control I2 × R losses.
3) I2 × R losses are easily predicted from the dc resistances of
the MOSFET , inductor, and current shunt. In continuous
mode the average output current flows through L and
RSENSE, but is “chopped” between the P-channel and N-
channel MOSFET s. If the two MOSFET s have about the
same RDS(ON), the resistance of one MOSFET can be simply
summed with the resistances of L and RSENSE to obtain I2 × R
losses. For example, if each RDS(ON) = 100 mΩ, RL = 150 mΩ,
and RSENSE = 50 mΩ, then the total resistance is 300 mΩ.
T his results in losses ranging from 3% to 10% as the output
current increases from 0.5 A to 2 A. I2 × R losses cause the
efficiency to roll-off at high output currents.
A second, more severe transient is caused by switching in loads
with large (>1 mF) supply bypass capacitors. T he discharged
bypass capacitors are effectively put in parallel with COUT , caus-
ing a rapid drop in VOUT . No regulator can deliver enough cur-
rent to prevent this problem if the load switch resistance is low
and it is driven quickly. T he only solution is to limit the inrush
current to these capacitors below the current limit of the circuit.
Figure 6 shows how the efficiency losses in a typical ADP1148
regulator. T he gate charge loss is responsible for the majority of
the efficiency lost in the midcurrent region. If power saving
mode operation was not employed at low currents, the gate
charge loss alone would cause the efficiency to drop to unac-
ceptable levels. With power saving mode operation, the dc supply
current represents the lone (and unavoidable) loss component
which continues to become a higher percentage as output cur-
rent is reduced. As expected, the I2 × R losses dominate at high
load currents. Other losses including CIN and COUT ESR dissi-
pative losses, MOSFET switching losses, Schottky conduction
losses during deadtime and inductor core losses, generally
account for less than 2% total additional loss.
Efficiency
T he percent efficiency of a switching regulator is equal to the
output power divided by the input power times 100%. It is often
useful to analyze individual losses to determine what is limiting
the efficiency and which change would produce the most im-
provement. Percent efficiency can be expressed as:
% Efficiency = 100% - (L1 + L2 + L3 +. . . )
where L1, L2, etc. are the individual losses as a percentage of
input power. (For high efficiency circuits only small errors are
incurred by expressing losses as a percentage of output power.)
REV. A
–9–
ADP1148, ADP1148-3.3, ADP1148-5
D esign Exam ple
O utput Cr owbar
As a design example, assume VIN = 12 V (nominal), VOUT = 5 V,
IMAX = 2 A, and f = 200 kHz, RSENSE. C T, and L can immedi-
ately be calculated:
An added feature to using an N-channel MOSFET as the syn-
chronous switch is the ability to crowbar the output with the
same MOSFET . Pulling the timing cap CT pin above 1.5 V
when the output voltage is greater than the desired regulated
value will turn “on” the N-channel MOSFET and turn “off” the
P-channel MOSFET .
RSENSE = 100 mV/2 = 50 mΩ
tOFF = (1/200 kHz) × [1 – (5/12)] = 2.92 µs
CT = 2.92 µs/(1.3 × 104) = 220 pF
A fault condition such as an external short between VIN and
VOUT , or an internal short of the P-channel device which causes
the output voltage to go above a maximum allowable value can
be detected by external circuity. T urning on the N-channel
MOSFET when this fault is detected will cause large currents to
flow and blow the system fuse.
L min = 5.1 × 105 × 50 E-3 Ω × 220 pF × 5 V = 28 µH
Assume that the MOSFET dissipations are to be limited to
PN = 2PP = 250 mW.
If TA = 50°C and the thermal resistance of each MOSFET is
50°C/W, then the junction temperatures will be 63°C and dP =
dP = 0.007 × (63–25) = 0.27.
T he N-channel MOSFET needs to be sized so it will safely
handle this over current condition. T he typical delay from pull-
ing the CT pin high and the N drive, Pin 14 going high is 250 ns.
Note: under shutdown conditions, the N-channel MOSFET
is held OFF and pulling the CT pin high will not cause the
N-channel MOSFET to crowbar the output.
T he required RDS(ON) for each MOSFET can now be calculated:
P-Ch RDS(ON) = 12 × 0.25/5 × 2 × 1.27 = 120 mΩ
N-Ch RDS(ON) = 12 × 0.25/7 × 2 × 1.27 = 85 mΩ
T he P-channel requirement can be met by a IRF7204. T he
N-channel requirement can be met by a IRF7404. Note that
the most stringent requirement for the N-channel MOSFET is
with VOUT = 0 (i.e., short circuit). During a continuous short
circuit, the worst case N-channel MOSFET dissipation rises to:
A simple N-channel FET can be used as an interface between
the overvoltage detect circuitry and the ADP1148 as shown in
Figure 16.
5
INT V
CC
2
PN ~ ISC(AVG) × RDS(ON) × (1 + dN)
*FROM CROWBAR
DETECT CIRCUIT
VN2222LL
ADP1148
With the 50 mΩ sense resistor ISC(AVG) = 2 A will result, increas-
ing the N-channel dissipation to 0.45 W at die temperature of
73°C.
4
C
T
*ACTIVE WHEN V
= VIN
GATE
OFF WHEN V
GATE
= GROUND
CIN will require an rms current rating of at least 1 A at tempera-
ture, and COUT will require an ESR of 50 mΩ for optimum
efficiency.
Figure 16. Output Crowbar Interface
T r oubleshooting
Since efficiency is critical to ADP1148 applications, it is very
important to verify that the circuit is functioning correctly in
both continuous and power saving mode operation. T he wave-
form to monitor is the voltage on the timing capacitor
CT pin.
Now allow VIN to drop to its minimum value. At lower input
voltages, the operating frequency will decrease and the P-
channel will be conducting most of the time causing the power
dissipation to increase. At VIN(MIN) = 7 V, the frequency shifts
to:
fMIN = (1 – VOUT/VIN)/tOFF = (1/2.92 µs) × (1 – 5/7) = 98 kHz
and the P-channel power dissipation increases to:
PP = (120 mΩ) (2 A)2 (1.27) 5 V/7 V = 435 mW
In continuous mode (ILOAD > IPOWER SAVING MODE), the voltage
on the CT pin should be a sawtooth with a 0.9 Vp-p swing. T his
voltage should never dip below 2 V as shown in Figure 17a.
T his last step is needed to ensure the maximum temperature of
the P-channel MOSFET is not exceeded.
When load currents are low (ILOAD < IPOWER SAVING MODE), power
saving mode operation occurs. T he voltage on the CT pin now
falls to ground for periods of time as shown in Figure 17b. If the
CT pin is observed falling to ground at high output currents, it
indicates poor decoupling or improper grounding. Refer to the
Board Layout list.
AD P 1148 Adjustable Applications
When an output voltage other than 3.3 V or 5 V is required, the
ADP1148 adjustable version is used with an external resistive
divider from VOUT to VFB Pin 9. T he regulated voltage is deter-
mined by:
3.3V
VOUT = 1.25 (1 + R2/R1)
0V
(A) CONTINOUS MODE OPERATION
To prevent a stray pickup, a 100 pF capacitor is suggested across
R1 located close to the ADP1148.
3.3V
Auxiliar y Windings
T he ADP1148 synchronous switch removes the normal limita-
tion that power must be drawn from the inductor primary wind-
ing in order to extract power from auxiliary windings. With
synchronous switching, auxiliary outputs may be loaded without
regard to the primary output load, providing that the loop re-
mains in continuous mode operation.
0V
(B) POWER-SAVING MODE
Figure 17. CT Waveform s
REV. A
–10–
ADP1148, ADP1148-3.3, ADP1148-5
Boar d Layout
4) Does the (+) plate of CIN connect to the source of the
P-channel MOSFET as closely as possible? T his capacitor
provides the ac current to the P-channel MOSFET .
When laying out the printed circuit board, the following check
list should be used to ensure proper operation of the ADP1148.
T hese items are also illustrated graphically in the layout diagram
of Figure 18. Check the following in your layout:
5) Is the input decoupling capacitor (1 µF) connected closely
between VIN (Pin 3) and POWER GND (Pin 12)? T his
capacitor carries the MOSFET driver peak currents.
1) Are the signal and power grounds segregated? T he ADP1148
SIGNAL GND (Pin 11) must return to the (–) plate of COUT
T he power ground returns to the source of the N-channel
MOSFET, anode of the Schottky diode, and (–) plate of CIN
which should have as short lead lengths as possible.
.
6) Is INT VCC (Pin 5) decoupled with a 10 nF capacitor to
signal ground?
,
7) Is the SHUT DOWN (Pin 10) actively pulled to ground
during normal operation? T he Shutdown pin is high imped-
ance and must not be allowed to float.
2) Does the ADP1148 SENSE(–), (Pin 7), connect to a point
close to RSENSE and the (+) plate Of COUT ? In adjustable
versions the resistive divider R1, R2 must be connected be-
tween the (+) plate of COUT and signal ground.
T o prevent noise spikes from erroneously tripping the current
comparator, a 1000 pF capacitor is needed across Sense(–) and
Sense(+).
3) Are the SENSE(–) and SENSE(+) leads routed together with
minimum PC trace spacing? T he 1000 pF capacitor between
Pins 7 and 8 should be as close as possible to the ADP1148.
P-CHANNEL
C
D1
IN
V
IN
–
1
14
13
N-DRIVE
NC
P-DRIVE
NC
N-CHANNEL
2
1F
ADP1148
12
11
10
3
4
5
L
POWER GND
V
IN
–
SIGNAL GND
C
T
C
T
R1
R2
INT V
SHUTDOWN
CC
C
OUT
3300pF
10nF
6
7
9
8
V
OUT
I
V
TH
FB
R
1k⍀
SENSE
SENSE(–)
SENSE(+)
1000pF
R1, R2 OUTPUT DIVIDER REQUIRED
FOR ADJUSTABLE VERSION ONLY.
NC = NO CONNECT
Figure 18. ADP1148 Layout Diagram (See Board Layout)
REV. A
–11–
ADP1148, ADP1148-3.3, ADP1148-5
V
IN
4V TO 18V
C
IN
IRF7204
D1
10BQ040
100F
20V
IRF7403
14
13
1
P-DRIVE
N-DRIVE
NC
12
11
10
2
*L
50H
NC
1F
ADP1148-3.3
3
4
6
7
POWER GND
V
IN
C
SIGNAL GND
SHUTDOWN
T
C
T
9
8
300pF
INT V
CC
10nF
C
OUT
I
V
TH
FB
220F
10V
؋ 2 AVX
C
C
3300pF
SENSE(–)
SENSE(+)
**R
1000pF
SENSE
R
C
0.1⍀
1k⍀
V
*COILTRONICS CTX50-2-MP
OUT
**KRL SP-1/2-A1-0R100J
3.3V/1A
NC = NO CONNECT
Figure 19. ADP1148 Low Dropout, 3.3 V/1 A High Efficiency Regulator
V
IN
4V TO 9V
C
IN
IRF7204
D1
10BQ015
220F
20V
IRF7403
1
2
14
13
P-DRIVE
N-DRIVE
*L
50H
ADP1148 NC
NC
1F
12
11
10
3
4
5
POWER GND
V
IN
V
OUT
C
SIGNAL GND
SHUTDOWN
T
–5V/1.4A
C
T
25k⍀
1%
560pF
200pF
INT V
CC
10nF
6
7
9
8
C
OUT
I
V
TH
FB
220F
؋ 2 10V
C
C
6800pF
SENSE(–)
SENSE(+)
75k⍀
**R
R
1000pF
SENSE
C
0.05⍀
1k⍀
NC = NO CONNECT
*COILTRONICS CTX50-2-MP
**KRL SL-1-C1-0R05J
Figure 20. 4 V to 9 V Input Voltage to –5 V/1.4 A Regulator
REV. A
–12–
ADP1148, ADP1148-3.3, ADP1148-5
V
IN
5.2V TO 14V
C
IN
IRF7204
D1
10BQ040
100F
20V
IRF7403
1
2
14
P-DRIVE
N-DRIVE
NC
13
12
11
10
*L
50H
NC ADP1148
VN2222LL
1F
3
4
5
0V: V
5V: V
= 3.3V
= 5V
OUT
OUT
POWER GND
V
IN
C
SIGNAL GND
SHUTDOWN
T
C
T
R1A
33k⍀
1%
R1B
390pF
100pF
INT V
43k⍀
CC
1%
C
OUT
10nF
6
7
9
8
220F
I
V
TH
FB
10V
؋ 2 C
C
R2
OS-CON
56k⍀
3300pF
SENSE(–)
SENSE(+)
1%
**R
R
1000pF
SENSE
C
V
0.05⍀
1k⍀
OUT
3.3V/2A
OR 5V/2A
NC = NO CONNECT
*COILTRONICS CTX50-2-MP
**KRL SL-1-C1-0R050J
Figure 21. Logic Selectable 5 V/1 A or 3.3 V/2 A High Efficiency Regulator
REV. A
–13–
ADP1148, ADP1148-3.3, ADP1148-5
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
14-Lead P lastic D IP
(N-14)
0.795 (20.19)
0.725 (18.42)
14
1
8
0.280 (7.11)
0.240 (6.10)
7
0.325 (8.25)
0.195 (4.95)
0.115 (2.93)
0.300 (7.62)
0.060 (1.52)
0.015 (0.38)
PIN 1
0.210 (5.33)
MAX
0.130
(3.30)
MIN
0.160 (4.06)
0.115 (2.93)
0.015 (0.381)
0.008 (0.204)
SEATING
PLANE
0.022 (0.558)
0.014 (0.356)
0.100 0.070 (1.77)
(2.54)
BSC
0.045 (1.15)
14-Lead P lastic SO
(SO -14)
0.3444 (8.75)
0.3367 (8.55)
14
8
7
0.1574 (4.00)
0.2440 (6.20)
0.2284 (5.80)
1
0.1497 (3.80)
0.0688 (1.75)
0.0532 (1.35)
PIN 1
0.0196 (0.50)
x 45°
0.0098 (0.25)
0.0040 (0.10)
0.0099 (0.25)
8°
0°
0.0500
(1.27)
BSC
0.0192 (0.49)
0.0138 (0.35)
SEATING
PLANE
0.0500 (1.27)
0.0160 (0.41)
0.0099 (0.25)
0.0075 (0.19)
REV. A
–14–
–15–
–16–
|