Transcend Information Computer Hardware TS32M~1GCF80 User Manual

TS32M~1GCF80

80X CompactFlash Card

1. Description

1.1 Feature

The Transcend CF 80X is a High Speed Compact

Flash Card with high quality Flash Memory assembled

on a printed circuit board.

• RoHS compliant products

• Compliant with CompactFlash® specification V3.0

• Single Power Supply: 5V 10% / 3.3V 5%

• Compliant to CompactFlash, PCMCIA, and ATA

standard

Placement

•

–

• True IDE Mode: Fixed Disk (Standard)

• PC Card Mode: Removable Disk (Standard)

• Operating Temperature: -25^oC to 85^oC

• Storage Temperature: -40^oC to 85^oC

• Hardware RS-code ECC

• Support Wear-Leveling to extend product life

• Durability of Connector: 10,000 times

1.2 Dimensions

Side

Millimeters

36.40 0.150

42.80 0.100

3.30 0.100

0.63 0.070

Inches

1.43 0.005

1.69 0.004

0.13 0.004

0.02 0.003

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TS32M~1GCF80

80X CompactFlash Card

2.Product Specification

Transcend

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TS32M~1GCF80

80X CompactFlash Card

2.2 Block Diagram

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TS32M~1GCF80

80X CompactFlash Card

3. Electrical Interface

3.1 Pin Assignment and Pin Type

PC Card Memory Mode

True IDE Mode⁴

PC Card I/O Mode

Num

Signal

Name

Type

Signal

Name

Type

In, Out

Type

Num

Signal

Name

Type

In, Out

Type

In, Out Type Pin Num

GND

D03

D04

D05

D06

D07

-CE1

A10

-OE

A09

Ground

I1Z, OZ3

I3U

GND

D03

D04

D05

D06

D07

-CE1

A10

-OE

A09

Ground

I1Z, OZ3

I3U

GND

D03

Ground

I1Z, OZ3

I3Z

I/O

D04

D05

D06

D07

-CS0

A10²

-ATA SEL

A09²

I1Z

I3U

I1Z

A08

A07

VCC

A06

A05

A04

A03

A02

A01

A00

D00

D01

D02

I1Z

A08

A07

I1Z

A08²

A07²

VCC

A06²

A05²

A04²

A03²

A02

I1Z

Power

I1Z

VCC

A06

Power

I1Z

Power

I1Z

A05

I1Z

A04

I1Z

A03

I1Z

A02

I1Z

A01

I1Z

A01

I1Z

A00

I1Z

A00

I1Z

I/O

I1Z, OZ3

OT3

D00

D01

D02

-IOIS16

I/O

I1Z, OZ3

OT3

D00

I/O

I1Z, OZ3

ON3

D01

D02

-IOCS16

-CD2

-CD1

D11¹

D121

D13¹

D14¹

D15¹

-CE2¹

Ground

I1Z, OZ3

I3U

-CD2

-CD1

D11¹

D12¹

D13¹

D14¹

D15¹

-CE2¹

Ground

I1Z, OZ3

I3U

-CD2

-CD1

D11¹

D12¹

D13¹

D14¹

D15¹

-CS1¹

Ground

I1Z, OZ3

I3Z

I/O

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TS32M~1GCF80

80X CompactFlash Card

True IDE Mode⁴

PC Card Memory Mode

PC Card I/O Mode

Num

Type

In, Out

Type

Num

Signal Name

Type

In, Out

Type

Num

Type

In, Out

Type

Signal Name

-VS1

Ground

I3U

-VS1

Ground

I3U

-VS1

Ground

-IORD

I3Z

-IOWR

-WE

I3U

-IOWR

-WE

I3U

-IOWR

-WE³

I3Z

I3U

READY

VCC

OT1

Power

I2Z

-IREQ

VCC

OT1

Power

I2Z

INTRQ

VCC

OZ1

Power

I2U

-CSEL⁵

-CSEL

-VS2

OPEN

I2Z

-VS2

OPEN

I2Z

OPEN

I2Z

RESET

-RESET

-WAIT

OT1

-WAIT

OT1

IORDY

ON1

-INPACK

-REG

OT1

I3U

-INPACK

-REG

OT1

I3U

DMARQ

-DMACK ⁶

-DASP

OZ1

I3U

BVD2

OT1

-SPKR

OT1

I/O

I1U, ON1

BVD1

-STSCHG

-PDIAG

I1Z,

OZ3

I1Z,

OZ3

I1Z,

OZ3

I1Z,

OZ3

I1Z,

OZ3

I1Z,

OZ3

D08¹

D09¹

I/O

D08¹

D09¹

I/O

D08¹

D09¹

I/O

I1Z, OZ3

D10¹

GND

D10¹

GND

D10¹

GND

I1Z, OZ3

Ground

Note:

1) These signals are required only for 16 bit accesses and not required when installed in 8 bit systems. Devices

should allow for 3-state signals not to consume current.

2) The signal should be grounded by the host.

3) The signal should be tied to VCC by the host.

4) The mode is required for CompactFlash Storage Cards.

5) The -CSEL signal is ignored by the card in PC Card modes. However, because it is not pulled upon the card in these

modes, it should not be left floating by the host in PC Card modes. In these modes, the pin should be connected by the

host to PC Card A25 or grounded by the host.

6) If DMA operations are not used, the signal should be held high or tied to VCC by the host. For proper operation in older

hosts: while DMA operations are not active, the card shall ignore this signal,including a floating condition

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TS32M~1GCF80

80X CompactFlash Card

3.2 Signal Description

Signal Name

Dir.

Description

A10 – A00

8,10,11,12, These address lines along with the -REG signal are used to select the following:

14,15,16,17, The I/O port address registers within the CompactFlash Storage Card , the

(PC Card Memory Mode)

18,19,20

memory mapped port address registers within the CompactFlash Storage Card,

a byte in the card's information structure and its configuration control and status

registers.

A10 – A00

This signal is the same as the PC Card Memory Mode signal.

(PC Card I/O Mode)

A02 - A00

18,19,20

In True IDE Mode, only A[02:00] are used to select the one of eight registers

in the Task File, the remaining address lines should be grounded by the

host.

(True IDE Mode)

BVD1

I/O

This signal is asserted high, as BVD1 is not supported.

(PC Card Memory Mode)

-STSCHG

This signal is asserted low to alert the host to changes in the READY and Write

Protect states, while the I/O interface is configured. Its use is controlled by the

Card Config and Status Register.

(PC Card I/O Mode)

Status Changed

-PDIAG

In the True IDE Mode, this input / output is the Pass Diagnostic signal in the

Master / Slave handshake protocol.

(True IDE Mode)

BVD2

I/O

This signal is asserted high, as BVD2 is not supported.

(PC Card Memory Mode)

-SPKR

This line is the Binary Audio output from the card. If the Card does not support

the Binary Audio function, this line should be held negated.

(PC Card I/O Mode)

-DASP

In the True IDE Mode, this input/output is the Disk Active/Slave Present signal in

the Master/Slave handshake protocol.

(True IDE Mode)

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TS32M~1GCF80

80X CompactFlash Card

-CD1, -CD2

26,25

These Card Detect pins are connected to ground on the CompactFlash Storage

Card. They are used by the host to determine that the CompactFlash Storage

Card is fully inserted into its socket.

(PC Card Memory Mode)

-CD1, -CD2

This signal is the same for all modes.

Description

(PC Card I/O Mode)

-CD1, -CD2

(True IDE Mode)

Signal Name

Dir.

7,32

These input signals are used both to select the card and to indicate to the card

whether a byte or a word operation is being performed. -CE2 always accesses

the odd byte of the word.-CE1 accesses the even byte or the Odd byte of the

word depending on A0 and -CE2. A multiplexing scheme based on A0,-CE1,

-CE2 allows 8 bit hosts to access all data on D0-D7. See Table 27, Table 29,

Table 31, Table 35, Table 36 and Table 37.

-CE1, -CE2

(PC Card Memory Mode)

Card Enable

This signal is the same as the PC Card Memory Mode signal.

-CE1, -CE2

(PC Card I/O Mode)

Card Enable

In the True IDE Mode, -CS0 is the address range select for the task file

registers while -CS1 is used to select the Alternate Status Register and the

Device Control Register.

-CS0, -CS1

(True IDE Mode)

While –DMACK is asserted, -CS0 and –CS1 shall be held negated and the

width of the transfers shall be 16 bits.

-CSEL

This signal is not used for this mode, but should be connected by the host to PC

Card A25 or grounded by the host.

(PC Card Memory Mode)

-CSEL

This signal is not used for this mode, but should be connected by the host to PC

Card A25 or grounded by the host.

(PC Card I/O Mode)

-CSEL

This internally pulled up signal is used to configure this device as a Master or a

Slave when configured in the True IDE Mode.

(True IDE Mode)

When this pin is grounded, this device is configured as a Master.

When the pin is open, this device is configured as a Slave.

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TS32M~1GCF80

80X CompactFlash Card

D15 - D00

(PC Card Memory Mode)

31,30,29,28,

27,49,48,47,

6,5,4,3,2,

I/O

These lines carry the Data, Commands and Status information between the host

and the controller. D00 is the LSB of the Even Byte of the Word. D08 is the LSB

of the Odd Byte of the Word.

23, 22, 21

This signal is the same as the PC Card Memory Mode signal.

D15 - D00

(PC Card I/O Mode)

D15 - D00

(True IDE Mode)

In True IDE Mode, all Task File operations occur in byte mode on the low order

bus D[7:0] while all data transfers are 16 bit using D[15:0].

GND

1,50

Ground.

(PC Card Memory Mode)

GND

This signal is the same for all modes.

(PC Card I/O Mode)

GND

(True IDE Mode)

Signal Name

Dir.

Description

-INPACK

(PC Card Memory Mode)

This signal is not used in this mode.

The Input Acknowledge signal is asserted by the CompactFlash Storage Card

when the card is selected and responding to an I/O read cycle at the address

that is on the address bus. This signal is used by the host to control the enable of

any input data buffers between the CompactFlash Storage Card and the CPU.

-INPACK

(PC Card I/O Mode)

Input Acknowledge

This signal is a DMA Request that is used for DMA data transfers between host

and device. It shall be asserted by the device when it is ready to transfer data to

or from the host. For Multiword DMA transfers, the direction of data transfer is

controlled by -IORD and -IOWR. This signal is used in a handshake manner with

-DMACK, i.e., the device shall wait until the host asserts -DMACK before

negating DMARQ, and reasserting DMARQ if there is more data to transfer.

DMARQ

(True IDE Mode)

DMARQ shall not be driven when the device is not selected.

While a DMA operation is in progress, -CS0 and –CS1 shall be held negated

and the width of the transfers shall be 16 bits.

If there is no hardware support for DMA mode in the host, this output signal is not

used and should not be connected at the host. In this case, the BIOS must report

that DMA mode is not supported by the host so that device drivers will not

attempt DMA mode.

A host that does not support DMA mode and implements both PCMCIA and

True-IDE modes of operation need not alter the PCMCIA mode connections

while in True-IDE mode as long as this does not prevent proper operation in any

mode.

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TS32M~1GCF80

80X CompactFlash Card

-IORD

(PC Card Memory Mode)

This signal is not used in this mode.

This is an I/O Read strobe generated by the host. This signal gates I/O data onto

the bus from the CompactFlash Storage Card when the card is configured to use

the I/O interface.

-IORD

(PC Card I/O Mode)

In True IDE Mode, this signal has the same function as in PC Card I/O Mode.

This signal is not used in this mode.

-IORD

(True IDE Mode )

-IOWR

(PC Card Memory Mode)

-IOWR

The I/O Write strobe pulse is used to clock I/O data on the Card Data bus into

the CompactFlash Storage Card controller registers when the CompactFlash

Storage Card is configured to use the I/O interface.

(PC Card I/O Mode)

The clocking shall occur on the negative to positive edge of the signal (trailing

edge).

-IOWR

In True IDE Mode, this signal has the same function as in PC Card I/O Mode.

(True IDE Mode)

Signal Name

Dir.

Description

-OE

(PC Card Memory Mode)

This is an Output Enable strobe generated by the host interface. It is used to

read data from the CompactFlash Storage Card in Memory Mode and to read

the CIS and configuration registers.

In PC Card I/O Mode, this signal is used to read the CIS and configuration

registers.

-OE

(PC Card I/O Mode)

-ATA SEL

(True IDE Mode)

To enable True IDE Mode this input should be grounded by the host.

READY

(PC Card Memory Mode)

In Memory Mode, this signal is set high when the CompactFlash Storage Card

is ready to accept a new data transfer operation and is held low when the card is

busy.

At power up and at Reset, the READY signal is held low (busy) until the

CompactFlash Storage Card has completed its power up or reset function. No

access of any type should be made to the CompactFlash Storage Card during

this time.

Note, however, that when a card is powered up and used with RESET

continuously disconnected or asserted, the Reset function of the RESET pin is

disabled. Consequently, the continuous assertion of RESET from the

application of power shall not cause the READY signal to remain continuously in

the busy state.

-IREQ

(PC Card I/O Mode)

I/O Operation – After the CompactFlash Storage Card Card has been

configured for I/O operation, this signal is used as -Interrupt Request. This line is

strobed low to generate a pulse mode interrupt or held low for a level mode

interrupt.

INTRQ

(True IDE Mode)

In True IDE Mode signal is the active high Interrupt Request to the host.

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TS32M~1GCF80

80X CompactFlash Card

-REG

(PC Card Memory Mode)

Attribute Memory Select

This signal is used during Memory Cycles to distinguish between Common

Memory and Register (Attribute) Memory accesses. High for Common Memory,

Low for Attribute Memory.

-REG

(PC Card I/O Mode)

The signal shall also be active (low) during I/O Cycles when the I/O address is

on the Bus.

-DMACK

(True IDE Mode)

This is a DMA Acknowledge signal that is asserted by the host in response to

DMARQ to initiate DMA transfers.

While DMA operations are not active, the card shall ignore the -DMACK signal,

including a floating condition.

If DMA operation is not supported by a True IDE Mode only host, this signal

should be driven high or connected to VCC by the host.

A host that does not support DMA mode and implements both PCMCIA and

True-IDE modes of operation need not alter the PCMCIA mode connections

while in True-IDE mode as long as this does not prevent proper operation all

modes.

Signal Name

Dir.

Description

RESET

The CompactFlash Storage Card is Reset when the RESET pin is high with the

following important exception:

(PC Card Memory Mode)

The host may leave the RESET pin open or keep it continually high from the

application of power without causing a continuous Reset of the card. Under

either of these conditions, the card shall emerge from power-up having

completed an initial Reset.

The CompactFlash Storage Card is also Reset when the Soft Reset bit in the

Card Configuration Option Register is set.

RESET

This signal is the same as the PC Card Memory Mode signal.

(PC Card I/O Mode)

In the True IDE Mode, this input pin is the active low hardware reset from the

host.

-RESET

(True IDE Mode)

VCC

13,38

+5 V, +3.3 V power.

(PC Card Memory Mode)

VCC

This signal is the same for all modes.

(PC Card I/O Mode)

VCC

(True IDE Mode)

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TS32M~1GCF80

80X CompactFlash Card

-VS1

Voltage Sense Signals. -VS1 is grounded on the Card and sensed by the Host

so that the CompactFlash Storage Card CIS can be read at 3.3 volts and -VS2 is

reserved by PCMCIA for a secondary voltage and is not connected on the Card.

-VS2

(PC Card Memory Mode)

-VS1

This signal is the same for all modes.

-VS2

(PC Card I/O Mode)

-VS1

This signal is the same for all modes.

-VS2

(True IDE Mode)

-WAIT

(PC Card Memory Mode)

The -WAIT signal is driven low by the CompactFlash Storage Card to signal the

host to delay completion of a memory or I/O cycle that is in progress.

-WAIT

(PC Card I/O Mode)

This signal is the same as the PC Card Memory Mode signal.

IORDY

(True IDE Mode)

In True IDE Mode, except in Ultra DMA modes, this output signal may be used

as IORDY.

Signal Name

Dir.

Description

-WE

This is a signal driven by the host and used for strobing memory write data to the

registers of the CompactFlash Storage Card when the card is configured in the

memory interface mode. It is also used for writing the configuration registers.

(PC Card Memory Mode)

-WE

In PC Card I/O Mode, this signal is used for writing the configuration registers.

(PC Card I/O Mode)

-WE

In True IDE Mode, this input signal is not used and should be connected to VCC

(True IDE Mode)

(PC Card Memory Mode)

Write Protect

by the host.

Memory Mode – The CompactFlash Storage Card does not have a write protect

switch. This signal is held low after the completion of the reset initialization

sequence.

-IOIS16

(PC Card I/O Mode)

I/O Operation – When the CompactFlash Storage Card is configured for I/O

Operation Pin 24 is used for the -I/O Selected is 16 Bit Port (-IOIS16) function. A

Low signal indicates that a 16 bit or odd byte only operation can be performed at

the addressed port.

In True IDE Mode this output signal is asserted low when this device is expecting

a word data transfer cycle.

-IOCS16

(True IDE Mode)

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TS32M~1GCF80

80X CompactFlash Card

3.3 Electrical Specification

The following tables indicate all D.C. Characteristics for the CompactFlash Storage Card. Unless otherwise stated,

conditions are:

Vcc = 5V 10%

Vcc = 3.3V 5%

ꢀ

Absolute Maximum Conditions

Input Power

3.3.1 Input Leakage Current

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TS32M~1GCF80

80X CompactFlash Card

3.3.2 Input Characteristics

3.3.2.1 CompactFlash interface I/O at 5.0V

Parameter

Symbol

Min.

4.5

Max.

Unit

Remark

Supply Voltage

V_CC

V_OH

V_OL

5.5

High level output voltage

Low level output voltage

V_CC-0.8

0.8

4.0

2.6

Non-schmitt trigger

Schmitt trigger¹

High level input voltage

V_IH

V_IL

0.8

1.79

86.56

244

Non-schmitt trigger

Schmitt trigger¹

Low level input voltage

Pull up resistance²

R_PU

R_PD

52.54

kOhm

Pull down resistance

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TS32M~1GCF80

80X CompactFlash Card

3.3.2.2 CompactFlash interface I/O at 3.3V

Parameter

Symbol

Min.

3.135

Max.

Unit

Remark

Supply Voltage

V_CC

V_OH

V_OL

3.465

High level output voltage

Low level output voltage

V_CC-0.8

0.8

2.4

Non-schmitt trigger

Schmitt trigger¹

High level input voltage

V_IH

V_IL

1.67

0.6

1.07

Non-schmitt trigger

Schmitt trigger¹

Low level input voltage

Pull up resistance²

R_PU

R_PD

81.39

154.85

172

kOhm

Pull down resistance

3.3.2.3 The I/O pins other than CompactFlash interface

Parameter

Symbol

Min.

Max.

Unit

Remark

Supply Voltage

V_CC

V_OH

V_OL

3.135

2.4

3.465

High level output voltage

Low level output voltage

0.4

2.0

1.4

Non-schmitt trigger

Schmitt trigger

High level input voltage

Low level input voltage

V_IH

V_IL

0.8

1.2

Non-schmitt trigger

Schmitt trigger

Pull up resistance

R_PU

R_PD

kOhm

Pull down resistance

1. Include CE1,CE2 ,HREG ,HOE ,HIOE ,HWE ,HIOW pins.

2. Include CE1,CE2 ,HREG ,HOE , HIOE ,HWE ,HIOW ,CSEL ,PDIAG ,DASP pins.

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TS32M~1GCF80

80X CompactFlash Card

3.3.3 Output Drive Type

3.3.4 Output Drive Characteristics

ꢀ

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TS32M~1GCF80

80X CompactFlash Card

3.4 Signal Interface

Electrical specifications shall be maintained to ensure data reliability.

Item

Signal

Card¹⁰

Host¹⁰

-CE1

-CE2

-REG

-IORD

-IOWR

-OE

Pull-up to V_CC500 K

50 K and

Control Signal

shall be sufficient to keep inputs inactive

when the pins are not connected at the host.¹

1,2

Pull-up to V_CC500 K

50 K

-WE

1,2,9,

RESET

READY

-WAIT

Status Signal

Pull-up to V_CC

10 K

In PCMCIA PC Card modes Pull-up to V_CC

10 K

In True IDE mode, if DMA operation is

supported by the host, Pull-down to Gnd R

5.6 K

-INPACK

PC Card / True IDE hosts switch the pull-up

to pull down in True IDE mode if DMA

operation is supported.

The PC Card mode Pull-up may be left

active during True IDE mode if True IDE

DMA operation is not supported.

A[10:00]

-CSEL

D[15:00]

Address

Data Bus

Card Detect

-CD[2:1] Connected to GND in the card

-VS1

-VS2

Voltage Sense

Battery/Detect

Pull-up to Vcc 10 K

100K

3.6

BVD[2:1]

Pull-up R

50 K

Notes: 1) Control Signals: each card shall present a load to the socket no larger than 50 pF ¹⁰at a DC current of 700 A low

state and 150 A high state, including pull-resistor. The socket shall be able to drive at least the following load ¹⁰

while meeting all AC timing requirements: (the number of sockets wired in parallel) multiplied by (50 pF with DC

current 700 A low state and 150 A high state per socket).

2) Resistor is optional.

3) Status Signals: the socket shall present a load to the card no larger than 50 pF ¹⁰at a DC current of 400 A low state

and 100 A high state, including pull-up resistor. The card shall be able to drive at least the following load 10 while

meeting all AC timing requirements: 50 pF at a DC current of 400 A low state and 100 A high state.

4) Status Signals: the socket shall present a load to the card no larger than 50 pF 10 at a DC current of 400 A low state

and 100 A high state, including pull-up resistor. The card shall be able to drive at least the following load ¹⁰while

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TS32M~1GCF80

80X CompactFlash Card

meeting all AC timing requirements: 50 pF at a DC current of 400 A low state and 100 A high state.

5) Status Signals: the socket shall present a load to the card no larger than 50 pF ¹⁰at a DC current of 400 A low state

and 100 A high state, including pull-up resistor. The card shall be able to drive at least the following load 10 while

meeting all AC timing requirements: 50 pF at a DC current of 400 A low state and 1100 A high state.

6) BVD2 was not defined in the JEIDA 3.0 release. Systems fully supporting JEIDA release 3 SRAM cards shall pull-up

pin 45 (BVD2) to avoid sensing their batteries as “Low.”

7) Address Signals: each card shall present a load of no more than 100pF ¹⁰at a DC current of 450 A low state and

150 A high state. The host shall be able to drive at least the following load 10 while meeting all AC timing

requirements: (the number of sockets wired in parallel) multiplied by (100pF with DC current 450 A low state and

150 A high state per socket).

8) Data Signals: the host and each card shall present a load no larger than 50pF ¹⁰at a DC current of 450 A and 150

A high state. The host and each card shall be able to drive at least the following load 10 while meeting all AC

timing requirements: 100pF with DC current 1.6mA low state and 300 A high state. This permits the host to wire

two sockets in parallel without derating the card access speeds.

9) Reset Signal: This signal is pulled up to prevent the input from floating when a CFA to PCMCIA adapter is used in a

PCMCIA revision 1 host. However, to minimize DC current drain through the pull-up resistor in normal operation the

pull-up should be turned off once the Reset signal has been actively driven low by the host. Consequently, the input

is specified as an I2Z because the resistor is not necessarily detectable in the input current leakage test.

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3.5 Attribute Memory Read Timing

Figure: Attribute Memory Read Timing Diagram

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3.6 Configuration Register (Attribute Memory) Write Timing

Figure: Configuration Register (Attribute Memory) Write Timing Diagram

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3.7 Common Memory Read Timing Specification

Cycle Time Mode:

250 ns

120 ns

100 ns

80 ns

ns.

IEEE

Symbol

Min Max Min Max Min Max Min

Item

Symbol

ns.

125

100

ns.

Output Enable Access Time

ta(OE)

tGLQV

Output Disable Time from OE tdis(OE)

tGHQZ

tAVGL

Address Setup Time

Address Hold Time

tsu(A)

th(A)

tGHAX

CE Setup before OE

CE Hold following OE

Wait Delay Falling from OE

Data Setup for Wait Release

Wait Width Time²

tsu(CE)

th(CE)

tELGL

tGHEH

tGLWTV

tQVWTH

tWTLWTH

tv(WT-OE

)

na¹

tv(WT)

tw(WT)

350

Notes:1) –WAIT is not supported in this mode.

2) The maximum load on -WAIT is 1 LSTTL with 50 pF (40pF below 120nsec Cycle Time) total load. All times are in

nanoseconds. Dout signifies data provided by the CompactFlash Storage Card to the system. The -WAIT signal may be ignored

if the -OE cycle to cycle time is greater than the Wait Width time. The Max Wait Width time can be determined from the Card

Information Structure. The Wait Width time meets the PCMCIA PC Card specification of 12µs but is intentionally less in this

specification.

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3.8 Common Memory Write Timing Specification

Cycle Time Mode: 250 ns

120 ns

100 ns

80 ns

IEEE

Symbol

Min

ns.

Max

ns.

Min

ns.

Max

ns.

Min

ns.

Max

ns.

Min

ns.

Item

Symbol

ns.

Data Setup before WE

Data Hold following WE

WE Pulse Width

tsu (D-WEH)

th(D)

tDVWH

tWMDX

tWLWH

tAVWL

150

tw(WE)

tsu(A)

Address Setup Time

CE Setup before WE

Write Recovery Time

Address Hold Time

tsu(CE)

trec(WE)

th(A)

tELWL

tWMAX

tGHAX

CE Hold following WE

Wait Delay Falling from WE

th(CE)

tGHEH

tv (WT-WE)

tWLWTV

tWTHWH

tWTLWTH

na¹

WE High from Wait Release tv(WT)

Wait Width Time2 tw (WT)

Notes: 1) –WAIT is not supported in this mode.

na¹

350

2) The maximum load on -WAIT is 1 LSTTL with 50 pF (40pF below 120nsec Cycle Time) total load. All times are in

nanoseconds. Din signifies data provided by the system to the CompactFlash Storage Card. The -WAIT signal may be

ignored if the -WE cycle to cycle time is greater than the Wait Width time. The Max Wait Width time can be determined from

the Card Information Structure. The Wait Width time meets the PCMCIA PC Card specification of 12µs but is intentionally

less in this specification.

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3.9 I/O Input (Read) Timing Specification

Cycle Time Mode: 250 ns

120 ns

100 ns

80 ns

ns.

IEEE

Symbol

Min

ns.

Max

ns.

Min

ns.

Max

ns.

Min

ns.

Max

ns.

Min

ns.

Item

Symbol

td(IORD)

Data Delay after IORD

Data Hold following IORD

IORD Width Time

tlGLQV

100

th(IORD)

tlGHQX

tlGLIGH

tAVIGL

tlGHAX

tELIGL

165

tw(IORD)

Address Setup before IORD

Address Hold following IORD

CE Setup before IORD

CE Hold following IORD

REG Setup before IORD

REG Hold following IORD

tsuA(IORD)

thA(IORD)

tsuCE(IORD)

thCE(IORD)

tsuREG (IORD)

thREG (IORD)

tlGHEH

tRGLIGL

tlGHRGH

INPACK Delay Falling from IORD³

INPACK Delay Rising from IORD³

tdfINPACK (IORD)

tlGLIAL

na¹

tdrINPACK (IORD) tlGHIAH

IOIS16 Delay Falling from Address³

IOIS16 Delay Rising from Address³

Wait Delay Falling from IORD³

tdfIOIS16 (ADR)

tdrIOIS16 (ADR)

tdWT(IORD)

tAVISL

na¹

na²

tAVISH

tlGLWTL

Data Delay from Wait Rising³

Wait Width Time3

td(WT)

tw(WT)

tWTHQV

na²

tWTLWTH

350

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3.10 I/O Output (Write) Timing Specification

Cycle Time Mode:

255 ns

120 ns

100 ns

80 ns

IEEE

Symbol

Min

ns.

Max

ns.

Min Max

ns. ns.

Min Max

ns. ns.

Min

ns.

Item

Symbol

tsu(IOWR)

ns.

Data Setup before IOWR

Data Hold following IOWR

IOWR Width Time

tDVIWH

tlWHDX

tlWLIWH

tAVIWL

tlWHAX

tELIWL

165

th(IOWR)

tw(IOWR)

Address Setup before IOWR

Address Hold following IOWR

CE Setup before IOWR

CE Hold following IOWR

REG Setup before IOWR

REG Hold following IOWR

tsuA(IOWR)

thA(IOWR)

tsuCE (IOWR)

thCE (IOWR)

tsuREG (IOWR)

thREG (IOWR)

tlWHEH

tRGLIWL

tlWHRGH

IOIS16 Delay Falling from Address³

IOIS16 Delay Rising from Address³

tdfIOIS16 (ADR)

tdrIOIS16 (ADR)

tAVISL

tAVISH

na¹

na²

Wait Delay Falling from IOWR³

IOWR high from Wait high³

tdWT(IOWR)

tlWLWTL

tWTJIWH

tdrIOWR (WT)

na²

tWTLWT

Wait Width Time³

tw(WT)

350

na²

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3.11 True IDE PIO Mode Read/Write Timing Specification

Mode

Item

Note

Cycle time (min)

600

383

240

180

120

100

Address Valid to -IORD/-IOWR

setup (min)

t2i

-IORD/-IOWR (min)

165

290

125

290

100

290

-IORD/-IOWR (min) Register (8 bit)

-IORD/-IOWR recovery time (min)

-IOWR data setup (min)

-IOWR data hold (min)

-IORD data setup (min)

-IORD data hold (min)

T6Z -IORD data tristate (max)

Address valid to -IOCS16 assertion

(max)

n/a

Address valid to -IOCS16 released

(max)

n/a

-IORD/-IOWR to address valid hold

Read Data Valid to IORDY active

(min), if IORDY initially low after tA

tRD

IORDY Setup time

na⁵

125

IORDY Pulse Width (max)

IORDY assertion to release (max)

1250 1250 1250 1250 na⁵

na⁵

Notes: All timings are in nanoseconds. The maximum load on -IOCS16 is 1 LSTTL with a 50 pF (40pF below 120nsec Cycle Time)

total load. All times are in nanoseconds. Minimum time from -IORDY high to -IORD high is 0 nsec, but minimum -IORD width

shall still be met.

1) t0 is the minimum total cycle time, t2 is the minimum command active time, and t2i is the minimum command recovery time or

command inactive time. The actual cycle time equals the sum of the actual command active time and the actual command

inactive time. The three timing requirements of t0, t2, and t2i shall be met. The minimum total cycle time requirement is greater

than the sum of t2 and t2i. This means a host implementation can lengthen either or both t2 or t2i to ensure that t0 is equal to

or greater than the value reported in the device’s identify device data. A CompactFlash Storage Card implementation shall

support any legal host implementation.

2) This parameter specifies the time from the negation edge of -IORD to the time that the data bus is no longer driven by the

CompactFlash Storage Card (tri-state).

3) The delay from the activation of -IORD or -IOWR until the state of IORDY is first sampled. If IORDY is inactive then the host

shall wait until IORDY is active before the PIO cycle can be completed. If the CompactFlash Storage Card is not driving IORDY

negated at tA after the activation of -IORD or -IOWR, then t5 shall be met and tRD is not applicable. If the CompactFlash

Storage Card is driving IORDY negated at the time tA after the activation of -IORD or -IOWR, then tRD shall be met and t5 is

not applicable.

4) t7 and t8 apply only to modes 0, 1 and 2. For other modes, this signal is not valid.

5) IORDY is not supported in this mode.

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3.12 True IDE Multiword DMA Mode Read/Write Timing Specification

The timing diagram for True IDE DMA mode of operation in this section is drawn using the conventions in the ATA-4

specification. Signals are shown with their asserted state as high regardless of whether the signal is actually negative or positive

true. Consequently, the -IORD, the -IOWR and the -IOCS16 signals are shown in the diagram inverted from their electrical states

on the bus.

Mode 0

(ns)

Mode 1

(ns)

Mode 2

(ns)

Mode 3

(ns)

Mode 4

(ns)

Item

Note

Cycle time (min)

480

215

150

120

100

-IORD / -IOWR asserted width (min)

-IORD data access (max)

-IORD data hold (min)

150

-IORD/-IOWR data setup (min)

-IOWR data hold (min)

100

DMACK to –IORD/-IOWR setup (min)

-IORD / -IOWR to -DMACK hold (min)

-IORD negated width (min)

-IOWR negated width (min)

-IORD to DMARQ delay (max)

-IOWR to DMARQ delay (max)

CS(1:0) valid to –IORD / -IOWR

CS(1:0) hold

215

120

t^KR

t^KW

t^LR

t^LW

-DMACK

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4. Card Configuration

The CompactFlash Storage Cards is identified by appropriate information in the Card Information Structure (CIS).

The following configuration registers are used to coordinate the I/O spaces and the Interrupt level of cards that are

located in the system. In addition, these registers provide a method for accessing status information about the

CompactFlash Storage Card that may be used to arbitrate between multiple interrupt sources on the same

interrupt level or to replace status information that appears on dedicated pins in memory cards that have alternate

use in I/O cards.

4.1 Multiple Function CompactFlash Storage Cards

Table: CompactFlash Storage Card Registers and Memory Space Decoding

-CE2 -CE1 -REG -OE -WE A10 A9 A8-A4 A3 A2 A1 A0

SELECTED SPACE

Standby and UDMA transfer

Configuration Registers Read

Common Memory Read (8 Bit D7-D0)

Common Memory Read (8 Bit D15-D8)

Common Memory Read (16 Bit D15-D0)

Configuration Registers Write

Common Memory Write (8 Bit D7-D0)

Common Memory Write (8 Bit D15-D8)

Common Memory Write (16 Bit D15-D0)

Card Information Structure Read

Invalid Access (CIS Write)

Invalid Access (Odd Attribute Read)

Invalid Access (Odd Attribute Write)

Invalid Access (Odd Attribute Read)

Invalid Access (Odd Attribute Write)

Table: CompactFlash Storage Card Configuration Registers Decoding

-CE2 -CE1 -REG -OE -WE A10 A9 A8-A4 A3 A2 A1 A0 SELECTED REGISTER

Configuration Option Reg Read

Configuration Option Reg Write

Card Status Register Read

Card Status Register Write

Pin Replacement Register Read

Pin Replacement Register Write

Socket and Copy Register Read

Socket and Copy Register Write

Note: For CompactFlash Storage Cards, the location of the card configuration registers should always be read from the

CIS since these locations may vary in future products.

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4.2 Attribute Memory Function

Attribute memory is a space where CompactFlash Storage Card identification and configuration information are

stored, and is limited to 8 bit wide accesses only at even addresses. The card configuration registers are also

located here. For CompactFlash Storage Cards, the base address of the Card configuration registers is 200h.

Table: Attribute Memory Function

Function Mode

Standby Mode

DMA CMD -REG -CE2 -CE1 A10

A0 -OE -WE

D15-D8

D7-D0

Don’t Care

High Z

Standby Mode

UDMA Operation (see section

4.3.18: Ultra DMA Mode

Even

Byte

Yes

Odd Byte

Read/Write

Specification)

Timing

Read Byte Access CIS ROM

(8 bits)

Even

Byte

High Z

Write Byte Access CIS (8 bits)

(Invalid)

Don’t

Care

Even

Byte

Read

Byte

Access

Even

Byte

Configuration CompactFlash

Storage (8 bits)

High Z

Write

Byte

Access

Don’t

Care

Even

Byte

Configuration CompactFlash

Storage (8 bits)

Read Word Access CIS (16

bits)

Even

Byte

Not Valid

Write Word Access CIS (16

bits) (Invalid)

Don’t

Care

Even

Byte

Read

Word

Access

Even

Byte

Configuration CompactFlash

Storage (16 bits)

Not Valid

Write

Word

Access

Don’t

Care

Even

Byte

Configuration CompactFlash

Storage (16 bits)

Note: The -CE signal or both the -OE signal and the -WE signal shall be de-asserted between consecutive cycle

operations.

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4.3 Configuration Option Register(Base + 00h in Attribute Memory)

The Configuration Option Register is used to configure the cards interface, address decoding and interrupt and to

issue a soft reset to the CompactFlash Storage Card.

SRESET - Soft Reset: setting this bit to one (1), waiting the minimum reset width time and returning to zero (0) places the

CompactFlash Storage Card in the Reset state. Setting this bit to one (1) is equivalent to assertion of the

+RESET signal except that the SRESET bit is not cleared. Returning this bit to zero (0) leaves the

CompactFlash Storage Card in the same un-configured, Reset state as following power-up and hardware

reset. This bit is set to zero (0) by power-up and hardware reset. For CompactFlash Storage Cards, using the

PCMCIA Soft Reset is considered a hard Reset by the ATA Commands. Contrast with Soft Reset in the

Device Control Register.

LevlREQ: this bit is set to one (1) when Level Mode Interrupt is selected, and zero (0) when Pulse Mode is selected. Set

to zero (0) by Reset.

Conf5 - Conf0 - Configuration Index: set to zero (0) by reset. It is used to select operation mode of the CompactFlash

Storage Card as shown below.

Note: Conf5 and Conf4 are reserved for CompactFlash Storage cards and shall be written as zero (0).

4.4 Card Configuration and Status Register (Base + 02h in Attribute Memory)

The Card Configuration and Status Register contains information about the Card’s condition.

Changed: indicates that one or both of the Pin Replacement register CReady, or CWProt bits are set to one (1). When

the Changed bit is set, -STSCHG Pin 46 is held low if the SigChg bit is a One (1) and the CompactFlash

Storage Card is configured for the I/O interface.

SigChg: this bit is set and reset by the host to enable and disable a state-change “signal” from the Status Register, the

Changed bit controls pin 46, the Changed Status signal. If no state change signal is desired, this bit is set to zero

(0) and pin 46 (-STSCHG) signal is then held high while the CompactFlash Storage Card is configured for I/O.

IOis8: the host sets this bit to a one (1) if the CompactFlash Storage Card is to be configured in an 8 bit I/O Mode. The

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CompactFlash Storage Card is always configured for both 8 and 16 bit I/O, so this bit is ignored.

-XE: For CompactFlash cards that do not support Power Level 1, this bit has value 0 and is not writeable.

Audio:This bit should always be zero for CompactFlash Storage cards.

PwrDwn: this bit indicates whether the host requests the CompactFlash Storage Card to be in the power saving or active

mode. When the bit is one (1), the CompactFlash Storage Card enters a power down mode. When PwrDwn is

zero (0), the host is requesting the CompactFlash Storage Card enter the active mode. The PCMCIA READY

value becomes false (busy) when this bit is changed. READY shall not become true (ready) until the power state

requested has been entered. The CompactFlash Storage Card automatically powers down when it is idle and

powers back up when it receives a command.

Int: this bit represents the internal state of the interrupt request. This value is available whether or not the I/O interface has

been configured. This signal remains true until the condition that caused the interrupt request has been serviced. If

interrupts are disabled by the -IEN bit in the Device Control Register, this bit is a zero (0).

4.5 Pin Replacement Register (Base + 04h in Attribute Memory)

CReady: this bit is set to one (1) when the bit RReady changes state. This bit can also be written by the host.

CWProt: this bit is set to one (1) when the RWprot changes state. This bit may also be written by the host.

RReady: this bit is used to determine the internal state of the READY signal. This bit may be used to determine the state

of the READY signal as this pin has been reallocated for use as Interrupt Request on an I/O card. When written,

this bit acts as a mask (MReady) for writing the corresponding bit CReady.

WProt: this bit is always zero (0) since the CompactFlash Storage Card does not have a Write Protect switch. When

written, this bit acts as a mask for writing the corresponding bit CWProt.

MReady: this bit acts as a mask for writing the corresponding bit CReady.

MWProt: this bit when written acts as a mask for writing the corresponding bit CWProt.

Table: Pin Replacement Changed Bit/Mask Bit Values

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4.6 Socket and Copy Register (Base + 06h in Attribute Memory)

This register contains additional configuration information. This register is always written by the system before writing

the card’s Configuration Index Register. This register is not required for CF Cards.

If present, it is optional for a CF Card to allow setting bit D4 (Drive number) to 1. If two drives are supported, it is

intended for use only when two cards are co-located at either the primary or secondary addresses in PCMCIA I/O mode.

The availability and capabilities of this register are described in the Card Information Structure of the CF Card.

Hosts shall not depend on the availability of this functionality.

Reserved: this bit is reserved for future standardization. This bit shall be set to zero (0) by the software when the register

is written.

Obsolete (Drive #): this bit is obsolete and should be written as 0.

If the obsolete functionality is not supported it shall be read as written or shall be read as 0. If the obsolete

functionality is supported, the bit shall be read as written. If supported, this bit sets the drive number, which the card

matches with the DRV bit of the Drive/Head register when configured in a twin card configuration.

It is recommended that the host always write 0 for the drive number in this register and in the DRV bit of the

Drive/Head register for PCMCIA modes of operation.

X: the socket number is ignored by the CompactFlash Storage Card.

4.7 I/O Transfer Function

The I/O transfer to or from the CompactFlash Storage can be either 8 or 16 bits. When a 16 bit accessible

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port is addressed, the signal -IOIS16 is asserted by the CompactFlash Storage. Otherwise, the -IOIS16 signal

is de-asserted. When a 16 bit transfer is attempted, and the -IOIS16 signal is not asserted by the CompactFlash

Storage, the system shall generate a pair of 8 bit references to access the word‘s even byte and odd byte. The

CompactFlash Storage Card permits both 8 and 16 bit accesses to all of its I/O addresses, so -IOIS16 is

asserted for all addresses to which the CompactFlash Storage responds. The CompactFlash Storage Card may

request the host to extend the length of an input cycle until data is ready by asserting the -WAIT signal at the

start of the cycle.

Table: PCMCIA Mode I/O Function

Function Code

Standby Mode

-REG -CE2 -CE1

-IORD

-IOWR

D15-D8

High Z

D7-D0

High Z

Even-Byte

Odd-Byte

Byte Input Access (8 bits)

Byte Output Access (8 bits)

Don’t Care

Even-Byte

Odd-Byte

Word Input Access (16 bits)

Word Output Access (16 bits)

Odd-Byte

Even-Byte

I/O Read Inhibit

Don’t Care

High Z

Don’t Care

High Z

I/O Write Inhibit

High Byte Input Only (8 bits)

Odd-Byte

High Z

High Byte Output Only (8 bits)

Odd-Byte

Don’t Care

4.8 Common Memory Transfer Function

The Common Memory transfer to or from the CompactFlash Storage can be either 8 or 16 bits.

Table: Common Memory Function

Function Code

-REG -CE2 -CE1 A0

-OE

-WE

D15-D8

D7-D0

Standby Mode

High Z

Even-Byte

Odd-Byte

Byte Read Access (8 bits)

Byte Write Access (8 bits)

Don’t Care

Even-Byte

Odd-Byte

Word Read Access (16 bits)

Word Write Access (16 bits)

Odd-Byte

Even-Byte

Odd Byte Read Only (8 bits)

Odd Byte Write Only (8 bits)

Odd-Byte

High Z

Don’t Care

4.9 True IDE Mode I/O Transfer Function

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The CompactFlash Storage Card can be configured in a True IDE Mode of operation. The CompactFlash

Storage Card is configured in this mode only when the -OE input signal is grounded by the host during the power off

to power on cycle. Optionally, CompactFlash Storage Cards may support the following optional detection methods:

1. The card is permitted to monitor the –OE (-ATA SEL) signal at any time(s) and switch to PCMCIA mode upon

detecting a high level on the pin.

2. The card is permitted to re-arbitrate the interface mode determination following a transition of the (-)RESET pin.

3. The card is permitted to monitor the –OE (-ATA SEL) signal at any time(s) and switch to True IDE mode upon

detection of a continuous low level on pin for an extended period of time.

Notes: 1) Implemented for backward compatibility. Bit D7 of the register shall remain High Z to prevent conflict with any

floppy disk controller at the same address. The host software should not rely on the contents of this register

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4.10 Host Configuration Requirements for Master/Slave or New Timing Modes

The CF Advanced Timing modes include PCMCIA PC Card style I/O modes that are faster than the original 250

ns cycle time. These modes are not supported by the PCMCIA PC Card specification nor CF by cards based on

revisions of the CF specification before Revision 3.0. Hosts shall ensure that all cards accessed through a

common electrical interface are capable of operation at the desired, faster than 250 ns, I/O mode before

configuring the interface for that I/O mode.

Advanced Timing modes are PCMCIA PC Card style I/O modes that are 100 ns or faster, PC Card Memory

modes that are 100ns or faster, True IDE PIO Modes 5,6 and Multiword DMA Modes 3,4. These modes are

permitted to be used only when a single card is present and the host and card are connected directly, without a

cable exceeding 0.15m in length. Consequently, the host shall not configure a card into an Advanced Timing

Mode if two cards are sharing I/O lines, as in Master/Slave operation, nor if it is constructed such that a cable

exceeding 0.15 meters is required to connect the host to the card.

When the use of two cards on an interface is otherwise permitted, the host may use any mode that is supported

by both cards, but to achieve maximum performance it should use its highest performance mode that is also

supported by both cards.

5 CF-ATA Drive Register Set Definition and Protocol

The CompactFlash Storage Card can be configured as a high performance I/O device through:

a) The standard PC-AT disk I/O address spaces 1F0h-1F7h, 3F6h-3F7h (primary) or 170h- 177h, 376h-377h

(secondary) with IRQ 14 (or other available IRQ).

b) Any system decoded 16 byte I/O block using any available IRQ.

c) Memory space.

The communication to or from the CompactFlash Storage Card is done using the Task File registers, which provide

all the necessary registers for control and status information related to the storage medium. The PCMCIA interface

connects peripherals to the host using four register mapping methods. Table is a detailed description of these

methods below:

Table: I/O Configurations

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5.1 I/O Primary and Secondary Address Configurations

Table: Primary and Secondary I/O Decoding

Note:

1) Register 0 is accessed with -CE1 low and -CE2 low (and A0 = Don’t Care) as a word register on the combined Odd Data

Bus and Even Data Bus (D15-D0). This register may also be accessed by a pair of byte accesses to the offset 0 with

-CE1 low and -CE2 high. Note that the address space of this word register overlaps the address space of the Error and

Feature byte-wide registers, which lie at offset 1. When accessed twice as byte register with -CE1 low, the first byte to

be accessed is the even byte of the word and the second byte accessed is the odd byte of the equivalent word access.

2) A byte access to register 0 with -CE1 high and -CE2 low accesses the error (read) or feature (write) register.

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5.2 Contiguous I/O Mapped Addressing

When the system decodes a contiguous block of I/O registers to select the CompactFlash Storage Card, the registers are

accessed in the block of I/O space decoded by the system as follows:

Table: Contiguous I/O Decoding

Notes:

1) Register 0 is accessed with -CE1 low and -CE2 low (and A0 = Don’t Care) as a word register on the combined Odd Data Bus and

Even Data Bus (D15-D0). This register may also be accessed by a pair of byte accesses to the offset 0 with -CE1 low and -CE2 high.

Note that the address space of this word register overlaps the address space of the Error and Feature byte-wide registers that lie at

offset

1. When accessed twice as byte register with -CE1 low, the first byte to be accessed is the even byte of the word and the second byte

accessed is the odd byte of the equivalent word access.

A byte access to register 0 with -CE1 high and -CE2 low accesses the error (read) or feature (write) register.

2) Registers at offset 8, 9 and D are non-overlapping duplicates of the registers at offset 0 and 1.

Register 8 is equivalent to register 0, while register 9 accesses the odd byte. Therefore, if the registers are byte accessed in the

order 9 then 8 the data shall be transferred odd byte then even byte.

Repeated byte accesses to register 8 or 0 shall access consecutive (even than odd) bytes from the data buffer. Repeated word

accesses to register 8, 9 or 0 shall access consecutive words from the data buffer. Repeated byte accesses to register 9 are not

supported. However, repeated alternating byte accesses to registers 8 then 9 shall access consecutive (even then odd) bytes from the

data buffer. Byte accesses to register 9 access only the odd byte of the data.

3) Address lines that are not indicated are ignored by the CompactFlash Storage Card for accessing all the registers in this table.

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5.3 Memory Mapped Addressing

When the CompactFlash Storage Card registers are accessed via memory references, the registers appear in the

common memory space window: 0-2K bytes as follows:

Notes:

1) Register 0 is accessed with -CE1 low and -CE2 low as a word register on the combined Odd Data Bus and Even Data Bus (D15-D0).

This register may also be accessed by a pair of byte accesses to the offset 0 with -CE1 low and -CE2 high. Note that the address

space of this word register overlaps the address space of the Error and Feature byte-wide registers that lie at offset 1. When

accessed twice as byte register with -CE1 low, the first byte to be accessed is the even byte of the word and the second byte

accessed is the odd byte of the equivalent word access.

A byte access to address 0 with -CE1 high and -CE2 low accesses the error (read) or feature (write) register.

2) Registers at offset 8, 9 and D are non-overlapping duplicates of the registers at offset 0 and 1.Register 8 is equivalent to register 0,

while register 9 accesses the odd byte. Therefore, if the registers are byte accessed in the order 9 then 8 the data shall be

transferred odd byte then even byte.

Repeated byte accesses to register 8 or 0 shall access consecutive (even then odd) bytes from the data buffer. Repeated word

accesses to register 8, 9 or 0 shall access consecutive words from the data buffer. Repeated byte accesses to register 9 are not

supported. However, repeated alternating byte accesses to registers 8 then 9 shall access consecutive (even then odd) bytes from

the data buffer. Byte accesses to register 9 access only the odd byte of the data.

3) Accesses to even addresses between 400h and 7FFh access register 8. Accesses to odd addresses between 400h and 7FFh

access register 9. This 1 Kbyte memory window to the data register is provided so that hosts can perform memory to memory block

moves to the data register when the register lies in memory space.

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Some hosts, such as the X86 processors, must increment both the source and destination addresses when executing the memory

to memory block move instruction. Some PCMCIA socket adapters also have auto incrementing address logic embedded within

them. This address window allows these hosts and adapters to function efficiently.

Note that this entire window accesses the Data Register FIFO and does not allow random access to the data buffer within the

CompactFlash Storage Card.

A word access to address at offset 8 shall provide even data on the low-order byte of the data bus, along with odd data at offset 9 on

the high-order byte of the data bus.

5.4 True IDE Mode Addressing

When the CompactFlash Storage Card is configured in the True IDE Mode, the I/O decoding is as follows:

Note: 1) See the section 6.1.5 CF-ATA Registers for information regarding the control of 8 or 16 bit transfers to the data register.

5.5 CF-ATA Registers

The following section describes the hardware registers used by the host software to issue commands to the

CompactFlash device. These registers are often collectively referred to as the “task file.”

Note: In accordance with the PCMCIA specification: each of the registers below that is located at an odd offset address

may be accessed in the PC Card Memory or PC Card I/O modes at its normal address and also the corresponding even

address (normal address -1) using data bus lines (D15-D8) when -CE1 is high and -CE2 is low unless -IOIS16 is high (not

asserted by the card) and an I/O cycle is being performed.

In the True IDE mode of operation, the size of the transfer is based solely on the register being addressed. All registers

are 8 bit only except for the Data Register, which is normally 16 bits, but can be programmed to use 8 bit transfers for

Non-DMA operations through the use of the Set Features command. The data register is also 8 bits during a portion of the

Read Long and Write Long commands, which exist solely for historical reasons and should not be used.

5.5.1 Data Register (Address - 1F0h[170h];Offset 0,8,9)

The Data Register is a 16 bit register, and it is used to transfer data blocks between the CompactFlash Storage

Card data buffer and the Host. This register overlaps the Error Register Table: Data Register Access below describes the

combinations of data register access and is provided to assist in understanding the overlapped Data Register and

Error/Feature Register rather than to attempt to define general PCMCIA word and byte access modes and operations.

See the PCMCIA PC Card Standard, for further definitions of the Card Accessing Modes for I/O and Memory cycles.

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Note: Because of the overlapped registers, PC Card modes access to the 1F1h, 171h or offset 1 are not defined for word

(-CE2 = 0 and -CE1 = 0) operations. These accesses are treated as accesses to the Word Data Register. The duplicated

registers at offsets 8, 9 and Dh have no restrictions on the operations that can be performed by the socket.

Table: Data Register Access

Notes: 1) -REG signal is mode dependent. Signal shall be 0 for I/O mode and 1 for Memory Mode.

5.5.2 Error Register (Address - 1F1h[171h]; Offset 1, 0Dh Read Only)

This register contains additional information about the source of an error when an error is indicated in bit 0 of the Status

Figure: Error Register

This register is also accessed in PC Card Modes on data bits D15-D8 during a read operation to offset 0 with -CE2 low

and -CE1 high.

Bit 7 (BBK): this bit is set when a Bad Block is detected.

Bit 6 (UNC): this bit is set when an Uncorrectable Error is encountered.

Bit 5: this bit is 0.

Bit 4 (IDNF): the requested sector ID is in error or cannot be found.

Bit 3: this bit is 0.

Bit 2 (Abort) This bit is set if the command has been aborted because of a CompactFlash Storage Card status condition:

(Not Ready, Write Fault, etc.) or when an invalid command has been issued.

Bit 1 This bit is 0.

Bit 0 (AMNF) This bit is set in case of a general error.

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5.5.3 Feature Register (Address - 1F1h[171h]; Offset 1, 0Dh Write Only)

This register provides information regarding features of the CompactFlash Storage Card that the host can utilize. This

-CE1 high.

5.5.4 Sector Count Register (Address - 1F2h[172h]; Offset 2)

This register contains the numbers of sectors of data requested to be transferred on a read or write operation between the

host and the CompactFlash Storage Card. If the value in this register is zero, a count of 256 sectors is specified. If the

command was successful, this register is zero at command completion. If not successfully completed, the register

contains the number of sectors that need to be transferred in order to complete the request.

5.5.5 Sector Number (LBA 7-0) Register (Address - 1F3h[173h]; Offset 3)

This register contains the starting sector number or bits 7-0 of the Logical Block Address (LBA) for any CompactFlash

Storage Card data access for the subsequent command.

5.5.6 Cylinder Low (LBA 15-8) Register (Address - 1F4h[174h]; Offset 4)

This register contains the low order 8 bits of the starting cylinder address or bits 15-8 of the Logical Block Address.

5.5.7 Cylinder High (LBA 23-16) Register (Address - 1F5h[175h]; Offset 5)

This register contains the high order bits of the starting cylinder address or bits 23-16 of the Logical Block Address.

5.5.8 Drive/Head (LBA 27-24) Register (Address 1F6h[176h]; Offset 6)

The Drive/Head register is used to select the drive and head. It is also used to select LBA addressing instead of

cylinder/head/sector addressing. The bits are defined as follows:

Figure: Drive/Head Register

Bit 7: this bit is specified as 1 for backward compatibility reasons. It is intended that this bit will become obsolete in a

future revision of the specification. This bit is ignored by some controllers in some commands.

Bit 6: LBA is a flag to select either Cylinder/Head/Sector (CHS) or Logical Block Address Mode (LBA). When LBA=0,

Cylinder/Head/Sector mode is selected. When LBA=1, Logical Block Address is selected. In Logical Block Mode,

the Logical Block Address is interpreted as follows:

LBA7-LBA0: Sector Number Register D7-D0.

LBA15-LBA8: Cylinder Low Register D7-D0.

LBA23-LBA16: Cylinder High Register D7-D0.

LBA27-LBA24: Drive/Head Register bits HS3-HS0.

Bit 5: this bit is specified as 1 for backward compatibility reasons. It is intended that this bit will become obsolete in a

future revisions of the specification. This bit is ignored by some controllers in some commands.

Bit 4 (DRV): DRV is the drive number. When DRV=0, drive (card) 0 is selected. When DRV=1, drive (card) 1 is selected.

Setting this bit to 1 is obsolete in PCMCIA modes of operation. If the obsolete functionality is support by a CF Storage

Card, the CompactFlash Storage Card is set to be Card 0 or 1 using the copy field (Drive #) of the PCMCIA Socket

& Copy configuration register.

Bit 3 (HS3): when operating in the Cylinder, Head, Sector mode, this is bit 3 of the head number.

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It is Bit 27 in the Logical Block Address mode.

Bit 2 (HS2): when operating in the Cylinder, Head, Sector mode, this is bit 2 of the head number.

It is Bit 26 in the Logical Block Address mode.

Bit 1 (HS1): when operating in the Cylinder, Head, Sector mode, this is bit 1 of the head number.

It is Bit 25 in the Logical Block Address mode.

Bit 0 (HS0): when operating in the Cylinder, Head, Sector mode, this is bit 0 of the head number.

It is Bit 24 in the Logical Block Address mode.

5.5.9 Status & Alternate Status Registers (Address 1F7h[177h]&3F6h[376h]; Offsets 7 & Eh)

These registers return the CompactFlash Storage Card status when read by the host. Reading the Status register does

clear a pending interrupt while reading the Auxiliary Status register does not. The status bits are described as follows:

Figure: Status & Alternate Status Register

Bit 7 (BUSY): the busy bit is set when the CompactFlash Storage Card has access to the command buffer and registers

and the host is locked out from accessing the command register and buffer. No other bits in this register are

valid when this bit is set to a 1.

During the data transfer of DMA commands, the Card shall not assert DMARQ unless either the BUSY bit,

the DRQ bit, or both are set to one.

Bit 6 (RDY): RDY indicates whether the device is capable of performing CompactFlash Storage Card operations. This bit

is cleared at power up and remains cleared until the CompactFlash Storage Card is ready to accept a

command.

Bit 5 (DWF): This bit, if set, indicates a write fault has occurred.

Bit 4 (DSC): This bit is set when the CompactFlash Storage Card is ready.

Bit 3 (DRQ): The Data Request is set when the CompactFlash Storage Card requires that information be transferred

either to or from the host through the Data register.

During the data transfer of DMA commands, the Card shall not assert DMARQ unless either the BUSY bit,

the DRQ bit, or both are set to one.

Bit 2 (CORR): This bit is set when a Correctable data error has been encountered and the data has been corrected. This

condition does not terminate a multi-sector read operation.

Bit 1 (IDX): This bit is always set to 0.

Bit 0 (ERR): This bit is set when the previous command has ended in some type of error. The bits in the Error register

contain additional information describing the error. It is recommended that media access commands (such

as Read Sectors and Write Sectors) that end with an error condition should have the address of the first

sector in error in the command block registers.

5.5.10 Device Control Register (Address - 3F6h[376h]; Offset Eh)

This register is used to control the CompactFlash Storage Card interrupt request and to issue an ATA soft reset to the

card. This register can be written even if the device is BUSY. The bits are defined as follows:

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Figure: Device Control Register

Bit 7: this bit is ignored by the CompactFlash Storage Card. The host software should set this bit to 0.

Bit 6: this bit is ignored by the CompactFlash Storage Card. The host software should set this bit to 0.

Bit 5: this bit is ignored by the CompactFlash Storage Card. The host software should set this bit to 0.

Bit 4: this bit is ignored by the CompactFlash Storage Card. The host software should set this bit to 0.

Bit 3: this bit is ignored by the CompactFlash Storage Card. The host software should set this bit to 0.

Bit 2 (SW Rst): this bit is set to 1 in order to force the CompactFlash Storage Card to perform an AT Disk controller Soft

Reset operation. This does not change the PCMCIA Card Configuration Registers (see Section 4.3 to 4.7)

as a hardware Reset does. The Card remains in Reset until this bit is reset to ‘0.’

Bit 1 (-IEn): the Interrupt Enable bit enables interrupts when the bit is 0. When the bit is 1, interrupts from the

CompactFlash Storage Card are disabled. This bit also controls the Int bit in the Configuration and Status

Bit 0: this bit is ignored by the CompactFlash Storage Card.

5.5.11 Card (Drive) Address Register (Address 3F7h[377h]; Offset Fh)

This register is provided for compatibility with the AT disk drive interface. It is recommended that this register not be

mapped into the host’s I/O space because of potential conflicts on Bit 7. The bits are defined as follows:

Bit 7: this bit is unknown.

Implementation Note:

Conflicts may occur on the host data bus when this bit is provided by a Floppy Disk Controller operating at the same

addresses as the CompactFlash Storage Card. Following are some possible solutions to this problem for the

PCMCIA implementation:

1) Locate the CompactFlash Storage Card at a non-conflicting address, i.e. Secondary address (377) or in an

independently decoded Address Space when a Floppy Disk Controller is located at the Primary addresses.

2) Do not install a Floppy and a CompactFlash Storage Card in the system at the same time.

3) Implement a socket adapter that can be programmed to (conditionally) tri-state D7 of I/0 address 3F7h/377h when

a CompactFlash Storage Card is installed and conversely to tristate D6-D0 of I/O address 3F7h/377h when a

floppy controller is installed.

4) Do not use the CompactFlash Storage Card’s Drive Address register. This may be accomplished by either a) If

possible, program the host adapter to enable only I/O addresses 1F0h-1F7h, 3F6h (or 170h-177h, 176h) to the

CompactFlash Storage Card or b) if provided use an additional Primary / Secondary configuration in the

CompactFlash Storage Card which does not respond to accesses to I/O locations 3F7h and 377h. With either of

these implementations, the host software shall not attempt to use information in the Drive Address Register.

Bit 6 (-WTG): this bit is 0 when a write operation is in progress; otherwise, it is 1.

Bit 5 (-HS3): this bit is the negation of bit 3 in the Drive/Head register.

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Bit 4 (-HS2): this bit is the negation of bit 2 in the Drive/Head register.

Bit 3 (-HS1): this bit is the negation of bit 1 in the Drive/Head register.

Bit 2 (-HS0): this bit is the negation of bit 0 in the Drive/Head register.

Bit 1 (-nDS1): this bit is 0 when drive 1 is active and selected.

Bit 0 (-nDS0): this bit is 0 when the drive 0 is active and selected.

5.6 CF-ATA Command Description

This section defines the software requirements and the format of the commands the host sends to the CompactFlash

Storage Cards. Commands are issued to the CompactFlash Storage Card by loading the required registers in the

command block with the supplied parameters, and then writing the command code to the Command Register. The

manner in which a command is accepted varies. There are three classes (see Table 38: CF-ATA Command Set) of

command acceptance, all dependent on the host not issuing commands unless the CompactFlash Storage Card is not

busy (BSY=0). All commands listed in this specification shall be implemented.

ꢀ

Upon receipt of a Class 1 command, the CompactFlash Storage Card sets BSY within 400 nsec.

Upon receipt of a Class 2 command, the CompactFlash Storage Card sets BSY within 400 nsec, sets up the sector

buffer for a write operation, sets DRQ within 700 µsec, and clears BSY within 400 nsec of setting DRQ.

ꢀ

Upon receipt of a Class 3 command, the CompactFlash Storage Card sets BSY within 400nsec, sets up the sector

buffer for a write operation, sets DRQ within 20 msec (assuming no re-assignments), and clears BSY within 400

nsec of setting DRQ.

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5.6.1 CF-ATA Command Set

CF-ATA Command Set summarizes the CF-ATA command set with the paragraphs that follow describing the

individual commands and the task file for each.

Command

Code

E5 or 98h

90h

–

LBA

–

Status

Support

Note

Check Power Mode

Execute Drive Diagnostic

Erase Sector

–

Support

C0h

–

Flush Cache

E7h

–

NOT Support #3

Support

Format Track

50h

–

Identify Device

Idle

ECh

–

Support

E3h or 97h

E1h or 95h

91h

–

Support

Idle Immediate

Initialize Drive Parameters

–

Support

–

Support

Key Management

Structure Read

B9 (Feature

0-127)

–

NOT Support #1

Key Management Read

Keying Material

B9 (Feature

80)

Key Management Change

Key Management Value

B9 (Feature

81)

13 NOP

00h

–

NOT Support

Support

14 Read Buffer

15 Read DMA

E4h

C8h

–

Support

16 Read Long Sector

17 Read Multiple

18 Read Sector(s)

19 Read Verify Sector(s)

20 Recalibrate

22h or 23h

C4h

NOT Support #3

Support

–

20h or 21h

40h or 41h

1Xh

Support

–

Support

21 Request Sense

03h

–

Support

Security Disable Password F6h

–

NOT Support #2

23 Security Erase Prepare

24 Security Erase Unit

25 Security Freeze Lock

26 Security Set Password

27 Security Unlock

F3h

F4h

F5h

F1h

F2h

–

NOT Support #2

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Command

Code

7Xh

–

LBA

–

Status

Support

Note

28 Seek

29 Set Feature

EFh

–

Support

Not Support

Support

30 Set Multiple Mode

31 Set Sleep Mode

32 Standby

C6h

–

E6h or 99h

E2 or 96h

E0 or 94h

87h

–

33 Standby Immediate

34 Translate Sector

35 Wear Level

–

F5h

36 Write Buffer

E8h

–

37 Write DMA

CAh

–

38 Write Long Sector

39 Write Multiple

40 Write Multiple w/o Erase

41 Write Sector(s)

42 Write Sector(s) w/o Erase

43 Write Verify

32h or 33h

C5h

CDh

30h or 31h

38h

3Ch

#1: This command is optional, depending on the key Management scheme in use.

#2: Use of this command is not recommended by CFA

#3: Use of this command is not recommended.

Definitions

FR = Features Register

SC =Sector Count register (00H to FFH, 00H means 256 sectors)

SN = Sector Number register

CY = Cylinder Low/High register

DH = Head No. (0 to 15) of Drive/Head register

LBA = Logic Block Address Mode Support

– = Not used for the command

Y = Used for the command

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5.6.2 Check Power Mode - 98h or E5h

If the CompactFlash Storage Card is in, going to, or recovering from the sleep mode, the CompactFlash Storage

Card sets BSY, sets the Sector Count Register to 00h, clears BSY and generates an interrupt.

If the CompactFlash Storage Card is in Idle mode, the CompactFlash Storage Card sets BSY, sets the Sector

Count Register to FFh, clears BSY and generates an interrupt.

Bit ->

Command (7)

C/D/H (6)

98h or E5h

Drive

Cyl High (5)

Cyl Low (4)

Sec Num (3)

Sec Cnt (2)

Feature (1)

5.6.3 Execute Drive Diagnostic - 90h

When the diagnostic command is issued in a PCMCIA configuration mode, this command runs only on the

CompactFlash Storage Card that is addressed by the Drive/Head register. This is because PCMCIA card interface

does not allows for direct inter-drive communication (such as the ATA PDIAG and DASP signals). When the

diagnostic command is issued in the True IDE Mode, the Drive bit is ignored and the diagnostic command is

executed by both the Master and the Slave with the Master responding with status for both devices.

Bit ->

Command (7)

C/D/H (6)

90h

Drive

Cyl High (5)

Cyl Low (4)

Sec Num (3)

Sec Cnt (2)

Feature (1)

Diagnostic Codes are returned in the Error Register at the end of the command.

Code

01h

02h

03h

04h

05h

8Xh

Error Type

No Error Detected

Formatter Device Error

Sector Buffer Error

ECC Circuitry Error

Controlling Microprocessor Error

Slave Error in True IDE Mode

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5.6.4 Erase Sector(s) - C0h

This command is used to pre-erase and condition data sectors in advance of a Write without Erase or Write Multiple

without Erase command. There is no data transfer associated with this command but a Write Fault error status can

occur.

Bit ->

Command (7)

C/D/H (6)

C0h

LBA

Drive

Head (LBA 27-24)

Cyl High (5)

Cyl Low (4)

Sec Num (3)

Sec Cnt (2)

Feature (1)

Cylinder High (LBA 23-16)

Cylinder Low (LBA 15-8)

Sector Number (LBA 7-0)

Sector Count

5.6.5 Format Track - 50h

This command writes the desired head and cylinder of the selected drive with a vendor unique data pattern (typically

FFh or 00h). To remain host backward compatible, the CompactFlash Storage Card expects a sector buffer of data

from the host to follow the command with the same protocol as the Write Sector(s) command although the

information in the buffer is not used by the CompactFlash Storage Card. If LBA=1 then the number of sectors to

format is taken from the Sec Cnt register (0=256). The use of this command is not recommended.

Bit ->

Command (7)

C/D/H (6)

50h

LBA

Drive

Head (LBA 27-24)

Cyl High (5)

Cyl Low (4)

Sec Num (3)

Sec Cnt (2)

Feature (1)

Cylinder High (LBA 23-16)

Cylinder Low (LBA 15-8)

X (LBA 7-0)

Count (LBA mode only)

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5.6.6 Identify Device – Ech

Bit ->

Command (7)

C/D/H (6)

ECh

Drive

Cyl High (5)

Cyl Low (4)

Sec Num (3)

Sec Cnt (2)

Feature (1)

The Identify Device command enables the host to receive parameter information from the CompactFlash

Storage Card. This command has the same protocol as the Read Sector(s) command. The parameter words

in the buffer have the arrangement and meanings defined in Table as below. All reserved bits or words are

zero. Hosts should not depend on Obsolete words in Identify Device containing 0. Table specifies each field in

the data returned by the Identify Device Command. In Table as below, X indicates a numeric nibble value

specific to the card and aaaa indicates an ASCII string specific to the particular drive.

Word

Address

Default

Value

Total

Bytes

Data Field Type Information

848Ah

0XXX

General configuration - signature for the CompactFlash 0 lash Storage Card

General configuration – Bit Significant with ATA-4 definitions.

XXXXh

0000h

00XXh

0000h

XXXXh

aaaa

Default number of cylinders

Reserved

Default number of heads

Obsolete

Default number of sectors per track

7-8

Number of sectors per card (Word 7 = MSW, Word 8 = LSW)

Obsolete

10-19

23-26

27-46

Serial number in ASCII (Right Justified)

0000h

0004h

aaaa

Obsolete

Number of ECC bytes passed on Read/Write Long Commands

Firmware revision in ASCII. Big Endian Byte Order in Word

aaaa

Model number in ASCII (Left Justified) Big Endian Byte Order in Word

XXXXh

0000h

XX00h

0000h

Maximum number of sectors on Read/Write Multiple command

Reserved

Capabilities

Reserved

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Word

Address

Default

Value

Total

Bytes

Data Field Type Information

PIO data transfer cycle timing mode

0X00h

0000h

000Xh

XXXXh

01XXh

XXXXh

0000h

0X0Xh

00XXh

Obsolete

Field Validity

Current numbers of cylinders

Current numbers of heads

Current sectors per track

57-58

Current capacity in sectors (LBAs)(Word 57 = LSW, Word 58 = MSW)

Multiple sector setting

60-61

Total number of sectors addressable in LBA Mode

Reserved

Multiword DMA transfer. In PC Card modes this value shall be 0h

Advanced PIO modes supported

Minimum Multiword DMA transfer cycle time per word. In PC Card modes this value

shall be 0h

XXXXh

Recommended Multiword DMA transfer cycle time. In PC Card modes this value

shall be 0h

XXXXh

0000h

XXXXh

0000h

XXXXh

0000h

XXXXh

0000h

XXXXh

0000h

Minimum PIO transfer cycle time without flow control

Minimum PIO transfer cycle time with IORDY flow control

Reserved

69-79

80-81

82-84

85-87

Reserved – CF cards do not return an ATA version

Features/command sets supported

Features/command sets enabled

Reserved

Time required for Security erase unit completion

Time required for Enhanced security erase unit completion

Current Advanced power management value

Reserved

92-127

128

Security status

129-159

160

Vendor unique bytes

Power requirement description

161

Reserved for assignment by the CFA

Key management schemes supported

CF Advanced True IDE Timing Mode Capability and Setting

CF Advanced PC Card I/O and Memory Timing Mode Capability

Reserved for assignment by the CFA

Reserved

162

163

164

165-167

168-255

158

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ꢁ

Word 0: General Configuration

This field indicates the general characteristics of the device. When Word 0 of the Identify drive information is

848Ah then the device is a CompactFlash Storage Card and complies with the CFA specification and CFA

command set. It is recommended that PCMCIA modes of operation report only the 848Ah value as they are

always intended as removable devices.

Bits 15-0: CF Standard Configuration Value

Word 0 is 848Ah. This is the recommended value of Word 0.

Some operating systems require Bit 6 of Word 0 to be set to 1 (Non-removable device) to use the card as the

root storage device. The Card must be the root storage device when a host completely replaces conventional

disk storage with a CompactFlash Card in True IDE mode. To support this requirement and provide capability

for any future removable media Cards, alternatehandling of Word 0 is permitted.

Bits 15-0: CF Preferred Alternate Configuration Values

044Ah: This is the alternate value of Word 0 turns on ATA device and turns off Removable Media and

Removable Device while preserving all Retired bits in the word.

0040h: This is the alternate value of Word 0 turns on ATA device and turns off Removable Media and

Removable Device while zeroing all Retired bits in the word

Bit 15-12: Configuration Flag

If bits 15:12 are set to 8h then Word 0 shall be 848Ah.

If bits 15:12 are set to 0h then Bits 11:0 are set using the definitions below and the Card is required to support

for the CFA command set and report that in bit 2 of Word 83.

Bit 15:12 values other than 8h and 0h are prohibited.

Bits 11-8: Retired

These bits have retired ATA bit definitions. It is recommended that the value of these bits be either the

preferred value of 0h or the value of 4h that preserves the corresponding bits from the 848Ah CF signature

value.

Bit 7: Removable Media Device

If Bit 7 is set to 1, the Card contains media that can be removed during Card operation.

If Bit 7 is set to 0, the Card contains nonremovable media.

Bit 6: Not Removable Controller and/or Device

Alert! This bit will be considered for obsolescence in a future revision of this standard.

If Bit 6 is set to 1, the Card is intended to be nonremovable during operation.

If Bit 6 is set to 0, the Card is intended to be removable during operation.

Bits 5-0: Retired/Reserved

Alert! Bit 2 will be considered for definition in a future revision of this standard and shall be 0 at this

time.

Bits 5-1 have retired ATA bit definitions.

Bit 2 shall be 0.

Bit 0 is Reserved and shall be 0.

It is recommended that the value of bits 5-0 be either the preferred value of 00h or the value of 0Ah that

preserves the corresponding bits from the 848Ah CF signature value.

ꢁ

Word 1: Default Number of Cylinders

This field contains the number of translated cylinders in the default translation mode. This value will be the

same as the number of cylinders.

ꢁ

Word 3: Default Number of Heads

This field contains the number of translated heads in the default translation mode.

Word 6: Default Number of Sectors per Track

This field contains the number of sectors per track in the default translation mode.

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ꢁ

Words 7-8: Number of Sectors per Card

This field contains the number of sectors per CompactFlash Storage Card. This double word

value is also the first invalid address in LBA translation mode.

Words 10-19: Serial Number

This field contains the serial number for this CompactFlash Storage Card and is right justified and padded

with spaces (20h).

Word 22: ECC Count

This field defines the number of ECC bytes used on each sector in the Read and Write Long commands. This

value shall be set to 0004h.

Words 23-26: Firmware Revision

ꢁ

This field contains the revision of the firmware for this product.

Words 27-46: Model Number

This field contains the model number for this product and is left justified and padded with spaces (20h).

Word 47: Read/Write Multiple Sector Count

Bits 15-8 shall be the recommended value of 80h or the permitted value of 00h. Bits 7-0 of this word define

the maximum number of sectors per block that the CompactFlash Storage Card supports for Read/Write

Multiple commands.

ꢁ

Word 49: Capabilities

Bit 13: Standby Timer

If bit 13 is set to 1 then the Standby timer is supported as defined by the IDLE command

If bit 13 is set to 0 then the Standby timer operation is defined by the vendor.

Bit 11: IORDY Supported

If bit 11 is set to 1 then this CompactFlash Storage Card supports IORDY operation.

If bit 11 is set to 0 then this CompactFlash Storage Card may support IORDY operation.

Bit 10: IORDY may be disabled

Bit 10 shall be set to 0, indicating that IORDY may not be disabled.

Bit 9: LBA supported

Bit 9 shall be set to 1, indicating that this CompactFlash Storage Card supports LBA mode addressing. CF

devices shall support LBA addressing.

Bit 8: DMA Supported If bit 8 is set to 1 then Read DMA and Write DMA commands are supported. Bit 8 shall

be set to 0. Read/Write DMA commands are not currently permitted on CF cards.

PIO Data Transfer Cycle Timing Mode

The PIO transfer timing for each CompactFlash Storage Card falls into modes that have unique parametric

timing specifications. The value returned in Bits 15-8 shall be 00h for mode 0, 01h for mode 1, or 02h for

mode 2. Values 03h through FFh are reserved.

ꢁ

Translation Parameters Valid

Bit 0 shall be set to 1 indicating that words 54 to 58 are valid and reflect the current number of cylinders,

heads and sectors. If bit 1 of word 53 is set to 1, the values in words 64 through 70 are valid. If this bit is

cleared to 0, the values reported in words 64-70 are not valid. Any CompactFlash Storage Card that supports

PIO mode 3 or above shall set bit 1 of word 53 to one and support the fields contained in words 64 through

70.

ꢁ

Current Number of Cylinders, Heads, Sectors/Track

These fields contains the current number of user addressable Cylinders, Heads, and Sectors/Track in the

current translation mode.

Current Capacity

This field contains the product of the current cylinders times heads times sectors.

Multiple Sector Setting

Bits 15-9 are reserved and shall be set to 0.

ꢁ

Bit 8 shall be set to 1 indicating that the Multiple Sector Setting is valid.

Bits 7-0 are the current setting for the number of sectors that shall be transferred per interrupt on Read/Write

Multiple commands.

ꢁ

Total Sectors Addressable in LBA Mode

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This field contains the total number of user addressable sectors for the CompactFlash Storage Card in LBA

mode only.

Multiword DMA transfer

ꢁ

Bits 15 through 8 of word 63 of the Identify Device parameter information is defined as the Multiword DMA

mode selected field. If this field is supported, bit 1 of word 53 shall be set to one. This field is bit significant.

Only one of bits may be set to one in this field by the CompactFlash Storage Card to indicate the multiword

DMA mode which is currently selected. Of these bits, bits 15 through 11 are reserved. Bit 8, if set to one,

indicates that Multiword DMA mode 0 has been selected. Bit 9, if set to one, indicates that Multiword DMA

mode 1 has been selected. Bit 10, if set to one, indicates that Multiword DMA mode 2 has been selected.

Selection of Multiword DMA modes 3 and above are specific to CompactFlash are reported in word 163,

Word 163: CF Advanced True IDE Timing Mode Capabilities and Settings.

Bits 7 through 0 of word 63 of the Identify Device parameter information is defined as the Multiword DMA data

transfer supported field. If this field is supported, bit 1 of word 53 shall be set to one. This field is bit significant.

Any number of bits may be set to one in this field by the CompactFlash Storage Card to indicate the Multiword

DMA modes it is capable of supporting.

Of these bits, bits 7 through 2 are reserved. Bit 0, if set to one, indicates that the CompactFlash Storage Card

supports Multiword DMA mode 0. Bit 1, if set to one, indicates that the CompactFlash Storage Card supports

Multiword DMA modes 1 and 0. Bit 2, if set to one, indicates that the CompactFlash Storage Card supports

Multiword DMA modes 2, 1 and 0. Support for Multiword DMA modes 3 and above are specific to

CompactFlash are reported in word 163, Word 163: CF Advanced True IDE Timing Mode Capabilities and

Settings.

ꢁ

Word 64: Advanced PIO transfer modes supported

Bits 7 through 0 of word 64 of the Identify Device parameter information is defined as the advanced PIO data

transfer supported field. If this field is supported, bit 1 of word 53 shall be set to one. This field is bit significant.

Any number of bits may be set to one in this field by the CompactFlash Storage Card to indicate the

advanced PIO modes it is capable of supporting.

Of these bits, bits 7 through 2 are reserved. Bit 0, if set to one, indicates that the CompactFlash Storage Card

supports PIO mode 3. Bit 1, if set to one, indicates that the CompactFlash StorageCard supports PIO mode

Support for PIO modes 5 and above are specific to CompactFlash are reported in word 163.

Word 65: Minimum Multiword DMA transfer cycle time

Word 65 of the parameter information of the Identify Device command is defined as the minimum Multiword

DMA transfer cycle time. This field defines, in nanoseconds, the minimum cycle time that, if used by the host,

the CompactFlash Storage Card guarantees data integrity during the transfer.

If this field is supported, bit 1 of word 53 shall be set to one. The value in word 65 shall not be less than the

minimum cycle time for the fastest DMA mode supported by the device. This field shall be supported by all

CompactFlash Storage Cards supporting DMA modes 1 and above. If bit 1 of word 53 is set to one, but this

field is not supported, the Card shall return a value of zero in this field.

ꢁ

Recommended Multiword DMA transfer cycle time

Word 66 of the parameter information of the Identify Device command is defined as the recommended

Multiword DMA transfer cycle time. This field defines, in nanoseconds, the cycle time that, if used by the host,

may optimize the data transfer from by reducing the probability that the CompactFlash Storage Card will

need to negate the DMARQ signal during the transfer of a sector.

If this field is supported, bit 1 of word 53 shall be set to one. The value in word 66 shall not be less than the

value in word 65. This field shall be supported by all CompactFlash Storage Cards supporting DMA modes 1

and above. If bit 1 of word 53 is set to one, but this field is not supported, the Card shall return a value of zero

in this field.

ꢁ

Word 67: Minimum PIO transfer cycle time without flow control

Word 67 of the parameter information of the Identify Device command is defined as the minimum PIO

transfer without flow control cycle time. This field defines, in nanoseconds, the minimum cycle time that, if

used by the host, the CompactFlash Storage Card guarantees data integrity during the transfer without

utilization of flow control. If this field is supported, Bit 1 of word 53 shall be set to one. Any CompactFlash

Storage Card that supports PIO mode 3 or above shall support this field, and the value in word 67 shall not

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be less than the value reported in word 68. If bit 1 of word 53 is set to one because a CompactFlash Storage

Card supports a field in words 64-70 other than this field and the CompactFlash Storage Card does not

support this field, the CompactFlash Storage Card shall return a value of zero in this field.

ꢁ

Word 68: Minimum PIO transfer cycle time with IORDY

Word 68 of the parameter information of the Identify Device command is defined as the minimum PIO

transfer with IORDY flow control cycle time. This field defines, in nanoseconds, the minimum cycle time that

the CompactFlash Storage Card supports while performing data transfers while utilizing IORDY flow control.

If this field is supported, Bit 1 of word 53 shall be set to one. Any CompactFlash Storage Card that supports

PIO mode 3 or above shall support this field, and the value in word 68 shall be the fastest defined PIO mode

supported by the CompactFlash Storage Card. If bit 1 of word 53 is set to one because a CompactFlash

Storage Card supports a field in words 64-70 other than this field and the CompactFlash Storage Card does

not support this field, the CompactFlash Storage Card shall return a value of zero in this field.

Words 82-84: Features/command sets supported

ꢁ

Words 82, 83, and 84 shall indicate features/command sets supported. The value 0000h or FFFFh was

placed in each of these words by CompactFlash Storage Cards prior to ATA-3 and shall be interpreted by the

host as meaning that features/command sets supported are not indicated. Bits 1 through 13 of word 83 and

bits 0 through 13 of word 84 are reserved. Bit 14 of word 83 and word 84 shall be set to one and bit 15 of word

83 and word 84 shall be cleared to zero to provide indication that the features/command sets supported

words are valid. The values in these words should not be depended on by host implementers.

Bit 0 of word 82 shall be set to zero; the SMART feature set is not supported.

If bit 1 of word 82 is set to one, the Security Mode feature set is supported.

Bit 2 of word 82 shall be set to zero; the Removable Media feature set is not supported.

Bit 3 of word 82 shall be set to one; the Power Management feature set is supported.

Bit 4 of word 82 shall be set to zero; the Packet Command feature set is not supported.

If bit 5 of word 82 is set to one, write cache is supported.

If bit 6 of word 82 is set to one, look-ahead is supported.

Bit 7 of word 82 shall be set to zero; release interrupt is not supported.

Bit 8 of word 82 shall be set to zero; Service interrupt is not supported.

Bit 9 of word 82 shall be set to zero; the Device Reset command is not supported.

Bit 10 of word 82 shall be set to zero; the Host Protected Area feature set is not supported.

Bit 11 of word 82 is obsolete.

Bit 12 of word 82 shall be set to one; the CompactFlash Storage Card supports the Write Buffer command.

Bit 13 of word 82 shall be set to one; the CompactFlash Storage Card supports the Read Buffer command.

Bit 14 of word 82 shall be set to one; the CompactFlash Storage Card supports the NOP command.

Bit 15 of word 82 is obsolete.

Bit 0 of word 83 shall be set to zero; the CompactFlash Storage Card does not support the Download

Microcode command.

Bit 1 of word 83 shall be set to zero; the CompactFlash Storage Card does not support the Read DMA

Queued and Write DMA Queued commands.

Bit 2 of word 83 shall be set to one; the CompactFlash Storage Card supports the CFA feature set.

If bit 3 of word 83 is set to one, the CompactFlash Storage Card supports the Advanced Power Management

feature set.

Bit 4 of word 83 shall be set to zero; the CompactFlash Storage Card does not support the Removable Media

Status feature set.

Words 85-87: Features/command sets enabled

ꢁ

Words 85, 86, and 87 shall indicate features/command sets enabled. The value 0000h or FFFFh was placed

in each of these words by CompactFlash Storage Cards prior to ATA-4 and shall be interpreted by the host

as meaning that features/command sets enabled are not indicated. Bits 1 through 15 of word 86 are reserved.

Bits 0-13 of word 87 are reserved. Bit 14 of word 87 shall be set to one and bit 15 of word 87 shall be cleared

to zero to provide indication that the features/command sets enabled words are valid. The values in these

words should not be depended on by host implementers.

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Bit 0 of word 85 shall be set to zero; the SMART feature set is not enabled.

If bit 1 of word 85 is set to one, the Security Mode feature set has been enabled via the Security Set

Password command.

Bit 2 of word 85 shall be set to zero; the Removable Media feature set is not supported.

Bit 3 of word 85 shall be set to one; the Power Management feature set is supported.

Bit 4 of word 85 shall be set to zero; the Packet Command feature set is not enabled.

If bit 5 of word 85 is set to one, write cache is enabled.

If bit 6 of word 85 is set to one, look-ahead is enabled.

Bit 7 of word 85 shall be set to zero; release interrupt is not enabled.

Bit 8 of word 85 shall be set to zero; Service interrupt is not enabled.

Bit 9 of word 85 shall be set to zero; the Device Reset command is not supported.

Bit 10 of word 85 shall be set to zero; the Host Protected Area feature set is not supported.

Bit 11 of word 85 is obsolete.

Bit 12 of word 85 shall be set to one; the CompactFlash Storage Card supports the Write Buffer command.

Bit 13 of word 85 shall be set to one; the CompactFlash Storage Card supports the Read Buffer command.

Bit 14 of word 85 shall be set to one; the CompactFlash Storage Card supports the NOP command.

Bit 15 of word 85 is obsolete.

Bit 0 of word 86 shall be set to zero; the CompactFlash Storage Card does not support the Download

Microcode command.

Bit 1 of word 86 shall be set to zero; the CompactFlash Storage Card does not support the Read DMA

Queued and Write DMA Queued commands.

If bit 2 of word 86 shall be set to one, the CompactFlash Storage Card supports the CFA feature set.

If bit 3 of word 86 is set to one, the Advanced Power Management feature set has been enabled via the Set

Features command.

Bit 4 of word 86 shall be set to zero; the CompactFlash Storage Card does not support the Removable Media

Status feature set.

Word 89: Time required for Security erase unit completion

Word 89 specifies the time required for the Security Erase Unit command to complete. This command shall

be supported on CompactFlash Storage Cards that support security.

ꢁ

Value

Time

Value not specified

(Value * 2) minutes

>508 minutes

1-254

255

Word 90: Time required for Enhanced security erase unit completion

Word 90 specifies the time required for the Enhanced Security Erase Unit command to complete.

This command shall be supported on CompactFlash Storage Cards that support security.

Value

Time

Value not specified

(Value * 2) minutes

>508 minutes

1-254

255

ꢁ

Word 91: Advanced power management level value

Bits 7-0 of word 91 contain the current Advanced Power Management level setting.

Word 128: Security Status

Bit 8: Security Level

If set to 1, indicates that security mode is enabled and the security level is maximum.

If set to 0 and security mode is enabled, indicates that the security level is high.

Bit 5: Enhanced security erase unit feature supported

If set to 1, indicates that the Enhanced security erase unit feature set is supported.

Bit 4: Expire

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If set to 1, indicates that the security count has expired and Security Unlock and Security Erase Unit are

command aborted until a power-on reset or hard reset.

Bit 3: Freeze

If set to 1, indicates that the security is Frozen.

Bit 2: Lock

If set to 1, indicates that the security is locked.

Bit 1: Enable/Disable

If set to 1, indicates that the security is enabled.

If set to 0, indicates that the security is disabled.

Bit 0: Capability

If set to 1, indicates that CompactFlash Storage Card supports security mode feature set.

If set to 0, indicates that CompactFlash Storage Card does not support security mode feature set.

ꢁ

Word 160: Power Requirement Description

This word is required for CompactFlash Storage Cards that support power mode 1.

Bit 15: VLD

If set to 1, indicates that this word contains a valid power requirement description.

If set to 0, indicates that this word does not contain a power requirement description.

Bit 14: RSV

This bit is reserved and shall be 0.

Bit 13: -XP

If set to 1, indicates that the CompactFlash Storage Card does not have Power Level 1 commands.

If set to 0, indicates that the CompactFlash Storage Card has Power Level 1 commands

Bit 12: -XE

If set to 1, indicates that Power Level 1 commands are disabled.

If set to 0, indicates that Power Level 1 commands are enabled.

Bit 0-11: Maximum current

This field contains the CompactFlash Storage Card’s maximum current in mA.

ꢁ

Word 162: Key Management Schemes Supported

Bit 0: CPRM support

If set to 1, the device supports CPRM Scheme (Content Protection for Recordable Media)

If set to 0, the device does not support CPRM.

Bits 1-15 are reserved for future additional Key Management schemes.

Word 163: CF Advanced True IDE Timing Mode Capabilities and Settings

This word describes the capabilities and current settings for CFA defined advanced timing modes using the

True IDE interface.

Notice! The use of True IDE PIO Modes 5 and above or of Multiword DMA Modes 3 and above impose

significant restrictions on the implementation of the host:

Additional Requirements for CF Advanced Timing Modes.

There are four separate fields defined that describe support and selection of Advanced PIO timing modes

and Advanced Multiword DMA timing modes. The older modes are reported in words 63 and 64.

Word 63: Multiword DMA transfer and 6.2.1.6.19: Word 64: Advanced PIO transfer modes supported.

Bits 2-0: Advanced True IDE PIO Mode Support Indicates the maximum True IDE PIO mode supported by

the card.

Value

Maximum PIO mode timing selected

Specified in word 64

PIO Mode 5

PIO Mode 6

3-7

Reserved

Bits 5-3: Advanced True IDE Multiword DMA Mode Support Indicates the maximum True IDE Multiword DMA

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mode supported by the card.

Value

Maximum Multiword DMA timing mode supported

Specified in word 63

Multiword DMA Mode 3

Multiword DMA Mode 4

3-7

Reserved

Bits 8-6: Advanced True IDE PIO Mode Selected Indicates the current True IDE PIO mode selected on the

card.

Value

Current PIO timing mode selected

Specified in word 64

PIO Mode 5

PIO Mode 6

3-7

Reserved

Bits 11-9: Advanced True IDE Multiword DMA Mode Selected Indicates the current True IDE Multiword DMA

Mode Selected on the card.

Value

Current Multiword DMA timing mode selected

Specified in word 63

Multiword DMA Mode 3

Multiword DMA Mode 4

Reserved

3-7

Bits 15-12 are reserved.

ꢁ

Word 164: CF Advanced PCMCIA I/O and Memory Timing Modes Capabilities and Settings

This word describes the capabilities and current settings for CFA defined advanced timing modes using the

Memory and PCMCIA I/O interface.

Notice! The use of PCMCIA I/O or Memory modes that are 100ns or faster impose significant restrictions

on the implementation of the host:

Additional Requirements for CF Advanced Timing Modes.

Bits 2-0: Maximum Advanced PCMCIA I/O Mode Support Indicates the maximum I/O timing mode supported

by the card.

Value

Maximum PCMCIA IO timing mode Supported

255ns Cycle PCMCIA I/O Mode

120ns Cycle PCMCIA I/O Mode

100ns Cycle PCMCIA I/O Mode

80ns Cycle PCMCIA I/O Mode

Reserved

4-7

Bits 5-3: Maximum Memory timing mode supported

Indicates the Maximum Memory timing mode supported by the card.

Value

Maximum Memory timing mode Supported

250ns Cycle Memory Mode

120ns Cycle Memory Mode

100ns Cycle Memory Mode

80ns Cycle Memory Mode

Reserved

4-7

Bits 15-6 are reserved.

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5.6.7 Idle - 97h or E3h

This command causes the CompactFlash Storage Card to set BSY, enter the Idle mode, clear BSY and generate

an interrupt. If the sector count is non-zero, it is interpreted as a timer count with each count being 5 milliseconds

and the automatic power down mode is enabled. If the sector count is zero, the automatic power down mode is

disabled. Note that this time base (5 msec) is different from the ATA specification.

Bit ->

Command (7)

C/D/H (6)

97h or E3h

Drive

Cyl High (5)

Cyl Low (4)

Sec Num (3)

Sec Cnt (2)

Feature (1)

Timer Count (5 msec increments)

5.6.8 Idle Immediate - 95h or E1h

This command causes the CompactFlash Storage Card to set BSY, enter the Idle mode, clear BSY and generate

an interrupt.

Bit ->

Command (7)

C/D/H (6)

95h or E1h

Drive

Cyl High (5)

Cyl Low (4)

Sec Num (3)

Sec Cnt (2)

Feature (1)

5.6.9 Initialize Drive Parameters - 91h

This command enables the host to set the number of sectors per track and the number of heads per cylinder.

Only the Sector Count and the Card/Drive/Head registers are used by this command.

Bit ->

Command (7)

C/D/H (6)

91h

Drive

Max Head (no. of heads-1)

Cyl High (5)

Cyl Low (4)

Sec Num (3)

Sec Cnt (2)

Feature (1)

Number of Sectors

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5.6.10 Read Buffer - E4h

The Read Buffer command enables the host to read the current contents of the CompactFlash Storage Card’s

sector buffer. This command has the same protocol as the Read Sector(s) command.

Bit ->

Command (7)

C/D/H (6)

E4h

Drive

Cyl High (5)

Cyl Low (4)

Sec Num (3)

Sec Cnt (2)

Feature (1)

5.6.11 Read DMA – C8h

This command uses DMA mode to read from 1 to 256 sectors as specified in the Sector Count register. A sector

count of 0 requests 256 sectors. The transfer begins at the sector specified in the Sector Number Register. When this

command is issued the CompactFlash Storage Card sets BSY, puts all or part of the sector of data in the buffer. The Card

is then permitted, although not required, to set DRQ, clear BSY. The Card asserts DMAREQ while data is available to be

transferred. The Card asserts DMAREQ while data is available to be transferred. The host then reads the (512 *

sector-count) bytes of data from the Card using DMA. While DMAREQ is asserted by the Card, the Host asserts -DMACK

while it is ready to transfer data by DMA and asserts -IORD once for each 16 bit word to be transferred to the Host.

Interrupts are not generated on every sector, but upon completion of the transfer of the entire number of sectors to be

transferred or upon the occurrence of an unrecoverable error.

At command completion, the Command Block Registers contain the cylinder, head and sector number of the last

sector read. If an error occurs, the read terminates at the sector where the error occurred. The Command Block Registers

contain the cylinder, head, and sector number of the sector where the error occurred. The amount of data transferred is

indeterminate.

When a Read DMA command is received by the Card and 8 bit transfer mode has been enabled by the Set Features

command, the Card shall return the Aborted error.

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5.6.12 Read Multiple - C4h

Note: This specification requires that CompactFlash Cards support a multiple block count of 1 and permits larger values to be

supported.

The Read Multiple command performs similarly to the Read Sectors command. Interrupts are not generated on every

sector, but on the transfer of a block, which contains the number of sectors defined by a Set Multiple command.

Command execution is identical to the Read Sectors operation except that the number of sectors defined by a Set

Multiple command is transferred without intervening interrupts. DRQ qualification of the transfer is required only at the

start of the data block, not on each sector.

The block count of sectors to be transferred without intervening interrupts is programmed by the Set Multiple Mode

command, which shall be executed prior to the Read Multiple command. When the Read Multiple command is issued, the

Sector Count Register contains the number of sectors (not the number of blocks or the block count) requested. If the

number of requested sectors is not evenly divisible by the block count, as many full blocks as possible are transferred,

followed by a final, partial block transfer. The partial block transfer is for n sectors, where

n = (sector count) modulo (block count).

If the Read Multiple command is attempted before the Set Multiple Mode command has been executed or when Read

Multiple commands are disabled, the Read Multiple operation is rejected with an Aborted Command error. Disk errors

encountered during Read Multiple commands are posted at the beginning of the block or partial block transfer, but DRQ

is still set and the data transfer shall take place as it normally would, including transfer of corrupted data, if any.

Interrupts are generated when DRQ is set at the beginning of each block or partial block. The error reporting is the same

as that on a Read Sector(s) Command. This command reads from 1 to 256 sectors as specified in the Sector Count

At command completion, the Command Block Registers contain the cylinder, head and sector number of the last sector

read.

If an error occurs, the read terminates at the sector where the error occurred. The Command Block Registers contain the

cylinder, head and sector number of the sector where the error occurred. The flawed data is pending in the sector buffer.

Subsequent blocks or partial blocks are transferred only if the error was a correctable data error. All other errors cause the

command to stop after transfer of the block that contained the error.

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5.6.13 Read Sector(s) - 20h or 21h

This command reads from 1 to 256 sectors as specified in the Sector Count register. A sector count of 0 requests 256

sectors. The transfer begins at the sector specified in the Sector Number Register. When this command is issued and

after each sector of data (except the last one) has been read by the host, the CompactFlash Storage Card sets BSY, puts

the sector of data in the buffer, sets DRQ, clears BSY, and generates an interrupt. The host then reads the 512 bytes of

data from the buffer.

At command completion, the Command Block Registers contain the cylinder, head and sector number of the last sector

read. If an error occurs, the read terminates at the sector where the error occurred. The Command Block Registers

contain the cylinder, head, and sector number of the sector where the error occurred. The flawed data is pending in the

sector buffer.

5.6.14 Read Verify Sector(s) - 40h or 41h

This command is identical to the Read Sectors command, except that DRQ is never set and no data is transferred to the

host. When the command is accepted, the CompactFlash Storage Card sets BSY.

When the requested sectors have been verified, the CompactFlash Storage Card clears BSY and generates an interrupt.

Upon command completion, the Command Block Registers contain the cylinder, head, and sector number of the last

sector verified.

If an error occurs, the Read Verify Command terminates at the sector where the error occurs. The Command Block

Registers contain the cylinder, head and sector number of the sector where the error occurred. The Sector Count

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TS32M~1GCF80

80X CompactFlash Card

5.6.15 Recalibrate - 1Xh

This command is effectively a NOP command to the CompactFlash Storage Card and is provided for compatibility

purposes.

5.6.16 Request Sense - 03h

This command requests extended error information for the previous command. Table defines the valid extended error

codes for the CompactFlash Storage Card Series product. The extended error code is returned to the host in the Error

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TS32M~1GCF80

80X CompactFlash Card

Table: Extended Error Codes

5.6.17 Seek - 7Xh

This command is effectively a NOP command to the CompactFlash Storage Card although it does perform a range check

of cylinder and head or LBA address and returns an error if the address is out of range.

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TS32M~1GCF80

80X CompactFlash Card

5.6.18 Set Features – EFh

This command is used by the host to establish or select certain features. If any subcommand input value is not supported

or is invalid, the Compact Flash Storage Card shall return command aborted. Table: Feature Supported defines all

features that are supported.

Table: Feature Supported

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TS32M~1GCF80

80X CompactFlash Card

Features 01h and 81h are used to enable and clear 8 bit data transfer modes in True IDE Mode. If the 01h feature

command is issued all data transfers shall occur on the low order D[7:0] data bus and the -IOIS16 signal shall not be

asserted for data register accesses. The host shall not enable this feature for DMA transfers.

Features 02h and 82h allow the host to enable or disable write cache in CompactFlash Storage Cards that implement

write cache. When the subcommand disable write cache is issued, the CompactFlash Storage Card shall initiate the

sequence to flush cache to non-volatile memory before command completion.

Feature 03h allows the host to select the PIO or Multiword DMA transfer mode by specifying a value in the Sector

Count register. The upper 5 bits define the type of transfer and the low order 3 bits encode the mode value. One PIO

mode shall be selected at all times. For Cards which support DMA, one Multiword DMA mode shall be selected at all

times. The host may change the selected modes by the Set Features command.

Mode

PIO default mode

PIO default mode, disable IORDY

PIO flow control transfer mode

Reserved

Multiword DMA mode

Reserved

Bits(7:3)

00000b

00001b

00010b

00100b

01000b

Bits(2:0)

000b

001b

Mode

N/A

Mode

N/A

10000b

Mode = transfer mode number

A CompactFlash Storage Card reporting support for Multiword DMA modes shall support all Multiword DMA modes below

the highest mode supported. For example, if Multiword DMA mode 2 support is reported, then modes 1 and 0 shall also

be supported.

5.6.19 Set Multiple Mode - C6h

This command enables the CompactFlash Storage Card to perform Read and Write Multiple operations and establishes

the block count for these commands. The Sector Count Register is loaded with the number of sectors per block. Upon

receipt of the command, the CompactFlash Storage Card sets BSY to 1 and checks the Sector Count Register.

If the Sector Count Register contains a valid value and the block count is supported, the value is loaded and execution is

enabled for all subsequent Read Multiple and Write Multiple commands. If the block count is not supported, an Aborted

Command error is posted and the Read Multiple and Write Multiple commands are disabled. If the Sector Count Register

contains 0 when the command is issued, Read and Write Multiple commands are disabled. At power on, or after a

hardware or (unless disabled by a Set Feature command) software reset, the default mode is Read and Write Multiple

disabled.

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TS32M~1GCF80

80X CompactFlash Card

5.6.20 Set Sleep Mode- 99h or E6h

This command causes the CompactFlash Storage Card to set BSY, enter the Sleep mode, clear BSY and generate an

interrupt. Recovery from sleep mode is accomplished by simply issuing another command (a reset is permitted but not

required). Sleep mode is also entered when internal timers expire so the host does not need to issue this command

except when it wishes to enter Sleep mode immediately. The default value for the timer is 5 milliseconds. Note that this

time base (5 msec) is different from the ATA Specification.

5.6.21 Standby - 96h or E2h

This command causes the CompactFlash Storage Card to set BSY, enter the Sleep mode (which corresponds to the ATA

“Standby” Mode), clear BSY and return the interrupt immediately. Recovery from sleep mode is accomplished by simply

issuing another command (a reset is not required).

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TS32M~1GCF80

80X CompactFlash Card

5.6.22 Standby Immediate - 94h or E0h

This command causes the CompactFlash Storage Card to set BSY, enter the Sleep mode (which corresponds to the ATA

“Standby” Mode), clear BSY and return the interrupt immediately. Recovery from sleep mode is accomplished by simply

issuing another command (a reset is not required).

5.6.23 Translate Sector - 87h

This command allows the host a method of determining the exact number of times a user sector has been erased and

programmed. The controller responds with a 512 byte buffer of information containing the desired cylinder, head and

sector, including its Logical Address, and the Hot Count, if available, for that sector. Table represents the information in

the buffer. Please note that this command is unique to the CompactFlash Storage Card.

Table:Translate Sector Information

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TS32M~1GCF80

80X CompactFlash Card

5.6.24 Wear Level - F5h

For the CompactFlash Storage Cards that do not support security mode feature set, this command is effectively a NOP

command and only implemented for backward compatibility. The Sector Count Register shall always be returned with a

00h indicating Wear Level is not needed. If the CompactFlash Storage Card supports security mode feature set, this

command shall be handled as Security Freeze Lock.

5.6.25 Write Buffer - E8h

The Write Buffer command enables the host to overwrite contents of the CompactFlash Storage Card’s sector buffer with

any data pattern desired. This command has the same protocol as the Write Sector(s) command and transfers 512 bytes.

5.6.26 Write DMA – CAh

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TS32M~1GCF80

80X CompactFlash Card

This command uses DMA mode to write from 1 to 256 sectors as specified in the Sector Count register. A sector count of

0 requests 256 sectors. The transfer begins at the sector specified in the Sector Number Register. When this command

is issued the CompactFlash Storage Card sets BSY, puts all or part of the sector of data in the buffer. The Card is then

permitted, although not required, to set DRQ, clear BSY. The Card asserts DMAREQ while data is available to be

transferred. The host then writes the (512 * sector-count) bytes of data to the Card using DMA. While DMAREQ is

asserted by the Card, the Host asserts -DMACK while it is ready to transfer data by DMA and asserts -IOWR once for

each 16 bit word to be transferred from the Host.

Interrupts are not generated on every sector, but upon completion of the transfer of the entire number of sectors to be

transferred or upon the occurrence of an unrecoverable error.

At command completion, the Command Block Registers contain the cylinder, head and sector number of the last sector

read. If an error occurs, the read terminates at the sector where the error occurred. The Command Block Registers

contain the cylinder, head, and sector number of the sector where the error occurred. The amount of data transferred is

indeterminate.

When a Write DMA command is received by the Card and 8 bit transfer mode has been enabled by the Set Features

command, the Card shall return the Aborted error.

5.6.27 Write Multiple Command - C5h

Note: This specification requires that CompactFlash Cards support a multiple block count of 1 and permits larger values

to be supported.

This command is similar to the Write Sectors command. The CompactFlash Storage Card sets BSY within 400 nsec of

accepting the command. Interrupts are not presented on each sector but on the transfer of a block that contains the

number of sectors defined by Set Multiple. Command execution is identical to the Write Sectors operation except that the

number of sectors defined by the Set Multiple command is transferred without intervening interrupts.

DRQ qualification of the transfer is required only at the start of the data block, not on each sector.The block count of

sectors to be transferred without intervening interrupts is programmed by the Set Multiple Mode command, which shall be

executed prior to the Write Multiple command.

When the Write Multiple command is issued, the Sector Count Register contains the number of sectors (not the number

of blocks or the block count) requested. If the number of requested sectors is not evenly divisible by the block count, as

many full blocks as possible are transferred, followed by a final, partial block transfer. The partial block transfer is for n

sectors, where:

n = (sector count) modulo (block count).

If the Write Multiple command is attempted before the Set Multiple Mode command has been executed or when Write

Multiple commands are disabled, the Write Multiple operation shall be rejected with an aborted command error.

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TS32M~1GCF80

80X CompactFlash Card

Errors encountered during Write Multiple commands are posted after the attempted writes of theblock or partial block

transferred. The Write command ends with the sector in error, even if it is in the middle of a block. Subsequent blocks are

not transferred in the event of an error. Interrupts are generated when DRQ is set at the beginning of each block or partial

block.

The Command Block Registers contain the cylinder, head and sector numbers of the sector where the error occurred. The

Sector Count Register contains the residual number of sectors that need to be transferred for successful completion of

the command, e.g., each block has 4 sectors, a request for 8 sectors is issued and an error occurs on the third sector. The

Sector Count Register contains 6 and the address is that of the third sector.

5.6.28 Write Multiple without Erase – CDh

This command is similar to the Write Multiple command with the exception that an implied erase before write operation is

not performed. The sectors should be pre-erased with the Erase Sector(s) command before this command is issued.

5.6.29 Write Sector(s) - 30h or 31h

This command writes from 1 to 256 sectors as specified in the Sector Count Register. A sector count of zero requests 256

sectors. The transfer begins at the sector specified in the Sector Number Register. When this command is accepted, the

CompactFlash Storage Card sets BSY, then sets DRQ and clears BSY, then waits for the host to fill the sector buffer with

the data to be written. No interrupt is generated to start the first host transfer operation. No data should be transferred by

the host until BSY has been cleared by the host.

For multiple sectors, after the first sector of data is in the buffer, BSY shall be set and DRQ shall be cleared. After the next

buffer is ready for data, BSY is cleared, DRQ is set and an interrupt is generated. When the final sector of data is

transferred, BSY is set and DRQ is cleared. It shall remain in this state until the command is completed at which time BSY

is cleared and an interrupt is generated.

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TS32M~1GCF80

80X CompactFlash Card

If an error occurs during a write of more than one sector, writing terminates at the sector where the error occurs. The

Command Block Registers contain the cylinder, head and sector number of the sector where the error occurred. The host

may then read the command block to determine what error has occurred, and on which sector.

5.6.30 Write Sector(s) without Erase - 38h

This command is similar to the Write Sector(s) command with the exception that an implied erase before write operation

is not performed. This command has the same protocol as the Write Sector(s) command. The sectors should be

pre-erased with the Erase Sector(s) command before this command is issued. If the sector is not pre-erased with the

Erase Sector(s) command, a normal write sector operation will occur.

5.6.31 Write Verify - 3Ch

This command is similar to the Write Sector(s) command, except each sector is verified immediately after being written.

This command has the same protocol as the Write Sector(s) command.

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TS32M~1GCF80

80X CompactFlash Card

ꢀ

Error Posting

Command

Error Register

Status Register

DSC CORR ERR

BBK

UNC IDNF ABRT AMNF DRDY DWF

Check Power Mode

Execute Drive Diagnostic¹

Erase Sector(s)

Format Track

Identify Device

Idle

Idle Immediate

Initialize Drive

Parameters

Read Buffer

Read DMA

Read Multiple

Read Sector(s)

Read Verify Sectors

Recalibrate

Request Sense

Seek

Set Features

Set Multiple Mode

Set Sleep Mode

Stand By

Stand By Immediate

Translate Sector

Wear Level

Write Buffer

Write DMA

Write Multiple

Write Multiple w/o Erase

Write Sector(s)

Write Sector(s) w/o Erase

Write Verify

Invalid Command Code

Error and Status Register summarizes the valid status and error value for all the CF-ATA Command set.

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TS32M~1GCF80

80X CompactFlash Card

6.CIS Description:

Address Data 7 6 5 4 3 2 1 0

Description of Contents

CIS function

000h

01h CISTPL_DEVICE

Device Info tuple

Tuple code

002h

004h

04h TPL_LINK Link

length is 4 byte

Link to next tuple

Device type, WPS

speed

DFh Device Type

Speed

Type=D: I/O device

WPS=1 : no WP switch

Speed=7: extend bye

006h

008h

00Ah

00Ch

79h Speed

79:80ns

Speed

01h # Address units –1 unit size

FFh CISTPL_END

2 Kbytes of address space

End of CISTPL_DEVICE

Common memory other

operating conditions tuple

Length is 5 byte

Device size

End marker

Tuple code

1Ch CISTPL_DEVICE_OC

00Eh

010h

05h TPL_LINK Link

Link to next tuple

Other Conditions

Information

02h

Ext Reserved

3V M 3V=1: dual voltage card,

conditions for 3.3V operation

M=0: conditions without wait

012h

DFh Device Type

79h Speed

Speed

Type=D: I/O device

Device type, WPS

speed

WPS=1 : no WP switch

Speed=7: extend bye

79:80ns

014h

016h

018h

01Ah

01Ch

01Eh

020h

022h

024h

026h

028h

02Ah

02Ch

02Eh

Speed

01h # Address units –1 unit size

FFh CISTPL_END

18h CISTPL_JEDEC_C

02h TPL_LINK

2 Kbytes of address space

End of CISTPL_DEVICE_OC

JEDEC programming info tuple

Link length is 2 byte

Mnufacturer ID

Device size

End marker

Tuple code

Link to next tuple

Manufacturer ID

Manufacturer info

Tuple code

DFh JEDEC ID Device

01h JEDEC Info

Manufacturer specific info

Manufacturer ID tuple

Length is 4 bytes

20h CISTPL_MANFID

04h TPL_LINK Link

0Ah TPLMID_MANF

00h

Link to next tuple

Manufacturer ID

PC Card manufacturer code

00h TPLMID_CARD

00h

Manufacturer specific info

Manufacturer info

Tuple code

15h CISTPL_VERS_1

Level 1 version/product info

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TS32M~1GCF80

80X CompactFlash Card

Address Data 7 6 5 4 3 2 1 0

Description of Contents

CIS function

030h

032h

034h

036h

038h

03Ah

03Ch

03Eh

040h

042h

044h

046h

048h

04Ah

04Ch

064h

066h

068h

06Ah

06Ch

06Eh

1Bh CISTPL_LINK

Link length is 27 bytes

PCMCIA2.0/JEIDA4.1

‘T’

Link to next tuple

Major version

Info string 1

04h TPPLV1_MAJOR

01h TPPLV1_MINOR

54h

52h

‘R’

41h

‘A’

‘ ’

4Eh

‘ ’

53h

43h

45h

4Eh

44h

20h

‘ ’

00h

Null terminator

54h…

Transcend PRODUCT Name

Null terminator

Info string 2

00h

FFh

End of CISTPL_VERS_1

Function ID tuple

End marker

21h CISTPL_FUNCID

02h CISTPL_LINK

04h TPLFID_FUNCTION

01h Reserved

Tuple code

Link length is 2 bytes

Fixed disk drive

Link to next tuple

Function code

System init byte

TPLFID_SYSINIT

Tuple code

R=0: no expansion ROM

P=1: configure at POST

Function Extension tuple

Link length is 2 bytes

Disk interface information

PC card ATA interface

Function Extension tuple

Link length is 3 bytes

PC card ATA basic features

070h

072h

074h

076h

078h

07Ah

07Ch

22h CISTPL_FUNCE

02h CISTPL_LINK

Link to next tuple

TPLFE_TYPE

TPLFE_DATA

Tuple code

01h Disk function extension tuple

01h Disk interface type

22h CISTPL_FUNCE

03h CISTPL_LINK

Link to next tuple

TPLFE_TYPE

02h Disk function extension tuple

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TS32M~1GCF80

80X CompactFlash Card

Address Data 7 6 5 4 3 2 1 0

Description of Contents

CIS function

07Eh

0Ch Reserved

D=0: single drive on card

U=1: unique serial number

S=1: silicon device

TPLFE_TYPE

V=00: no VPP required

I=0: twin IOIS16# unspecified

E=0: index bit not emulated

N=0: I/O includes 0x3F7

P=F(1111):low power, sleep, standby, idle

supported

080h

0Fh

TPLFE_TYPE

082h

084h

086h

1Ah CISTPL_CONFIG

05h TPL_LINK

Configuration Tuple

Tuple code

Link length is 5 bytes

RFS: reserved

Link to next tuple

Size of fields

TPCC_SZ

01h RFS RMS RAS

RMS: 1 byte register mask

RAS: 2 bytes base address

Last configuration entry is 03H

Configuration registers are

Located at 0200H

088h

08Ah

08Ch

08Eh

03h TPCC_LAST

Last entry index

Configuration

00h TPCC_RADR (LSB)

02h TPCC_RADR (MSB)

0Fh TPCC_RMSK

Configuration register

present mask

Configuration registers 0 to 3

are present

090h

092h

094h

1Bh CISTPL_CFTABLE_ENTRY

08h CISTPL_LINK

Configuration tuple

Tuple code

Link length is 8 bytes

Memory mapped configuration,

index=0

Link to next tuple

Configuration Table

Index Byte

C0h

Configuration Index

I=1: Interface byte follows

D=1: Default entry

TPCE_INDX

096h

C0h

Interface type

W=1: wait required

Interface

R=1: ready/busy active

P=0: WP not used

Description

TPCE_IF

B=0: BVD1, BVD2 not used

Type=0: Memory interface

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TS32M~1GCF80

80X CompactFlash Card

Address Data 7 6 5 4 3 2 1 0

Description of Contents

CIS function

098h

A1h M MS

IR IO T Power

M=1: misc info present

Feature Selection

Byte TPCE_FS

MS=1: 2 byte memory length

IR=0: no interrupt is used

IO=0: no I/O space is used

T=0: no timing info specified

Power=1: VCC info, no VPP

09Ah

01h

R DI PI AI SI HV LV NV DI: no power-down current

PI:no peak current info

Power Description

Structure Parameter

Selection Byte

TPCE_PD

AI: no average current info

SI: no static current info

HV:no max voltage info

LV:no min voltage info

NV=1: nominal voltage info

09Ch

09Eh

0A0h

0A2h

55h X Mantissa Exponent

Nominal voltage 5.0V

08h Length in 256 byte units (LSB)

Length of memory space is 2

Memory space

00h Length in 256 byte units (MSB) Kbyte

20h X R P RO A

descr. TPCE_MS

Miscellaneous

X=0: no more misc fields

P=1: power-down supported

RO=0:read/write media

A=0: audio not supported

T=0: max twins is 0

features TPCE_MI

0A4h

0A6h

0A8h

1Bh CISTPL_CFTABLE_ENTRY

06h CISTPL_LINK

Configuration tuple

Tuple code

Link length is 6 bytes

Memory mapped configuration,

index=0

Link to next tuple

TPCE_INDX

00h

Configuration Index

0AAh

0ACh

01h

21h

M MS

IR IO T Power Power=1: VCC info, no VPP

TPCE_FS

TPCE_PD

R DI PI AI SI HV LV NV PI=1: peak current info

NV=1: nominal voltage info

0AEh

0B0h

0B2h

B5h X Mantissa Exponent

1Eh X Extension

X=1: extension byte present

Nominal voltage 3.30V

Peak current 45 mA

4Dh X Mantissa Exponent

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TS32M~1GCF80

80X CompactFlash Card

Address Data 7 6 5 4 3 2 1 0

Description of Contents

CIS function

0B4h

0B6h

0B8h

1Bh CISTPL_CFTABLE_ENTRY

0Ah CISTPL_LINK

Configuration tuple

Tuple code

Link length is 10 bytes

I/O mapped, index=1

Link to next tuple

TPCE_INDX

C1h

41h

D Configuration Index

R P B Interface type

I=1: Interface byte follows

D=1: Default entry

0BAh

W=0: wait not required

R=1: ready/busy active

P=0: WP not used

TPCE_IF

B=0: BVD1, BVD2 not used

Type=1: I/O interface

0BCh

99h

M MS IR IO T Power

M=1: misc info present

MS=0: no memory space info

IR=1: interrupt is used

IO=1: I/O space is used

T=0: no timing info specified

Power=1: VCC info, no VPP

TPCE_FS

0BEh

01h

R DI PI AI SI HV LV NV DI: no power-down current

PI: no peak current info

TPCE_PD

AI: no average current info

SI: no static current info

HV:no max voltage info

LV:no min voltage info

NV=1: nominal voltage info

0C0h

0C2h

55h X Mantissa Exponent

64h IO

Nominal voltage 5.0V

S =1: support 16 bit hosts

E =1: support 8 bit hosts

IO=4: 4 address lines decoded

TPCE_IO

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TS32M~1GCF80

80X CompactFlash Card

Address Data 7 6 5 4 3 2 1 0

Description of Contents

CIS function

0C4h

F0h

N S=1: interrupt sharing logic

P=1: pulse mode supported

L=1: level mode supported

M=1: masks V..N present

V=0: no vendor unique IRQ

B=0: no bus error IRQ

I=0: no I/O check IRQ

N=0: no NMI

TPCE_IR

0C6h

0C8h

0CAh

FFh IRQ7..0

FFh IRQ15..8

Interrupt signal may be

Assigned to any host IRQ

X=0: no more misc fields

P=1: power-down supported

RO=0:read/write media

A=0: audio not supported

T=0: max twins is 0

20h

P RO A T

TPCE_MI

0CCh

0CEh

0D0h

0D2h

0D4h

1Bh CISTPL_CFTABLE_ENTRY

06h CISTPL_LINK

Configuration tuple

Tuple code

Link length is 6 bytes

Link to next tuple

TPCE_INDX

TPCE_FS

01h

21h

Configuration Index

I/O mapped, index=1

M MS IR IO T Power

Power=1: VCC info, no VPP

R DI PI AI SI HV LV NV PI=1: peak current info

NV=1: nominal voltage info

TPCE_PD

0D6h

0D8h

0DAh

0DCh

0DEh

0E0h

B5h X Mantissa Exponent

1Eh X Extension

X=1: extension byte present

Nominal voltage 3.30V

Peak current 45 mA

4Dh X Mantissa Exponent

1Bh CISTPL_CFTABLE_ENTRY

0Fh CISTPL_LINK

Configuration tuple

Tuple code

Link length is 15 bytes

I/O mapped, index=2

I =1: Interface byte follows

D=1: Default entry

Link to next tuple

TPCE_INDX

C2h

Configuration Index

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TS32M~1GCF80

80X CompactFlash Card

Address Data 7 6 5 4 3 2 1 0

Description of Contents

CIS function

0E2h

41h

W R

Interface type W=0: wait not required

R=1: ready/busy active

TPCE_IF

P=0: WP not used

B=0: BVD1, BVD2 not used

Type=1: I/O interface

0E4h

99h

M MS IR IO T Power

M=1: misc info present

TPCE_FS

MS=0: no memory space info

IR=1: interrupt is used

IO=1: I/O space is used

T=0: no timing info specified

Power=1: VCC info, no VPP

0E6h

01h

R DI PI AI SI HV LV NV DI: no power-down current

PI:no peak current info

TPCE_PD

AI: no average current info

SI: no static current info

HV:no max voltage info

LV:no min voltage info

NV=1: nominal voltage info

0E8h

55h X Mantissa Exponent

Nominal voltage 5.0V

R=1: range follows

0EAh

EAh

TPCE_IO

S=1: support 16 bit hosts

E=1: support 8 bit hosts

IO=10: 10 lines decoded

LS=1: 1 byte length

AS=2: 2 byte address

NR=1: 2 address ranges

Address range 1

0ECh

61h LS

0EEh

0F0h

0F2h

0F4h

0F6h

0F8h

F0h Base address 1 (LSB)

01h Base address 1 (MSB)

07h Address range 1 length

F6h Base address 2 (LSB)

03h Base address 2 (MSB)

01h Address range 2 length

0x1F0 to 0x1F7

Address range 2

0x3F6 to 0x3F7

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TS32M~1GCF80

80X CompactFlash Card

Address Data 7 6 5 4 3 2 1 0

Description of Contents

CIS function

0FAh

EEh

M IRQN

S=1: interrupt sharing logic

P=1: pulse mode supported

L=1: level mode supported

M=0: masks V..N not present

IRQN=14: use interrupt 14

X=0: no more misc fields

P=1: power-down supported

RO=0:read/write media

A=0: audio not supported

T=1: max twins is 0

TPCE_IR

0FCh

20h

P RO A

TPCE_MI

0FEh

100h

102h

104h

106h

1Bh CISTPL_CFTABLE_ENTRY

06h CISTPL_LINK

Configuration tuple

Tuple code

Link length is 6 bytes

Link to next tuple

TPCE_INDX

TPCE_FS

02h

01h

21h

Configuration Index

I/O mapped, index=2

M MS IR IO T Power

Power=1: VCC info, no VPP

R DI PI AI SI HV LV NV PI=1: peak current info

NV=1: nominal voltage info

TPCE_PD

108h

10Ah

10Ch

10Eh

110h

112h

B5h X Mantissa Exponent

1Eh X Extension

X=1: extension byte present

Nominal voltage 3.30V

Peak current 45 mA

4Dh X Mantissa Exponent

1Bh CISTPL_CFTABLE_ENTRY

0Fh CISTPL_LINK

Configuration tuple

Tuple code

Link length is 15 bytes

I/O mapped, index=3

I=1: Interface byte follows

D=1: Default entry

Link to next tuple

TPCE_INDX

C3h

Configuration Index

114h

41h

W R

Interface type

W=0: wait not required

R=1: ready/busy active

P=0: WP not used

TPCE_IF

B=0: BVD1, BVD2 not used

Type=1: I/O interface

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TS32M~1GCF80

80X CompactFlash Card

Address Data 7 6 5 4 3 2 1 0

Description of Contents

CIS function

116h

99h

M MS IR IO T Power

M=1: misc info present

TPCE_FS

MS=0: no memory space info

IR=1: interrupt is used

IO=1: I/O space is used

T=0: no timing info specified

Power=1: VCC info, no VPP

118h

R DI PI AI SI HV LV NV DI: no power-down current

PI:no peak current info

TPCE_PD

AI: no average current info

SI: no static current info

HV:no max voltage info

LV:no min voltage info

NV=1: nominal voltage info

11Ah

11Ch

55h X Mantissa Exponent

EAh R S IO

Nominal voltage 5.0V

R=1: range follows

TPCE_IO

S=1: support 16 bit hosts

E=1: support 8 bit hosts

IO=10: 10 lines decoded

LS=1: 1 byte length

AS=2: 2 byte address

NR=1: 2 address ranges

Address range 1

11Eh

61h LS AS NR

120h

122h

124h

126h

128h

12Ah

12Ch

70h Base address 1 (LSB)

01h Base address 1 (MSB)

07h Address range 1 length

76h Base address 2 (LSB)

03h Base address 2 (MSB)

01h Address range 2 length

0x170 to 0x177

Address range 2

0x376 to 0x377

EEh

S P

M IRQN

S=1: interrupt sharing logic

P=1: pulse mode supported

L=1: level mode supported

M=0: masks V..N not present

IRQN=14: use interrupt 14

TPCE_IR

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TS32M~1GCF80

80X CompactFlash Card

Address Data 7 6 5 4 3 2 1 0

Description of Contents

CIS function

12Eh

20h

P RO A T

X=0: no more misc fields

P=1: power-down supported

RO=0:read/write media

A=0: audio not supported

T=0: max twins is 0

TPCE_MI

130h

132h

134h

136h

138h

1Bh CISTPL_CFTABLE_ENTRY

06h CISTPL_LINK

Configuration tuple

Tuple code

Link length is 6 bytes

Link to next tuple

TPCE_INDX

TPCE_FS

03h

01h

21h

Configuration Index

I/O mapped, index=3

M MS IR IO T Power

Power=1: VCC info, no VPP

R DI PI AI SI HV LV NV PI=1: peak current info

NV=1: nominal voltage info

TPCE_PD

13Ah

13Ch

13Eh

140h

142h

144h

146h

B5h X Mantissa Exponent

1Eh X Extension

X=1: extension byte present

Nominal voltage 3.30V

Peak current 45 mA

No link control tuple

Link length is 0 bytes

End of CISTPL_VERS_1

End of CIS

4Dh X Mantissa Exponent

14h CISTPL_NO_LINK

00h CISTPL_LINK

FFh

Tuple code

Link to next tuple

End marker

FFh CISTPL_END

Tuple code

Above technical information is based on industry standard data and tested to be reliable. However, Transcend makes no

warranty, either expressed or implied, as to its accuracy and assumes no liability in connection with the use of this product.

Transcend reserves the right to make changes in specifications at any time without prior notice.

Transcend Information Inc.

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