T
L
C
4
5
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User’s Guide
January 2002
AAP Data Acquisition (Dallas)
SLAU081
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EVM IMPORTANT NOTICE
Texas Instruments (TI) provides the enclosed product(s) under the following conditions:
This evaluation kit being sold by TI is intended for use for ENGINEERING
DEVELOPMENT OR EVALUATION PURPOSES ONLY and is not considered by TI to
befitforcommercialuse. Assuch, thegoodsbeingprovidedmaynotbecompleteinterms
of required design-, marketing-, and/or manufacturing-related protective considerations,
including product safety measures typically found in the end product incorporating the
goods. As a prototype, this product does not fall within the scope of the European Union
directive on electromagnetic compatibility and therefore may not meet the technical
requirements of the directive.
Should this evaluation kit not meet the specifications indicated in the EVM User’s Guide,
the kit may be returned within 30 days from the date of delivery for a full refund. THE
FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY SELLER TO
BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR
STATUTORY, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS
FOR ANY PARTICULAR PURPOSE.
The user assumes all responsibility and liability for proper and safe handling of the goods.
Further, the user indemnifies TI from all claims arising from the handling or use of the
goods. Please be aware that the products received may not be regulatory compliant or
agency certified (FCC, UL, CE, etc.). Due to the open construction of the product, it is
the user’s responsibility to take any and all appropriate precautions with regard to
electrostatic discharge.
EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE, NEITHER
PARTY SHALL BE LIABLE TO THE OTHER FOR ANY INDIRECT, SPECIAL,
INCIDENTAL, OR CONSEQUENTIAL DAMAGES.
TI currently deals with a variety of customers for products, and therefore our arrangement
with the user is not exclusive.
TI assumes no liability for applications assistance, customer product design,
software performance, or infringement of patents or services described herein.
Please read the EVM User’s Guide and, specifically, the EVM Warnings and Restrictions
notice in the EVM User’s Guide prior to handling the product. This notice contains
important safety information about temperatures and voltages. For further safety
concerns, please contact the TI application engineer.
Personshandlingtheproductmusthaveelectronicstrainingandobservegoodlaboratory
practice standards.
No license is granted under any patent right or other intellectual property right of TI
covering or relating to any machine, process, or combination in which such TI products
or services might be or are used.
Mailing Address:
Texas Instruments
Post Office Box 655303
Dallas, Texas 75265
Copyright 2002, Texas Instruments Incorporated
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EVM WARNINGS AND RESTRICTIONS
It is important to operate this EVM within the input voltage range of ±12 V and the output
voltage range of ±12 V.
Exceeding the specified input range may cause unexpected operation and/or irreversible
damage to the EVM. If there are questions concerning the input range, please contact a TI
field representative prior to connecting the input power.
Applyingloadsoutsideofthespecifiedoutputrangemayresultinunintendedoperationand/or
possible permanent damage to the EVM. Please consult the EVM User’s Guide prior to
connecting any load to the EVM output. If there is uncertainty as to the load specification,
please contact a TI field representative.
During normal operation, some circuit components may have case temperatures greater than
60°C. The EVM is designed to operate properly with certain components above 60°C as long
as the input and output ranges are maintained. These components include but are not limited
tolinearregulators, switchingtransistors, passtransistors, andcurrentsenseresistors. These
types of devices can be identified using the EVM schematic located in the EVM User’s Guide.
When placing measurement probes near these devices during operation, please be aware
that these devices may be very warm to the touch.
Mailing Address:
Texas Instruments
Post Office Box 655303
Dallas, Texas 75265
Copyright 2002, Texas Instruments Incorporated
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Contents
1
2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.1
EVM Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1.1.1 Stand-Alone Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
1.1.2 User Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
Analog Input Conditioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
Analog Output Conditioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
Prototype Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
1.2
1.3
1.4
Getting Started . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.1
2.2
Shipping (Default Configuration) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2.2.1 Analog I/O Signal Conditioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2.2.2 Channel 0 Analog Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2.2.3 Channel 0 Analog Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
2.2.4 Signal Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
2.2.5 Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
2.2.6 ADC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
2.2.7 Clock/Timer Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2.3.1 Stand-Alone-Mode, SW1-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
ADC and DAC Direct Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
Host Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
2.6.1 Common Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
2.6.2 Legacy Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
2.3
2.4
2.5
2.6
A
Bill of Materials, Board Layout, and Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1
v
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Figures
2–1
SAM Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Tables
2–1
2–2
2–3
Default Switch Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Default Jumper Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Jumper/Function Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
vi
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Chapter 1
Introduction
This chapter contains an overview of the features and functions of the EVM.
Topic
Page
1.1 EVM Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2
1.2 Analog Input Conditioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3
1.3 Analog Output Conditioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3
1.4 Prototype Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3
1-1
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EVM Modes
This user’s guide has been written to help you get the most from your
evaluation module (EVM). The TLC4541 EVM is a member of the
multipurpose (MP) family of serial EVMs. It provides a platform to demonstrate
the performance and functionality of the TLC4541 ADC and the
TLV5636 DAC.
TI’s websites are regularly updated. They present the latest software
additions, development information, troubleshooting help, general
background, as well as all applicable data sheets.
For specific questions related to this EVM or device send an email to the
orderable tool description – TLC4541 EVM.
This user’s guide is divided into the following chapters:
- Chapter 1 offers an overview of the EVM and introduces the general
features and functions of the system.
- Chapter 2 describes the operation of the EVM from a user’s view. It details
options that can be modified, connectors used, and pinout details.
- Appendix A details the bill of materials (BOM) and the schematic, along
with explanations of certain EVM features.
1.1 EVM Modes
This EVM has been designed, tested, and shipped in a condition that enables
the user to begin evaluation with minimal effort.
There are basically two operating modes for the EVM. These modes are
mutually exclusive. They are:
- Stand-Alone Mode (SAM)
Stand-alone mode enables the user to check the system without the
support of a signal generator, pattern generator, or DSP. In this mode, the
digital output from the ADC is fed into the companion DAC and
reconstructed.
User mode is deselected if SAM is selected. The DSP will be unable to
communicate with either the ADC or the DAC.
- User Mode
The EVM typically operates via a DSP or a microprocessor. In this mode
theuserisresponsibleforgeneratingallthecontrolsignals. Ifusermodeis
selected, SAM is deselected.
1-2
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Analog Input Conditioning
1.1.1 Stand-Alone Mode
A unique feature of this EVM is the facility it offers the user to closely couple
the ADC and DAC with a minimum of user intervention. This feature allows the
serial bit stream from the digitized analog output to be fed directly to the DAC.
Therefore, the signal that is fed into the ADC can be reconstructed via the
DAC. No DSP need be present.
SAM is selected by:
- Switching SW1-1 to the on position, LED is on.
1.1.2 User Mode
The user can connect the ADC to a DSP or to a microprocessor in two ways:
- Via IDC ribbon cable
- Via daughterboard connectors J16 and J17
User mode is selected by:
- Switching SW1-1 to the off position, LED is off.
For example, TI’s range of DSP starter kits (DSK modules) provides a simple
low-cost solution, offering a range of DSK modules for most needs. The EVM
also supports the TMS320C6000 daughtercard specification (SPRA711), in
addition to providing support for the Motorola specification for data
transfer (SPI).
1.2 Analog Input Conditioning
There are a number of methods to connect analog input signals to the EVM.
Chapter 2 discusses these alternatives.
1.3 Analog Output Conditioning
There are a number of methods to connect analog output signals to the EVM.
Chapter 2 discusses these alternatives.
1.4 Prototype Area
An area of the PWB has been set aside if none of the signal conditioning
options provided are suitable.
The prototype area has the following features:
- A matrix of plated-through holes (PTH)
- SMT pads in a standard 14-pin JEDEC footprint
- Convenient points to pick up all power options
Introduction
1-3
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Chapter 2
Getting Started
This chapter describes how the user can modify the various options of
this EVM.
Topic
Page
2.1 Shipping (Default Configuration) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.2 Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2.3 Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2.4 Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2.5 ADC and DAC Direct Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
2.6 Host Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
2-1
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Shipping (Default Configuration)
It is very important that users feel comfortable with the EVM from the
beginning. To achieve this, each unit is manufactured and shipped in a
predetermined condition. This allows the user to begin evaluation of the
system immediately and to have confidence that the EVM is working.
To confirm that the EVM is working properly, follow the steps below:
1) Apply power to the system. The green LED will illuminate.
2) Ensure stand-alone mode (SAM) LED is on.
3) Check TP7 via oscilloscope. This will be a sine wave.
4) Press the reset button SW3.
5) Press the start button SW2.
6) Check TP20 with an oscilloscope. If the system is working properly, the
signal at TP20 will also be a sine wave.
The system works as illustrated below. Any analog input supplied to the ADC
will be digitized and reconstructed by the DAC.
Figure 2–1. SAM Configuration
TP7
Data
Data
ADC
Control
Electronics
DSP / Micro
Interface
DAC
TP20
The user may probe the data and control signals to observe the signals that
allow stand-alone mode to function.
2.1 Shipping (Default Configuration)
The EVM is tested and shipped with jumpers and switches in a predetermined
arrangement. This arrangement enables users to verify at once that the EVM
is working. The tables below list switch and jumper settings that the EVM
should be set to upon receipt.
2-2
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Shipping (Default Configuration)
Table 2–1.Default Switch Settings
Switch Settings
Default
Description
Configuration
SW1-1
SW1-2
SW1-3
SW1-4
On
Off
Off
Off
Stand-alone mode is selected, LED is on
Reserved
Reserved
Reserved
Table 2–2.Default Jumper Settings
Jumper Settings
Default Configuration
Description
Pins 1–2
Pins 2–3
Not inserted
Inserted
W1
Inserted
Input for channel 0 is via BNC connector J1.
Sine wave test signal is selected for channel 0.
Sine wave test signal is output for channel 0.
Onboard conditioned input for channel 0 is selected.
Not populated
W2
Not inserted
Not inserted
Not inserted
W3
Inserted
W4
Inserted
W5
Not populated
W6
Not populated
Not populated
Not populated
Not inserted
Not populated
W7
Not populated
W8
Not populated
W9
Disables onboard sine and triangle wave generator
SCLK routed to ADC
W10 Inserted
Not inserted
Inserted
W11 Not inserted
W12 Inserted
Signal conditioning output selected for channel 0
FS routed to ADC
Not inserted
W13
Not Inserted
Inserted
Not populated
Not inserted
5-V analog
W14
EVM reference or DAC’s on-chip reference selected.
Not populated
W15
W16 Inserted
W17 Inserted
W18 Not inserted
W19 Inserted
Selects internal or external reference
Determines EVM reference voltage
FS routed to DAC
Not inserted
Inserted
Not inserted
Selects source of signal conditioning output from DAC
W20
Not inserted
W21 Inserted
W22 Inserted
W23 Inserted
W24
Not inserted
Not inserted
Not inserted
These jumpers determine various options for supplying system
clock. This has been designed to be as flexible as possible to
accommodate many potential options.
Not inserted
Not populated
W25
Not populated
The hardware that can be reconfigured falls into one of the following sections:
- Jumpers
- Switches
- Connectors
Getting Started
2-3
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Jumpers
2.2 Jumpers
The table below lists the functions that users can reconfigure along with the
shipping condition.
Table 2–3.Jumper/Function Reference
Function
Reference Designator
Subsection
Channel 0
Analog input
Analog output
W1, W11, W4, W2, W3
W14, W19, W18
3.2.3
3.2.4
3.2.7
3.2.8
3.2.9
3.2.10
Disable onboard signal generator W9
Voltage reference
W16, W17
3.3-V/5-V analog supply select
Clock/timer routing
W13
W20, W21, W22, W23, W24
2.2.1 Analog I/O Signal Conditioning
The TLC4541 supports various signal conditioning configurations.
The user has the following options:
- Bypass signal conditioning
- Use the onboard signal conditioning. This consists of an operational
amplifier for each input channel configured with a gain of 1.
- Use the prototype area for signal conditioning.
- Use the expansion connector via a TI universal operational amplifier
evaluation module (such as SLOP224/SLOP249).
2.2.2 Channel 0 Analog Input
This is the primary analog input and can always be connected externally.
Analog Input Configuration Channel 0
Functional Description
Reference
Designator
W1
W11
W4
W1 allows the user to select between an analog input via BNC – J1 or IDC – J4 pin 1.
W11 allows selection of either the conditioned or nonconditioned analog input signal.
W4 allows the user to select either the prototype area output or the output from W11.
W2
W2 enables the user to select either the output from the expansion connector or the output
from the onboard signal generator.
W3
W3 completes the selection choices for channel 0 by determining if the output from W2 or W4
is chosen to be presented to the ADC.
2-4
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Jumpers
2.2.3 Channel 0 Analog Output
With a one-channel DAC installed, this signal is the primary analog output
(output A).
With a two-channel DAC installed, the pinout of these devices effectively
resolves this channel to be the secondary analog output (output B).
Analog Input Configuration Channel 0
Reference
Designator
Functional Description
W19
This jumper selects the source for the analog output on channel 0.
When a jumper is installed between pins 1 and 2, the output from the expansion connector’s
B-channel is routed out.
When the jumper is installed between pins 2 and 3, the output from the onboard signal
conditioning is directed through channel 0.
2.2.4 Signal Generator
Signal Generator
Reference
Designator
Functional Description
W9
W9 controls the generation of both onboard test signals. A jumper installed between pins 1 and 2
disables the waveform generator.
2.2.5 Voltage Reference
Voltage Reference
Functional Description
Reference
Designator
W16
W17
W14
W16 selects either the onboard reference or an external reference supplied by the user.
W17 allows the user to vary the reference voltage.
There are a number of possible DACs that a user can install on this EVM. Some have an internal
reference that the user can select via software, and some do not have an internal reference. For
the DACs that support an internal reference, it is important to have the facility to remove the
external reference supplied by the EVM (or user) to avoid conflicts between the DAC’s internal
reference and the external reference.
2.2.6 ADC Supply Voltage
ADC Supply Voltage
Functional Description
Reference
Designator
W13
This jumper controls the analog supply voltage.
When the jumper is installed, the supply voltage to the ADC is 3.3 V.
When the jumper is not installed, the supply voltage to the ADC is 5 V.
Getting Started
2-5
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Switches
2.2.7 Clock/Timer Routing
A variety of options are available to the user. Be careful about altering these.
Clock/Timer Routing
Reference
Designator
Functional Description
W21
This jumper defines the clock that the ADC and DAC use for all their timing. The user can select
either the output from W23 or the output from W22 to be the base clock for the system.
W23
This jumper allows the user to select either an external clock, or the onboard 20-MHz oscillator for
conversion. In addition, this signal is fed to W20.
W20
W22
W20 provides a route for the EVM to generate CLKS for a DSP if so desired.
This jumper enables the user to select either the transmit clock from a DSP, or the output
from W24.
W24
W24 connects or isolates the timer output from a DSP.
2.3 Switches
There are three switches present on the EVM:
- One 8-pin DIL switch which houses four individual switches; these are
denoted SW1-1, SW1-2, SW1-3, and SW1-4.
- Two momentary push-button switches
Features and functions of each switch:
Reference
Designator
Default
Condition
Function
SW1-1
Selects either stand-alone mode (SAM) or user mode
SAM
SW1-2
SW1-3
SW1-4
Reserved
Reserved
Reserved
2.3.1 Stand-Alone-Mode, SW1-1
SW1-1 chooses either stand-alone mode or user mode. If the switch is set to
the off position, SAM is selected and the EVM ignores all signals generated
by a DSP. In addition, the EVM will not output any signals to a DSP or
microprocessor.
In this mode, SW2 and SW3 are used to reset the EVM’s logic and initiate
automatic conversions from the ADC, in addition to automatically routing the
serial bit stream from the ADC to the DAC for reconstruction.
Reference
Function
Designator
SW2
Initiates ADC and DAC conversions in SAM
Forces the EVM’s control logic into a known state
SW3
2-6
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Connectors
If SW1-1 is set to the on position, user mode is selected. In this case the user
has absolute control of the data and control signals for the ADC and DAC. With
SW1-1 in the on position, the logic that generates the control for SAM is
disabled and plays no active part in the process.
2.4 Connectors
In addition to jumpers and switches, the user also has access to various
connectors. This section details the pinout of each connector.
Reference
Description
Designator
J1
Analog input option for channel 0, miniature BNC
Cells in grey are not supported (tracked) directly by this EVM.
Reference
Pin
Description
Function
Designator
Number
J3
Analog input option
for universal
operational-amplifier
evaluation board, SIL
PTH not installed.
1
2
Noninverting input signal to dual operational amplifier, (2)
Noninverting input signal to dual operational amplifier, (2)
Inverting input signal to dual operational amplifier, (2)
Inverting input signal to dual operational amplifier, (2)
Nonfiltered output from dual operational amplifier, (2)
Filtered output from dual operational amplifier, (2)
+V supply
3
4
5
6
7
8
Operational amplifier (2) shutdown signal
Reference voltage
9
10
11
12
13
14
15
16
17
18
Analog ground
Operational amplifier (1) shutdown signal
–V supply
Nonfiltered output from dual operational amplifier, (1)
Filtered output from dual operational amplifier, (1)
Noninverting input signal to dual operational amplifier, (1)
Noninverting input signal to dual operational amplifier, (1)
Inverting input signal to dual operational amplifier, (1)
Inverting input signal to dual operational amplifier, (1)
Getting Started
2-7
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Connectors
Reference
Designator
Pin
Number
Description
Function
J4
Analog input option, 26-pin
DIL header
1
Channel 0 input
AGND
2
3
Channel 1 input
AGND
4
5
Not connected
AGND
6
7
Not connected
AGND
8
9
Not connected
AGND
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
Not connected
AGND
Not connected
AGND
Not connected
AGND
Not connected
AGND
Not connected
AGND
Not connected
AGND
Not connected
AGND
External reference voltage
AGND
Reference
Designator
Description
J5
Analog output for one-channel DAC
2-8
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Connectors
Reference
Designator
Pin
Number
Description
EVM power
Function
J7
1
2
5 V
–12 V
0 V
3
4
12 V
J8
Analog output option,
26-pin DIL header
1
No output
AGND
2
3
Analog output for one-channel DAC
AGND
4
5
Not connected
AGND
6
7
Not connected
AGND
8
9
Not connected
AGND
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
Not connected
AGND
Not connected
AGND
Not connected
AGND
Not connected
AGND
Not connected
AGND
Not connected
AGND
Not connected
AGND
Not connected
AGND
Getting Started
2-9
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Connectors
Reference
Designator
Pin
Number
Description
Function
J9
Analog input option
for universal
operational-amplifier
evaluation board, SIL
PTH not installed.
1
2
Noninverting input signal to dual operational amplifier, (2)
Noninverting input signal to dual operational amplifier, (2)
Inverting input signal to dual operational amplifier, (2)
Inverting input signal to dual operational amplifier, (2)
Nonfiltered output from dual operational amplifier, (2)
Filtered output from dual operational amplifier, (2)
+V supply
3
4
5
6
7
8
Operational amplifier (2) shutdown signal
Reference voltage
9
10
11
12
13
14
15
16
17
18
Analog ground
Operational amplifier (1) shutdown signal
–V supply
Nonfiltered output from dual operational amplifier, (1)
Filtered output from dual operational amplifier, (1)
Noninverting input signal to dual operational amplifier, (1)
Noninverting input signal to dual operational amplifier, (1)
Inverting input signal to dual operational amplifier, (1)
Inverting input signal to dual operational amplifier, (1)
2-10
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ADC and DAC Direct Access
2.5 ADC and DAC Direct Access
J10 and J11 offer users the facility to directly inspect the digital signals coming
from and going to the ADC and DAC.
Reference
Designator
Pin
Number
Description
Signal
Digital ground
SDO
J10
Allows the user direct access to all digital signals for the ADC
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
Digital ground
SCLK
Digital ground
CS or CS/FS
Digital ground
FS
J11
Allows the user direct access to all digital signals for the DAC
Digital ground
SDI
Digital ground
SCLK
Digital ground
CS
Digital ground
FS
2.6 Host Communication
There are two ways to connect a host system (DSP/microprocessor):
- Texas Instruments’ new DSKs provide two dedicated 80-pin connectors.
The EVM can be plugged directly onto these DSKs. This connector
standard is referred to as the common connector.
- Legacy DSKs not equipped with the 80-pin common connectors will
communicate via the daisy-chained legacy header.
The following sections discuss each connection method.
Getting Started
2-11
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Host Communication
2.6.1 Common Connector
Reference
Designator
Pin
Number
Description
Function
5 V
J16
80-pin memory interface connector for ’C5000 and ’C6000 DSK
1
EVMs. Pins unused by this EVM are omitted for clarity.
2
5 V
11
12
21
22
29
30
31
32
41
42
51
52
61
62
71
72
79
80
PCI ground
PCI ground
5 V
5 V
PCI ground
PCI ground
PCI ground
PCI ground
3.3 V
3.3 V
PCI ground
PCI ground
PCI ground
PCI ground
PCI ground
PCI ground
PCI ground
PCI ground
2-12
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Host Communication
Reference
Designator
Pin
Number
Description
Function
12 V
J17
80-pin peripheral and control connector for ’C5000 and ’C6000
1
DSK EVMs. Pins unused by this EVM are omitted for clarity.
2
–12 V
3
PCI ground
PCI ground
5 V
4
5
6
5 V
7
PCI ground
PCI ground
5 V
8
9
10
35
33
36
25
26
39
41
42
31
32
37
38
43
44
45
49
51
52
61
62
76
77
79
80
5 V
FSX
CLKX
DX
PCI ground
PCI ground
CLKR
FSR
DR
PCI ground
PCI ground
PCI ground
PCI ground
PCI ground
PCI ground
TOUT
XF
PCI ground
PCI ground
PCI ground
PCI ground
PCI ground
PCI ground
PCI ground
PCI ground
Getting Started
2-13
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Host Communication
2.6.2 Legacy Connector
J12, J13, and J15 are three 2x20 headers daisy-chained together and are
collectively referred to as the legacy connector. The principle behind this
arrangement is to eliminate the confused and untidy custom cabling that is
typically present when connecting a legacy DSP to an EVM. This
daisy-chained connector method is flexible, robust, and makes it possible to
use a standard flat signal-cable assembly, improving reliability of
communications between host and EVM.
Two shorting bars are inserted in J12 and J15; these bars permit alternate pins
on J13 to be DGND. If the user has complete discretion over signal routing at
the host end, it is recommended that the host-end connector should reflect the
same pinout as J13.
However, if the host-end connector does not (or cannot) mirror the pinout for
J13, then some degree of signal-twisting is necessary. This is accomplished
on the EVM by removing the shorting bars on J12 and J15 and typically
wire-wrapping directly onto the appropriate header.
For example, if the host connector on the DSP has the pin assignment
described in the following table, then a 1:1 mapping is possible and the user
should plug a flat 20-way ribbon cable into J13.
Host Connector
EVM Connector – J13
Pin No. Signal Pin No. Signal
Pin No. Signal Pin No. Signal
1
3
XF
CLKX
CLKR
DX
2
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
1
3
XF
CLKX
CLKR
DX
2
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
4
4
5
6
5
6
7
8
7
8
9
DR
10
12
14
16
18
20
9
DR
10
12
14
16
18
20
11
13
15
17
19
FSX
11
13
15
17
19
FSX
FSR
FSR
Resvd
CLKS
TOUT
Resvd
CLKS
TOUT
However, if the host connector has a different signal pinout, the user should
remove the shorting bars from J12 and J15. A flat 20-way IDC ribbon cable can
still be used; in this case, the user should plug the connector into J12 of the
EVM. Since the cable is now plugged into J12, and all the signals on bothsides
of the J12 pins are routed to adjacent connector pins (J13 and J15), the user
can typically wire-wrap the associated host signal to the relevant EVM signal.
The example shown below demonstrates the steps that must be taken to
reassign the connector and wire-wrap the correct signals.
2-14
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Host Communication
Consider a host cable signal assignment as shown below:
Host Connector
Pin No. Signal Pin No. Signal
1
3
NA
NA
2
DGND
DGND
CLKR
DGND
DR
4
5
CLKX
TOUT
DX
6
7
8
9
10
12
14
16
18
20
11
13
15
17
19
FSX
NA
FSR
DGND
DGND
NA
XF
NA
NA
CLKS
The host connector mates with J12. Signals on either side of J12 are available
on J13 and J15.
J13
Host Connector Plugged into J12
J15
Pin No.
Pin No.
Signal
N/A
Pin No.
Signal
DGND
DGND
CLKR
DGND
DR
Pin No.
2
1
3
2
1
3
4
N/A
4
6
5
CLKX
TOUT
DX
6
5
8
7
8
7
10
12
14
16
18
20
9
10
12
14
16
18
20
9
11
13
15
17
19
FSX
N/A
FSR
11
13
15
17
19
DGND
DGND
N/A
XF
N/A
N/A
CLKS
Getting Started
2-15
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Host Communication
For clarity, the above table can be redrawn with J12 removed.
J13
J15
Pin No.
Signal
NA
Pin No. Signal
2
1
3
DGND
DGND
CLKR
DGND
DR
4
NA
6
CLKX
TOUT
DX
5
8
7
10
12
14
16
18
20
9
FSX
NA
11
13
15
17
19
FSR
DGND
DGND
NA
XF
NA
NA
CLKS
The table below shows the signal names and pin assignments that the
composite connector shown above must be mapped onto.
J13
Pin No. Signal
1
3
XF
CLKX
CLKR
DX
5
7
9
DR
11
13
15
17
19
FSX
FSR
Resvd
CLKS
TOUT
2-16
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Host Communication
All of the signals required to interface the EVM to the host are now available
on either J13 or J15. This is simply a matter of wire-wrapping in the following
way:
Wire Wrap
J13
J13
Pin No.
Signal
NA
Pin No. Signal
2
4
NA
6
CLKX
TOUT
DX
3
19
7
CLKX
TOUT
DX
8
10
12
14
16
18
20
FSX
NA
11
FSX
XF
1
XF
NA
NA
Wire Wrap
Jumper
Between
J15
Pin No. Signal
J13
J15
Pin No. Signal
Pin No. Signal
1
3
DGND
DGND
CLKR
DGND
DR
YES
YES
2
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
4
5
YES
5
CLKR
6
7
YES
8
9
YES
YES
9
DR
10
12
14
16
18
20
11
13
15
17
19
FSR
13
FSR
DGND
DGND
NA
YES
YES
CLKS
YES
17
CLKS
Getting Started
2-17
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Host Communication
All of these connectors are shown below:
Reference
Pin
Description
20-pin connector
Signal Name/Function
J13 pin 2
Designator
Number
J12
1
2
J15 pin 1
3
J13 pin 4
4
J15 pin 3
5
J13 pin 6
6
J15 pin 5
7
J13 pin 8
8
J15 pin 7
9
J13 pin 10
J15 pin 9
10
11
12
13
14
15
16
17
18
19
20
J13 pin 12
J15 pin 11
J13 pin 14
J15 pin 13
J13 pin 16
J15 pin 15
J13 pin 18
J15 pin 17
J13 pin 20
J15 pin 19
2-18
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Host Communication
Reference
Designator
Pin
Number
Description
Signal Name/Function
ADC select signal
J12 pin 1
J13
20-pin signal connector
1
2
3
CLKX/transmit clock
J12 pin 3
4
5
CLKR receive clock
J12 pin 5
6
7
DX/data transmit
J12 pin 7
8
9
DR/data receive
J12 pin 9
10
11
12
13
14
15
16
17
18
19
20
FSX/frame sync transmit
J12 pin 11
FSR/frame sync receive
J12 pin 13
Reserved
J12 pin 15
CLKS/sync clock
J12 pin 17
TOUT/host timer output
J12 pin 19
Getting Started
2-19
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Host Communication
Reference
Designator
Pin
Number
Description
20-Pin connector
Signal Name/Function
J12 pin 2
DGND
J15
1
2
3
J12 pin 4
DGND
4
5
J12 pin 6
DGND
6
7
J12 pin 8
DGND
8
9
J12 pin 10
DGND
10
11
12
13
14
15
16
17
18
19
20
J12 pin 12
DGND
J12 pin 14
DGND
J12 pin 16
DGND
J12 pin 18
DGND
J12 pin 20
DGND
2-20
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Appendix A
Bill of Materials, Board Layout, and
Schematics
This appendix contains the bill of materials, board layouts, and the EVM
schematics.
A-1
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1
2
3
4
Input Config
D
C
B
A
D
C
B
A
ADC
Interface
User connectors
DSP_CLKS
J1
J2
BNC_0
DSP_CLKS
ADC_Data_out
DSP_TOUT
ADC_Data_out
DSP_TOUT
BNC_1
SENSE
VREFP
SENSE
VREFP
DSP_FSX
DSP_FSR
DSP_FSX
DSP_FSR
FS
FS
J4
LCL_CS_ADC*
LCL_CLKX
LCL_CS_ADC*
2
4
6
8
1
3
5
7
9
IDC_0
IDC_1
LCL_CLKX
DSP_DX
DSP_DR
DSP_DX
DSP_DR
10
12 11
14 13
16 15
18 17
20 19
22 21
24 23
26 25
Channel_0
Channel_1
In_0
In_1
DSP_XF
DSP_XF
DSP_CLKX
DSP_CLKR
DSP_CLKX
DSP_CLKR
DAC
LCL_CLKX
J8
2
4
6
8
1
3
5
7
LCL_CS_DAC*
DAC_Data_in
DAC_Write*
LCL_CS_DAC*
J6
J5
DAC_Data_in
DAC_Write*
10
9
12 11
14 13
16 15
18 17
20 19
22 21
24 23
26 25
PCI_+5v
VREFP
AOUT
PCI_+12V
PCI_GND
PCI_-12V
AOUT_A
Power & Reference
J7
EXT_VREFP
+Supply
VREFP
SENSE
VREFP
SENSE
4
3
2
1
+Supply
Ground
-Supply
+5V_IN
PCI_+5v
PCI_+12V
PCI_GND
PCI_-12V
Ground
-Supply
+5V_IN
ꢀꢁ
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040500
D
C
B
A
Power
D
C
B
A
FL2
+VS
1
1
1
3
3
3
+Supply
+VIN
+Vs
C11
10uF
C57
+
+
R70
0
10uF
PCI_+12V
GND
FL3
Ground
REF_IN
R68
0
PCI_GND
GND
GND
FL4
-VS
-Supply
-VIN
-Vs
C10
10uF
C56
+
+
R69
0
10uF
PCI_-12V
GND
+DVdd
FB13
SM_FB_27--044447
+5V_IN
+DVdd
+DVdd
R58
0
PCI_+5v
Reference
+VIN
SENSE
SENSE
VREFP
VREFP
FL1
1
3
EXT_VREFP
EXT_REFP
ꢀꢁ
Power & Reference
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F
040500
TP16
+DVdd
+DVdd
D2
D
C
B
A
D
C
B
A
C51
C53
4.7uF
C50
0.1uF
C58
C59
C44
+
+
+
0.01uF
0.1uF
10uF
10uF
TP18
TP12
FB3
+Vs
BLM11A121SGPB
U6
TPS77801D
3
4
8
+VIN
IN
IN
PG
TP9
+AVdd
FB2
2
6
5
D1
Green
/ENA
OUT
OUT
+
+
BLM11A121SGPB
C24
C28
C29
C42
C20
C27
0.1uF
R63
357K
+
+
+
+
C25
10uF
C26
4.7uF
R18
20K
R24
590K
R17
1K
C31
4.7uF
C34
0.1uF
4.7uF
0.1uF
0.01uF
10uF
10uF
1
7
GND SENSE / FB
REF_IN
W13
TP11
R14
0
R62
0
R64
110K
TP13
FB1
-VIN
-Vs
ꢀꢁ
Power
BLM11A121SGPB
C33
10uF
+
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F
040500
R25
Not Installed
D
C
B
A
D
C
B
A
+Vs
C46
0.1uF
U11
2
3
SENSE
-In
TLE2081
6
Vout
W17
+In
RV9
10k
R20
0
U7
VRE3050
Vout
R23
0
RV10
100K
2
8
6
5
+VIN
+Vin
TP10
W16
VREFP
R29
10K
R50
5K
RV7
10k
-Vs
C30
C45
+
R66
4k
NR
TRIM
2.2uF
0.1uF
R65
6k
C38
+
2.2uF
EXT_REFP
R67
10K
ꢀꢁ
Reference
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040500
+AVdd
C22
0.1uF
C19
D
C
B
A
D
C
B
A
C47
0.01uF
10uF
ADC_REF
R19
0
ADC_REF
SENSE
VREFP
U501
4
5
AIN0
AIN1
8
MSOP ADC
C23
10uF
C14
0.1uF
+DVdd
U5
R10
10K
4
AIN0
In_0
AIN or AIN0 or AIN(+)
SOCKETED ADC
8
SDO
5
AIN1
C1
100pF
SCLK or AIN1 or AIN(-)
J10
1
3
5
7
2
4
6
8
ADC_Data_out
LCL_CLKX
In_1
W10
LCL_CS_ADC*
FS
W12
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+AVdd
2
040500
DAC Out
C43
C21
0.1uF
0.1uF
C41
D
C
B
A
DAC_OUT
D
C
B
A
VREFP
OUT/OUTB
R54
10K
10uF
W14
REF
J9
R55
10K
10
GND
C32
0.1uF
-VS
9
VREF2
V2-
12
7
U8
AOUT
W19
V2+
TP20
+VS
14
13
15
16
17
18
11
7
1
A2_FLT
A204+
A203+
A202-
A201-
A2/SD
OUT/OUTB
DIN
DAC_Data_in
SOCKETED DAC
REF
A2_OUT
+AVdd
LCL_CLKX
U801
J11
1
3
5
7
2
4
6
8
7
1
8
4
3
2
1
DAC SOP(D)
B2/SD
B201-
B202-
B203+
B204+
6
5
B2_FLT
B2_OUT
LCL_CS_DAC*
DAC_Write*
AOUT_A
W15
DAC Out
TP21
OUTA
W18
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DAC_OUTA
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-Vs
R33
0
2
040500
RV11
100K
C49
0.1uF
R32
0
D
C
B
A
D
C
B
A
R30
0
3
2
U12
+In
OUTA
TLE2081
R35
6
DAC_OUTA
Vout
4.7K
R31
-In
C52
NI
C48
+Vs
0.1uF
R34
0
-Vs
R51
5K
RV8
100K
R28
0
R27
0
C39
0.1uF
3
2
+In
OUT/OUTB
U9
R26
6
DAC_OUT
Vout
4.7K
R22
NI
-In
C36
ꢀꢁ
DAC Output
C40
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Memory Interface Connector
Peripheral & Control Connector
F
040500
FB12
CLKX
CLKR
DSP_CLKX
DSP_CLKR
+5v
+5v
BLM11A121SGPB
FB11
D
C
B
A
D
C
B
A
PCI_-12V
PCI_+12V
PCI_+5V
BLM11A121SGPB
FB5
+3.3v
+3.3v
1
3
5
7
9
2
4
6
8
1
3
5
7
9
2
4
6
8
FSX
FSR
DSP_FSX
DSP_FSR
BLM11A121SGPB
FB4
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
BLM11A121SGPB
FB6
DX
DR
DSP_DX
DSP_DR
BLM11A121SGPB
FB7
CLKX
FSX
CLKS
DX
BLM11A121SGPB
FB9
CLKR
FSR
XF
DSP_XF
DR
BLM11A121SGPB
TOUT
XF
FB10
TOUT
CLKS
DSP_TOUT
DSP_CLKS
BLM11A121SGPB
FB8
BLM11A121SGPB
J16
J17
J13
J12
J15
XF
1
3
5
7
9
2
4
6
8
10
1
3
5
7
9
2
4
6
8
10
1
3
5
7
9
2
4
6
8
10
CLKX
CLKR
DX
DR
FSX
FSR
PCI_GND
11 12
13 14
15 16
17 18
19 20
11 12
13 14
15 16
17 18
19 20
11 12
13 14
15 16
17 18
19 20
ꢀꢁ
User Connectors
CLKS
TOUT
12500 TI Boulevard. Dallas, Texas 75243
TITLE:
Engineer:
Joe Purvis
Joe Purvis
DOCUMENT CONTROL #:
REV:
6430333
Drawn By:
User connectors
DATE:
28-Nov-2001
A4
FILE:
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TO / FROM USER
CONNECTIONS
DSP_TOUT
SYSCLK
DSP_TOUT
DSP_CLKS
DSP_CLKX
DSP_CLKR
DSP_DX
D
C
B
A
D
C
B
A
DSP_CLKS
DSP_CLKX
DSP_CLKR
DSP_DX
+DVdd
EVM_CLKX
DSP_FSR
DSP_FSX
X1
VCC
R40
8
1
5
OE
33
C64
0.01uF
C65
0.1uF
DSP_DR
DSP_DR
4
SYSCLK
W24
DSP_FSX
DSP_FSR
DSP_XF
GND OUT
DSP_TOUT
DSP_FSX
DSP_FSR
DSP_XF
W22
W21
R45
R43
DSP_CLKX
Stand Alone Mode
33
33
R71
33
SYSCLK
DSP_CLKR
DSP_CLKS
SYSCLK
FS
FS
EVM_CLKX
W20
EVM_CLKX
R44
DSP_XF
LCL_CS_ADC*
LCL_CS_ADC*
LCL_CLKX
DSP_XF
W23
33
+DVdd
LCL_CLKX
DSP_FSX
J14
DSP_FSX
R6
DSP_DX
DSP_DR
ADC_Data_out
ADC_Data_out
DSP_DX
DSP_DR
MOM
430
R46
49.9K
R11
1K
MOM*
DAC_Type
TO / FROM ADC
D5
+DVdd
DAC_Type
+DVdd
DAC_Data_in
DAC_Data_in
R57
430
R38
1K
R56
430
LCL_CS_DAC*
DAC_Write*
LCL_CS_DAC*
DAC_Write*
R37
1K
SAM*
SW1C
D4
SAM*
TO DAC
D3
SW1D
In Out
4
5
ꢀꢁ
Digital Interface
SW1A
SW1B
12500 TI Boulevard. Dallas, Texas 75243
TITLE:
Engineer:
Drawn By:
Joe Purvis
Joe Purvis
DOCUMENT CONTROL #:
REV:
6430333
Digital Interface
EVM-0309R2.DDB
DATE:
28-Nov-2001
A4
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U16B
U13A
I12/O0/Q0
+DVdd
DSP_DR
MOM
17
18
19
16
13
12
11
10
9
DSP_DR
I11
14
28
GND
Vcc
ADC_Data_n3
ADC_Data_out
DSP_DX
ADC_TC*
START*
I13/O1/Q1
I14/O2/Q2
I15/O3/Q3
I16/O4/Q4
I17/O5/Q5
I18/O6/Q6
I19/O7/Q7
I20/O8/Q8
I21/O9/Q9
I10
C63
0.1uF
ADC_CS*
MOM
D
C
B
A
LCL_CS_ADC*
DAC_Data_in
I9
MOM
EVM_CLKX
SYSCLK
D
C
B
A
DAC_Data_in 20
EVM_CLKX
SYSCLK
DSP_FSX
DSP_DX
DSP_XF
SAM*
I8
TP15
21
I7
U13B
+DVdd
Q0
23
24
25
26
27
I6
DSP_FSX
DSP_DX
14
28
Q1
7
SAM*
GND
Vcc
I5
C55
0.1uF
Q2
6
DAC_Type
DSP_FSX
DSP_XF
I4
I3
DSP_XF
+DVdd
Q3
5
SAM*
INIT*
4
DAC_Type
ADC_Data_out
START*
R39
10K
I2
DAC_Type
ADC_Data_out
U14B
+DVdd
3
RESET
I1
TP14
14
28
1
8
15
22
2
SYSCLK
GND
Vcc
NC
NC
NC
NC
CLK/I0
C54
0.1uF
START
+DVdd
SW2
U10
U16A
I12/O0/Q0
U14A
I12/O0/Q0
I13/O1/Q1
RESET
+DVdd
3
4
R42
10K
OUT
RESET
17
18
19
20
21
23
24
25
26
27
16
ADC_TC*
17
16
FS
I11
I11
TP19
13
12
11
10
9
Q0
18
19
20
21
23
24
25
26
27
13
12
11
10
9
Q0
Q1
Q2
Q3
7
6
I13/O1/Q1
I14/O2/Q2
I15/O3/Q3
I16/O4/Q4
I17/O5/Q5
I18/O6/Q6
I19/O7/Q7
I20/O8/Q8
I21/O9/Q9
I10
I10
DISCH
THRES
C61
Q1
8
LCL_CS_DAC*
LCL_CLKX
I9
I14/O2/Q2
I15/O3/Q3
I16/O4/Q4
I17/O5/Q5
I18/O6/Q6
I19/O7/Q7
I20/O8/Q8
I21/O9/Q9
I9
VCC
R41
10K
Q2
5
I8
I8
CONT
C60
0.1uF
ADC_Data_n3
Q3
I7
I7
2
TRIG
C62
MOM
1
I6
I6
GND
7
DAC_Type
EVM_CLKX
DSP_FSX
DSP_XF
RESET
SYSCLK
7
DAC_Type
INIT*
NE555D
RESET
I5
I5
6
6
SW3
I4
I3
I4
I3
5
5
DSP_FSX
DSP_XF
RESET
ADC_Data_out
TP17
4
4
I2
I2
3
3
I1
I1
1
8
15
22
2
1
8
15
22
2
SYSCLK
NC
NC
NC
NC
CLK/I0
NC
NC
NC
NC
CLK/I0
ꢀꢁ
Stand Alone
12500 TI Boulevard. Dallas, Texas 75243
TITLE:
DAC_Write*
Engineer:
Drawn By:
Joe Purvis
Joe Purvis
DOCUMENT CONTROL #:
REV:
6430333
Stand Alone Mode
DATE:
28-Nov-2001
A4
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040500
Signal Conditioning
Prototype Area
D
C
B
A
D
C
B
A
IN_0
OUT_0
BB_Output_0
W4
IN_0
TP7
W3
R9
33
W11
BNC_0
Channel_0
C8
6800pF
W1
J3
1
2
3
4
8
5
B204+
B2_OUT
B203+
B202-
B201-
B2/SD
6
B2_FLT
W2
IDC_0
Signal Generator
Test signal 0
Test signal 1
11
18
17
16
15
A2/SD
A201-
A202-
A203+
A204+
W6
BNC_1
13
14
A2_OUT
A2_FLT
W5
+Vs
-Vs
7
12
9
V2+
TP6
W7
IDC_1
R12
V2-
Channel_1
33
C9
VREF2
GND
6800pF
10
Signal Conditioning
Prototype Area
OUT_1
BB_Output_1
W8
ꢀꢁ
Input Configuration
IN_1
IN_1
12500 TI Boulevard. Dallas, Texas 75243
TITLE:
W25
Engineer:
Drawn By:
Joe Purvis
Joe Purvis
DOCUMENT CONTROL #:
REV:
6430333
Input configuration
DATE:
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+Vs
2
040500
R8
D
C
B
A
D
C
B
A
4.7K
C6
C5
+
-Vs
0.1uF
10uF
TP5
C13
0.1uF
RV3
U4A
R5
4.7K
2
3
U3
1
Test Signal 0
6
5
4
100K
V+
TLE2082D
R60
R72
Duty adj.
Duty Adj.
+Vs
49.9K
49.9K
2
9
3
Sine Out
+Vs
C12
0.1uF
12
1
RV4
Sine Adj
Sine Adj
R59
10K
4.7K
C7
R7
4.7K
Square Out
0.1uF
10
Timing Cap.
8
7
-Vs
FM Sweep Input
FM Bias
W9
C17
1nF
Triangle Out
14
13
11
Not Connected
Not connected
V- / GND
R61
4.7K
TP8
RV6
ICL8038
U4B
R16
6
7
4.7K
Test Signal 1
5
100K
TLE2082D
C18
10uF
+
C15
0.1uF
+Vs
RV5
R13
4.7K
-Vs
10K
ꢀꢁ
Signal Generator
C16
0.1uF
R15
4.7K
12500 TI Boulevard. Dallas, Texas 75243
TITLE:
-Vs
Engineer:
Drawn By:
Joe Purvis
Joe Purvis
DOCUMENT CONTROL #:
REV:
6430333
Signal Generator
DATE:
28-Nov-2001
A4
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2
040500
D
C
B
A
D
C
B
A
TP1
TP2
IN_0
IN_1
BB_Output_0
BB_Output_1
TP3
TP4
PT1
1
14
13
12
11
10
9
2
3
4
5
6
7
8
ꢀꢁ
Prototype Area
12500 TI Boulevard. Dallas, Texas 75243
TITLE:
Engineer:
Drawn By:
Joe Purvis
Joe Purvis
DOCUMENT CONTROL #:
REV:
6430333
Prototype Area
DATE:
28-Nov-2001
A4
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F
040500
R3
NI
R4
0
D
C
B
A
D
C
B
A
+Vs
C2
0.1uF
2
3
U2
TLE2081
-In
6
Vout
OUT_1
IN_1
+In
R36
0
R47
0
C37
RV2
100K
R1
NI
R2
0
0.1uF
-Vs
R52
5K
+Vs
C4
0.1uF
2
3
U1
-In
TLE2081
6
Vout
OUT_0
IN_0
+In
R48
0
R49
0
ꢀꢁ
Signal Conditioning
RV1
100K
12500 TI Boulevard. Dallas, Texas 75243
C3
0.1uF
TITLE:
-Vs
Engineer:
Drawn By:
R53
5K
Joe Purvis
Joe Purvis
DOCUMENT CONTROL #:
REV:
6430333
Signal Conditioning
DATE:
28-Nov-2001
A4
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SIZE:
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SHEET:
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