8XC251SA, 8XC251SB,
8XC251SP, 8XC251SQ
Embedded Microcontroller
User’s Manual
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8XC251SA, 8XC251SB,
8XC251SP, 8XC251SQ
Embedded Microcontroller
User’s Manual
May 1996
Order Number 272795-002
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Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including in-
fringement of any patent or copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of
Sale for such products.
Intel retains the right to make changes to these specifications at any time, without notice. Microcontroller products may have
minor variations to this specification known as errata.
*Other brands and names are the property of their respective owners.
Contact your local Intel sales office or your distributor to obtain the latest specifications before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be
obtained from:
Intel Corporation
Literature Sales
P.O. Box 7641
Mt. Prospect, IL 60056-7641
or call 1-800-548-4725
COPYRIGHT © INTEL CORPORATION, 1996
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CONTENTS
CHAPTER 1
GUIDE TO THIS MANUAL
1.1
1.2
1.3
1.3.1
1.3.2
1.4
1.4.1
1.4.2
1.4.3
1.4.4
MANUAL CONTENTS................................................................................................... 1-1
NOTATIONAL CONVENTIONS AND TERMINOLOGY ................................................ 1-3
RELATED DOCUMENTS.............................................................................................. 1-5
Data Sheet ................................................................................................................1-6
Application Notes ......................................................................................................1-6
APPLICATION SUPPORT SERVICES.......................................................................... 1-7
World Wide Web .......................................................................................................1-7
CompuServe Forums ................................................................................................1-7
FaxBack Service .......................................................................................................1-8
Bulletin Board System (BBS) ....................................................................................1-8
CHAPTER 2
ARCHITECTURAL OVERVIEW
2.1
2.2
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
8XC251SA, SB, SP, SQ ARCHITECTURE ................................................................... 2-3
MCS 251 MICROCONTROLLER CORE....................................................................... 2-4
CPU ..........................................................................................................................2-5
Clock and Reset Unit ................................................................................................2-6
Interrupt Handler .......................................................................................................2-7
On-chip Code Memory ..............................................................................................2-7
On-chip RAM ............................................................................................................2-7
ON-CHIP PERIPHERALS.............................................................................................. 2-7
Timer/Counters and Watchdog Timer .......................................................................2-7
Programmable Counter Array (PCA) ........................................................................2-8
Serial I/O Port ...........................................................................................................2-8
2.3
2.3.1
2.3.2
2.3.3
CHAPTER 3
ADDRESS SPACES
3.1
3.1.1
3.2
3.2.1
ADDRESS SPACES FOR MCS® 251 MICROCONTROLLERS................................... 3-1
Compatibility with the MCS® 51 Architecture ...........................................................3-2
8XC251SA, SB, SP, SQ MEMORY SPACE.................................................................. 3-5
On-chip General-purpose Data RAM ........................................................................3-8
On-chip Code Memory (83C251SA, SB, SP, SQ/87C251SA, SB, SP, SQ) .............3-8
3.2.2
3.2.2.1
3.2.3
Accessing On-chip Code Memory in Region 00: ..................................................3-9
External Memory .....................................................................................................3-10
8XC251SA, SB, SP, SQ REGISTER FILE .................................................................. 3-10
Byte, Word, and Dword Registers ...........................................................................3-13
Dedicated Registers ................................................................................................3-13
3.3
3.3.1
3.3.2
3.3.2.1
3.3.2.2
Accumulator and B Register ..............................................................................3-13
Extended Data Pointer, DPX ..............................................................................3-15
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8XC251SA, SB, SP, SQ USER’S MANUAL
3.3.2.3
Extended Stack Pointer, SPX ............................................................................3-15
3.4 SPECIAL FUNCTION REGISTERS (SFRS) ............................................................... 3-16
CHAPTER 4
DEVICE CONFIGURATION
4.1
4.2
4.3
4.4
4.5
4.5.1
4.5.2
4.5.2.1
4.5.2.2
4.5.2.3
4.5.2.4
4.5.3
4.5.3.1
4.5.3.2
4.5.3.3
CONFIGURATION OVERVIEW .................................................................................... 4-1
DEVICE CONFIGURATION .......................................................................................... 4-1
THE CONFIGURATION BITS........................................................................................ 4-4
CONFIGURATION BYTE LOCATION SELECTOR (UCON)......................................... 4-5
CONFIGURING THE EXTERNAL MEMORY INTERFACE........................................... 4-8
Page Mode and Nonpage Mode (PAGE#) ................................................................4-8
Configuration Bits RD1:0 ..........................................................................................4-9
RD1:0 = 00 (18 External Address Bits) ................................................................4-9
RD1:0 = 01 (17 External Address Bits) ................................................................4-9
RD1:0 = 10 (16 External Address Bits) ..............................................................4-12
RD1:0 = 11 (Compatible with MCS 51 Microcontrollers) ....................................4-12
Wait State Configuration Bits ..................................................................................4-12
Configuration Bits WSA1:0#, WSB1:# ...............................................................4-12
Configuration Bit WSB .......................................................................................4-12
Configuration Bit XALE# ....................................................................................4-13
4.6
4.6.1
OPCODE CONFIGURATIONS (SRC)......................................................................... 4-13
Selecting Binary Mode or Source Mode ..................................................................4-14
MAPPING ON-CHIP CODE MEMORY TO DATA MEMORY (EMAP#) ...................... 4-16
INTERRUPT MODE (INTR)......................................................................................... 4-16
4.7
4.8
CHAPTER 5
PROGRAMMING
5.1
5.2
5.2.1
5.2.1.1
5.2.2
5.2.3
5.2.4
SOURCE MODE OR BINARY MODE OPCODES ........................................................ 5-1
PROGRAMMING FEATURES OF THE MCS® 251 ARCHITECTURE......................... 5-1
Data Types ................................................................................................................5-2
Order of Byte Storage for Words and Double Words ...........................................5-2
Register Notation ......................................................................................................5-2
Address Notation ......................................................................................................5-2
Addressing Modes ....................................................................................................5-4
DATA INSTRUCTIONS ................................................................................................. 5-4
Data Addressing Modes ............................................................................................5-4
5.3
5.3.1
5.3.1.1
5.3.1.2
5.3.1.3
5.3.1.4
5.3.1.5
5.3.2
5.3.3
5.3.4
Register Addressing .............................................................................................5-5
Immediate ............................................................................................................5-5
Direct ....................................................................................................................5-5
Indirect .................................................................................................................5-6
Displacement .......................................................................................................5-8
Arithmetic Instructions ...............................................................................................5-8
Logical Instructions ...................................................................................................5-9
Data Transfer Instructions .......................................................................................5-10
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CONTENTS
5.4
5.4.1
5.5
5.5.1
5.5.2
5.5.3
5.5.4
BIT INSTRUCTIONS ................................................................................................... 5-11
Bit Addressing .........................................................................................................5-11
CONTROL INSTRUCTIONS ....................................................................................... 5-12
Addressing Modes for Control Instructions .............................................................5-13
Conditional Jumps ..................................................................................................5-14
Unconditional Jumps ...............................................................................................5-15
Calls and Returns ...................................................................................................5-15
PROGRAM STATUS WORDS .................................................................................... 5-16
5.6
CHAPTER 6
INTERRUPT SYSTEM
6.1
6.2
6.2.1
6.2.2
6.3
OVERVIEW ................................................................................................................... 6-1
8XC251SA, SB, SP, SQ INTERRUPT SOURCES........................................................ 6-3
External Interrupts .....................................................................................................6-3
Timer Interrupts .........................................................................................................6-4
PROGRAMMABLE COUNTER ARRAY (PCA) INTERRUPT........................................ 6-5
SERIAL PORT INTERRUPT.......................................................................................... 6-5
INTERRUPT ENABLE................................................................................................... 6-5
INTERRUPT PRIORITIES............................................................................................. 6-7
INTERRUPT PROCESSING ......................................................................................... 6-9
Minimum Fixed Interrupt Time ................................................................................6-10
Variable Interrupt Parameters .................................................................................6-10
6.4
6.5
6.6
6.7
6.7.1
6.7.2
6.7.2.1
6.7.2.2
Response Time Variables ..................................................................................6-10
Computation of Worst-case Latency With Variables ..........................................6-12
Latency Calculations ..........................................................................................6-13
Blocking Conditions ............................................................................................6-14
Interrupt Vector Cycle ........................................................................................6-14
ISRs in Process ......................................................................................................6-15
6.7.2.3
6.7.2.4
6.7.2.5
6.7.3
CHAPTER 7
INPUT/OUTPUT PORTS
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
INPUT/OUTPUT PORT OVERVIEW............................................................................. 7-1
I/O CONFIGURATIONS................................................................................................. 7-2
PORT 1 AND PORT 3 ................................................................................................... 7-2
PORT 0 AND PORT 2 ................................................................................................... 7-2
READ-MODIFY-WRITE INSTRUCTIONS..................................................................... 7-5
QUASI-BIDIRECTIONAL PORT OPERATION.............................................................. 7-6
PORT LOADING............................................................................................................ 7-7
EXTERNAL MEMORY ACCESS................................................................................... 7-7
CHAPTER 8
TIMER/COUNTERS AND WATCHDOG TIMER
8.1
TIMER/COUNTER OVERVIEW..................................................................................... 8-1
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8XC251SA, SB, SP, SQ USER’S MANUAL
8.2
8.3
8.3.1
8.3.2
8.3.3
8.3.4
TIMER/COUNTER OPERATION................................................................................... 8-1
TIMER 0......................................................................................................................... 8-3
Mode 0 (13-bit Timer) ...............................................................................................8-4
Mode 1 (16-bit Timer) ...............................................................................................8-4
Mode 2 (8-bit Timer With Auto-reload) ......................................................................8-5
Mode 3 (Two 8-bit Timers) ........................................................................................8-5
TIMER 1......................................................................................................................... 8-5
Mode 0 (13-bit Timer) ...............................................................................................8-9
Mode 1 (16-bit Timer) ...............................................................................................8-9
Mode 2 (8-bit Timer with Auto-reload) .......................................................................8-9
Mode 3 (Halt) ............................................................................................................8-9
TIMER 0/1 APPLICATIONS........................................................................................... 8-9
Auto-load Setup Example .........................................................................................8-9
Pulse Width Measurements ....................................................................................8-10
TIMER 2....................................................................................................................... 8-10
Capture Mode .........................................................................................................8-11
Auto-reload Mode ...................................................................................................8-12
8.4
8.4.1
8.4.2
8.4.3
8.4.4
8.5
8.5.1
8.5.2
8.6
8.6.1
8.6.2
8.6.2.1
8.6.2.2
8.6.3
8.6.4
Up Counter Operation ........................................................................................8-12
Up/Down Counter Operation ..............................................................................8-13
Baud Rate Generator Mode ....................................................................................8-14
Clock-out Mode .......................................................................................................8-14
8.7
WATCHDOG TIMER ................................................................................................... 8-16
Description ..............................................................................................................8-16
Using the WDT ........................................................................................................8-18
WDT During Idle Mode ...........................................................................................8-18
WDT During PowerDown ........................................................................................8-18
8.7.1
8.7.2
8.7.3
8.7.4
CHAPTER 9
PROGRAMMABLE COUNTER ARRAY
9.1
9.1.1
PCA DESCRIPTION...................................................................................................... 9-1
Alternate Port Usage .................................................................................................9-2
PCA TIMER/COUNTER................................................................................................. 9-2
PCA COMPARE/CAPTURE MODULES ....................................................................... 9-5
16-bit Capture Mode .................................................................................................9-5
Compare Modes .......................................................................................................9-7
16-bit Software Timer Mode ......................................................................................9-7
High-speed Output Mode ..........................................................................................9-8
PCA Watchdog Timer Mode .....................................................................................9-9
Pulse Width Modulation Mode ................................................................................9-11
9.2
9.3
9.3.1
9.3.2
9.3.3
9.3.4
9.3.5
9.3.6
CHAPTER 10
SERIAL I/O PORT
10.1 OVERVIEW ................................................................................................................. 10-1
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CONTENTS
10.2 MODES OF OPERATION............................................................................................ 10-4
10.2.1 Synchronous Mode (Mode 0) ..................................................................................10-4
10.2.1.1 Transmission (Mode 0) ......................................................................................10-4
10.2.1.2 Reception (Mode 0) ............................................................................................10-5
10.2.2 Asynchronous Modes (Modes 1, 2, and 3) .............................................................10-6
10.2.2.1 Transmission (Modes 1, 2, 3) .............................................................................10-6
10.2.2.2 Reception (Modes 1, 2, 3) ..................................................................................10-6
10.3 FRAMING BIT ERROR DETECTION (MODES 1, 2, AND 3)...................................... 10-7
10.4 MULTIPROCESSOR COMMUNICATION (MODES 2 AND 3).................................... 10-7
10.5 AUTOMATIC ADDRESS RECOGNITION................................................................... 10-7
10.5.1 Given Address ........................................................................................................10-8
10.5.2 Broadcast Address ..................................................................................................10-9
10.5.3 Reset Addresses ...................................................................................................10-10
10.6 BAUD RATES............................................................................................................ 10-10
10.6.1 Baud Rate for Mode 0 ...........................................................................................10-10
10.6.2 Baud Rates for Mode 2 .........................................................................................10-10
10.6.3 Baud Rates for Modes 1 and 3 .............................................................................10-10
10.6.3.1 Timer 1 Generated Baud Rates (Modes 1 and 3) ............................................10-11
10.6.3.2 Selecting Timer 1 as the Baud Rate Generator ...............................................10-11
10.6.3.3 Timer 2 Generated Baud Rates (Modes 1 and 3) ............................................10-12
10.6.3.4 Selecting Timer 2 as the Baud Rate Generator ...............................................10-12
CHAPTER 11
MINIMUM HARDWARE SETUP
11.1 MINIMUM HARDWARE SETUP.................................................................................. 11-1
11.2 ELECTRICAL ENVIRONMENT ................................................................................... 11-2
11.2.1 Power and Ground Pins ..........................................................................................11-2
11.2.2 Unused Pins ............................................................................................................11-2
11.2.3 Noise Considerations ..............................................................................................11-2
11.3 CLOCK SOURCES...................................................................................................... 11-3
11.3.1 On-chip Oscillator (Crystal) .....................................................................................11-3
11.3.2 On-chip Oscillator (Ceramic Resonator) .................................................................11-4
11.3.3 External Clock .........................................................................................................11-4
11.4 RESET......................................................................................................................... 11-5
11.4.1 Externally Initiated Resets ......................................................................................11-6
11.4.2 WDT Initiated Resets ..............................................................................................11-6
11.4.3 Reset Operation ......................................................................................................11-6
11.4.4 Power-on Reset ......................................................................................................11-7
CHAPTER 12
SPECIAL OPERATING MODES
12.1 GENERAL.................................................................................................................... 12-1
12.2 POWER CONTROL REGISTER ................................................................................. 12-1
12.2.1 Serial I/O Control Bits .............................................................................................12-1
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8XC251SA, SB, SP, SQ USER’S MANUAL
12.2.2 Power Off Flag ........................................................................................................12-1
12.3 IDLE MODE................................................................................................................. 12-4
12.3.1 Entering Idle Mode ..................................................................................................12-4
12.3.2 Exiting Idle Mode ....................................................................................................12-5
12.4 POWERDOWN MODE ................................................................................................ 12-5
12.4.1 Entering Powerdown Mode .....................................................................................12-6
12.4.2 Exiting Powerdown Mode .......................................................................................12-6
12.5 ON-CIRCUIT EMULATION (ONCE) MODE ................................................................ 12-7
12.5.1 Entering ONCE Mode .............................................................................................12-7
12.5.2 Exiting ONCE Mode ................................................................................................12-7
CHAPTER 13
EXTERNAL MEMORY INTERFACE
13.1 OVERVIEW ................................................................................................................. 13-1
13.2 EXTERNAL BUS CYCLES .......................................................................................... 13-3
13.2.1 Bus Cycle Definitions ..............................................................................................13-3
13.2.2 Nonpage Mode Bus Cycles ....................................................................................13-4
13.2.3 Page Mode Bus Cycles ...........................................................................................13-5
13.3 WAIT STATES............................................................................................................. 13-8
13.4 EXTERNAL BUS CYCLES WITH CONFIGURABLE WAIT STATES.......................... 13-8
13.4.1 Extending RD#/WR#/PSEN# ..................................................................................13-8
13.4.2 Extending ALE ......................................................................................................13-10
13.5 EXTERNAL BUS CYCLES WITH REAL-TIME WAIT STATES................................. 13-10
13.5.1 Real-time WAIT# Enable (RTWE) .........................................................................13-12
13.5.2 Real-time WAIT CLOCK Enable (RTWCE) ...........................................................13-12
13.5.3 Real-time Wait State Bus Cycle Diagrams ............................................................13-12
13.6 CONFIGURATION BYTE BUS CYCLES................................................................... 13-15
13.7 PORT 0 AND PORT 2 STATUS ................................................................................ 13-16
13.7.1 Port 0 and Port 2 Pin Status in Nonpage Mode ....................................................13-16
13.7.2 Port 0 and Port 2 Pin Status in Page Mode ..........................................................13-17
13.8 EXTERNAL MEMORY DESIGN EXAMPLES............................................................ 13-18
13.8.1 Example 1: RD1:0 = 00, 18-bit Bus, External Flash and RAM ..............................13-18
13.8.2 Example 2: RD1:0 = 01, 17-bit Bus, External Flash and RAM ..............................13-20
13.8.3 Example 3: RD1:0 = 01, 17-bit Bus, External RAM ..............................................13-22
13.8.4 Example 4: RD1:0 = 10, 16-bit Bus, External RAM ..............................................13-24
13.8.5 Example 5: RD1:0 = 11, 16-bit Bus, External EPROM and RAM .........................13-26
13.8.5.1 An Application Requiring Fast Access to the Stack .........................................13-26
13.8.5.2 An Application Requiring Fast Access to Data .................................................13-26
13.8.6 Example 6: RD1:0 = 11, 16-bit Bus, External EPROM and RAM .........................13-29
13.8.7 Example 7: RD1:0 = 01, 17-bit Bus, External Flash ..............................................13-30
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CONTENTS
CHAPTER 14
PROGRAMMING AND VERIFYING
NONVOLATILE MEMORY
14.1 GENERAL.................................................................................................................... 14-1
14.1.1 Programming Considerations for On-chip Code Memory .......................................14-2
14.1.2 EPROM Devices .....................................................................................................14-3
14.2 PROGRAMMING AND VERIFYING MODES.............................................................. 14-3
14.3 GENERAL SETUP....................................................................................................... 14-3
14.4 PROGRAMMING ALGORITHM................................................................................... 14-5
14.5 VERIFY ALGORITHM.................................................................................................. 14-6
14.6 PROGRAMMABLE FUNCTIONS ................................................................................ 14-6
14.6.1 On-chip Code Memory ............................................................................................14-7
14.6.2 Configuration Bytes .................................................................................................14-7
14.6.3 Lock Bit System ......................................................................................................14-7
14.6.4 Encryption Array .....................................................................................................14-8
14.6.5 Signature Bytes .......................................................................................................14-8
14.7 VERIFYING THE 83C251SA, SB, SP, SQ (ROM) ...................................................... 14-9
APPENDIX A
INSTRUCTION SET REFERENCE
A.1
A.2
A.3
A.3.1
A.3.2
NOTATION FOR INSTRUCTION OPERANDS............................................................ A-2
OPCODE MAP AND SUPPORTING TABLES ............................................................. A-4
INSTRUCTION SET SUMMARY................................................................................ A-11
Execution Times for Instructions that Access the Port SFRs ................................ A-11
Instruction Summaries .......................................................................................... A-14
APPENDIX B
SIGNAL DESCRIPTIONS
APPENDIX C
REGISTERS
GLOSSARY
INDEX
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8XC251SA, SB, SP, SQ USER’S MANUAL
FIGURES
Figure
Page
2-1
2-2
2-3
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
5-1
5-2
5-3
6-1
6-2
6-3
6-4
6-5
6-6
6-7
7-1
7-2
7-3
7-4
8-1
8-2
8-3
8-4
8-5
8-6
8-7
8-8
8-9
8-10
8-11
Functional Block Diagram of the 8XC251SA, SB, SP, SQ...........................................2-2
The CPU.......................................................................................................................2-5
Clocking Definitions......................................................................................................2-6
Address Spaces for MCS® 251 Microcontrollers.........................................................3-1
Address Spaces for the MCS® 51 Architecture ...........................................................3-3
Address Space Mappings MCS® 51 Architecture to MCS® 251 Architecture.............3-4
8XC251SA, SB, SP, SQ Address Space .....................................................................3-6
Hardware Implementation of the 8XC251SA, SB, SP, SQ Address Space .................3-7
The Register File........................................................................................................3-11
Register File Locations 0–7........................................................................................3-12
Dedicated Registers in the Register File and their Corresponding SFRs...................3-14
Configuration Array (On-chip).......................................................................................4-2
Configuration Array (External)......................................................................................4-3
Configuration Byte UCONFIG0 ....................................................................................4-6
Configuration Byte UCONFIG1 ....................................................................................4-7
Internal/External Address Mapping (RD1:0 = 00 and 01)...........................................4-10
Internal/External Address Mapping (RD1:0 = 10 and 11)...........................................4-11
Binary Mode Opcode Map..........................................................................................4-15
Source Mode Opcode Map ........................................................................................4-15
Word and Double-word Storage in Big Endien Form ...................................................5-3
Program Status Word Register...................................................................................5-18
Program Status Word 1 Register................................................................................5-19
Interrupt Control System ..............................................................................................6-2
Interrupt Enable Register .............................................................................................6-6
Interrupt Priority High Register .....................................................................................6-8
Interrupt Priority Low Register......................................................................................6-8
The Interrupt Process...................................................................................................6-9
Response Time Example #1 ......................................................................................6-11
Response Time Example #2 ......................................................................................6-12
Port 1 and Port 3 Structure...........................................................................................7-3
Port 0 Structure ............................................................................................................7-3
Port 2 Structure ............................................................................................................7-4
Internal Pullup Configurations ......................................................................................7-7
Basic Logic of the Timer/Counters ...............................................................................8-2
Timer 0/1 in Mode 0 and Mode 1 .................................................................................8-4
Timer 0/1 in Mode 2, Auto-Reload................................................................................8-5
Timer 0 in Mode 3, Two 8-bit Timers............................................................................8-6
TMOD: Timer/Counter Mode Control Register.............................................................8-7
TCON: Timer/Counter Control Register .......................................................................8-8
Timer 2: Capture Mode ..............................................................................................8-11
Timer 2: Auto Reload Mode (DCEN = 0)....................................................................8-12
Timer 2: Auto Reload Mode (DCEN = 1)....................................................................8-13
Timer 2: Clock Out Mode............................................................................................8-15
T2MOD: Timer 2 Mode Control Register....................................................................8-16
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CONTENTS
Page
FIGURES
Figure
8-12
9-1
9-2
9-3
9-4
9-5
9-6
9-7
9-8
T2CON: Timer 2 Control Register ..............................................................................8-17
Programmable Counter Array.......................................................................................9-3
PCA 16-bit Capture Mode ............................................................................................9-6
PCA Software Timer and High-speed Output Modes...................................................9-8
PCA Watchdog Timer Mode.......................................................................................9-10
PCA 8-bit PWM Mode ................................................................................................9-11
PWM Variable Duty Cycle..........................................................................................9-12
CMOD: PCA Timer/Counter Mode Register...............................................................9-13
CCON: PCA Timer/Counter Control Register.............................................................9-14
CCAPMx: PCA Compare/Capture Module Mode Registers.......................................9-15
Serial Port Block Diagram ..........................................................................................10-2
SCON: Serial Port Control Register ...........................................................................10-3
Mode 0 Timing............................................................................................................10-5
Data Frame (Modes 1, 2, and 3) ................................................................................10-6
Timer 2 in Baud Rate Generator Mode ....................................................................10-13
Minimum Setup ..........................................................................................................11-1
CHMOS On-chip Oscillator.........................................................................................11-3
External Clock Connection.........................................................................................11-4
External Clock Drive Waveforms................................................................................11-5
Reset Timing Sequence.............................................................................................11-8
Power Control (PCON) Register.................................................................................12-2
Idle and Powerdown Clock Control ............................................................................12-3
Bus Structure in Nonpage Mode and Page Mode......................................................13-1
External Code Fetch (Nonpage Mode).......................................................................13-4
External Data Read (Nonpage Mode) ........................................................................13-4
External Data Write (Nonpage Mode) ........................................................................13-5
External Code Fetch (Page Mode).............................................................................13-6
External Data Read (Page Mode) ..............................................................................13-7
External Data Write (Page Mode)...............................................................................13-7
External Code Fetch (Nonpage Mode, One RD#/PSEN# Wait State) .......................13-9
External Data Write (Nonpage Mode, One WR# Wait State).....................................13-9
9-9
10-1
10-2
10-3
10-4
10-5
11-1
11-2
11-3
11-4
11-5
12-1
12-2
13-1
13-2
13-3
13-4
13-5
13-6
13-7
13-8
13-9
13-10 External Code Fetch (Nonpage Mode, One ALE Wait State)...................................13-10
13-11 Real-time Wait State Control Register (WCON).......................................................13-11
13-12 External Code Fetch/Data Read (Nonpage Mode, RT Wait State) ..........................13-13
13-13 External Data Write (Nonpage Mode, RT Wait State)..............................................13-13
13-14 External Data Read (Page Mode, RT Wait State)....................................................13-14
13-15 External Data Write (Page Mode, RT Wait State)....................................................13-14
13-16 Configuration Byte Bus Cycles.................................................................................13-15
13-17 Bus Diagram for Example 1: 80C251SB in Page Mode...........................................13-18
13-18 Address Space for Example 1..................................................................................13-19
13-19 Bus Diagram for Example 2: 80C251SB in Page Mode...........................................13-20
13-20 Address Space for Example 2..................................................................................13-21
13-21 Bus Diagram for Example 3: 87C251SB/83C251SB in Nonpage Mode ..................13-22
13-22 Address Space for Example 3..................................................................................13-23
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FIGURES
Figure
Page
13-23 Bus Diagram for Example 4: 87C251SB/83C251SB in Nonpage Mode ..................13-24
13-24 Address Space for Example 4..................................................................................13-25
13-25 Bus Diagram for Example 5: 80C251SB in Nonpage Mode.....................................13-27
13-26 Address Space for Examples 5 and 6 ......................................................................13-28
13-27 Bus Diagram for Example 6: 80C251SB in Page Mode...........................................13-29
13-28 Bus Diagram for Example 7: 80C251SB in Page Mode...........................................13-30
14-1
14-2
B-1
Setup for Programming and Verifying Nonvolatile Memory........................................14-5
Program/Verify Bus Cycles.........................................................................................14-6
8XC251SA, SB, SP, SQ 44-pin PLCC Package ......................................................... B-1
8XC251SA, SB, SP, SQ 40-pin PDIP and Ceramic DIP Packages ............................ B-3
B-2
xii
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CONTENTS
Page
TABLES
Table
1-1
2-1
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
4-1
4-2
4-3
4-4
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9
5-10
6-1
6-2
6-3
6-4
6-5
6-6
6-7
7-1
7-2
8-1
8-2
8-3
9-1
9-2
9-3
10-1
10-2
10-3
Intel Application Support Services................................................................................1-7
8XC251SA, SB, SP, SQ Features................................................................................2-3
Address Mappings........................................................................................................3-4
Minimum Times to Fetch Two Bytes of Code...............................................................3-9
Register Bank Selection.............................................................................................3-12
Dedicated Registers in the Register File and their Corresponding SFRs...................3-15
8XC251SA, SB, SP, SQ SFR Map and Reset Values ...............................................3-17
Core SFRs..................................................................................................................3-18
I/O Port SFRs.............................................................................................................3-18
Serial I/O SFRs ..........................................................................................................3-19
Timer/Counter and Watchdog Timer SFRs................................................................3-19
Programmable Counter Array (PCA) SFRs................................................................3-19
External Addresses for Configuration Array.................................................................4-4
Memory Signal Selections (RD1:0) ..............................................................................4-8
RD#, WR#, PSEN# External Wait States...................................................................4-13
Examples of Opcodes in Binary and Source Modes..................................................4-14
Data Types ...................................................................................................................5-2
Notation for Byte Registers, Word Registers, and Dword Registers............................5-3
Addressing Modes for Data Instructions in the MCS® 51 Architecture........................5-6
Addressing Modes for Data Instructions in the MCS® 251 Architecture......................5-7
Bit-addressable Locations..........................................................................................5-11
Addressing Two Sample Bits......................................................................................5-12
Addressing Modes for Bit Instructions........................................................................5-12
Addressing Modes for Control Instructions.................................................................5-13
Compare-conditional Jump Instructions.....................................................................5-14
The Effects of Instructions on the PSW and PSW1 Flags..........................................5-17
Interrupt System Pin Signals ........................................................................................6-1
Interrupt System Special Function Registers ...............................................................6-3
Interrupt Control Matrix.................................................................................................6-4
Level of Priority.............................................................................................................6-7
Interrupt Priority Within Level .......................................................................................6-7
Interrupt Latency Variables ........................................................................................6-13
Actual vs. Predicted Latency Calculations..................................................................6-13
Input/Output Port Pin Descriptions...............................................................................7-1
Instructions for External Data Moves............................................................................7-9
Timer/Counter and Watchdog Timer SFRs..................................................................8-2
External Signals ...........................................................................................................8-3
Timer 2 Modes of Operation.......................................................................................8-15
PCA Special Function Registers (SFRs)......................................................................9-4
External Signals ...........................................................................................................9-4
PCA Module Modes ...................................................................................................9-14
Serial Port Signals......................................................................................................10-1
Serial Port Special Function Registers.......................................................................10-2
Summary of Baud Rates ..........................................................................................10-10
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TABLES
Table
Page
10-4
10-5
10-6
12-1
13-1
13-2
13-3
14-1
14-2
14-3
A-1
A-2
A-3
A-4
A-5
A-6
A-7
A-8
A-9
A-10
A-11
A-12
A-13
A-14
A-15
A-16
A-17
A-18
A-19
A-20
A-21
A-22
A-23
A-24
A-25
A-26
A-27
A-28
B-1
Timer 1 Generated Baud Rates for Serial I/O Modes 1 and 3..................................10-12
Selecting the Baud Rate Generator(s) .....................................................................10-13
Timer 2 Generated Baud Rates ...............................................................................10-14
Pin Conditions in Various Modes................................................................................12-3
External Memory Interface Signals.............................................................................13-2
Bus Cycle Definitions (No Wait States)......................................................................13-3
Port 0 and Port 2 Pin Status In Normal Operating Mode..........................................13-16
Programming and Verifying Modes ............................................................................14-4
Lock Bit Function........................................................................................................14-8
Contents of the Signature Bytes.................................................................................14-9
Notation for Register Operands................................................................................... A-2
Notation for Direct Addresses...................................................................................... A-3
Notation for Immediate Addressing............................................................................. A-3
Notation for Bit Addressing.......................................................................................... A-3
Notation for Destinations in Control Instructions ......................................................... A-3
Instructions for MCS® 51 Microcontrollers.................................................................. A-4
New Instructions for the MCS® 251 Architecture........................................................ A-5
Data Instructions ......................................................................................................... A-6
High Nibble, Byte 0 of Data Instructions...................................................................... A-6
Bit Instructions............................................................................................................. A-7
Byte 1 (High Nibble) for Bit Instructions....................................................................... A-7
PUSH/POP Instructions .............................................................................................. A-8
Control Instructions .................................................................................................... A-8
Displacement/Extended MOVs.................................................................................... A-9
INC/DEC.................................................................................................................... A-10
Encoding for INC/DEC .............................................................................................. A-10
Shifts ......................................................................................................................... A-10
State Times to Access the Port SFRs ....................................................................... A-12
Summary of Add and Subtract Instructions............................................................... A-14
Summary of Compare Instructions............................................................................ A-15
Summary of Increment and Decrement Instructions ................................................. A-16
Summary of Multiply, Divide, and Decimal-adjust Instructions.................................. A-16
Summary of Logical Instructions ............................................................................... A-17
Summary of Move Instructions.................................................................................. A-19
Summary of Exchange, Push, and Pop Instructions................................................. A-22
Summary of Bit Instructions....................................................................................... A-23
Summary of Control Instructions............................................................................... A-24
Flag Symbols............................................................................................................. A-26
PLCC/DIP Pin Assignments Listed by Functional Category........................................ B-2
Signal Descriptions...................................................................................................... B-3
Memory Signal Selections (RD1:0) ............................................................................. B-7
8XC251SA, SB, SP, SQ SFR Map..............................................................................C-2
Core SFRs...................................................................................................................C-3
I/O Port SFRs..............................................................................................................C-3
B-2
B-3
C-1
C-2
C-3
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CONTENTS
Page
TABLES
Table
C-4
C-5
C-6
C-7
Serial I/O SFRs ...........................................................................................................C-4
Timer/Counter and Watchdog Timer SFRs.................................................................C-4
Programmable Counter Array (PCA) SFRs.................................................................C-5
Register File ................................................................................................................C-6
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1
Guide to This Manual
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CHAPTER 1
GUIDE TO THIS MANUAL
This manual describes the 8XC251SA, SB, SP, SQ† embedded microcontroller, which is the first
member of the Intel MCS® 251 microcontroller family. This manual is intended for use by both
software and hardware designers familiar with the principles of microcontrollers.
1.1 MANUAL CONTENTS
This manual contains 14 chapters and 3 appendices. This chapter, Chapter 1, provides an over-
view of the manual. This section summarizes the contents of the remaining chapters and appen-
dices. The remainder of this chapter describes notational conventions and terminology used
throughout the manual and provides references to related documentation.
Chapter 2, “Architectural Overview” — provides an overview of device hardware. It covers
core functions (pipelined CPU, clock and reset unit, and on-chip memory) and on-chip peripher-
als (timer/counters, watchdog timer, programmable counter array, and serial I/O port.)
Chapter 3, “Address Spaces” — describes the three address spaces of the MCS 251 microcon-
troller: memory address space, special function register (SFR) space, and the register file. It also
provides a map of the SFR space showing the location of the SFRs and their reset values and ex-
plains the mapping of the address spaces of the MCS® 51 architecture into the address spaces of
the MCS 251 architecture.
Chapter 4, “Device Configuration” — describes microcontroller features that are configured at
device reset, including the external memory interface (the number of external address bits, the
number of wait states, memory regions for asserting RD#, WR#, and PSEN#, page mode), binary/
source opcodes, interrupt mode, and the mapping of a portion of on-chip code memory to data
memory. It describes the configuration bytes and how to program them for the desired configu-
ration. It also describes how internal memory space maps into external memory.
Chapter 5, “Programming” — provides an overview of the instruction set. It describes each in-
struction type (control, arithmetic, logical, etc.) and lists the instructions in tabular form. This
chapter also discusses the addressing modes, bit instructions, and the program status words.
Appendix A provides a detailed description of each instruction.
Chapter 6, “Interrupt System” — describes the 8XC251Sx interrupt circuitry which provides
a TRAP instruction interrupt and seven maskable interrupts: two external interrupts, three timer
interrupts, a PCA interrupt, and a serial port interrupt. This chapter also discusses the interrupt
priority scheme, interrupt enable, interrupt processing, and interrupt response time.
†
The 8XC251SA, SB, SP, SQ products are also collectively referred to as 8XC251Sx.
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Chapter 7, “Input/Output Ports” — describes the four 8-bit I/O ports (ports 0–3) and discusses
their configuration for general-purpose I/O, external memory accesses (ports 0, 2), and alterna-
tive special functions.
Chapter 8, “Timer/Counters and WatchDog Timer” — describes the three on-chip tim-
er/counters and discusses their application. This chapter also provides instructions for using the
hardware watchdog timer (WDT) and describes the operation of the WDT during the idle and
powerdown modes.
Chapter 9, “Programmable Counter Array” — describes the PCA on-chip peripheral and ex-
plains how to configure it for general-purpose applications (timers and counters) and special ap-
plications (programmable WDT and pulse-width modulator).
Chapter 10, “Serial I/O Port” — describes the full-duplex serial I/O port and explains how to
program it to communicate with external peripherals. This chapter also discusses baud rate gen-
eration, framing error detection, multiprocessor communications, and automatic address recog-
nition.
Chapter 11, “Minimum Hardware Setup” — describes the basic requirements for operating
the 8XC251Sx in a system. It also discusses on-chip and external clock sources and describes de-
vice resets, including power-on reset.
Chapter 12, “Special Operating Modes” — provides an overview of the idle, powerdown, and
on-circuit emulation (ONCE) modes and describes how to enter and exit each mode. This chapter
also describes the power control (PCON) special function register and lists the status of the device
pins during the special modes and reset (Table 12-1).
Chapter 13, “External Memory Interface” —describes the external memory signals and bus
cycles and provides examples of external memory design. It provides waveform diagrams for the
bus cycles, bus cycles with wait states, and the configuration byte bus cycles. It also provides bus
cycle diagrams with AC timing symbols and definitions of the symbols.
Chapter 14, “Programming and Verifying Nonvolatile Memory” — provides instructions for
programming and verifying on-chip code memory, configuration bytes, signature bytes, lock bits
and the encryption array.
Appendix A, “Instruction Set Reference” — provides reference information for the instruction
set. It describes each instruction; defines the bits in the program status word registers (PSW,
PSW1); shows the relationships between instructions and PSW flags; and lists hexadecimal op-
codes, instruction lengths, and execution times. Chapter 5, “Programming,” includes a general
discussion of the instruction set.
1-2
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Appendix B, “Signal Descriptions” — describes the function(s) of each device pin. Descrip-
tions are listed alphabetically by signal name. This appendix also provides a list of the signals
grouped by functional category.
Appendix C, “Registers” — accumulates, for convenient reference, copies of the register defi-
nition figures that appear throughout the manual.
A glossary has been included for your convenience.
1.2 NOTATIONAL CONVENTIONS AND TERMINOLOGY
The following notations and terminology are used in this manual. The Glossary defines other
terms with special meanings.
#
The pound symbol (#) has either of two meanings, depending on the
context. When used with a signal name, the symbol means that the
signal is active low. When used in an instruction, the symbol prefixes
an immediate value in immediate addressing mode.
italics
Italics identify variables and introduce new terminology. The context
in which italics are used distinguishes between the two possible
meanings.
Variables in registers and signal names are commonly represented by
x and y, where x represents the first variable and y represents the
second variable. For example, in register Px.y, x represents the
variable [1–4] that identifies the specific port, and y represents the
register bit variable [7:0]. Variables must be replaced with the correct
values when configuring or programming registers or identifying
signals.
XXXX
Uppercase X (no italics) represents an unknown value or a “don’t
care” state or condition. The value may be either binary or
hexadecimal, depending on the context. For example, 2XAFH (hex)
indicates that bits 11:8 are unknown; 10XX in binary context
indicates that the two LSBs are unknown.
Assert and Deassert
The terms assert and deassert refer to the act of making a signal
active (enabled) and inactive (disabled), respectively. The active
polarity (high/low) is defined by the signal name. Active-low signals
are designated by a pound symbol (#) suffix; active-high signals have
no suffix. To assert RD# is to drive it low; to assert ALE is to drive it
high; to deassert RD# is to drive it high; to deassert ALE is to drive it
low.
1-3
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Instructions
Instruction mnemonics are shown in upper case to avoid confusion.
When writing code, either upper case or lower case may be used.
Logic 0 (Low)
An input voltage level equal to or less than the maximum value of
VIL or an output voltage level equal to or less than the maximum
value of VOL. See data sheet for values.
Logic 1 (High)
Numbers
An input voltage level equal to or greater than the minimum value of
VIH or an output voltage level equal to or greater than the minimum
value of VOH. See data sheet for values.
Hexadecimal numbers are represented by a string of hexadecimal
digits followed by the character H. Decimal and binary numbers are
represented by their customary notations. That is, 255 is a decimal
number and 1111 1111 is a binary number. In some cases, the letter B
is added for clarity.
Register Bits
Bit locations are indexed by 7:0 for byte registers, 15:0 for word
registers, and 31:0 for double-word (dword) registers, where bit 0 is
the least-significant bit and 7, 15, or 31 is the most-significant bit. An
individual bit is represented by the register name, followed by a
period and the bit number. For example, PCON.4 is bit 4 of the
power control register. In some discussions, bit names are used. For
example, the name of PCON.4 is POF, the power-off flag.
Register Names
Reserved Bits
Set and Clear
Signal Names
Register names are shown in upper case. For example, PCON is the
power control register. If a register name contains a lowercase
character, it represents more than one register. For example,
CCAPMx represents the five registers: CCAPM0 through CCAPM4.
Some registers contain reserved bits. These bits are not used in this
device, but they may be used in future implementations. Do not write
a “1” to a reserved bit. The value read from a reserved bit is indeter-
minate.
The terms set and clear refer to the value of a bit or the act of giving
it a value. If a bit is set, its value is “1;” setting a bit gives it a “1”
value. If a bit is clear, its value is “0;” clearing a bit gives it a “0”
value.
Signal names are shown in upper case. When several signals share a
common name, an individual signal is represented by the signal name
followed by a number. Port pins are represented by the port abbrevi-
ation, a period, and the pin number (e.g., P0.0, P0.1). A pound
symbol (#) appended to a signal name identifies an active-low signal.
1-4
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Units of Measure
The following abbreviations are used to represent units of measure:
A
amps, amperes
DCV
direct current volts
Kbyte kilobytes
KΩ
kilo-ohms
mA
milliamps, milliamperes
Mbyte megabytes
MHz
ms
mW
ns
megahertz
milliseconds
milliwatts
nanoseconds
picofarads
pF
W
watts
V
volts
µA
µF
µs
microamps, microamperes
microfarads
microseconds
microwatts
µW
1.3 RELATED DOCUMENTS
The following documents contain additional information that is useful in designing systems that
incorporate the 8XC251Sx microcontroller. To order documents, please call Intel Literature Ful-
fillment (1-800-548-4725 in the U.S. and Canada; +44(0) 793-431155 in Europe).
Embedded Microcontrollers
Embedded Processors
Embedded Applications
Packaging
Order Number 270646
Order Number 272396
Order Number 270648
Order Number 240800
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1.3.1 Data Sheet
The data sheet is included in Embedded Microcontrollers and is also available individually.
8XC251SA, SB, SP, SQ High-Performance CHMOS Microcontroller
(Commercial/Express)
Order Number 272783
1.3.2 Application Notes
The following application notes apply to the MCS 251 microcontroller.
AP-125, Designing Microcontroller Systems
for Electrically Noisy Environments
Order Number 210313
AP-155, Oscillators for Microcontrollers
Order Number 230659
Order Number 272670
AP-708, Introducing the MCS® 251 Microcontroller
—the 8XC251SB
AP-709, Maximizing Performance Using MCS® 251 Microcontroller
—Programming the 8XC251SB
Order Number 272671
AP-710, Migrating from the MCS® 51 Microcontroller to the MCS 251 Order Number 272672
Microcontroller (8XC251SB)—Software and Hardware
Considerations
The following MCS 51 microcontroller application notes also apply to the MCS 251 microcon-
troller.
AP70, Using the Intel MCS® 51 Boolean Processing Capabilities
AP-223, 8051 Based CRT Terminal Controller
AP-252, Designing With the 80C51BH
Order Number 203830
Order Number 270032
Order Number 270068
Order Number 270622
Order Number 270490
Order Number 270609
Order Number 272319
AP-425, Small DC Motor Control
AP-410, Enhanced Serial Port on the 83C51FA
AP-415, 83C51FA/FB PCA Cookbook
AP-476, How to Implement I2C Serial Communication
Using Intel MCS® 51 Microcontrollers
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1.4 APPLICATION SUPPORT SERVICES
You can get up-to-date technical information from a variety of electronic support systems: the
World Wide Web, CompuServe, the FaxBack* service, and Intel’s Brand Products and Applica-
tions Support bulletin board service (BBS). These systems are available 24 hours a day, 7 days a
week, providing technical information whenever you need it.
In the U.S. and Canada, technical support representatives are available to answer your questions
between 5 a.m. and 5 p.m. Pacific Standard Time (PST). Outside the U.S. and Canada, please con-
tact your local distributor. You can order product literature from Intel literature centers and sales
offices.
Table 1-1 lists the information you need to access these services.
Table 1-1. Intel Application Support Services
Service
U.S. and Canada
Asia-Pacific and Japan
Europe
World Wide Web URL: http://www.intel.com/ URL: http://www.intel.com/ URL: http://www.intel.com/
CompuServe
FaxBack*
go intel
go intel
go intel
800-525-3019
503-264-6835
916-356-3105
+44(0)1793-496646
BBS
503-264-7999
916-356-3600
503-264-7999
916-356-3600
+44(0)1793-432955
Help Desk
Literature
800-628-8686
916-356-7999
Please contact your local
distributor.
Please contact your local
distributor.
800-548-4725
708-296-9333
+44(0)1793-431155 England
+44(0)1793-421777 France
+44(0)1793-421333 Germany
+81(0)120 47 88 32
1.4.1 World Wide Web
We offer a variety of technical and product information through the World Wide Web (URL: ht-
tp://www.intel.com/design/mcs96). Also visit Intel’s Web site for financials, history, and news.
1.4.2 CompuServe Forums
Intel maintains several CompuServe forums that provide a means for you to gather information,
share discoveries, and debate issues. Type “go intel” for access. The INTELC forum is set up to
support designers using various Intel components. For information about CompuServe access and
service fees, call CompuServe at 1-800-848-8199 (U.S.) or 614-529-1340 (outside the U.S.).
1-7
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1.4.3 FaxBack Service
The FaxBack service is an on-demand publishing system that sends documents to your fax ma-
chine. You can get product announcements, change notifications, product literature, device char-
acteristics, design recommendations, and quality and reliability information from FaxBack 24
hours a day, 7 days a week.
Think of the FaxBack service as a library of technical documents that you can access with your
phone. Just dial the telephone number and respond to the system prompts. After you select a doc-
ument, the system sends a copy to your fax machine.
Each document is assigned an order number and is listed in a subject catalog. The first time you
use FaxBack, you should order the appropriate subject catalogs to get a complete listing of doc-
ument order numbers. Catalogs are updated twice monthly. In addition, daily update catalogs list
the title, status, and order number of each document that has been added, revised, or deleted dur-
ing the past eight weeks. The daily update catalogs are numbered with the subject catalog number
followed by a zero. For example, for the complete microcontroller and flash catalog, request doc-
ument number 2; for the daily update to the microcontroller and flash catalog, request document
number 20.
The following catalogs and information are available at the time of publication:
1. Solutions OEM subscription form
2. Microcontroller and flash catalog
3. Development tools catalog
4. Systems catalog
5. Multimedia catalog
6. Multibus and iRMX® software catalog and BBS file listings
7. Microprocessor, PCI, and peripheral catalog
8. Quality and reliability and change notification catalog
9. iAL (Intel Architecture Labs) technology catalog
1.4.4 Bulletin Board System (BBS)
Intel’s Brand Products and Applications Support bulletin board system (BBS) lets you download
files to your PC. The BBS has the latest ApBUILDER software, hypertext manuals and
datasheets, software drivers, firmware upgrades, application notes and utilities, and quality and
reliability data.
1-8
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Any customer with a PC and modem can access the BBS. The system provides automatic config-
uration support for 1200- through 19200-baud modems. Use these modem settings: no parity, 8
data bits, and 1 stop bit (N, 8, 1).
To access the BBS, just dial the telephone number (see Table 1-1 on page 1-7) and respond to the
system prompts. During your first session, the system asks you to register with the system oper-
ator by entering your name and location. The system operator will set up your access account
within 24 hours. At that time, you can access the files on the BBS.
NOTE
In the U.S. and Canada, you can get a BBS user’s guide, a master list of BBS
files, and lists of FaxBack documents by calling 1-800-525-3019. Use these
modem settings: no parity, 8 data bits, and 1 stop bit (N, 8, 1).
1-9
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2
Architectural
Overview
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CHAPTER 2
ARCHITECTURAL OVERVIEW
The 8XC251Sx is the first member of the MCS® 251 microcontroller family. This family of 8-bit
microcontrollers is a high-performance upgrade of the widely-used MCS 51® microcontrollers.
It extends features and performance while maintaining binary-code compatibility and pin com-
cal control applications for the 8XC251Sx include copiers, scanners, CD ROMs, and tape drives.
It is also well suited for communications applications, such as phone terminals, business/feature
phones, and phone switching and transmission systems.
This manual covers all memory options of the 8XC251SA, SB, SP, SQ and these options are listed
in Table 2-1.
All MCS 251 microcontrollers share a set of common features:
• 24-bit linear addressing and up to 16 Mbytes of memory
• a register-based CPU with registers accessible as bytes, words, and double words
• a page mode for accelerating external instruction fetches
• an instruction pipeline
• an enriched instruction set, including 16-bit arithmetic and logic instructions
• a 64-Kbyte extended stack space
• a minimum instruction-execution time of two clocks (vs. 12 clocks for MCS 51 microcon-
trollers)
• three types of wait state solutions: real-time, RD#/WR#/PSEN#, and ALE
• binary-code compatibility with MCS 51 microcontrollers
Several benefits are derived from these features:
• preservation of code written for MCS 51 microcontrollers
• a significant increase in core execution speed in comparison with MCS 51 microcontrollers
at the same clock rate
• support for larger programs and more data
• increased efficiency for code written in C
• dynamic bus control through real-time wait state operations
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I/O Ports and
Peripheral Signals
System Bus and I/O Ports
P0.7:0
P1.7:0
P2.7:0
P3.7:0
Code
OTPROM/ROM
8 Kbytes
or
Data RAM
512 Bytes
or
Port 0
Drivers
Port 2
Drivers
Port 1
Drivers
Port 3
Drivers
1024 Bytes
16 Kbytes
Memory Data (16)
Watchdog
Timer
Memory Address (16)
Peripheral
Interface
Bus Interface
Timer/
Counters
Code Bus (16)
Code Address (24)
Interrupt
Handler
Instruction Sequencer
PCA
SRC1 (8)
SRC2 (8)
Serial I/O
Clock
&
Reset
Data
Register
File
Memory
Interface
ALU
Peripherals
DST (16)
®
MCS 251 Microcontroller Core
Clock & Reset
8XC251SA/SB/SP/SQ Microcontroller
A4214-01
Figure 2-1. Functional Block Diagram of the 8XC251SA, SB, SP, SQ
2-2
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ARCHITECTURAL OVERVIEW
2.1 8XC251SA, SB, SP, SQ ARCHITECTURE
Figure 2-1 is a functional block diagram of the 8XC251SA, SB, SP, SQ. The core, which is com-
mon to all MCS 251 microcontrollers, is described in section 2.2, “MCS 251 Microcontroller
Core.” Each microcontroller type in the family has its own on-chip peripherals, I/O ports, external
system bus, size of on-chip RAM, and type and size of on-chip program memory. Table 2-1 lists
the distinguishing features of the product.
The 8XC251Sx peripherals include a dedicated watchdog timer, a timer/counter unit, a program-
mable counter array (PCA), and a serial I/O unit. The 8XC251Sx has four 8-bit I/O ports, P0–P3.
Each port pin can be individually programmed as a general I/O signal or as a special-function sig-
nal that supports the external bus or one of the on-chip peripherals. Ports P0 and P2 comprise a
16-line external bus, which transmits a 16-bit address multiplexed with 8 data bits. (You can also
configure the 8XC251Sx to have a 17-bit or an 18-bit external address bus. See section 4.5, “Con-
figuring the External Memory Interface.” Ports P1 and P3 carry bus-control and peripheral sig-
nals.
Table 2-1. 8XC251SA, SB, SP, SQ Features
On-chip Memory
Device
Number
OTPROM/EPROM
(Kbytes)
ROM
(Kbytes)
RAM
(Bytes)
80C251SB
80C251SQ
83C251SA
83C251SB
83C251SP
83C251SQ
87C251SA
87C251SB
87C251SP
87C251SQ
0
0
0
0
1024
512
0
8
1024
1024
512
0
16
8
0
0
16
0
512
8
1024
1024
512
16
8
0
0
16
0
512
Common features:
Address space
512 Kbytes
External Address bus 16-bit, 17-bit, or 18-bit
Register file
I/O lines
40 bytes
32
Interrupt sources
11
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The 8XC251Sx has two power-saving modes. In idle mode, the CPU clock is stopped, while
clocks to the peripherals continue to run. In powerdown mode, the on-chip oscillator is stopped,
and the chip enters a static state. An enabled interrupt or a hardware reset can bring the chip back
to its normal operating mode from idle or powerdown. See Chapter 12, “Special Operating
Modes,” for details on the power-saving modes.
MCS 251 microcontrollers use an instruction set that has been expanded to include new opera-
tions, addressing modes, and operands. Many instructions can operate on 8-, 16-, or 32-bit oper-
ands, providing easier and more efficient programming in high-level languages such as C.
Additional new features include the TRAP instruction, a new displacement addressing mode, and
several conditional jump instructions. Chapter 5, “Programming,” describes the instruction set
and compares it with the instruction set for MCS 51 microcontrollers.
You can configure the 8XC251Sx to run in binary mode or source mode. Either mode executes
all of the MCS 51 architecture instructions and all of the MCS 251 architecture instructions. How-
ever, source mode is more efficient for MCS 251 architecture instructions, and binary mode is
more efficient for MCS 51 architecture instructions. In binary mode, object code for an MCS 51
microcontroller runs on the 8XC251Sx without recompiling.
If a system was originally developed using an MCS 51 microcontroller, and if the new
8XC251Sx-based system will run code written for the MCS 51 microcontroller, performance will
be better with the 8XC251Sx running in binary mode. Object code written for the MCS 51 mi-
crocontroller runs faster on the 8XC251Sx.
However, if most of the code is rewritten using the new instruction set, performance will be better
with the 8XC251Sx running in source mode. In this case the 8XC251Sx can run significantly fast-
er than the MCS 51 microcontroller. See Chapter 4, “Device Configuration,” for a discussion of
binary mode and source mode.
MCS 251 microcontrollers store both code and data in a single, linear 16-Mbyte memory space.
The 8XC251Sx can address up to 256 Kbytes of external memory. The special function registers
(SFRs) and the register file have separate address spaces. See Chapter 3, “Address Spaces,” for a
description.
2.2 MCS 251 MICROCONTROLLER CORE
The MCS 251 microcontroller core contains the CPU, the clock and reset unit, the interrupt han-
dler, the bus interface, and the peripheral interface. The CPU contains the instruction sequencer,
ALU, register file, and data memory interface.
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ARCHITECTURAL OVERVIEW
2.2.1 CPU
Figure 2-2 is a functional block diagram of the CPU (central processor unit). The 8XC251Sx
fetches instructions from on-chip code memory two bytes at a time, or from external memory in
single bytes. The instructions are sent over the 16-bit code bus to the execution unit. You can con-
figure the 8XC251Sx to operate in page mode for accelerated instruction fetches from external
memory. In page mode, if an instruction fetch is to the same 256-byte “page” as the previous
fetch, the fetch requires one state (two clocks) rather than two states (four clocks).
The 8XC251Sx register file has forty registers, which can be accessed as bytes, words, and double
words. As in the MCS 51 architecture, registers 0–7 consist of four banks of eight registers each,
where the active bank is selected by the program status word (PSW) for fast context switches.
The 8XC251Sx is a single-pipeline machine. When the pipeline is full and code is executing from
on-chip code memory, an instruction is completed every state time. When the pipeline is full and
code is executing from external memory (with no wait states and no extension of the ALE signal),
an instruction is completed every two state times.
Code Address
Code Bus
16
24
Instruction Sequencer
Interrupt
Handler
8
8
SRC1
SRC2
Data Bus
8
Data
Memory
Interface
Register
File
ALU
24
Data Address
16
DST
Figure 2-2. The CPU
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2.2.2 Clock and Reset Unit
The timing source for the 8XC251Sx can be an external oscillator or an internal oscillator with
an external crystal/resonator (see Chapter 11, “Minimum Hardware Setup”). The basic unit of
time in MCS 251 microcontrollers is the state time (or state), which is two oscillator periods (see
Figure 2-3). The state time is divided into phase 1 and phase 2.
The 8XC251Sx peripherals operate on a peripheral cycle, which is six state times. (This periph-
eral cycle is particular to the 8XC251Sx and not a characteristic of the MCS 251 architecture.) A
one-clock interval in a peripheral cycle is denoted by its state and phase. For example, the PCA
timer is incremented once each peripheral cycle in phase 2 of state 5 (denoted as S5P2).
The reset unit places the 8XC251Sx into a known state. A chip reset is initiated by asserting the
RST pin or allowing the watchdog timer to time out (see Chapter 11, “Minimum Hardware Set-
up”).
Phase 1
P1
Phase 2
P2
XTAL1
TOSC
2 TOSC = State Time
State 1
P2
State 2
P2
State 3
P2
State 6
P2
P1
State 4
P2
State 5
P2
P1
P1
P1
P1
P1
XTAL1
Peripheral Cycle
A2604-02
Figure 2-3. Clocking Definitions
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ARCHITECTURAL OVERVIEW
2.2.3 Interrupt Handler
The interrupt handler can receive interrupt requests from eleven sources: seven maskable sources
and the TRAP instruction. When the interrupt handler grants an interrupt request, the CPU dis-
continues the normal flow of instructions and branches to a routine that services the source that
requested the interrupt. You can enable or disable the interrupts individually (except for TRAP)
and you can assign one of four priority levels to each interrupt. See Chapter 6, “Interrupt System,”
for a detailed description.
2.2.4 On-chip Code Memory
For 83C251SA (ROM) and 87C251SA (OTPROM/EPROM) devices, memory locations
FF:0000H–FF:1FFFH are implemented with 8-Kbytes of on-chip code memory. For 83C251SB
and 87C251SB devices, memory locations FF:0000H–FF:3FFFH are implemented with 16-
Kbytes of on-chip code memory.
Following a reset, the first instruction is fetched from location FF:0000H. For 80C251Sx (no
ROM/OTPROM/EPROM) devices, location FF:0000H is always in external memory.
2.2.5 On-chip RAM
The 8XC251SA and 8XC251SB have 1-Kbyte of on-chip data RAM at locations 20H–41FH. The
8XC251SP and 8XC251SQ have 512 bytes of on-chip data RAM at locations 20H–21FH. These
RAM locations can be accessed with direct, indirect, and displacement addressing. Ninety-six of
these locations (20H–7FH) are bit addressable. An additional 32 bytes of on-chip RAM (00H–
1FH) provide storage for the four banks of registers R0–R7.
2.3 ON-CHIP PERIPHERALS
The on-chip peripherals, which lie outside the core, perform specialized functions. Software ac-
cesses the peripherals via their special function registers (SFRs). The 8XC251Sx has four periph-
erals: the watchdog timer, the timer/counters, the programmable counter array (PCA), and the
serial I/O port.
2.3.1 Timer/Counters and Watchdog Timer
The timer/counter unit has three timer/counters, which can be clocked by the oscillator (for timer
operation) or by an external input (for counter operation). You can set up an 8-bit, 13-bit, or 16-
bit timer/counter, and you can program them for special applications, such as capturing the time
of an event on an external pin, outputting a programmable clock signal on an external pin, or gen-
erating a baud rate for the serial I/O port. Timer/counter events can generate interrupt requests.
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The watchdog timer is a circuit that automatically resets the 8XC251Sx in the event of a hardware
or software upset. When enabled by software, the watchdog timer begins running, and unless
software intervenes, the timer reaches a maximum count and initiates a chip reset. In normal op-
eration, software periodically clears the timer register to prevent the reset. If an upset occurs and
software fails to clear the timer, the resulting chip reset disables the timer and returns the system
to a known state. The watchdog and the timer/counters are described in Chapter 8, “Tim-
er/Counters and WatchDog Timer.”
2.3.2 Programmable Counter Array (PCA)
The programmable counter array (PCA) has its own timer and five capture/compare modules that
perform several functions: capturing (storing) the timer value in response to a transition on an in-
put pin; generating an interrupt request when the timer matches a stored value; toggling an output
pin when the timer matches a stored value; generating a programmable PWM (pulse width mod-
ulator) signal on an output pin; and serving as a software watchdog timer. Chapter 9, “Program-
mable Counter Array,” describes this peripheral in detail.
2.3.3 Serial I/O Port
The serial I/O port provides one synchronous and three asynchronous communication modes.
The synchronous mode (mode 0) is half-duplex: the serial port outputs a clock signal on one pin
and transmits or receives data on another pin.
The asynchronous modes (modes 1–3) are full-duplex (i.e., the port can send and receive simul-
taneously). Mode 1 uses a serial frame of 10 bits: a start bit, 8 data bits, and a stop bit. The baud
rate is generated by overflow of timer 1 or timer 2. Modes 2 and 3 use a serial frame of 11 bits: a
start bit, eight data bits, a programmable ninth data bit, and a stop bit. The ninth bit can be used
for parity checking or to specify that the frame contains an address and data. In mode 2, you can
use a baud rate of 1/32 or 1/64 of the oscillator frequency. In mode 3, you can use the overflow
from timer 1 or timer 2 to determine the baud rate.
In its synchronous modes (modes 1–3) the serial port can operate as a slave in an environment
where multiple slaves share a single serial line. It can accept a message intended for itself or a
message that is being broadcast to all of the slaves, and it can ignore a message sent to another
slave.
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3
Address Spaces
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CHAPTER 3
ADDRESS SPACES
MCS® 251 microcontrollers have three address spaces: a memory space, a special function reg-
ister (SFR) space, and a register file. This chapter describes these address spaces as they apply to
all MCS 251 microcontrollers and to the 8XC251Sx in particular. It also discusses the compati-
bility of the MCS 251 architecture and the MCS® 51 architecture in terms of their address spaces.
3.1 ADDRESS SPACES FOR MCS® 251 MICROCONTROLLERS
Figure 3-1 shows the memory space, the SFR space, and the register file for MCS 251 microcon-
trollers. (The address spaces are depicted as being eight bytes wide with addresses increasing
from left to right and from bottom to top.)
Memory Address Space
16 Mbytes
FF:FFFFH
SFR Space
512 Bytes
S:1FFH
S:007H
S:000H
Register File
64 Bytes
63
7
00:0000H
0
00:0007H
A4100-01
Figure 3-1. Address Spaces for MCS® 251 Microcontrollers
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It is convenient to view the unsegmented, 16-Mbyte memory space as consisting of 256 64-Kbyte
regions, numbered 00: to FF:.
NOTE
The memory space in the MCS 251 architecture is unsegmented. The 64-
Kbyte “regions” 00:, 01:, ..., FF: are introduced only as a convenience for
discussions. Addressing in the MCS 251 architecture is linear; there are no
segment registers.
MCS 251 microcontrollers can have up to 64 Kbytes of on-chip code memory in region FF:. On-
chip data RAM begins at location 00:0000H. The first 32 bytes (00:0000H–00:001FH) provide
storage for a part of the register file. On-chip, general-purpose data RAM begins at 00:0020H.
The register file has its own address space (Figure 3-1). The 64 locations in the register file are
numbered decimally from 0 to 63. Locations 0–7 represent one of four switchable register banks,
each having 8 registers. The 32 bytes required for these banks occupy locations 00:0000H–
00:001FH in the memory space. Register file locations 8–63 do not appear in the memory space.
file.
The SFR space can accommodate up to 512 8-bit special function registers with addresses
S:000H–S:1FFH. Some of these locations may be unimplemented in a particular device. In the
MCS 251 architecture, the prefix “S:” is used with SFR addresses to distinguish them from the
memory space addresses 00:0000H–00:01FFH. See “Special Function Registers (SFRs)” on page
3-16 for details on the SFR space.
3.1.1 Compatibility with the MCS® 51 Architecture
The address spaces in the MCS 51 architecture† are mapped into the address spaces in the MCS
251 architecture. This mapping allows code written for MCS 51 microcontrollers to run on MCS
251 microcontrollers. (Chapter 5, “Programming,” discusses the compatibility of the two instruc-
tion sets.)
Figure 3-2 shows the address spaces for the MCS 51 architecture. Internal data memory locations
00H–7FH can be addressed directly and indirectly. Internal data locations 80H–FFH can only be
addressed indirectly. Directly addressing these locations accesses the SFRs. The 64-Kbyte code
memory has a separate memory space. Data in the code memory can be accessed only with the
MOVC instruction. Similarly, the 64-Kbyte external data memory can be accessed only with the
MOVX instruction.
†
MCS®51 Microcontroller Family User’s Manual
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ADDRESS SPACES
The register file (registers R0–R7) comprises four switchable register banks, each having eight
registers. The 32 bytes required for the four banks occupy locations 00H–1FH in the on-chip data
memory.
Figure 3-3 shows how the address spaces in the MCS 51 architecture map into the address spaces
in the MCS 251 architecture; details are listed in Table 3-1.
The 64-Kbyte code memory for MCS 51 microcontrollers maps into region FF: of the memory
space for MCS 251 microcontrollers. Assemblers for MCS 251 microcontrollers assemble code
for MCS 51 microcontrollers into region FF:, and data accesses to code memory are directed to
this region. The assembler also maps the interrupt vectors to region FF:. This mapping is trans-
parent to the user; code executes just as before, without modification.
FFFFH
Code
(MOVC)
0000H
FFFFH
Register File
R0
R7
External Data
(MOVX)
0000H
FFH
7FH
FFH
Internal Data
(indirect)
SFRs
(direct)
80H
80H
00H
Internal Data
(direct, indirect)
A4139-01
®
Figure 3-2. Address Spaces for the MCS 51 Architecture
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Memory Address Space
16 Mbytes
FFFFH
SFR Space
512 Bytes
MCS 51 Architecture
Code Memory
S:1FFH
0000H
FF:0000H
S:100H
S:000H
FFH
MCS 51 Architecture
SFRs
80H
S:07FH
02:0000H
01:0000H
FFFFH
MCS 51 Architecture
External Data Memory
0000H
00H
Register File
64 Bytes
63
FFH
MCS 51 Architecture
Internal Data Memory
8
0
MCS 51 Architecture R. F.
0
7
00:0000H
A4133-01
®
®
Figure 3-3. Address Space Mappings MCS 51 Architecture to MCS 251 Architecture
Table 3-1. Address Mappings
®
®
MCS 51 Architecture
MCS 251 Architecture
Memory Type
Data
Addressing
Size
Location
Location
Indirect using
MOVC instr.
Code
64 Kbytes
64 Kbytes
0000H–FFFFH
0000H–FFFFH
FF:0000H–FF:FFFFH
01:0000H–01:FFFFH
Indirect using
MOVX instr.
External Data
Internal Data
128 bytes
128 bytes
128 bytes
8 bytes
00H–7FH
80H–FFH
S:80H–S:FFH
R0–R7
Direct, Indirect
Indirect
00:0000H–00:007FH
00:0080H–00:00FFH
S:080H–S:0FFH
R0–R7
SFRs
Direct
Register File
Register
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ADDRESS SPACES
The 64-Kbyte external data memory for MCS 51 microcontrollers is mapped into the memory
region specified by bits 16–23 of the data pointer DPX, i.e., DPXL. DPXL is accessible as register
file location 57 and also as the SFR at S:084H (see “Dedicated Registers” on page 3-13). The re-
set value of DPXL is 01H, which maps the external memory to region 01: as shown in Figure 3-3.
You can change this mapping by writing a different value to DPXL. A mapping of the MCS 51
microcontroller external data memory into any 64-Kbyte memory region in the MCS 251 archi-
tecture provides complete run-time compatibility because the lower 16 address bits are identical
in the two address spaces.
The 256 bytes of on-chip data memory for MCS 51 microcontrollers (00H-FFH) are mapped to
addresses 00:0000H-00:00FFH to ensure complete run-time compatibility. In the MCS 51 archi-
per 128 bytes are accessible by indirect addressing only. In the MCS 251 architecture, all
locations in region 00: are accessible by direct, indirect, and displacement addressing (see
“8XC251SA, SB, SP, SQ Memory Space” on page 3-5).
The 128-byte SFR space for MCS 51 microcontrollers is mapped into the 512-byte SFR space of
the MCS 251 architecture starting at address S:080H, as shown in Figure 3-3. This provides com-
plete compatibility with direct addressing of MCS 51 microcontroller SFRs (including bit ad-
dressing). The SFR addresses are unchanged in the new architecture. In the MCS 251
the register file for high performance. However, to maintain compatibility, they are also mapped
into the SFR space at the same addresses as in the MCS 51 architecture.
3.2 8XC251SA, SB, SP, SQ MEMORY SPACE
Figure 3-4 shows the logical memory space for the 8XC251Sx microcontroller. The usable mem-
ory space of the 8XC251Sx consists of four 64-Kbyte regions: 00:, 01:, FE:, and FF:. Code can
execute from all four regions; code execution begins at FF:0000H. Regions 02:–FD: are reserved.
Reading a location in the reserved area returns an unspecified value. Software can execute a write
to the reserved area, but nothing is actually written.
All four regions of the memory space are available at the same time. The maximum number of
external address lines is 18, which limits external memory to a maximum of four regions (256
Kbytes). See “Configuring the External Memory Interface” on page 4-8 and “External Memory
Design Examples” on page 13-18.
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Memory Address Space
16 Mbytes
FF:FFFFH
FF:0000H
FE:0000H
FE:FFFFH
Indirect and
Displacement
Addressing
(16 Mbytes)
Regions 02–FD
are Reserved
01:FFFFH
00:FFFFH
01:0000H
00:0080H
Direct Addressing
(64 Kbytes)
Bit Addressing
(96 Bytes)
00:007FH
00:001FH
00:0020H
00:0000H
Register Addressing
(32 Bytes)
A4385-01
Figure 3-4. 8XC251SA, SB, SP, SQ Address Space
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ADDRESS SPACES
†
FF:FFF7H
FE:FFFFH
External Memory
On-chip ROM
8 or 16 Kbytes
FF:0000H
FE:0000H
External Memory
Regions 02–FD
are Reserved
01:FFFFH
00:FFFFH
External Memory
01:0000H
00:0000H
External Memory
On-chip RAM
512 or 1024 Bytes
Registers R0-R7
††
†
††
Eight-byte configuration array (FF:FFF8H - FF:FFFFH)
Four banks of registers R0-R7 (32 bytes, 00:0000H - 00:001FH)
A4382-02
Figure 3-5. Hardware Implementation of the 8XC251SA, SB, SP, SQ Address Space
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Locations FF:FFF8H–FF:FFFFH are reserved for the configuration array (see Chapter 4, “Device
FF:FFF8H and FF:FFF9H; locations FF:FFFAH–FF:FFFFH are reserved for configuration bytes
in future products. Do not attempt to execute code from locations FF:FFF8H–FF:FFFFH. Also,
see the caution on page 4-2 regarding execution of code from locations immediately below the
configuration array.
Figure 3-4 also indicates the addressing modes that can be used to access different areas of mem-
ory. The first 64 Kbytes can be directly addressed. The first 96 bytes of general-purpose RAM
(00:0020H–00:007FH) are bit addressable. Chapter 5, “Programming,” discusses addressing
modes.
Figure 3-5 on page 3-7 shows how areas of the memory space are implemented by on-chip RAM,
on-chip ROM/OTPROM/EPROM, and external memory. The first 32 bytes of on-chip RAM
store banks 0–3 of the register file (see “8XC251SA, SB, SP, SQ Register File” on page 3-10).
3.2.1 On-chip General-purpose Data RAM
On-chip RAM (512 bytes or 1 Kbyte) is provided for general data storage (Figure 3-5). Instruc-
tions cannot execute from on-chip data RAM. The data is accessible by direct, indirect, and dis-
placement addressing. Locations 00:0020H–00:007FH are also bit addressable.
3.2.2 On-chip Code Memory (83C251SA, SB, SP, SQ/87C251SA, SB, SP, SQ)
The 8XC251Sx is available with 8 Kbytes or 16 Kbytes of on-chip ROM (83C251Sx) or
OTPROM/EPROM (87C251Sx) as well as without on-chip code memory (Figure 3-5). Table 2-1
on page 2-3 lists the amount of on-chip code memory for each device. The on-chip
ROM/OTPROM/EPROM is intended primarily for code storage, although its contents can also
be read as data with the indirect and displacement addressing modes. Following a chip reset, pro-
Memory,” describes programming and verification of the ROM/OTPROM/EPROM.
A code fetch within the address range of the on-chip ROM/OTPROM/EPROM accesses the on-
chip ROM/OTPROM/EPROM only if EA# = 1. For EA# = 0, a code fetch in this address range
accesses external memory. The value of EA# is latched when the chip leaves the reset state. Code
is fetched faster from on-chip code memory than from external memory. Table 3-2 lists the min-
imum times to fetch two bytes of code from on-chip memory and external memory.
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ADDRESS SPACES
Table 3-2. Minimum Times to Fetch Two Bytes of Code
Type of Code Memory
On-chip Code Memory
State Times
1
2
4
External Memory (page mode)
External Memory (nonpage mode)
NOTE
If your program executes exclusively from on-chip ROM/OTPROM/EPROM
(not from external memory), beware of executing code from the upper eight
bytes of the on-chip ROM/OTPROM/EPROM (FF:1FF8H–FF:1FFFH for 8
Kbytes, FF:3FF8H–FF:3FFFH for 16 Kbytes). Because of its pipeline
capability, the 8XC251Sx may attempt to prefetch code from external memory
(at an address above FF:1FFFH/FF:3FFFH) and thereby disrupt I/O ports 0
and 2. Fetching code constants from these eight bytes does not affect ports 0
and 2.
If your program executes from both on-chip ROM/OTPROM/EPROM and
external memory, your code can be placed in the upper eight bytes of the on-
chip ROM/OTPROM/EPROM. As the 8XC251Sx fetches bytes above the top
address in the on-chip ROM/OTPROM/EPROM, the code fetches automati-
cally become external bus cycles. In other words, the rollover from on-chip
ROM/OTPROM/EPROM to external code memory is transparent to the user.
3.2.2.1
Accessing On-chip Code Memory in Region 00:
The 87C251SB, SQ and the 83C251SB, SQ can be configured so that the upper half of the 16-
Kbyte on-chip code memory can also be read as data at locations in the top of region 00: (see
“Configuration Bytes” on page 14-7). That is, locations FF:2000H–FF:3FFFH can also be access-
ed at locations 00:E000H–00:FFFFH. This is useful for accessing code constants stored in
ROM/OTPROM/EPROM. Note, however, that all of the following three conditions must hold for
this mapping to be effective:
• The device is configured with EMAP# = 0 in the UCONFIG1 register (See Chapter 4).
• EA# = 1.
• The access to this area of region 00: is a data read, not a code fetch.
If one or more of these conditions do not hold, accesses to the locations in region 00: are referred
to external memory.
NOTE
Remapping does not apply to the 87C251SA, SP and the 83C251SA, SP.
3-9
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3.2.3 External Memory
Regions 01:, FE:, and portions of regions 00: and FF: of the memory space are implemented as
external memory (Figure 3-5 on page 3-7). For discussions of external memory see “Configuring
3.3 8XC251SA, SB, SP, SQ REGISTER FILE
The 8XC251Sx register file consists of 40 locations: 0–31 and 56–63, as shown in Figure 3-6.
These locations are accessible as bytes, words, and dwords, as described in “Byte, Word, and
Dword Registers” on page 3-13. Several locations are dedicated to special registers (see “Dedi-
cated Registers” on page 3-13); the others are general-purpose registers.
3-10
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ADDRESS SPACES
Byte Registers
Note: R10 = B
R11 = ACC
R8 R9 R10 R11 R12 R13 R14 R15
R0 R1 R2 R3 R4 R5 R6 R7
Register File
Word Registers
56 57 58 59 60 61 62 63
Locations 32-55 are Reserved
24 25 26 27 28 29 30 31
16 17 18 19 20 21 22 23
WR24
WR16
WR8
WR26
WR18
WR10
WR2
WR28
WR20
WR12
WR4
WR30
WR22
WR14
WR6
8
0
9
1
10 11 12 13 14 15
2
3
4
5
6
7
WR0
Dword Registers
DR56 = DPX DR60 = SPX
0
1
2
3
4
5
6
7
Banks 0-3
DR24
DR16
DR8
DR28
DR20
DR12
DR4
DR0
A4099-01
Figure 3-6. The Register File
3-11
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8XC251SA, SB, SP, SQ USER’S MANUAL
Register file locations 0–7 actually consist of four switchable banks of eight registers each, as il-
lustrated in Figure 3-7. The four banks are implemented as the first 32 bytes of on-chip RAM and
are always accessible as locations 00:0000H–00:001FH in the memory address space.† Only one
of the four banks is accessible via the register file at a given time. The accessible, or “active,”
bank is selected by bits RS1 and RS0 in the PSW register, as shown in Table 3-3. (The PSW is
described in “Program Status Words” on page 5-16.) This bank selection can be used for fast con-
text switches.
Register file locations 8–31 and 56–63 are always accessible. These locations are implemented
as registers in the CPU. Register file locations 32–55 are reserved and cannot be accessed.
Register File
Memory Address Space
FF:FFFFH
63
8
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
00:0020H
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
18H
10H
08H
00H
1FH
17H
0FH
07H
Banks 0–3
accessible
in memory
0
1
2
3
4
5
6
7
PSW bits RS1:0
select one bank
to be accessed via
the register file.
Banks 0–3
address space
A4215-01
Figure 3-7. Register File Locations 0–7
Table 3-3. Register Bank Selection
PSW Selection Bits
Bank
Address Range
RS1
RS0
Bank 0
Bank 1
Bank 2
Bank 3
00H–07H
08H–0FH
10H–17H
18H–1FH
0
0
1
1
0
1
0
1
†
Because these locations are dedicated to the register file, they are not considered a part of the general-
purpose, 1-Kbyte, on-chip RAM (locations 00:0020H–00:041FH).
3-12
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ADDRESS SPACES
3.3.1 Byte, Word, and Dword Registers
Depending on its location in the register file, a register is addressable as a byte, a word, and/or a
dword, as shown on the right side of Figure 3-6. A register is named for its lowest numbered byte
location. For example:
R4 is the byte register consisting of location 4.
WR4 is the word register consisting of registers 4 and 5.
DR4 is the dword register consisting of registers 4–7.
Locations R0–R15 are addressable as bytes, words, or dwords. Locations 16–31 are addressable
only as words or dwords. Locations 56–63 are addressable only as dwords. Registers are ad-
dressed only by the names shown in Figure 3-6 — except for the 32 registers that comprise the
four banks of registers R0–R7, which can also be accessed as locations 00:0000H–00:001FH in
the memory space.
3.3.2 Dedicated Registers
The register file has four dedicated registers:
• R10 is the B-register
• R11 is the accumulator (ACC)
• DR56 is the extended data pointer, DPX
• DR60 is the extended stack pointer, SPX
These registers are located in the register file; however, R10, R11, and some bytes of DR56 and
DR60 are also accessible as SFRs. The bytes of DPX and SPX can be accessed in the register file
responding SFRs are illustrated in Figure 3-8 and listed in Table 3-4.
3.3.2.1
Accumulator and B Register
The 8-bit accumulator (ACC) is byte register R11, which is also accessible in the SFR space as
ACC at S:E0H (Figure 3-8). The B register, used in multiplies and divides, is register R10, which
is also accessible in the SFR space as B at S:F0H. Accessing ACC or B as a register is one state
faster than accessing them as SFRs.
3-13
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8XC251SA, SB, SP, SQ USER’S MANUAL
Instructions in the MCS 51 architecture use the accumulator as the primary register for data
moves and calculations. However, in the MCS 251 architecture, any of registers R1–R15 can
serve for these tasks†. As a result, the accumulator does not play the central role that it has in
MCS 51 microcontrollers.
Register File
SFRs
Stack Pointer, High
Stack Pointer
SPH S:BEH
S:81H
SP
SPH
62
SP
63
60
61
DR60 = Extended Stack Pointer, SPX
Data Pointer Extended, Low
Data Pointer, High
S:84H
DPXL
DPH S:83H
Data Pointer, Low
S:82H
DPL
DPH
58
DPL
59
DPXL
57
56
DR56 = Extended Data Pointer, DPX
B
S:F0H
ACC S:E0H
B
ACC
R10, B Register
R11, Accumulator, ACC
A4152-02
Figure 3-8. Dedicated Registers in the Register File and their Corresponding SFRs
†
Bits in the PSW and PSW1 registers reflect the status of the accumulator. There are no equivalent status
indicators for the other registers.
3-14
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ADDRESS SPACES
3.3.2.2
Extended Data Pointer, DPX
Dword register DR56 is the extended data pointer, DPX (Figure 3-8). The lower three bytes of
DPX (DPL, DPH, and DPXL) are accessible as SFRs. DPL and DPH comprise the 16-bit data
pointer DPTR. While instructions in the MCS 51 architecture always use DPTR as the data point-
er, instructions in the MCS 251 architecture can use any word or dword register as a data pointer.
DPXL, the byte in location 57, specifies the region of memory (00:–FF:) that maps into the 64-
Kbyte external data memory space in the MCS 51 architecture. In other words, the MOVX in-
struction addresses the region specified by DPXL when it moves data to and from external mem-
ory. The reset value of DPXL is 01H.
3.3.2.3
Extended Stack Pointer, SPX
Dword register DR60 is the stack pointer, SPX (Figure 3-8). The byte at location 63 is the 8-bit
stack pointer, SP, in the MCS 51 architecture. The byte at location 62 is the stack pointer high,
SPH. The two bytes allow the stack to extend to the top of memory region 00:. SP and SPH can
be accessed as SFRs.
Two instructions, PUSH and POP directly address the stack pointer. Subroutine calls (ACALL,
ECALL, LCALL) and returns (ERET, RET, RETI) also use the stack pointer. To preserve the
stack, do not use DR60 as a general-purpose register.
Table 3-4. Dedicated Registers in the Register File and their Corresponding SFRs
Register File
Mnemonic Reg. Location
SFRs
Mnemonic
Name
Address
—
—
—
—
60
61
62
63
56
57
58
59
11
10
—
—
—
Stack
Pointer
(SPX)
—
DR60
DR56
Stack Pointer, High
Stack Pointer, Low
—
SPH
SP
SPH
SP
S:BEH
S:81H
—
—
—
Data
Pointer
(DPX)
Data Pointer, Extended Low
DPXL
DPH
DPL
A
DPXL
DPH
DPL
ACC
B
S:84H
S:83H
S:82H
S:E0H
S:F0H
Data Pointer, High
DPTR
Data Pointer, Low
Accumulator (A Register)
B Register
R11
R10
B
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3.4 SPECIAL FUNCTION REGISTERS (SFRS)
The special function registers (SFRs) reside in their associated on-chip peripherals or in the core.
Table 3-5 shows the SFR address space with the SFR mnemonics and reset values. SFR addresses
are preceded by “S:” to differentiate them from addresses in the memory space. Unoccupied lo-
cations in the SFR space (the shaded locations in Table 3-5) are unimplemented, i.e., no register
exists. If an instruction attempts to write to an unimplemented SFR location, the instruction exe-
cutes, but nothing is actually written. If an unimplemented SFR location is read, it returns an un-
specified value.
NOTE
SFRs may be accessed only as bytes; they may not be accessed as words or
dwords.
3-16
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ADDRESS SPACES
Table 3-5. 8XC251SA, SB, SP, SQ SFR Map and Reset Values
0/8
1/9
CH
2/A
3/B
4/C
5/D
6/E
7/F
CCAP0H
CCAP1H
xxxxxxxx
CCAP2H
xxxxxxxx
CCAP3H
xxxxxxxx
CCAP4H
xxxxxxxx
F8
F0
E8
E0
D8
D0
C8
C0
B8
B0
A8
A0
98
90
88
80
FF
F7
EF
E7
DF
D7
CF
C7
BF
B7
AF
A7
9F
97
8F
87
00000000 xxxxxxxx
B
00000000
CL
CCAP0L
CCAP1L
xxxxxxxx
CCAP2L
xxxxxxxx
CCAP3L
xxxxxxxx
CCAP4L
xxxxxxxx
00000000 xxxxxxxx
ACC
00000000
CCON
CMOD
CCAPM0 CCAPM1 CCAPM2 CCAPM3 CCAPM4
00x00000 00xxx000 x0000000 x0000000 x0000000 x0000000 x0000000
PSW PSW1
00000000 00000000
T2CON T2MOD
00000000 xxxxxx00 00000000 00000000 00000000 00000000
RCAP2L
RCAP2H
TL2
TH2
IPL0
SADEN
SPH
x0000000 00000000
00000000
P3
IPH0
11111111
x0000000
IE0
SADDR
00000000 00000000
P2
WDTRST
xxxxxxxx
WCON
11111111
xxxxxx00
SCON
SBUF
00000000 xxxxxxxx
P1
11111111
TCON
TMOD
TL0
TL1
TH0
TH1
00000000 00000000 00000000 00000000 00000000 00000000
P0
SP
DPL
DPH
DPXL
PCON
11111111
00000111 00000000 00000000 00000001
00xx0000
0/8
1/9 2/A 3/B 4/C
5/D
6/E
7/F
NOTE: Shaded areas represent unimplemented SFR locations. Locations S:000H–S:07FH and
S:100H–S:1FFH are also unimplemented.
3-17
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Table 3-6 — Core SFRs
Table 3-7 — I/O Port SFRs
Table 3-8 — Serial I/O SFRs
Table 3-9 — Timer/Counter and Watchdog Timer SFRs
Table 3-10 — Programmable Counter Array (PCA) SFRs
Table 3-6. Core SFRs
Mnemonic
Name
Address
ACC†
B†
Accumulator
S:E0H
S:F0H
S:D0H
S:D1H
S:81H
S:BEH
—
B Register
PSW
PSW1
SP†
Program Status Word
Program Status Word 1
Stack Pointer – LSB of SPX
Stack Pointer High – MSB of SPX
Data Pointer (2 bytes)
Low Byte of DPTR
SPH†
DPTR†
DPL†
DPH†
DPXL†
PCON
IE0
S:82H
S:83H
S:84H
S:87H
S:A8H
S:B7H
S:B8H
High Byte of DPTR
Data Pointer, Extended Low
Power Control
Interrupt Enable Control 0
Interrupt Priority Control High 0
Interrupt Priority Control Low 0
IPH0
IPL0
†
These SFRs can also be accessed by their corresponding registers in the
register file (see Table 3-4 on page 3-15).
Table 3-7. I/O Port SFRs
Mnemonic
Name
Address
P0
P1
P2
P3
Port 0
Port 1
Port 2
Port 3
S:80H
S:90H
S:A0H
S:B0H
3-18
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ADDRESS SPACES
Table 3-8. Serial I/O SFRs
Mnemonic
Name
Address
SCON
SBUF
Serial Control
S:98H
S:99H
S:B9H
S:A9H
Serial Data Buffer
Slave Address Mask
Slave Address
SADEN
SADDR
Table 3-9. Timer/Counter and Watchdog Timer SFRs
Name
Mnemonic
Address
TL0
Timer/Counter 0 Low Byte
Timer/Counter 0 High Byte
Timer/Counter 1 Low Byte
Timer/Counter 1 High Byte
Timer/Counter 2 Low Byte
Timer/Counter 2 High Byte
Timer/Counter 0 and 1 Control
Timer/Counter 0 and 1 Mode Control
Timer/Counter 2 Control
S:8AH
S:8CH
S:8BH
S:8DH
S:CCH
S:CDH
S:88H
S:89H
S:C8H
S:C9H
S:CAH
S:CBH
S:A6H
TH0
TL1
TH1
TL2
TH2
TCON
TMOD
T2CON
T2MOD
RCAP2L
RCAP2H
WDTRST
Timer/Counter 2 Mode Control
Timer 2 Reload/Capture Low Byte
Timer 2 Reload/Capture High Byte
WatchDog Timer Reset
Table 3-10. Programmable Counter Array (PCA) SFRs
Name
Mnemonic
Address
CCON
PCA Timer/Counter Control
PCA Timer/Counter Mode
PCA Timer/Counter Mode 0
PCA Timer/Counter Mode 1
PCA Timer/Counter Mode 2
PCA Timer/Counter Mode 3
PCA Timer/Counter Mode 4
S:D8H
S:D9H
S:DAH
S:DBH
S:DCH
S:DDH
S:DEH
CMOD
CCAPM0
CCAPM1
CCAPM2
CCAPM3
CCAPM4
3-19
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8XC251SA, SB, SP, SQ USER’S MANUAL
Table 3-10. Programmable Counter Array (PCA) SFRs (Continued)
Mnemonic
Name
Address
CL
PCA Timer/Counter Low Byte
S:E9H
S:F9H
S:EAH
S:EBH
S:ECH
S:EDH
S:EEH
S:FAH
S:FBH
S:FCH
S:FDH
S:FEH
CH
PCA Timer/Counter High Byte
CCAP0L
CCAP1L
CCAP2L
CCAP3L
CCAP4L
CCAP0H
CCAP1H
CCAP2H
CCAP3H
CCAP4H
PCA Compare/Capture Module 0 Low Byte
PCA Compare/Capture Module 1 Low Byte
PCA Compare/Capture Module 2 Low Byte
PCA Compare/Capture Module 3 Low Byte
PCA Compare/Capture Module 4 Low Byte
PCA Compare/Capture Module 0 High Byte
PCA Compare/Capture Module 1 High Byte
PCA Compare/Capture Module 2 High Byte
PCA Compare/Capture Module 3 High Byte
PCA Compare/Capture Module 4 High Byte
3-20
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4
Device
Configuration
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CHAPTER 4
DEVICE CONFIGURATION
The 8XC251Sx provides user design flexibility by configuring certain operating features at de-
vice reset. These features fall into the following categories:
• external memory interface (page mode, address bits, pre-programmed wait states and the
address range for RD#, WR#, and PSEN#)
• source mode/binary mode opcodes
• selection of bytes stored on the stack by an interrupt
• mapping of the upper portion of on-chip code memory to region 00:
This chapter provides a detailed discussion of 8XC251Sx device configuration. It describes the
configuration bytes and provides information to aid you in selecting a suitable configuration for
your application. It discusses the choices involved in configuring the external memory interface
and shows how the internal memory maps into the external memory. See 4.5, “Configuring the
External Memory Interface.” Section 4.6, “Opcode Configurations (SRC),” discusses the choice
of source mode or binary mode opcode arrangements.
4.1 CONFIGURATION OVERVIEW
The configuration of the MCS® 251 microcontroller is established by the reset routine based on
information stored in configuration bytes. The 8XC251Sx microcontrollers store configuration
information in two configuration bytes located in code memory. Devices with no on-chip code
customer provided configuration data supplied on floppy disc.
4.2 DEVICE CONFIGURATION
The 8XC251Sx reserves the top eight bytes of the memory address map (FF:FFF8H–FF:FFFFH)
for an eight-byte configuration array (Figure 4-1). The two lowest bytes of the configuration array
are assigned to the user configuration bytes UCONFIG0 (FF:FFF8H) and UCONFIG1
(FF:FFF9H). For ROM/OTPROM/EPROM devices, configuration information is stored in on-
chip non-volatile memory at these addresses. For devices without on-chip
ROM/OTPROM/EPROM, configuration information is accessed from external memory.
4-1
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8XC251SA, SB, SP, SQ USER’S MANUAL
For ROM/OTPROM/EPROM devices, user configuration bytes UCONFIG0 and UCONFIG1
can be programmed at the factory or on-site using the procedures provided in Chapter 14, “Pro-
gramming and Verifying Nonvolatile Memory.” For devices without ROM/OTPROM/ EPROM,
the designer should store configuration information in an eight-byte configuration array located
at the highest addresses implemented in external code memory. See Table 4-1 and Figure 4-2.
Bit definitions of UCONFIG0 and UCONFIG1 are provided in Figures 4-3 and 4-4. The upper 6
bytes of the configuration array are reserved for future use. When EA# = 1, the 8XC251Sx obtains
configuration information at reset from on-chip non-volatile memory at addresses FF:FFF8H and
FF:FFF9H. When EA# = 0, the microcontroller obtains configuration information at reset from
the external memory system using internal addresses FF:FFF8H and FF:FFF9H.
CAUTION
The eight highest addresses in the memory address space (FF:FFF8H–
FF:FFFFH) are reserved for the configuration array. Do not read or write these
locations. These addresses are also used to access the configuration array in
external memory, so the same restrictions apply to the eight highest addresses
implemented in external memory. Instructions that might inadvertently cause
these addresses to be accessed due to call returns or prefetches should not be
located at addresses immediately below the configuration array. Use an EJMP
instruction, five or more addresses below the configuration array, to continue
execution in other areas of memory.
83C251SA, SP
87C251SA, SP
83C251SB, SQ
87C251SB, SQ
FF:
FF:
FF:FFFFH
FF:FFFEH
FF:FFFDH
FF:FFFCH
FF:FFFBH
FF:FFFAH
16 Kbytes
8 Kbytes
Reserved
For EA# = 1, the 8XC251Sx obtains configuration information
from on-chip nonvolatile memory at addresses FF:FFF8H
and FF:FFF9H.
FF:FFF9H UCONFIG1
UCONFIG0
FF:FFF8H
Detail. On-chip configuration array.
A4237-01
Figure 4-1. Configuration Array (On-chip)
4-2
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DEVICE CONFIGURATION
64 Kbytes
FFF9H
FFF8H
8 Kbytes
16 Kbytes
32 Kbytes
7FF9H
7FF8H
3FF9H
3FF8H
1FF9H
1FF8H
128 Kbytes
256 Kbytes
1:FFF9H
1:FFF8H
3:FFF9H
3:FFF8H
x:xFFFH
x:xFFEH
x:xFFDH
Reserved
x:xFFCH
x:xFFBH
x:xFFAH
x:xFF9H UCONFIG1
UCONFIG0
x:xFF8H
Detail.
Configuration array in external memory.
This figure shows the addresses of configuration bytes UCONFIG1 and UCONFIG0 in external memory for
several memory implementations. For EA# = 0, the 8XC251Sx obtains configuration information from configuration
bytes in external memory using internal addresses FF:FFF8H and FF:FFF9H. In external memory, the eight-byte
configuration array is located at the highest addresses implemented.
A4236-01
Figure 4-2. Configuration Array (External)
4-3
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Table 4-1. External Addresses for Configuration Array
Size of External
Address Bus
(Bits)
Address of
Configuration Array on
External Bus (2)
Address of
Configuration Bytes
on External Bus (1)
16
17
FFF8H–FFFFH
1FFF8H–1FFFFH
3FFF8H–3FFFFH
UCONFIG1: FFF9H
UCONFIG0: FFF8H
UCONFIG1: 1FFF9H
UCONFIG0: 1FFF8H
18
UCONFIG1: 3FFF9H
UCONFIG0: 3FFF8H
NOTES:
1. When EA# = 0, the reset routine retrieves UCONFIG0 and UCONFIG1 from
external memory using internal addresses FF:FFF8H and FF:FFF9H, which
2. The upper six bytes of the configuration array are reserved for future use.
4.3 THE CONFIGURATION BITS
This section provides a brief description of the configuration bits contained in the configuration
bytes (Figures 4-3 and 4-4). UCONFIG0 and UCONFIG1 have five wait state bits: WSA1:0#,
WSB1:0#, and WSB.
• UCON. Configuration byte location selector.
• SRC. Selects source mode or binary mode opcode configuration.
• INTR. Selects the bytes pushed onto the stack by interrupts.
The following bits configure the external memory interface.
• PAGE#. Selects page/nonpage mode and specifies the data port.
• RD1:0. Selects the number of external address bus pins and the address range for RD#, WR,
and PSEN#. See Table 4-2.
• XALE#. Extends the ALE pulse.
• WSA1:0#. Selects 0, 1, 2, or 3 pre-programmed wait states for all regions except 01:.
• WSB1:0#. Selects 0 - 3 pre-programmed wait states for memory region 01:.
• EMAP#. Affects the external memory interface in that, when asserted, addresses in the
range 00:E000H–00:FFFH access on-chip memory.
4-4
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DEVICE CONFIGURATION
4.4 CONFIGURATION BYTE LOCATION SELECTOR (UCON)
The Configuration Byte Location Selector (UCON) applies only to OTPROM and EPROM prod-
ucts. In conjunction with EA#, UCON specifies whether the configuration array is accessed from
on-chip memory or external memory.
If the UCON bit is clear (e.g., UCON=0), the configuration array is fetched from on-chip nonvol-
atile memory at addresses FF:FFF8H to FF:FFFFH. The configuration bytes are located at loca-
tions FF:FFF8H and FF:FFF9H.
If UCON is set (e.g., UCON=1), the state of the EA# pin at device reset determines whether the
configuration array is accessed from on-chip memory or external memory. If EA# is connected
to VCC, the configuration array is accessed from on-chip nonvolatile memory at addresses
FF:FFF8H through FF:FFFFH (same as for UCON=0). If EA# is connected to VSS, the configu-
ration array is obtained from external memory (e.g., a 27512 EPROM).
4-5
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Address:FF:FFF8H (2)
UCONFIG0
(1), (3)
7
0
UCON
WSA1#
WSA0#
XALE#
RD1
RD0
PAGE#
SRC
Bit
Bit
Function
Number Mnemonic
7
UCON
Configuration Byte Location Selector (OTPROM/EPROM products only):
Clearing this bit causes the 8XC251Sx to fetch configuration information
from on-chip memory. Leaving this bit unprogrammed (logic 1) causes the
8XC251Sx to fetch configuration information from on-chip memory if EA# =
1 or from external memory if EA# = 0.
87C251Sx
—
Reserved:
80C251Sx Write a 1 to this bit when programming UCONFIG0.
83C251Sx
6:5
WSA1:0#
Wait State A (all regions except 01:):
For external memory accesses, selects the number of wait states for RD#,
WR#, and PSEN#.
WSA1# WSA0#
0
0
1
1
0
1
0
1
Inserts 3 wait states for all regions except 01:
Inserts 2 wait states for all regions except 01:
Inserts 1 wait state for all regions except 01:
Zero wait states for all regions except 01:
4
XALE#
RD1:0
PAGE#
Extend ALE:
Set this bit for ALE = TOSC
Clear this bit for ALE = 3TOSC (adds one external wait state).
.
3:2
1
Memory Signal Selection:
RD1:0 bit codes specify an 18-bit, 17-bit, or 16-bit external address bus and
address ranges for RD#, WR#, and PSEN#. See Table 4-2.
Page Mode Select:
Clear this bit for page mode enabled with A15:8/D7:0 on P2 and A7:0 on P0.
Set this bit for page mode disabled with A15:8 on P2 and A7:0/D7:0 on P0
(compatible with 44-pin PLCC and 40-pin DIP MCS 51 microcontrollers).
0
SRC
Source Mode/Binary Mode Select:
Clear this bit for binary mode (compatible with MCS 51 microcontrollers).
Set this bit for source mode.
NOTES:
1. User configuration bytes UCONFIG0 and UCONFIG1 define the configuration of the 8XC251Sx.
2. Address. UCONFIG0 is the second-lowest byte of the 8-byte configuration array. As determined by
UCON and EA#, the 8XC251Sx fetches configuration information from on-chip nonvolatile memory at
addresses FF:FFF8H and FF:FFF9H or from external memory using these same addresses. In exter-
nal memory, configuration information is obtained from an 8-byte configuration array located at the
highest addresses implemented. The location of the configuration array in external memory depends
on the size and decode arrangement of the external memory (Table 4-1 and Figure 4-2).
3. Instructions for programming and verifying on-chip configuration bytes are given in Chapter 14.
Figure 4-3. Configuration Byte UCONFIG0
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DEVICE CONFIGURATION
Address:FF:FFF9H (2)
UCONFIG1
(1), (3)
7
0
—
—
—
INTR
WSB
WSB1#
WSB0#
EMAP#
Bit
Bit
Function
Number Mnemonic
7:5
—
Reserved for internal or future use. Set these bits when programming
UCONFIG1.
4
INTR
Interrupt Mode:
If this bit is set, interrupts push 4 bytes onto the stack (the 3 bytes of the PC
and PSW1). If this bit is clear, interrupts push the 2 lower bytes of the PC
onto the stack. See 4.8, “Interrupt Mode (INTR).”
3
WSB
Wait State B. Use only for A-step compatibility:
Clear this bit to generate one external wait state for memory region 01:. Set
this bit for no wait states for region 01:.
2:1
WSB1:0#
External Wait State B (Region 01:):
WSB1# WSB0#
0
0
1
1
0
1
0
1
Inserts 3 wait states for region 01:
Inserts 2 wait states for region 01:
Inserts 1 wait state for region 01:
Zero wait states for region 01:
0
EMAP#
EPROM Map:
For devices with 16 Kbytes of on-chip code memory, clear this bit to map the
upper half of on-chip code memory to region 00: (data memory). Maps
FF:2000H–FF:3FFFH to 00:E000H–00:FFFFH. If this bit is set, mapping
does not occur and addresses in the range 00:E000H–00:FFFFH access
external RAM. See 4.7, “Mapping On-chip Code Memory to Data Memory
(EMAP#).”
NOTES:
1. User configuration bytes UCONFIG0 and UCONFIG1 define the configuration of the 8XC251Sx.
2. Address. UCONFIG1 is the second-lowest byte of the 8-byte configuration array. As determined by
UCON and EA#, the 8XC251SA, SB, SP, SQ fetches configuration information from on-chip nonvolatile
memory at addresses FF:FFF8H and FF:FFF9H or from external memory using these same
addresses. In external memory, configuration information is obtained from an 8-byte configuration
array located at the highest addresses implemented. The physical location of the configuration array in
external memory depends on the size and decode arrangement of the external memory (Table 4-1 and
Figure 4-2).
3. Instructions for programming and verifying on-chip configuration bytes are given in Chapter 14.
Figure 4-4. Configuration Byte UCONFIG1
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Table 4-2. Memory Signal Selections (RD1:0)
P1.7/CEX/
A17/WCLK
RD1:0
P3.7/RD#/A16
PSEN#
WR#
Features
0
0
1
0
1
0
A17
A16
Asserted for
all addresses all memory locations
Asserted for writes to 256-Kbyte external
memory
P1.7/CEX4/
WCLK
A16
Asserted for Asserted for writes to 128-Kbyte external
all addresses all memory locations memory
P1.7/CEX4/
WCLK
P3.7 only
Asserted for Asserted for writes to 64-Kbyte external
all addresses all memory locations
memory. One
additional port pin.
1
1
P1.7/CEX4/
WCLK
RD# asserted
for addresses
≤ 7F:FFFFH
Asserted for
≥ 80:0000H
Asserted only for
writes to MCS 51
microcontroller data
memory locations.
64-Kbyte external
memory. Compatible
with MCS 51 micro-
controllers.
4.5 CONFIGURING THE EXTERNAL MEMORY INTERFACE
This section describes the configuration options that affect the external memory interface. The
configuration bits described here determine the following interface features:
• page mode or nonpage mode (PAGE#)
• the number of external address pins (16, 17, or 18) (RD1:0)
• the memory regions assigned to the read signals RD# and PSEN# (RD1:0)
• the external wait states (WSA1:0#, WSB1:0#, XALE#)
• mapping a portion of on-chip code memory to data memory (EMAP#)
4.5.1 Page Mode and Nonpage Mode (PAGE#)
The PAGE# bit (UCONFIG0.1) determines whether code fetches use page mode or nonpage
mode and whether data is transmitted on P2 or P0. See Figure 13-1 on page 13-1 and section
13.2.3, “Page Mode Bus Cycles,” for a description of the bus structure and page mode operation.
• Nonpage mode: PAGE# = 1. The bus structure is the same as for the MCS 51 architecture
with data D7:0 multiplexed with A7:0 on P0. External code fetches require two state times
(4TOSC).
• Page mode: PAGE# = 0. The bus structure differs from the bus structure in MCS 51
controllers. Data D7:0 is multiplexed with A15:8 on P2. Under certain conditions, external
code fetches require only one state time (2TOSC).
4-8
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DEVICE CONFIGURATION
4.5.2 Configuration Bits RD1:0
The RD1:0 configuration bits (UCONFIG0.3:2) determine the number of external address signals
and the address ranges for asserting the read signals PSEN#/RD# and the write signal WR#.
These selections offer different ways of addressing external memory. Figures 4-5 and 4-6 show
how internal memory maps into external memory for the four values of RD1:0. Section 13.8, “Ex-
ternal Memory Design Examples,” provides examples of external memory designs for each
choice of RD1:0.
A key to the memory interface is the relationship between internal memory addresses and exter-
nal memory addresses. While the 8XC251Sx has 24 internal address bits, the number of external
address lines is less than 24 (i.e., 16, 17, or 18 depending on the values of RD1:0). This means
that reads/writes to different internal memory addresses can access the same location in external
memory.
For example, if the 8XC251Sx is configured for 17 external address lines, a write to location
01:6000H and a write to location FF:6000H accesses the same 17-bit external address (1:6000H)
because A16 = 1 for both internal addresses. In other words, regions 01: and FF: map into the
same 64-Kbyte region in external memory.
not preclude using more than one region. For example, for a device with on-chip ROM/
OTPROM/EPROM configured for 17 address bits and with EA# = 1, an access to FF:0000H–
FF:3FFFH (16 Kbytes) accesses the on-chip ROM/OTPROM/EPROM, while an access to
01:0000H–01:3FFFH is to external memory. In this case, you could execute code from these lo-
cations in region FF: and store data in the corresponding locations in region 01: without conflict.
See Figure 4-5 and section 13.8.3, “Example 3: RD1:0 = 01, 17-bit Bus, External RAM.”
4.5.2.1
RD1:0 = 00 (18 External Address Bits)
The selection RD1:0 = 00 provides 18 external address bits: A15:0 (ports P0 and P2), A16 (from
P3.7/RD#/A16), and A17 (from P1.7/CEX4/A17/WCLK). Bits A16 and A17 can select four 64-
Kbyte regions of external memory for a total of 256 Kbytes (top half of Figure 4-5). This is the
largest possible external memory space. See section 13.8.1, “Example 1: RD1:0 = 00, 18-bit Bus,
External Flash and RAM.”
4.5.2.2
RD1:0 = 01 (17 External Address Bits)
The selection RD1:0 = 01 provides 17 external address bits: A15:0 (ports P0 and P2) and A16
(from P3.7/RD#/A16). Bit A16 can select two 64-Kbyte regions of external memory for a total
of 128 Kbytes (bottom half of Figure 4-5). Regions 00: and FE: (each having A16 = 0) map into
the same 64-Kbyte region in external memory. This duplication also occurs for regions 01: and
FF:
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This selection provides a 128-Kbyte external address space. The advantage of this selection, in
comparison with the 256-Kbyte external memory space with RD1:0 = 00, is the availability of
pin P1.7/CEX4/A17/WCLK for general I/O, PCA I/O, and real-time wait clock output. I/O P3.7
is unavailable. All four 64-Kbyte regions are strobed by PSEN# and WR#. Sections 13.8.2 and
13.8.3 show examples of memory designs with this option.
RD1:0 = 00
18 external address bits:
P0, P2, A16, A17
External
Memory
Internal Memory with
Read/Write Signals
256 Kbytes
Notes:
1. Maximum external
memory
A17:16
1 1
FF:
FF:
PSEN#, WR#
FE:
1 0
FE:
01
2. Single read signal
0 1
0 0
01:
00:
PSEN#, WR#
00
RD1:0 = 01
External
Memory
Internal Memory with
Read/Write Signals
17 external address bits:
P0, P2, A16
128 Kbytes
Note:
Single read signal
FF:
A16
1
PSEN#, WR#
FE:
01:, FF:
00:, FE:
0
01:
00:
PSEN#, WR#
A4218-02
Figure 4-5. Internal/External Address Mapping (RD1:0 = 00 and 01)
4-10
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DEVICE CONFIGURATION
RD1:0 = 10
16 external address bits:
P0, P2
External
Memory
Internal Memory with
Read/Write Signals
64 Kbytes
Notes:
FF:
1. Single read signal
2. P3.7/RD#/A16 functions
only as P3.7
PSEN#, WR#
FE:
00:, 01:, FE:, FF:
01:
00:
PSEN#, WR#
RD1:0 = 11
External
Memory
Internal Memory with
Read/Write Signals
16 external address bits:
P0, P2
128 Kbytes
Note:
1. Compatible with MCS® 51
microcontrollers
FF:
PSEN#
FE:
FE:, FF:
00:, 01:
2. Cannot write to regions FC:–FF:
01:
RD#, WR#
00:
A4217-02
Figure 4-6. Internal/External Address Mapping (RD1:0 = 10 and 11)
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8XC251SA, SB, SP, SQ USER’S MANUAL
4.5.2.3
RD1:0 = 10 (16 External Address Bits)
For RD1:0 = 10, the 16 external address bits (A15:0 on ports P0 and P2) provide a single 64-
Kbyte region in external memory (top of Figure 4-6). This selection provides the smallest exter-
nal memory space; however, pin P3.7/RD#/A16 is available for general I/O and pin
P1.7/CEX4/A17/WCLK is available for general I/O, PCA I/O, and real-time wait clock output.
This selection is useful when the availability of these pins is required and/or a small amount of
external memory is sufficient.
4.5.2.4
RD1:0 = 11 (Compatible with MCS 51 Microcontrollers)
The selection RD1:0 = 11 provides only 16 external address bits (A15:0 on ports P0 and P2).
However, PSEN# is the read signal for regions FE:–FF:, while RD# is the read signal for regions
00:–01: (bottom of Figure 4-6). The two read signals effectively expand the external memory
space to two 64-Kbyte regions. WR# is asserted only for writes to regions 00:–01:. This selection
provides compatibility with MCS 51 microcontrollers, which have separate external memory
spaces for code and data.
4.5.3 Wait State Configuration Bits
You can add wait states to external bus cycles by extending the RD#/WR#/PSEN# pulse and/or
extending the ALE pulse. Each additional wait state extends the pulse by 2TOSC. A separate wait
state specification for external accesses via region 01: permits a slow external device to be ad-
dressed in region 01: without slowing accesses to other external devices. Table 4-3 summarizes
the wait state selections for RD#,WR#,PSEN#. For waveform diagrams showing wait states, see
section 13.4, “External Bus Cycles with Configurable Wait States.”
4.5.3.1
Configuration Bits WSA1:0#, WSB1:#
The WSA1:0# wait state bits (UCONFIG0.6:5) permit RD#, WR#, and PSEN# to be extended by
1, 2, or 3 wait states for accesses to external memory via all regions except region 01:. The
WSB1:0# wait state bits (UCONFIG1.2:1) permit RD#, WR#, and PSEN# to be extended by 1,
2, or 3 wait states for accesses to external memory via region 01:.
4.5.3.2
Configuration Bit WSB
Use the WSB bit only for A-stepping compatibility. The WSB wait state bit (UCONFIG1.3) per-
mits RD#, WR#, and PSEN# to be extended by one wait state for accesses to external memory
via region 01:.
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DEVICE CONFIGURATION
4.5.3.3
Configuration Bit XALE#
Clearing XALE# (UCONFIG0.4) extends the time ALE is asserted from TOSC to 3TOSC. This ac-
commodates an address latch that is too slow for the normal ALE signal. Section 13.4.2, “Extend-
ing ALE,” shows an external bus cycle with ALE extended.
Table 4-3. RD#, WR#, PSEN# External Wait States
8XC251Sx
Regions
WSA1# WSA0#
00: FE: FF:
0
0
1
1
0
1
0
1
3 Wait States
2 Wait States
1 Wait State
0 Wait States
Region 01:
WSB1# WSB0#
0
0
1
1
0
1
0
1
3 Wait States
2 Wait States
1 Wait State
0 Wait States
4.6 OPCODE CONFIGURATIONS (SRC)
The SRC configuration bit (UCONFIG0.0) selects the source mode or binary mode opcode ar-
rangement. Opcodes for the MCS 251 architecture are listed in Table A-6 on page A-4 and Table
A-7 on page A-5. Note that in Table A-6 every opcode (00H–FFH), is used for an instruction ex-
cept A5H (ESC) which provides an alternative set of opcodes for columns 6H through FH. The
SRC bit selects which set of opcodes is assigned to columns 6H through FH and which set is the
alternative.
Binary mode and source mode refer to two ways of assigning opcodes to the instruction set for
the MCS 251 architecture. One of these modes must be selected when the chip is configured. De-
pending on the application, binary mode or source mode may produce more efficient code. This
section describes the binary and source modes and provides some guidelines for selecting the
mode for your application.
The MCS 251 architecture has two types of instructions:
• instructions that originate in the MCS 51 architecture
• instructions that are unique to the MCS 251 architecture
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Figure 4-7 shows the opcode map for binary mode. Area I (columns 1 through 5 in Table A-6 on
page A-4) and area II (columns 6 through F) make up the opcode map for the instructions that
of these opcodes are reserved for future instructions. The opcode values for areas II and III are
identical (06H–FFH). To distinguish between the two areas in binary mode, the opcodes in area
III are given the prefix A5H. The area III opcodes are thus A506H–A5FFH.
Figure 4-8 shows the opcode map for source mode. Areas II and III have switched places (com-
pare with Figure 4-7). In source mode, opcodes for instructions in area II require the A5F escape
prefix while opcodes for instructions in area III (MCS 251 architecture) do not.
To illustrate the difference between the binary-mode and source-mode opcodes, Table 4-4 shows
the opcode assignments for three sample instructions.
Table 4-4. Examples of Opcodes in Binary and Source Modes
Opcode
Instruction
Binary Mode
14H
Source Mode
DEC A
14H
SUBB A,R4
SUB R4,R4
9CH
A59CH
9CH
A59CH
4.6.1 Selecting Binary Mode or Source Mode
If you have code that was written for an MCS 51 microcontroller and you want to run it unmod-
ified on an MCS 251 microcontroller, choose binary mode. You can use the object code without
reassembling the source code. You can also assemble the source code with an assembler for the
MCS 251 architecture and have it produce object code that is binary-compatible with MCS 51
microcontrollers. The remainder of this section discusses the selection of binary mode or source
mode for code that may contain instructions from both architectures.
An instruction with a prefixed opcode requires one more byte for code storage, and if an addition-
al fetch is required for the extra byte, the execution time is increased by one state. This means that
using fewer prefixed opcodes produces more efficient code.
If a program uses only instructions from the MCS 51 architecture, the binary-mode code is more
efficient because it uses no prefixes. On the other hand, if a program uses many more new instruc-
tions than instructions from the MCS 51 architecture, source mode is likely to produce more ef-
ficient code. For a program where the choice is not clear, the better mode can be found by
experimenting with a simulator.
4-14
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DEVICE CONFIGURATION
A5H Prefix
6H FH
0H
5H 6H
FH
0H
0H
I
II
III
FH
FH
MCS® 51
MCS 51
MCS 251
Architecture
Architecture
Architecture
A4131-01
Figure 4-7. Binary Mode Opcode Map
A5H Prefix
6H FH
0H
5H 6H
FH
0H
0H
I
III
II
FH
FH
MCS® 51
MCS 251
MCS 51
Architecture
Architecture
Architecture
A4130-01
Figure 4-8. Source Mode Opcode Map
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4.7 MAPPING ON-CHIP CODE MEMORY TO DATA MEMORY (EMAP#)
For devices with 16 Kbytes of on-chip code memory (87C251SB, SQ and 83C251SB, SQ), the
EMAP# bit (UCONFIG1.0) provides the option of accessing the upper half of on-chip code mem-
ory as data memory. This allows code constants to be accessed as data in region 00: using direct
addressing. See section 3.2.2.1, “Accessing On-chip Code Memory in Region 00:,” for the exact
conditions required for this mapping to be effective.
EMAP# = 0. For 87C251SB/83C251SB and 87C251SQ/83C251SQ, the upper 8 Kbytes of on-
chip code memory (FF:2000–FF:3FFFH) are mapped to locations 00:E000H–00:FFFFH.
EMAP# = 1. Mapping of on-chip code memory to region 00: does not occur. Addresses in the
range 00:E000H–00:FFFFH access external RAM.
4.8 INTERRUPT MODE (INTR)
The INTR bit (UCONFIG1.4) determines what bytes are stored on the stack when an interrupt
occurs and how the RETI (Return from Interrupt) instruction restores operation.
For INTR = 0, an interrupt pushes the two lower bytes of the PC onto the stack in the following
order: PC.7:0, PC.15:8. The RETI instruction pops these two bytes in the reverse order and uses
them as the 16-bit return address in region FF:.
For INTR = 1, an interrupt pushes the three PC bytes and the PSW1 register onto the stack in the
following order: PSW1, PC.23:16, PC.7:0, PC.15:8. The RETI instruction pops these four bytes
and then returns to the specified 24-bit address, which can be anywhere in the 16-Mbyte address
space.
4-16
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5
Programming
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CHAPTER 5
PROGRAMMING
The instruction set for the MCS® 251 architecture is a superset of the instruction set for the
MCS® 51 architecture. This chapter describes the addressing modes and summarizes the instruc-
tion set, which is divided into data instructions, bit instructions, and control instructions. Appen-
dix A, “Instruction Set Reference,” contains an opcode map and a detailed description of each
instruction. The program status words PSW and PSW1 are also described.
NOTE
The instruction execution times given in Appendix A are for code executing
from on-chip code memory and for data that is read from and written to on-
chip RAM. Execution times are increased by executing code from external
memory, accessing peripheral SFRs, accessing data in external memory, using
real time wait states, using RD#/WR#/PSEN# preprogrammed wait states, or
extending the ALE pulse.
For some instructions, accessing the port SFRs (Px, x = 3:0) increases the
execution time. These cases are noted individually in the tables in Appendix A.
5.1 SOURCE MODE OR BINARY MODE OPCODES
Source mode and Binary mode refer to the two ways of assigning opcodes to the instruction set
of the MCS 251 architecture. Depending on the application, one mode or the other may produce
more efficient code. The mode is established during device reset based on the value of the SRC
bit in configuration byte UCONFIG0. For information regarding the selection of the opcode
mode, see section 4.6, “Opcode Configurations (SRC).”
5.2 PROGRAMMING FEATURES OF THE MCS® 251 ARCHITECTURE
The instruction set for MCS 251 microcontrollers provides the user with new instructions that ex-
ands. (In comparison with 8-bit and 16-bit operands, 32-bit operands are accessed with fewer ad-
dressing modes.) This capability increases the ease and efficiency of programming MCS 251
microcontrollers in a high-level language such as C.
The instruction set is divided into data (refer to section 5.3, “Data Instructions”), bits (see section
5.4, “Bit Instructions”), and control instructions (see section 5.5, “Control Instructions”). Data in-
structions process 8-bit, 16-bit, and 32-bit data; bit instructions manipulate bits; and control in-
structions manage program flow.
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5.2.1 Data Types
Table 5-1 lists the data types that are addressed by the instruction set. Words or dwords (double
words) can be in stored memory starting at any byte address; alignment on two-byte or four-byte
boundaries is not required. Words and dwords are stored in memory and the register file in big
endien form.
Table 5-1. Data Types
Data Type
Number of Bits
Bit
1
8
Byte
Word
16
32
Dword (Double Word)
5.2.1.1
Order of Byte Storage for Words and Double Words
MCS 251 microcontrollers store words (2 bytes) and double words (4 bytes) in memory and in
word or double word is stored in the memory byte specified in the instruction; the remaining bytes
are stored at higher addresses, with the least significant byte (LSB) at the highest address. Words
and double words can be stored in memory starting at any byte address. In the register file, the
MSB is stored in the lowest byte of the register specified in the instruction. For a description of
the register file, see section 3.3, “8XC251SA, SB, SP, SQ Register File.” The code fragment in
Figure 5-1 illustrates the storage of words and double words in big endien form.
5.2.2 Register Notation
In register-addressing instructions, specific indices denote the registers that can be used in that
instruction. For example, the instruction ADD A,Rn uses “Rn” to denote any one of R0, R1, ...,
R7; i.e., the range of n is 0–7. The instruction ADD Rm,#data uses “Rm” to denote R0, R1, ...,
R15; i.e., the range of m is 0–15. Table 5-2 summarizes the notation used for the register indices.
When an instruction contains two registers of the same type (e.g., MOV Rmd,Rms) the first index
“d” denotes “destination” and the second index “s” denotes “source.”
5.2.3 Address Notation
In the MCS 251 architecture, memory addresses include a region number (00:, 01:, ..., FF:) (Fig-
ure 3-4 on page 3-6). SFR addresses have a prefix “S:” (S:000H–S:1FFH). The distinction be-
tween memory addresses and SFR addresses is necessary because memory locations 00:0000H–
00:01FFH and SFR locations S:000H–S:1FFH can both be directly addressed in an instruction.
5-2
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PROGRAMMING
Memory
200H 201H 202H 203H
MOV WR0,#A3B6H
MOV 00:0201H,WR0
A3H
B6H
MOV DR4,#0000C4D7H
Register File
0
1
2
3
4
5
6
7
A3H
B6H
00H
00H
C4H
D7H
WR0
DR4
Contents of register file and memory after execution
A4242-01
Figure 5-1. Word and Double-word Storage in Big Endien Form
Table 5-2. Notation for Byte Registers, Word Registers, and Dword Registers
Register
Type
Register
Symbol
Destination
Register
Source
Register
Register Range
Ri
—
—
R0, R1
R0–R7
R0–R15
Byte
Rn
—
—
Rm
WRj
DRk
Rmd
WRjd
DRkd
Rms
WRjs
DRks
Word
WR0, WR2, WR4, ..., WR30
Dword
DR0, DR4, DR8, ..., DR28, DR56, DR60
Instructions in the MCS 51 architecture use 80H–FFH as addresses for both memory locations
and SFRs, because memory locations are addressed only indirectly and SFR locations are ad-
dressed only directly. For compatibility, software tools for MCS 251 controllers recognize this
notation for instructions in the MCS 51 architecture. No change is necessary in any code written
for MCS 51 controllers.
For new instructions in the MCS 251 architecture, the memory region prefixes (00:, 01, ..., FF:)
and the SFR prefix (S:) are required. Also, software tools for the MCS 251 architecture permit
00: to be used for memory addresses 00H–FFH and permit the prefix S: to be used for SFR ad-
dresses in instructions in the MCS 51 architecture.
5-3
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5.2.4 Addressing Modes
The MCS 251 architecture supports the following addressing modes:
• register addressing: The instruction specifies the register that contains the operand.
• immediate addressing: The instruction contains the operand.
• direct addressing: The instruction contains the operand address.
• indirect addressing: The instruction specifies the register that contains the operand address.
• displacement addressing: The instruction specifies a register and an offset. The operand
address is the sum of the register contents (the base address) and the offset.
• relative addressing: The instruction contains the signed offset from the next instruction to
the target address (the address for transfer of control, e.g., the jump address).
• bit addressing: The instruction contains the bit address.
More detailed descriptions of the addressing modes are given in sections 5.3.1, “Data Addressing
Modes," 5.4.1, “Bit Addressing," and 5.5.1, “Addressing Modes for Control Instructions.”
5.3 DATA INSTRUCTIONS
Data instructions consist of arithmetic, logical, and data-transfer instructions for 8-bit, 16-bit, and
32-bit data. This section describes the data addressing modes and the set of data instructions.
5.3.1 Data Addressing Modes
This section describes the data-addressing modes, which are summarized in two tables: Table 5-3
structions in the MCS 251 architecture.
NOTE
References to registers R0–R7, WR0–WR6, DR0, and DR2 always refer to the
register bank that is currently selected by the PSW and PSW1 registers (see
section 5.6, “Program Status Words”). Registers in all banks (active and
inactive) can be accessed as memory locations in the range 00H–1FH.
Instructions from the MCS 51 architecture access external memory through the
region of memory specified by byte DPXL in the extended data pointer
register, DPX (DR56). Following reset, DPXL contains 01H, which maps the
external memory to region 01:. You can specify a different region by writing to
DR56 or the DPXL SFR. See section 3.3.2, “Dedicated Registers.”
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5.3.1.1
Register Addressing
Both architectures address registers directly.
• MCS 251 architecture. In the register addressing mode, the operand(s) in a data instruction
are in byte registers (R0–R15), word registers (WR0, WR2, ..., WR30), or dword registers
(DR0, DR4, ..., DR28, DR56, DR60).
• MCS 51 architecture. Instructions address registers R0–R7 only.
5.3.1.2
Immediate
Both architectures use immediate addressing.
• MCS 251 architecture. In the immediate addressing mode, the instruction contains the data
operand itself. Byte operations use 8-bit immediate data (#data); word operations use 16-bit
immediate data (#data16). Dword operations use 16-bit immediate data in the lower word,
and either zeros in the upper word (denoted by #0data16), or ones in the upper word
(denoted by #1data16). MOV instructions that place 16-bit immediate data into a dword
register (DRk), place the data either into the upper word while leaving the lower word
unchanged, or into the lower word with a sign extension or a zero extension.
The increment and decrement instructions contain immediate data (#short = 1, 2, or 4) that
specifies the amount of the increment/decrement.
• MCS 51 architecture. Instructions use only 8-bit immediate data (#data).
5.3.1.3
Direct
• MCS 251 architecture. In the direct addressing mode, the instruction contains the address of
the data operand. The 8-bit direct mode addresses on-chip RAM (dir8 = 00:0000H–
00:007FH) as both bytes and words, and addresses the SFRs (dir8 = S:080H–S:1FFH) as
bytes only. (See the notes in section 5.3.1, “Data Addressing Modes,” regarding SFRs in the
MCS 251 architecture.) The 16-bit direct mode addresses both bytes and words in memory
(dir16 = 00:0000H–00:FFFFH).
• MCS 51 architecture. The 8-bit direct mode addresses 256 bytes of on-chip RAM (dir8 =
00H–7FH) as bytes only and the SFRs (dir8 = 80H–FFH) as bytes only.
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®
Table 5-3. Addressing Modes for Data Instructions in the MCS 51 Architecture
Address Range of
Operand
Assembly Language
Reference
Mode
Comments
R0–R7
(Bank selected by PSW)
Register
00H–1FH
Immediate
Direct
Operand in Instruction #data = #00H–#FFH
00H–7FH
dir8 = 00H–7FH
dir8 = 80H–FFH
On-chip RAM
SFRs
SFR address
or SFR mnemonic.
Accesses on-chip RAM or the
lowest 256 bytes of external
data memory (MOVX).
00H–FFH
@R0, @R1
Indirect
Accesses external data
memory (MOVX).
0000H–FFFFH
0000H–FFFFH
@DPTR, @A+DPTR
@A+DPTR, @A+PC
Accesses region FF: of code
memory (MOVC).
5.3.1.4
Indirect
In arithmetic and logical instructions that use indirect addressing, the source operand is always a
byte, and the destination is either the accumulator or a byte register (R0–R15). The source address
is a byte, word, or dword. The two architectures do indirect addressing via different registers:
• MCS 251 architecture. Memory is indirectly addressed via word and dword registers:
— Word register (@WRj, j = 0, 2, 4, ..., 30). The 16-bit address in WRj can access
locations 00:0000H–00:FFFFH.
— Dword register (@DRk, k = 0, 4, 8, ..., 28, 56, and 60). The 24 least significant bits can
access the entire 16-Mbyte address space. The upper eight bits of DRk must be 0. If
you use DR60 as a general data pointer, be aware that DR60 is the extended stack
pointer register SPX.
• MCS 51 architecture. Instructions use indirect addressing to access on-chip RAM, code
memory, and external data RAM. See the notes in section 5.3.1, “Data Addressing Modes,”
regarding the region of external data RAM that is addressed by instructions in the MCS 51
architecture.
— Byte register (@Ri, i = 1, 2). Registers R0 and R1 indirectly address on-chip memory
locations 00H–FFH and the lowest 256 bytes of external data RAM.
— 16-bit data pointer (@DPTR or @A+DPTR). The MOVC and MOVX instructions use
these indirect modes to access code memory and external data RAM.
— 16-bit program counter (@A+PC). The MOVC instruction uses this indirect mode to
access code memory.
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®
Address Range of
Operand
Assembly Language
Notation
Mode
Comments
R0–R7, WR0–WR6, DR0, and
DR2 are in the register bank
currently selected by the
PSW and PSW1.
00:0000H–00:001FH
(R0–R7, WR0–WR3,
DR0, DR2) (1)
R0–R15, WR0–WR30,
Register
DR0–DR28, DR56, DR60
Immediate,
2 bits
N.A. (Operand is in the
instruction)
Used only in increment and
#short = 1, 2, or 4
Immediate,
8 bits
N.A. (Operand is in the
instruction)
#data8 = #00H–#FFH
Immediate,
16 bits
N.A. (Operand is in the
instruction)
#data16 = #0000H–#FFFFH
dir8 = 00:0000H–00:007FH
00:0000H–00:007FH
On-chip RAM
SFR address
Direct,
8 address bits
dir8 = S:080H–S:1FFH (2)
SFRs
or SFR mnemonic
Direct,
16 address bits
00:0000H–00:FFFFH
00:0000H–00:FFFFH
00:0000H–FF:FFFFH
dir16 = 00:0000H–00:FFFFH
@WR0–@WR30
Indirect,
16 address bits
Indirect,
24 address bits
@DR0–@DR30, @DR56,
@DR60
Upper 8 bits of DRk must be
00H.
@WRj + dis16 =
Displacement,
16 address bits
Offset is signed; address
wraps around in region 00:.
00:0000H–00:FFFFH
00:0000H–FF:FFFFH
@WR0 + 0H through
@WR30 + FFFFH
@DRk + dis24 =
@DR0 + 0H through
@DR28 + FFFFH,
@DR56 + (0H–FFFFH),
@DR60 + (0H–FFFFH)
Displacement,
24 address bits
Offset is signed, upper 8 bits
of DRk must be 00H.
NOTES:
1. These registers are accessible in the memory space as well as in the register file (see section 3.3,
“8XC251SA, SB, SP, SQ Register File.”
2. The MCS 251 architecture supports SFRs in locations S:000H–S:1FFH; however, in the 8XC251Sx,
all SFRs are in the range S:080H–S:0FFH.
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5.3.1.5
Displacement
Several move instructions use displacement addressing to move bytes or words from a source to
a destination. Sixteen-bit displacement addressing (@WRj+dis16) accesses indirectly the lowest
64 Kbytes in memory. The base address can be in any word register WRj. The instruction contains
a 16-bit signed offset which is added to the base address. Only the lowest 16 bits of the sum are
used to compute the operand address. If the sum of the base address and a positive offset exceeds
FFFFH, the computed address wraps around within region 00: (e.g. F000H + 2005H becomes
1005H). Similarly, if the sum of the base address and a negative offset is less than zero, the com-
puted address wraps around the top of region 00: (e.g., 2005H + F000H becomes 1005H).
Twenty-four-bit displacement addressing (@DRk+dis24) accesses indirectly the entire 16-Mbyte
address space. The base address must be in DR0, DR4, ..., DR24, DR28, DR56, or DR60. The
upper byte in the dword register must be zero. The instruction contains a 16-bit signed offset
which is added to the base address.
5.3.2 Arithmetic Instructions
The set of arithmetic instructions is greatly expanded in the MCS 251 architecture. The ADD and
SUB instructions (Table A-19 on page A-14) operate on byte and word data that is accessed in
several ways:
• as the contents of the accumulator, a byte register (Rn), or a word register (WRj)
• in the instruction itself (immediate data)
• in memory via direct or indirect addressing
The ADDC and SUBB instructions (Table A-19) are the same as those for MCS 51 microcontrol-
lers.
The CMP (compare) instruction (Table A-20 on page A-15) calculates the difference of two bytes
or words and then writes to flags CY, OV, AC, N, and Z in the PSW and PSW1 registers. The
difference is not stored. The operands can be addressed in a variety of modes. The most frequent
use of CMP is to compare data or addresses preceding a conditional jump instruction.
Table A-21 on page A-16 lists the INC (increment) and DEC (decrement) instructions. The in-
structions for MCS 51 microcontrollers are supplemented by instructions that can address byte,
word, and dword registers and increment or decrement them by 1, 2, or 4 (denoted by #short).
These instructions are supplied primarily for register-based address pointers and loop counters.
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The MCS 251 architecture provides the MUL (multiply) and DIV (divide) instructions for un-
signed 8-bit and 16-bit data (Table A-22 on page A-16). Signed multiply and divide are left for
the user to manage through a conversion process. The following operations are implemented:
• eight-bit multiplication: 8 bits × 8 bits → 16 bits
• sixteen-bit multiplication: 16 bits × 16 bits → 32 bits
÷
• eight-bit division: 8 bits 8 bits → 16 bits (8-bit quotient, 8-bit remainder)
• sixteen-bit division: 16 bits ÷ 16 bits → 32 bits (16-bit quotient, 16-bit remainder)
These instructions operate on pairs of byte registers (Rmd,Rms), word registers (WRjd,WRjs), or
the accumulator and B register (A,B). For 8-bit register multiplies, the result is stored in the word
register that contains the first operand register. For example, the product from an instruction
MUL R3,R8 is stored in WR2. Similarly, for 16-bit multiplies, the result is stored in the dword
register that contains the first operand register. For example, the product from the instruction
MUL WR6,WR18 is stored in DR4.
For 8-bit divides, the operands are byte registers. The result is stored in the word register that con-
tains the first operand register. The quotient is stored in the lower byte, and the remainder is stored
in the higher byte. A 16-bit divide is similar. The first operand is a word register, and the result is
stored in the double word register that contains that word register. If the second operand (the di-
visor) is zero, the overflow flag (OV) is set and the other bits in PSW and PSW1 are meaningless.
5.3.3 Logical Instructions
The MCS 251 architecture provides a set of instructions that perform logical operations. The
ANL, ORL, and XRL (logical AND, logical OR, and logical exclusive OR) instructions operate
on bytes and words that are accessed via several addressing modes (Table A-23 on page A-17).
A byte register, word register, or the accumulator can be logically combined with a register, im-
mediate data, or data that is addressed directly or indirectly. These instructions affect the Z and N
flags.
In addition to the CLR (clear), CPL (complement), SWAP (swap), and four rotate instructions that
operate on the accumulator, MCS 251 microcontrollers have three shift commands for byte and
word registers:
• SLL (Shift Left Logical) shifts the register one bit left and replaces the LSB with 0
• SRL (Shift Right Logical) shifts the register one bit right and replaces the MSB with 0
• SRA (Shift Right Arithmetic) shifts the register one bit right; the MSB is unchanged
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5.3.4 Data Transfer Instructions
Data transfer instructions copy data from one register or memory location to another. These in-
structions include the move instructions (Table A-24 on page A-19) and the exchange, push, and
pop instructions (Table A-25 on page A-22). Instructions that move only a single bit are listed
with the other bit instructions in Table A-26 on page A-23.
MOV (Move) is the most versatile instruction, and its addressing modes are expanded in the
MCS 251 architecture. MOV can transfer a byte, word, or dword between any two registers or
between a register and any location in the address space.
The MOVX (Move External) instruction moves a byte from external memory to the accumulator
or from the accumulator to memory. The external memory is in the region specified by DPXL,
whose reset value is 01H. See section 3.3.2, “Dedicated Registers.”
The MOVC (Move Code) instruction moves a byte from code memory (region FF:) to the accu-
mulator.
MOVS (Move with Sign Extension) and MOVZ (Move with Zero Extension) move the contents
of an 8-bit register to the lower byte of a 16-bit register. The upper byte is filled with the sign bit
(MOVS) or zeros (MOVZ). The MOVH (Move to High Word) instruction places 16-bit immedi-
ate data into the high word of a dword register.
The XCH (Exchange) instruction interchanges the contents of the accumulator with a register or
memory location. The XCHD (Exchange Digit) instruction interchanges the lower nibble of the
accumulator with the lower nibble of a byte in on-chip RAM. XCHD is useful for BCD (binary
coded decimal) operations.
The PUSH and POP instructions facilitate storing information (PUSH) and then retrieving it
(POP) in reverse order. Push can push a byte, a word, or a dword onto the stack, using the imme-
diate, direct, or register addressing modes. POP can pop a byte or a word from the stack to a reg-
ister or to memory.
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5.4 BIT INSTRUCTIONS
A bit instruction addresses a specific bit in a memory location or SFR. There are four categories
of bit instructions:
• SETB (Set Bit), CLR (Clear Bit), CPL (Complement Bit). These instructions can set, clear
or complement any addressable bit.
• ANL (And Logical), ANL/ (And Logical Complement), ORL (OR Logical), ORL/ (Or
or its complement with the CY flag.
• MOV (Move) instructions transfer any addressable bit to the carry (CY) bit or vice versa.
• Bit-conditional jump instructions execute a jump if the bit has a specified state. The bit-
conditional jump instructions are classified with the control instructions and are described
in section 5.5.2, “Conditional Jumps.”
5.4.1 Bit Addressing
The bits that can be individually addressed are in the on-chip RAM and the SFRs (Table 5-5). The
bit instructions that are unique to the MCS 251 architecture can address a wider range of bits than
the instructions from the MCS 51 architecture.
the MCS 51 architecture, a bit (denoted by bit51) can be specified in terms of its location within
a certain register, or it can be specified by a bit address in the range 00H–7FH. The MCS 251
architecture does not have bit addresses as such. A bit can be addressed by name or by its location
within a certain register, but not by a bit address.
Table 5-6 illustrates bit addressing in the two architectures by using two sample bits:
• RAMBIT is bit 5 in RAMREG, which is location 23H. “RAMBIT” and “RAMREG” are
assumed to be defined in user code.
• IT1 is bit 2 in TCON, which is an SFR at location 88H.
Table 5-5. Bit-addressable Locations
Bit-addressable Locations
Architecture
On-chip RAM
SFRs
®
MCS 251 Architecture
20H–7FH
All defined SFRs
SFRs with addresses ending in 0H or 8H:
80H, 88H, 90H, 98H, ..., F8H
MCS 51 Architecture
20H–2FH
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Table 5-7 lists the addressing modes for bit instructions and Table A-26 on page A-23 summarizes
the bit instructions. “Bit” denotes a bit that is addressed by a new instruction in the MCS 251 ar-
chitecture and “bit51” denotes a bit that is addressed by an instruction in the MCS 51 architecture.
Table 5-6. Addressing Two Sample Bits
®
Addressing
Mode
MCS 51
MCS 251
Architecture
Location
Architecture
Register Name
Register Address
Bit Name
RAMREG.5
23H.5
RAMBIT
1DH
RAMREG.5
23H.5
RAMBIT
NA
On-chip RAM
Bit Address
Register Name
Register Address
Bit Name
TCON.2
88.2H
IT1
TCON.2
S:88.2H
IT1
SFR
Bit Address
8A
NA
Table 5-7. Addressing Modes for Bit Instructions
Architecture Variants
Bit Address
Memory/SFR Address
20H.0–7FH.7
Comments
®
MCS 251
Architecture
(bit)
Memory NA
SFR NA
Memory 00H–7FH
All defined SFRs
20H.0–7FH.7
MCS 51
Architecture
(bit51)
SFRs are not defined
at all bit-addressable
locations.
XXH.0–XXH.7, where XX = 80,
88, 90, 98, ..., F0, F8.
SFR
80H–F8H
5.5 CONTROL INSTRUCTIONS
Control instructions—instructions that change program flow—include calls, returns, and condi-
tional and unconditional jumps (see Table A-27 on page A-24). Instead of executing the next in-
struction in the queue, the processor executes a target instruction. The control instruction provides
the address of a target instruction either implicitly, as in a return from a subroutine, or explicitly,
in the form of a relative, direct, or indirect address.
MCS 251 microcontrollers have a 24-bit program counter (PC), which allows a target instruction
to be anywhere in the 16-Mbyte address space. However, as discussed in this section, some con-
trol instructions restrict the target address to the current 2-Kbyte or 64-Kbyte address range by
allowing only the lowest 11 or lowest 16 bits of the program counter to change.
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5.5.1 Addressing Modes for Control Instructions
Table 5-8 lists the addressing modes for the control instructions.
• Relative addressing: The control instruction provides the target address as an 8-bit signed
offset (rel) from the address of the next instruction.
• Direct addressing: The control instruction provides a target address, which can have 11 bits
(addr11), 16 bits (addr16), or 24 bits (addr24). The target address is written to the PC.
— addr11: Only the lower 11 bits of the PC are changed; i.e., the target address must be in
the current 2-Kbyte block (the 2-Kbyte block that includes the first byte of the next
instruction).
— addr16: Only the lower 16 bits of the PC are changed; i.e., the target address must be in
the current 64-Kbyte region (the 64-Kbyte region that includes the first byte of the next
instruction).
— addr24: The target address can be anywhere in the 16-Mbyte address space.
• Indirect addressing: There are two types of indirect addressing for control instructions:
— For the instructions LCALL @WRj and LJMP @WRj, the target address is in the
current 64-Kbyte region. The 16-bit address in WRj is placed in the lower 16 bits of the
PC. The upper eight bits of the PC remain unchanged from the address of the next
instruction.
— For the instruction JMP @A+DPTR, the sum of the accumulator and DPTR is placed in
the lower 16 bits of the PC, and the upper eight bits of the PC are FF:, which restricts
the target address to the code memory space of the MCS 51 architecture.
Table 5-8. Addressing Modes for Control Instructions
Address Bits
Description
Address Range
Provided
Relative, 8-bit relative address (rel)
Direct, 11-bit target address (addr11)
Direct, 16-bit target address (addr16)
Direct, 24-bit target address (addr24)†
Indirect (@WRj)†
8
-128 to +127 from first byte of next instruction
Current 2 Kbytes
11
16
24
16
Current 64 Kbytes
00:0000H–FF:FFFFH
Current 64 Kbytes
64-Kbyte region specified by DPXL (reset
value = 01H)
Indirect (@A+DPTR)
16
®
†These modes are not used by instructions in the MCS 51 architecture.
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5.5.2 Conditional Jumps
The MCS 251 architecture supports bit-conditional jumps, compare-conditional jumps, and
jumps based on the value of the accumulator. A bit-conditional jump is based on the state of a bit.
In a compare-conditional jump, the jump is based on a comparison of two operands. All condi-
tional jumps are relative, and the target address (rel) must be in the current 256-byte block of
• JB (Jump on Bit): Jump if the bit is set.
• JNB (Jump on Not Bit): Jump if the bit is clear.
• JBC (Jump on Bit then Clear it): Jump if the bit is set; then clear it.
Section 5.4.1, “Bit Addressing,” describes the bit addressing used in these instructions.
Compare-conditional jumps test a condition resulting from a compare (CMP) instruction that is
assumed to precede the jump instruction. The jump instruction examines the PSW and PSW1 reg-
isters and interprets their flags as though they were set or cleared by a compare (CMP) instruction.
Actually, the state of each flag is determined by the last instruction that could have affected that
flag.
The condition flags are used to test one of the following six relations between the operands:
• greater than (>), less than (<)
• greater than or equal (≥), less than or equal (≤)
For each relation there are two instructions, one for signed operands and one for unsigned oper-
ands (Table 5-9).
Table 5-9. Compare-conditional Jump Instructions
Relation
Operand
Type
=
≠
>
<
≥
≤
Unsigned
Signed
JG
JL
JGE
JLE
JE
JNE
JSG
JSL
JSGE
JSLE
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5.5.3 Unconditional Jumps
There are five unconditional jumps. NOP and SJMP jump to addresses relative to the program
counter. AJMP, LJMP, and EJMP jump to direct or indirect addresses.
• NOP (No Operation) is an unconditional jump to the next instruction.
• SJMP (Short Jump) jumps to any instruction within -128 to 127 of the next instruction.
• AJMP (Absolute Jump) changes the lowest 11 bits of the PC to jump anywhere within the
current 2-Kbyte block of memory. The address can be direct or indirect.
• LJMP (Long Jump) changes the lowest 16 bits of the PC to jump anywhere within the
current 64-Kbyte region.
• EJMP (Extended Jump) changes all 24 bits of the PC to jump anywhere in the 16-Mbyte
address space. The address can be direct or indirect.
5.5.4 Calls and Returns
The MCS 251 architecture provides relative, direct, and indirect calls and returns.
ACALL (Absolute Call) pushes the lower 16 bits of the next instruction address onto the stack
and then changes the lower 11 bits of the PC to the 11-bit address specified by the instruction.
The call is to an address that is in the same 2-Kbyte block of memory as the address of the next
instruction.
LCALL (Long Call) pushes the lower 16 bits of the next-instruction address onto the stack and
then changes the lower 16 bits of the PC to the 16-bit address specified by the instruction. The
call is to an address in the same 64-Kbyte block of memory as the address of the next instruction.
ECALL (Extended Call) pushes the 24 bits of the next instruction address onto the stack and then
changes the 24 bits of the PC to the 24-bit address specified by the instruction. The call is to an
address anywhere in the 16-Mbyte memory space.
RET (Return) pops the top two bytes from the stack to return to the instruction following a sub-
routine call. The return address must be in the same 64-Kbyte region.
ERET (Extended Return) pops the top three bytes from the stack to return to the address follow-
ing a subroutine call. The return address can be anywhere in the 16-Mbyte address space.
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RETI (Return from Interrupt) provides a return from an interrupt service routine. The operation
of RETI depends on the INTR bit in the UCONFIG1 or CONFIG1 configuration byte:
• For INTR = 0, an interrupt pushes the two lower bytes of the PC onto the stack in the
following order: PC.7:0, PC.15:8. The RETI instruction pops these two bytes and uses them
as the 16-bit return address in region FF:. RETI also restores the interrupt logic to accept
additional interrupts at the same priority level as the one just processed.
• For INTR = 1, an interrupt pushes the three PC bytes and PSW1 onto the stack in the
following order: PSW1, PC.23:16, PC.7:0, PC.15:8. The RETI instruction pops these four
bytes and then returns to the specified 24-bit address, which can be anywhere in the 16-
Mbyte address space. RETI also clears the interrupt request line. (See the note in Table 5-8
regarding compatibility with code written for MCS 51 microcontrollers.)
ler.
5.6 PROGRAM STATUS WORDS
The Program Status Word (PSW) register and the Program Status Word 1 (PSW1) register contain
four types of bits (Figures 5-2 and 5-3):
• CY, AC, OV, N, and Z are flags set by hardware to indicate the result of an operation.
• The P bit indicates the parity of the accumulator.
registers R0–R7.
• F0 and UD are available to the user as general-purpose flags.
The PSW and PSW1 registers are read/write registers; however, the parity bit in the PSW is not
affected by a write. Individual bits can be addressed with the bit instructions (section 5.4, “Bit
(section 5.5.2, “Conditional Jumps”).
The PSW register is identical to the PSW register in MCS 51 microcontrollers. The PSW1 regis-
ter exists only in MCS 251 microcontrollers. Bits CY, AC, RS0, RS1, and OV in PSW1 are iden-
tical to the corresponding bits in PSW; i.e., the same bit can be accessed in either register. Table
5-10 lists the instructions that affect the CY, AC, OV, N, and Z bits.
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Table 5-10. The Effects of Instructions on the PSW and PSW1 Flags
Flags Affected (1), (5)
Instruction Type
Instruction
CY
OV
AC (2)
N
Z
ADD, ADDC, SUB,
SUBB, CMP
X
X
X
X
X
INC, DEC
MUL, DIV (3)
DA
X
X
X
X
X
X
X
X
Arithmetic
0
X
X
ANL, ORL, XRL, CLR A,
CPL A, RL, RR, SWAP
Logical
RLC, RRC, SRL, SLL,
SRA (4)
X
X
X
X
CJNE
DJNE
X
X
X
X
Program Control
NOTES:
1. X = the flag can be affected by the instruction.
0 = the flag is cleared by the instruction.
2. The AC flag is affected only by operations on 8-bit operands.
3. If the divisor is zero, the OV flag is set and the other bits are meaningless.
4. For SRL, SLL, and SRA instructions, the last bit shifted out is stored in the CY bit.
5. The parity bit (PSW.0) is set or cleared by instructions that change the contents of the
accumulator (ACC, Register R11).
5-17
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.
Address:
Reset State:
S:D0H
0000 0000B
PSW
7
0
CY
AC
F0
RS1
RS0
OV
UD
P
Bit
Number
Bit
Mnemonic
Function
7
CY
Carry Flag:
The carry flag is set by an addition instruction (ADD, ADDC) if there is a
carry out of the MSB. It is set by a subtraction (SUB, SUBB) or compare
(CMP) if a borrow is needed for the MSB. The carry flag is also affected
by some rotate and shift instructions, logical bit instructions, bit move
(see Table 5-10).
6
AC
Auxiliary Carry Flag:
The auxiliary carry flag is affected only by instructions that address 8-bit
operands. The AC flag is set if an arithmetic instruction with an 8-bit
operand produces a carry out of bit 3 (from addition) or a borrow into bit
3 (from subtraction). Otherwise, it is cleared. This flag is useful for BCD
arithmetic (see Table 5-10).
5
F0
Flag 0:
This general-purpose flag is available to the user.
4:3
RS1:0
Register Bank Select Bits 1 and 0:
These bits select the memory locations that comprise the active bank of
the register file (registers R0–R7).
RS1 RS0
Bank Address
0
0
1
1
0
1
0
1
0
1
2
3
00H–07H
08H–0FH
10H–17H
18H–1FH
2
OV
Overflow Flag:
This bit is set if an addition or subtraction of signed variables results in
an overflow error (i.e., if the magnitude of the sum or difference is too
great for the seven LSBs in 2’s-complement representation). The
overflow flag is also set if a multiplication product overflows one byte or if
a division by zero is attempted.
1
0
UD
P
User-definable Flag:
This general-purpose flag is available to the user.
Parity Bit:
This bit indicates the parity of the accumulator. It is set if an odd number
of bits in the accumulator are set. Otherwise, it is cleared. Not all instruc-
tions update the parity bit. The parity bit is set or cleared by instructions
that change the contents of the accumulator (ACC, Register R11).
Figure 5-2. Program Status Word Register
5-18
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PROGRAMMING
.
Address:
Reset State:
S:D1H
0000 0000B
PSW1
7
0
CY
AC
N
RS1
RS0
OV
Z
—
Bit
Number
Bit
Mnemonic
Function
7
6
5
CY
Carry Flag:
Identical to the CY bit in the PSW register (Figure 5-2).
AC
N
Auxiliary Carry Flag:
Identical to the AC bit in the PSW register (Figure 5-2).
Negative Flag:
This bit is set if the result of the last logical or arithmetic operation was
negative (i.e., bit 15 = 1). Otherwise it is cleared.
4–3
2
RS1:0
OV
Register Bank Select Bits 0 and 1:
Identical to the RS1:0 bits in the PSW register (Figure 5-2).
Overflow Flag:
Identical to the OV bit in the PSW register (Figure 5-2).
1
Z
Zero Flag:
This flag is set if the result of the last logical or arithmetic operation is
zero. Otherwise it is cleared.
0
—
Reserved:
The value read from this bit is indeterminate. Write a “0” to this bit.
Figure 5-3. Program Status Word 1 Register
5-19
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6
Interrupt System
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CHAPTER 6
INTERRUPT SYSTEM
6.1 OVERVIEW
The 8XC251Sx, like other control-oriented computer architectures, employs a program interrupt
method. This operation branches to a subroutine and performs some service in response to the
interrupt. When the subroutine completes, execution resumes at the point where the interrupt oc-
curred. Interrupts may occur as a result of internal 8XC251Sx activity (e.g., timer overflow) or at
the initiation of electrical signals external to the microcontroller (e.g., serial port communication).
of interrupt service relative to normal code execution and other interrupt service routines. Seven
of the eight interrupts are enabled or disabled by the system designer and may be manipulated
dynamically.
A typical interrupt event chain occurs as follows. An internal or external device initiates an inter-
rupt-request signal. This signal, connected to an input pin (see Table 6-1) and periodically sam-
pled by the 8XC251Sx, latches the event into a flag buffer. The priority of the flag (see Table 6-2,
Interrupt System Special Function Registers) is compared to the priority of other interrupts by the
interrupt handler. A high priority causes the handler to set an interrupt flag. This signals the in-
struction execution unit to execute a context switch. This context switch breaks the current flow
of instruction sequences. The execution unit completes the current instruction prior to a save of
the program counter (PC) and reloads the PC with the start address of a software service routine.
The software service routine executes assigned tasks and as a final activity performs a RETI (re-
turn from interrupt) instruction. This instruction signals completion of the interrupt, resets the in-
terrupt-in-progress priority, and reloads the program counter. Program operation then continues
from the original point of interruption.
Table 6-1. Interrupt System Pin Signals
Signal
Name
Multiplexed
With
Type
Description
INT1:0#
I
External Interrupts 0 and 1. These inputs set bits IE1:0 in the
TCON register. If bits IT1:0 in the TCON register are set, bits IE1:0
are controlled by a negative-edge trigger on INT1#/INT0#. If bits
INT1:0# are clear, bits IE1:0 are controlled by a low level trigger on
INT1:0#.
P3.3:2
NOTE: Other signals are defined in their respective chapters and in Appendix B, “Signal Descriptions.”
6-1
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Interrupt Enable
Priority Enable
EA
Highest
Priority
Interrupt
IP
0
IE0
IT0
INT0#
EX0
1
Timer 0
INT1#
TF0
IE1
ET0
EX1
0
1
IT1
Timer 1
TF1
ET1
0
PCA
Counter
Overflow
ECF
CF
1
0
PCA
Match or
Capture
EC
ECCFx
5
CCFx
1
Receive
Transmit
RI
TI
ES
Timer 2
T2EX
TF2
EXF2
ET2
Lowest
Priority
Interrupt
A4149-01
Figure 6-1. Interrupt Control System
6-2
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INTERRUPT SYSTEM
Table 6-2. Interrupt System Special Function Registers
Mnemonic
Description
Address
S:A8H
IE0
Interrupt Enable Register. Used to enable and disable programmable
interrupts. The reset value of this register is zero (interrupts disabled).
IPL0
IPH0
Interrupt Priority Low Register. Establishes relative four-level priority for
programmable interrupts. Used in conjunction with IPH0.
S:B8H
S:B7H
programmable interrupts. Used in conjunction with IPL0.
NOTE: Other special function registers are described in their respective chapters.
6.2 8XC251SA, SB, SP, SQ INTERRUPT SOURCES
Figure 6-1 illustrates the interrupt control system. The 8XC251Sx has eight interrupt sources;
seven maskable sources and the TRAP instruction (always enabled). The maskable sources in-
clude two external interrupts (INT0# and INT1#), three timer interrupts (timers 0, 1, and 2), one
programmable counter array (PCA) interrupt, and one serial port interrupt. Each interrupt (except
TRAP) has an interrupt request flag, which can be set by software as well as by hardware (see
Table 6-3, “Interrupt Control Matrix”). For some interrupts, hardware clears the request flag
when it grants an interrupt. Software can clear any request flag to cancel an impending interrupt.
6.2.1 External Interrupts
External interrupts INT0# and INT1# (INTx#) pins may each be programmed to be level-trig-
gered or edge-triggered, dependent upon bits IT0 and IT1 in the TCON register (see Figure 8-6
on page 8-8). If ITx = 0, INTx# is triggered by a detected low at the pin. If ITx = 1, INTx# is neg-
ative-edge triggered. External interrupts are enabled with bits EX0 and EX1 (EXx) in the IE0 reg-
ister (see Figure 6-2, “Interrupt Enable Register”). Events on the external interrupt pins set the
interrupt request flags IEx in TCON. These request bits are cleared by hardware vectors to service
routines only if the interrupt is negative-edge triggered. If the interrupt is level-triggered, the in-
terrupt service routine must clear the request bit. External hardware must deassert INTx# before
the service routine completes, or an additional interrupt is requested. External interrupt pins must
be deasserted for at least four state times prior to a request.
External interrupt pins are sampled once every four state times (a frame length of 666.4 ns at 12
MHz). A level-triggered interrupt pin held low or high for any five-state time period guarantees
detection. Edge-triggered external interrupts must hold the request pin low for at least five state
times. This ensures edge recognition and sets interrupt request bit EXx. The CPU clears EXx au-
tomatically during service routine fetch cycles for edge-triggered interrupts.
6-3
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Table 6-3. Interrupt Control Matrix
Global
Enable
Timer
2
Serial
Port
Timer
1
Timer
0
Interrupt Name
PCA
INT1#
INT0#
Bit Name in IE0
Register
EA
NA
EC
ET2
6
ES
5
ET1
4
EX1
ET0
2
EX0
Interrupt Priority-
Within-Level
(7 = Low Priority,
1 = High Priority)
7
3
1
Bit Names in:
IPH0
Reserved IPH0.6 IPH0.5 IPH0.4 IPH0.3
IPH0.2
IPL0.2
IPH0.1
IPL0.1
IPH0.0
IPL0.0
IPL0
Reserved IPL0.6
IPL0.5
IPL0.4
IPL0.3
Programmable for
Negative-edge
Triggered or Level-
triggered Detect?
NA
NA
Edge
No
No
No
Yes
IE1
No
Yes
IE0
Interrupt Request
Flag in CCON,
T2CON, SCON, or
TCON Register
CF,
CCFx
TF2,
EXF2
RI, TI
TF1
TF0
Yes
Interrupt Request
Flag Cleared by
Hardware?
Edge
Yes,
Level No
Edge
Yes,
Level No
No
NA
No
No
No
Yes
FF:
ISR Vector Address
FF:
FF:
FF:
FF:
0013H
FF:
000BH
FF:
0003H
0033H 002BH 0023H 001BH
Two timer-interrupt request bits TF0 and TF1 (see TCON register, Figure 8-6 on page 8-8) are set
by timer overflow (the exception is Timer 0 in Mode 3, see Figure 8-4 on page 8-6). When a timer
interrupt is generated, the bit is cleared by an on-chip hardware vector to an interrupt service rou-
tine. Timer interrupts are enabled by bits ET0, ET1, and ET2 in the IE0 register (see Figure 6-2,
"Interrupt Enable Register”).
Timer 2 interrupts are generated by a logical OR of bits TF2 and EXF2 in register T2CON (see
Figure 8-12 on page 8-17). Neither flag is cleared by a hardware vector to a service routine. In
fact, the interrupt service routine must determine if TF2 or EXF2 generated the interrupt, and then
clear the bit. Timer 2 interrupt is enabled by ET2 in register IE0.
6-4
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INTERRUPT SYSTEM
6.3 PROGRAMMABLE COUNTER ARRAY (PCA) INTERRUPT
The programmable counter array (PCA) interrupt is generated by the logical OR of five event
flags (CCFx) and the PCA timer overflow flag (CF) in the CCON register (see Figure 9-8 on page
9-14). All PCA interrupts share a common interrupt vector. Bits are not cleared by hardware vec-
tors to service routines. Normally, interrupt service routines resolve interrupt requests and clear
flag bits. This allows the user to define the relative priorities of the five PCA interrupts.
The PCA interrupt is enabled by bit EC in the IE0 register (see Figure 6-1). In addition, the CF
flag and each of the CCFx flags must also be individually enabled by bits ECF and ECCFx in reg-
isters CMOD and CCAPMx respectively for the flag to generate an interrupt (see Figure 9-8 on
page 9-14 and Figure 9-9 on page 9-15).
NOTE
CCFx refers to 5 separate bits, one for each PCA module (CCF0, CCF1, CCF2,
CCF3, CCF4). CCAPMx refers to 5 separate registers, one for each PCA
module (CCAPM0, CCAPM1, CCAPM2, CCAPM3, CCAPM4).
6.4 SERIAL PORT INTERRUPT
Serial port interrupts are generated by the logical OR of bits RI and TI in the SCON register (see
Figure 10-2 on page 10-3). Neither flag is cleared by a hardware vector to the service routine. The
service routine resolves RI or TI interrupt generation and clears the serial port request flag. The
serial port interrupt is enabled by bit ES in the IE0 register (see Figure 6-2).
6.5 INTERRUPT ENABLE
Each interrupt source (with the exception of TRAP) may be individually enabled or disabled by
the appropriate interrupt enable bit in the IE0 register at S:A8H (see Figure 6-2). Note IE0 also
contains a global disable bit (EA). If EA is set, interrupts are individually enabled or disabled by
bits in IE0. If EA is clear, all interrupts are disabled.
6-5
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Address:
Reset State:
S:A8H
0000 0000B
IE0
7
0
EA
EC
ET2
ES
ET1
EX1
ET0
EX0
Bit
Number
Bit
Mnemonic
Function
7
EA
Global Interrupt Enable:
Setting this bit enables all interrupts that are individually enabled by bits
0–6. Clearing this bit disables all interrupts, except the TRAP interrupt,
which is always enabled.
6
5
4
3
2
1
0
EC
PCA Interrupt Enable:
Setting this bit enables the PCA interrupt.
ET2
ES
Timer 2 Overflow Interrupt Enable:
Setting this bit enables the timer 2 overflow interrupt.
Serial I/O Port Interrupt Enable:
Setting this bit enables the serial I/O port interrupt.
ET1
EX1
ET0
EX0
Timer 1 Overflow Interrupt Enable:
Setting this bit enables the timer 1 overflow interrupt.
External Interrupt 1 Enable:
Setting this bit enables external interrupt 1.
Timer 0 Overflow Interrupt Enable:
Setting this bit enables the timer 0 overflow interrupt.
External Interrupt 0 Enable:
Setting this bit enables external interrupt 0.
Figure 6-2. Interrupt Enable Register
6-6
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INTERRUPT SYSTEM
6.6 INTERRUPT PRIORITIES
Each of the seven 8XC251Sx interrupt sources may be individually programmed to one of four
priority levels. This is accomplished with the IPH0.x/IPL0.x bit pairs in the interrupt priority high
(IPH0) and interrupt priority low (IPL0) registers (Figures 6-3 and 6-4 on page 6-8). Specify the
priority level as shown in Table 6-4 using IPH0.x as the MSB and IPL0.x as the LSB.
Table 6-4. Level of Priority
IPH0.x (MSB)
IPL0.x (LSB)
Priority Level
0 Lowest Priority
0
0
1
1
0
1
0
1
1
2
3 Highest Priority
A low-priority interrupt is always interrupted by a higher priority interrupt but not by another in-
terrupt of equal or lower priority. The highest priority interrupt is not interrupted by any other in-
terrupt source. Higher priority interrupts are serviced before lower priority interrupts. The
response to simultaneous occurrence of equal priority interrupts (i.e., sampled within the same
four state interrupt cycle) is determined by a hardware priority-within-level resolver (see Table
6-5).
Table 6-5. Interrupt Priority Within Level
Priority Number
Interrupt Name
1 (Highest Priority)
INT0#
Timer 0
INT1#
2
3
4
Timer 1
Serial Port
Timer 2
PCA
5
6
7 (Lowest Priority)
NOTE
The 8XC251Sx Interrupt Priority Within Level table (Table 6-5) differs from
MCS® 51 microcontrollers. Other MCS 251 microcontrollers may have unique
interrupt priority within level tables.
6-7
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Address:
Reset State:
S:B7H
X000 0000B
IPH0
7
0
—
IPH0.6
IPH0.5
IPH0.4
IPH0.3
IPH0.2
IPH0.1
IPH0.0
Bit
Number
Bit
Mnemonic
Function
7
—
Reserved. The value read from this bit is indeterminate. Write a “0” to
this bit.
6
5
4
3
2
1
0
IPH0.6
IPH0.5
IPH0.4
IPH0.3
IPH0.2
IPH0.1
IPH0.0
PCA Interrupt Priority Bit High
Timer 2 Overflow Interrupt Priority Bit High
Serial I/O Port Interrupt Priority Bit High
Timer 1 Overflow Interrupt Priority Bit High
External Interrupt 1 Priority Bit High
Timer 0 Overflow Interrupt Priority Bit High
External Interrupt 0 Priority Bit High
Figure 6-3. Interrupt Priority High Register
Address:
Reset State:
S:B8H
X000 0000B
IPL0
7
0
—
IPL0.6
IPL0.5
IPL0.4
IPL0.3
IPL0.2
IPL0.1
IPL0.0
Bit
Number
Bit
Mnemonic
Function
7
—
Reserved. The value read from this bit is indeterminate. Write a “0” to
this bit.
6
5
4
3
2
1
0
IPL0.6
IPL0.5
IPL0.4
IPL0.3
IPL0.2
IPL0.1
IPL0.0
PCA Interrupt Priority Bit Low
Timer 2 Overflow Interrupt Priority Bit Low
Serial I/O Port Interrupt Priority Bit Low
Timer 1 Overflow Interrupt Priority Bit Low
External Interrupt 1 Priority Bit Low
Timer 0 Overflow Interrupt Priority Bit Low
External Interrupt 0 Priority Bit Low
Figure 6-4. Interrupt Priority Low Register
6-8
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INTERRUPT SYSTEM
6.7 INTERRUPT PROCESSING
Interrupt processing is a dynamic operation that begins when a source requests an interrupt and
lasts until the execution of the first instruction in the interrupt service routine (see Figure 6-5).
Response time is the amount of time between the interrupt request and the resulting break in the
current instruction stream. Latency is the amount of time between the interrupt request and the
execution of the first instruction in the interrupt service routine. These periods are dynamic due
to the presence of both fixed-time sequences and several variable conditions. These conditions
contribute to total elapsed time.
Response Time
OSC
State
Time
External
Interrupt
Request
Ending Instructions
Push PC
Call ISR
ISR
Latency
A4153-01
Figure 6-5. The Interrupt Process
Both response time and latency begin with the request. The subsequent minimum fixed sequence
comprises the interrupt sample, poll, and request operations. The variables consist of (but are not
limited to): specific instructions in use at request time, internal versus external interrupt source
requests, internal versus external program operation, stack location, presence of wait states, page-
mode operation, and branch pointer length.
NOTE
In the following discussion, external interrupt request pins are assumed to be
inactive for at least four state times prior to assertion. In this chapter all
external hardware signals maintain some setup period (i.e., less than one state
time). Signals must meet VIH and VIL specifications prior to any state time
under discussion. This setup state time is not included in examples or calcula-
tions for either response or latency.
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6.7.1 Minimum Fixed Interrupt Time
All interrupts are sampled or polled every four state times (see Figure 6-5). Two of eight inter-
rupts are latched and polled per state time within any given four state time window. One addition-
al state time is required for a context switch request. For code branches to jump locations in the
current 64-Kbyte memory region (compatible with MCS 51 microcontrollers), the context switch
time is 11 states. Therefore, the minimum fixed poll and request time is 16 states (4 poll states +
1 request state + 11 states for the context switch = 16 state times).
Therefore, this minimum fixed period rests upon four assumptions:
• The source request is an internal interrupt with high enough priority to take precedence over
other potential interrupts,
• The request is coincident with internal execution and needs no instruction completion time,
• The program uses an internal stack location, and
• The ISR is in on-chip OTPROM/ROM.
6.7.2 Variable Interrupt Parameters
Both response time and latency calculations contain fixed and variable components. By defini-
tion, it is often difficult to predict exact timing calculations for real-time requests. One large vari-
able is the completion time of an instruction cycle coincident with the occurrence of an interrupt
request. Worst-case predictions typically use the longest-executing instruction in an architecture’s
code set. In the case of the 8XC251Sx, the longest-executing instruction is a 16-bit divide (DIV).
However, even this 21- state instruction may have only 1 or 2 remaining states to complete before
the interrupt system injects a context switch. This uncertainty affects both response time and la-
tency.
6.7.2.1
Response Time Variables
Response time is defined as the start of a dynamic time period when a source requests an interrupt
and lasts until a break in the current instruction execution stream occurs (see Figure 6-5). Re-
sponse time (and therefore latency) is affected by two primary factors: the incidence of the re-
quest relative to the four-state-time sample window and the completion time of instructions in the
response period (i.e., shorter instructions complete earlier than longer instructions).
NOTE
External interrupt signals require one additional state time in comparison to
internal interrupts. This is necessary to sample and latch the pin value prior to
a poll of interrupts. The sample occurs in the first half of the state time and the
poll/request occurs in the second half of the next state time. Therefore, this
sample and poll/request portion of the minimum fixed response and latency
6-10
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INTERRUPT SYSTEM
time is five states for internal interrupts and six states for external interrupts.
External interrupts must remain active for at least five state times to guarantee
interrupt recognition when the request occurs immediately after a sample has
been taken (i.e., requested in the second half of a sample state time).
If the external interrupt goes active one state after the sample state, the pin is not resampled for
another three states. After the second sample is taken and the interrupt request is recognized, the
interrupt controller requests the context switch. The programmer must also consider the time to
complete the instruction at the moment the context switch request is sent to the execution unit. If
9 states of a 10-state instruction have completed when the context switch is requested, the total
response time is 6 states, with a context switch immediately after the final state of the 10-state
instruction (see Figure 6-6).
Response Time = 6
OSC
State Time
INT0#
Sample INT0#
Request
Ten State
Push PC
Instruction
A4155-02
Figure 6-6. Response Time Example #1
Conversely, if the external interrupt requests service in the state just prior to the next sample, re-
sponse is much quicker. One state asserts the request, one state samples, and one state requests
the context switch. If at that point the same instruction conditions exist, one additional state time
is needed to complete the 10-state instruction prior to the context switch (see Figure 6-7). The
total response time in this case is four state times. The programmer must evaluate all pertinent
conditions for accurate predictability.
6-11
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Response Time = 4
OSC
State Time
INT0#
Sample INT0#
Request
Ten State
Instruction
Push PC
A4154-02
Figure 6-7. Response Time Example #2
6.7.2.2
Worst-case latency calculations assume that the longest 8XC251Sx instruction used in the pro-
gram must fully execute prior to a context switch. The instruction execution time is reduced by
one state with the assumption the instruction state overlaps the request state (therefore, 16-bit
DIV is 21 state times - 1 = 20 states for latency calculations). The calculations add fixed and vari-
able interrupt times (see Table 6-6) to this instruction time to predict latency. The worst-case la-
tency (both fixed and variable times included) is expressed by a pseudo-formula:
FIXED_TIME + VARIABLES + LONGEST_INSTRUCTION = MAXIMUM LATENCY PREDICTION
6-12
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INTERRUPT SYSTEM
Table 6-6. Interrupt Latency Variables
External
INT0#,
Variable INT1#,
T2EX
>64K
Jump to
ISR (1)
External
External
Stack
>64K (1) Wait State
External
Stack
External
Execution Mode
Page
Memory
Wait
Stack
<64K (1)
State
Number
of
States
1 per
bus cycle
1 per
bus cycle
1
2
1
8
4
8
Added
NOTES:
1. <64K/>64K means inside/outside the 64-Kbyte memory region where code is executing.
2. Base-case fixed time is 16 states and assumes:
— A 2-byte instruction is the first ISR byte.
— <64K jump to ISR
— Internal execution
— Internal stack
— Internal peripheral interrupt
6.7.2.3
Latency Calculations
Assume the use of a zero-wait-state external memory where current instructions, the ISR, and the
stack are located within the same 64-Kbyte memory region (compatible with memory maps for
MCS 51 microcontrollers.) Further, assume there are 3 states yet to complete in the current 21-
state DIV instruction when INT0# requests service. Also assume INT0# has made the request one
state prior to the sample state (as in Figure 6-7). Unlike in Figure 6-7, the response time for this
assumption is three state times as the current instruction completes in time for the branch to occur.
Latency calculations begin with the minimum fixed latency of 16 states. From Table 6-6, one state
is added for an INT0# request from external hardware; two states are added for external execu-
tion; and four states for an external stack in the current 64-Kbyte region. Finally, three states are
added for the current instruction to complete. The actual latency is 26 states. Worst-case latency
calculations predict 43 states for this example due to inclusion of total DIV instruction time (less
one state).
Table 6-7. Actual vs. Predicted Latency Calculations
Latency Factors
Actual
16
Predicted
Base Case Minimum Fixed Time
INT0# External Request
External Execution
16
1
1
2
2
<64K Byte Stack Location
Execution Time for Current DIV Instruction
TOTAL
4
4
3
20
43
26
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6.7.2.4
Blocking Conditions
If all enable and priority requirements have been met, a single prioritized interrupt request at a
time generates a vector cycle to an interrupt service routine (refer to the CALL instructions in Ap-
pendix A, “Instruction Set Reference”). There are three causes of blocking conditions with hard-
ware-generated vectors:
1. An interrupt of equal or higher priority level is already in progress (defined as any point
after the flag has been set and the RETI of the ISR has not executed).
2. The current polling cycle is not the final cycle of the instruction in progress.
3. The instruction in progress is RETI or any write to the IE0, IPH0, or IPL0 registers.
Any of these conditions blocks calls to interrupt service routines. Condition two ensures the in-
struction in progress completes before the system vectors to the ISR. Condition three ensures at
least one more instruction executes before the system vectors to additional interrupts if the in-
struction in progress is a RETI or any write to IE0, IPH0, or IPL0. The complete polling cycle is
repeated every four state times.
6.7.2.5
Interrupt Vector Cycle
When an interrupt vector cycle is initiated, the CPU breaks the instruction stream sequence, re-
solves all instruction pipeline decisions, and pushes multiple program counter (PC) bytes onto the
stack. The CPU then reloads the PC with a start address for the appropriate ISR. The number of
bytes pushed to the stack depends upon the INTR bit in the UCONFIG1 configuration byte (see
Figure 4-4 on page 4-7). The complete sample, poll, request and context switch vector sequence
is illustrated in the interrupt latency timing diagram (Figure 6-5).
NOTE
If the interrupt flag for a level-triggered external interrupt is set but denied for
one of the above conditions and is clear when the blocking condition is
removed, then the denied interrupt is ignored. In other words, blocked interrupt
requests are not buffered for retention.
6-14
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INTERRUPT SYSTEM
6.7.3 ISRs in Process
ISR execution proceeds until the RETI instruction is encountered. The RETI instruction informs
the processor that the interrupt routine is completed. The RETI instruction in the ISR pops PC
address bytes off the stack (as well as PSW1 for INTR = 1) and execution resumes at the suspend-
ed instruction stream.
NOTE
Some programs written for MCS 51 microcontrollers use RETI instead of RET
to return from a subroutine that is called by ACALL or LCALL (i.e., not an
interrupt service routine (ISR)). In the 8XC251Sx, this causes a compatibility
problem if INTR = 1 in configuration byte CONFIG1. In this case, the CPU
pushes four bytes (the three-byte PC and PSW1) onto the stack when the
routine is called and pops the same four bytes when the RETI is executed. In
contrast, RET pushes and pops only the lower two bytes of the PC. To
maintain compatibility, configure the 8XC251Sx with INTR = 0.
With the exception of TRAP, the start addresses of consecutive interrupt service routines are eight
bytes apart. If consecutive interrupts are used (IE0 and TF0, for example, or TF0 and IE1), the
first interrupt routine (if more than seven bytes long) must execute a jump to some other memory
location. This prevents overlap of the start address of the following interrupt routine.
6-15
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7
Input/Output Ports
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CHAPTER 7
INPUT/OUTPUT PORTS
7.1 INPUT/OUTPUT PORT OVERVIEW
The 8XC251Sx uses input/output (I/O) ports to exchange data with external devices. In addition
to performing general-purpose I/O, some ports are capable of external memory operations (see
Chapter 13, “External Memory Interface”); others allow for alternate functions. All four
8XC251Sx I/O ports are bidirectional. Each port contains a latch, an output driver, and an input
buffer. Port 0 and port 2 output drivers and input buffers facilitate external memory operations.
Port 0 drives the lower address byte onto the parallel address bus, and port 2 drives the upper ad-
dress byte onto the bus. In nonpage mode, the data is multiplexed with the lower address byte on
port 0. In page mode, the data is multiplexed with the upper address byte on port 2. All port 1 and
port 3 pins serve for both general-purpose I/O and alternate functions (see Table 7-1).
Table 7-1. Input/Output Port Pin Descriptions
Pin
Name
Alternate
Pin Name
Alternate
Type
Type
Alternate Description
P0.7:0 I/O AD7:0
Address/Data (Nonpage Mode), Address (Page Mode)
Timer 2 Clock Input/Output
Timer 2 External Input
I/O
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
I/O T2
I/O
I/O T2EX
I/O ECI
I
PCA External Clock Input
PCA Module 0 I/O
I
I/O CEX0
I/O CEX1
I/O CEX2
I/O CEX3/WAIT#
I/O
PCA Module 1 I/O
I/O
PCA Module 2 I/O
I/O
PCA Module 3 I/O
I/O
I/O CEX4/A17/WCLK PCA Module 4 I/O or 18th Address Bit
I/O(O)
P2.7:0 I/O A15:8
Address (Nonpage Mode), Address/Data (Page Mode)
Serial Port Receive Data Input
Serial Port Transmit Data Output
External Interrupt 0
I/O
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
I/O RXD
I/O TXD
I/O INT0#
I/O INT1#
I/O T0
I (I/O)
O (O)
I
I
External Interrupt 1
Timer 0 Input
I
I/O T1
Timer 1 Input
I
I/O WR#
I/O RD#/A16
Write Signal to External Memory
Read Signal to External Memory or 17th Address Bit
O
O
7-1
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7.2 I/O CONFIGURATIONS
Each port SFR operates via type-D latches, as illustrated in Figure 7-1 for ports 1 and 3. A CPU
“write to latch” signal initiates transfer of internal bus data into the type-D latch. A CPU “read
latch” signal transfers the latched Q output onto the internal bus. Similarly, a “read pin” signal
transfers the logical level of the port pin. Some port data instructions activate the “read latch” sig-
write instructions (see section 7.5, “Read-Modify-Write Instructions”). Each I/O line may be in-
dependently programmed as input or output.
7.3 PORT 1 AND PORT 3
Figure 7-1 shows the structure of ports 1 and 3, which have internal pullups. An external source
can pull the pin low. Each port pin can be configured either for general-purpose I/O or for its al-
ternate input or output function (Table 7-1).
1, 3). To use a pin for general-purpose input, set the bit in the Px register. This turns off the output
driver FET.
To configure a pin for its alternate function, set the bit in the Px register. When the latch is set, the
and 3 is discussed further in section 7.6, “Quasi-bidirectional Port Operation.”
7.4 PORT 0 AND PORT 2
Ports 0 and 2 are used for general-purpose I/O or as the external address/data bus. Port 0, shown
in Figure 7-2, differs from the other ports in not having internal pullups. Figure 7-3 shows the
structure of port 2. An external source can pull a port 2 pin low.
To use a pin for general-purpose output, set or clear the corresponding bit in the Px register (x =
0, 2). To use a pin for general-purpose input set the bit in the Px register to turn off the output
driver FET.
7-2
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INPUT/OUTPUT PORTS
VCC
Alternate
Output
Function
Internal
Pullup
Read
Latch
P3.x
Internal
Bus
D
Q
P3.x
Latch
Write to
Latch
CL
Q#
Read
Pin
Alternate
Input
Function
A2239-01
Figure 7-1. Port 1 and Port 3 Structure
Address/
Data
VCC
Read
Latch
Control
P0.x
Internal
Bus
D
Q
P0.x
1
0
Latch
Write to
Latch
CL
Q#
Read
Pin
A2238-01
Figure 7-2. Port 0 Structure
7-3
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8XC251SA, SB, SP, SQ USER’S MANUAL
VCC
Address
Control
Internal
Pullup
Read
Latch
P2.x
1
0
Internal
D
Q
Bus
P2.x
Latch
Write to
Latch
CL
Q#
Read
Pin
A2240-01
Figure 7-3. Port 2 Structure
When port 0 and port 2 are used for an external memory cycle, an internal control signal switches
the output-driver input from the latch output to the internal address/data line. Section 7.8, “Exter-
nal Memory Access,” discusses the operation of port 0 and port 2 as the external address/data bus.
NOTE
Port 0 and port 2 are precluded from use as general purpose I/O ports when
used as address/data bus drivers.
Port 0 internal pullups assist the logic-one output for memory bus cycles only.
Except for these bus cycles, the pullup FET is off. All other port 0 outputs are
open drain.
7-4
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INPUT/OUTPUT PORTS
7.5 READ-MODIFY-WRITE INSTRUCTIONS
Some instructions read the latch data rather than the pin data. The latch based instructions read
the data, modify the data, and then rewrite the latch. These are called “read-modify-write” in-
structions. Below is a complete list of these special instructions. When the destination operand is
a port, or a port bit, these instructions read the latch rather than the pin:
ANL
(logical AND, e.g., ANL P1, A)
(logical OR, e.g., ORL P2, A)
ORL
XRL
(logical EX-OR, e.g., XRL P3, A)
(jump if bit = 1 and clear bit, e.g., JBC P1.1, LABEL)
(complement bit, e.g., CPL P3.0)
(increment, e.g., INC P2)
JBC
CPL
INC
DEC
(decrement, e.g., DEC P2)
DJNZ
(decrement and jump if not zero, e.g., DJNZ P3, LABEL)
(move carry bit to bit Y of port X)
(clear bit Y of port X)
MOV PX.Y, C
CLR PX.Y
SETB PX.Y
(set bit Y of port x)
It is not obvious that the last three instructions in this list are read-modify-write instructions.
These instructions read the port (all 8 bits), modify the specifically addressed bit, and write the
new byte back to the latch. These read-modify-write instructions are directed to the latch rather
than the pin in order to avoid possible misinterpretation of voltage (and therefore, logic) levels at
the pin. For example, a port bit used to drive the base of an external bipolar transistor cannot rise
above the transistor’s base-emitter junction voltage (a value lower than V ). With a logic one
IL
written to the bit, attempts by the CPU to read the port at the pin are misinterpreted as logic zero.
A read of the latch rather than the pin returns the correct logic-one value.
7-5
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7.6 QUASI-BIDIRECTIONAL PORT OPERATION
Port 1, port 2, and port 3 have fixed internal pullups and are referred to as “quasi-bidirectional”
ports. When configured as an input, the pin impedance appears as logic one and sources current
(see the 8XC251Sx datasheet) in response to an external logic-zero condition. Port 0 is a “true
bidirectional” pin. The pin floats when configured as input. Resets write logical one to all port
latches. If logical zero is subsequently written to a port latch, it can be returned to input conditions
by a logical one written to the latch. For additional electrical information, refer to the 8XC251SA,
SB, SP, SQ High-Performance CHMOS Microcontroller Datasheet.
Port latch values change near the end of read-modify-write instruction cycles.
Output buffers (and therefore the pin state) update early in the instruction after
the read-modify-write instruction cycle.
Logical zero-to-one transitions in port 1, port 2, and port 3 utilize an additional pullup to aid this
logic transition (see Figure 7-4). This increases switch speed. The extra pullup briefly sources 100
times the normal internal circuit current. The internal pullups are field-effect transistors rather
than linear resistors. Pullups consist of three p-channel FET (pFET) devices. A pFET is on when
the gate senses logical zero and off when the gate senses logical one. pFET #1 is turned on for
two oscillator periods immediately after a zero-to-one transition in the port latch. A logic one at
the port pin turns on pFET #3 (a weak pullup) through the inverter. This inverter and pFET pair
form a latch to drive logic one. pFET #2 is a very weak pullup switched on whenever the associ-
ated nFET is switched off. This is the traditional CMOS switch convention. Current strengths are
1/10 that of pFET #3.
7-6
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INPUT/OUTPUT PORTS
VCC
VCC
VCC
2 Osc. Periods
P1
P2
P3
Port
Q#
From
Port
n
Latch
Input Data
Read Port Pin
A2242-01
Figure 7-4. Internal Pullup Configurations
7.7 PORT LOADING
Output buffers of port 1, port 2, and port 3 can each sink 1.6 mA at logic zero (see VOL specifica-
tions in the 8XC251Sx data sheet). These port pins can be driven by open-collector and open-
drain devices. Logic zero-to-one transitions occur slowly as limited current pulls the pin to a log-
ic-one condition (Figure 7-4). A logic-zero input turns off pFET #3. This leaves only pFET #2
weakly in support of the transition. In external bus mode, port 0 output buffers each sink 3.2 mA
at logic zero (see VOL1 in the 8XC251Sx data sheet). However, the port 0 pins require external
pullups to drive external gate inputs. See the latest revision of the 8XC251Sx datasheet for com-
plete electrical design information. External circuits must be designed to limit current require-
ments to these conditions.
7.8 EXTERNAL MEMORY ACCESS
The external bus structure is different for page mode and nonpage mode. In nonpage mode (used
by MCS 51 microcontrollers), port 2 outputs the upper address byte; the lower address byte and
the data are multiplexed on port 0. In page mode, the upper address byte and the data are multi-
plexed on port 2, while port 0 outputs the lower address byte.
7-7
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The 8XC251Sx CPU writes FFH to the P0 register for all external memory bus cycles. This over-
writes previous information in P0. In contrast, the P2 register is unmodified for external bus cy-
cles. When address bits or data bits are not on the port 2 pins, the bit values in P2 appear on the
port 2 pins.
In nonpage mode, port 0 uses a strong internal pullup FET to output ones or a strong internal pull-
down FET to output zeros for the lower address byte and the data. Port 0 is in a high-impedance
state for data input.
In page mode, port 0 uses a strong internal pullup FET to output ones or a strong internal pull-
down FET to output zeros for the lower address byte; port 0 also uses a strong internal pulldown
FET to output zeros for the upper address byte.
In nonpage mode, port 2 uses a strong internal pullup FET to output ones or a strong internal pull-
down FET to output zeros for the upper address byte. In page mode, port 2 uses a strong internal
pullup FET to output ones or a strong internal pulldown FET to output zeros for the upper address
byte and data. Port 2 is in a high-impedance state for data input.
NOTE
In external bus mode port 0 outputs do not require external pullups.
There are two types of external memory accesses: external program memory and external data
memory (see Chapter 13, “External Memory Interface”). External program memories utilize sig-
nal PSEN# as a read strobe. MCS 51 microcontrollers use RD# (read) or WR# (write) to strobe
memory for data accesses. Depending on its RD1:0 configuration bits, the 8XC251Sx uses
PSEN# or RD# for data reads (see section 4.5.2, “Configuration Bits RD1:0”).
During instruction fetches, external program memory can transfer instructions with 16-bit ad-
dresses for binary-compatible code or with the external bus configured for extended memory ad-
dressing (17-bit or 18-bit).
External data memory transfers use an 8-, 16-, 17-, or 18-bit address bus, depending on the in-
struction and the configuration of the external bus. Table 7-2 lists the instructions that can be used
for these bus widths.
7-8
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INPUT/OUTPUT PORTS
Table 7-2. Instructions for External Data Moves
Bus Width
Instructions
8
MOVX @Ri; MOV @Rm; MOV dir8
MOVX @DPTR; MOV @WRj; MOV @WRj+dis; MOV dir16
MOV @DRk; MOV @DRk+dis
16
17
18
MOV @DRk; MOV @DRk+dis
NOTE
Avoid MOV P0 instructions for external memory accesses. These instructions
can corrupt input code bytes at port 0.
External signal ALE (address latch enable) facilitates external address latch capture. The address
byte is valid after the ALE pin drives VOL. For write cycles, valid data is written to port 0 just prior
to the write (WR#) pin asserting VOL. Data remains valid until WR# is undriven. For read cycles,
data returned from external memory must appear at port 0 before the read (RD#) pin is undriven
(refer to the 8XC251Sx datasheet for exact specifications). Wait states, by definition, affect bus-
timing.
7-9
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8
Timer/Counters and
Watchdog Timer
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CHAPTER 8
TIMER/COUNTERS AND WATCHDOG TIMER
This chapter describes the timer/counters and the watchdog timer (WDT) included as peripherals
on the 8XC251Sx. When operating as a timer, a timer/counter runs for a programmed length of
tive transitions on an external pin. After a preset number of counts, the counter issues an interrupt
request. Timer/counters are covered in sections 8.1 through 8.6.
The watchdog timer provides a way to monitor system operation. It causes a system reset if a soft-
ware malfunction allows it to expire. The watchdog timer is covered in section 8.7, “Watchdog
Timer.”
8.1 TIMER/COUNTER OVERVIEW
The 8XC251Sx contains three general-purpose, 16-bit timer/counters. Although they are identi-
fied as timer 0, timer 1, and timer 2, you can independently configure each to operate in a variety
of modes as a timer or as an event counter. Each timer employs two 8-bit timer registers, used
separately or in cascade, to maintain the count. The timer registers and associated control and cap-
ture registers are implemented as addressable special function registers (SFRs). Table 8-1 briefly
describes the SFRs referred to in this chapter. Four of the SFRs provide programmable control of
the timers as follows:
• Timer/counter mode control register (TMOD) and timer/counter control register (TCON)
control timer 0 and timer 1
• Timer/counter 2 mode control register (T2MOD) and timer/counter 2 control register
(T2CON) control timer 2
For a map of the SFR address space, see Table 3-5 on page 3-17. Table 8-2 describes the external
signals referred to in this chapter.
8.2 TIMER/COUNTER OPERATION
The block diagram in Figure 8-1 depicts the basic logic of the timers. Here timer registers THx
and TLx (x = 0, 1, and 2) connect in cascade to form a 16-bit timer. Setting the run control bit
(TRx) turns the timer on by allowing the selected input to increment TLx. When TLx overflows
it increments THx; when THx overflows it sets the timer overflow flag (TFx) in the TCON or
T2CON register. Setting the run control bit does not clear the THx and TLx timer registers. The
timer registers can be accessed to obtain the current count or to enter preset values. Timer 0 and
timer 1 can also be controlled by external pin INTx# to facilitate pulse width measurements.
8-1
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Table 8-1. Timer/Counter and Watchdog Timer SFRs
Mnemonic
Description
Address
TL0
TH0
Timer 0 Timer Registers. Used separately as 8-bit counters or in cascade S:8AH
as a 16-bit counter. Counts an internal clock signal with frequency FOSC/12 S:8CH
(timer operation) or an external input (event counter operation).
TL1
TH1
Timer 1 Timer Registers. Used separately as 8-bit counters or in cascade S:8BH
as a 16-bit counter. Counts an internal clock signal with frequency FOSC/12 S:8DH
(timer operation) or an external input (event counter operation).
TL2
TH2
Timer 2 Timer Registers. TL2 and TH2 connect in cascade to provide a
16-bit counter. Counts an internal clock signal with frequency FOSC/12
(timer operation) or an external input (event counter operation).
S:CCH
S:CDH
TCON
TMOD
Timer 0/1 Control Register. Contains the run control bits, overflow flags,
interrupt flags, and interrupt-type control bits for timer 0 and timer 1.
S:88H
S:89H
Timer 0/1 Mode Control Register. Contains the mode select bits,
counter/timer select bits, and external control gate bits for timer 0 and
timer 1.
T2CON
Timer 2 Control Register. Contains the receive clock, transmit clock, and S:C8H
capture/reload bits used to configure timer 2. Also contains the run control
bit, counter/timer select bit, overflow flag, external flag, and external enable
for timer 2.
T2MOD
Timer 2 Mode Control Register. Contains the timer 2 output enable and
S:C9H
down count enable bits.
RCAP2L
RCAP2H
Timer 2 Reload/Capture Registers (RCAP2L, RCAP2H). Provide values S:CAH
to and receive values from the timer registers (TL2,TH2).
S:CBH
WDTRST
Watchdog Timer Reset Register (WDTRST). Used to reset and enable
S:A6H
the WDT.
XTAL1
12
Interrupt
Request
0
1
Overflow
THx
(8 Bits) (8 Bits)
TLx
TFx
Tx
C/Tx#
x = 0, 1, or 2
TRx
A4121-02
Figure 8-1. Basic Logic of the Timer/Counters
The C\Tx# control bit selects timer operation or counter operation by selecting the divided-down
system clock or external pin Tx as the source for the counted signal.
8-2
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TIMER/COUNTERS AND WATCHDOG TIMER
For timer operation (C/Tx# = 0), the timer register counts the divided-down system clock. The
timer register is incremented once every peripheral cycle, i.e., once every six states (see section
2.2.2, “Clock and Reset Unit”). Since six states equals 12 clock cycles, the timer clock rate is
FOSC/12. Exceptions are the timer 2 baud rate and clock-out modes, where the timer register is
incremented by the system clock divided by two.
For counter operation (C/Tx# = 1), the timer register counts the negative transitions on the Tx ex-
ternal input pin. The external input is sampled during every S5P2 state. Section 2.2.2, “Clock and
Reset Unit,” describes the notation for the states in a peripheral cycle. When the sample is high
in one cycle and low in the next, the counter is incremented. The new count value appears in the
register during the next S3P1 state after the transition was detected. Since it takes 12 states (24
oscillator periods) to recognize a negative transition, the maximum count rate is 1/24 of the os-
cillator frequency. There are no restrictions on the duty cycle of the external input signal, but to
ensure that a given level is sampled at least once before it changes, it should be held for at least
one full peripheral cycle.
Table 8-2. External Signals
Signal
Name
Alternate
Function
Type
Description
T2
I/O
Timer 2 Clock Input/Output. This signal is the external clock input
for the timer 2 capture mode; and it is the timer 2 clock-output for the
clock-out mode.
P1.0
T2EX
INT1:0#
T1:0
I
I
I
Timer 2 External Input. In timer 2 capture mode, a falling edge
initiates a capture of the timer 2 registers. In auto-reload mode, a
falling edge causes the timer 2 registers to be reloaded. In the up-
down counter mode, this signal determines the count direction:
high = up, low = down.
P1.1
External Interrupts 1:0. These inputs set the IE1:0 interrupt flags in
the TCON register. TCON bits IT1:0 select the triggering method:
IT1:0 = 1 selects edge-triggered (high-to-low);IT1:0 = 0 selects level-
triggered (active low). INT1:0# also serves as external run control for
timer 1:0 when selected by TCON bits GATE1:0#.
P3.3:2
P3.5:4
counter, a falling edge on the T1:0 pin increments the count.
8.3 TIMER 0
Timer 0 functions as either a timer or event counter in four modes of operation. Figures 8-2, 8-3,
and 8-4 show the logical configuration of each mode.
Timer 0 is controlled by the four low-order bits of the TMOD register (Figure 8-5) and bits 5, 4,
1, and 0 of the TCON register (Figure 8-6). The TMOD register selects the method of timer gating
(GATE0), timer or counter operation (T/C0#), and mode of operation (M10 and M00). The
TCON register provides timer 0 control functions: overflow flag (TF0), run control (TR0), inter-
rupt flag (IE0), and interrupt type control (IT0).
8-3
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For normal timer operation (GATE0 = 0), setting TR0 allows TL0 to be incremented by the se-
lected input. Setting GATE0 and TR0 allows external pin INT0# to control timer operation. This
setup can be used to make pulse width measurements. See section 8.5.2, “Pulse Width Measure-
ments.”
Timer 0 overflow (count rolls over from all 1s to all 0s) sets the TF0 flag generating an interrupt
request.
8.3.1 Mode 0 (13-bit Timer)
Mode 0 configures timer 0 as a 13-bit timer which is set up as an 8-bit timer (TH0 register) with
a modulo 32 prescalar implemented with the lower five bits of the TL0 register (Figure 8-2). The
upper three bits of the TL0 register are indeterminate and should be ignored. Prescalar overflow
increments the TH0 register.
XTAL1
12
Interrupt
Request
0
1
Overflow
THx
(8 Bits) (8 Bits)
TLx
TFx
Tx
C/Tx#
TRx
Mode 0: 13-bit Timer/Counter
Mode 1: 16-bit Timer/Counter
x = 0 or 1
GATEx
INTx#
A4110-02
Figure 8-2. Timer 0/1 in Mode 0 and Mode 1
8.3.2 Mode 1 (16-bit Timer)
Mode 1 configures timer 0 as a 16-bit timer with TH0 and TL0 connected in cascade (Figure 8-2).
The selected input increments TL0.
8-4
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TIMER/COUNTERS AND WATCHDOG TIMER
Mode 2 configures timer 0 as an 8-bit timer (TL0 register) that automatically reloads from the
TH0 register (Figure 8-3). TL0 overflow sets the timer overflow flag (TF0) in the TCON register
and reloads TL0 with the contents of TH0, which is preset by software. When the interrupt re-
quest is serviced, hardware clears TF0. The reload leaves TH0 unchanged. See section 8.5.1,
“Auto-load Setup Example.”
XTAL1
Tx
12
Interrupt
Request
0
1
Overflow
TLx
(8 Bits)
TFx
C/Tx#
Reload
TRx
THx
(8 Bits)
GATEx
INTx#
x = 0 or 1
A4111-02
Figure 8-3. Timer 0/1 in Mode 2, Auto-Reload
8.3.4 Mode 3 (Two 8-bit Timers)
Mode 3 configures timer 0 such that registers TL0 and TH0 operate as separate 8-bit timers (Fig-
ure 8-4). This mode is provided for applications requiring an additional 8-bit timer or counter.
TL0 uses the timer 0 control bits C/T0# and GATE0 in TMOD, and TR0 and TF0 in TCON in the
normal manner. TH0 is locked into a timer function (counting FOSC /12) and takes over use of the
timer 0 is in mode 3. See section 8.4, “Timer 1,” and section 8.4.4, “Mode 3 (Halt).”
8.4 TIMER 1
Timer 1 functions as either a timer or event counter in three modes of operation. Figures 8-2 and
8-3 show the logical configuration for modes 0, 1, and 2. Timer 1’s mode 3 is a hold-count mode.
8-5
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Timer 1 is controlled by the four high-order bits of the TMOD register (Figure 8-5) and bits 7, 6,
3, and 2 of the TCON register (Figure 8-6). The TMOD register selects the method of timer gating
(GATE1), timer or counter operation (T/C1#), and mode of operation (M11 and M01). The
TCON register provides timer 1 control functions: overflow flag (TF1), run control (TR1), inter-
rupt flag (IE1), and interrupt type control (IT1).
generator for the serial port. Mode 2 is best suited for this purpose.
For normal timer operation (GATE1 = 0), setting TR1 allows timer register TL1 to be increment-
ed by the selected input. Setting GATE1 and TR1 allows external pin INT1# to control timer op-
eration. This setup can be used to make pulse width measurements. See section 8.5.2, “Pulse
Width Measurements.”
Timer 1 overflow (count rolls over from all 1s to all 0s) sets the TF1 flag generating an interrupt
request.
.
1/12 F
XTAL1
T0
12
OSC
Interrupt
Request
0
1
Overflow
TL0
(8 Bits)
TF0
C/T0#
TR0
GATE0
Interrupt
Request
Overflow
TH0
1/12 F
OSC
TR1
TF1
INT0#
(8 Bits)
A4112-02
Figure 8-4. Timer 0 in Mode 3, Two 8-bit Timers
8-6
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TIMER/COUNTERS AND WATCHDOG TIMER
Address:
Reset State:
S:89H
0000 0000B
TMOD
7
0
GATE1
C/T1#
M11
M01
GATE0
C/T0#
M10
M00
Bit
Number
Bit
Mnemonic
Function
7
GATE1
Timer 1 Gate:
When GATE1 = 0, run control bit TR1 gates the input signal to the timer
register. When GATE1 = 1 and TR1 = 1, external signal INT1 gates the
timer input.
6
C/T1#
Timer 1 Counter/Timer Select:
C/T1# = 0 selects timer operation: timer 1 counts the divided-down
system clock. C/T1# = 1 selects counter operation: timer 1 counts
negative transitions on external pin T1.
5, 4
M11, M01
Timer 1 Mode Select:
M11 M01
0
0
1
0
1
0
Mode 0: 8-bit timer/counter (TH1) with 5-bit prescalar (TL1)
Mode 1: 16-bit timer/counter
Mode 2: 8-bit auto-reload timer/counter (TL1). Reloaded
from TH1 at overflow
1
1
Mode 3: Timer 1 halted. Retains count.
3
GATE0
C/T0#
Timer 0 Gate:
When GATE0 = 0, run control bit TR0 gates the input signal to the timer
register. When GATE0 = 1 and TR0 = 1, external signal INT0 gates the
timer input.
2
Timer 0 Counter/Timer Select:
C/T0# = 0 selects timer operation: timer 0 counts the divided-down
system clock. C/T0# = 1 selects counter operation: timer 0 counts
negative transitions on external pin T0.
1, 0
M10, M00
Timer 0 Mode Select:
M10 M00
0
0
1
0
1
0
Mode 0: 8-bit timer/counter (T0) with 5-bit prescalar (TL0)
Mode 1: 16-bit timer/counter
Mode 2: 8-bit auto-reload timer/counter (TL0). Reloaded
from TH0 at overflow.
1
1
Mode 3: TL0 is an 8-bit timer/counter. TH0 is an 8-bit timer
using timer 1’s TR1 and TF1 bits.
Figure 8-5. TMOD: Timer/Counter Mode Control Register
8-7
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Address:
Reset State:
S:88H
0000 0000B
TCON
7
0
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
Bit
Number
Bit
Mnemonic
Function
7
TF1
Timer 1 Overflow Flag:
Set by hardware when the timer 1 register overflows. Cleared by
hardware when the processor vectors to the interrupt routine.
6
5
TR1
TF0
Timer 1 Run Control Bit:
Set/cleared by software to turn timer 1 on/off.
Timer 0 Overflow Flag:
Set by hardware when the timer 0 register overflows. Cleared by
hardware when the processor vectors to the interrupt routine.
4
3
TR0
IE1
Timer 0 Run Control Bit:
Set/cleared by software to turn timer 0 on/off.
Interrupt 1 Flag:
Set by hardware when an external interrupt is detected on the INT1# pin.
Edge- or level- triggered (see IT1). Cleared when interrupt is processed
if edge-triggered.
2
1
IT1
IE0
Interrupt 1 Type Control Bit:
Set this bit to select edge-triggered (high-to-low) for external interrupt 1.
Clear this bit to select level-triggered (active low).
Interrupt 1 Flag:
Set by hardware when an external interrupt is detected on the INT0# pin.
Edge- or level- triggered (see IT0). Cleared when interrupt is processed
if edge-triggered.
0
IT0
Interrupt 0 Type Control Bit:
Set this bit to select edge-triggered (high-to-low) for external interrupt 0.
Clear this bit to select level-triggered (active low).
Figure 8-6. TCON: Timer/Counter Control Register
When timer 0 is in mode 3, it uses timer 1’s overflow flag (TF1) and run control bit (TR1). For
this situation, use timer 1 only for applications that do not require an interrupt (such as a baud rate
generator for the serial interface port) and switch timer 1 in and out of mode 3 to turn it off and on.
8-8
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TIMER/COUNTERS AND WATCHDOG TIMER
8.4.1 Mode 0 (13-bit Timer)
Mode 0 configures timer 0 as a 13-bit timer, which is set up as an 8-bit timer (TH1 register) with
a modulo-32 prescalar implemented with the lower 5 bits of the TL1 register (Figure 8-2). The
upper 3 bits of the TL1 register are ignored. Prescalar overflow increments the TH1 register.
8.4.2 Mode 1 (16-bit Timer)
The selected input increments TL1.
8.4.3 Mode 2 (8-bit Timer with Auto-reload)
Mode 2 configures timer 1 as an 8-bit timer (TL1 register) with automatic reload from the TH1
register on overflow (Figure 8-3). Overflow from TL1 sets overflow flag TF1 in the TCON reg-
ister and reloads TL1 with the contents of TH1, which is preset by software. The reload leaves
8.4.4 Mode 3 (Halt)
Placing timer 1 in mode 3 causes it to halt and hold its count. This can be used to halt timer 1
when the TR1 run control bit is not available, i.e., when timer 0 is in mode 3. See the final para-
graph of section 8.4, “Timer 1.”
8.5 TIMER 0/1 APPLICATIONS
Timer 0 and timer 1 are general purpose timers that can be used in a variety of ways. The timer
applications presented in this section are intended to demonstrate timer setup, and do not repre-
sent the only arrangement nor necessarily the best arrangement for a given task. These examples
employ timer 0, but timer 1 can be set up in the same manner using the appropriate registers.
8.5.1 Auto-load Setup Example
Timer 0 can be configured as an eight-bit timer (TL0) with automatic reload as follows:
1. Program the four low-order bits of the TMOD register (Figure 8-5) to specify: mode 2 for
timer 0, C/T0# = 0 to select FOSC/12 as the timer input, and GATE0 = 0 to select TR0 as
the timer run control.
2. Enter an eight-bit initial value (n0) in timer register TL0, so that the timer overflows after
the desired number of peripheral cycles.
8-9
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3. Enter an eight-bit reload value (nR) in register TH0. This can be the same as n0 or
different, depending on the application.
4. Set the TR0 bit in the TCON register (Figure 8-6) to start the timer. Timer overflow occurs
after FFH + 1 - n0 peripheral cycles, setting the TF0 flag and loading nR into TL0 from
TH0. When the interrupt is serviced, hardware clears TF0.
5. The timer continues to overflow and generate interrupt requests every FFH + 1 - nR
peripheral cycles.
6. To halt the timer, clear the TR0 bit.
8.5.2 Pulse Width Measurements
For timer 0 and timer 1, setting GATEx and TRx allows an external waveform at pin INTx# to
turn the timer on and off. This setup can be used to measure the width of a positive-going pulse
present at pin INTx#. Pulse width measurements using timer 0 in mode 1 can be made as follows:
timer 0, C/T0# = 0 to select FOSC/12 as the timer input, and GATE0 = 1 to select INT0 as
timer run control.
2. Enter an initial value of all zeros in the 16-bit timer register TH0/TL0, or read and store
the current contents of the register.
3. Set the TR0 bit in the TCON register (Figure 8-6) to enable INT0.
4. Apply the pulse to be measured to pin INT0. The timer runs when the waveform is high.
5. Clear the TR0 bit to disable INT0.
6. Read timer register TH0/TL0 to obtain the new value.
7. Calculate pulse width = 12 TOSC × (new value - initial value).
8. Example: FOSC = 16 MHz and 12TOSC = 750 ns. If the new value = 10,00010 and the initial
8.6 TIMER 2
Timer 2 is a 16-bit timer/counter. The count is maintained by two eight-bit timer registers, TH2
and TL2, connected in cascade. The timer/counter 2 mode control register (T2MOD, as shown in
Figure 8-11 on page 8-16) and the timer/counter 2 control register (T2CON, as shown in Figure
8-12 on page 8-17) control the operation of timer 2.
8-10
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TIMER/COUNTERS AND WATCHDOG TIMER
Timer 2 provides the following operating modes: capture mode, auto-reload mode, baud rate gen-
erator mode, and programmable clock-out mode. Select the operating mode with T2MOD and
TCON register bits as shown in Table 8-3 on page 8-15. Auto-reload is the default mode. Setting
RCLK and/or TCLK selects the baud rate generator mode.
Timer 2 operation is similar to timer 0 and timer 1. C/T2# selects FOSC /12 (timer operation) or
external pin T2 (counter operation) as the timer register input. Setting TF2 allows TL2 to be in-
cremented by the selected input.
The operating modes are described in the following paragraphs. Block diagrams in Figures 8-7
through 8-10 show the timer 2 configuration for each mode.
8.6.1 Capture Mode
In the capture mode, timer 2 functions as a 16-bit timer or counter (Figure 8-7). An overflow con-
dition sets bit TF2, which you can use to request an interrupt. Setting the external enable bit
EXEN2 allows the RCAP2H and RCAP2L registers to capture the current value in timer registers
TH2 and TL2 in response to a 1-to-0 transition at external input T2EX. The transition at T2EX
also sets bit EXF2 in T2CON. The EXF2 bit, like TF2, can generate an interrupt.
12
Overflow
XTAL1
T2
0
1
TH2
TL2
TF2
(8 Bits) (8 Bits)
TR2
C/T2#
Capture
Interrupt
Request
RCAP2H RCAP2L
T2EX
EXF2
EXEN2
A4113-02
Figure 8-7. Timer 2: Capture Mode
8-11
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8.6.2 Auto-reload Mode
The auto-reload mode configures timer 2 as a 16-bit timer or event counter with automatic reload.
2 defaults to operation as an up counter.
8.6.2.1
Up Counter Operation
When DCEN = 0, timer 2 operates as an up counter (Figure 8-8). The external enable bit EXEN2
in the T2CON register provides two options (Figure 8-12). If EXEN2 = 0, timer 2 counts up to
FFFFH and sets the TF2 overflow flag. The overflow condition loads the 16-bit value in the re-
load/capture registers (RCAP2H, RCAP2L) into the timer registers (TH2, TL2). The values in
RCAP2H and RCAP2L are preset by software.
If EXEN2 = 1, the timer registers are reloaded by either a timer overflow or a high-to-low tran-
sition at external input T2EX. This transition also sets the EXF2 bit in the T2CON register. Either
TF2 or EXF2 bit can generate a timer 2 interrupt request.
XTAL1
T2
12
0
1
Overflow
TH2
TL2
(8 Bits) (8 Bits)
TR2
C/T2#
Reload
RCAP2H RCAP2L
TF2
Interrupt
Request
T2EX
EXF2
EXEN2
A4115-02
Figure 8-8. Timer 2: Auto Reload Mode (DCEN = 0)
8-12
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TIMER/COUNTERS AND WATCHDOG TIMER
8.6.2.2
Up/Down Counter Operation
When DCEN = 1, timer 2 operates as an up/down counter (Figure 8-9). External pin T2EX con-
trols the direction of the count (Table 8-2 on page 8-3). When T2EX is high, timer 2 counts up.
The timer overflow occurs at FFFFH which sets the timer 2 overflow flag (TF2) and generates an
interrupt request. The overflow also causes the 16-bit value in RCAP2H and RCAP2L to be load-
ed into the timer registers TH2 and TL2.
When T2EX is low, timer 2 counts down. Timer underflow occurs when the count in the timer
registers (TH2, TL2) equals the value stored in RCAP2H and RCAP2L. The underflow sets the
TF2 bit and reloads FFFFH into the timer registers.
The EXF2 bit toggles when timer 2 overflows or underflows changing the direction of the count.
When timer 2 operates as an up/down counter, EXF2 does not generate an interrupt. This bit can
be used to provide 17-bit resolution.
(Down Counting Reload Value)
FFH
FFH
Toggle
XTAL1
12
EXF2
Interrupt
Request
0
1
Overflow
TH2
TL2
TF2
(8 Bits) (8 Bits)
T2
TR2
C/T2#
Count
Direction
1 = Up
0 = Down
RCAP2H RCAP2L
T2EX
(Up Counting Reload Value)
A4114-01
Figure 8-9. Timer 2: Auto Reload Mode (DCEN = 1)
8-13
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8.6.3 Baud Rate Generator Mode
This mode configures timer 2 as a baud rate generator for use with the serial port. Select this mode
by setting the RCLK and/or TCLK bits in T2CON. See Table 8-3. For details regarding this mode
of operation, refer to section 10.6, “Baud Rates.”
8.6.4 Clock-out Mode
In the clock-out mode, timer 2 functions as a 50%-duty-cycle, variable-frequency clock (Figure
8-10). The input clock increments TL0 at frequency FOSC/2. The timer repeatedly counts to over-
flow from a preloaded value. At overflow, the contents of the RCAP2H and RCAP2L registers
are loaded into TH2/TL2. In this mode, timer 2 overflows do not generate interrupts. The formula
gives the clock-out frequency as a function of the system oscillator frequency and the value in the
RCAP2H and RCAP2L registers:
FOSC
Clock-out Frequency = --------------------------------------------------------------------------------------
4 × (65536 - RCAP2H, RCAP2L)
For a 16 MHz system clock, timer 2 has a programmable frequency range of 61 Hz to 4 MHz.
The generated clock signal is brought out to the T2 pin.
Timer 2 is programmed for the clock-out mode as follows:
1. Set the T2OE bit in T2MOD. This gates the timer register overflow to the ÷2 counter.
2. Clear the C/T2# bit in T2CON to select FOSC/2 as the timer input signal. This also gates the
output of the ÷2 counter to pin T2.
3. Determine the 16-bit reload value from the formula and enter in the RCAP2H/RCAP2L
registers.
4. Enter a 16-bit initial value in timer register TH2/TL2. This can be the same as the reload
value, or different, depending on the application.
5. To start the timer, set the TR2 run control bit in T2CON.
Operation is similar to timer 2 operation as a baud rate generator. It is possible to use timer 2 as
a baud rate generator and a clock generator simultaneously. For this configuration, the baud rates
and clock frequencies are not independent since both functions use the values in the RCAP2H
and RCAP2L registers.
8-14
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TIMER/COUNTERS AND WATCHDOG TIMER
XTAL1
T2
2
0
1
TH2
TL2
(8 Bits) (8 Bits)
TR2
RCAP2H RCAP2L
C/T2#
2
T2OE
Interrupt
Request
T2EX
EXF2
EXEN2
A4116-02
Figure 8-10. Timer 2: Clock Out Mode
Table 8-3. Timer 2 Modes of Operation
.
RCLK OR TCLK
(in T2CON)
CP/RL2#
(in T2CON) (in T2MOD)
T2OE
Mode
Auto-reload Mode
0
0
1
X
0
1
X
0
0
0
X
1
Capture Mode
Baud Rate Generator Mode
Programmable Clock-Out
8-15
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Address:
Reset State: XXXX XX00B
S:C9H
T2MOD
7
0
—
—
—
—
—
—
T2OE
DCEN
Bit
Number
Bit
Mnemonic
Function
7:2
—
Reserved:
The values read from these bits are indeterminate. Write zeros to these
bits.
1
0
T2OE
DCEN
Timer 2 Output Enable Bit:
In the timer 2 clock-out mode, connects the programmable clock output
to external pin T2.
Down Count Enable Bit:
Configures timer 2 as an up/down counter.
Figure 8-11. T2MOD: Timer 2 Mode Control Register
8.7 WATCHDOG TIMER
The peripheral section of the 8XC251Sx contains a dedicated, hardware watchdog timer (WDT)
that automatically resets the chip if it is allowed to time out. The WDT provides a means of re-
covering from routines that do not complete successfully due to software malfunctions. The WDT
described in this section is not associated with the PCA watchdog timer, which is implemented
in software.
8.7.1 Description
The WDT is a 14-bit counter that counts peripheral cycles, i.e., the system clock divided by
twelve (FOSC/12). The WDTRST special function register at address S:A6H provides control ac-
cess to the WDT. Two operations control the WDT:
• Device reset clears and disables the WDT (see section 11.4, “Reset”).
• Writing a specific two-byte sequence to the WDTRST register clears and enables the WDT.
If it is not cleared, the WDT overflows on count 3FFFH + 1. With FOSC = 16 MHz, a peripheral
cycle is 750 ns and the WDT overflows in 750 × 16384 = 12.288 ms. The WDTRST is a write-
only register. Attempts to read it return FFH. The WDT itself is not read or write accessible. The
WDT does not drive the external RESET pin.
8-16
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TIMER/COUNTERS AND WATCHDOG TIMER
Address:
Reset State:
S:C8H
0000 0000B
T2CON
7
0
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
C/T2#
CP/RL2#
Bit
Number
Bit
Mnemonic
Function
7
TF2
Timer 2 Overflow Flag:
Set by timer 2 overflow. Must be cleared by software. TF2 is not set if
RCLK = 1 or TCLK = 1.
6
EXF2
Timer 2 External Flag:
If EXEN2 = 1, capture or reload caused by a negative transition on T2EX
sets EFX2. EXF2 does not cause an interrupt in up/down counter mode
(DCEN = 1).
5
4
3
RCLK
TCLK
Receive Clock Bit:
Selects timer 2 overflow pulses (RCLK = 1) or timer 1 overflow pulses
(RCLK = 0) as the baud rate generator for serial port modes 1 and 3.
Transmit Clock Bit:
Selects timer 2 overflow pulses (TCLK = 1) or timer 1 overflow pulses
(TCLK = 0) as the baud rate generator for serial port modes 1 and 3.
EXEN2
Timer 2 External Enable Bit:
Setting EXEN2 causes a capture or reload to occur as a result of a
negative transition on T2EX unless timer 2 is being used as the baud
rate generator for the serial port. Clearing EXEN2 causes timer 2 to
ignore events at T2EX.
2
1
TR2
Timer 2 Run Control Bit:
Setting this bit starts the timer.
C/T2#
Timer 2 Counter/Timer Select:
C/T2# = 0 selects timer operation: timer 2 counts the divided-down
system clock. C/T2# = 1 selects counter operation: timer 2 counts
negative transitions on external pin T2.
0
CP/RL2#
Capture/Reload Bit:
When set, captures occur on negative transitions at T2EX if EXEN2 = 1.
When cleared, auto-reloads occur on timer 2 overflows or negative
transitions at T2EX if EXEN2 = 1. The CP/RL2# bit is ignored and timer 2
forced to auto-reload on timer 2 overflow, if RCLK = 1 or TCLK = 1.
Figure 8-12. T2CON: Timer 2 Control Register
8-17
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8.7.2 Using the WDT
To use the WDT to recover from software malfunctions, the user program should control the
WDT as follows:
1. Following device reset, write the two-byte sequence 1EH-E1H to the WDTRST register to
enable the WDT. The WDT begins counting from 0.
2. Repeatedly for the duration of program execution, write the two-byte sequence 1EH-E1H
to the WDTRST register to clear and enable the WDT before it overflows. The WDT
starts over at 0.
If the WDT overflows, it initiates a device reset (see section 11.4, “Reset”). Device reset clears
the WDT and disables it.
8.7.3 WDT During Idle Mode
Operation of the WDT during the power reduction modes deserves special attention. The WDT
continues to count while the microcontroller is in idle mode. This means the user must service the
WDT during idle. One approach is to use a peripheral timer to generate an interrupt request when
the timer overflows. The interrupt service routine then clears the WDT, reloads the peripheral
timer for the next service period, and puts the microcontroller back into idle.
8.7.4 WDT During PowerDown
The powerdown mode stops all phase clocks. This causes the WDT to stop counting and to hold
its count. The WDT resumes counting from where it left off if the powerdown mode is terminated
by INT0/INT1. To ensure that the WDT does not overflow shortly after exiting the powerdown
mode, clear the WDT just before entering powerdown. The WDT is cleared and disabled if the
powerdown mode is terminated by a reset.
8-18
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9
Programmable
Counter Array
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CHAPTER 9
PROGRAMMABLE COUNTER ARRAY
This chapter describes the programmable counter array (PCA), an on-chip peripheral of the
8XC251Sx that performs a variety of timing and counting operations, including pulse width mod-
ulation (PWM). The PCA provides the capability for a software watchdog timer (WDT).
9.1 PCA DESCRIPTION
The programmable counter array (PCA) consists of a 16-bit timer/counter and five 16-bit com-
pare/capture modules. The timer/counter serves as a common time base and event counter for the
A special function register (SFR) pair, CH/CL, maintains the count in the timer/counter, while
five SFR pairs, CCAPxH/CCAPxL, store values for the modules (see Figure 9-1). Additional
SFRs provide control and mode select functions as follows:
(CCON) control the operation of the timer/counter. See Figure 9-7 on page 9-13 and Figure
9-8 on page 9-14.
• Five PCA module mode registers (CCAPMx) specify the operating modes of the
compare/capture modules. See Figure 9-9.
For a list of SFRs associated with the PCA, see Table 9-1. For an address map of all SFRs, see
Table 3-5 on page 3-17. Port 1 provides external I/O for the PCA on a shared basis with other
functions. Table 9-2 identifies the port pins associated with the timer/counter and compare/cap-
ture modules. When not used for PCA I/O, these pins can be used for standard I/O functions.
The operating modes of the five compare/capture modules determine the functions performed by
the PCA. Each module can be independently programmed to provide input capture, output com-
pare, or pulse width modulation. Module 4 only also has a watchdog-timer mode.
EC bit in the IE special function register is a global interrupt enable for the PCA. Capture events,
compare events in some modes, and PCA timer/counter overflow all set flags in the CCON reg-
ister. Setting the overflow flag (CF) generates a PCA interrupt request if the PCA timer/counter
interrupt enable bit (ECF) in the CMOD register is set (Figure 9-1). Setting a compare/capture
flag (CCFx) generates a PCA interrupt request if the ECCFx interrupt enable bit in the corre-
sponding CCAPMx register is set (Figures 9-2 and 9-3). For a description of the 8XC251Sx in-
terrupt system see Chapter 6, “Interrupt System.”
9-1
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9.1.1 Alternate Port Usage
PCA modules 3 and 4 share port pins with the real-time wait state and address functions as fol-
lows:
• PCA module 3 — P1.6/CEX3/WAIT#
• PCA module 4 — P1.7/CEX4/A17/WCLK
When the real-time wait state functions are enabled (using the WCON register), the correspond-
ing PCA modules are automatically disabled. Configuring the 8XC251Sx to use address line A17
(specified by UCONFIG0, bits RD1:0) overrides the PCA module 3 and WCLK functions. When
a real-time wait state function is enabled, do not use the corresponding PCA module.
NOTE
operations at port 1.6 (CEX3/WAIT#) or port 1.7 (CEX4/WCLK). See section
13.5, “External Bus Cycles with Real-time Wait States.”
9.2 PCA TIMER/COUNTER
Figure 9-1 depicts the basic logic of the timer/counter portion of the PCA. The CH/CL special
(low byte) register. When CL overflows, the CH (high byte) register increments after two oscil-
lator periods; when CH overflows it sets the PCA overflow flag (CF in the CCON register) gen-
erating a PCA interrupt request if the ECF bit in the CMOD register is set.
The CPS1 and CPS0 bits in the CMOD register select one of four signals as the input to the
timer/counter (Figure 9-7).
• FOSC/12. Provides a clock pulse at S5P2 of every peripheral cycle. With FOSC = 16 MHz, the
time/counter increments every 750 nanoseconds.
• FOSC/4. Provides clock pulses at S1P2, S3P2, and S5P2 of every peripheral cycle. With
FOSC = 16 MHz, the time/counter increments every 250 nanoseconds.
• Timer 0 overflow. The CL register is incremented at S5P2 of the peripheral cycle when
timer 0 overflows. This selection provides the PCA with a programmable frequency input.
• External signal on P1.2/ECI. The CPU samples the ECI pin at S1P2, S3P2, and S5P2 of
every peripheral cycle. The first clock pulse (S1P2, S3P2, or S5P2) that occurs following a
high-to-low transition at the ECI pin increments the CL register. The maximum input
frequency for this input selection is FOSC/8.
For a description of peripheral cycle timing, see section 2.2.2, “Clock and Reset Unit.”
9-2
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Setting the run control bit (CR in the CCON register) turns the PCA timer/counter on, if the out-
put of the NAND gate (Figure 9-1) equals logic 1. The PCA timer/counter continues to operate
during idle mode unless the CIDL bit of the CMOD register is set. The CPU can read the contents
of the CH and CL registers at any time. However, writing to them is inhibited while they are
counting (i.e., when the CR bit is set).
Compare/Capture
Modules
Module 0
Module 1
Module 2
Module 3
P1.3/CEX0
P1.4/CEX1
16-bit
Bus
P1.5/CEX2
P1.6/CEX3/WAIT#
P1.7/CEX4/
A17/WCLK
Module 4
(16 Bits)
00
01
10
11
F
/12
OSC
Interrupt
Request
F
/4
OSC
CH
CL
CF
(8 Bits) (8 Bits)
Timer 0 Overflow
P1.2/ECI
PCA
CCON.7
Overflow
Timer/Counter
CPS1
CPS0
CIDL
ECF
CMOD.2 CMOD.1 CMOD.7
CMOD.0
Enable
IDL
PCON.0
Idle Mode Run Control
CR
CCON.6
A4162-04
Figure 9-1. Programmable Counter Array
9-3
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Table 9-1. PCA Special Function Registers (SFRs)
Mnemonic
Description
Address
CL
CH
PCA Timer/Counter. These registers serve as a common 16-bit timer or
event counter for the five compare/capture modules. Counts FOSC/12,
S:E9H
S:F9H
F
OSC/4, timer 0 overflow, or the external signal on P1.2/ECI, as selected by
CMOD. In PWM mode CL operates as an 8-bit timer.
CCON
CMOD
PCA Timer/Counter Control Register. Contains the run control bit and
the overflow flag for the PCA timer/counter, and interrupt flags for the five
compare/capture modules.
S:D8H
S:D9H
PCA Timer/Counter Mode Register. Contains bits for disabling the PCA
timer/counter during idle mode, enabling the PCA watchdog timer (module
4), selecting the timer/counter input, and enabling the PCA timer/counter
overflow interrupt.
CCAP0H
CCAP0L
PCA Module 0 Compare/Capture Registers. This register pair stores the
comparison value or the captured value. In the PWM mode, the low-byte
register controls the duty cycle of the output waveform.
S:FAH
S:EAH
CCAP1H
CCAP1L
PCA Module 1 Compare/Capture Registers. This register pair stores the
comparison value or the captured value. In the PWM mode, the low-byte
register controls the duty cycle of the output waveform.
S:FBH
S:EBH
CCAP2H
CCAP2L
PCA Module 2 Compare/Capture Registers. This register pair stores the
comparison value or the captured value. In the PWM mode, the low-byte
register controls the duty cycle of the output waveform.
S:FCH
S:ECH
CCAP3H
CCAP3L
PCA Module 3 Compare/Capture Registers. This register pair stores the
comparison value or the captured value. In the PWM mode, the low-byte
register controls the duty cycle of the output waveform.
S:FDH
CCAP4H
CCAP4L
PCA Module 4 Compare/Capture Registers. This register pair stores the
comparison value or the captured value. In the PWM mode, the low-byte
register controls the duty cycle of the output waveform.
S:FEH
S:EEH
CCAPM0
CCAPM1
CCAPM2
CCAPM3
CCAPM4
PCA Compare/Capture Module Mode Registers. Contain bits for
selecting the operating mode of the compare/capture modules and
enabling the compare/capture flag. See Table 9-3 on page 9-14 for mode
select bit combinations.
S:DAH
S:DBH
S:DCH
S:DDH
S:DEH
Table 9-2. External Signals
Signal
Name
Alternate
Function
Type
Description
ECI
I
PCA Timer/counter External Input. This signal is the external
P1.2
clock input for the PCA timer/counter.
CEX0
CEX1
CEX2
CEX3
CEX4
I/O
Compare/Capture Module External I/O. Each compare/capture
module connects to a Port 1 pin for external I/O. When not used by
the PCA, these pins can handle standard I/O.
P1.3
P1.4
P1.5
P1.6/WAIT#
P1.7/A17/WCLK
9-4
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9.3 PCA COMPARE/CAPTURE MODULES
Each compare/capture module is made up of
a
compare/capture register pair
The registers store the time or count at which an external event occurred (capture) or at which an
action should occur (comparison). In the PWM mode, the low-byte register controls the duty cy-
cle of the output waveform.
The logical configuration of a compare/capture module depends on its mode of operation
(Figures 9-2 through 9-5). Each module can be independently programmed for operation in any
of the following modes:
• 16-bit capture mode with triggering on the positive edge, negative edge, or either edge.
• Compare modes: 16-bit software timer, 16-bit high-speed output, 16-bit WDT (module 4
only), or 8-bit pulse width modulation.
• No operation.
Bit combinations programmed into a compare/capture module’s mode register (CCAPMx) deter-
mine the operating mode. Figure 9-9 provides bit definitions and Table 9-3 lists the bit combina-
tions of the available modes. Other bit combinations are invalid and produce undefined results.
The compare/capture modules perform their programmed functions when their common time
base, the PCA timer/counter, runs. The timer/counter is turned on and off with the CR bit in the
CCON register. To disable any given module, program it for the no operation mode. The occur-
rence of a capture, software timer, or high-speed output event in a compare/capture module sets
the module’s compare/capture flag (CCFx) in the CCON register and generates a PCA interrupt
The CPU can read or write the CCAPxH and CCAPxL registers at any time.
9.3.1 16-bit Capture Mode
The capture mode (Figure 9-2) provides the PCA with the ability to measure periods, pulse
widths, duty cycles, and phase differences at up to five separate inputs. External I/O pins CEX0
through CEX4 are sampled for signal transitions (positive and/or negative as specified). When a
compare/capture module programmed for the capture mode detects the specified transition, it
captures the PCA timer/counter value. This records the time at which an external event is detect-
ed, with a resolution equal to the timer/counter clock period.
9-5
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To program a compare/capture module for the 16-bit capture mode, program the CAPPx and
• To trigger the capture on a positive transition, set CAPPx and clear CAPNx.
• To trigger the capture on a negative transition, set CAPNx and clear CAPPx.
Table 9-3 on page 9-14 lists the bit combinations for selecting module modes. For modules in the
capture mode, detection of a valid signal transition at the I/O pin (CEXx) causes hardware to load
the current PCA timer/counter value into the compare/capture registers (CCAPxH/CCAPxL) and
to set the module’s compare/capture flag (CCFx) in the CCON register. If the corresponding in-
terrupt enable bit (ECCFx) in the CCAPMx register is set (Figure 9-9), the PCA sends an interrupt
request to the interrupt handler.
Since hardware does not clear the event flag when the interrupt is processed, the user must clear
the flag in software. A subsequent capture by the same module overwrites the existing captured
value. To preserve a captured value, save it in RAM with the interrupt service routine before the
next capture event occurs.
PCA Timer/Counter
Count
Input
CH
CL
(8 Bits) (8 Bits)
Capture
CEXx
External I/O
CCAPxH CCAPxL
x = 0,1,2,3 or 4
X = Don't Care
Interrupt
Request
CCFx
CCON Register
Enable
X
7
O
CAPPx CAPNx
O
O
O
ECCFx
0
CCAPMx Mode Register
A4163-02
Figure 9-2. PCA 16-bit Capture Mode
9-6
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9.3.2 Compare Modes
The compare function provides the capability for operating the five modules as timers, event
counters, or pulse width modulators. Four modes employ the compare function: 16-bit software
timer mode, high-speed output mode, WDT mode, and PWM mode. In the first three of these, the
compare/capture module continuously compares the 16-bit PCA timer/counter value with the 16-
bit value pre-loaded into the module’s CCAPxH/CCAPxL register pair. In the PWM mode, the
an 8-bit value in the CCAPxL module register. Comparisons are made three times per peripheral
cycle to match the fastest PCA timer/counter clocking rate (FOSC/4). For a description of periph-
eral cycle timing, see section 2.2.2, “Clock and Reset Unit.”
Setting the ECOMx bit in a module’s mode register (CCAPMx) selects the compare function for
that module (Figure 9-9 on page 9-15). To use the modules in the compare modes, observe the
following general procedure:
1. Select the module’s mode of operation.
2. Select the input signal for the PCA timer/counter.
3. Load the comparison value into the module’s compare/capture register pair.
4. Set the PCA timer/counter run control bit.
5. After a match causes an interrupt, clear the module’s compare/capture flag.
9.3.3 16-bit Software Timer Mode
To program a compare/capture module for the 16-bit software timer mode (Figure 9-3), set the
ECOMx and MATx bits in the module’s CCAPMx register. Table 9-3 lists the bit combinations
for selecting module modes.
A match between the PCA timer/counter and the compare/capture registers (CCAPxH/CCAPxL)
sets the module’s compare/capture flag (CCFx in the CCON register). This generates an interrupt
request if the corresponding interrupt enable bit (ECCFx in the CCAPMx register) is set. Since
hardware does not clear the compare/capture flag when the interrupt is processed, the user must
clear the flag in software. During the interrupt routine, a new 16-bit compare value can be written
to the compare/capture registers (CCAPxH/CCAPxL).
NOTE
To prevent an invalid match while updating these registers, user software
should write to CCAPxL first, then CCAPxH. A write to CCAPxL clears the
ECOMx bit disabling the compare function, while a write to CCAPxH sets the
ECOMx bit re-enabling the compare function.
9-7
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Compare/Capture
PCA Timer/Counter
CH CL
Module
Count
Input
CCAPxH CCAPxL
(8 Bits) (8 Bits)
(8 Bits) (8 Bits)
Toggle
Match
16-Bit
Comparator
CEXx
Interrupt
Request
Enable
CCFx
CCON
Enable
X
7
ECOMx
0
0
MATx
TOGx
0
ECCFx
0
CCAPMx Mode Register
"0"
Reset
Write to
CCAPxL
X = Don't Care
x = 0, 1, 2, 3, 4
For software timer mode, set ECOMx and MATx.
"1"
Write to CCAPxH
For high speed output mode, set ECOMx, MATx, and TOGx.
A4164-01
Figure 9-3. PCA Software Timer and High-speed Output Modes
9.3.4 High-speed Output Mode
pin (CEXx) when a match occurs. This provides greater accuracy than toggling pins in software
because the toggle occurs before the interrupt request is serviced. Thus, interrupt response time
does not affect the accuracy of the output.
To program a compare/capture module for the high-speed output mode, set the ECOMx, MATx,
TOGx bits in the module’s CCAPMx register. Table 9-3 on page 9-14 lists the bit combinations
for selecting module modes. A match between the PCA timer/counter and the compare/capture
registers (CCAPxH/CCAPxL) toggles the CEXx pin and sets the module’s compare/capture flag
(CCFx in the CCON register). By setting or clearing the CEXx pin in software, the user selects
whether the match toggles the pin from low to high or vice versa.
9-8
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PROGRAMMABLE COUNTER ARRAY
The user also has the option of generating an interrupt request when the match occurs by setting
the corresponding interrupt enable bit (ECCFx in the CCAPMx register). Since hardware does not
clear the compare/capture flag when the interrupt is processed, the user must clear the flag in soft-
ware.
If the user does not change the compare/capture registers in the interrupt routine, the next toggle
occurs after the PCA timer/counter rolls over and the count again matches the comparison value.
During the interrupt routine, a new 16-bit compare value can be written to the compare/capture
registers (CCAPxH/CCAPxL).
NOTE
To prevent an invalid match while updating these registers, user software
should write to CCAPxL first, then CCAPxH. A write to CCAPxL clears the
ECOMx bit disabling the compare function, while a write to CCAPxH sets the
ECOMx bit re-enabling the compare function.
9.3.5 PCA Watchdog Timer Mode
A watchdog timer (WDT) provides the means to recover from routines that do not complete suc-
cessfully. A WDT automatically invokes a device reset if it does not regularly receive hold-off
signals. WDTs are used in applications that are subject to electrical noise, power glitches, elec-
trostatic discharges, etc., or where high reliability is required.
In addition to the 8XC251Sx’s 14-bit hardware WDT, the PCA provides a programmable-fre-
compare/capture registers. A PCA WDT reset has the same effect as an external reset. Module 4
is the only PCA module that has the WDT mode. When not programmed as a WDT, it can be used
in the other modes.
To program module 4 for the PCA WDT mode (Figure 9-4), set the ECOM4 and MAT4 bits in
the CCAPM4 register and the WDTE bit in the CMOD register. Table 9-3 lists the bit combina-
tions for selecting module modes. Also select the desired input for the PCA timer/counter by pro-
gramming the CPS0 and CPS1 bits in the CMOD register (see Figure 9-7 on page 9-13). Enter a
16-bit comparison value in the compare/capture registers (CCAP4H/CCAP4L). Enter a 16-bit
initial value in the PCA timer/counter (CH/CL) or use the reset value (0000H). The difference
between these values multiplied by the PCA input pulse rate determines the running time to “ex-
piration.” Set the timer/counter run control bit (CR in the CCON register) to start the PCA WDT.
9-9
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The PCA WDT generates a reset signal each time a match occurs. To hold off a PCA WDT reset,
the user has three options:
• periodically change the comparison value in CCAP4H/CCAP4L so a match never occurs
• periodically change the PCA timer/counter value so a match never occurs
• disable the module 4 reset output signal by clearing the WDTE bit before a match occurs,
then later re-enable it
The first two options are more reliable because the WDT is not disabled as in the third option.
The second option is not recommended if other PCA modules are in use, since the five modules
share a common time base. Thus, in most applications the first option is the best one.
Compare/Capture
PCA Timer/Counter
CH CL
Module
Count
Input
CCAP4H CCAP4L
(8 Bits) (8 Bits)
(8 Bits) (8 Bits)
Match
16-Bit
Comparator
PCA WDT Reset
WDTE
Enable
CMOD.6
X
7
ECOM4
0
0
1
X
0
X
0
CCAPM4 Mode Register
"0"
"1"
Reset
Write to
CCAP4L
X = Don't Care
Write to CCAP4H
A4165-01
Figure 9-4. PCA Watchdog Timer Mode
9-10
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9.3.6 Pulse Width Modulation Mode
The five PCA comparator/capture modules can be independently programmed to function as
of eight bits, is available at the CEXx pin. The PWM output can be used to convert digital data to
an analog signal with simple external circuitry.
In this mode the value in the low byte of the PCA timer/counter (CL) is continuously compared
with the value in the low byte of the compare/capture register (CCAPxL). When CL < CCAPxL,
the output waveform (Figure 9-6) is low. When a match occurs (CL = CCAPxL), the output wave-
form goes high and remains high until CL rolls over from FFH to 00H, ending the period. At roll-
over the output returns to a low, the value in CCAPxH is loaded into CCAPxL, and a new period
begins.
CCAPxH
CL rollover from FFH to 00H loads
CCAPxH contents into CCAPxL
CCAPxL
X = Don't Care
x = 0, 1, 2, 3, 4.
8
"0"
8
CL < CCAPxL
CL
(8 Bits)
8-Bit
Comparator
CEXx
CL ≥ CCAPxL
"1"
Enable
X
7
ECOMx
0
0
0
0
PWMx
0
0
CCAPMx Mode Register
A4166-01
Figure 9-5. PCA 8-bit PWM Mode
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The value in CCAPxL determines the duty cycle of the current period. The value in CCAPxH de-
termines the duty cycle of the following period. Changing the value in CCAPxL over time mod-
ulates the pulse width. As depicted in Figure 9-6, the 8-bit value in CCAPxL can vary from 0
(100% duty cycle) to 255 (0.4% duty cycle).
NOTE
To change the value in CCAPxL without glitches, write the new value to the
high byte register (CCAPxH). This value is shifted by hardware into CCAPxL
when CL rolls over from FFH to 00H.
The frequency of the PWM output equals the frequency of the PCA timer/counter input signal
er/counter. For FOSC = 16 MHz, this is 15.6 KHz.
To program a compare/capture module for the PWM mode, set the ECOMx and PWMx bits in
the module’s CCAPMx register. Table 9-3 lists the bit combinations for selecting module modes.
Also select the desired input for the PCA timer/counter by programming the CPS0 and CPS1 bits
in the CMOD register (see Figure 9-7). Enter an 8-bit value in CCAPxL to specify the duty cycle
of the first period of the PWM output waveform. Enter an 8-bit value in CCAPxH to specify the
duty cycle of the second period. Set the timer/counter run control bit (CR in the CCON register)
to start the PCA timer/counter.
Duty
Cycle
0.4%
10%
CCAPxL
255
230
128
25
Output Waveform
1
0
1
0
1
0
1
0
1
0
50%
90%
0
100%
A4161-01
Figure 9-6. PWM Variable Duty Cycle
9-12
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Address:
Reset State: 00XX X000B
S:D9H
CMOD
7
0
CIDL
WDTE
—
—
—
CPS1
CPS0
ECF
Bit
Number
Bit
Mnemonic
Function
PCA Timer/Counter Idle Control:
7
CIDL
CIDL = 1 disables the PCA timer/counter during idle mode. CIDL = 0
allows the PCA timer/counter to run during idle mode.
6
WDTE
—
Watchdog Timer Enable:
WDTE = 1 enables the watchdog timer output on PCA module 4.
WDTE = 0 disables the PCA watchdog timer output.
5:3
2:1
Reserved:
The values read from these bits are indeterminate. Write zeros to these
bits.
CPS1:0
PCA Timer/Counter Input Select:
CPS1 CPS0
0
0
1
1
0
1
0
1
F
F
OSC /12
OSC /4
Timer 0 overflow
External clock at ECI pin (maximum rate = FOSC /8 )
0
ECF
PCA Timer/Counter Interrupt Enable:
ECF = 1 enables the CF bit in the CCON register to generate an interrupt
request.
Figure 9-7. CMOD: PCA Timer/Counter Mode Register
9-13
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Address:
Reset State:
S:D8H
00X0 0000B
CCON
7
0
CF
CR
—
CCF4
CCF3
CCF2
CCF1
CCF0
Bit
Number
Bit
Mnemonic
Function
PCA Timer/Counter Overflow Flag:
7
CF
Set by hardware when the PCA timer/counter rolls over. This generates
an interrupt request if the ECF interrupt enable bit in CMOD is set. CF
can be set by hardware or software but can be cleared only by software.
6
CR
PCA Timer/Counter Run Control Bit:
Set and cleared by software to turn the PCA timer/counter on and off.
5
—
Reserved:
The value read from this bit is indeterminate. Write a zero to this bit.
4:0
CCF4:0
PCA Module Compare/Capture Flags:
Set by hardware when a match or capture occurs. This generates a PCA
interrupt request if the ECCFx interrupt enable bit in the corresponding
CCAPMx register is set. Must be cleared by software.
Figure 9-8. CCON: PCA Timer/Counter Control Register
Table 9-3. PCA Module Modes
ECOMx CAPPx CAPNx
MATx
TOGx
PWMx ECCFx
Module Mode
No operation
0
0
1
0
0
0
0
0
0
0
0
0
X
X
16-bit capture on positive-edge
trigger at CEXx
X
X
0
1
1
1
0
0
0
0
0
0
X
X
16-bit capture on negative-edge
trigger at CEXx
16-bit capture on positive- or
negative-edge trigger at CEXx
1
1
1
1
0
0
0
0
0
0
0
0
1
1
0
1
0
1
0
X
0
0
1
0
X
X
0
Compare: software timer
Compare: high-speed output
Compare: 8-bit PWM
X
Compare: PCA WDT
(CCAPM4 only) (Note 3)
NOTES:
1. This table shows the CCAPMx register bit combinations for selecting the operating modes of the PCA
compare/capture modules. Other bit combinations are invalid. See Figure 9-9 for bit definitions.
2. x = 0–4, X = Don’t care.
3. For PCA WDT mode, also set the WDTE bit in the CMOD register to enable the reset output signal.
9-14
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Address: CCAPM0 S:DAH
CCAPM1 S:DBH
CCAPMx (x = 0–4)
CCAPM2 S:DCH
CCAPM3 S:DDH
CCAPM4 S:DEH
Reset State: X000 0000B
7
0
—
ECOMx
CAPPx
CAPNx
MATx
TOGx
PWMx
ECCFx
Bit
Number
Bit
Mnemonic
Function
7
—
Reserved:
The value read from this bit is indeterminate. Write a zero to this bit.
Compare Modes:
6
ECOMx
ECOMx = 1 enables the module comparator function. The comparator is
used to implement the software timer, high-speed output, pulse width
modulation, and watchdog timer modes.
5
4
3
CAPPx
CAPNx
MATx
Capture Mode (Positive):
CAPPx = 1 enables the capture function with capture triggered by a
positive edge on pin CEXx.
Capture Mode (Negative):
CAPNx = 1 enables the capture function with capture triggered by a
negative edge on pin CEXx.
Match:
Set ECOMx and MATx to implement the software timer mode. When
MATx = 1, a match of the PCA timer/counter with the compare/capture
register sets the CCFx bit in the CCON register, flagging an interrupt.
2
TOGx
Toggle:
Set ECOMx, MATx, and TOGx to implement the high-speed output
mode. When TOGx = 1, a match of the PCA timer/counter with the
compare/capture register toggles the CEXx pin.
1
0
PWMx
ECCFx
Pulse Width Modulation Mode:
PWMx = 1 configures the module for operation as an 8-bit pulse width
modulator with output waveform on the CEXx pin.
Enable CCFx Interrupt:
Enables compare/capture flag CCFx in the CCON register to generate
an interrupt request.
Figure 9-9. CCAPMx: PCA Compare/Capture Module Mode Registers
9-15
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10
Serial I/O Port
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CHAPTER 10
SERIAL I/O PORT
The serial input/output port supports communication with modems and other external peripheral
devices. This chapter provides instructions for programming the serial port and generating the se-
rial I/O baud rates with timer 1 and timer 2.
10.1 OVERVIEW
The serial I/O port provides both synchronous and asynchronous communication modes. It oper-
ates as a universal asynchronous receiver and transmitter (UART) in three full-duplex modes
(modes 1, 2, and 3). Asynchronous transmission and reception can occur simultaneously and at
cation, and automatic address recognition. The serial port also operates in a single synchronous
mode (mode 0).
The synchronous mode (mode 0) operates at a single baud rate. Mode 2 operates at two baud
rates. Modes 1 and 3 operate over a wide range of baud rates, which are generated by timer 1 and
timer 2. Baud rates are detailed in section 10.6, “Baud Rates.”
The serial port signals are defined in Table 10-1, and the serial port special function registers are
described in Table 10-2. Figure 10-1 is a block diagram of the serial port.
For the three asynchronous modes, the UART transmits on the TXD pin and receives on the RXD
pin. For the synchronous mode (mode 0), the UART outputs a clock signal on the TXD pin and
sends and receives messages on the RXD pin (Figure 10-1). The SBUF register, which holds re-
ceived bytes and bytes to be transmitted, actually consists of two physically different registers.
To send, software writes a byte to SBUF; to receive, software reads SBUF. The receive shift reg-
ister allows reception of a second byte before the first byte has been read from SBUF. However,
if software has not read the first byte by the time the second byte is received, the second byte will
overwrite the first. The UART sets interrupt bits TI and RI on transmission and reception, respec-
tively. These two bits share a single interrupt request and interrupt vector.
Table 10-1. Serial Port Signals
Function
Name
Multiplexed
With
Type
Description
TXD
RXD
O
Transmit Data. In mode 0, TXD transmits the clock signal. In
modes 1, 2, and 3, TXD transmits serial data.
P3.1
P3.0
I/O
Receive Data. In mode 0, RXD transmits and receives serial
data. In modes 1, 2, and 3, RXD receives serial data.
10-1
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Table 10-2. Serial Port Special Function Registers
Mnemonic
Description
Address
SBUF
Serial Buffer. Two separate registers comprise the SBUF register. Writing
to SBUF loads the transmit buffer; reading SBUF accesses the receive
buffer.
99H
SCON
Serial Port Control. Selects the serial port operating mode. SCON enables
and disables the receiver, framing bit error detection, multiprocessor
communication, automatic address recognition, and the serial port interrupt
bits.
98H
SADDR
SADEN
Serial Address. Defines the individual address for a slave device.
A8H
B8H
Serial Address Enable. Specifies the mask byte that is used to define the
given address for a slave device.
IB Bus
Write SBUF
Read SBUF
TXD
SBUF
SBUF
(Transmit)
(Receive)
Mode 0
Transmit
Load SBUF
Receive
Shift Register
RXD
Interrupt
Request
RI
TI
Serial I/O
Control
SCON
A4123-02
Figure 10-1. Serial Port Block Diagram
10-2
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SERIAL I/O PORT
The serial port control (SCON) register (Figure 10-2) configures and controls the serial port.
Address:
Reset State:
98H
0000 0000B
SCON
7
0
FE/SM0
SM1
SM2
REN
TB8
RB8
TI
RI
Bit
Number
Bit
Mnemonic
Function
7
FE
Framing Error Bit:
To select this function, set the SMOD0 bit in the PCON register. Set by
hardware to indicate an invalid stop bit. Cleared by software, not by valid
frames.
SM0
SM1
Serial Port Mode Bit 0:
To select this function, clear the SMOD0 bit in the PCON register.
Software writes to bits SM0 and SM1 to select the serial port operating
mode. Refer to the SM1 bit for the mode selections.
6
Serial Port Mode Bit 1:
Software writes to bits SM1 and SM0 (above) to select the serial port
operating mode.
SM0 SM1 Mode
Description
Shift register
8-bit UART
9-bit UART
9-bit UART
Baud Rate
OSC/12
Variable
0
0
1
1
†
0
1
0
1
0
1
2
3
F
†
†
F
OSC/32 or FOSC/64
Variable
Select by programming the SMOD bit in the PCON register (see section
10.6, “Baud Rates”).
5
SM2
Serial Port Mode Bit 2:
Software writes to bit SM2 to enable and disable the multiprocessor
communication and automatic address recognition features. This allows
the serial port to differentiate between data and command frames and to
recognize slave and broadcast addresses.
4
3
REN
TB8
Receiver Enable Bit:
To enable reception, set this bit. To enable transmission, clear this bit.
Transmit Bit 8:
In modes 2 and 3, software writes the ninth data bit to be transmitted to
TB8. Not used in modes 0 and 1.
2
RB8
Receiver Bit 8:
Mode 0: Not used.
Mode 1 (SM2 clear): Set or cleared by hardware to reflect the stop bit
received.
Modes 2 and 3 (SM2 set): Set or cleared by hardware to reflect the ninth
data bit received.
Figure 10-2. SCON: Serial Port Control Register
10-3
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1
0
TI
Transmit Interrupt Flag Bit:
Set by the transmitter after the last data bit is transmitted. Cleared by
software.
RI
Receive Interrupt Flag Bit:
Set by the receiver after the last data bit of a frame has been received.
Cleared by software.
Figure 10-2. SCON: Serial Port Control Register (Continued)
10.2 MODES OF OPERATION
The serial I/O port can operate in one synchronous and three asynchronous modes.
10.2.1 Synchronous Mode (Mode 0)
Mode 0 is a half-duplex, synchronous mode, which is commonly used to expand the I/O capabil-
ities of a device with shift registers. The transmit data (TXD) pin outputs a set of eight clock puls-
es while the receive data (RXD) pin transmits or receives a byte of data. The eight data bits are
transmitted and received least-significant bit (LSB) first. Shifts occur in the last phase (S6P2) of
every peripheral cycle, which corresponds to a baud rate of FOSC/12. Figure 10-3 shows the timing
for transmission and reception in mode 0.
10.2.1.1
Transmission (Mode 0)
Follow these steps to begin a transmission:
1. Write to the SCON register, clearing bits SM0, SM1, and REN.
2. Write the byte to be transmitted to the SBUF register. This write starts the transmission.
Hardware executes the write to SBUF in the last phase (S6P2) of a peripheral cycle. At S6P2 of
the following cycle, hardware shifts the LSB (D0) onto the RXD pin. At S3P1 of the next cycle,
the TXD pin goes low for the first clock-signal pulse. Shifts continue every peripheral cycle. In
the ninth cycle after the write to SBUF, the MSB (D7) is on the RXD pin. At the beginning of the
tenth cycle, hardware drives the RXD pin high and asserts TI (S1P1) to indicate the end of the
transmission.
10-4
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SERIAL I/O PORT
Transmit
TXD
S3P1 S6P1
Write to
SBUF
S6P2
Shift
RXD
TI
S6P2
S6P2
D2
S6P2
D6
S6P2
D0
D1
D7
S6P2
S6P2
S1P1
Receive
TXD
S3P1 S6P1
Set REN, Clear RI
Write to
SCON
S6P2
S6P2
Shift
S6P2
S6P2
D1
S6P2
D6
S6P2
D7
D0
RXD
RI
S6P2
S5P2
S1P1
A4124-02
Figure 10-3. Mode 0 Timing
10.2.1.2
Reception (Mode 0)
To start a reception in mode 0, write to the SCON register. Clear bits SM0, SM1, and RI and set
the REN bit.
Hardware executes the write to SCON in the last phase (S6P2) of a peripheral cycle (Figure 10-3).
In the second peripheral cycle following the write to SCON, TXD goes low at S3P1 for the first
clock-signal pulse, and the LSB (D0) is sampled on the RXD pin at S5P2. The D0 bit is then shift-
ed into the shift register. After eight shifts at S6P2 of every peripheral cycle, the LSB (D7) is shift-
ed into the shift register, and hardware asserts RI (S1P1) to indicate a completed reception.
Software can then read the received byte from SBUF.
10-5
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10.2.2 Asynchronous Modes (Modes 1, 2, and 3)
The serial port has three asynchronous modes of operation.
consists of 10 bits: one start bit, eight data bits, and one stop bit. Serial data is transmitted
on the TXD pin and received on the RXD pin. When a message is received, the stop bit is
read in the RB8 bit in the SCON register. The baud rate is generated by overflow of timer 1
or timer 2 (see section 10.6, “Baud Rates”).
• Modes 2 and 3. Modes 2 and 3 are full-duplex, asynchronous modes. The data frame
(Figure 10-4) consists of 11 bits: one start bit, eight data bits (transmitted and received LSB
first), one programmable ninth data bit, and one stop bit. Serial data is transmitted on the
TXD pin and received on the RXD pin. On receive, the ninth bit is read from the RB8 bit in
the SCON register. On transmit, the ninth data bit is written to the TB8 bit in the SCON
register. Alternatively, you can use the ninth bit as a command/data flag.
— In mode 2, the baud rate is programmable to 1/32 or 1/64 of the oscillator frequency.
— In mode 3, the baud rate is generated by overflow of timer 1 or timer 2.
D0
D1
D2
D3
D4
D5
D6
D7
D8
Data Byte
Start Bit
Ninth Data Bit (Modes 2 and 3 only)
Stop Bit
A2261-01
Figure 10-4. Data Frame (Modes 1, 2, and 3)
Transmission (Modes 1, 2, 3)
Follow these steps to initiate a transmission:
10.2.2.1
1. Write to the SCON register. Select the mode with the SM0 and SM1 bits, and clear the
REN bit. For modes 2 and 3, also write the ninth bit to the TB8 bit.
2. Write the byte to be transmitted to the SBUF register. This write starts the transmission.
10.2.2.2
Reception (Modes 1, 2, 3)
To prepare for a reception, set the REN bit in the SCON register. The actual reception is then ini-
tiated by a detected high-to-low transition on the RXD pin.
10-6
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SERIAL I/O PORT
10.3 FRAMING BIT ERROR DETECTION (MODES 1, 2, AND 3)
Framing bit error detection is provided for the three asynchronous modes. To enable the framing
bit error detection feature, set the SMOD0 bit in the PCON register (Figure 12-1 on page 12-2).
When this feature is enabled, the receiver checks each incoming data frame for a valid stop bit.
An invalid stop bit may result from noise on the serial lines or from simultaneous transmission
by two CPUs. If a valid stop bit is not found, the software sets the FE bit in the SCON register
(Figure 10-2).
Software may examine the FE bit after each reception to check for data errors. Once set, only soft-
ware or a reset can clear the FE bit. Subsequently received frames with valid stop bits cannot clear
the FE bit.
10.4 MULTIPROCESSOR COMMUNICATION (MODES 2 AND 3)
Modes 2 and 3 provide a ninth-bit mode to facilitate multiprocessor communication. To enable
this feature, set the SM2 bit in the SCON register (Figure 10-2). When the multiprocessor com-
munication feature is enabled, the serial port can differentiate between data frames (ninth bit
clear) and address frames (ninth bit set). This allows the microcontroller to function as a slave
processor in an environment where multiple slave processors share a single serial line.
When the multiprocessor communication feature is enabled, the receiver ignores frames with the
ninth bit clear. The receiver examines frames with the ninth bit set for an address match. If the
received address matches the slave’s address, the receiver hardware sets the RB8 bit and the RI
bit in the SCON register, generating an interrupt.
NOTE
The ES bit must be set in the IE register to allow the RI bit to generate an
interrupt. The IE register is described in Chapter 8, Interrupts.
The addressed slave’s software then clears the SM2 bit in the SCON register and prepares to re-
ceive the data bytes. The other slaves are unaffected by these data bytes because they are waiting
to respond to their own addresses.
10.5 AUTOMATIC ADDRESS RECOGNITION
The automatic address recognition feature is enabled when the multiprocessor communication
feature is enabled (i.e., the SM2 bit is set in the SCON register).
10-7
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Implemented in hardware, automatic address recognition enhances the multiprocessor communi-
cation feature by allowing the serial port to examine the address of each incoming command
frame. Only when the serial port recognizes its own address does the receiver set the RI bit in the
SCON register to generate an interrupt. This ensures that the CPU is not interrupted by command
frames addressed to other devices.
If desired, you may enable the automatic address recognition feature in mode 1. In this configu-
ration, the stop bit takes the place of the ninth data bit. The RI bit is set only when the received
command frame address matches the device’s address and is terminated by a valid stop bit.
NOTE
The multiprocessor communication and automatic address recognition features
cannot be enabled in mode 0 (i.e., setting the SM2 bit in the SCON register in
mode 0 has no effect).
To support automatic address recognition, a device is identified by a given address and a broad-
cast address.
10.5.1 Given Address
Each device has an individual address that is specified in the SADDR register; the SADEN reg-
ister is a mask byte that contains don't-care bits (defined by zeros) to form the device’s given ad-
dress. These don't-care bits provide the flexibility to address one or more slaves at a time. The
following example illustrates how a given address is formed. Note that to address a device by its
individual address, the SADEN mask byte must be 1111 1111.
SADDR
SADEN
Given
=
=
=
0101 0110
1111 1100
0101 01XX
The following is an example of how to use given addresses to address different slaves:
Slave A:
SADDR
SADEN
Given
=
=
=
1111 0001
1111 1010
1111 0X0X
Slave C:
SADDR
SADEN
Given
=
=
=
1111 0010
1111 1101
1111 00X1
Slave B:
SADDR
SADEN
Given
=
=
=
1111 0011
1111 1001
1111 0XX1
10-8
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SERIAL I/O PORT
The SADEN byte is selected so that each slave may be addressed separately. For Slave A, bit 0
(the LSB) is a don't-care bit; for Slaves B and C, bit 0 is a 1. To communicate with Slave A only,
the master must send an address where bit 0 is clear (e.g., 1111 0000).
For Slave A, bit 1 is a 0; for Slaves B and C, bit 1 is a don’t-care bit. To communicate with Slaves
B and C, but not Slave A, the master must send an address with bits 0 and 1 both set (e.g.,
1111 0011).
For Slaves A and B, bit 2 is a don’t-care bit; for Slave C, bit 2 is a 0. To communicate with Slaves
A and B, but not Slave C, the master must send an address with bit 0 set, bit 1 clear, and bit 2 set
(e.g., 1111 0101).
To communicate with Slaves A, B, and C, the master must send an address with bit 0 set, bit 1
clear, and bit 2 clear (e.g., 1111 0001).
10.5.2 Broadcast Address
A broadcast address is formed from the logical OR of the SADDR and SADEN registers with
zeros defined as don't-care bits, e.g.:
SADDR
=
=
=
0101 0110
1111 1100
1111 111X
SADEN
(SADDR) OR (SADEN)
The use of don't-care bits provides flexibility in defining the broadcast address, however, in most
applications, a broadcast address is 0FFH.
The following is an example of using broadcast addresses:
Slave A:
Slave B:
SADDR
SADEN
=
=
=
1111 0001
1111 1010
1111 1X11
Slave C:
SADDR
SADEN
=
=
=
1111 0010
1111 1101
1111 1111
Broadcast
Broadcast
SADDR
SADEN
=
=
=
1111 0011
1111 1001
1111 1X11
Broadcast
For Slaves A and B, bit 2 is a don’t-care bit; for Slave C, bit 2 is set. To communicate with all of
the slaves, the master must send an address FFH.
To communicate with Slaves A and B, but not Slave C, the master can send an address FBH.
10-9
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10.5.3 Reset Addresses
On reset, the SADDR and SADEN registers are initialized to 00H, i.e., the given and broadcast
addresses are XXXX XXXX (all don't-care bits). This ensures that the serial port is backwards-
compatible with MCS® 51 microcontrollers that do not support automatic address recognition.
10.6 BAUD RATES
You must select the baud rate for the serial port transmitter and receiver when operating in modes
1, 2, and 3. (The baud rate is preset for mode 0.) In its asynchronous modes, the serial port can
transmit and receive simultaneously. Depending on the mode, the transmission and reception
rates can be the same or different. Table 10-3 summarizes the baud rates that can be used for the
four serial I/O modes.
Table 10-3. Summary of Baud Rates
No. of
Send and Receive Send and Receive
Mode
Baud Rates at the Same Rate at Different Rates
0
1
2
3
1
N/A
Yes
Yes
Yes
N/A
Yes
?
Many †
2
Many †
Yes
†
Baud rates are determined by overflow of timer 1 and/or timer 2.
10.6.1 Baud Rate for Mode 0
The baud rate for mode 0 is fixed at FOSC/12.
10.6.2 Baud Rates for Mode 2
Mode 2 has two baud rates, which are selected by the SMOD1 bit in the PCON register (Figure
12-1 on page 12-2). The following expression defines the baud rate:
FOSC
Serial I/O Mode 2 Baud Rate = 2SMOD1
×
-------------
64
10.6.3 Baud Rates for Modes 1 and 3
In modes 1 and 3, the baud rate is generated by overflow of timer 1 (default) and/or timer 2. You
may select either or both timer(s) to generate the baud rate(s) for the transmitter and/or the receiv-
er.
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SERIAL I/O PORT
10.6.3.1
Timer 1 Generated Baud Rates (Modes 1 and 3)
Timer 1 is the default baud rate generator for the transmitter and the receiver in modes 1 and 3.
The baud rate is determined by the timer 1 overflow rate and the value of SMOD, as shown in the
following formula:
Timer 1 Overflow Rate
Serial I/O Modes 1 and 3 Baud Rate = 2SMOD1
×
-----------------------------------------------------------
32
10.6.3.2
Selecting Timer 1 as the Baud Rate Generator
To select timer 1 as the baud rate generator:
• Disable the timer interrupt by clearing the ETI bit in the IE0 register (Figure 6-2 on page
6-6).
• Configure timer 1 as a timer or an event counter (set or clear the C/T# bit in the TMOD
register, Figure 8-5 on page 8-7).
• Select timer mode 0–3 by programming the M1, M0 bits in the TMOD register.
In most applications, timer 1 is configured as a timer in auto-reload mode (high nibble of TMOD
= 0010B). The resulting baud rate is defined by the following expression:
FOSC
Serial I/O Modes 1 and 3 Baud Rate = 2SMOD1 × -----------------------------------------------------------------
32 ×12 ×[256 – (TH1) ]
• Enable the timer 1 interrupt by setting the ET1 bit in the IE register.
• Configure timer 1 to run as a 16-bit timer (high nibble of TMOD = 0001B).
• Use the timer 1 interrupt to initiate a 16-bit software reload.
Table 10-4 lists commonly used baud rates and shows how they are generated by timer 1.
10-11
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Table 10-4. Timer 1 Generated Baud Rates for Serial I/O Modes 1 and 3
Timer 1
Oscillator
Baud
Frequency
SMOD1
Rate
Reload
Value
(F
)
C/T# Mode
OSC
62.5 Kbaud (Max)
19.2 Kbaud
9.6 Kbaud
12.0 MHz
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
2
2
2
2
2
2
2
2
1
FFH
FDH
FDH
FAH
11.059 MHz
11.059 MHz
11.059 MHz
11.059 MHz
11.059 MHz
11.986 MHz
6.0 MHz
4.8 Kbaud
2.4 Kbaud
F4H
1.2 Kbaud
E8H
137.5 Baud
110.0 Baud
110.0 Baud
1DH
72H
12.0 MHz
FEEBH
10.6.3.3
Timer 2 Generated Baud Rates (Modes 1 and 3)
Timer 2 may be selected as the baud rate generator for the transmitter and/or receiver (Figure
10-5). The timer 2 baud rate generator mode is similar to the auto-reload mode. A rollover in the
TH2 register reloads registers TH2 and TL2 with the 16-bit value in registers RCAP2H and
RCAP2L, which are preset by software.
The timer 2 baud rate is expressed by the following formula:
Timer 2 Overflow Rate
Serial I/O Modes 1 and 3 Baud Rate = -----------------------------------------------------------
16
10.6.3.4
Selecting Timer 2 as the Baud Rate Generator
To select timer 2 as the baud rate generator for the transmitter and/or receiver, program the
RCLCK and TCLCK bits in the T2CON register as shown in Table 10-5. (You may select differ-
ent baud rates for the transmitter and receiver.) Setting RCLK and/or TCLK puts timer 2 into its
baud rate generator mode (Figure 10-5). In this mode, a rollover in the TH2 register does not set
the TF2 bit in the T2CON register. Also, a high-to-low transition at the T2EX pin sets the EXF2
bit in the T2CON register but does not cause a reload from (RCAP2H, RCAP2L) to (TH2, TL2).
You can use the T2EX pin as an additional external interrupt by setting the EXEN2 bit in T2CON.
NOTE
Turn the timer off (clear the TR2 bit in the T2CON register) before accessing
registers TH2, TL2, RCAP2H, and RCAP2L.
10-12
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SERIAL I/O PORT
You may configure timer 2 as a timer or a counter. In most applications, it is configured for timer
operation (i.e., the C/T2# bit is clear in the T2CON register).
Table 10-5. Selecting the Baud Rate Generator(s)
RCLCK TCLCK
Receiver
Transmitter
Bit
Bit
Baud Rate Generator Baud Rate Generator
0
0
1
1
0
1
0
1
Timer 1
Timer 1
Timer 2
Timer 2
Timer 1
Timer 2
Timer 1
Timer 2
Note:
Oscillator frequency
is divided by 2, not 12.
2
0
1
Timer 1
Overflow
SMOD1
XTAL1
T2
2
0
TH2
TL2
1
0
RX
Clock
(8 Bits) (8 Bits)
1
16
16
TR2
RCLCK
C/T2#
1
0
TX
Clock
RCAP2H RCAP2L
EXF2
TCLCK
Interrupt
Request
T2EX
EXEN2
Note availability of additional external interrupt.
A4120-01
Figure 10-5. Timer 2 in Baud Rate Generator Mode
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Note that timer 2 increments every state time (2TOSC) when it is in the baud rate generator mode.
In the baud rate formula that follows, “RCAP2H, RCAP2L” denotes the contents of RCAP2H
and RCAP2L taken as a 16-bit unsigned integer:
FOSC
Serial I/O Modes 1 and 3 Baud Rates = ------------------------------------------------------------------------------------------------------
32 ×[65536 – (RCAP2H, RCAP2L) ]
NOTE
not read or write the TH2 or TL2 registers. The timer is being incremented
every state time, and the results of a read or write may not be accurate. In
addition, you may read, but not write to, the RCAP2 registers; a write may
overlap a reload and cause write and/or reload errors.
Table 10-6 lists commonly used baud rates and shows how they are generated by timer 2.
Table 10-6. Timer 2 Generated Baud Rates
Oscillator
Baud Rate
Frequency
(F
RCAP2H RCAP2L
)
OSC
375.0 Kbaud
9.6 Kbaud
4.8 Kbaud
2.4 Kbaud
1.2 Kbaud
300.0 baud
110.0 baud
300.0 baud
110.0 baud
12 MHz
12 MHz
12 MHz
12 MHz
12 MHz
12 MHz
12 MHz
6 MHz
FFH
FFH
FFH
FFH
FEH
FBH
F2H
FDH
F9H
FFH
D9H
B2H
64H
C8H
1EH
AFH
8FH
57H
6 MHz
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11
Minimum Hardware
Setup
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CHAPTER 11
MINIMUM HARDWARE SETUP
scribes a minimum hardware setup. Topics covered include power, ground, clock source, and de-
11.1 MINIMUM HARDWARE SETUP
Figure 11-1 shows a minimum hardware setup that employs the on-chip oscillator for the system
clock and provides power-on reset. Control signals and Ports 0, 1, 2, and 3 are not shown. See
sections 11.3, “Clock Sources” and 11.4.4, “Power-on Reset.”
VCC
8XC251Sx
VCC
VCC2
+
1µF
XTAL1
RST
C1
C2
XTAL2
VSS
VSS1
VSS2
Note:
VCC2 is a secondary power pin that reduces power supply noise. VSS1 and VSS2 are
secondary ground pins that reduce ground bounce and improve power supply by-passing.
Connections to these pins are not required for proper device operation.
A4141-02
Figure 11-1. Minimum Setup
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11.2 ELECTRICAL ENVIRONMENT
The 8XC251Sx is a high-speed CHMOS device. To achieve satisfactory performance, its operat-
ing environment should accommodate the device signal waveforms without introducing distor-
tion or noise. Design considerations relating to device performance are discussed in this section.
See the device data sheet for voltage and current requirements, operating frequency, and wave-
form timing.
11.2.1 Power and Ground Pins
Power the 8XC251Sx from a well-regulated power supply designed for high-speed digital loads.
Use short, low impedance connections to the power (VCC and VCC2) and ground (VSS, VSS1, and
V
SS2) pins.
VCC2 is a secondary power pin that reduces power supply noise. VSS1 and VSS2 are secondary
ground pins that reduce ground bounce and improve power supply bypassing. The secondary
power and ground pins are not substitutes for VCC and VSS. They are not required for proper de-
vice operation; thus, the 8XC251Sx is compatible with designs that do not provide connections
to these pins.
11.2.2 Unused Pins
To provide stable, predictable performance, connect unused input pins to VSS or VCC. Untermi-
nated input pins can float to a mid-voltage level and draw excessive current. Unterminated inter-
rupt inputs may generate spurious interrupts.
11.2.3 Noise Considerations
The fast rise and fall times of high-speed CHMOS logic may produce noise spikes on the power
supply lines and signal outputs. To minimize noise and waveform distortion follow good board
layout techniques. Use sufficient decoupling capacitors and transient absorbers to keep noise
within acceptable limits. Connect 0.01 µF bypass capacitors between VCC and each VSS pin. Place
the capacitors close to the device to minimize path lengths.
Multilayer printed circuit boards with separate VCC and ground planes help minimize noise. For
additional information on noise reduction, see Application Note AP-125, “Designing Microcon-
troller Systems for Electrically Noisy Environments.”
11-2
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MINIMUM HARDWARE SETUP
11.3 CLOCK SOURCES
The 8XC251Sx can obtain the system clock signal from an external clock source (Figure 11-3) or
resonator (Figure 11-2).
11.3.1 On-chip Oscillator (Crystal)
This clock source uses an external quartz crystal connected from XTAL1 to XTAL2 as the fre-
quency-determining element (Figure 11-2). The crystal operates in its fundamental mode as an
inductive reactance in parallel resonance with capacitance external to the crystal. Oscillator de-
sign considerations include crystal specifications, operating temperature range, and parasitic
board capacitance. Consult the crystal manufacturer’s data sheet for parameter values. With high
quality components, C1 = C2 = 30 pF is adequate for this application.
Pins XTAL1 and XTAL2 are protected by on-chip electrostatic discharge (ESD) devices, D1 and
D2, which are diodes parasitic to the RF FETs. They serve as clamps to VCC and VSS. Feedback
resistor RF in the inverter circuit, formed from paralleled n- and p- channel FETs, permits the PD
bit in the PCON register (Figure 12-1 on page 12-2) to disable the clock during powerdown.
Noise spikes at XTAL1 and XTAL2 can disrupt microcontroller timing. To minimize coupling
between other digital circuits and the oscillator, locate the crystal and the capacitors near the chip
and connect to XTAL1, XTAL2, and VSS with short, direct traces. To further reduce the effects of
noise, place guard rings around the oscillator circuitry and ground the metal crystal case.
To Internal
x
Timing Circuit
VCC
Quartz Crystal
or Ceramic Resonator
PD#
D1
D2
XTAL1
XTAL2
C1
C2
RF
A4143-02
Figure 11-2. CHMOS On-chip Oscillator
11-3
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For a more in-depth discussion of crystal specifications, ceramic resonators, and the selection of
C1 and C2 see Applications Note AP-155, “Oscillators for Microcontrollers,” in the Embedded
Applications handbook.
11.3.2 On-chip Oscillator (Ceramic Resonator)
In cost-sensitive applications, you may choose a ceramic resonator instead of a crystal. Ceramic
Consult the manufacturer’s data sheet for specific information.
11.3.3 External Clock
To operate the CHMOS 8XC251Sx from an external clock, connect the clock source to the
XTAL1 pin as shown in Figure 11-3. Leave the XTAL2 pin floating. The external clock driver
can be a CMOS gate. If the clock driver is a TTL device, its output must be connected to VCC
through a 4.7 kΩ pullup resistor.
External
XTAL1
Clock
CMOS
Clock Driver
N/C
XTAL2
VSS
Note: If TTL clock driver is used, connect a 4.7kΩ pullup resistor from driver output to VCC.
A4142-03
Figure 11-3. External Clock Connection
11-4
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For external clock drive requirements, see the device data sheet. Figure 11-4 shows the clock
drive waveform. The external clock source must meet the minimum high and low times (TCHCX
and TCLCX) and the maximum rise and fall times (TCLCH and TCHCL) to minimize the effect of ex-
ternal noise on the clock generator circuit. Long rise and fall times increase the chance that ex-
ternal noise will affect the clock circuitry and cause unreliable operation.
The external clock driver may encounter increased capacitance loading at XTAL1 due to the
interaction between the internal amplifier and its feedback capacitance (i.e., the Miller effect) at
power-on. Once the input waveform requirements are met, the input capacitance remains under
20 pF.
TCLCH
TCHCX
VCC – 0.5
0.7 VCC
TCLCX
0.2 VCC – 0.1
0.45 V
TCHCL
TCLCL
A4119-01
Figure 11-4. External Clock Drive Waveforms
11.4 RESET
A device reset initializes the 8XC251Sx and vectors the CPU to address FF:0000H. A reset is re-
quired after applying power at turn-on. A reset is a means of exiting the idle and powerdown
modes or recovering from software malfunctions.
To achieve a valid reset, VCC must be within its normal operating range (see device data sheet)
and the reset signal must be maintained for 64 clock cycles (64TOSC) after the oscillator has sta-
bilized.
Device reset is initiated in two ways:
• externally, by asserting the RST pin
• internally, if the hardware WDT or the PCA WDT expires
11-5
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The power off flag (POF) in the PCON register indicates whether a reset is a warm start or a cold
start. A cold start reset (POF = 1) is a reset that occurs after power has been off or VCC has fallen
below 3 V, so the contents of volatile memory are indeterminate. POF is set by hardware when
VCC rises from less than 3V to its normal operating level. See section 12.2.2, “Power Off Flag.”
A warm start reset (POF = 0) is a reset that occurs while the chip is at operating voltage, for ex-
ample, a reset initiated by a WDT overflow or an external reset used to terminate the idle or pow-
erdown modes.
11.4.1 Externally Initiated Resets
To reset the 8XC251Sx, hold the RST pin at a logic high for at least 64 clock cycles (64TOSC
)
while the oscillator is running. Reset can be accomplished automatically at the time power is ap-
plied by capacitively coupling RST to VCC (see Figure 11-1 and section 11.4.4, “Power-on Re-
set”). The RST pin has a Schmitt trigger input and a pulldown resistor.
11.4.2 WDT Initiated Resets
Expiration of the hardware WDT (overflow) or the PCA WDT (comparison match) generates a
reset signal. WDT initiated resets have the same effect as an external reset. See section 8.7,
“Watchdog Timer,” and section 9.3.5, “PCA Watchdog Timer Mode.”
11.4.3 Reset Operation
When a reset is initiated, whether externally or by a WDT, the port pins are immediately forced
to their reset condition as a fail-safe precaution, whether the clock is running or not.
The external reset signal and the WDT initiated reset signals are combined internally. For an ex-
ternal reset the voltage on the RST pin must be held high for 64TOSC. For WDT initiated resets, a
5-bit counter in the reset logic maintains the signal for the required 64TOSC
.
The CPU checks for the presence of the combined reset signal every 2TOSC. When a reset is de-
tected, the CPU responds by triggering the internal reset routine. The reset routine loads the SFRs
with their reset values (see Table 3-5 on page 3-17). Reset does not affect on-chip data RAM or
the register file. However, following a cold start reset, these are indeterminate because VCC has
fallen too low or has been off. Following a synchronizing operation and the configuration fetch,
the CPU vectors to address FF:0000. Figure 11-5 shows the reset timing sequence.
11-6
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While the RST pin is high ALE, PSEN#, and the port pins are weakly pulled high. The first ALE
occurs 32TOSC after the reset signal goes low. For this reason, other devices can not be synchro-
nized to the internal timings of the 8XC251Sx.
NOTE
Externally driving the ALE and/or PSEN# pins to 0 during the reset routine
may cause the device to go into an indeterminate state.
Powering up the 8XC251Sx without a reset may improperly initialize the
undetermined memory location.
11.4.4 Power-on Reset
To automatically generate a reset at power-on, connect the RST pin to the VCC pin through a 1-µF
capacitor as shown in Figure 11-1.
When VCC is applied, the RST pin rises to VCC, then decays exponentially as the capacitor charg-
es. The time constant must be such that RST remains high (above the turn-off threshold of the
Schmitt trigger) long enough for the oscillator to start and stabilize, plus 64TOSC. At power-on,
VCC should rise within approximately 10 ms. Oscillator start-up time is a function the crystal fre-
quency; typical start-up times are 1 ms for a 10 MHz crystal and 10 ms for a 1 Mhz crystal.
During power-on, the port pins are in a random state until forced to their reset state by the asyn-
chronous logic.
Reducing VCC quickly to 0 causes the RST pin voltage to momentarily fall below 0 V. This volt-
age is internally limited and does not harm the device.
11-7
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12
Special Operating
Modes
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CHAPTER 12
SPECIAL OPERATING MODES
This chapter describes the power control (PCON) register and three special operating modes: idle,
powerdown, and on-circuit emulation (ONCE).
12.1 GENERAL
The idle and powerdown modes are power reduction modes for use in applications where power
consumption is a concern. User instructions activate these modes by setting bits in the PCON reg-
ister. Program execution halts, but resumes when the mode is exited by an interrupt. While in idle
ONCE is a test mode that electrically isolates the 8XC251Sx from the system in which it operates.
12.2 POWER CONTROL REGISTER
The PCON special function register (Figure 12-1) provides two control bits for the serial I/O
purpose flags.
12.2.1 Serial I/O Control Bits
The SMOD1 bit in the PCON register is a factor in determining the serial I/O baud rate. See Fig-
ure 12-1 and section 10.6, “Baud Rates.”
The SMOD0 bit in the PCON register determines whether bit 7 of the SCON register provides
read/write access to the framing error (FE) bit (SMOD0 = 1) or to SM0, a serial I/O mode select
bit (SMOD0 = 0). See Figure 12-1 (PCON) and Figure 10-2 on page 10-3 (SCON).
12.2.2 Power Off Flag
Hardware sets the Power Off Flag (POF) in PCON when VCC rises from < 3 V to > 3 V to indicate
that on-chip volatile memory is indeterminate (e.g., at power-on). The POF can be set or cleared
by software. After a reset, check the status of this bit to determine whether a cold start reset or a
warm start reset occurred (see section 11.4, “Reset”). After a cold start, user software should clear
the POF. If POF = 1 is detected at other times, do a reset to reinitialize the chip, since for VCC
3 V data may have been lost or some logic may have malfunctioned.
<
12-1
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Address:
Reset State:
S:87H
00XX 0000B
PCON
7
0
SMOD1
SMOD0
—
POF
GF1
GF0
PD
IDL
Bit
Number
Bit
Mnemonic
Function
7
SMOD1
Double Baud Rate Bit:
When set, doubles the baud rate when timer 1 is used and mode 1, 2, or
3 is selected in the SCON register. See section 10.6, “Baud Rates.”
6
SMOD0
SCON.7 Select:
When set, read/write accesses to SCON.7 are to the FE bit.
When clear, read/write accesses to SCON.7 are to the SM0 bit.
See Figure 10-2 on page 10-3 (SCON).
5
4
—
Reserved:
The value read from this bit is indeterminate. Write a zero to this bit.
POF
Power Off Flag:
Set by hardware as V rises above 3 V to indicate that power has been
CC
off or V had fallen below 3 V and that on-chip volatile memory is
CC
indeterminate. Set or cleared by software.
3
2
1
0
GF1
GF0
PD
General Purpose Flag:
Set or cleared by software. One use is to indicate whether an interrupt
occurred during normal operation or during idle mode.
General Purpose Flag:
Set or cleared by software. One use is to indicate whether an interrupt
occurred during normal operation or during idle mode.
Powerdown Mode Bit:
When set, activates powerdown mode.
Cleared by hardware when an interrupt or reset occurs.
IDL
Idle Mode Bit:
When set, activates idle mode.
Cleared by hardware when an interrupt or reset occurs.
If IDL and PD are both set, PD takes precedence.
Figure 12-1. Power Control (PCON) Register
12-2
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SPECIAL OPERATING MODES
Table 12-1. Pin Conditions in Various Modes
Program
Memory
ALE
Pin
PSEN#
Pin
Port 0
Pins
Port 1
Pins
Port 2
Pins
Port 3
Pins
Mode
Reset
Don’t Care
Internal
Weak High Weak High Floating
Weak High Weak High Weak High
Idle
Idle
1
1
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
External
1
1
Floating
Data
Powerdown Internal
Powerdown External
0
0
0
0
Floating
Floating
ONCE
Don’t Care
Floating
Floating
Weak High Weak High Weak High
XTAL1
Interrupt,
Clock
Serial Port,
Gen
C1
C2
Timer Block
OSC
XTAL2
CPU
PD#
IDL#
A4160-01
Figure 12-2. Idle and Powerdown Clock Control
12-3
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12.3 IDLE MODE
Idle mode is a power reduction mode that reduces power consumption to about 40% of normal.
while the peripherals continue to be clocked (Figure 12-2). The CPU status before entering idle
mode is preserved; i.e., the program counter, program status word register, and register file retain
status of the port pins depends upon the location of the program memory.
• Internal program memory: the ALE and PSEN# pins are pulled high and the ports 0, 1, 2,
and 3 pins are reading data (Table 12-1).
• External program memory: the ALE and PSEN# pins are pulled high; the port 0 pins are
floating; and the pins of ports 1, 2, and 3 are reading data (Table 12-1).
NOTE
If desired, the PCA may be instructed to pause during idle mode by setting the
CIDL bit in the CMOD register (Figure 9-7 on page 9-13).
12.3.1 Entering Idle Mode
To enter idle mode, set the PCON register IDL bit. The 8XC251Sx enters idle mode upon execu-
tion of the instruction that sets the IDL bit. The instruction that sets the IDL bit is the last instruc-
tion executed.
CAUTION
If the IDL bit and the PD bit are set simultaneously, the 8XC251Sx enters
powerdown mode.
12-4
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SPECIAL OPERATING MODES
12.3.2 Exiting Idle Mode
There are two ways to exit idle mode:
• Generate an enabled interrupt. Hardware clears the PCON register IDL bit which restores
the clocks to the CPU. Execution resumes with the interrupt service routine. Upon
completion of the interrupt service routine, program execution resumes with the instruction
immediately following the instruction that activated idle mode. The general purpose flags
(GF1 and GF0 in the PCON register) may be used to indicate whether an interrupt occurred
during normal operation or during idle mode. When idle mode is exited by an interrupt, the
interrupt service routine may examine GF1 and GF0.
• Reset the chip. See section 11.4, “Reset.” A logic high on the RST pin clears the IDL bit in
the PCON register directly and asynchronously. This restores the clocks to the CPU.
Program execution momentarily resumes with the instruction immediately following the
instruction that activated the idle mode and may continue for a number of clock cycles
before the internal reset algorithm takes control. Reset initializes the 8XC251Sx and vectors
the CPU to address FF:0000H.
NOTE
During the time that execution resumes, the internal RAM cannot be accessed;
however, it is possible for the port pins to be accessed. To avoid unexpected
outputs at the port pins, the instruction immediately following the instruction
that activated idle mode should not write to a port pin or to the external RAM.
12.4 POWERDOWN MODE
The powerdown mode places the 8XC251Sx in a very low power state. Powerdown mode stops
ing powerdown mode is preserved, i.e., the program counter, program status word register, and
register file retain their data for the duration of powerdown mode. In addition, the SFRs and RAM
contents are preserved. The status of the port pins depends on the location of the program mem-
ory:
• Internal program memory: the ALE and PSEN# pins are pulled low and the ports 0, 1, 2,
and 3 pins are reading data (Table 12-1).
• External program memory: the ALE and PSEN# pins are pulled low; the port 0 pins are
floating; and the pins of ports 1, 2, and 3 are reading data (Table 12-1).
NOTE
Vcc may be reduced to as low as 2 V during powerdown to further reduce
power dissipation. Take care, however, that Vcc is not reduced until power-
down is invoked.
12-5
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12.4.1 Entering Powerdown Mode
To enter powerdown mode, set the PCON register PD bit. The 8XC251Sx enters the power-down
mode upon execution of the instruction that sets the PD bit. The instruction that sets the PD bit is
the last instruction executed.
12.4.2 Exiting Powerdown Mode
CAUTION
If VCC was reduced during the powerdown mode, do not exit powerdown until
V
CC is restored to the normal operating level.
There are two ways to exit the powerdown mode:
• Generate an enabled external interrupt. Hardware clears the PD bit in the PCON register
which starts the oscillator and restores the clocks to the CPU and peripherals. Execution
resumes with the interrupt service routine. Upon completion of the interrupt service routine,
program execution resumes with the instruction immediately following the instruction that
activated powerdown mode.
NOTE
To enable an external interrupt, set the IE register EX0 and/or EX1 bit[s]. The
external interrupt used to exit powerdown mode must be configured as level
sensitive and must be assigned the highest priority. In addition, the duration of
the interrupt must be of sufficient length to allow the oscillator to stabilize.
• Generate a reset. See section 11.4, “Reset.” A logic high on the RST pin clears the PD bit in
the PCON register directly and asynchronously. This starts the oscillator and restores the
clocks to the CPU and peripherals. Program execution momentarily resumes with the
instruction immediately following the instruction that activated powerdown and may
continue for a number of clock cycles before the internal reset algorithm takes control.
Reset initializes the 8XC251Sx and vectors the CPU to address FF:0000H.
NOTE
During the time that execution resumes, the internal RAM cannot be accessed;
however, it is possible for the port pins to be accessed. To avoid unexpected
outputs at the port pins, the instruction immediately following the instruction
that activated the powerdown mode should not write to a port pin or to the
external RAM.
12-6
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SPECIAL OPERATING MODES
12.5 ON-CIRCUIT EMULATION (ONCE) MODE
The on-circuit emulation (ONCE) mode permits external testers to test and debug 8XC251Sx-
based systems without removing the chip from the circuit board. A clamp-on emulator or test
CPU is used in place of the 8XC251Sx which is electrically isolated from the system.
12.5.1 Entering ONCE Mode
To enter the ONCE mode:
1. Assert RST to initiate a device reset. See section 11.4.1, “Externally Initiated Resets,” and
the reset waveforms in Figure 11-5 on page 11-8.
2. While holding RST asserted, apply and hold logic levels to I/O pins as follows: PSEN# =
low, P0.7:5 = low, P0.4 = high, P0.3:0 = low (i.e., port 0 = 10H).
3. Deassert RST, then remove the logic levels from PSEN# and port 0.
These actions cause the 8XC251Sx to enter the ONCE mode. Port 1, 2, and 3 pins are weakly
pulled high and port 0, ALE, and PSEN# pins are floating (Table 12-1). Thus the device is elec-
trically isolated from the remainder of the system which can then be tested by an emulator or test
CPU. Note that in the ONCE mode the device oscillator remains active.
12.5.2 Exiting ONCE Mode
To exit ONCE mode, reset the device.
12-7
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13
External Memory
Interface
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CHAPTER 13
EXTERNAL MEMORY INTERFACE
13.1 OVERVIEW
The external memory interface comprises the external bus (ports 0 and 2, and when enabled also
includes port 1.7:6) as well as the bus control signals (RD#, WR#, PSEN# and ALE). Chip con-
figuration bytes (see Chapter 4, “Device Configuration”) determine several interface options:
page mode or nonpage mode for external code fetches; the number of external address bits (16,
17, or 18); the address ranges for RD#, WR#, and PSEN#; and the number of preprogrammed
external wait states to extend RD#, WR#, PSEN# or ALE. Real-time wait states can be enabled
with special function register WCON.1:0. You can use these options to tailor the interface to your
The external memory interface operates in either page mode or nonpage mode. Page mode pro-
vides increased performance by reducing the time for external code fetches. Page mode does not
eration in page mode or nonpage mode according to bit 1 of configuration byte UCONFIG0. Fig-
ure 13-1 shows the structure of the external address bus for page and nonpage mode operation.
P0 carries address A7:0 while P2 carries address A15:8. Data D7:0 is multiplexed with A7:0 on
P0 in nonpage mode and with A15:8 on P2 in page mode.
Table 13-1 describes the external memory interface signals. The address and data signals (AD7:0
on port 0 and A15:8 on port 2) are defined for nonpage mode.
RAM/
EPROM/
Flash
RAM/
EPROM/
Flash
8XC251SA
8XC251SB
8XC251SP
8XC251SQ
8XC251SA
8XC251SB
8XC251SP
8XC251SQ
D7:0
A15:8
A7:0
A15:8
P2
A15:8
AD7:0
A7:0
P2
P0
Latch
P0
Latch
A7:0
D7:0
A15:8/D7:0
A7:0
A15.8
Nonpage Mode
Page Mode
A4159-02
Figure 13-1. Bus Structure in Nonpage Mode and Page Mode
13-1
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Table 13-1. External Memory Interface Signals
Signal
Name
Alternate
Function
Type
Description
A17
O
O
Address Line 17.
Address Line 16. See RD#.
P1.7/CEX4/WCLK
P3.7/RD#
A16
A15:8†
AD7:0†
O
Address Lines. Upper address for external bus (non-page mode). P2.7:0
I/O
Address/Data Lines. Multiplexed lower address and data for the
P0.7:0
external bus (non-page mode).
ALE
EA#
O
I
Address Latch Enable. ALE signals the start of an external bus
cycle and indicates that valid address information is available on
lines A15:8 and AD7:0.
PROG#
External Access. For EA# strapped to ground, all program
memory accesses are off-chip. For EA# = strapped to VCC, an
access is to on-chip OTPROM/ROM if the address is within the
range of the on-chip OTPROM/ROM; otherwise the access is off-
chip. The value of EA# is latched at reset. For a ROMless device,
strap EA# to ground.
VPP
PSEN#
O
O
I
Program Store Enable. Read signal output. This output is
asserted for a memory address range that depends on bits RD0
and RD1 in the configuration byte (see also RD#):
—
RD1 RD0 Address Range for Assertion
0
0
1
1
0
1
0
1
All addresses
All addresses
All addresses
All addresses ≥ 80:0000H
RD#
Read or 17th Address Bit (A16). Read signal output to external
data memory or 17th external address bit (A16), depending on the
values of bits RD0 and RD1 in configuration byte. (See PSEN#):
P3.7/A16
RD1 RD0 Function
0
0
1
1
0
1
0
1
The pin functions as A16 only.
The pin functions as A16 only.
The pin functions as P3.7 only.
RD# asserted for reads at all addresses ≤7F:FFFFH.
WAIT#
WCLK
Real-time Wait State Input. The real-time WAIT # input is
enabled by writing a logical ‘1’ to the WCON.0 (RTWE) bit at
S:A7H. During bus cycles, the external memory system can signal
‘system ready’ to the microcontroller in real time by controlling the
WAIT# input signal on the port 1.6 input.
P1.6/CEX3
O
O
Wait Clock Output. The real-time WCLK output is driven at port
1.7 (WCLK) by writing a logical ‘1’ to the WCON.1 (RTWCE) bit at
S:A7H. When enabled, the WCLK output produces a square wave
signal with a period of one-half the oscillator frequency.
A17/P1.7/CEX4
WR#
Write. Write signal output to external memory. WR# is asserted for P3.6
writes to all valid memory locations.
†
If the chip is configured for page-mode operation, port 0 carries the lower address bits (A7:0), and port 2
carries the upper address bits (A15:8) and the data (D7:0).
13-2
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EXTERNAL MEMORY INTERFACE
13.2 EXTERNAL BUS CYCLES
The section describes the bus cycles the 8XC251Sx executes to fetch code, read data, and write
data in external memory. Both page mode and nonpage mode are described and illustrated. For
simplicity, the accompanying figures depict the bus cycle waveforms in idealized form and do not
provide precise timing information. This section does not cover wait states (see section 13.4, “Ex-
ternal Bus Cycles with Configurable Wait States”) or configuration byte bus cycles (see section
13.6, “Configuration Byte Bus Cycles”). For bus cycle timing parameters refer to the datasheet.
An “inactive external bus” exists when the 8XC251Sx is not executing external bus cycles. This
occurs under any of the three following conditions:
• Bus Idle (The chip is in normal operating mode but no external bus cycles are executing)
• The chip is in powerdown mode
13.2.1 Bus Cycle Definitions
Table 13-2 lists the types of external bus cycles. It also shows the activity on the bus for nonpage
mode and page mode bus cycles with no wait states. There are three types of nonpage mode bus
cycles: code read, data read, and data write. There are four types of page mode bus cycles: code
fetch (page miss), code read (page hit), data read, and data write. The data read and data write
cycles are the same for page mode and nonpage mode (except the multiplexing of D7:0 on ports
0 and 2).
Table 13-2. Bus Cycle Definitions (No Wait States)
Bus Activity
Mode
Bus Cycle
State 1
State 2
State 3
Code Read
ALE
ALE
ALE
RD#/PSEN#, code in
RD#/PSEN#
Nonpage
Mode
Data Read (2)
data in
Data Write (2)
WR#
WR# high, data out
Code Read, Page Miss
RD#/PSEN#, code in
Code Read, Page Hit (3) PSEN#, code in
Page
Mode
Data Read (2)
Data Write (2)
ALE
ALE
RD#/PSEN#
WR#
data in
WR# high, data out
NOTES:
1. Signal timing implied by this table is approximate (idealized).
2. Data read (page mode) = data read (nonpage mode) and write (page mode) = write (nonpage mode)
except that in page mode data appears on P2 (multiplexed with A15:0), whereas in nonpage mode
data appears on P0 (multiplexed with A7:0).
3. The initial code read page hit bus cycle can execute only following a code read page miss cycle.
13-3
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In nonpage mode, the external bus structure is the same as for MCS 51 microcontrollers. The up-
per address bits (A15:8) are on port 2, and the lower address bits (A7:0) are multiplexed with the
data (D7:0) on port 0. External code read bus cycles execute in approximately two state times.
See Table 13-2 and Figure 13-2. External data read bus cycles (Figure 13-3) and external write
bus cycles (Figure 13-4) execute in approximately three state times. For the write cycle (Figure
13-4), a third state is appended to provide recovery time for the bus. Note that the write signal
WR# is asserted for all memory regions, except for the case of RD1:0 = 11, where WR# is assert-
ed for regions 00:–01: but not for regions FE:–FF:.
State 1
State 2
XTAL
ALE
RD#/PSEN#
P0
A7:0
D7:0
A17/A16/P2
A17/A16/A15:8
A2807-04
Figure 13-2. External Code Fetch (Nonpage Mode)
State 1
State 2
State 3
XTAL
ALE
RD#/PSEN#
P0
A7:0
D7:0
A17/A16/P2
A17/A16/A15:8
A4230-01
Figure 13-3. External Data Read (Nonpage Mode)
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EXTERNAL MEMORY INTERFACE
State 1
State 2
State 3
XTAL
ALE
WR#
P0
A7:0
D7:0
A17/A16/P2
A17/A16/A15:8
A2808-03
13.2.3 Page Mode Bus Cycles
Page mode increases performance by reducing the time for external code fetches. Under certain
conditions the controller fetches an instruction from external memory in one state time instead of
two (Table 13-2). Page mode does not affect internal code fetches.
The first code fetch to a 256-byte “page” of memory always uses a two-state bus cycle. Subse-
quent successive code fetches to the same page (page hits) require only a one-state bus cycle.
When a subsequent fetch is to a different page (a page miss) it again requires a two-state bus cy-
cle. The following external code fetches are always page-miss cycles:
• the first external code fetch after a page rollover†
• the first external code fetch after powerdown or idle mode
• the first external code fetch after a branch, return, interrupt, etc.
In page mode, the 8XC251Sx bus structure differs from the bus structure in MCS 51 controllers
(Figure 13-1). The upper address bits A15:8 are multiplexed with the data D7:0 on port 2, and the
lower address bits (A7:0) are on port 0.
†
A page rollover occurs when the address increments from the top of one 256-byte page to the bottom of
the next (e.g., from FF:FAFFH to FF:FB00H).
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Figure 13-5 shows the two types of external bus cycles for code fetches in page mode. The page-
miss cycle is the same as a code fetch cycle in nonpage mode (except D7:0 is multiplexed with
ing cycle. Therefore, ALE is not asserted, and the values of A15:8 are retained in the address
latches. In a single state, the new values of A7:0 are placed on port 0, and memory places the in-
struction byte on port 2. Notice that a page hit reduces the available address access time by one
state. Therefore, faster memories may be required to support page mode.
Figure 13-6 and Figure 13-7 show the bus cycles for data reads and data writes in page mode.
These cycles are identical to those for nonpage mode, except for the different signals on ports 0
and 2.
Cycle 1, Page-Miss
State 1 State 2
Cycle 2, Page-Hit
State 1
XTAL
ALE
†
PSEN#
A17/A16/P0
A17/A16/A7:0
A17/A16/A7:0
A15:8
P2
D7:0
D7:0
†
During a sequence of page hits, PSEN# remains low until the end of the last page-hit cycle.
A2809-04
Figure 13-5. External Code Fetch (Page Mode)
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EXTERNAL MEMORY INTERFACE
State 1
State 2
State 3
XTAL
ALE
RD#/PSEN#
A17/A16/P0
A17/A16/A7:0
P2
A15:8
D7:0
A2811-04
Figure 13-6. External Data Read (Page Mode)
State 1
State 2
State 3
XTAL
ALE
WR#
A17/A16/P0
A17/A16/A7:0
P2
A15:8
D7:0
A2810-03
Figure 13-7. External Data Write (Page Mode)
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13.3 WAIT STATES
The 8XC251SA, SB, SP, SQ provides three types of wait state solutions to external memory prob-
lems: real-time, RD#/WR#/PSEN#, and ALE wait states. The 8XC251SA, SB, SP, SQ supports
traditional real-time wait state operations for dynamic bus control. Real-time wait state opera-
tions are controlled by means of the WCON special function register. See section 13.5, “External
Bus Cycles with Real-time Wait States.”
In addition, the 8XC251SA, SB, SP, SQ device can be configured at reset to add wait states to
external bus cycles by extending the ALE or RD#/WR#/PSEN# pulses. See section 4.5.3, “Wait
State Configuration Bits.”
You can configure the chip to use multiple types of wait states. Accesses to on-chip code and data
memory always use zero wait states. The following sections demonstrate wait state usage.
13.4 EXTERNAL BUS CYCLES WITH CONFIGURABLE WAIT STATES
Three types of wait state solutions are available; real-time, RD#/WR#/PSEN#, and ALE wait
states. The 8XC251SA, SB, SP, SQ supports traditional real-time wait state operations for dy-
namic bus control. The real-time wait state operations are enabled with the WCON SFR bits at
address S:0A7H. The device can also be configured to add wait states to the external bus cycles
by extending the bus timing of the RD#/WR#/PSEN# pulses or by extending the ALE pulse or
by adding 0, 1, 2, or 3 wait states to the RD#/WR#/PSEN# pulses.
The XALE# configuration bit specifies 0 or 1 wait state for ALE. The WSA1:0# and WSB1:0#
configuration bits specify the number of wait states for RD/WR/PSEN. See section 4.5.3, “Wait
each solution.
13.4.1 Extending RD#/WR#/PSEN#
Figure 13-8 shows the nonpage mode code fetch bus cycle with one RD#/PSEN# wait state. The
wait state extends the bus cycle to three states. Figure 13-9 shows the nonpage mode data write
bus cycle with one WR# wait state. The wait state extends the bus cycle to four states. The wave-
forms in Figure 13-9 also apply to the nonpage mode data read external bus cycle if RD#/PSEN#
is substituted for WR#.
13-8
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EXTERNAL MEMORY INTERFACE
State 1
State 2
State 3
XTAL
ALE
RD#/PSEN#
P0
A7:0
D7:0
A17/A16/P2
A17/A16/A15:8
A2812-04
Figure 13-8. External Code Fetch (Nonpage Mode, One RD#/PSEN# Wait State)
State 1
State 2
State 3
State 4
XTAL
ALE
WR#
P0
A7:0
D7:0
A17/A16/P2
A17/A16/A15:8
A4174-02
Figure 13-9. External Data Write (Nonpage Mode, One WR# Wait State)
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13.4.2 Extending ALE
Figure 13-10 shows the nonpage mode code fetch external bus cycle with ALE extended. The
wait state extends the bus cycle from two states to three. For read and write external bus cycles,
the extended ALE extends the bus cycle from three states to four.
State 1
State 2
State 3
XTAL
ALE
RD#/PSEN#
P0
A7:0
D7:0
A17/A16/P2
A15:8
A2813-04
Figure 13-10. External Code Fetch (Nonpage Mode, One ALE Wait State)
13.5 EXTERNAL BUS CYCLES WITH REAL-TIME WAIT STATES
In addition to fixed-length wait states such as RD#/WR#/PSEN# and ALE, the 8XC251SA, SB,
time wait state by means of registers.
There are two ways of using real-time wait states; the WAIT# pin used as an input bus control and
the WAIT# signal used in conjunction with the WCLK output signal. These two signals are en-
abled with the WCON special function register in the SFR space at S:0A7H. Refer to Figure
13-11.
13-10
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EXTERNAL MEMORY INTERFACE
Address:
Reset State: XXXX XX00B
S:A7H
WCON
7
0
—
—
—
—
—
—
RTWCE
RTWE
Bit
Bit
Function
Number Mnemonic
7:2
—
Reserved:
The values read from these bits are indeterminate. Write “0” to these
bits.
1
0
RTWCE
RTWE
Real-time WAIT CLOCK enable. Write a ‘1’ to this bit to enable the WAIT
CLOCK on port 1.7 (WCLK). The square wave output signal is one-half
the oscillator frequency.
Real-time WAIT# enable. Write a ‘1’ to this bit to enable real-time wait-
state input on port 1.6 (WAIT#).
Figure 13-11. Real-time Wait State Control Register (WCON)
NOTE
The WAIT# and WCLK signals are alternate functions for the port 1.6:7 input
and output buffers. Use of other alternate functions may conflict with wait
state operation.
When WAIT# is enabled, PCA module 3 is disabled and resumes operation
only when the WAIT# function is disabled. The same relationship exists
between WCLK and PCA module 4. It is not advisable to alternate between
PCA operations and real-time wait-state operations at port 1.6 (CEX3/WAIT#)
or port 1.7 (CEX4/WCLK).
Port 1.7 can also be enabled to drive address signal A17 in some memory
designs. The A17 address signal always takes priority over other alternate
functions (in this case, both PCA.4 and WCLK). Even if RTWCE is enabled in
WCON.1, the WCLK output does not appear during bus cycles enabled to
drive address A17. The use of WAIT# as an input on port 1.6 is unaffected by
address signals.
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13.5.1 Real-time WAIT# Enable (RTWE)
The real-time WAIT# input is enabled by writing a logical ‘1’ to the WCON.0 (RTWE) bit at
S:A7H. During bus cycles, the external memory system can signal “system ready” to the micro-
controller in real time by controlling the WAIT# input signal on the port 1.6 input. Sampling of
WAIT# is coincident with the activation of RD#/PSEN# or WR# signals driven low during a bus
cycle. A ‘not-ready’ condition is recognized by the WAIT# signal held at VIL by the external
memory system. Use of PCA module 3 may conflict with your design. Do not use CEX3 inter-
changeably with the WAIT# signal on the port 1.3 input. Setup and hold times are illustrated in
the 8XC251SA, SB, SP, SQ High-Performance CHMOS Microcontroller Datasheet.
13.5.2 Real-time WAIT CLOCK Enable (RTWCE)
The real-time WAIT CLOCK output is driven at port 1.7 (WCLK) by writing a logical ‘1’ to the
WCON.1 (RTWCE) bit at S:A7H. When enabled, the WCLK output produces a square wave sig-
(module 4) may conflict with your design. Do not use CEX4 interchangeably with WCLK output.
Use of address signal A17 disables both WCLK and CEX4 operation at the port 1.7 output.
13.5.3 Real-time Wait State Bus Cycle Diagrams
Figure 13-12 shows the code fetch/data read bus cycle in nonpage mode. Figure 13-14 depicts the
data read cycle in page mode.
CAUTION
The real-time wait function has critical external timing for code fetch. For this
reason, it is not advisable to use the real-time wait feature for code fetch in
page mode.
The data write bus cycle in nonpage mode is shown in Figure 13-13. Figure 13-15 shows the data
write bus cycle in page mode.
13-12
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EXTERNAL MEMORY INTERFACE
State 1
State 2
State 3
State 1 (next cycle)
WCLK
ALE
RD#/PSEN#
WAIT#
RD#/PSEN#
stretched
P0
P2
A0-A7
D0-D7
stretched
stretched
A0-A7
A8-A15
A8-A15
A5007-01
Figure 13-12. External Code Fetch/Data Read (Nonpage Mode, RT Wait State)
State 1
State 2
State 3
State 4
WCLK
ALE
WR#
WR# stretched
WAIT#
P0
D0-D7
A0-A7
stretched
stretched
P2
A8-A15
A5009-01
Figure 13-13. External Data Write (Nonpage Mode, RT Wait State)
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State 1
State 2
State 3
State 1 (next cycle)
WCLK
ALE
RD#/PSEN#
WAIT#
RD#/PSEN# stretched
P2
P0
A8-A15
D0-D7
A0-A7
stretched
stretched
A8-A15
A0-A7
A5008-01
Figure 13-14. External Data Read (Page Mode, RT Wait State)
State 1
State 2
State 3
State 4
WCLK
ALE
WR#
WR# stretched
WAIT#
P2
A8-A15
D0-D7
stretched
stretched
P0
A0-A7
A5010-01
Figure 13-15. External Data Write (Page Mode, RT Wait State)
13-14
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EXTERNAL MEMORY INTERFACE
13.6 CONFIGURATION BYTE BUS CYCLES
If EA# = 0, devices obtain configuration information from a configuration array in external mem-
ory. This section describes the bus cycles executed by the reset routine to fetch user configuration
bytes from external memory. Configuration bytes are discussed in Chapter 4, “Device Configu-
ration.”
the 8XC251Sx accesses external memory using internal address FF:FFF8H (UCONFIG0). See
states 1–4 in Figure 13-16. If the external memory is set up for page mode, it places UCONFIG0
on P2 as D7:0, overwriting A15:8 (FFH). If external memory is set up for nonpage mode, A15:8
is not overwritten. The 8XC251Sx examines P2 bit 1. Subsequent configuration byte fetches are
in page mode if P2.1 = 0 and in nonpage mode if P2.1 = 1. The 8XC251Sx fetches UCONFIG0
again (states 5–8 in Figure 13-16) and then UCONFIG1 via internal address FF:FFF9H.
The configuration byte bus cycles always execute with ALE extended and one PSEN# wait state.
State 1
State 2
State 3
State 4
State 5
State 6
State 7
State 8
XTAL
ALE
PSEN#
P0
A7:0 = F8H
A7:0 = F8H
A7:0 = F8H
A15:8 = FFH
D7:0
A15:8 = FFH
D7:0
D7:0
P2
Page Mode
A7:0 = F8H
P0
A15:8 = FFH
P2
Nonpage Mode
A4228-01
Figure 13-16. Configuration Byte Bus Cycles
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13.7 PORT 0 AND PORT 2 STATUS
This section summarizes the status of the port 0 and port 2 pins when these ports are used as the
external bus. A more comprehensive description of the ports and their use is given in Chapter 7,
“Input/Output Ports.”
When port 0 and port 2 are used as the external memory bus, the signals on the port pins can orig-
inate from three sources:
• the 8XC251Sx CPU (address bits, data bits)
• the port SFRs: P0 and P2 (logic levels)
• an external device (data bits)
The port 0 pins (but not the port 2 pins) can also be held in a high-impedance state. Table 13-3
lists the status of the port 0 and port 2 pins when the chip in is the normal operating mode and the
external bus is idle or executing a bus cycle.
Nonpage Mode
Page Mode
8-bit/16-bit
Addressing
Port
Bus Cycle
Bus Idle
Bus Cycle
Bus Idle
Port 0
Port 2
8 or 16
AD7:0 (1)
P2 (2)
High Impedance
A7:0 (1)
High Impedance
High Impedance
High Impedance
8
P2
P2
P2/D7:0 (2)
A15:8/D7:0
16
A15:8
NOTES:
1. During external memory accesses, the CPU writes FFH to the P0 register and the register con-
tents are lost.
2. The P2 register can be used to select 256-byte pages in external memory.
13.7.1 Port 0 and Port 2 Pin Status in Nonpage Mode
In nonpage mode, the port pins have the same signals as those on the 8XC51FX. For an external
memory instruction using a 16-bit address, the port pins carry address and data bits during the bus
cycle. However, if the instruction uses an 8-bit address (e.g., MOVX @Ri), the contents of P2 are
driven onto the pins. These pin signals can be used to select 256-bit pages in external memory.
During a bus cycle, the CPU always writes FFH to P0, and the former contents of P0 are lost. A
bus cycle does not change the contents of P2. When the bus is idle, the port 0 pins are held at high
impedance, and the contents of P2 are driven onto the port 2 pins.
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EXTERNAL MEMORY INTERFACE
13.7.2 Port 0 and Port 2 Pin Status in Page Mode
In a page-mode bus cycle, the data is multiplexed with the upper address byte on port 2. However,
if the instruction uses an 8-bit address (e.g., MOVX @Ri), the contents of P2 are driven onto the
pins when data is not on the pins. These logic levels can be used to select 256-bit pages in external
memory. During bus idle, the port 0 and port 2 pins are held at high impedance.
(For port pin status when the chip in is idle mode, powerdown mode, or reset, see Chapter 12,
“Special Operating Modes.”)
13-17
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13.8 EXTERNAL MEMORY DESIGN EXAMPLES
This section presents several external memory designs for 8XC251Sx systems. These examples
illustrate the design flexibility provided by the configuration options, especially for the PSEN#
and RD# signals. Many designs are possible. The examples employ the 8XC251SB but also apply
to SA, SP, and SQ devices if the differences in on-chip memory are allowed for. The first example
is an exception; it employs an 18-bit external address bus. For a general discussion on external
memory see “Configuring the External Memory Interface” on page 4-8. Figure 4-5 on page 4-10
13.8.1 Example 1: RD1:0 = 00, 18-bit Bus, External Flash and RAM
In this example, an 80C251SB operates in page mode with an 18-bit external address bus inter-
faced to 128 Kbytes of external flash memory and 128 Kbytes of external RAM (Figure 13-17).
Figure 13-18 shows how the external flash and RAM are addressed in the internal address space.
On-chip data RAM (1056 bytes) occupies the lowest addresses in region 00:.
CE#
CE#
80C251SB
A17
RAM
(128 Kbytes)
Flash
(128 Kbytes)
D7:0
D7:0
A15:8
A7:0
A16
Latch
P2
P0
A15:8
A7:0
A16
A16
EA#
WR#
PSEN#
OE#
WE#
OE#
WE#
A4219-01
Figure 13-17. Bus Diagram for Example 1: 80C251SB in Page Mode
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EXTERNAL MEMORY INTERFACE
Address Space
(256 Kbytes)
FFFFH
FF:
FE:
0000H
128 Kbytes External Flash
01:
128 Kbytes –1056 Bytes
External RAM
FFFFH
00:
0420H
1056 Bytes On-chip RAM
00:0000H
A4220-02
Figure 13-18. Address Space for Example 1
13-19
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13.8.2 Example 2: RD1:0 = 01, 17-bit Bus, External Flash and RAM
In this example, an 80C251SB operates in page mode with a 17-bit external address bus inter-
faced to 64 Kbytes of flash memory for code storage and 32 Kbytes of external RAM (Figure
13-19). The 80C251SB is configured so that PSEN# is asserted for all reads, and RD# functions
as A16 (RD1:0 = 01). Figure 13-20 shows how the external flash and RAM are addressed in the
internal address space. Addresses 0420H–7FFFH in external RAM are addressed in region 00:.
On-chip data RAM (1056 bytes) occupies the lowest addresses in region 00:.
CE#
CE#
80C251SB
RAM
(32 Kbytes)
FLASH
(64 Kbytes)
A16
D7:0
D7:0
P2
P0
A15:8
Data
A15:8
Code
A7;0
Latch
A15:8/D7:0
A7:0
A15:8
A7:0
EA#
WR#
OE#
WE#
WE#
OE#
PSEN#
A4148-01
Figure 13-19. Bus Diagram for Example 2: 80C251SB in Page Mode
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EXTERNAL MEMORY INTERFACE
Address Space
(256 Kbytes)
FFFFH
FF:
FE:
64 Kbytes External Flash
0000H
01:
00:
32 Kbytes –1056 Bytes External RAM
1056 Bytes On-chip RAM
7FFFH
0420H
00:0000H
A4168-03
Figure 13-20. Address Space for Example 2
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13.8.3 Example 3: RD1:0 = 01, 17-bit Bus, External RAM
In this example, an 87C251SB/83C251SB operates in nonpage mode with a 17-bit external ad-
dress bus interfaced to 128 Kbytes of external RAM (Figure 13-21). The 87C251SB/83C251SB
is configured so that RD# functions as A16, and PSEN# is asserted for all reads. Figure 13-22
shows how the external RAM is addressed in the internal address space.
RAM
(128 Kbytes)
83C251SB
87C251SB
VCC
EA#
CE#
A16
A16
A16
Data
A15:8
P2
P0
A15:8
AD7:0
A7:0
Latch
A7:0
D7:0
OE#
WR#
WE#
PSEN#
A4147-02
Figure 13-21. Bus Diagram for Example 3: 87C251SB/83C251SB in Nonpage Mode
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EXTERNAL MEMORY INTERFACE
Address Space
(256 Kbytes)
FFFFH
FF:
FE:
3FFFH
16 Kbytes On-chip Code Memory
0000H
128 Kbytes –1056 Bytes External RAM
01:
FFFFH
00:
0420H
1056 Bytes On-chip RAM
00:0000H
A4169-03
Figure 13-22. Address Space for Example 3
13-23
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13.8.4 Example 4: RD1:0 = 10, 16-bit Bus, External RAM
In this example, an 87C251SB/83C251SB operates in nonpage mode with a 16-bit external ad-
dress bus interfaced to 64 Kbytes of RAM (Figure 13-23). This configuration leaves
P3.7/RD#/A16 available for general I/O (RD1:0 = 10). A maximum of 64 Kbytes of external
memory can be used and all regions of internal memory map into the single 64-Kbyte region in
external memory (see Figure 4-6 on page 4-11). User code is stored in on-chip ROM/OT-
PROM/EPROM.
RAM
(64 Kbytes)
83C251SB
87C251SB
VCC
EA#
P2
CE#
A15:8
P0
Latch
A7:0
D7:0
WR#
WE#
OE#
PSEN#
A4221-01
Figure 13-23. Bus Diagram for Example 4: 87C251SB/83C251SB in Nonpage Mode
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EXTERNAL MEMORY INTERFACE
Address Space
(256 Kbytes)
FFFFH
FF:
FE:
3FFFH
16 Kbytes On-chip Code Memory
0000H
01:
FFFFH
External RAM 64 Kbytes – 1056 Bytes
1056 Bytes On-chip RAM
00:
0420H
00:0000H
A4224-02
Figure 13-24. Address Space for Example 4
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13.8.5 Example 5: RD1:0 = 11, 16-bit Bus, External EPROM and RAM
In this example, an 80C251SB operates in nonpage mode with a 16-bit external address bus in-
terfaced to 64 Kbytes of EPROM and 64 Kbytes of RAM (Figure 13-25). The 80C251SB is con-
figured so that RD# is asserted for addresses ≤ 7F:FFFFH and PSEN# is asserted for addresses ≥
80:0000H. Figure 13-26 shows two ways to address the external memory in the internal memory
space.
Addressing external RAM locations in either region 00: or region 01: produces the same address
at the external bus pins. However, if the external EPROM and the external RAM require different
numbers of wait states, the external RAM must be addressed entirely in region 01:. Recall that
the number of wait states for region 01: is independent of the remaining regions and always have
the same number of wait states (see Table 4-3 on page 4-13) unless the real-time wait states are
selected (see Figure 13-11 on page 13-11).
13.8.5.1
An Application Requiring Fast Access to the Stack
If an application requires fast access to the stack, the stack can reside in the fast on-chip data
RAM (00:0020H–00:041FH) and, when necessary, roll out into the slower external RAM. See
the left side of Figure 13-26. In this case, the external RAM can have wait states only if the
EPROM has wait states. Otherwise, if the stack rolls out above location 00:041FH, the external
RAM would be accessed with no wait state.
13.8.5.2
An Application Requiring Fast Access to Data
If fast access to a block of data is more important than fast access to the stack, the data can be
stored in the on-chip data RAM, and the stack can be located entirely in external memory. If the
external RAM requires a different number of wait states than the EPROM, address the external
RAM entirely in region 01:. See the right side of Figure 13-26. Addresses above 00:041FH roll
out to external memory beginning at 0420H.
13-26
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EXTERNAL MEMORY INTERFACE
EPROM
(64 Kbytes)
RAM
(64 Kbytes)
80C251SB
EA#
CE#
CE#
A15:8
P2
A15:8
Code
A15:8
Data
A7:0
A/D7:0
P0
Latch
A7:0
A7:0
D7:0
D7:0
WR#
OE#
RD#
WE#
OE#
PSEN#
A4145-01
Figure 13-25. Bus Diagram for Example 5: 80C251SB in Nonpage Mode
13-27
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Address Space
(256 Kbytes)
Address Space
(256 Kbytes)
64 Kbytes
FFFFH
FFFFH
64 Kbytes
External
EPROM
FF:
FE:
External EPROM
FF:
FE:
0000H
0000H
FFFFH
64 Kbytes
External
RAM
01:
01:
00:
0000H
0420H
External RAM
64 Kbytes –
1056 Bytes
FFFFH
00:
0420H
1056 Bytes
On-chip RAM
1056 Bytes
On-chip RAM
00:0000H
4175-03
Figure 13-26. Address Space for Examples 5 and 6
13-28
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13.8.6 Example 6: RD1:0 = 11, 16-bit Bus, External EPROM and RAM
faced to 64 Kbytes of EPROM and 64 Kbytes of RAM (Figure 13-27). The 80C251SB is config-
ured so that RD# is asserted for addresses ≤ 7F:FFFFH, and PSEN# is asserted for addresses ≥
80:0000.
This system is the same as Example 5 (Figure 13-25) except that it operates in page mode. Ac-
cordingly, the two systems have the same memory map (Figure 13-26), and the comments on ad-
dressing external RAM apply here also.
EPROM
(64 Kbytes)
RAM
(64 Kbytes)
80C251SB
D7:0
D7:0
P2
P0
A15:8
Code
A15:8
Data
Latch
A15:8/D7:0
A7:0
A15:8
A7:0
A7;0
EA#
CE#
CE#
WR#
OE#
RD#
WE#
OE#
PSEN#
A4146-01
Figure 13-27. Bus Diagram for Example 6: 80C251SB in Page Mode
13-29
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8XC251SA, SB, SP, SQ USER’S MANUAL
13.8.7 Example 7: RD1:0 = 01, 17-bit Bus, External Flash
In this example, an 80C251SB operates in page mode with a 17-bit external address bus inter-
faced to 128 Kbytes of flash memory (Figure 13-28). Port 2 carries both the upper address bits
(A15:0) and the data (D7:0), while port 0 carries only the lower address bits (A7:0). The
80C251SB is configured for a single read signal (PSEN#). The 128 Kbytes of external flash are
accessed via internal memory regions FE: and FF: in the internal address space.
80C251SB
FLASH
(128 Kbytes)
EA#
A16
CE#
A16
A16
Code
D7:0
P2
P0
A15:8
Latch
A15:8/D7:0
A7:0
A15:8
A7:0
OE#
WR#
WE#
PSEN#
A4151-01
Figure 13-28. Bus Diagram for Example 7: 80C251SB in Page Mode
13-30
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14
Programming and
Verifying Nonvolatile
Memory
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CHAPTER 14
PROGRAMMING AND VERIFYING
NONVOLATILE MEMORY
This chapter provides instructions for programming and verifying on-chip nonvolatile memory
on the 8XC251Sx. The programming instructions cover the entry of program code into on-chip
code memory, configuration information into the on-chip configuration bytes, and other catego-
ries of information into on-chip memory outside the memory address space. The verify instruc-
tions permit reading these memory locations to verify their contents. The operations covered in
this chapter are:
• programming and verifying the on-chip code memory
• programming and verifying the on-chip configuration bytes
• programming and verifying the lock bits
• programming the encryption array
(8 Kbytes, 16 Kbytes)
(8 bytes)
(3 bits)
(128 bytes)
(3 bytes)
• verifying the signature bytes
Programming instructions apply to the 87C251Sx (one-time programmable ROM (OTPROM)
and erasable programmable ROM (EPROM)). Verify instructions apply to the 87C251Sx, the
83C251Sx (mask ROM), and the configuration bytes on the 80C251SB, SQ (no ROM/OTPROM/
EPROM). In the unprogrammed state, EPROM and OTPROM contains all 1s.
14.1 GENERAL
The 87C251Sx is programmed and verified in the same manner as the 87C51FX, using the same
quick-pulse programming algorithm, which programs at VPP = 12.75 V using a series of five
100-µs PROG# pulses per byte. This results in a programming time of approximately 16 seconds
for the 16-Kbyte on-chip code memory.
Programming and verifying operations differ from normal microcontroller operation. Memory
accesses are made one byte at a time, input/output ports are used in a different manner, and the
EA#/VPP and ALE/PROG# pins are used for their alternative (programming) functions. For a
complete list of signal descriptions, see Appendix B.
14-1
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In some microcontroller applications, it is desirable that user program code be secure from unau-
thorized access. The 8XC251Sx offers two types of protection for program code stored in the on-
chip array.
• Program code in the on-chip code memory is encrypted when read out for verification if the
encryption array is programmed.
• A three-level lock bit system restricts external access to the on-chip code memory.
14.1.1 Programming Considerations for On-chip Code Memory
It is recommended that user program code be located starting at address FF:0100H. Since the first
instruction following device reset is fetched from FF:0000H, use a jump instruction to FF:0100H
to begin execution of the user program. For information on address spaces, see Chapter 3.
The top eight bytes of the memory address space (FF:FFF8H–FF:FFFFH) are reserved for device
configuration. Do not read or write user code at these locations. For EA# = 1, the reset routine
obtains configuration information from a configuration array located these addresses. For
EA# = 0, the reset routine obtains configuration information from a configuration array in exter-
nal memory using these internal addresses. For a detailed discussion of device configuration, see
Chapter 4.
ROM/OTPROM/EPROM devices have on-chip user code memory at FF:0000–FF:1FFFH
(8 Kbytes) or FF:0000H–FF:3FFFH (16 Kbytes). Addresses outside these ranges access external
memory. With EA# = 1 and both on-chip and external code memory, you can place code at the
highest addresses of the on-chip ROM/OTPROM/EPROM. When the highest on-chip address is
exceeded during execution, code fetches automatically rollover from on-chip memory to external
memory. See the notes on pipelining in section 3.2.2, “On-chip Code Memory (83C251SA, SB,
SP, SQ/87C251SA, SB, SP, SQ).”
With EA# = 1 and only on-chip code memory, multi-byte instructions and instructions that result
in call returns or prefetches should be located a few bytes below the maximum address to avoid
inadvertently exceeding the top address. Use an EJMP instruction, five or more addresses below
the top of memory, to continue execution in other areas of memory. See the note on pipelining in
section 3.2.2, “On-chip Code Memory (83C251SA, SB, SP, SQ/87C251SA, SB, SP, SQ).”
CAUTION
Execution of user code located in the top few bytes of the on-chip user
memory may cause prefetches from the next higher addresses, i.e. external
memory. External memory fetches make use of port 0 and port 3 and may
disrupt program execution if the program uses port 0 or port 3 for a different
purpose.
14-2
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PROGRAMMING AND VERIFYING NONVOLATILE MEMORY
14.1.2 EPROM Devices
On EPROM devices, the quartz window must be covered with an opaque label when the device
protect the RAM and other on-chip logic. Allowing light to impinge on the silicon die during
device operation may cause a logical malfunction.
14.2 PROGRAMMING AND VERIFYING MODES
Table 14-1 lists the programming and verifying modes and provides details about the setup. The
value applied to port 0 determines the mode. The upper digit specifies program or verify and the
lower digit selects what memory function is programmed (e.g., on-chip code memory, encryption
array, configuration bytes, etc.). The addresses applied to port 1 and port 3 address locations in
the selected memory function. The encryption array, lock bits, and signature bytes reside in non-
volatile memory outside the memory address space. Configuration bytes (UCONFIG0 and
PROM/EPROM devices (Figure 4-1 on page 4-2) and in external memory for devices without
ROM/OTPROM/EPROM (Figure 4-2 on page 4-3).
14.3 GENERAL SETUP
Figure 14-1 shows the general setup for programming and verifying nonvolatile memory on the
87C251Sx. The figure also applies to verifying the 83C251Sx and reading the configuration bytes
on the 80C251SB, and the 80C251SQ.
The controller must be running with an oscillator frequency of 4 MHz to 6 MHz. To program, set
up the controller as shown in Table 14-1 with the mode of operation (program/verify and memory
plied to ports 1 and 3, and the data on port 2. Apply a logic high to the RST pin and VCC to
EA#/VPP. ALE/PSEN#, normally an output pin, must be held low externally.
To perform the write operation, raise VPP to 12.75 V and pulse the PROG# pin per Table 14-1.
Then return VPP to 5 V. Verification is performed in a similar manner but without increasing VPP
and without pulsing PROG#. Figure 14-2 shows the program and verify bus cycle waveforms.
For waveform timing information, refer to the 8XC251SA, SB, SP, SQ High-Performance
CHMOS Microcontroller Datasheet.
CAUTION
The VPP source must be well regulated and free of glitches. The voltage on the
V
PP pin must not exceed the specified maximum, even under transient
conditions. See the current data sheet.
14-3
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Table 14-1. Programming and Verifying Modes
Mode
RST PSEN#
VPP
PROG#
Port Port
Address
Port 1 (high)
Port 3 (low)
Notes
0
2
Program Mode. On-chip
Code Memory
8K 87C251SA,SP
16K 87C251SB,SQ
High
High
High
Low
Low
Low
Low
5 V,
12.75 V
5 Pulses 68H data
1, 4
0000H-1FFFH
0000H-3FFFH
Verify Mode. On-chip
Code Memory
8K 87/83C251SA,SP
16K 87/83C251SB,SQ
5 V
High
28H data
4
1, 4
4
0000H-1FFFH
0000H-3FFFH
Program Mode. Configu-
ration Bytes (UCONFIG0,
UCONFIG1)
5 V,
12.75 V
5 Pulses 69H data FFF8H-FFFFH
87C251Sx
Verify Mode. Configuration High
Bytes (UCONFIG0,
UCONFIG1)
5 V
High
29H data FFF8H-FFFFH
8XC251Sx
Program Mode. Lock Bits
87C251Sx
High
High
Low
Low
Low
Low
5 V,
12.75 V
25 Pulses 6BH data 0001H-0003H
1, 2
3
Verify Mode. Lock bits
87C251Sx, 83C251Sx
5 V
High
2BH data
0000H
Program Mode. Encryption High
Array
87C251Sx
5 V,
12.75 V
1
Verify Mode. Signature
Bytes
87C251Sx, 83C251Sx
High
5 V
High
29H data 0030H, 0031H,
0060H,
0061H
NOTES:
1. To program, raise VPP to 12.75 V and pulse the PROG# pin. See Figure 14-2 for waveforms.
2. No data input. Identify the lock bits with the address lines as follows: LB3 - 0003H, LB2 - 0002H,
LB1 - 0001H.
3. The three lock bits are verified in a single operation. The states of the lock bits appear simultaneously
at port 2 as follows: LB3 - P2.3, LB2 - P2.2. LB1 - P2.1. High = programmed.
4. For these modes, the internal address is FF:xxxxH.
14-4
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PROGRAMMING AND VERIFYING NONVOLATILE MEMORY
VCC
8XC251Sx
VCC
P3
P1
A0 - A7
RST
Address
(16 Bits)
Data
(8 Bits)
P2
A8 - A15
EA#/V
Programming
Signals
pp
XTAL1
ALE/PROG#
PSEN#
4 MHz
to
6 MHz
XTAL2
VSS
Program/Verify Mode
(8 Bits)
P0
A4122-02
Figure 14-1. Setup for Programming and Verifying Nonvolatile Memory
14.4 PROGRAMMING ALGORITHM
The procedure for programming the 87C251Sx is as follows:
1. Set up the controller for operation in the appropriate mode according to Table 14-1.
2. Input the 16-bit address on ports 1 and 3.
3. Input the data byte on port 2.
4. Raise the voltage on the VPP pin from 5 V to 12.75 V.
5. Pulse the PROG# pin 5 times for the on-chip code memory and the configuration bytes,
and 25 times for the encryption array and the lock bits.
6. Reduce the voltage on the VPP pin to 5 V.
7. If the procedure is program/immediate-verify, go to section 14.5, “Verify Algorithm,” and
perform steps 1 through 4 to verify the currently addressed byte. Make sure the voltage on
the EA#/VPP pin has been lowered to 5 V before performing the verifying procedure.
8. Repeat steps 1 through 7 until all memory locations are programmed.
14-5
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Programming Cycle
Verification Cycle
P1, P3
P2
Address (16-Bit)
Data In (8-Bit)
Address
Data Out
PROG#
1
2
3
4
5
12.75V
EA#/V
PP
5V
P0
Mode (8-Bit)
Mode
A4129-01
Figure 14-2. Program/Verify Bus Cycles
14.5 VERIFY ALGORITHM
Use this procedure to verify user program code, signature bytes, configuration bytes, and lock bits
stored in nonvolatile memory on the 8XC251Sx. To preserve the secrecy of the encryption key
byte sequence, the encryption array cannot be verified. Verification can be performed on bytes as
they are programmed, or on a block of bytes that have been previously programmed. The proce-
dure for verifying the 8XC251Sx is as follows:
1. Set up the controller for operation in the appropriate mode according to Table 14-1.
2. Input the 16-bit address on ports P1 and P3.
3. Wait for the data on port P2 to become valid (TAVQV = 48 clock cycles — see the
datasheet), then compare the data with the expected value.
4. If the procedure is program/immediate-verify, return to step 8 of 14.4, “Programming
Algorithm,” to program the next byte.
5. Repeat steps 1 through 5 until all memory locations are verified.
14.6 PROGRAMMABLE FUNCTIONS
This section discusses factors related to programming and verifying the various nonvolatile mem-
ory functions.
14-6
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PROGRAMMING AND VERIFYING NONVOLATILE MEMORY
14.6.1 On-chip Code Memory
FF:0000H. At reset, the 87C251Sx and 83C251Sx devices vector to this address. See Chapter 3,
“Address Spaces,” for detailed information on the 8XC251Sx address space.
scribed in 14.4, “Programming Algorithm,” using the program on-chip code memory mode (Ta-
ble 14-1).
To verify that the on-chip code memory is correctly programmed, perform the procedure de-
scribed in section 14.5, “Verify Algorithm,” using the verify on-chip code memory mode (Table
14-1).
14.6.2 Configuration Bytes
ray at FF:FFF8H–FF:FFFFH. UCONFIG0 (FF:FFF8H) and UCONFIG1 (FF:FFF9H) are imple-
mented; the remaining bytes are reserved for future use. See Figure 4-1 on page 4-2, Figure 4-3
on page 4-6, and Figure 4-4 on page 4-7.
To program the 87C251Sx configuration bytes, perform the procedure described in 14.4, “Pro-
gramming Algorithm,” using the program configuration byte mode (Table 14-1).
To verify the 87C251Sx, 83C251Sx, or 80C251SB, SQ configuration bytes, perform the proce-
dure described in 14.5, “Verify Algorithm,” using the verify configuration byte mode (Table
14-1).
14.6.3 Lock Bit System
The 87C251Sx provides a three-level lock system for protecting user program code stored in the
on-chip code memory from unauthorized access. On the 83C251Sx, only LB1 protection is avail-
To program the lock bits, perform the procedure described in 14.4, “Programming Algorithm,”
using the program lock bits mode (Table 14-1).
To verify that the lock bits are correctly programmed, perform the procedure described in 14.5,
“Verify Algorithm,” using the verify lock bits mode (Table 14-1).
14-7
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Table 14-2. Lock Bit Function
Lock Bits Programmed
Protection Type
LB3
U
LB2
U
LB1
U
Level 1
Level 2
No program lock features are enabled. On-chip user code is
encrypted when verified, if encryption array is programmed.
U
U
P
External code is prevented from fetching code bytes from on-
chip code memory. Further programming of the on-chip
OTPROM is disabled.
Level 3
Level 4
U
P
P
P
P
P
Same as level 2, plus on-chip code memory verify is disabled.
Same as level 3, plus external memory execution is disabled.
NOTE: Other combinations of the lock bits are not defined.
14.6.4 Encryption Array
The 87C251Sx and 83C251Sx controllers include a 128-byte encryption array located in nonvol-
atile memory outside the memory address space. During verification of the on-chip code memory,
the seven low-order address bits also address the encryption array. As the byte of the code mem-
ory is read, it is exclusive-NOR’ed (XNOR) with the key byte from the encryption array. If the
encryption array is not programmed (still all 1s), the user program code is placed on the data bus
in its original, unencrypted form. If the encryption array is programmed with key bytes, the user
program code is encrypted and can’t be used without knowledge of the key byte sequence.
CAUTION
memory that does not contain program code should be filled with “random”
byte values other than FFH to prevent the encryption key sequence from being
revealed.
To program the encryption array, perform the procedure described in section 14.4, “Programming
Algorithm,” using the program encryption array mode (Table 14-1).
To preserve the secrecy of the encryption key byte sequence, the encryption array can not be ver-
ified.
14.6.5 Signature Bytes
The 87C251Sx and 83C251Sx contain factory-programmed signature bytes. These bytes are lo-
cated in nonvolatile memory outside the memory address space at 30H, 31H, 60H, and 61H. To
read the signature bytes, perform the procedure described in 14.5, “Verify Algorithm,” using the
verify signature mode (Table 14-1). Signature byte values are listed in Table 14-3.
14-8
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PROGRAMMING AND VERIFYING NONVOLATILE MEMORY
Table 14-3. Contents of the Signature Bytes
ADDRESS
30H
CONTENTS
89H
DEVICE TYPE
Indicates Intel Devices
31H
40H
Indicates MCS 251 core product
Indicates 83C251SA device
Indicates 83C251SB device
Indicates 83C251SP device
Indicates 83C251SQ device
Indicates 87C251SA device
Indicates 87C251SB device
Indicates 87C251SP device
Indicates 87C251SQ device
Indicates 8XC251SA, SB, SP, SQ
60H
7AH
60H
7BH
60H
4AH
60H
4BH
60H
FAH
60H
FBH
60H
CAH
CBH
55H
60H
61H
14.7 VERIFYING THE 83C251SA, SB, SP, SQ (ROM)
applies, as do the waveform and timing diagrams. Like the 87C251Sx, the 83C251Sx has 8-
Kbytes or 16-Kbytes of on-chip code memory and a 128-byte encryption array.
For information on verifying the contents of nonvolatile memory on the 83C251Sx, see 14.6,
“Programmable Functions” for each function desired. Or more directly, perform the verification
procedure described in 14.5, “Verify Algorithm,” using the appropriate verify mode (Table 14-1).
14-9
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A
Instruction Set
Reference
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APPENDIX A
INSTRUCTION SET REFERENCE
®
times — and a detailed description of each instruction. It contains the following tables:
• Tables A-1 through A-4 describe the notation used for the instruction operands. Table A-5
describes the notation used for control instruction destinations.
• Tables A-6 and A-7 comprise the opcode map for the instruction set.
• Tables A-8 through A-17 contain supporting material for the opcode map.
Add and Subtract Instructions, Table A-19
Compare Instructions, Table A-20
Logical Instructions, Table A-23
Move Instructions, Table A-24
Exchange, Push, and Pop Instructions, Table A-25
Bit Instructions, Table A-26
Control Instructions, Table A-27
“Instruction Descriptions” on page A-26 contains a detailed description of each instruction.
NOTE
The instruction execution times given in this appendix are for code executing
chip RAM. Execution times are increased by executing code from external
memory, accessing peripheral SFRs, accessing data in external memory, using
a wait state, or extending the ALE pulse.
For some instructions, accessing the port SFRs, Px, x = 0–3, increases the
execution time. These cases are listed in Table A-18 and are noted in the
instruction summary tables and the instruction descriptions.
A-1
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A.1 NOTATION FOR INSTRUCTION OPERANDS
Table A-1. Notation for Register Operands
®
MCS 251 MCS 51
Register Notation
Arch.
Arch.
@Ri
A memory location (00H–FFH) addressed indirectly via byte register
R0 or R1
✔
Rn
n
Byte register R0–R7 of the currently selected register bank
Byte register index: n = 0–7
✔
r r r
Binary representation of n
Rm
Byte register R0–R15 of the currently selected register file
Destination register
Rmd
Rms
Source register
✔
m, md, ms Byte register index: m, md, ms = 0–15
s s s s
Binary representation of m or md
Binary representation of ms
S S S S
WRj
Word register WR0, WR2, ..., WR30 of the currently selected register
file
WRjd
WRjs
@WRj
Destination register
Source register
A memory location (00:0000H–00:FFFFH) addressed indirectly
through word register WR0–WR30
✔
@WRj
+dis16
Data RAM location (00:0000H–00:FFFFH) addressed indirectly
through a word register (WR0–WR30) + displacement value, where
the displacement value is from 0 to 64 Kbytes.
j, jd, js
t t t t
Word register index: j, jd, js = 0–30
Binary representation of j or jd
Binary representation of js
T T T T
DRk
Dword register DR0, DR4, ..., DR28, DR56, DR60 of the currently
selected register file
DRkd
DRks
@DRk
Destination Register
Source Register
A memory location (00:0000H–FF:FFFFH) addressed Indirectly
through dword register DR0–DR28, DR56, DR60
✔
@DRk
+dis24
Data RAM location (00:0000H–FF:FFFFH) addressed indirectly
through a dword register (DR0–DR28, DR56, DR60) + displacement
value, where the displacement value is from 0 to 64 Kbytes
k, kd, ks
u u u u
Dword register index: k, kd, ks = 0, 4, 8, ..., 28, 56, 60
Binary representation of k or kd
U U U U
Binary representation of ks
A-2
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INSTRUCTION SET REFERENCE
Table A-2. Notation for Direct Addresses
®
Direct
Address.
MCS 251 MCS 51
Description
Arch.
Arch.
dir8
An 8-bit direct address. This can be a memory address
(00:0000H–00:00FFH) or an SFR address (S:00H - S:FFH).
✔
✔
dir16
A 16-bit memory address (00:0000H–00:FFFFH) used in direct
addressing.
✔
Table A-3. Notation for Immediate Addressing
Description
®
Immediate
Data
MCS 251 MCS 51
Arch.
Arch.
#data
An 8-bit constant that is immediately addressed in an instruction.
A 16-bit constant that is immediately addressed in an instruction.
✔
✔
✔
#data16
#0data16
#1data16
A 32-bit constant that is immediately addressed in an instruction. The
upper word is filled with zeros (#0data16) or ones (#1data16).
✔
#short
A constant, equal to 1, 2, or 4, that is immediately addressed in an
instruction.
✔
v v
Binary representation of #short.
Table A-4. Notation for Bit Addressing
Description
®
Bit
MCS 251 MCS 51
Address
Arch.
Arch.
bit
A directly addressed bit in memory locations 00:0020H–00:007FH or in
any defined SFR.
✔
y y y
bit51
A binary representation of the bit number (0–7) within a byte.
A directly addressed bit (bit number = 00H–FFH) in memory or an SFR.
Bits 00H–7FH are the 128 bits in byte locations 20H–2FH in the on-chip
RAM. Bits 80H–FFH are the 128 bits in the 16 SFR’s with addresses
that end in 0H or 8H: S:80H, S:88H, S:90H, . . . , S:F0H, S:F8H.
✔
Table A-5. Notation for Destinations in Control Instructions
®
Destination
Address
MCS 251 MCS 51
Description
Arch.
Arch.
rel
A signed (two's complement) 8-bit relative address. The destination is
-128 to +127 bytes relative to first byte of the next instruction.
✔
✔
addr11
addr16
addr24
An 11-bit destination address. The destination is in the same 2-Kbyte
block of memory as the first byte of the next instruction.
✔
✔
✔
✔
✔
A 16-bit destination address. A destination can be anywhere within
the same 64-Kbyte region as the first byte of the next instruction.
A 24-bit destination address. A destination can be anywhere within
the 16-Mbyte address space.
A-3
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8XC251SA, SB, SP, SQ USER’S MANUAL
A.2 OPCODE MAP AND SUPPORTING TABLES
®
Table A-6. Instructions for MCS 51 Microcontrollers
Bin.
0
0
1
1
2
2
3
3
4
4
5
5
6-7
8-F
Src.
A5x6–A5x7
A5x8–A5xF
0
NOP
AJMP
addr11
LJMP
addr16
RR
A
INC
A
INC
dir8
INC
@Ri
INC
Rn
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
JBC
bit,rel
ACALL LCALL
RRC
A
DEC
A
DEC
dir8
DEC
@Ri
DEC
Rn
addr11
addr16
JB
bit,rel
AJMP
RET
RLA
ADD
A,#data
ADD
A,dir8
ADD
A,@Ri
ADD
A,Rn
addr11
JNB
bit,rel
ACALL RETI
addr11
RLCA
ORL
ADDC
A,#data
ADDC
A,dir8
ADDC
A,@Ri
ADDC
A,Rn
JC
rel
AJMP
ORL
ORL
A,#data
ORL
A,dir8
ORL
A,@Ri
ORL
A,Rn
addr11
dir8,A
dir8,#data
JNC
rel
ACALL ANL
ANL
dir8,#data
ANL
A,#data
ANL
A,dir8
ANL
A,@Ri
ANL
A,Rn
addr11
dir8,A
JZ
rel
AJMP
XRL
XRL
dir8,#data
XRL
A,#data
XRL
A,dir8
XRL
A,@Ri
XRL
A,Rn
addr11
dir8,A
JNZ
rel
ACALL ORL
JMP
@A+DPTR
MOV
A,#data
MOV
MOV
MOV
Rn,#data
addr11
CY,bit
dir8,#data @Ri,#data
SJMP
rel
AJMP
ANL
MOVC
A,@A+PC
DIV
AB
MOV
dir8,dir8
MOV
dir8,@Ri
MOV
dir8,Rn
addr11
CY,bit
MOV
ACALL MOV
MOVC
A,@A+DPTR
SUBB
A,#data
SUBB
A,dir8
SUBB
A,@Ri
SUBB
A,Rn
DPTR,#data16 addr11
bit,CY
ORL
CY,bit
AJMP
MOV
INC
DPTR
MUL
AB
ESC
MOV
@Ri,dir8
MOV
Rn,dir8
addr11
CY,bit
ANL
CY,bit
ACALL CPL
CPL
CY
CJNE
A,#data,rel
CJNE
A,dir8,rel
CJNE
CJNE
addr11
bit
@Ri,#data,rel Rn,#data,rel
PUSH
dir8
AJMP
addr11
CLR
bit
CLR
CY
SWAP
A
XCH
A,dir8
XCH
A,@Ri
XCH
A,Rn
POP
dir8
ACALL SETB
SETB
CY
DA
A
DJNZ
dir8,rel
XCHD
A,@Ri
DJNZ
Rn,rel
addr11
bit
MOVX
A,@DPTR
AJMP
addr11
MOVX
A,@Ri
CLR
A
MOV
A,dir8
MOV
A,@Ri
MOV
A,Rn
MOV
@DPTR,A
ACALL
addr11
MOVX
@Ri,A
CPL
A
MOV
dir8,A
MOV
@Ri,A
MOV
Rn,A
A-4
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INSTRUCTION SET REFERENCE
®
Bin. A5x8
A5x9
x9
A5xA
xA
A5xB
xB
A5xC
xC
A5xD
xD
A5xE
xE
A5xF
xF
Src.
x8
0
JSLE
rel
MOV
Rm,@WRj+dis
MOVZ
WRj,Rm
INC R,#short (1)
MOV reg,ind
SRA
reg
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
JSG
rel
MOV
@WRj+dis,Rm
MOVS
WRj,Rm
DEC R,#short (1)
MOV ind,reg
SRL
reg
JLE
rel
MOV
Rm,@DRk+dis
ADD
Rm,Rm
ADD
WRj,WRj
ADD
ADD
reg,op2 (2) DRk,DRk
JG
rel
MOV
@DRk+dis,Rm
SLL
reg
JSL
rel
MOV
WRj,@WRj+dis
ORL
Rm,Rm
ORL
WRj,WRj
ORL
reg,op2 (2)
JSGE MOV
rel
ANL
Rm,Rm
ANL
WRj,WRj
ANL
reg,op2 (2)
@WRj+dis,WRj
JE
rel
MOV
WRj,@DRk+dis
XRL
Rm,Rm
XRL
WRj,WRj
XRL
reg,op2 (2)
JNE
rel
MOV
MOV
MOV
Rm,Rm
MOV
WRj,WRj
MOV
MOV
@DRk+dis,WRj op1,reg (2)
reg,op2 (2) DRk,DRk
LJMP @WRj
EJMP @DRk
EJMP
addr24
DIV
Rm,Rm
DIV
WRj,WRj
LCALL@WRj
ECALL @DRk
ECALL
addr24
SUB
Rm,Rm
SUB
WRj,WRj
SUB
SUB
reg,op2 (2) DRk,DRk
Bit
ERET
MUL
Rm,Rm
MUL
WRj,WRj
Instructions (3)
TRAP
CMP
Rm,Rm
CMP
WRj,WRj
CMP
CMP
reg,op2 (2) DRk,DRk
PUSH op1 (4)
MOV DRk,PC
POP
op1 (4)
NOTES:
1. R = Rm/WRj/DRk.
2. op1, op2 are defined in Table A-8.
3. See Tables A-10 and A-11.
4. See Table A-12.
A-5
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Table A-8. Data Instructions
Instruction
Byte 0
Byte 1
Byte 2
Byte 3
Oper Rmd,Rms
Oper WRjd,WRjs
Oper DRkd,DRks
Oper Rm,#data
x
x
x
x
x
x
C
D
F
md
ms
jd/2
kd/4
m
js/2
ks/4
0000
0100
1000
1100
E
E
E
#data
Oper WRj,#data16
Oper DRk,#data16
j/2
#data (high)
#data (high)
#data (high)
#data (low)
#data (low)
#data (low)
k/4
k/4
MOV DRk(h),#data16
MOV DRk,#1data16
CMP DRk,#1data16
7
7
A
E
E
B
Oper Rm,dir8
Oper WRj,dir8
Oper DRk,dir8
Oper Rm,dir16
Oper WRj,dir16
Oper DRk,dir16 (1)
Oper Rm,@WRj
Oper Rm,@DRk
NOTE:
x
x
x
x
x
x
x
x
E
E
E
E
E
E
E
E
m
j/2
k/4
m
0001
0101
1101
0011
0111
1111
1001
1011
dir8 addr
dir8 addr
dir8 addr
dir16 addr (high)
dir16 addr (high)
dir16 addr (high)
dir16 addr (low)
dir16 addr (low)
dir16 addr (low)
j/2
k/4
j/2
k/4
m
m
00
00
1. For this instruction, the only valid operation is MOV.
Table A-9. High Nibble, Byte 0 of Data Instructions
x
Operation
Notes
2
9
B
4
5
6
7
8
A
ADD reg,op2
SUB reg,op2
CMP reg,op2 (1)
ORL reg,op2 (2)
ANL reg,op2 (2)
XRL reg,op2 (2)
MOV reg,op2
DIV reg,op2
All addressing modes are
supported.
Two modes only:
reg,op2 = Rmd,Rms
reg,op2 = Wjd,Wjs
MUL reg,op2
NOTES:
1. The CMP operation does not support DRk, direct16.
2. For the ORL, ANL, and XRL operations, neither reg nor op2
can be DRk.
A-6
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INSTRUCTION SET REFERENCE
All of the bit instructions in the MCS 251 architecture (Table A-7) have opcode A9, which serves
as an escape byte (similar to A5). The high nibble of byte 1 specifies the bit instruction, as given
in Table A-10.
Table A-10. Bit Instructions
Instruction
Byte 0(x)
Byte 1
xxxx
Byte 2
Byte 3
1
Bit Instr (dir8)
A
9
0
bit
dir8 addr
rel addr
Table A-11. Byte 1 (High Nibble) for Bit Instructions
xxxx
Bit Instruction
JBC bit
0001
0010
0011
0111
1000
1001
1010
1011
1100
1101
1110
1111
JB bit
JNB bit
ORL CY,bit
ANL CY,bit
MOV bit,CY
MOV CY,bit
CPL bit
CLR bit
SETB bit
ORL CY, /bit
ANL CY, /bit
A-7
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Table A-12. PUSH/POP Instructions
Instruction
Byte 0(x)
Byte 1
0010
Byte 2
Byte 3
PUSH #data
PUSH #data16
PUSH Rm
PUSH WRj
PUSH DRk
MOV DRk,PC
POP Rm
C
A
A
A
A
A
A
A
A
A
0000
0000
m
#data
#data16 (high)
C
C
C
C
C
D
D
D
0110
1000
1001
1011
0001
1000
1001
1011
#data16 (low)
j/2
k/4
k/4
m
POP WRj
j/2
POP DRk
k/4
Table A-13. Control Instructions
Instruction
Byte 0(x)
Byte 1
Byte 2
Byte 3
EJMP addr24
ECALL addr24
LJMP @WRj
LCALL @WRj
EJMP @DRk
ECALL @DRk
ERET
8
9
8
9
8
9
A
8
7
2
3
4
5
0
1
B
A
A
9
9
9
9
A
8
8
8
8
8
8
8
8
9
addr[23:16]
addr[23:16]
addr[15:8]
addr[15:8]
addr[7:0]
addr[7:0]
j/2
j/2
0100
0100
1000
1000
k/4
k/4
JE rel
rel
rel
rel
rel
rel
rel
rel
rel
JNE rel
JLE rel
JG rel
JSL rel
JSGE rel
JSLE rel
JSG rel
TRAP
A-8
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INSTRUCTION SET REFERENCE
Table A-14. Displacement/Extended MOVs
Instruction
Byte 0
Byte 1
j/2
Byte 2
Byte 3
MOV Rm,@WRj+dis
MOV WRk,@WRj+dis
MOV Rm,@DRk+dis
MOV WRj,@DRk+dis
MOV @WRj+dis,Rm
MOV @WRj+dis,WRk
MOV @DRk+dis,Rm
MOV @DRk+dis,WRj
MOVS WRj,Rm
0
4
2
6
1
5
3
7
1
0
0
0
1
1
7
7
7
7
7
7
7
7
9
9
m
dis[15:8]
dis[15:8]
dis[15:8]
dis[15:8]
dis[15:8]
dis[15:8]
dis[15:8]
dis[15:8]
dis[7:0]
dis[7:0]
dis[7:0]
dis[7:0]
dis[7:0]
dis[7:0]
dis[7:0]
dis[7:0]
j/2
m
k2
k/4
k/4
j/2
k2
k/4
k/4
m
9
9
j/2
m
9
9
j/2
m
9
9
j/2
j/2
j/2
A
A
B
B
B
B
A
A
A
A
A
A
A
A
MOVZ WRj,Rm
m
MOV WRj,@WRj
MOV WRj,@DRk
MOV @WRj,WRj
MOV @DRk,WRj
MOV dir8,Rm
j/2 1000
k/4 1010
j/2 1000
k/4 1010
j/2
0000
j/2
0000
0000
0000
j/2
j/2
m
0001
dir8 addr
dir8 addr
dir8 addr
MOV dir8,WRj
j/2 0101
k/4 1101
MOV dir8,DRk
MOV dir16,Rm
m
0011
dir16 addr (high)
dir16 addr (high)
dir16 addr (high)
dir16 addr (low)
dir16 addr (low)
dir16 addr (low)
MOV dir16,WRj
j/2 0111
k/4 1111
j/2 1001
k/4 1011
MOV dir16,DRk
MOV @WRj,Rm
MOV @DRk,Rm
m
m
0000
0000
A-9
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Table A-15. INC/DEC
Instruction
Byte 0
Byte 1
00 ss
1
2
3
4
5
6
INC Rm,#short
INC WRj,#short
INC DRk,#short
DEC Rm,#short
DEC WRj,#short
DEC DRk,#short
0
0
0
1
1
1
B
B
B
B
B
B
m
j/2 01 ss
k/4 11 ss
m
00 ss
j/2 01 ss
k/4 11 ss
Table A-16. Encoding for INC/DEC
ss
#short
00
01
10
1
2
4
Table A-17. Shifts
Instruction
Byte 0
Byte 1
0000
j/2 0100
0000
j/2 0100
0000
j/2 0100
1
2
3
4
5
6
SRA Rm
SRA WRj
SRL Rm
SRL WRj
SLL Rm
SLL WRj
0
0
1
1
3
3
E
E
E
E
E
E
m
m
m
A-10
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INSTRUCTION SET REFERENCE
A.3 INSTRUCTION SET SUMMARY
This section summarizes the MCS 251 architecture instruction set. Tables A-19 through A-27 list
the instructions by category, providing for each instruction a short description, its length in bytes,
and its execution time in states.
NOTE
The instruction execution times given in the tables are for code executing from
on-chip code memory and for data that is read from and written to on-chip
RAM. Execution times are increased by executing code from external
memory, accessing peripheral SFRs, accessing data in external memory, using
a wait state, or extending the ALE pulse.
execution time. These cases are noted individually in the tables.
A.3.1 Execution Times for Instructions that Access the Port SFRs
The execution times for some instructions increase when the instruction accesses a port SFR (Px,
x = 0–3) as opposed to any other SFR. Table A-18 lists these instructions and the execution times
for Case 0:
• Case 0. Code executes from on-chip ROM/OTPROM/EPROM and accesses locations in
on-chip data RAM. The port SFRs are not accessed.
In Cases 1–4, the instructions access a port SFR:
• Case 1. Code executes from on-chip ROM/OTPROM/EPROM and accesses a port SFR.
• Case 2. Code executes from external memory with no wait state and a short ALE (not
extended) and accesses a port SFR.
• Case 3. Code executes from external memory with one wait state and a short ALE (not
extended) and accesses a port SFR.
• Case 4. Code executes from external memory with one wait state and an extended ALE, and
accesses a port SFR.
The times for Cases 1 through 4 are expressed as the number of state times to add to the state
times for given for Case 0.
A-11
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Table A-18. State Times to Access the Port SFRs
Case 0
Execution Times
Additional State Times
Instruction
Binary
Source
Case 1
Case 2
Case 3
Case 4
ADD A,dir8
1
3
1
1
3
1
3
1
3
2
3
4
2
3
4
2
2
2
1
4
2
3
1
3
2
4
2
3
1
1
3
1
3
1
2
1
1
2
1
2
1
3
2
2
3
2
2
3
2
2
2
1
3
2
2
1
3
2
3
3
2
2
1
2
1
2
1
1
1
1
1
1
1
1
2
2
1
2
2
1
2
2
2
2
1
2
2
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
4
4
2
4
4
2
4
4
4
4
2
4
4
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
3
3
3
3
3
6
6
3
6
6
3
6
6
6
6
3
6
6
3
3
3
3
3
3
3
3
3
3
3
3
4
4
4
4
4
4
4
4
8
8
4
8
8
4
8
8
8
8
4
8
8
4
4
4
4
4
4
4
4
4
4
4
4
ADD Rm,dir8
ADDC A,dir8
ANL A,dir8
ANL CY,bit
ANL CY,bit51
ANL CY,/bit
ANL CY,/bit51
ANL dir8,#data
ANL dir8,A
ANL Rm,dir8
CLR bit
CLR bit51
CMP Rm,dir8
CPL bit
CPL bit51
DEC dir8
INC dir8
MOV A,dir8
MOV bit,CY
MOV bit51,CY
MOV CY,bit
MOV CY,bit51
MOV dir8,#data
MOV dir8,A
MOV dir8,Rm
MOV dir8,Rn
MOV Rm,dir8
MOV Rn,dir8
ORL A,dir8
ORL CY,bit
ORL CY,bit51
ORL CY,/bit
A-12
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INSTRUCTION SET REFERENCE
Table A-18. State Times to Access the Port SFRs (Continued)
Case 0
Execution Times
Additional State Times
Instruction
Binary
Source
Case 1
Case 2
Case 3
Case 4
ORL CY,/bit51
ORL dir8,#data
ORL dir8,A
1
3
2
3
4
2
3
1
3
1
3
2
3
1
3
2
2
3
2
2
1
3
1
3
2
2
1
1
2
1
2
2
1
1
2
1
2
2
1
2
2
4
2
4
4
2
2
4
2
4
4
2
3
3
6
3
6
6
3
3
6
3
6
6
3
4
4
8
4
8
8
4
4
8
4
8
8
4
ORL Rm,dir8
SETB bit
SETB bit51
SUB Rm,dir8
SUBB A,dir8
XCH A,dir8
XRL A,dir8
XRL dir8,#data
XRL dir8,A
XRL Rm,dir8
A-13
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A.3.2 Instruction Summaries
Table A-19. Summary of Add and Subtract Instructions
Add
Subtract
Add with Carry
Subtract with Borrow
ADD <dest>,<src>
dest opnd ← dest opnd + src opnd
SUB <dest>,<src>
ADDC <dest>,<src>
SUBB <dest>,<src>
dest opnd ← dest opnd - src opnd
(A) ← (A) + src opnd + carry bit
(A) ← (A) - src opnd - carry bit
Binary Mode
Source Mode
Mnemonic
<dest>,<src>
Notes
Bytes States Bytes States
A,Rn
Reg to acc
1
2
1
2
3
3
3
4
5
5
1
1 (2)
2
2
2
2
2
2
2
2
3
4
4
2
1 (2)
3
A,dir8
Dir byte to acc
ADD
A,@Ri
Indir addr to acc
A,#data
Immediate data to acc
Byte reg to/from byte reg
Word reg to/from word reg
Dword reg to/from dword reg
Immediate 8-bit data to/from byte reg
Immediate 16-bit data to/from word reg
1
1
Rmd,Rms
WRjd,WRjs
DRkd,DRks
Rm,#data
WRj,#data16
DRk,#0data16
2
1
3
2
5
4
3
2
4
3
16-bit unsigned immediate data to/from
dword reg
6
5
ADD;
SUB
Rm,dir8
WRj,dir8
Rm,dir16
WRj,dir16
Rm,@WRj
Rm,@DRk
A,Rn
Dir addr to/from byte reg
4
4
5
5
4
4
1
2
1
2
3 (2)
3
3
4
4
3
3
2
2
2
2
2 (2)
Dir addr to/from word reg
4
3
3
2
Dir addr (64K) to/from byte reg
Dir addr (64K) to/from word reg
Indir addr (64K) to/from byte reg
Indir addr (16M) to/from byte reg
Reg to/from acc with carry
4
3
3
2
4
3
1
2
A,dir8
Dir byte to/from acc with carry
Indir RAM to/from acc with carry
Immediate data to/from acc with carry
1 (2)
2
1 (2)
3
ADDC;
SUBB
A,@Ri
A,#data
1
1
NOTES:
®
1. A shaded cell denotes an instruction in the MCS 51 architecture.
2. If this instruction addresses an I/O port (Px, x = 3:0), add 1 to the number of states.
A-14
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INSTRUCTION SET REFERENCE
Table A-20. Summary of Compare Instructions
Compare
CMP <dest>,<src>
dest opnd – src opnd
Binary Mode
Source Mode
Mnemonic
<dest>,<src>
Notes
Bytes States Bytes States
Rmd,Rms
Reg with reg
3
3
3
4
5
5
2
3
5
3
4
6
2
2
2
3
4
4
1
2
4
2
3
5
WRjd,WRjs
DRkd,DRks
Rm,#data
Word reg with word reg
Dword reg with dword reg
Reg with immediate data
WRj,#data16
DRk,#0data16
Word reg with immediate 16-bit data
Dword reg with zero-extended 16-bit
immediate data
CMP
DRk,#1data16
Dword reg with one-extended 16-bit
immediate data
5
6
4
5
†
†
Rm,dir8
Dir addr from byte reg
4
4
5
5
4
4
3
3
3
4
4
3
3
2
WRj,dir8
Rm,dir16
WRj,dir16
Rm,@WRj
Rm,@DRk
Dir addr from word reg
4
3
4
3
4
3
2
3
2
3
Dir addr (64K) from byte reg
Dir addr (64K) from word reg
Indir addr (64K) from byte reg
Indir addr (16M) from byte reg
†
If this instruction addresses an I/O port (Px, x = 3:0), add 1 to the number of states.
A-15
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8XC251SA, SB, SP, SQ USER’S MANUAL
Table A-21. Summary of Increment and Decrement Instructions
Increment
Increment
Increment
Decrement
Decrement
INC DPTR
INC byte
INC <dest>,<src>
DEC byte
DEC <dest>,<src>
(DPTR) ← (DPTR) + 1
byte ← byte + 1
dest opnd ← dest opnd + src opnd
byte ← byte – 1
dest opnd ← dest opnd - src opnd
Binary Mode
Source Mode
Mnemonic <dest>,<src>
Notes
Bytes States Bytes States
A
acc
1
1
2
1
3
3
3
1
1
1
1
2
2
2
2
2
2
1
1
2
Rn
Reg
dir8
Dir byte
Indir RAM
2 (2)
3
2 (2)
4
INC;
@Ri
DEC
Rm,#short
WRj,#short
DRk,#short
Byte reg by 1, 2, or 4
Word reg by 1, 2, or 4
Double word reg by 1, 2, or 4
Data pointer
2
1
2
1
4
3
INC
DPTR
1
1
NOTES:
®
1. A shaded cell denotes an instruction in the MCS 51 architecture.
2. If this instruction addresses an I/O port (Px, x = 0–3), add 2 to the number of states.
Table A-22. Summary of Multiply, Divide, and Decimal-adjust Instructions
Multiply
Divide
MUL <reg1,reg2>
MUL AB
DIV <reg1>,<reg2>
DIV AB
(2)
(B:A) = A x B
(2)
(A) = Quotient; (B) =Remainder
(2)
Decimal-adjust ACC
for Addition (BCD)
DA A
Binary Mode
Source Mode
Mnemonic <dest>,<src>
Notes
Bytes States Bytes States
AB
Multiply A and B
1
3
3
1
3
3
1
5
6
1
2
2
1
2
2
1
5
5
MUL
DIV
Rmd,Rms
WRjd,WRjs
AB
Multiply byte reg and byte reg
Multiply word reg and word reg
12
10
11
21
1
11
10
10
20
1
Rmd,Rms
WRjd,WRjs
A
Divide byte reg by byte reg
Divide word reg by word reg
Decimal adjust acc
DA
NOTES:
®
1. A shaded cell denotes an instruction in the MCS 51 architecture.
2. See section A.4, “Instruction Descriptions.”
A-16
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INSTRUCTION SET REFERENCE
Logical AND
Logical OR
Logical Exclusive OR
Clear
Complement
Rotate
ANL <dest>,<src>
ORL <dest>,<src>
XRL <dest>,<src>
CLR A
CPL A
RXX A
dest opnd ←dest opnd Λ src opnd
dest opnd ← dest opnd V src opnd
dest opnd ← dest opnd ∀ src opnd
(A) ← 0
(Ai) ← Ø(Ai)
(1)
Shift
SWAP
SXX Rm or Wj
A
(1)
A3:0 ↔ A7:4
Binary Mode
Source Mode
Mnemonic <dest>,<src>
Notes
Bytes States Bytes States
A,Rn
Reg to acc
1
2
1
2
2
3
3
3
4
5
4
4
5
5
4
4
1
1
1
1
1
1
3
3
1
2
2
2
2
2
3
2
2
3
4
3
3
4
4
3
3
1
1
1
1
1
1
2
2
2
A,dir8
Dir byte to acc
1 (3)
1 (3)
A,@Ri
Indir addr to acc
2
3
A,#data
dir8,A
Immediate data to acc
Acc to dir byte
1
1
2 (4)
2 (4)
dir8,#data
Rmd,Rms
Immediate data to dir byte
Byte reg to byte reg
Word reg to word reg
8-bit data to byte reg
16-bit data to word reg
Dir addr to byte reg
Dir addr to word reg
Dir addr (64K) to byte reg
Dir addr (64K) to word reg
Indir addr (64K) to byte reg
Indir addr (16M) to byte reg
Clear acc
3 (4)
2
3 (4)
1
2
ANL;
WRjd,WRjs
3
ORL;
Rm,#data
3
2
XRL;
WRj,#data16
Rm,dir8
4
3
3 (3)
4
2 (3)
3
WRj,dir8
Rm,dir16
WRj,dir16
Rm,@WRj
Rm,@DRk
3
2
4
3
3
2
4
3
CLR
CPL
RL
A
1
1
A
Complement acc
1
1
A
Rotate acc left
1
1
RLC
RR
A
Rotate acc left through the carry
Rotate acc right
1
1
A
1
1
RRC
A
Rotate acc right through the carry
Shift byte reg left
1
1
Rm
WRj
2
1
SLL
Shift word reg left
2
1
NOTES:
1. See section A.4, “Instruction Descriptions.”
2. A shaded cell denotes an instruction in the MCS 51 architecture.
®
3. If this instruction addresses an I/O port (Px, x = 0–3), add 1 to the number of states.
4. If this instruction addresses an I/O port (Px, x = 0–3), add 2 to the number of states.
A-17
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8XC251SA, SB, SP, SQ USER’S MANUAL
Table A-23. Summary of Logical Instructions (Continued)
Logical AND
Logical OR
Logical Exclusive OR
Clear
Complement
Rotate
ANL <dest>,<src>
dest opnd ←dest opnd Λ src opnd
ORL <dest>,<src>
XRL <dest>,<src>
CLR A
CPL A
RXX A
dest opnd ← dest opnd V src opnd
dest opnd ← dest opnd ∀ src opnd
(A) ← 0
(Ai) ← Ø(Ai)
(1)
Shift
SWAP
SXX Rm or Wj
A
(1)
A3:0 ↔ A7:4
Binary Mode
Source Mode
Mnemonic <dest>,<src>
Notes
Bytes States Bytes States
Rm
Shift byte reg right through the MSB
Shift word reg right through the MSB
Shift byte reg right
3
3
3
3
1
2
2
2
2
2
2
2
2
2
1
1
1
1
1
2
SRA
WRj
Rm
SRL
WRj
Shift word reg right
SWAP
A
Swap nibbles within the acc
NOTES:
1. See section A.4, “Instruction Descriptions.”
2. A shaded cell denotes an instruction in the MCS 51 architecture.
®
3. If this instruction addresses an I/O port (Px, x = 0–3), add 1 to the number of states.
4. If this instruction addresses an I/O port (Px, x = 0–3), add 2 to the number of states.
A-18
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INSTRUCTION SET REFERENCE
Table A-24. Summary of Move Instructions
Move (2)
MOV <dest>,<src>
destination ← src opnd
Move with Sign Extension MOVS <dest>,<src>
Move with Zero Extension MOVZ <dest>,<src>
Move Code Byte
Move to External Mem
Move from External Mem
destination ← src opnd with sign extend
destination ← src opnd with zero extend
A ← code byte
MOVC <dest>,<src>
MOVX <dest>,<src>
MOVX <dest>,<src>
external mem ← (A)
A ← source opnd in external mem
Binary Mode
Source Mode
Mnemonic
<dest>,<src>
Notes
Bytes States Bytes States
A,Rn
Reg to acc
1
2
1
2
1
2
2
2
2
3
2
3
1
2
2
3
3
3
3
4
5
5
1
2
2
2
2
2
3
3
2
3
3
3
3
2
3
3
3
2
2
2
3
4
4
2
A,dir8
Dir byte to acc
1 (3)
1 (3)
A,@Ri
Indir RAM to acc
2
3
A,#data
Immediate data to acc
Acc to reg
1
1
Rn,A
1
2
Rn,dir8
Dir byte to reg
1 (3)
2 (3)
Rn,#data
dir8,A
Immediate data to reg
Acc to dir byte
1
2
2 (3)
2 (3)
dir8,Rn
Reg to dir byte
2 (3)
3 (3)
dir8,dir8
Dir byte to dir byte
3
3
3
4
dir8,@Ri
dir8,#data
@Ri,A
Indir RAM to dir byte
Immediate data to dir byte
Acc to indir RAM
3 (3)
3
3 (3)
4
MOV
@Ri,dir8
@Ri,#data
DPTR,#data16
Rmd,Rms
WRjd,WRjs
DRkd,DRks
Rm,#data
WRj,#data16
DRk,#0data16
Dir byte to indir RAM
Immediate data to indir RAM
Load Data Pointer with a 16-bit const
Byte reg to byte reg
Word reg to word reg
Dword reg to dword reg
8-bit immediate data to byte reg
16-bit immediate data to word reg
3
4
3
4
2
2
2
1
2
1
3
2
3
2
3
2
zero-extended 16-bit immediate data
to dword reg
5
4
DRk,#1data16
one-extended 16-bit immediate data
to dword reg
5
5
4
4
NOTES:
®
1. A shaded cell denotes an instruction in the MCS 51 architecture.
2. Instructions that move bits are in Table A-26 on page A-23.
3. If this instruction addresses an I/O port (Px, x = 0–3), add 1 to the number of states.
4. External memory addressed by instructions in the MCS 51 architecture is in the region specified by
DPXL (reset value = 01H). See section 3.1.1, “Compatibility with the MCS® 51 Architecture.”
A-19
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8XC251SA, SB, SP, SQ USER’S MANUAL
Table A-24. Summary of Move Instructions (Continued)
Move (2)
MOV <dest>,<src>
destination ← src opnd
Move with Sign Extension MOVS <dest>,<src>
Move with Zero Extension MOVZ <dest>,<src>
Move Code Byte
Move to External Mem
Move from External Mem
destination ← src opnd with sign extend
destination ← src opnd with zero extend
A ← code byte
MOVC <dest>,<src>
MOVX <dest>,<src>
MOVX <dest>,<src>
external mem ← (A)
A ← source opnd in external mem
Binary Mode
Source Mode
Mnemonic
<dest>,<src>
Notes
Bytes States Bytes States
DRk,dir8
Dir addr to dword reg
4
5
4
4
5
5
4
4
4
4
4
4
5
5
4
4
4
4
4
5
5
5
5
5
5
6
6
3
4
3
3
4
4
3
3
3
3
3
3
4
4
3
3
3
3
3
4
4
4
4
4
4
5
5
DRk,dir16
Rm,dir8
Dir addr (64K) to dword reg
Dir addr to byte reg
3 (3)
4
2 (3)
3
WRj,dir8
Dir addr to word reg
Rm,dir16
Dir addr (64K) to byte reg
Dir addr (64K) to word reg
Indir addr (64K) to byte reg
Indir addr (16M) to byte reg
Indir addr(64K) to word reg
Indir addr(16M) to word reg
Byte reg to dir addr
3
2
WRj,dir16
Rm,@WRj
Rm,@DRk
WRjd,@WRjs
WRj,@DRk
dir8,Rm
4
3
2
2
4
3
4
3
5
4
4 (3)
5
3 (3)
4
dir8,WRj
Word reg to dir addr
MOV
dir16,Rm
Byte reg to dir addr (64K)
Word reg to dir addr (64K)
Byte reg to indir addr (64K)
Byte reg to indir addr (16M)
Word reg to indir addr (64K)
Word reg to indir addr (16M)
Dword reg to dir addr
4
3
dir16,WRj
@WRj,Rm
@DRk,Rm
@WRjd,WRjs
@DRk,WRj
dir8,DRk
5
4
4
3
5
4
5
4
6
5
7
6
dir16,DRk
Rm,@WRj+dis16
Dword reg to dir addr (64K)
Indir addr with disp (64K) to byte reg
7
6
6
5
WRj,@WRj+dis16 Indir addr with disp (64K) to word reg
Rm,@DRk+dis24 Indir addr with disp (16M) to byte reg
WRj,@DRk+dis24 Indir addr with disp (16M) to word reg
7
6
7
6
8
7
@WRj+dis16,Rm
Byte reg to Indir addr with disp (64K)
6
5
NOTES:
®
1. A shaded cell denotes an instruction in the MCS 51 architecture.
2. Instructions that move bits are in Table A-26 on page A-23.
3. If this instruction addresses an I/O port (Px, x = 0–3), add 1 to the number of states.
4. External memory addressed by instructions in the MCS 51 architecture is in the region specified by
DPXL (reset value = 01H). See section 3.1.1, “Compatibility with the MCS® 51 Architecture.”
A-20
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INSTRUCTION SET REFERENCE
Table A-24. Summary of Move Instructions (Continued)
Move (2)
MOV <dest>,<src>
destination ← src opnd
Move with Sign Extension MOVS <dest>,<src>
Move with Zero Extension MOVZ <dest>,<src>
Move Code Byte
Move to External Mem
Move from External Mem
destination ← src opnd with sign extend
destination ← src opnd with zero extend
A ← code byte
MOVC <dest>,<src>
MOVX <dest>,<src>
MOVX <dest>,<src>
external mem ← (A)
A ← source opnd in external mem
Binary Mode
Source Mode
Mnemonic
<dest>,<src>
Notes
Bytes States Bytes States
@WRj+dis16,WRj Word reg to Indir addr with disp (64K)
@DRk+dis24,Rm Byte reg to Indir addr with disp (16M)
5
5
5
7
7
8
4
4
4
6
6
7
MOV
@DRk+dis24,WRj Word reg to Indir addr with disp
(16M)
DRk(hi), #data16
16-bit immediate data into upper
word of dword reg
5
3
3
3
2
2
4
2
2
2
1
1
MOVH
MOVS
WRj,Rm
Byte reg to word reg with sign
extension
WRj,Rm
Byte reg to word reg with zeros
extension
MOVZ
MOVC
A,@A+DPTR
A,@A+PC
A,@Ri
Code byte relative to DPTR to acc
Code byte relative to PC to acc
1
1
1
1
1
1
6
6
4
5
4
5
1
1
2
1
1
1
6
6
5
5
4
5
External mem (8-bit addr) to acc (4)
External mem (16-bit addr) to acc (4)
Acc to external mem (8-bit addr) (4)
Acc to external mem (16-bit addr) (4)
A,@DPTR
@Ri,A
MOVX
@DPTR,A
NOTES:
®
1. A shaded cell denotes an instruction in the MCS 51 architecture.
2. Instructions that move bits are in Table A-26 on page A-23.
3. If this instruction addresses an I/O port (Px, x = 0–3), add 1 to the number of states.
4. External memory addressed by instructions in the MCS 51 architecture is in the region specified by
DPXL (reset value = 01H). See section 3.1.1, “Compatibility with the MCS® 51 Architecture.”
A-21
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Table A-25. Summary of Exchange, Push, and Pop Instructions
Exchange Contents
Exchange Digit
Push
XCH <dest>,<src>
XCHD <dest>,<src>
PUSH <src>
A ↔ src opnd
A3:0 ↔ on-chip RAM bits 3:0
SP ← SP + 1; (SP) ← src
dest ← (SP); SP ← SP – 1
Pop
POP <dest>
Binary Mode
Source Mode
Mnemonic
<dest>,<src>
Notes
Bytes States Bytes States
A,Rn
Acc and reg
1
2
1
1
3
3 (2)
4
2
2
2
2
4
3 (2)
5
XCH
A,dir8
A,@Ri
A,@Ri
Acc and dir addr
Acc and on-chip RAM (8-bit addr)
Acc and low nibble in on-chip RAM
(8-bit addr)
4
5
XCHD
dir8
Push dir byte onto stack
2
4
5
2
4
5
2
3
4
2
3
5
#data
#data16
Push immediate data onto stack
Push 16-bit immediate data onto
stack
PUSH
Rm
Push byte reg onto stack
Push word reg onto stack
Push double word reg onto stack
Pop dir byte from stack
3
3
3
2
3
3
3
4
6
2
2
2
2
2
2
2
3
5
9
3
2
4
8
WRj
DRk
dir8
Rm
10
3
Pop byte reg from stack
3
POP
WRj
DRk
Pop word reg from stack
Pop double word reg from stack
5
9
NOTES:
®
1. A shaded cell denotes an instruction in the MCS 51 architecture.
2. If this instruction addresses an I/O port (Px, x = 0–3), add 2 to the number of states.
A-22
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INSTRUCTION SET REFERENCE
Table A-26. Summary of Bit Instructions
Clear Bit
Set Bit
Complement Bit
AND Carry with Bit
AND Carry with Complement of Bit
OR Carry with Bit
ORL Carry with Complement of Bit
Move Bit to Carry
CLR bit
SETB bit
CPL bit
ANL CY,bit
ANL CY,/bit
ORL CY,bit
ORL CY,/bit
MOV CY,bit
MOV bit,CY
bit ← 0
bit ← 1
bit← Øbit
CY ← CY Λ bit
CY ← CY Λ Øbit
CY ← CY V bit
CY ← CY V Øbit
CY ← bit
Move Bit from Carry
bit ← CY
Binary Mode
Source Mode
Mnemonic <src>,<dest>
Notes
Bytes States Bytes States
CY
Clear carry
Clear dir bit
1
2
4
1
2
4
1
2
4
2
4
2
4
2
4
2
4
2
4
2
4
1
1
2
3
1
2
3
1
2
3
2
3
2
3
2
3
2
3
2
3
2
3
1
CLR
SETB
CPL
bit51
2 (2)
4
2 (2)
3
bit
Clear dir bit
CY
Set carry
1
1
bit51
Set dir bit
2 (2)
4 (2)
1
1
bit
Set dir bit
CY
Complement carry
Complement dir bit
Complement dir bit
AND dir bit to carry
AND dir bit to carry
AND complemented dir bit to carry
AND complemented dir bit to carry
OR dir bit to carry
bit51
2 (2)
4 (2)
1 (3)
3 (3)
1 (3)
3 (3)
1 (3)
3 (3)
1 (3)
3 (3)
1 (3)
3 (3)
2 (2)
4 (2)
1 (3)
2 (3)
2 (3)
1 (3)
2 (3)
2 (2)
3 (2)
bit
CY,bit51
CY,bit
CY,/bit51
CY,/bit
CY,bit51
CY,bit
CY,/bit51
CY,/bit
CY,bit51
CY,bit
bit51,CY
bit,CY
ANL
ANL/
ORL
ORL/
OR dir bit to carry
OR complemented dir bit to carry
OR complemented dir bit to carry
Move dir bit to carry
Move dir bit to carry
Move carry to dir bit
Move carry to dir bit
MOV
NOTES:
®
1. A shaded cell denotes an instruction in the MCS 51 architecture.
2. If this instruction addresses an I/O port (Px, x = 0–3), add 2 to the number of states.
3. If this instruction addresses an I/O port (Px, x = 0–3), add 1 to the number of states.
A-23
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8XC251SA, SB, SP, SQ USER’S MANUAL
Table A-27. Summary of Control Instructions
Binary Mode
Source Mode
Mnemonic <dest>,<src>
Notes
Bytes States (2) Bytes States (2)
ACALL
ECALL
addr11
@DRk
addr24
@WRj
addr16
Absolute subroutine call
Extended subroutine call, indirect
Extended subroutine call
Long subroutine call, indirect
Long subroutine call
Return from subroutine
Extended subroutine return
Return from interrupt
Absolute jump
2
3
5
3
3
1
3
1
2
5
3
3
3
2
1
2
2
3
5
9
12
14
9
2
2
4
2
3
1
2
1
2
4
2
2
3
2
1
2
2
3
4
9
11
13
8
LCALL
9
9
RET
6
6
ERET
RETI
AJMP
10
6
9
6
addr11
addr24
@DRk
@WRj
addr16
rel
3
3
Extended jump
6
5
EJMP
LJMP
Extended jump, indirect
Long jump, indirect
7
6
6
5
Long jump
4
4
SJMP
JMP
JC
Short jump (relative addr)
Jump indir relative to the DPTR
Jump if carry is set
3
3
@A+DPTR
rel
5
5
1/4
1/4
2/5
4/7
1/4
1/4
2/5
3/6
JNC
rel
Jump if carry not set
Jump if dir bit is set
bit51,rel
bit,rel
JB
Jump if dir bit of 8-bit addr location
is set
bit51,rel
bit,rel
Jump if dir bit is not set
3
5
2/5
4/7
3
4
2/5
3/6
JNB
JBC
Jump if dir bit of 8-bit addr location
is not set
bit51,rel
bit,rel
Jump if dir bit is set & clear bit
3
5
4/7
3
4
4/7
6/9
Jump if dir bit of 8-bit addr location
is set and clear bit
7/10
JZ
rel
rel
rel
rel
rel
rel
rel
Jump if acc is zero
Jump if acc is not zero
Jump if equal
2
2
3
3
3
3
3
2/5
2/5
2/5
2/5
2/5
2/5
2/5
2
2
2
2
2
2
2
2/5
2/5
1/4
1/4
1/4
1/4
1/4
JNZ
JE
JNE
JG
Jump if not equal
Jump if greater than
Jump if less than or equal
Jump if less than (signed)
JLE
JSL
NOTES:
®
1. A shaded cell denotes an instruction in the MCS 51 architecture.
2. For conditional jumps, times are given as not-taken/taken.
A-24
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INSTRUCTION SET REFERENCE
Table A-27. Summary of Control Instructions (Continued)
Binary Mode
Source Mode
Mnemonic <dest>,<src>
Notes
Bytes States (2) Bytes States (2)
JSLE
JSG
rel
rel
rel
Jump if less than or equal (signed)
Jump if greater than (signed)
3
3
3
2/5
2/5
2/5
2
2
2
1/4
1/4
1/4
JSGE
Jump if greater than or equal
(signed)
A,dir8,rel
Compare dir byte to acc and jump
if not equal
3
3
3
3
2
3
2/5
2/5
2/5
3/6
2/5
3/6
3
3
4
4
3
3
2/5
2/5
3/6
4/7
3/6
3/6
A,#data,rel
Rn,#data,rel
Compare immediate to acc and
jump if not equal
CJNE
DJNZ
Compare immediate to reg and
jump if not equal
@Ri,#data,rel Compare immediate to indir and
jump if not equal
Rn,rel
Decrement reg and jump if not
zero
dir8,rel
Decrement dir byte and jump if not
zero
TRAP
NOP
—
Jump to the trap interrupt vector
No operation
2
1
10
1
1
1
9
1
—
NOTES:
®
1. A shaded cell denotes an instruction in the MCS 51 architecture.
2. For conditional jumps, times are given as not-taken/taken.
A-25
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A.4 INSTRUCTION DESCRIPTIONS
This section describes each instruction in the MCS 251 architecture. See the note on page A-11
regarding execution times.
Table A-28 defines the symbols (—, ✓, 1, 0,?) used to indicate the effect of the instruction on the
flags in the PSW and PSW1 registers. For a conditional jump instruction, “!” indicates that a flag
influences the decision to jump.
Table A-28. Flag Symbols
Symbol
Description
—
✓
1
The instruction does not modify the flag.
The instruction sets or clears the flag, as appropriate.
The instruction sets the flag.
0
The instruction clears the flag.
?
The instruction leaves the flag in an indeterminate state.
!
For a conditional jump instruction: The state of the flag before the
instruction executes influences the decision to jump or not jump.
ACALL <addr11>
Function:
Absolute call
Description:
Unconditionally calls a subroutine at the specified address. The instruction increments the 3-
byte PC twice to obtain the address of the following instruction, then pushes bytes 0 and 1 of
the result onto the stack (byte 0 first) and increments the stack pointer twice. The destination
address is obtained by successively concatenating bits 15–11 of the incremented PC,
opcode bits 7–5, and the second byte of the instruction. The subroutine called must
therefore start within the same 2-Kbyte “page” of the program memory as the first byte of the
instruction following ACALL.
Flags:
CY
—
AC
—
OV
—
N
Z
—
—
Example:
The stack pointer (SP) contains 07H and the label "SUBRTN" is at program memory location
0345H. After executing the instruction
ACALL SUBRTN
at location 0123H, SP contains 09H; on-chip RAM locations 08H and 09H contain 25H
and 01H, respectively; and the PC contains 0345H.
Binary Mode
Source Mode
Bytes:
States:
2
9
2
9
A-26
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[Encoding]
a10 a9 a8 1
0 0 0 1
a7 a6 a5 a4
a3 a2 a1 a0
Hex Code in: Binary Mode = [Encoding]
Source Mode = [Encoding]
Operation:
ACALL
(PC) ← (PC) + 2
(SP) ← (SP) + 1
((SP)) ← (PC.7:0)
(SP) ← (SP) + 1
((SP)) ← (PC.15:8)
(PC.10:0) ← page address
ADD <dest>,<src>
Function:
Add
Description:
Adds the source operand to the destination operand, which can be a register or the accumu-
lator, leaving the result in the register or accumulator. If there is a carry out of bit 7 (CY), the
CY flag is set. If byte variables are added, and if there is a carry out of bit 3 (AC), the AC flag
is set. For addition of unsigned integers, the CY flag indicates that an overflow occurred.
If there is a carry out of bit 6 but not out of bit 7, or a carry out of bit 7 but not bit 6, the OV
flag is set. When adding signed integers, the OV flag indicates a negative number produced
as the sum of two positive operands, or a positive sum from two negative operands.
Bit 6 and bit 7 in this description refer to the most significant byte of the operand (8, 16, or 32
bit).
Four source operand addressing modes are allowed: register, direct, register-indirect, and
immediate.
Flags:
CY
AC
OV
N
Z
✓
✓
✓
✓
✓
Example:
Register 1 contains 0C3H (11000011B) and register 0 contains 0AAH (10101010B). After
executing the instruction
ADD R1,R0
register 1 contains 6DH (01101101B), the AC flag is clear, and the CY and OV flags are set.
Variations
ADD A,#data
Binary Mode
Source Mode
Bytes:
States:
2
1
2
1
[Encoding]
0 0 1 0
0 1 0 0
immed. data
A-27
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Hex Code in: Binary Mode = [Encoding]
Source Mode = [Encoding]
Operation:
ADD A,dir8
ADD
(A) ← (A) + #data
Binary Mode
Source Mode
Bytes:
States:
2
2
1†
1†
†If this instruction addresses a port (Px, x = 0–3), add 1 state.
[Encoding]
0 0 1 0 0 1 0 1 direct addr
Hex Code in: Binary Mode = [Encoding]
Source Mode = [Encoding]
Operation:
ADD A,@Ri
ADD
(A) ← (A) + (dir8)
Binary Mode
Source Mode
Bytes:
States:
1
2
2
3
[Encoding]
0 0 1 0
0 1 1 i
Hex Code in: Binary Mode = [Encoding]
Source Mode = [A5][Encoding]
Operation:
ADD A,Rn
ADD
(A) ← (A) + ((Ri))
Binary Mode
Source Mode
Bytes:
States:
1
1
2
2
[Encoding]
0 0 1 0
1 r r r
Hex Code in: Binary Mode = [Encoding]
Source Mode = [A5][Encoding]
Operation:
ADD
(A) ← (A) + (Rn)
ADD Rmd,Rms
Binary Mode
Source Mode
Bytes:
States:
3
2
2
1
A-28
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[Encoding]
0 0 1 0
1 1 0 0
s s s s
S S S S
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
ADD
(Rmd) ← (Rmd) + (Rms)
ADD WRjd,WRjs
Binary Mode
Source Mode
Bytes:
States:
3
3
2
2
[Encoding]
0 0 1 0
1 1 0 1
t t t t
T T T T
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
ADD
(WRjd) ← (WRjd) + (WRjs)
ADD DRkd,DRks
Binary Mode
Source Mode
Bytes:
States:
3
5
2
4
[Encoding]
0 0 1 0
1 1 1 1
u u u u
U U U U
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
ADD
(DRkd) ← (DRkd) + (DRks)
ADD Rm,#data
Binary Mode
Source Mode
Bytes:
States:
4
3
3
2
[Encoding]
0 0 1 0
1 1 1 0
s s s s
0 0 0 0
#data
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
ADD
(Rm) ← (Rm) + #data
A-29
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ADD WRj,#data16
Binary Mode
Source Mode
Bytes:
5
4
4
3
States:
[Encoding]
0 0 1 0
1 1 1 0
t t t t
0 1 0 0
#data hi
#data low
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
ADD
(WRj) ← (WRj) + #data16
ADD DRk,#0data16
Binary Mode
Source Mode
Bytes:
5
6
4
5
States:
[Encoding]
0 0 1 0
1 1 1 0
u u u u
1 0 0 0
#data hi
#data low
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
ADD
(DRk) ← (DRk) + #data16
ADD Rm,dir8
Binary Mode
Source Mode
Bytes:
States:
4
3
3†
2†
†If this instruction addresses a port (Px, x = 0–3), add 1 state.
[Encoding]
0 0 1 0
1 1 1 0
s s s s
0 0 0 1
direct addr
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
ADD
(Rm) ← (Rm) + (dir8)
ADD WRj,dir8
Binary Mode
Source Mode
Bytes:
States:
4
4
3
3
[Encoding]
0 0 1 0
1 1 1 0
t t t t
0 1 0 1
direct addr
A-30
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INSTRUCTION SET REFERENCE
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding
Operation:
ADD
(WRj) ← (WRj) + (dir8)
ADD Rm,dir16
Binary Mode
Source Mode
Bytes:
5
3
4
2
States:
[Encoding]
0 0 1 0
1 1 1 0
s s s s
0 0 1 1
direct addr
direct add
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
ADD
(Rm) ← (Rm) + (dir16)
ADD WRj,dir16
Binary Mode
Source Mode
Bytes:
5
4
4
3
States:
[Encoding]
0 0 1 0
1 1 1 0
t t t t
0 1 1 1
direct addr
direct addr
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
ADD
(WRj) ← (WRj) + (dir16)
ADD Rm,@WRj
Binary Mode
Source Mode
Bytes:
4
3
3
2
States:
[Encoding]
0 0 1 0
1 1 1 0
t t t t
1 0 0 1
s s s s
0 0 0 0
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
ADD
(Rm) ← (Rm) + ((WRj))
A-31
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ADD Rm,@DRk
Binary Mode
Source Mode
Bytes:
4
4
3
3
States:
[Encoding]
0 0 1 0
1 1 1 0
u u u u
1 0 1 1
s s s s
0 0 0 0
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
ADD
(Rm) ← (Rm) + ((DRk))
ADDC A,<src>
Function:
Add with carry
Description:
Simultaneously adds the specified byte variable, the CY flag, and the accumulator contents,
leaving the result in the accumulator. If there is a carry out of bit 7 (CY), the CY flag is set; if
there is a carry out of bit 3 (AC), the AC flag is set. When adding unsigned integers, the CY
flag indicates that an overflow occurred.
If there is a carry out of bit 6 but not out of bit 7, or a carry out of bit 7 but not bit 6, the OV
flag is set. When adding signed integers, the OV flag indicates a negative number produced
as the sum of two positive operands, or a positive sum from two negative operands.
Bit 6 and bit 7 in this description refer to the most significant byte of the operand (8, 16, or 32
bit)
Four source operand addressing modes are allowed: register, direct, register-indirect, and
immediate.
Flags:
CY
AC
OV
N
Z
✓
✓
✓
✓
✓
Example:
The accumulator contains 0C3H (11000011B), register 0 contains 0AAH (10101010B), and
the CY flag is set. After executing the instruction
ADDC A,R0
the accumulator contains 6EH (01101110B), the AC flag is clear, and the CY and OV flags
are set.
Variations
ADDC A,#data
Binary Mode
Source Mode
Bytes:
States:
2
1
2
1
A-32
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[Encoding]
0 0 1 1
0 1 0 0
immed. data
Hex Code in: Binary Mode = [Encoding]
Source Mode = [Encoding]
Operation:
ADDC
(A) ← (A) + (CY) + #data
ADDC A,dir8
Binary Mode
Source Mode
Bytes:
States:
2
2
1†
1†
†If this instruction addresses a port (Px, x = 0–3), add 1 state.
[Encoding]
0 0 1 1 0 1 0 1 direct addr
Hex Code in: Binary Mode = [Encoding]
Source Mode = [Encoding]
Operation:
ADDC
(A) ← (A) + (CY) + (dir8)
ADDC A,@Ri
Binary Mode
Source Mode
Bytes:
States:
1
2
2
3
[Encoding]
0 0 1 1
0 1 1 i
Hex Code in: Binary Mode = [Encoding]
Source Mode = [A5][Encoding]
Operation:
ADDC A,Rn
ADDC
(A) ← (A) + (CY) + ((Ri))
Binary Mode
Source Mode
Bytes:
States:
1
1
2
2
[Encoding]
0 0 1 1
1 r r r
Hex Code in: Binary Mode = [Encoding]
Source Mode = [A5][Encoding]
Operation:
ADDC
(A) ← (A) + (CY) + (Rn)
A-33
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AJMP addr11
Function:
Absolute jump
Description:
Transfers program execution to the specified address, which is formed at run time by
concatenating the upper five bits of the PC (after incrementing the PC twice), opcode bits 7–
5, and the second byte of the instruction. The destination must therefore be within the same
2-Kbyte “page” of program memory as the first byte of the instruction following AJMP.
Flags:
CY
—
AC
—
OV
—
N
Z
—
—
Example:
The label "JMPADR" is at program memory location 0123H. After executing the instruction
AJMP JMPADR
at location 0345H, the PC contains 0123H.
Binary Mode
Source Mode
Bytes:
States:
2
3
2
3
[Encoding]
a10 a9 a8 0
0 0 0 1
a7 a6 a5 a4
a3 a2 a1 a0
Hex Code in: Binary Mode = [Encoding]
Source Mode = [Encoding]
Operation:
AJMP
(PC) ← (PC) + 2
(PC.10:0) ← page address
ANL <dest>,<src>
Function:
Logical-AND
Description:
Performs the bitwise logical-AND (Λ) operation between the specified variables and stores
the results in the destination variable.
The two operands allow 10 addressing mode combinations. When the destination is the
register or accumulator, the source can use register, direct, register-indirect, or immediate
addressing; when the destination is a direct address, the source can be the accumulator or
immediate data.
Note: When this instruction is used to modify an output port, the value used as the original
port data is read from the output data latch, not the input pins.
Flags:
CY
—
AC
—
OV
—
N
Z
✓
✓
A-34
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Example:
Register 1 contains 0C3H (11000011B) and register 0 contains 55H (01010101B). After
executing the instruction
ANL R1,R0
register 1 contains 41H (01000001B).
When the destination is a directly addressed byte, this instruction clears combinations of bits
in any RAM location or hardware register. The mask byte determining the pattern of bits to
be cleared would either be an immediate constant contained in the instruction or a value
computed in the register or accumulator at run time. The instruction
ANL P1,#01110011B
clears bits 7, 3, and 2 of output port 1.
Variations
ANL dir8,A
Binary Mode
Source Mode
Bytes:
States:
2
2
2†
2†
†If this instruction addresses a port (Px, x = 0–3), add 2 states.
[Encoding]
0 1 0 1 0 0 1 0 direct addr
Hex Code in: Binary Mode = [Encoding]
Source Mode = [Encoding]
Operation:
ANL
(dir8) ← (dir8) Λ (A)
ANL dir8,#data
Binary Mode
Source Mode
Bytes:
States:
3
3
3†
3†
†If this instruction addresses a port (Px, x = 0–3), add 1 state.
[Encoding]
0 1 0 1 0 0 1 1 direct addr immed. data
Hex Code in: Binary Mode = [Encoding]
Source Mode = [Encoding]
Operation:
ANL
(dir8) ← (dir8) Λ #data
ANL A,#data
Binary Mode
Source Mode
Bytes:
States:
2
1
2
1
[Encoding]
0 1 0 1
0 1 0 0
immed. data
A-35
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Hex Code in: Binary Mode = [Encoding]
Source Mode = [Encoding]
Operation:
ANL A,dir8
ANL
(A) ← (A) Λ #data
Binary Mode
Source Mode
Bytes:
States:
2
2
1†
1†
†If this instruction addresses a port (Px, x = 0–3), add 1 state.
[Encoding]
0 1 0 1 0 1 0 1 direct addr
Hex Code in: Binary Mode = [Encoding]
Source Mode = [Encoding]
Operation:
ANL A,@Ri
ANL
(A) ← (A) Λ (dir8)
Binary Mode
Source Mode
Bytes:
States:
1
2
2
3
[Encoding]
0 1 0 1
0 1 1 i
Hex Code in: Binary Mode = [Encoding]
Source Mode = [A5][Encoding]
Operation:
ANL A,Rn
ANL
(A) ← (A) Λ ((Ri))
Binary Mode
Source Mode
Bytes:
States:
1
1
2
2
[Encoding]
0 1 0 1
1 r r r
Hex Code in: Binary Mode = [Encoding]
Source Mode = [A5][Encoding]
Operation:
ANL
(A) ← (A) Λ (Rn)
ANL Rmd,Rms
Binary Mode
Source Mode
Bytes:
States:
3
2
2
1
A-36
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[Encoding]
0 1 0 1
1 1 0 0
s s s s
S S S S
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
ANL
(Rmd) ← (Rmd) Λ (Rms)
ANL WRjd,WRjs
Binary Mode
Source Mode
Bytes:
States:
3
3
2
2
[Encoding]
0 1 0 1
1 1 0 1
t t t t
T T T T
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
ANL
(WRjd) ← (WRjd) Λ (WRjs)
ANL Rm,#data
Binary Mode
Source Mode
Bytes:
States:
4
3
3
2
[Encoding]
0 1 0 1
1 1 1 0
s s s s
0000
#data
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
ANL
(Rm) ← (Rm) Λ #data
ANL WRj,#data16
Binary Mode
Source Mode
Bytes:
5
4
4
3
States:
[Encoding]
0 1 0 1
1 1 1 0
t t t t
0 1 0 0
#data hi
#data low
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
ANL
(WRj) ← (WRj) Λ #data16
A-37
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ANL Rm,dir8
Binary Mode
Source Mode
Bytes:
States:
4
3
3†
2†
†If this instruction addresses a port (Px, x = 0–3), add 1 state.
[Encoding]
0 1 0 1 1 1 1 0 s s s s 0 0 0 1
direct addr
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
ANL
(Rm) ← (Rm) Λ (dir8)
ANL WRj,dir8
Binary Mode
Source Mode
Bytes:
States:
4
4
3
3
[Encoding]
0 1 0 1
1 1 10
t t t t
0 1 0 1
direct addr
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
ANL
(WRj) ← (WRj) Λ (dir8)
ANL Rm,dir16
Binary Mode
Source Mode
Bytes:
5
3
4
2
States:
[Encoding]
0 1 0 1
1 1 1 0
s s s s
0 0 1 1
direct
direct
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
ANL
(Rm) ← (Rm) Λ (dir16)
ANL WRj,dir16
Binary Mode
Source Mode
Bytes:
States:
5
4
4
3
A-38
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[Encoding]
0 1 0 1
1 1 1 0
t t t t
0 1 1 1
direct
direct
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
ANL
(WRj) ← (WRj) Λ (dir16)
ANL Rm,@WRj
Binary Mode
Source Mode
Bytes:
4
3
3
2
States:
[Encoding]
0 1 0 1
1 1 1 0
t t t t
1 0 0 1
s s s s
0 0 0 0
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
ANL
(Rm) ← (Rm) Λ ((WRj))
ANL Rm,@DRk
Binary Mode
Source Mode
Bytes:
4
4
3
3
States:
[Encoding]
0 1 0 1
1 1 1 0
u u u u
1 0 1 1
s s s s
0 0 0 0
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
ANL
(Rm) ← (Rm) Λ ((DRk))
ANL CY,<src–bit>
Function:
Logical-AND for bit variables
Description:
If the Boolean value of the source bit is a logical 0, clear the CY flag; otherwise leave the CY
flag in its current state. A slash ("/") preceding the operand in the assembly language
indicates that the logical complement of the addressed bit is used as the source value, but
the source bit itself is not affected.
Only direct addressing is allowed for the source operand.
A-39
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Flags:
CY
AC
—
OV
—
N
Z
✓
—
—
Example:
Set the CY flag if, and only if, P1.0 = 1, ACC. 7 = 1, and OV = 0:
MOV CY,P1.0 ;Load carry with input pin state
ANL CY,ACC.7 ;AND carry with accumulator bit 7
ANL CY,/OV
;AND with inverse of overflow flag
ANL CY,bit51
Binary Mode
Source Mode
Bytes:
States:
2
2
1†
1†
†If this instruction addresses a port (Px, x = 0–3), add 1 state.
[Encoding]
1 0 0 0 0 0 1 0 bit addr
Hex Code in: Binary Mode = [Encoding]
Source Mode = [Encoding]
Operation:
ANL
(CY) ← (CY) Λ (bit51)
ANL CY,/bit51
Binary Mode
Source Mode
Bytes:
States:
2
2
1†
1†
†If this instruction addresses a port (Px, x = 0–3), add 1 state.
[Encoding]
1 0 1 1 0 0 0 0 bit addr
Hex Code in: Binary Mode = [Encoding]
Source Mode = [Encoding]
Operation:
ANL CY,bit
ANL
(CY) ← (CY) Λ Ø (bit51)
Binary Mode
Source Mode
Bytes:
States:
4
3
3†
2†
†If this instruction addresses a port (Px, x = 0–3), add 1 state.
[Encoding]
1 0 1 0
1 0 0 1
1 0 0 0
0
y y y
dir addr
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
A-40
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Operation:
ANL CY,/bit
ANL
(CY) ← (CY) Λ (bit)
Binary Mode
Source Mode
Bytes:
States:
4
3
3†
2†
†If this instruction addresses a port (Px, x = 0–3), add 1 state.
[Encoding]
1 0 1 0
1 0 0 1
1 1 1 1
0
y y y
dir addr
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
ANL
(CY) ← (CY) Λ Ø (bit)
CJNE <dest>,<src>,rel
Function:
Compare and jump if not equal.
Description:
Compares the magnitudes of the first two operands and branches if their values are not
equal. The branch destination is computed by adding the signed relative displacement in the
last instruction byte to the PC, after incrementing the PC to the start of the next instruction. If
the unsigned integer value of <dest-byte> is less than the unsigned integer value of <src-
byte>, the CY flag is set. Neither operand is affected.
The first two operands allow four addressing mode combinations: the accumulator may be
compared with any directly addressed byte or immediate data, and any indirect RAM
location or working register can be compared with an immediate constant.
Flags:
CY
AC
—
OV
—
N
Z
✓
✓
✓
Example:
The accumulator contains 34H and R7 contains 56H. After executing the first instruction in
the sequence
CJNE
. . .
R7,#60H,NOT_EQ
;
. . .
;R7 = 60H
NOT_EQ:
;
JC
REQ_LOW
. . .
; IF R7 < 60H
;R7 > 60H
. . .
the CY flag is set and program execution continues at label NOT_EQ. By testing the CY flag,
this instruction determines whether R7 is greater or less than 60H.
If the data being presented to Port 1 is also 34H, then executing the instruction,
WAIT: CJNE A,P1,WAIT
clears the CY flag and continues with the next instruction in the sequence, since the
accumulator does equal the data read from P1. (If some other value was being input on P1,
the program loops at this point until the P1 data changes to 34H.)
A-41
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Variations
CJNE A,#data,rel
Binary Mode
Source Mode
Not Taken
Not Taken
Taken
Taken
Bytes:
States:
3
2
3
5
3
2
3
5
[Encoding]
1 0 1 1
0 1 0 0
immed. data
rel. addr
Hex Code in: Binary Mode = [Encoding]
Source Mode = [Encoding]
Operation:
(PC) ← (PC) + 3
IF (A) ≠ #data
THEN
(PC) ← (PC) + relative offset
IF (A) < #data
THEN
(CY) ← 1
ELSE
(CY) ← 0
CJNE A,dir8,rel
Binary Mode
Source Mode
Not Taken
Not Taken
Taken
Taken
Bytes:
States:
3
3
3
6
3
3
3
6
[Encoding]
1 0 1 1
0 1 0 1
direct addr
rel. addr
Hex Code in: Binary Mode = [Encoding]
Source Mode = [Encoding]
Operation:
(PC) ← (PC) + 3
IF (A) ≠ dir8
THEN
(PC) ← (PC) + relative offset
IF (A) < dir8
THEN
(CY) ← 1
ELSE
(CY) ← 0
CJNE @Ri,#data,rel
Binary Mode
Source Mode
Not Taken
Taken
Not Taken
Taken
Bytes:
States:
3
3
6
4
4
4
7
3
A-42
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INSTRUCTION SET REFERENCE
[Encoding]
1 0 1 1
0 1 1 i
immed. data
rel. addr
Hex Code in: Binary Mode = [Encoding]
Source Mode = [A5][Encoding]
Operation:
(PC) ← (PC) + 3
IF ((Ri)) ≠ #data
THEN
(PC) ← (PC) + relative offset
IF ((Ri)) < #data
THEN
(CY) ← 1
ELSE
(CY) ← 0
CJNE Rn,#data,rel
Binary Mode
Not Taken
Source Mode
Taken
Not Taken
Taken
Bytes:
States:
3
2
3
5
4
3
4
6
[Encoding]
1 01 1
1 r r r
immed. data
rel. addr
Hex Code in: Binary Mode = [Encoding]
Source Mode = [A5][Encoding]
Operation:
(PC) ← (PC) + 3
IF (Rn) ≠ #data
THEN
(PC) ← (PC) + relative offset
IF (Rn) < #data
THEN
(CY) ← 1
ELSE
(CY) ← 0
CLR A
Function:
Clear accumulator
Description:
Flags:
Clears the accumulator (i.e., resets all bits to zero).
CY
—
AC
—
OV
—
N
Z
✓
✓
Example:
The accumulator contains 5CH (01011100B). The instruction
CLR A
clears the accumulator to 00H (00000000B).
A-43
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Binary Mode
Source Mode
Bytes:
States:
1
1
1
1
[Encoding]
1 1 1 0
0 1 0 0
Hex Code in: Binary Mode = [Encoding]
Source Mode = [Encoding]
Operation:
CLR
(A) ← 0
CLR bit
Function:
Description:
Flags:
Clear bit
Clears the specified bit. CLR can operate on the CY flag or any directly addressable bit.
Only for instructions with CY as the operand.
CY
AC
—
OV
—
N
Z
✓
—
—
Example:
Port 1 contains 5DH (01011101B). After executing the instruction
CLR P1.2
port 1 contains 59H (01011001B).
Variations
CLR bit51
Binary Mode
Source Mode
Bytes:
States:
4
3
2†
2†
†If this instruction addresses a port (Px, x = 0–3), add 2 states.
[Encoding]
1 1 0 0 0 0 1 0 Bit addr
Hex Code in: Binary Mode = [Encoding]
Source Mode = [Encoding]
Operation:
CLR CY
CLR
(bit51) ← 0
Binary Mode
Source Mode
Bytes:
States:
1
1
1
1
[Encoding]
1 1 0 0
0 0 1 1
A-44
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INSTRUCTION SET REFERENCE
Hex Code in: Binary Mode = [Encoding]
Source Mode = [Encoding]
Operation:
CLR bit
CLR
(CY) ← 0
Binary Mode
Source Mode
Bytes:
States:
4
4
4†
3†
†If this instruction addresses a port (Px, x = 0–3), add 2 states.
[Encoding]
1 0 1 0
1 0 0 1
1 1 0 0
0
y y y
dir addr
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
CLR
(bit) ← 0
CMP <dest>,<src>
Function:
Compare
Description:
Subtracts the source operand from the destination operand. The result is not stored in the
destination operand. If a borrow is needed for bit 7, the CY (borrow) flag is set; otherwise it is
clear.
When subtracting signed integers, the OV flag indicates a negative result when a negative
value is subtracted from a positive value, or a positive result when a positive value is
subtracted from a negative value.
Bit 7 in this description refers to the most significant byte of the operand (8, 16, or 32 bit)
The source operand allows four addressing modes: register, direct, immediate and indirect.
Flags:
CY
AC
OV
N
Z
✓
✓
✓
✓
✓
Example:
Register 1 contains 0C9H (11001001B) and register 0 contains 54H (01010100B). The
instruction
CMP R1,R0
clears the CY and AC flags and sets the OV flag.
Variations
CMP Rmd,Rms
Binary Mode
Source Mode
Bytes:
States:
3
2
2
1
A-45
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[Encoding]
1 0 1 1
1 1 0 0
s s s s
S S S S
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
CMP
(Rmd) – (Rms)
CMP WRjd,WRjs
Binary Mode
Source Mode
Bytes:
States:
3
3
2
2
[Encoding]
1 0 1 1
1 1 1 0
t t t t
T T T T
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
CMP
(WRjd) – (WRjs)
CMP DRkd,DRks
Binary Mode
Source Mode
Bytes:
States:
3
5
2
4
[Encoding]
1 0 1 1
1 1 1 1
u u u u
UUUU
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
CMP
(DRkd) – (DRks)
CMP Rm,#data
Binary Mode
Source Mode
Bytes:
States:
4
3
3
2
[Encoding]
1 0 1 1
1 1 1 0
s s s s
0 0 0 0
# data
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
CMP
(Rm) – #data
A-46
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INSTRUCTION SET REFERENCE
CMP WRj,#data16
Binary Mode
Source Mode
Bytes:
5
4
4
3
States:
[Encoding]
1 0 1 1
1 1 1 0
t t t t
0 1 0 0
1 0 0 0
1 1 0 0
#data hi
#data hi
#data hi
#data low
#data low
#data hi
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
CMP
(WRj) – #data16
CMP DRk,#0data16
Binary Mode
Source Mode
Bytes:
5
6
4
5
States:
[Encoding]
1 0 1 1
1 1 1 0
u u u u
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
CMP
(DRk) – #0data16
CMP DRk,#1data16
Binary Mode
Source Mode
Bytes:
5
6
4
5
States:
[Encoding]
1 0 1 1
1 1 1 0
u u u u
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
CMP
(DRk) – #1data16
CMP Rm,dir8
Binary Mode
Source Mode
Bytes:
States:
4
3
3†
2†
†If this instruction addresses a port (Px, x = 0–3), add 1 state.
A-47
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[Encoding]
1 0 1 1
1 1 1 0
s s s s
0001
dir addr
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
CMP
(Rm) – (dir8)
CMP WRj,dir8
Binary Mode
Source Mode
Bytes:
States:
4
4
3
3
[Encoding]
1 0 1 1
1 1 10
t t t t
0 1 0 1
dir addr
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
CMP
(WRj) – (dir8)
CMP Rm,dir16
Binary Mode
Source Mode
Bytes:
5
3
4
2
States:
[Encoding]
1 0 1 1
1 1 1 0
s s s s
0 0 1 1
dir addr
dir addr
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
CMP
(Rm) – (dir16)
CMP WRj,dir16
Binary Mode
Source Mode
Bytes:
5
4
4
3
States:
[Encoding]
1 0 1 1
1 1 1 0
t t t t
0 1 1 1
dir addr
dir addr
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
CMP
(WRj) – (dir16)
A-48
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INSTRUCTION SET REFERENCE
CMP Rm,@WRj
Binary Mode
Source Mode
Bytes:
4
3
3
2
States:
[Encoding]
1 0 1 1
1 1 1 0
t t t t
1 0 0 1
s s s s
0 0 0 0
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
CMP
(Rm) – ((WRj))
CMP Rm,@DRk
Binary Mode
Source Mode
Bytes:
4
4
3
3
States:
[Encoding]
1 0 1 1
1 1 1 0
u u u u
1 0 1 1
s s s s
0 0 0 0
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
CMP
(Rm) – ((DRk))
CPL A
Function:
Description:
Complement accumulator
Logically complements (Ø) each bit of the accumulator (one's complement). Clear bits are
set and set bits are cleared.
Flags:
CY
—
AC
—
OV
—
N
Z
✓
✓
Example:
The accumulator contains 5CH (01011100B). After executing the instruction
CPL A
the accumulator contains 0A3H (10100011B).
Binary Mode
Source Mode
Bytes:
States:
1
1
1
1
[Encoding]
1 1 1 1
0 1 0 0
A-49
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Hex Code in: Binary Mode = [Encoding]
Source Mode = [Encoding]
Operation:
CPL bit
CPL
(A) ← Ø(A)
Function:
Complement bit
Description:
Complements (Ø) the specified bit variable. A clear bit is set, and a set bit is cleared. CPL
can operate on the CY or any directly addressable bit.
Note: When this instruction is used to modify an output pin, the value used as the original
data is read from the output data latch, not the input pin.
Flags:
Only for instructions with CY as the operand.
CY
AC
—
OV
—
N
Z
✓
—
—
Example:
Port 1 contains 5BH (01011101B). After executing the instruction sequence
CPL P1.1
CPL P1.2
port 1 contains 5BH (01011011B).
Variations
CPL bit51
Binary Mode
Source Mode
Bytes:
States:
2
2
2†
2†
†If this instruction addresses a port (Px, x = 0–3), add 2 states.
[Encoding]
1 0 1 1 0 0 1 0 bit addr
Hex Code in: Binary Mode = [Encoding]
Source Mode = [Encoding]
Operation:
CPL CY
CPL
(bit51) ← Ø(bit51)
Binary Mode
Source Mode
Bytes:
States:
1
1
1
1
[Encoding]
1 0 1 1
0 0 1 1
Hex Code in: Binary Mode = [Encoding]
Source Mode = [Encoding]
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Operation:
CPL bit
CPL
(CY) ← Ø(CY)
Binary Mode
Source Mode
Bytes:
States:
4
3
4†
3†
†If this instruction addresses a port (Px, x = 0–3), add 2 states.
[Encoding]
1 0 1 0
1 0 0 1
1 0 1 1
0
y y y
dir addr
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
CPL
(bit) ← Ø(bit)
DA A
Function:
Description:
Decimal-adjust accumulator for addition
Adjusts the 8-bit value in the accumulator that resulted from the earlier addition of two
variables (each in packed-BCD format), producing two 4-bit digits. Any ADD or ADDC
instruction may have been used to perform the addition.
If accumulator bits 3:0 are greater than nine (XXXX1010–XXXX1111), or if the AC flag is set,
six is added to the accumulator, producing the proper BCD digit in the low nibble. This
internal addition sets the CY flag if a carry out of the lowest 4 bits propagated through all
higher bits, but it does not clear the CY flag otherwise.
If the CY flag is now set, or if the upper four bits now exceed nine (1010XXXX–1111XXXX),
these four bits are incremented by six, producing the proper BCD digit in the high nibble.
Again, this sets the CY flag if there was a carry out of the upper four bits, but does not clear
the carry. The CY flag thus indicates if the sum of the original two BCD variables is greater
than 100, allowing multiple-precision decimal addition. The OV flag is not affected.
All of this occurs during one instruction cycle. Essentially, this instruction performs the
decimal conversion by adding 00H, 06H, 60H, or 66H to the accumulator, depending on
initial accumulator and PSW conditions.
Note: DA A cannot simply convert a hexadecimal number in the accumulator to BCD
notation, nor does DA A apply to decimal subtraction.
Flags:
CY
AC
—
OV
—
N
Z
✓
✓
✓
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Example:
The accumulator contains 56H (01010110B), which represents the packed BCD digits of the
decimal number 56. Register 3 contains 67H (01100111B), which represents the packed
BCD digits of the decimal number 67. The CY flag is set. After executing the instruction
sequence
ADDC A,R3
DA A
the accumulator contains 0BEH (10111110) and the CY and AC flags are clear. The
Decimal Adjust instruction then alters the accumulator to the value 24H (00100100B),
indicating the packed BCD digits of the decimal number 24, the lower two digits of the
decimal sum of 56, 67, and the carry-in. The CY flag is set by the Decimal Adjust instruction,
indicating that a decimal overflow occurred. The true sum of 56, 67, and 1 is 124.
BCD variables can be incremented or decremented by adding 01H or 99H. If the
accumulator contains 30H (representing the digits of 30 decimal), then the instruction
sequence,
ADD A,#99H
DA A
leaves the CY flag set and 29H in the accumulator, since 30 + 99 = 129. The low byte of the
sum can be interpreted to mean 30 – 1 = 29.
Binary Mode
Source Mode
Bytes:
States:
1
1
1
1
[Encoding]
1 1 0 1
0 1 0 0
Hex Code in: Binary Mode = [Encoding]
Source Mode = [Encoding]
Operation:
DA
(Contents of accumulator are BCD)
IF
[[(A.3:0) > 9] V [(AC) = 1]]
THEN (A.3:0) ← (A.3:0) + 6
AND
IF
[[(A.7:4) > 9] V [(CY) = 1]]
THEN (A.7:4) ← (A.7:4) + 6
DEC byte
Function:
Description:
Decrement
Decrements the specified byte variable by 1. An original value of 00H underflows to 0FFH.
Four operands addressing modes are allowed: accumulator, register, direct, or register-
indirect.
Note: When this instruction is used to modify an output port, the value used as the original
port data is read from the output data latch, not the input pins.
Flags:
CY
—
AC
—
OV
—
N
Z
✓
✓
A-52
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Example:
Register 0 contains 7FH (01111111B). On-chip RAM locations 7EH and 7FH contain 00H
and 40H, respectively. After executing the instruction sequence
DEC @R0
DEC R0
DEC @R0
register 0 contains 7EH and on-chip RAM locations 7EH and 7FH are set to 0FFH and 3FH,
respectively.
Variations
DEC A
Binary Mode
Source Mode
Bytes:
States:
1
1
1
1
[Encoding]
0 0 0 1
0 1 0 0
Hex Code in: Binary Mode = [Encoding]
Source Mode = [Encoding]
Operation:
DEC dir8
DEC
(A) ← (A) – 1
Binary Mode
Source Mode
Bytes:
States:
2
2
2†
2†
†If this instruction addresses a port (Px, x = 0–3), add 2 states.
[Encoding]
0 0 0 1 0 1 0 1 dir addr
Hex Code in: Binary Mode = [Encoding]
Source Mode = [Encoding]
Operation:
DEC @Ri
DEC
(dir8) ← (dir8) – 1
Binary Mode
Source Mode
Bytes:
States:
1
3
2
4
[Encoding]
0 0 0 1
0 1 1 i
Hex Code in: Binary Mode = [Encoding]
Source Mode = [A5][Encoding]
Operation:
DEC
((Ri)) ← ((Ri)) – 1
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DEC Rn
Binary Mode
Source Mode
Bytes:
States:
1
1
2
2
[Encoding]
0 0 0 1
1 r r r
Hex Code in: Binary Mode = [Encoding]
Source Mode = [A5][Encoding]
Operation:
DEC
(Rn) ← (Rn) – 1
DEC <dest>,<src>
Function:
Decrement
Description:
Decrements the specified variable at the destination operand by 1, 2, or 4. An original value
of 00H underflows to 0FFH.
Flags:
CY
—
AC
—
OV
—
N
Z
✓
✓
Example:
Register 0 contains 7FH (01111111B). After executing the instruction sequence
DEC R0,#1
register 0 contains 7EH.
Variations
DEC Rm,#short
Binary Mode
Source Mode
Bytes:
States:
3
2
2
1
[Encoding]
0 0 0 1
1 0 1 1
s s s s
0 1
v v
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
DEC
(Rm) ← (Rm) – #short
DEC WRj,#short
Binary Mode
Source Mode
Bytes:
States:
3
2
2
1
A-54
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[Encoding]
0 0 0 1
1 0 1 1
t t t t
0 1
v v
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
DEC
(WRj) ← (WRj) – #short
DEC DRk,#short
Binary Mode
Source Mode
Bytes:
States:
3
5
2
4
[Encoding]
0 0 0 1
1 0 1 1
u u u u
1 1
v v
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
DEC
(DRk) ← (DRk) – #short
DIV <dest>,<src>
Function:
Divide
Description:
Divides the unsigned integer in the register by the unsigned integer operand in register
addressing mode and clears the CY and OV flags.
For byte operands (<dest>,<src> = Rmd,Rms) the result is 16 bits. The 8-bit quotient is
stored in the higher byte of the word where Rmd resides; the 8-bit remainder is stored in the
lower byte of the word where Rmd resides. For example: Register 1 contains 251 (0FBH or
11111011B) and register 5 contains 18 (12H or 00010010B). After executing the instruction
DIV R1,R5
register 1 contains 13 (0DH or 00001101B); register 0 contains 17 (11H or 00010001B),
since 251 = (13 X 18) + 17; and the CY and OV bits are clear (see Flags).
Flags:
The CY flag is cleared. The N flag is set if the MSB of the quotient is set. The Z flag is set if
the quotient is zero.
CY
0
AC
—
OV
N
Z
✓
✓
✓
Exception: if <src> contains 00H, the values returned in both operands are undefined; the
CY flag is cleared, OV flag is set, and the rest of the flags are undefined.
CY
0
AC
—
OV
1
N
?
Z
?
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Variations
DIV Rmd Rms
Binary Mode
Source Mode
Bytes:
States:
3
2
11
10
[Encoding]
1 0 0 0
1 1 0 0
s s s s
S S S S
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
DIV (8-bit operands)
(Rmd) ← remainder (Rmd) / (Rms) if <dest> md = 0,2,4,..,14
(Rmd+1) ← quotient (Rmd) / (Rms)
(Rmd–1) ← remainder (Rmd) / (Rms) if <dest> md = 1,3,5,..,15
(Rmd) ← quotient (Rmd) / (Rms)
DIV WRjd,WRjs
Binary Mode
Source Mode
Bytes:
States:
3
2
22
21
[Encoding]
1 0 0 0
1 1 0 1
t t t t
T T T T
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
DIV (16-bit operands)
(WRjd) ← remainder (WRjd) / (WRjs) if <dest> jd = 0, 4, 8, ... 28
(WRjd+2) ← quotient (WRjd) / (WRjs)
(WRjd–2) ← remainder (WRjd) / (WRjs) if <dest> jd = 2, 6, 10, ... 30
(WRjd) ← quotient (WRjd) / (WRjs)
For word operands (<dest>,<src> = WRjd,WRjs) the 16-bit quotient is in WR(jd+2), and the
16-bit remainder is in WRjd. For example, for a destination register WR4, assume the
quotient is 1122H and the remainder is 3344H. Then, the results are stored in these register
file locations:
Location
Contents
4
5
6
7
33H
44H
11H
22H
DIV AB
Function:
Description:
Divide
Divides the unsigned 8-bit integer in the accumulator by the unsigned 8-bit integer in register
B. The accumulator receives the integer part of the quotient; register B receives the integer
remainder. The CY and OV flags are cleared.
A-56
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Exception: if register B contains 00H, the values returned in the accumulator and register B
are undefined; the CY flag is cleared and the OV flag is set.
Flags:
CY
0
AC
—
OV
N
Z
✓
✓
✓
For division by zero:
CY
0
AC
—
OV
1
N
?
Z
?
Hex Code in: Binary Mode = [Encoding]
Source Mode = [Encoding]
Example:
The accumulator contains 251 (0FBH or 11111011B) and register B contains 18 (12H or
00010010B). After executing the instruction
DIV AB
the accumulator contains 13 (0DH or 00001101B); register B contains 17 (11H or
00010001B), since 251 = (13 X 18) + 17; and the CY and OV flags are clear.
Binary Mode
Source Mode
Bytes:
States:
1
1
10
10
[Encoding]
1 0 0 0
0 1 0 0
Hex Code in: Binary Mode = [Encoding]
Source Mode = [Encoding]
Operation:
DIV
(A) ← quotient (A)/(B)
(B) ← remainder (A)/(B)
DJNZ <byte>,<rel–addr>
Function:
Decrement and jump if not zero
Description:
Decrements the specified location by 1 and branches to the address specified by the second
operand if the resulting value is not zero. An original value of 00H underflows to 0FFH. The
branch destination is computed by adding the signed relative-displacement value in the last
instruction byte to the PC, after incrementing the PC to the first byte of the following
instruction.
The location decremented may be a register or directly addressed byte.
Note: When this instruction is used to modify an output port, the value used as the original
port data is read from the output data latch, not the input pins.
Flags:
CY
—
AC
—
OV
—
N
Z
✓
✓
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Example:
The on-chip RAM locations 40H, 50H, and 60H contain 01H, 70H, and 15H, respectively.
After executing the following instruction sequence
DJNZ 40H,LABEL1
DJNZ 50H,LABEL2
DJNZ 60H,LABEL
on-chip RAM locations 40H, 50H, and 60H contain 00H, 6FH, and 14H, respectively, and
program execution continues at label LABEL2. (The first jump was not taken because the
result was zero.)
This instruction provides a simple way of executing a program loop a given number of times,
or for adding a moderate time delay (from 2 to 512 machine cycles) with a single instruction.
The instruction sequence,
MOV R2,#8
TOGGLE: CPL P1.7
DJNZ R2,TOGGLE
toggles P1.7 eight times, causing four output pulses to appear at bit 7 of output Port 1. Each
pulse lasts three states: two for DJNZ and one to alter the pin.
Variations
DJNZ dir8,rel
Binary Mode
Not Taken
Source Mode
Not Taken
Taken
Taken
Bytes:
States:
3
3
3
6
3
3
3
6
[Encoding]
1 1 0 1
0 1 0 1
direct addr
rel. addr
Hex Code in: Binary Mode = [Encoding]
Source Mode = [Encoding]
Operation:
DJNZ
(PC) ← (PC) + 2
(dir8) ← (dir8) – 1
IF (dir8) > 0 or (dir8) < 0
THEN
(PC) ← (PC) + rel
DJNZ Rn,rel
Binary Mode
Not Taken
Source Mode
Not Taken
Taken
Taken
Bytes:
States:
2
2
2
5
3
3
3
6
[Encoding]
1 1 0 1
1 r r r
rel. addr
Hex Code in: Binary Mode = [Encoding]
Source Mode = [A5][Encoding]
A-58
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Operation:
DJNZ
(PC) ← (PC) + 2
(Rn) ← (Rn) – 1
IF (Rn) > 0 or (Rn) < 0
THEN
(PC) ← (PC) + rel
ECALL <dest>
Function:
Extended call
Description:
Calls a subroutine located at the specified address. The instruction adds four to the program
counter to generate the address of the next instruction and then pushes the 24-bit result
onto the stack (high byte first), incrementing the stack pointer by three. The 8 bits of the high
word and the 16 bits of the low word of the PC are then loaded, respectively, with the
second, third and fourth bytes of the ECALL instruction. Program execution continues with
the instruction at this address. The subroutine may therefore begin anywhere in the full 16-
Mbyte memory space.
Flags:
CY
—
AC
—
OV
—
N
Z
—
—
Example:
The stack pointer contains 07H and the label “SUBRTN” is assigned to program memory
location 123456H. After executing the instruction
ECALL SUBRTN
at location 012345H, SP contains 0AH; on-chip RAM locations 08H, 09H and 0AH contain
01H, 23H and 45H, respectively; and the PC contains 123456H.
Variations
ECALL addr24
Binary Mode
Source Mode
Bytes:
States:
5
4
14
13
[Encoding]
1 0 0 1
1 0 1 0
addr23–
addr16
addr15–addr8
addr7–addr0
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
ECALL
(PC) ← (PC) + 4
(SP) ← (SP) + 1
((SP)) ← (PC.23:16)
(SP) ← (SP) + 1
((SP)) ← (PC.15:8)
(SP) ← (SP) + 1
((SP)) ← (PC.7:0)
(PC) ← (addr.23:0)
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ECALL @DRk
Binary Mode
Source Mode
Bytes:
States:
3
2
12
11
[Encoding]
1 0 0 1
1 0 0 1
u u u u
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
ECALL
(PC) ← (PC) + 4
(SP) ← (SP) + 1
((SP)) ← (PC.23:16)
(SP) ← (SP) + 1
((SP)) ← (PC.15:8)
(SP) ← (SP) + 1
((SP)) ← (PC.7:0)
(PC) ← ((DRk))
EJMP <dest>
Function:
Extended jump
Description:
Causes an unconditional branch to the specified address by loading the 8 bits of the high
order and 16 bits of the low order words of the PC with the second, third, and fourth
instruction bytes. The destination may be therefore be anywhere in the full 16-Mbyte
memory space.
Flags:
CY
—
AC
—
OV
—
N
Z
—
—
Example:
The label "JMPADR" is assigned to the instruction at program memory location 123456H.
The instruction is
EJMP JMPADR
Variations
EJMP addr24
Binary Mode
Source Mode
Bytes:
States:
5
6
4
5
[Encoding]
1 0 0 0
1 0 1 0
addr23–
addr16
addr15–addr8
addr7–addr0
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
EJMP
(PC) ← (addr.23:0)
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EJMP @DRk
Binary Mode
Source Mode
Bytes:
States:
3
7
2
6
[Encoding]
1 0 0 0
1 0 0 1
u u u u
Hex Code in: Binary Mode = [A5] [Encoding]
Source Mode = [Encoding]
Operation:
EJMP
(PC) ← ((DRk))
ERET
Function:
Description:
Extended return
Pops byte 2, byte 1, and byte 0 of the 3-byte PC successively from the stack and
decrements the stack pointer by 3. Program execution continues at the resulting address,
which normally is the instruction immediately following ECALL.
Flags:
No flags are affected.
Example:
The stack pointer contains 0BH. On-chip RAM locations 08H, 09H and 0AH contain 01H,
23H and 49H, respectively. After executing the instruction
ERET
the stack pointer contains 08H and program execution continues at location 012349H.
Binary Mode
Source Mode
Bytes:
States:
3
2
9
10
[Encoding]
1 0 1 0
1 0 1 0
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
ERET
(PC.23:16) ¨ ((SP))
(SP) ¨ (SP) – 1
(PC.15:8) ¨ ((SP))
(SP) ¨ (SP) – 1
(PC.7:0) ← ((SP))
(SP) ← (SP) – 1
INC <Byte>
Function:
Increment
Description:
Increments the specified byte variable by 1. An original value of FFH overflows to 00H.
Three addressing modes are allowed for 8-bit operands: register, direct, or register-indirect.
Note: When this instruction is used to modify an output port, the value used as the original
port data is read from the output data latch, not the input pins.
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Flags:
CY
—
AC
—
OV
—
N
Z
✓
✓
Example:
Register 0 contains 7EH (011111110B) and on-chip RAM locations 7EH and 7FH contain
0FFH and 40H, respectively. After executing the instruction sequence
INC @R0
INC R0
INC @R0
register 0 contains 7FH and on-chip RAM locations 7EH and 7FH contain 00H and 41H,
respectively.
Variations
INC A
Binary Mode
Source Mode
Bytes:
States:
1
1
1
1
[Encoding]
0 0 0 0
0 1 0 0
Hex Code in: Binary Mode = [Encoding]
Source Mode = [Encoding]
Operation:
INC dir8
INC
(A) ← (A) + 1
Binary Mode
Source Mode
Bytes:
States:
2
2
2†
2†
†If this instruction addresses a port (Px, x = 0–3), add 2 states.
[Encoding]
0 0 0 0 0 1 0 1 direct addr
Hex Code in: Binary Mode = [Encoding]
Source Mode = [Encoding]
Operation:
INC @Ri
INC
(dir8) ← (dir8) + 1
Binary Mode
Source Mode
Bytes:
States:
1
3
2
4
[Encoding]
0 0 0 0
0 1 1 i
Hex Code in: Binary Mode = [Encoding]
Source Mode = [A5][Encoding]
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Operation:
INC Rn
INC
((Ri) ← ((Ri)) + 1
Binary Mode
Source Mode
Bytes:
States:
1
1
2
2
[Encoding]
0 0 0 0
1 r r r
Hex Code in: Binary Mode = [Encoding]
Source Mode = [A5][Encoding]
Operation:
INC
(Rn) ← (Rn) + 1
INC <dest>,<src>
Function:
Increment
Description:
Increments the specified variable by 1, 2, or 4. An original value of 0FFH overflows to 00H.
Flags:
CY
—
AC
—
OV
—
N
Z
✓
✓
Example:
Register 0 contains 7EH (011111110B). After executing the instruction
INC R0,#1
register 0 contains 7FH.
Variations
INC Rm,#short
Binary Mode
Source Mode
Bytes:
States:
3
2
2
1
[Encoding]
0 0 0 0
1 0 1 1
s s s s
00
v v
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
INC
(Rm) ← (Rm) + #short
INC WRj,#short
Binary Mode
Source Mode
Bytes:
States:
3
2
2
1
[Encoding]
0 0 0 0
1 0 1 1
t t t t
01
v v
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Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
INC
(WRj) ← (WRj) + #short
INC DRk,#short
Binary Mode
Source Mode
Bytes:
States:
3
4
2
3
[Encoding]
0 0 0 0
1 0 1 1
u u u u
11
v v
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
INC
(DRk) ← (DRk) + #shortdata pointer
INC DPTR
Function:
Increment data pointer
16
Description:
Increments the 16-bit data pointer by one. A 16-bit increment (modulo 2 ) is performed; an
overflow of the low byte of the data pointer (DPL) from 0FFH to 00H increments the high
byte of the data pointer (DPH) by one. An overflow of the high byte (DPH) does not
increment the high word of the extended data pointer (DPX = DR56).
Flags:
CY
—
AC
—
OV
—
N
Z
✓
✓
Example:
Registers DPH and DPL contain 12H and 0FEH, respectively. After the instruction sequence
INC DPTR
INC DPTR
INC DPTR
DPH and DPL contain 13H and 01H, respectively.
Binary Mode
Source Mode
Bytes:
States:
1
1
1
1
[Encoding]
1 0 1 0
0 0 1 1
Hex Code in: Binary Mode = [Encoding]
Source Mode = [Encoding]
Operation:
INC
(DPTR) ← (DPTR) + 1
A-64
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JB bit51,rel
JB bit,rel
Function:
Jump if bit set
Description:
If the specified bit is a one, jump to the address specified; otherwise proceed with the next
instruction. The branch destination is computed by adding the signed relative displacement
in the third instruction byte to the PC, after incrementing the PC to the first byte of the next
instruction. The bit tested is not modified.
Flags:
CY
—
AC
—
OV
—
N
Z
—
—
Example:
Input port 1 contains 11001010B and the accumulator contains 56 (01010110B). After the
instruction sequence
JB P1.2,LABEL1
JB ACC.2,LABEL2
program execution continues at label LABEL2.
Variations
JB bit51,rel
Binary Mode
Not Taken
Source Mode
Not Taken
Taken
Taken
Bytes:
States:
3
2
3
5
3
2
3
5
[Encoding]
0 0 1 0
0 0 0 0
bit addr
rel. addr
Hex Code in: Binary Mode = [Encoding]
Source Mode = [Encoding]
Operation:
JB bit,rel
JB
(PC) ← (PC) + 3
IF (bit51) = 1
THEN
(PC) ← (PC) + rel
Binary Mode
Not Taken
Source Mode
Taken
Not Taken
Taken
Bytes:
5
4
5
7
4
3
4
6
States:
[Encoding]
1 0 1 0
1 0 0 1
0 0 1 0
0
y y
direct addr
rel. addr
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
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Operation:
JB
(PC) ← (PC) + 3
IF (bit) = 1
THEN
(PC) ← (PC) + rel
JBC bit51,rel
JBC bit,rel
Function:
Jump if bit is set and clear bit
Description:
If the specified bit is one, branch to the specified address; otherwise proceed with the next
instruction. The bit is not cleared if it is already a zero. The branch destination is computed
by adding the signed relative displacement in the third instruction byte to the PC, after incre-
menting the PC to the first byte of the next instruction.
Note: When this instruction is used to test an output pin, the value used as the original data
is read from the output data latch, not the input pin.
Flags:
CY
—
AC
—
OV
—
N
Z
—
—
Example:
The accumulator contains 56H (01010110B). After the instruction sequence
JBC ACC.3,LABEL1
JBC ACC.2,LABEL2
the accumulator contains 52H (01010010B) and program execution continues at label
LABEL2.
Variations
JBC bit51,rel
Binary Mode
Not Taken
Source Mode
Not Taken
Taken
Taken
Bytes:
States:
3
4
3
7
3
4
3
7
[Encoding]
0 0 0 1
0 0 0 0
bit addr
rel. addr
Hex Code in: Binary Mode = [Encoding]
Source Mode = [Encoding]
Operation:
JBC
(PC) ← (PC) + 3
IF (bit51) = 1
THEN
(bit51) ← 0
(PC) ← (PC) + rel
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JBC bit,rel
Binary Mode
Not Taken
Source Mode
Taken
Not Taken
Taken
Bytes:
5
4
5
7
4
3
4
6
States:
[Encoding]
1 0 1 0
1 0 0 1
0 0 0 1
0
y y y
direct addr
rel. addr
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
JBC
(PC) ← (PC) + 3
IF (bit51) = 1
THEN
(bit51) ← 0
(PC) ← (PC) + rel
JC rel
Function:
Description:
Jump if carry is set
If the CY flag is set, branch to the address specified; otherwise proceed with the next
instruction. The branch destination is computed by adding the signed relative displacement
in the second instruction byte to the PC, after incrementing the PC twice.
Flags:
CY
!
AC
—
OV
—
N
Z
—
—
Example:
The CY flag is clear. After the instruction sequence
JC
LABEL1
CPL CY
JC LABEL 2
the CY flag is set and program execution continues at label LABEL2.
Binary Mode
Not Taken
Source Mode
Not Taken
Taken
Taken
Bytes:
States:
2
1
2
4
2
1
2
4
[Encoding]
0 1 0 0
0 0 0 0
rel. addr
Hex Code in: Binary Mode = [Encoding]
Source Mode = [Encoding]
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Operation:
JC
(PC) ← (PC) + 2
IF (CY) = 1
THEN
(PC) ← (PC) + rel
JE rel
Function:
Description:
Jump if equal
If the Z flag is set, branch to the address specified; otherwise proceed with the next
instruction. The branch destination is computed by adding the signed relative displacement
in the second instruction byte to the PC, after incrementing the PC twice.
Flags:
CY
—
AC
—
OV
—
N
Z
!
—
Example:
The Z flag is set. After executing the instruction
JE LABEL1
program execution continues at label LABEL1.
Binary Mode
Source Mode
Not Taken
Taken
Not Taken
Taken
Bytes:
States:
3
2
3
5
2
1
2
4
[Encoding]
0 1 1 0
1 0 0 0
rel. addr
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
JE
(PC) ← (PC) + 2
IF (Z) = 1
THEN (PC) ← (PC) + rel
JG rel
Function:
Description:
Jump if greater than
If the Z flag and the CY flag are both clear, branch to the address specified; otherwise
proceed with the next instruction. The branch destination is computed by adding the signed
relative displacement in the second instruction byte to the PC, after incrementing the PC
twice.
Flags:
CY
—
AC
—
OV
—
N
!
Z
—
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INSTRUCTION SET REFERENCE
Example:
The instruction
JG LABEL1
causes program execution to continue at label LABEL1 if the Z flag and the CY flag are both
clear.
Binary Mode
Not Taken
Source Mode
Not Taken
Taken
Taken
Bytes:
States:
3
2
3
5
2
1
2
4
[Encoding]
0 0 1 1
1 0 0 0
rel. addr
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
JG
(PC) ← (PC) + 2
IF (Z) = 0 AND (CY) = 0
THEN (PC) ← (PC) + rel
JLE rel
Function:
Description:
Jump if less than or equal
If the Z flag or the CY flag is set, branch to the address specified; otherwise proceed with the
next instruction. The branch destination is computed by adding the signed relative
displacement in the second instruction byte to the PC, after incrementing the PC twice.
Flags:
CY
—
AC
—
OV
—
N
!
Z
!
Example:
The instruction
JLE LABEL1
causes program execution to continue at LABEL1 if the Z flag or the CY flag is set.
Binary Mode
Not Taken
Source Mode
Not Taken
Taken
Taken
Bytes:
States:
3
2
3
5
2
1
2
4
[Encoding]
0 0 1 0
1 0 0 0
rel. addr
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
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Operation:
JLE
(PC) ← (PC) + 2
IF (Z) = 1 OR (CY) = 1
THEN (PC) ← (PC) + rel
JMP @A+DPTR
Function:
Jump indirect
Description:
Add the 8-bit unsigned contents of the accumulator with the 16-bit data pointer and load the
resulting sum into the lower 16 bits of the program counter. This is the address for
subsequent instruction fetches. The contents of the accumulator and the data pointer are
not affected.
Flags:
CY
—
AC
—
OV
—
N
Z
—
—
Example:
The accumulator contains an even number from 0 to 6. The following sequence of instruc-
tions branch to one of four AJMP instructions in a jump table starting at JMP_TBL:
MOV
JMP
DPTR,#JMP_TB
L
AJMP
AJMP
AJMP
AJMP
@A+DPTR
LABEL0
LABEL1
LABEL2
LABEL3
JMP_TBL:
If the accumulator contains 04H at the start this sequence, execution jumps to LABEL2.
Remember that AJMP is a two-byte instruction, so the jump instructions start at every other
address.
Binary Mode
Source Mode
Bytes:
States:
1
5
1
5
[Encoding]
0 1 1 1
0 0 1 1
Hex Code in: Binary Mode = [Encoding]
Source Mode = [Encoding]
Operation:
JMP
(PC.15:0) ← (A) + (DPTR)
JNB bit51,rel
JNB bit,rel
Function:
Jump if bit not set
Description:
If the specified bit is clear, branch to the specified address; otherwise proceed with the next
instruction. The branch destination is computed by adding the signed relative displacement
in the third instruction byte to the PC, after incrementing the PC to the first byte of the next
instruction. The bit tested is not modified.
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Flags:
CY
—
AC
—
OV
—
N
Z
—
—
Example:
Input port 1 contains 11001010B and the accumulator contains 56H (01010110B). After
executing the instruction sequence
JNB P1.3,LABEL1
JNB ACC.3,LABEL2
program execution continues at label LABEL2.
Variations
JNB bit51,rel
Binary Mode
Not Taken
Source Mode
Not Taken
Taken
Taken
Bytes:
States:
3
2
3
5
3
2
3
5
[Encoding]
0 0 1 1
0 0 0 0
bit addr
rel. addr
Hex Code in: Binary Mode = [Encoding]
Source Mode = [Encoding]
Operation:
JNB
(PC) ← (PC) + 3
IF (bit51) = 0
THEN (PC) ← (PC) + rel
JNB bit,rel
Binary Mode
Not Taken
Source Mode
Taken
Not Taken
Taken
Bytes:
5
4
5
7
4
3
4
6
States:
[Encoding]
1 0 1 0
1 0 0 1
0 0 1 1
0
y y
direct addr
rel. addr
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
JNB
(PC) ← (PC) + 3
IF (bit) = 0
THEN
(PC) ← (PC) + rel
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JNC rel
Function:
Jump if carry not set
Description:
If the CY flag is clear, branch to the address specified; otherwise proceed with the next
instruction. The branch destination is computed by adding the signed relative displacement
in the second instruction byte to the PC, after incrementing the PC twice to point to the next
instruction. The CY flag is not modified.
Flags:
CY
!
AC
—
OV
—
N
Z
—
—
Example:
The CY flag is set. The instruction sequence
JNC LABEL1
CPL CY
JNC LABEL2
clears the CY flag and causes program execution to continue at label LABEL2.
Binary Mode
Not Taken
Source Mode
Not Taken
Taken
Taken
Bytes:
States:
2
1
2
4
2
1
2
4
[Encoding]
0 1 0 1
0 0 0 0
rel. addr
Hex Code in: Binary Mode = [Encoding]
Source Mode = [Encoding]
Operation:
JNC
(PC) ← (PC) + 2
IF (CY) = 0
THEN (PC) ← (PC) + rel
JNE rel
Function:
Description:
Jump if not equal
If the Z flag is clear, branch to the address specified; otherwise proceed with the next
instruction. The branch destination is computed by adding the signed relative displacement
in the second instruction byte to the PC, after incrementing the PC twice.
Flags:
CY
—
AC
—
OV
—
N
Z
!
—
Example:
The instruction
JNE LABEL1
causes program execution to continue at LABEL1 if the Z flag is clear.
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Binary Mode
Not Taken
Source Mode
Taken
Not Taken
Taken
Bytes:
States:
3
2
3
5
2
1
2
4
[Encoding]
0 1 1 1
1 0 0 0
rel. addr
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
JNE
(PC) ← (PC) + 2
IF (Z) = 0
THEN (PC) ← (PC) + rel
JNZ rel
Function:
Description:
Jump if accumulator not zero
If any bit of the accumulator is set, branch to the specified address; otherwise proceed with
the next instruction. The branch destination is computed by adding the signed relative
displacement in the second instruction byte to the PC, after incrementing the PC twice. The
accumulator is not modified.
Flags:
CY
—
AC
—
OV
—
N
Z
!
—
Example:
The accumulator contains 00H. After executing the instruction sequence
JNZ LABEL1
INC A
JNZ LABEL2
the accumulator contains 01H and program execution continues at label LABEL2.
Binary Mode Source Mode
Not Taken Not Taken
Taken
Taken
Bytes:
States:
2
2
2
5
2
2
2
5
[Encoding]
0 1 1 1
0 0 0 0
rel. addr
Hex Code in: Binary Mode = [Encoding]
Source Mode = [Encoding]
Operation:
JNZ
(PC) ← (PC) + 2
IF (A) ≠ 0
THEN (PC) ← (PC) + rel
A-73
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JSG rel
Function:
Jump if greater than (signed)
Description:
If the Z flag is clear AND the N flag and the OV flag have the same value, branch to the
address specified; otherwise proceed with the next instruction. The branch destination is
computed by adding the signed relative displacement in the second instruction byte to the
PC, after incrementing the PC twice.
Flags:
CY
—
AC
—
OV
!
N
!
Z
!
Example:
The instruction
JSG LABEL1
causes program execution to continue at LABEL1 if the Z flag is clear AND the N flag and
the OV flag have the same value.
Binary Mode
Not Taken
Source Mode
Not Taken
Taken
Taken
Bytes:
States:
3
2
3
5
2
1
2
4
[Encoding]
0 0 0 1
1 0 0 0
rel. addr
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
JSG
(PC) ← (PC) + 2
IF [(N) = 0 AND (N) = (OV)]
THEN (PC) ← (PC) + rel
JSGE rel
Function:
Jump if greater than or equal (signed)
Description:
If the N flag and the OV flag have the same value, branch to the address specified;
otherwise proceed with the next instruction. The branch destination is computed by adding
the signed relative displacement in the second instruction byte to the PC, after incrementing
the PC twice.
Flags:
CY
—
AC
—
OV
!
N
!
Z
!
Example:
The instruction
JSGE LABEL1
causes program execution to continue at LABEL1 if the N flag and the OV flag have the
same value.
A-74
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Binary Mode
Not Taken
Source Mode
Taken
Not Taken
Taken
Bytes:
States:
3
2
3
5
2
1
2
4
[Encoding]
0 1 0 1
1 0 0 0
rel. addr
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
JSGE
(PC) ← (PC) + 2
IF [(N) = (OV)]
THEN (PC) ← (PC) + rel
JSL rel
Function:
Description:
Jump if less than (signed)
If the N flag and the OV flag have different values, branch to the address specified;
otherwise proceed with the next instruction. The branch destination is computed by adding
the signed relative displacement in the second instruction byte to the PC, after incrementing
the PC twice.
Flags:
CY
—
AC
—
OV
!
N
!
Z
!
Example:
The instruction
JSL LABEL1
causes program execution to continue at LABEL1 if the N flag and the OV flag have different
values.
Binary Mode
Not Taken
Source Mode
Not Taken
Taken
Taken
Bytes:
States:
3
2
3
5
2
1
2
4
[Encoding]
0 1 0 0
1 0 0 0
rel. addr
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
JSL
(PC) ← (PC) + 2
IF (N) ≠ (OV)
THEN (PC) ← (PC) + rel
A-75
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JSLE rel
Function:
Jump if less than or equal (signed)
Description:
If the Z flag is set OR if the the N flag and the OV flag have different values, branch to the
address specified; otherwise proceed with the next instruction. The branch destination is
computed by adding the signed relative displacement in the second instruction byte to the
PC, after incrementing the PC twice.
Flags:
CY
—
AC
—
OV
!
N
!
Z
!
Example:
The instruction
JSLE LABEL1
causes program execution to continue at LABEL1 if the Z flag is set OR if the N flag and the
OV flag have different values.
Binary Mode
Not Taken
Source Mode
Not Taken
Taken
Taken
Bytes:
States:
3
2
3
5
2
1
2
4
[Encoding]
0 0 0 0
1 0 0 0
rel. addr
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
JSLE
(PC) ← (PC) + 2
IF {(Z) = 1 OR [(N) ≠ (OV)]}
THEN (PC) ← (PC) + rel
JZ rel
Function:
Jump if accumulator zero
Description:
Flags:
If all bits of the accumulator are clear (zero), branch to the address specified; otherwise
proceed with the next instruction. The branch destination is computed by adding the signed
relative displacement in the second instruction byte to the PC, after incrementing the PC
twice. The accumulator is not modified.
CY
—
AC
—
OV
—
N
Z
!
—
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INSTRUCTION SET REFERENCE
Example:
The accumulator contains 01H. After executing the instruction sequence
JZ LABEL1
DEC A
JZ LABEL2
the accumulator contains 00H and program execution continues at label LABEL2.
Binary Mode
Not Taken
Source Mode
Not Taken
Taken
Taken
Bytes:
States:
2
2
2
5
2
2
2
5
[Encoding]
0 1 1 0
0 0 0 0
rel. addr
Hex Code in: Binary Mode = [Encoding]
Source Mode = [Encoding]
Operation:
JZ
(PC) ← (PC) + 2
IF (A) = 0
THEN (PC) ← (PC) + rel
LCALL <dest>
Function:
Long call
Description:
Calls a subroutine located at the specified address. The instruction adds three to the
program counter to generate the address of the next instruction and then pushes the 16-bit
result onto the stack (low byte first). The stack pointer is incremented by two. The high and
low bytes of the PC are then loaded, respectively, with the second and third bytes of the
LCALL instruction. Program execution continues with the instruction at this address. The
subroutine may therefore begin anywhere in the 64-Kbyte region of memory where the next
instruction is located.
Flags:
CY
—
AC
—
OV
—
N
Z
—
—
Example:
The stack pointer contains 07H and the label "SUBRTN" is assigned to program memory
location 1234H. After executing the instruction
LCALL SUBRTN
at location 0123H, the stack pointer contains 09H, on-chip RAM locations 08H and 09H
contain 01H and 26H, and the PC contains 1234H.
LCALL addr16
Binary Mode
Source Mode
Bytes:
States:
3
9
3
9
[Encoding]
0 0 0 1
0 0 1 0
addr15–addr8
addr7–addr0
A-77
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Hex Code in: Binary Mode = [Encoding]
Source Mode = [Encoding]
Operation:
LCALL
(PC) ← (PC) + 3
(SP) ← (SP) + 1
((SP)) ← (PC.7:0)
(SP) ← (SP) + 1
((SP)) ← (PC.15:8)
(PC) ← (addr.15:0)
LCALL @WRj
Binary Mode
Source Mode
Bytes:
States:
3
9
2
8
[Encoding]
1 0 0 1
1 0 0 1
t t t t
0 1 0 0
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
LCALL
(PC) ← (PC) + 3
(SP) ← (SP) + 1
((SP)) ← (PC.7:0)
(SP) ← (SP) + 1
((SP)) ← (PC.15:8)
(PC) ← ((WRj))
LJMP <dest>
Function:
Long Jump
Description:
Causes an unconditional branch to the specified address, by loading the high and low bytes
of the PC (respectively) with the second and third instruction bytes. The destination may
therefore be anywhere in the 64-Kbyte memory region where the next instruction is located.
Flags:
CY
—
AC
—
OV
—
N
Z
—
—
Example:
The label “JMPADR” is assigned to the instruction at program memory location 1234H. After
executing the instruction
LJMP JMPADR
at location 0123H, the program counter contains 1234H.
LJMP addr16
Binary Mode
Source Mode
Bytes:
States:
3
5
3
5
[Encoding]
0 0 0 0
0 0 1 0
addr15–addr8
addr7–addr0
A-78
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Hex Code in: Binary Mode = [Encoding]
Source Mode = [Encoding]
Operation:
LJMP
(PC) ← (addr.15:0)
LJMP @WRj
Binary Mode
Source Mode
Bytes:
States:
3
6
2
5
[Encoding]
1 0 0 0
1 0 0 1
t t t t
0 1 0 0
Hex Code in: Binary Mode = [A5] [Encoding]
Source Mode = [Encoding]
Operation:
LJMP
(PC) ← ((WRj))
MOV <dest>,<src>
Function:
Move byte variable
Description:
Copies the byte variable specified by the second operand into the location specified by the
first operand. The source byte is not affected.
This is by far the most flexible operation. Twenty-four combinations of source and
destination addressing modes are allowed.
Flags:
CY
—
AC
—
OV
—
N
Z
—
—
Example:
On-chip RAM location 30H contains 40H, on-chip RAM location 40H contains 10H, and
input port 1 contains 11001010B (0CAH). After executing the instruction sequence
MOV
MOV
MOV
MOV
MOV
MOV
R0,#30H
A,@R0
R1,A
B,@R1
@R1,P1
P2,P1
;R0 < = 30H
;A < = 40H
;R1 < = 40H
;B < = 10H
;RAM (40H) < = 0CAH
;P2 #0CAH
register 0 contains 30H, the accumulator and register 1 contain 40H, register B contains
10H, and on-chip RAM location 40H and output port 2 contain 0CAH (11001010B).
Variations
MOV A,#data
Binary Mode
Source Mode
Bytes:
States:
2
1
2
1
[Encoding]
0 1 1 1
0 1 0 0
immed. data
A-79
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Hex Code in: Binary Mode = [Encoding]
Source Mode = [Encoding]
Operation:
MOV
(A) ← #data
MOV dir8,#data
Binary Mode
Source Mode
Bytes:
States:
3
3
3†
3†
†If this instruction addresses a port (Px, x = 0–3), add 1 state.
[Encoding]
0 1 1 1 0 1 0 1 direct addr immed. data
Hex Code in: Binary Mode = [Encoding]
Source Mode = [Encoding]
Operation:
MOV
(dir8) ← #data
MOV @Ri,#data
Binary Mode
Source Mode
Bytes:
States:
2
3
3
4
[Encoding]
0 1 1 1
0 1 1 i
immed. data
Hex Code in: Binary Mode = [Encoding]
Source Mode = [A5][Encoding]
Operation:
MOV
((Ri)) ← #data
MOV Rn,#data
Binary Mode
Source Mode
Bytes:
States:
2
1
3
2
[Encoding]
0 1 1 1
1 r r r r
immed. data
Hex Code in: Binary Mode = [Encoding]
Source Mode = [A5][Encoding]
Operation:
MOV
(Rn) ← #data
MOV dir8,dir8
Binary Mode
Source Mode
Bytes:
States:
3
3
3
3
A-80
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[Encoding]
1 0 0 0
0 1 0 1
direct addr
direct addr
Hex Code in: Binary Mode = [Encoding]
Source Mode = [Encoding]
Operation:
MOV
(dir8) ← (dir8)
MOV dir8,@Ri
Binary Mode
Source Mode
Bytes:
States:
2
3
3
4
[Encoding]
1 0 0 0
0 1 1 i
direct addr
Hex Code in: Binary Mode = [Encoding]
Source Mode = [A5][Encoding]
Operation:
MOV
(dir8) ← ((Ri))
MOV dir8,Rn
Binary Mode
Source Mode
Bytes:
States:
2
3
2†
3†
†If this instruction addresses a port (Px, x = 0–3), add 1 state.
[Encoding]
1 0 0 0 1 r r r direct addr
Hex Code in: Binary Mode = [Encoding]
Source Mode = [A5][Encoding]
Operation:
MOV
(dir8) ← (Rn)
MOV @Ri,dir8
Binary Mode
Source Mode
Bytes:
States:
2
3
3
4
[Encoding]
1 0 1 0
0 1 1 i
direct addr
Hex Code in: Binary Mode = [Encoding]
Source Mode = [A5][Encoding]
Operation:
MOV
((Ri)) ← (dir8)
A-81
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MOV Rn,dir8
Binary Mode
Source Mode
Bytes:
States:
2
3
1†
2†
†If this instruction addresses a port (Px, x = 0–3), add 1 state.
[Encoding]
1 0 1 0 1 r r r direct addr
Hex Code in: Binary Mode = [Encoding]
Source Mode = [A5][Encoding]
Operation:
MOV A,dir8
MOV
(Rn) ← (dir8)
Binary Mode
Source Mode
Bytes:
States:
2
2
1†
1†
†If this instruction addresses a port (Px, x = 0–3), add 1 state.
[Encoding]
1 1 1 0 0 1 0 1 direct addr
Hex Code in: Binary Mode = [Encoding]
Source Mode = [Encoding]
Operation:
MOV A,@Ri
MOV
(A) ← (dir8)
Binary Mode
Source Mode
Bytes:
States:
1
2
2
3
[Encoding]
1 1 1 0
0 1 1 i
Hex Code in: Binary Mode = [Encoding]
Source Mode = [A5][Encoding]
Operation:
MOV A,Rn
MOV
(A) ← ((Ri))
Binary Mode
Source Mode
Bytes:
States:
1
1
2
2
[Encoding]
1 1 1 0
1 r r r
Hex Code in: Binary Mode = [Encoding]
Source Mode = [A5][Encoding]
A-82
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INSTRUCTION SET REFERENCE
Operation:
MOV dir8,A
MOV
(A) ← (Rn)
Binary Mode
Source Mode
Bytes:
States:
2
2
2†
2†
†If this instruction addresses a port (Px, x = 0–3), add 1 state.
[Encoding]
1 1 1 1 0 1 0 1 direct addr
Hex Code in: Binary Mode = [Encoding]
Source Mode = [Encoding]
Operation:
MOV @Ri,A
MOV
(dir8) ← (A)
Binary Mode
Source Mode
Bytes:
States:
1
3
2
4
[Encoding]
1 1 1 1
0 1 1 i
Hex Code in: Binary Mode = [Encoding]
Source Mode = [A5][Encoding]
Operation:
MOV Rn,A
MOV
((Ri)) ← (A)
Binary Mode
Source Mode
Bytes:
States:
1
1
2
2
[Encoding]
1 1 1 1
1 1 1 r
Hex Code in: Binary Mode = [Encoding]
Source Mode = [A5][Encoding]
Operation:
MOV
(Rn) ← (A)
MOV Rmd,Rms
Binary Mode
Source Mode
Bytes:
States:
3
2
2
1
[Encoding]
0 1 1 1
1 1 0 0
s s s s
S S S S
A-83
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Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
MOV
(Rmd) ← (Rms)
MOV WRjd,WRjs
Binary Mode
Source Mode
Bytes:
States:
3
2
2
1
[Encoding]
0 1 1 1
1 1 0 1
t t t t
u u u u
s s s s
T T T T
UUUU
0 0 0 0
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
MOV
(WRjd) ← (WRjs)
MOV DRkd,DRks
Binary Mode
Source Mode
Bytes:
States:
3
3
2
2
[Encoding]
0 1 1 1
1 1 1 1
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
MOV
(DRkd) ← (DRks)
MOV Rm,#data
Binary Mode
Source Mode
Bytes:
States:
4
3
3
2
[Encoding]
0 1 1 1
1 1 1 0
#data
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
MOV
(Rm) ← #data
MOV WRj,#data16
Binary Mode
Source Mode
Bytes:
States:
5
3
4
2
A-84
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INSTRUCTION SET REFERENCE
[Encoding]
0 1 1 1
1 1 1 0
t t t t
0 1 0 0
1 0 0 0
1 1 0 0
#data hi
#data hi
#data hi
#data low
#data low
#data low
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
MOV
(WRj) ← #data16
MOV DRk,#0data16
Binary Mode
Source Mode
Bytes:
5
5
4
4
States:
[Encoding]
0 1 1 1
1 1 1 0
u u u u
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
MOV
(DRk) ← #0data16
MOV DRk,#1data16
Binary Mode
Source Mode
Bytes:
5
5
4
4
States:
[Encoding]
0 1 1 1
1 1 1 0
u u u u
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
MOV
(DRk) ← #1data16
MOV Rm,dir8
Binary Mode
Source Mode
Bytes:
States:
4
3
3†
2†
†If this instruction addresses a port (Px, x = 0–3), add 1 state.
[Encoding]
0 1 1 1 1 1 1 0 s s s s 0 0 0 1
direct addr
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
A-85
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Operation:
MOV
(Rm) ← (dir8)
MOV WRj,dir8
Binary Mode
Source Mode
Bytes:
States:
4
4
3
3
[Encoding]
0 1 1 1
1 1 1 0
t t t t
0 1 0 1
direct addr
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
MOV
(WRj) ← (dir8)
MOV DRk,dir8
Binary Mode
Source Mode
Bytes:
States:
4
6
3
5
[Encoding]
0 1 1 1
1 1 1 0
u u u u
1 1 0 1
direct addr
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
MOV
(DRk) ← (dir8)
MOV Rm,dir16
Binary Mode
Source Mode
Bytes:
5
3
4
2
States:
[Encoding]
0 1 1 1
1 1 1 0
s s s s
0 0 1 1
direct addr
direct addr
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
MOV
(Rm) ← (dir16)
MOV WRj,dir16
Binary Mode
Source Mode
Bytes:
States:
5
4
4
3
A-86
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[Encoding]
0 1 1 1
1 1 1 0
t t t t
0 1 1 1
direct addr
direct addr
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
MOV
(WRj) ← (dir16)
MOV DRk,dir16
Binary Mode
Source Mode
Bytes:
5
6
4
5
States:
[Encoding]
0 1 1 1
1 1 1 0
u u u u
1 1 1 1
direct addr
direct addr
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
MOV
(DRk) ← (dir16)
MOV Rm,@WRj
Binary Mode
Source Mode
Bytes:
4
2
3
2
States:
[Encoding]
0 1 1 1
1 1 1 0
t t t t
1 0 0 1
s s s s
0 0 0 0
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
MOV
(Rm) ← ((WRj))
MOV Rm,@DRk
Binary Mode
Source Mode
Bytes:
4
4
3
3
States:
[Encoding]
0 1 1 1
1 1 1 0
u u u u
1 0 1 1
s s s s
0 0 0 0
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
MOV
(Rm) ← ((DRk))
A-87
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MOV WRjd,@WRjs
Binary Mode
Source Mode
Bytes:
4
4
3
3
States:
[Encoding]
0 0 0 0
1 0 1 1
T T T T
1 0 0 0
t t t t
0 0 0 0
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
MOV
(WRjd) ← ((WRjs))
MOV WRj,@DRk
Binary Mode
Source Mode
Bytes:
4
5
3
4
States:
[Encoding]
0 0 0 0
1 0 1 1
u u u u
1 0 1 0
t t t t
0 0 0 0
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
MOV
(WRj) ← ((DRk))
MOV dir8,Rm
Binary Mode
Source Mode
Bytes:
States:
4
3
4†
3†
†If this instruction addresses a port (Px, x = 0–3), add 1 state.
[Encoding]
0 1 1 1 1 0 1 0 s s s s 0 0 1 1
direct addr
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
MOV
(dir8) ← (Rm)
MOV dir8,WRj
Binary Mode
Source Mode
Bytes:
States:
4
5
3
4
A-88
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INSTRUCTION SET REFERENCE
[Encoding]
0 1 1 1
1 0 1 0
t t t t
0 1 0 1
direct addr
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
MOV
(dir8) ← (WRj)
MOV dir8,DRk
Binary Mode
Source Mode
Bytes:
States:
4
7
3
6
[Encoding]
0 1 1 1
1 0 1 0
u u u u
1 1 0 1
direct addr
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
MOV
(dir8) ← (DRk)
MOV dir16,Rm
Binary Mode
Source Mode
Bytes:
5
4
4
3
States:
[Encoding]
0 1 1 1
1 0 1 0
s s s s
0 0 1 1
direct addr
direct addr
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
MOV
(dir16) ← (Rm)
MOV dir16,WRj
Binary Mode
Source Mode
Bytes:
5
5
4
4
States:
[Encoding]
0 1 1 1
1 0 1 0
t t t t
0 1 1 1
direct addr
direct addr
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
MOV
(dir16) ← (WRj)
A-89
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MOV dir16,DRk
Binary Mode
Source Mode
Bytes:
5
7
4
6
States:
[Encoding]
0 1 1 1
1 0 1 0
u u u u
1 1 1 1
1 0 0 1
1 0 1 1
1 0 0 0
direct addr
direct addr
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
MOV
(dir16) ← (DRk)
MOV @WRj,Rm
Binary Mode
Source Mode
Bytes:
4
4
3
3
States:
[Encoding]
0 1 1 1
1 0 1 0
t t t t
s s s s
0 0 0 0
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
MOV
((WRj)) ← (Rm)
MOV @DRk,Rm
Binary Mode
Source Mode
Bytes:
4
5
3
4
States:
[Encoding]
0 1 1 1
1 0 1 0
u u u u
s s s s
0 0 0 0
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
MOV
((DRk)) ← (Rm)
MOV @WRjd,WRjs
Binary Mode
Source Mode
Bytes:
4
5
3
4
States:
[Encoding]
0 0 0 1
1 0 1 1
t t t t
T T T T
0 0 0 0
A-90
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INSTRUCTION SET REFERENCE
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
MOV
((WRjd)) ← (WRjs)
MOV @DRk,WRj
Binary Mode
Source Mode
Bytes:
4
6
3
5
States:
[Encoding]
0 0 0 1
1 0 1 1
u u u u
1 0 1 0
t t t t
0 0 0 0
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
MOV
((DRk)) ← (WRj)
MOV Rm,@WRj + dis16
Binary Mode
Source Mode
Bytes:
5
6
4
5
States:
[Encoding]
0 0 0 0
1 0 0 1
s s s s
t t t t
dis hi
dis low
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
MOV
(Rm) ← ((WRj)) + (dis)
MOV WRj,@WRj + dis16
Binary Mode
Source Mode
Bytes:
5
7
4
6
States:
[Encoding]
0 1 0 0
1 0 0 1
t t t t
T T T T
dis hi
dis low
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
MOV
(WRj) ← ((WRj)) + (dis)
A-91
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MOV Rm,@DRk + dis24
Binary Mode
Source Mode
Bytes:
5
7
4
6
States:
[Encoding]
0 0 1 0
1 0 0 1
s s s s
u u u u
u u u u
s s s s
dis hi
dis hi
dis hi
dis low
dis low
dis low
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
MOV
(Rm) ← ((DRk)) + (dis)
MOV WRj,@DRk + dis24
Binary Mode
Source Mode
Bytes:
5
8
4
7
States:
[Encoding]
0 1 1 0
1 0 0 1
t t t t
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
MOV
(WRj) ← ((DRk)) + (dis)
MOV @WRj + dis16,Rm
Binary Mode
Source Mode
Bytes:
5
6
4
5
States:
[Encoding]
0 0 0 1
1 0 0 1
t t t t
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
MOV
((WRj)) + (dis) ← (Rm)
MOV @WRj + dis16,WRj
Binary Mode
Source Mode
Bytes:
States:
5
7
4
6
A-92
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INSTRUCTION SET REFERENCE
[Encoding]
0 1 0 1
1 0 0 1
t t t t
T T T T
dis hi
dis low
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
MOV
((WRj)) + (dis) ← (WRj)
MOV @DRk + dis24,Rm
Binary Mode
Source Mode
Bytes:
5
7
4
6
States:
[Encoding]
0 0 1 1
1 0 0 1
u u u u
s s s s
dis hi
dis low
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
MOV
((DRk)) + (dis) ← (Rm)
MOV @DRk + dis24,WRj
Binary Mode
Source Mode
Bytes:
5
8
4
7
States:
[Encoding]
0 1 1 1
1 0 0 1
u u u u
t t t t
dis hi
dis low
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
MOV
((DRk)) + (dis) ← (WRj)
MOV <dest–bit>,<src–bit>
Function:
Move bit data
Description:
Copies the Boolean variable specified by the second operand into the location specified by
the first operand. One of the operands must be the CY flag; the other may be any directly
addressable bit. Does not affect any other register.
Flags:
CY
AC
—
OV
—
N
Z
✓
—
—
A-93
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Example:
The CY flag is set, input Port 3 contains 11000101B, and output Port 1 contains 35H
(00110101B). After executing the instruction sequence
MOV P1.3,CY
MOV CY,P3.3
MOV P1.2,CY
the CY flag is clear and Port 1 contains 39H (00111001B).
Variations
MOV bit51,CY
Binary Mode
Source Mode
Bytes:
States:
2
2
2†
2†
†If this instruction addresses a port (Px, x = 0–3), add 2 states.
[Encoding]
1 0 0 1 0 0 1 0 bit addr
Hex Code in: Binary Mode = [Encoding]
Source Mode = [Encoding]
Operation:
MOV
(bit51) ← (CY)
MOV CY,bit51
Binary Mode
Source Mode
Bytes:
States:
2
2
1†
1†
†If this instruction addresses a port (Px, x = 0–3), add 1 state.
[Encoding]
1 0 1 0 0 0 1 0 bit addr
Hex Code in: Binary Mode = [Encoding]
Source Mode = [Encoding]
Operation:
MOV bit,CY
MOV
(CY) ← (bit51)
Binary Mode
Source Mode
Bytes:
States:
4
3
4†
3†
†If this instruction addresses a port (Px, x = 0–3), add 2 states.
[Encoding]
1 0 1 0
1 0 0 1
1 0 0 1
0
y y y
direct addr
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
A-94
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INSTRUCTION SET REFERENCE
Operation:
MOV CY,bit
MOV
(bit) ← (CY)
Binary Mode
Source Mode
Bytes:
States:
4
3
3†
2†
†If this instruction addresses a port (Px, x = 0–3), add 1 state.
[Encoding]
1 0 1 0
1 0 0 1
1 0 1 0
0
y y y
direct addr
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
MOV
(CY) ← (bit)
MOV DPTR,#data16
Function:
Load data pointer with a 16-bit constant
Description:
Loads the 16-bit data pointer (DPTR) with the specified 16-bit constant. The high byte of the
constant is loaded into the high byte of the data pointer (DPH). The low byte of the constant
is loaded into the low byte of the data pointer (DPL).
Flags:
CY
—
AC
—
OV
—
N
Z
—
—
Example:
After executing the instruction
MOV DPTR,#1234H
DPTR contains 1234H (DPH contains 12H and DPL contains 34H).
Binary Mode
Source Mode
Bytes:
States:
3
2
3
2
[Encoding]
1 0 0 1
0 0 0 0
data hi
data low
Hex Code in: Binary Mode = [Encoding]
Source Mode = [Encoding]
Operation:
MOV
(DPTR) ← #data16
A-95
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MOVC A,@A+<base–reg>
Function:
Move code byte
Description:
Loads the accumulator with a code byte or constant from program memory. The address of
the byte fetched is the sum of the original unsigned 8-bit accumulator contents and the
contents of a 16-bit base register, which may be the 16 LSBs of the data pointer or PC. In
the latter case, the PC is incremented to the address of the following instruction before being
added with the accumulator; otherwise the base register is not altered. Sixteen-bit addition is
performed.
Flags:
CY
—
AC
—
OV
—
N
Z
—
—
Example:
The accumulator contains a number between 0 and 3. The following instruction sequence
translates the value in the accumulator to one of four values defined by the DB (define byte)
directive.
RELPC:
INC
MOVC
RET
DB
DB
DB
A
A,@A+PC
66H
77H
88H
99H
DB
If the subroutine is called with the accumulator equal to 01H, it returns with 77H in the
accumulator. The INC A before the MOVC instruction is needed to "get around" the RET
instruction above the table. If several bytes of code separated the MOVC from the table, the
corresponding number would be added to the accumulator instead.
Variations
MOVC A,@A+PC
Binary Mode
Source Mode
Bytes:
States:
1
6
1
6
[Encoding]
1 0 0 0
0 0 1 1
Hex Code in: Binary Mode = [Encoding]
Source Mode = [Encoding]
Operation:
MOVC
(PC) ← (PC) + 1
(A) ← ((A) + (PC))
MOVC A,@A+DPTR
Binary Mode
Source Mode
Bytes:
States:
1
6
1
6
[Encoding]
1 0 0 1
0 0 1 1
A-96
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INSTRUCTION SET REFERENCE
Hex Code in: Binary Mode = [Encoding]
Source Mode = [Encoding]
Operation:
MOVC
(A) ← ((A) + (DPTR))
MOVH DRk,#data16
Function:
Move immediate 16-bit data to the high word of a dword (double-word) register
Description:
Moves 16-bit immediate data to the high word of a dword (32-bit) register. The low word of
the dword register is unchanged.
Flags:
CY
—
AC
—
OV
—
N
Z
—
—
Example:
Variations
The dword register DRk contains 5566 7788H. After the instruction
MOVH DRk,#1122H
executes, DRk contains 1122 7788H.
MOVH DRk,#data16
Binary Mode
Source Mode
Bytes:
5
3
4
2
States:
[Encoding]
0 1 1 1
1 0 1 0
u u u u
1 1 0 0
#data hi
#data low
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
MOVH
(DRk).31:16 ← #data16
MOVS WRj,Rm
Function:
Move 8-bit register to 16-bit register with sign extension
Description:
Moves the contents of an 8-bit register to the low byte of a 16-bit register. The high byte of
the 16-bit register is filled with the sign extension, which is obtained from the MSB of the 8-
bit source register.
Flags:
CY
—
AC
—
OV
—
N
Z
—
—
A-97
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Example:
Eight-bit register Rm contains 055H (01010101B) and the 16-bit register WRj contains
0FFFFH (11111111 11111111B). The instruction
MOVS WRj,Rm
moves the contents of register Rm (01010101B) to register WRj (i.e., WRj contains
00000000 01010101B).
Variations
MOVS WRj,Rm
Binary Mode
Source Mode
Bytes:
States:
3
2
2
1
[Encoding]
0 0 0 1
1 0 1 0
t t t t
s s s s
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
MOVS
(WRj).7–0 ← (Rm).7–0
(WRj).15–8 ← MSB
MOVX <dest>,<src>
Function:
Move external
Description:
Transfers data between the accumulator and a byte in external data RAM. There are two
types of instructions. One provides an 8-bit indirect address to external data RAM; the
second provides a 16-bit indirect address to external data RAM.
In the first type of MOVX instruction, the contents of R0 or R1 in the current register bank
provides an 8-bit address on port 0. Eight bits are sufficient for external I/O expansion
decoding or for a relatively small RAM array. For larger arrays, any port pins can be used to
output higher address bits. These pins would be controlled by an output instruction
preceding the MOVX.
In the second type of MOVX instruction, the data pointer generates a 16-bit address. Port 2
outputs the upper eight address bits (from DPH) while port 0 outputs the lower eight address
bits (from DPL).
For both types of moves in nonpage mode, the data is multiplexed with the lower address
bits on port 0. In page mode, the data is multiplexed with the contents of P2 on port 2 (8-bit
address) or with the upper address bits on port 2 (16-bit address).
It is possible in some situations to mix the two MOVX types. A large RAM array with its
upper address lines driven by P2 can be addressed via the data pointer, or with code to
output upper address bits to P2 followed by a MOVX instruction using R0 or R1.
Flags:
CY
—
AC
—
OV
—
N
Z
—
—
A-98
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INSTRUCTION SET REFERENCE
Example:
The MCS 251 controller is operating in nonpage mode. An external 256-byte RAM using
multiplexed address/data lines (e.g., an Intel 8155 RAM/I/O/Timer) is connected to port 0.
Port 3 provides control lines for the external RAM. ports 1 and 2 are used for normal I/O. R0
and R1 contain 12H and 34H. Location 34H of the external RAM contains 56H. After
executing the instruction sequence
MOVX A,@R1
MOVX @R0,A
the accumulator and external RAM location 12H contain 56H.
Variations
MOVX A,@DPTR
Binary Mode
Source Mode
Bytes:
States:
1
5
1
5
[Encoding]
1 1 1 0
0 0 0 0
Hex Code in: Binary Mode = [Encoding]
Source Mode = [Encoding]
Operation:
MOVX
(A) ← ((DPTR))
MOVX A,@Ri
Binary Mode
Source Mode
Bytes:
States:
1
3
1
3
[Encoding]
1 1 1 0
0 0 1 i
Hex Code in: Binary Mode = [Encoding]
Source Mode = [A5][Encoding]
Operation:
MOVX
(A) ← ((Ri))
MOVX @DPTR,A
Binary Mode
Source Mode
Bytes:
States:
1
5
1
5
[Encoding]
1 1 1 1
0 0 0 0
Hex Code in: Binary Mode = [Encoding]
Source Mode = [Encoding]
Operation:
MOVX
((DPTR)) ← (A)
A-99
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MOVX @Ri,A
Binary Mode
Source Mode
Bytes:
States:
1
4
1
4
[Encoding]
1 1 1 1
0 0 1 i
Hex Code in: Binary Mode = [Encoding]
Source Mode = [A5][Encoding]
Operation:
MOVX
((Ri)) ← (A)
MOVZ WRj,Rm
Function:
Move 8-bit register to 16-bit register with zero extension
Description:
Moves the contents of an 8-bit register to the low byte of a 16-bit register. The upper byte of
the 16-bit register is filled with zeros.
Flags:
CY
—
AC
—
OV
—
N
Z
—
—
Example:
Eight-bit register Rm contains 055H (01010101B) and 16-bit register WRj contains 0FFFFH
(11111111 11111111B). The instruction
MOVZ WRj,Rm
moves the contents of register Rm (01010101B) to register WRj. At the end of the operation,
WRj contains 00000000 01010101B.
Variations
MOVZ WRj,Rm
Binary Mode
Source Mode
Bytes:
States:
3
2
2
1
[Encoding]
0 0 0 0
1 0 1 0
t t t t
s s s s
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
MOVZ
(WRj)7–0 ← (Rm)7–0
(WRj)15–8 ← 0
A-100
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INSTRUCTION SET REFERENCE
MUL <dest>,<src>
Function:
Multiply
Description:
Multiplies the unsigned integer in the source register with the unsigned integer in the
destination register. Only register addressing is allowed.
For 8-bit operands, the result is 16 bits. The most significant byte of the result is stored in the
low byte of the word where the destination register resides. The least significant byte is
stored in the following byte register. The OV flag is set if the product is greater than 255
(0FFH); otherwise it is cleared.
For 16-bit operands, the result is 32 bits. The most significant word is stored in the low word
of the dword where the destination register resides. The least significant word is stored in
the following word register. In this operation, the OV flag is set if the product is greater than
0FFFFH, otherwise it is cleared. The CY flag is always cleared. The N flag is set when the
MSB of the result is set. The Z flag is set when the result is zero.
Flags:
CY
0
AC
—
OV
N
Z
✓
✓
✓
Example:
Register R1 contains 80 (50H or 10010000B) and register R0 contains 160 (0A0H or
10010000B). After executing the instruction
MUL R1,R0
which gives the product 12,800 (3200H), register R0 contains 32H (00110010B), register R1
contains 00H, the OV flag is set, and the CY flag is clear.
MUL Rmd,Rms
Binary Mode
Source Mode
Bytes:
States:
3
6
2
5
[Encoding]
1 0 1 0
1 1 0 0
s s s s
S S S S
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
MUL (8-bit operands)
if <dest> md = 0, 2, 4, .., 14
Rmd ← high byte of the Rmd X Rms
Rmd+1 ← low byte of the Rmd X Rms
if <dest> md = 1, 3, 5, .., 15
Rmd–1 ← high byte of the Rmd X Rms
Rmd ← low byte of the Rmd X Rms
A-101
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MUL WRjd,WRjs
Binary Mode
Source Mode
Bytes:
States:
3
2
12
11
[Encoding]
1 0 1 0
1 1 0 1
t t t t
t t t t
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
MUL (16-bit operands)
if <dest> jd = 0, 4, 8, .., 28
WRjd ← high word of the WRjd X WRjs
WRjd+2 ← low word of the WRjd X WRjs
if <dest> jd = 2, 6, 10, .., 30
WRjd–2 ← high word of the WRjd X WRjs
WRjd ← low word of the WRjd X WRjs
MUL AB
Function:
Description:
Multiply
Multiplies the unsigned 8-bit integers in the accumulator and register B. The low byte of the
16-bit product is left in the accumulator, and the high byte is left in register B. If the product is
greater than 255 (0FFH) the OV flag is set; otherwise it is clear. The CY flag is always clear.
Flags:
CY
0
AC
—
OV
N
Z
✓
✓
✓
Example:
The accumulator contains 80 (50H) and register B contains 160 (0A0H). After executing the
instruction
MUL AB
which gives the product 12,800 (3200H), register B contains 32H (00110010B), the
accumulator contains 00H, the OV flag is set, and the CY flag is clear.
Binary Mode
Source Mode
Bytes:
States:
1
5
1
5
[Encoding]
1 0 1 0
0 1 0 0
Hex Code in: Binary Mode = [Encoding]
Source Mode = [Encoding]
Operation:
MUL
(A) ← low byte of (A) X (B)
(B) ← high byte of (A) X (B)
A-102
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INSTRUCTION SET REFERENCE
NOP
Function:
No operation
Execution continues at the following instruction. Affects the PC register only.
Description:
Flags:
CY
—
AC
—
OV
—
N
Z
—
—
Example:
You want to produce a low-going output pulse on bit 7 of Port 2 that lasts exactly 11 states. A
simple CLR-SETB sequence generates an eight-state pulse. (Each instruction requires four
states to write to a port SFR.) You can insert three additional states (if no interrupts are
enabled) with the following instruction sequence:
CLR P2.7
NOP
NOP
NOP
SETB P2.7
Binary Mode
Source Mode
Bytes:
States:
1
1
1
1
[Encoding]
0 0 0 0
0 0 0 0
Hex Code in: Binary Mode = [Encoding]
Source Mode = [Encoding]
Operation:
NOP
(PC) ← (PC) + 1
ORL <dest> <src>
Function:
Logical-OR for byte variables
Description:
Performs the bitwise logical-OR operation (V) between the specified variables, storing the
results in the destination operand.
The destination operand can be a register, an accumulator or direct address.
The two operands allow twelve addressing mode combinations. When the destination is the
accumulator, the source can be register, direct, register-indirect, or immediate addressing;
when the destination is a direct address, the source can be the accumulator or immediate
data. When the destination is register the source can be register, immediate, direct and
indirect addressing.
Note: When this instruction is used to modify an output port, the value used as the original
port data is read from the output data latch, not the input pins.
Flags:
CY
—
AC
—
OV
—
N
Z
✓
✓
A-103
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Example:
The accumulator contains 0C3H (11000011B) and R0 contains 55H (01010101B). After
executing the instruction
ORL A,R0
the accumulator contains 0D7H (11010111B).
When the destination is a directly addressed byte, the instruction can set combinations of
bits in any RAM location or hardware register. The pattern of bits to be set is determined by
a mask byte, which may be a constant data value in the instruction or a variable computed in
the accumulator at run time. After executing the instruction
ORL P1,#00110010B
sets bits 5, 4, and 1 of output Port 1.
Variations
ORL dir8,A
Binary Mode
Source Mode
Bytes:
States:
2
2
2†
2†
†If this instruction addresses a port (Px, x = 0–3), add 2 states.
[Encoding]
0 1 0 0 0 0 1 0 direct addr
Hex Code in: Binary Mode = [Encoding]
Source Mode = [Encoding]
Operation:
ORL
(dir8) ← (dir8) V (A)
ORL dir8,#data
Binary Mode
Source Mode
Bytes:
States:
3
3
3†
3†
†If this instruction addresses a port (Px, x = 0–3), add 1 state.
[Encoding]
0 1 0 0 0 0 1 1 direct addr immed. data
Hex Code in: Binary Mode = [Encoding]
Source Mode = [Encoding]
Operation:
ORL
(dir8) ← (dir8) V #data
ORL A,#data
Binary Mode
Source Mode
Bytes:
States:
2
1
2
1
[Encoding]
0 1 0 0
0 1 0 0
immed. data
A-104
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INSTRUCTION SET REFERENCE
Hex Code in: Binary Mode = [Encoding]
Source Mode = [Encoding]
Operation:
ORL A,dir8
ORL
(A) ← (A) V #data
Binary Mode
Source Mode
Bytes:
States:
2
2
1†
1†
†If this instruction addresses a port (Px, x = 0–3), add 1 state.
[Encoding]
0 1 0 0 0 1 0 1 direct addr
Hex Code in: Binary Mode = [Encoding]
Source Mode = [Encoding]
Operation:
ORL A,@Ri
ORL
(A) ← (A) V (dir8)
Binary Mode
Source Mode
Bytes:
States:
1
2
2
3
[Encoding]
0 1 0 0
0 1 1 i
Hex Code in: Binary Mode = [Encoding]
Source Mode = [A5][Encoding]
Operation:
ORL A,Rn
ORL
(A) ← (A) V ((Ri))
Binary Mode
Source Mode
Bytes:
States:
1
1
2
2
[Encoding]
0 1 0 0
1 r r r
Hex Code in: Binary Mode = [Encoding]
Source Mode = [A5][Encoding]
Operation:
ORL
(A) ← (A) V (Rn)
ORL Rmd,Rms
Binary Mode
Source Mode
Bytes:
States:
3
2
2
1
[Encoding]
0 1 0 0
1 1 0 0
s s s s
S S S S
A-105
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Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
ORL
(Rmd) ← (Rmd) V (Rms)
ORL WRjd,WRjs
Binary Mode
Source Mode
Bytes:
States:
3
3
2
2
[Encoding]
0 1 0 0
1 1 0 1
t t t t
T T T T
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
ORL
(WRjd)←(WRjd) V (WRjs)
ORL Rm,#data
Binary Mode
Source Mode
Bytes:
States:
4
3
3
2
[Encoding]
0 1 0 0
1 1 1 0
s s s s
0 0 0 0
#data
Hex Code in
Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
ORL
(Rm) ← (Rm) V #data
ORL WRj,#data16
Binary Mode
Source Mode
Bytes:
5
4
4
3
States:
[Encoding]
0 1 0 0
1 1 1 0
t t t t
0 1 0 0
#data hi
#data low
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
ORL
(WRj) ← (WRj) V #data16
A-106
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ORL Rm,dir8
Binary Mode
Source Mode
Bytes:
States:
4
3
3†
2†
†If this instruction addresses a port (Px, x = 0–3), add 1 state.
[Encoding]
0 1 0 0
1 1 1 0
s s s s
0 0 0 1
direct addr
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
ORL
(Rm) ← (Rm) V (dir8)
ORL WRj,dir8
Binary Mode
Source Mode
Bytes:
States:
4
4
3
3
[Encoding]
0 1 0 0
1 1 1 1
t t t t
0101
direct addr
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
ORL
(WRj) ← (WRj) V (dir8)
ORL Rm,dir16
Binary Mode
Source Mode
Bytes:
5
3
4
2
States:
[Encoding]
0 1 0 0
1 1 1 0
s s s s
0 0 1 1
direct addr
direct addr
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
ORL
(Rm) ← (Rm) V (dir16)
ORL WRj,dir16
Binary Mode
Source Mode
Bytes:
States:
5
4
4
3
A-107
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[Encoding]
0 1 0 0
1 1 1 0
t t t t
0 1 1 1
direct addr
direct addr
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
ORL
(WRj) ← (WRj) V (dir16)
ORL Rm,@WRj
Binary Mode
Source Mode
Bytes:
4
3
3
2
States:
[Encoding]
0 1 0 0
1 1 1 0
t t t t
1 0 0 1
s s s s
0 0 0 0
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
ORL
(Rm) ← (Rm) V ((WRj))
ORL Rm,@DRk
Binary Mode
Source Mode
Bytes:
States:
4
4
3
3
[Encoding]
0 1 0 0
1 1 1 0
u u u u
1 0 1 1
s s s s
0 0 0 0
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
ORL
(Rm) ← (Rm) V ((DRk))
ORL CY,<src–bit>
Function:
Logical-OR for bit variables
Description:
Sets the CY flag if the Boolean value is a logical 1; leaves the CY flag in its current state
otherwise . A slash ("/") preceding the operand in the assembly language indicates that the
logical complement of the addressed bit is used as the source value, but the source bit itself
is not affected.
Flags:
CY
AC
—
OV
—
N
Z
✓
—
—
A-108
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INSTRUCTION SET REFERENCE
Example:
Set the CY flag if and only if P1.0 = 1, ACC. 7 = 1, or OV = 0:
MOV CY,P1.0
ORL CY,ACC.7 ;OR CARRY WITH THE ACC. BIT 7
ORL CY,/OV ;OR CARRY WITH THE INVERSE OF OV.
;LOAD CARRY WITH INPUT PIN P10
Variations
ORL CY,bit51
Binary Mode
Source Mode
Bytes:
States:
2
2
1†
1†
†If this instruction addresses a port (Px, x = 0–3), add 1 state.
[Encoding]
0 1 1 1 0 0 1 0 bit addr
Hex Code in: Binary Mode = [Encoding]
Source Mode = [Encoding]
Operation:
ORL
(CY) ← (CY) V (bit51)
ORL CY,/bit51
Binary Mode
Source Mode
Bytes:
States:
2
2
1†
1†
†If this instruction addresses a port (Px, x = 0–3), add 1 state.
[Encoding]
1 0 1 0 0 0 0 0 bit addr
Hex Code in: Binary Mode = [Encoding]
Source Mode = [Encoding]
Operation:
ORL CY,bit
ORL
(CY) ← (CY) V¬ (bit51)
Binary Mode
Source Mode
Bytes:
States:
4
3
3†
2†
†If this instruction addresses a port (Px, x = 0–3), add 1 state.
[Encoding]
1 0 1 0
1 0 0 1
0 1 1 1
0
y y y
direct addr
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
ORL
(CY) ← (CY) V (bit)
A-109
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ORL CY,/bit
Binary Mode
Source Mode
Bytes:
States:
4
3
3†
2†
†If this instruction addresses a port (Px, x = 0–3), add 1 state.
[Encoding]
1 0 1 0
1 0 0 1
1 1 1 0
0
y y y
direct addr
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
ORL
(CY) ← (CY) V ¬ (bit)
POP <src>
Function:
Pop from stack
Description:
Reads the contents of the on-chip RAM location addressed by the stack pointer, then
decrements the stack pointer by one. The value read at the original RAM location is
transferred to the newly addressed location, which can be 8-bit or 16-bit.
Flags:
CY
—
AC
—
OV
—
N
Z
—
—
Example:
The stack pointer contains 32H and on-chip RAM locations 30H through 32H contain 01H,
23H, and 20H, respectively. After executing the instruction sequence
POP DPH
POP DPL
the stack pointer contains 30H and the data pointer contains 0123H. After executing the
instruction
POP SP
the stack pointer contains 20H. Note that in this special case the stack pointer was
decremented to 2FH before it was loaded with the value popped (20H).
Variations
POP dir8
Binary Mode
Source Mode
Bytes:
States:
2
3
2
3
[Encoding]
1 1 0 1
0 0 0 0
direct addr
A-110
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INSTRUCTION SET REFERENCE
Hex Code in: Binary Mode = [Encoding]
Source Mode = [Encoding]
Operation:
POP
(dir8) ← ((SP))
(SP) ← (SP) – 1
POP Rm
Binary Mode
Source Mode
Bytes:
States:
3
3
2
2
[Encoding]
1 1 0 1
1 0 1 0
s s s s
1 0 0 0
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
POP
(Rm) ← ((SP))
(SP) ← (SP) – 1
POP WRj
Binary Mode
Source Mode
Bytes:
States:
3
5
2
4
[Encoding]
1 1 0 1
1 0 1 0
t t t t
1 0 0 1
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
POP
(SP) ← (SP) – 1
(WRj) ← ((SP))
(SP) ← (SP) – 1
POP DRk
Binary Mode
Source Mode
Bytes:
States:
3
2
9
10
[Encoding]
1 1 0 1
1 0 1 0
u u u u
1 0 1 1
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
POP
(SP) ← (SP) – 3
(DRk) ← ((SP))
(SP) ← (SP) – 1
A-111
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PUSH <dest>
Function:
Push onto stack
Description:
Increments the stack pointer by one. The contents of the specified variable are then copied
into the on-chip RAM location addressed by the stack pointer.
Flags:
CY
—
AC
—
OV
—
N
Z
—
—
Example:
On entering an interrupt routine, the stack pointer contains 09H and the data pointer
contains 0123H. After executing the instruction sequence
PUSH DPL
PUSH DPH
the stack pointer contains 0BH and on-chip RAM locations 0AH and 0BH contain 01H and
23H, respectively.
Variations
PUSH dir8
Binary Mode
Source Mode
Bytes:
States:
2
4
2
4
[Encoding]
1 1 0 0
0 0 0 0
direct addr
Hex Code in: Binary Mode = [Encoding]
Source Mode = [Encoding]
Operation:
PUSH
(SP) ← (SP) + 1
((SP)) ← (dir8)
PUSH #data
Binary Mode
Source Mode
Bytes:
States:
4
4
3
3
[Encoding]
1 1 0 0
1 0 1 0
0 0 0 0
0 0 1 0
#data
Hex Code in: Binary Mode = [Encoding]
Source Mode = [Encoding]
Operation:
PUSH
(SP) ← (SP) + 1
((SP)) ← #data
A-112
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INSTRUCTION SET REFERENCE
PUSH #data16
Binary Mode
Source Mode
Bytes:
5
6
4
5
States:
[Encoding]
1 1 0 0
1 0 1 0
0 0 0 0
0 1 1 0
#data hi
#data lo
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
PUSH
(SP) ← (SP) + 2
((SP)) ← MSB of #data16
((SP)) ← LSB of #data16
PUSH Rm
Binary Mode
Source Mode
Bytes:
States:
3
4
2
3
[Encoding]
1 1 0 0
1 0 1 0
s s s s
1 0 0 0
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
PUSH
(SP) ← (SP) + 1
((SP)) ← (Rm)
PUSH WRj
Binary Mode
Source Mode
Bytes:
States:
3
5
2
4
[Encoding]
1 1 0 0
1 0 1 0
t t t t
1 0 0 1
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
PUSH
(SP) ← (SP) + 1
((SP)) ← (WRj)
(SP) ¨ (SP) + 1
A-113
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PUSH DRk
Binary Mode
Source Mode
Bytes:
States:
3
9
2
8
[Encoding]
1 1 0 0
1 0 1 0
u u u u
1 0 1 1
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
PUSH
(SP) ← (SP) + 1
((SP)) ← (DRk)
(SP) ← (SP) + 3
RET
Function:
Description:
Return from subroutine
Pops the high and low bytes of the PC successively from the stack, decrementing the stack
pointer by two. Program execution continues at the resulting address, which normally is the
instruction immediately following ACALL or LCALL.
Flags:
CY
—
AC
—
OV
—
N
Z
—
—
Example:
The stack pointer contains 0BH and on-chip RAM locations 0AH and 0BH contain 01H and
23H, respectively. After executing the instruction,
RET
the stack pointer contains 09H and program execution continues at location 0123H.
Binary Mode
Source Mode
Bytes:
States:
1
7
1
7
[Encoding]
0 0 1 0
0 0 1 0
Hex Code in: Binary Mode = [Encoding]
Source Mode = [Encoding]
Operation:
RET
(PC).15:8 ← ((SP))
(SP) ← (SP) – 1
(PC).7:0 ← ((SP))
(SP) ← (SP) – 1
A-114
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RETI
Function:
Description:
Return from interrupt
This instruction pops two or four bytes from the stack, depending on the INTR bit in the
CONFIG1 register.
If INTR = 0, RETI pops the high and low bytes of the PC successively from the stack and
uses them as the 16-bit return address in region FF:. The stack pointer is decremented by
two. No other registers are affected, and neither PSW nor PSW1 is automatically restored to
its pre-interrupt status.
If INTR = 1, RETI pops four bytes from the stack: PSW1 and the three bytes of the PC. The
three bytes of the PC are the return address, which can be anywhere in the 16-Mbyte
memory space. The stack pointer is decremented by four. PSW1 is restored to its pre-
interrupt status, but PSW is not restored to its pre-interrupt status. No other registers are
affected.
For either value of INTR, hardware restores the interrupt logic to accept additional interrupts
at the same priority level as the one just processed. Program execution continues at the
return address, which normally is the instruction immediately after the point at which the
interrupt request was detected. If an interrupt of the same or lower priority is pending when
the RETI instruction is executed, that one instruction is executed before the pending
interrupt is processed.
Flags:
CY
—
AC
—
OV
—
N
Z
—
—
Example:
INTR = 0. The stack pointer contains 0BH. An interrupt was detected during the instruction
ending at location 0122H. On-chip RAM locations 0AH and 0BH contain 01H and 23H,
respectively. After executing the instruction
RETI
the stack pointer contains 09H and program execution continues at location 0123H.
Binary Mode
Source Mode
Bytes:
1
1
States (INTR = 0):
States (INTR = 1):
9
9
12
12
[Encoding]
0 0 1 1
0 0 1 0
Hex Code in: Binary Mode = [Encoding]
Source Mode = [Encoding]
Operation for INTR = 0:
RETI
(PC).15:8 ←((SP))
(SP) ← (SP) – 1
(PC).7:0 ← ((SP))
(SP) ←(SP) – 1
A-115
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Operation for INTR = 1:
RETI
(PC).15:8 ← ((SP))
(SP) ← (SP) – 1
PC).7:0 ← ((SP))
(SP) ← (SP) – 1
(PC).23:16 ← ((SP))
(SP) ← (SP) – 1
PSW1 ← ((SP))
(SP) ← (SP) – 1
RL A
Function:
Rotate accumulator left
Description:
Rotates the eight bits in the accumulator one bit to the left. Bit 7 is rotated into the bit 0
position.
Flags:
CY
—
AC
—
OV
—
N
Z
✓
✓
Example:
The accumulator contains 0C5H (11000101B). After executing the instruction,
RL A
the accumulator contains 8BH (10001011B); the CY flag is unaffected.
Binary Mode
Source Mode
Bytes:
States:
1
1
1
1
[Encoding]
0 0 1 0
0 0 1 1
Hex Code in: Binary Mode = [Encoding]
Source Mode = [Encoding]
Operation:
RL
(A).a+1 ← (A).a
(A).0 ← (A).7
RLC A
Function:
Description:
Rotate accumulator left through the carry flag
Rotates the eight bits in the accumulator and the CY flag one bit to the left. Bit 7 moves into
the CY flag position and the original state of the CY flag moves into bit 0 position.
Flags:
CY
AC
—
OV
—
N
Z
✓
✓
✓
A-116
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Example:
The accumulator contains 0C5H (11000101B) and the CY flag is clear. After executing the
instruction
RLC A
the accumulator contains 8AH (10001010B) and the CY flag is set.
Binary Mode
Source Mode
Bytes:
States:
1
1
1
1
[Encoding]
0 0 1 1
0 0 1 1
Hex Code in: Binary Mode = [Encoding]
Source Mode = [Encoding]
Operation:
RLC
(A).a+1 ← (A).a
(A).0 ← (CY)
(CY) ← (A) .7
RR A
Function:
Description:
Rotate accumulator right
Rotates the 8 or 16 bits in the accumulator one bit to the right. Bit 0 is moved into the bit 7 or
15 position.
Flags:
CY
—
AC
—
OV
—
N
Z
✓
✓
Example:
The accumulator contains 0C5H (11000101B). After executing the instruction
RR A
the accumulator contains 0E2H (11100010B) and the CY flag is unaffected.
Binary Mode
Source Mode
Bytes:
States:
1
1
1
1
[Encoding]
0 0 0 0
0 0 1 1
Hex Code in: Binary Mode = [Encoding]
Source Mode = [Encoding]
Operation:
RR
(A).a ← (A).a+1
(A).7 ← (A) .0
A-117
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RRC A
Function:
Rotate accumulator right through carry flag
Description:
Rotates the eight bits in the accumulator and the CY flag one bit to the right. Bit 0 moves into
the CY flag position; the original value of the CY flag moves into the bit 7 position.
Flags:
CY
AC
—
OV
—
N
Z
✓
✓
✓
Example:
The accumulator contains 0C5H (11000101B) and the CY flag is clear. After executing the
instruction
RRC A
the accumulator contains 62 (01100010B) and the CY flag is set.
Binary Mode
Source Mode
Bytes:
States:
1
1
1
1
[Encoding]
0 0 0 1
0 0 1 1
Hex Code in: Binary Mode = [Encoding]
Source Mode = [Encoding]
Operation:
RRC
(A).a ← (A).a+1
(A).7 ← (CY)
(CY) ← (A).0
SETB <bit>
Function:
Set bit
Description:
Sets the specified bit to one. SETB can operate on the CY flag or any directly addressable
bit.
Flags:
No flags are affected except the CY flag for instruction with CY as the operand.
CY
AC
—
OV
—
N
Z
✓
—
—
Example:
The CY flag is clear and output Port 1 contains 34H (00110100B). After executing the
instruction sequence
SETB CY
SETB P1.0
the CY flag is set and output Port 1 contains 35H (00110101B).
A-118
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INSTRUCTION SET REFERENCE
SETB bit51
Binary Mode
Source Mode
Bytes:
States:
2
2
2†
2†
†If this instruction addresses a port (Px, x = 0–3), add 2 states.
[Encoding]
1 1 0 1 0 0 1 0 bit addr
Hex Code in: Binary Mode = [Encoding]
Source Mode = [Encoding]
Operation:
SETB CY
SETB
(bit51) ← 1
Binary Mode
Source Mode
Bytes:
States:
1
1
1
1
[Encoding]
1 1 0 1
0 0 1 1
Hex Code in: Binary Mode = [Encoding]
Source Mode = [Encoding]
Operation:
SETB bit
SETB
(CY) ← 1
Binary Mode
Source Mode
Bytes:
States:
4
3
4†
3†
†If this instruction addresses a port (Px, x = 0–3), add 2 states.
[Encoding]
1 0 1 0
1 0 0 1
1 1 0 1
0
y y y
direct addr
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
SETB
(bit) ← 1
SJMP rel
Function:
Description:
Short jump
Program control branches unconditionally to the specified address. The branch destination
is computed by adding the signed displacement in the second instruction byte to the PC,
after incrementing the PC twice. Therefore, the range of destinations allowed is from 128
bytes preceding this instruction to 127 bytes following it.
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Flags:
CY
—
AC
—
OV
—
N
Z
—
—
Example:
The label "RELADR" is assigned to an instruction at program memory location 0123H. The
instruction
SJMP RELADR
assembles into location 0100H. After executing the instruction, the PC contains 0123H.
(Note: In the above example, the instruction following SJMP is located at 102H. Therefore,
the displacement byte of the instruction is the relative offset (0123H–0102H) = 21H. Put
another way, an SJMP with a displacement of 0FEH would be a one-instruction infinite loop.)
Binary Mode
Source Mode
Bytes:
States:
2
4
2
4
[Encoding]
1 0 0 0
0 0 0 0
rel. addr
Hex Code in: Binary Mode = [Encoding]
Source Mode = [Encoding]
Operation:
SJMP
(PC) ← (PC) + 2
(PC) ← (PC) + rel
SLL <src>
Function:
Shift logical left by 1 bit
Description:
Shifts the specified variable to the left by 1 bit, replacing the LSB with zero. The bit shifted
out (MSB) is stored in the CY bit.
Flags:
CY
AC
—
OV
—
N
Z
✓
✓
✓
Example:
Register 1 contains 0C5H (11000101B). After executing the instruction
SLL register 1
Register 1 contains 8AH (10001010B) and CY = 1.
Variations
SLL Rm
Binary Mode
Source Mode
Bytes:
States:
3
2
2
1
[Encoding]
0 0 1 1
1 1 1 0
s s s s
0 0 0 0
A-120
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Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
SLL
(Rm).a+1 ← (Rm).a
(Rm).0 ← 0
CY ← (Rm).7
SLL WRj
Binary Mode
Source Mode
Bytes:
States:
3
2
2
1
[Encoding]
0 0 1 1
1 1 1 0
t t t t
0 1 0 0
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
SLL
WRj).b+1 ← (WRj).b
(WRj).0 ← 0
CY ← (WRj).15
SRA <src>
Function:
Shift arithmetic right by 1 bit
Description:
Flags:
Shifts the specified variable to the arithmetic right by 1 bit. The MSB is unchanged. The bit
shifted out (LSB) is stored in the CY bit.
CY
AC
—
OV
—
N
Z
✓
✓
✓
Example:
Register 1 contains 0C5H (11000101B). After executing the instruction
SRA register 1
Register 1 contains 0E2H (11100010B) and CY = 1.
Variations
SRA Rm
Binary Mode
Source Mode
Bytes:
States:
3
2
2
1
[Encoding]
0 0 0 0
1 1 1 0
s s s s
0 0 0 0
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
SRA
(Rm).7 ← (Rm).7
(Rm).a ← (Rm).a+1
CY ← (Rm).0
A-121
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SRA WRj
Binary Mode
Source Mode
Bytes:
States:
3
2
2
1
[Encoding]
0 0 0 0
1 1 1 0
t t t t
0 1 0 0
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
SRA
(WRj).15 ← (WRj).15
(WRj).b ← (WRj).b+1
CY ← (WRj).0
SRL <src>
Function:
Shift logical right by 1 bit
Description:
SRL shifts the specified variable to the right by 1 bit, replacing the MSB with a zero. The bit
shifted out (LSB) is stored in the CY bit.
Flags:
CY
AC
—
OV
—
N
Z
✓
✓
✓
Example:
Register 1 contains 0C5H (11000101B). After executing the instruction
SRL register 1
Register 1 contains 62H (01100010B) and CY = 1.
Variations
SRL Rm
Binary Mode
Source Mode
Bytes:
States:
3
2
2
1
[Encoding]
0 0 0 1
1 1 1 0
s s s s
0 0 0 0
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
SRL
(Rm).7 ← 0
(Rm).a ← (Rm).a+1
CY ← (Rm).0
A-122
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SRL WRj
Binary Mode
Source Mode
Bytes:
States:
3
2
2
1
[Encoding]
0 0 0 1
1 1 1 0
t t t t
0 1 0 0
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
SRL
(WRj).15 ← 0
(WRj).b ← (WRj).b+1
CY← (WRj).0
SUB <dest>,<src>
Function:
Subtract
Description:
Subtracts the specified variable from the destination operand, leaving the result in the
destination operand. SUB sets the CY (borrow) flag if a borrow is needed for bit 7.
Otherwise, CY is clear.
When subtracting signed integers, the OV flag indicates a negative number produced when
a negative value is subtracted from a positive value, or a positive result when a positive
number is subtracted from a negative number.
Bit 7 in this description refers to the most significant byte of the operand (8, 16, or 32 bit).
The source operand allows four addressing modes: immediate, indirect, register and direct.
Flags:
CY
AC
OV
N
Z
✓
✓†
✓
✓
✓
†For word and dword subtractions, AC is not affected.
Example:
Register 1 contains 0C9H (11001001B) and register 0 contains 54H (01010100B). After
executing the instruction
SUB R1,R0
register 1 contains 75H (01110101B), the CY and AC flags are clear, and the OV flag is set.
Variations
SUB Rmd,Rms
Binary Mode
Source Mode
Bytes:
States:
3
2
2
1
[Encoding]
1 0 0 1
1 1 0 0
s s s s
S S S S
A-123
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Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
SUB
(Rmd) ← (Rmd) – (Rms)
SUB WRjd,WRjs
Binary Mode
Source Mode
Bytes:
States:
3
3
2
2
[Encoding]
1 0 0 1
1 1 0 1
t t t t
T T T T
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
SUB
(WRjd) ← (WRjd) – (WRjs)
SUB DRkd,DRks
Binary Mode
Source Mode
Bytes:
States:
3
5
2
4
[Encoding]
1 0 0 1
1 1 1 1
u u u u
U U U U
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
SUB
(DRkd) ← (DRkd) – (DRks)
SUB Rm,#data
Binary Mode
Source Mode
Bytes:
States:
4
3
3
2
[Encoding]
1 0 0 1
1 1 1 0
s s s s
0 0 0 0
#data
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
SUB
(Rm) ← (Rm) – #data
SUB WRj,#data16
Binary Mode
Source Mode
Bytes:
States:
5
4
4
3
A-124
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INSTRUCTION SET REFERENCE
[Encoding]
1 0 0 1
1 1 1 0
t t t t
0 1 0 0
#data hi
#data low
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
SUB
(WRj) ← (WRj) – #data16
SUB DRk,#data16
Binary Mode
Source Mode
Bytes:
5
6
4
5
States:
[Encoding]
1 0 0 1
1 1 1 0
u u u u
1 0 0 0
#data hi
#data low
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
SUB
(DRk) ← (DRk) – #data16
SUB Rm,dir8
Binary Mode
Source Mode
Bytes:
States:
4
3
3†
2†
†If this instruction addresses a port (Px, x = 0–3), add 1 state.
[Encoding]
1 0 0 1 1 1 1 0 s s s s 0 0 0 1
direct addr
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
SUB
(Rm) ← (Rm) – (dir8)
SUB WRj,dir8
Binary Mode
Source Mode
Bytes:
States:
4
4
3
3
[Encoding]
1 0 0 1
1 1 1 0
t t t t
0 1 0 1
direct addr
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
SUB
(WRj) ← (WRj) – (dir8)
A-125
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SUB Rm,dir16
Binary Mode
Source Mode
Bytes:
5
3
4
2
States:
[Encoding]
1 0 0 1
1 1 1 0
s s s s
0 0 1 1
direct addr
direct addr
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
SUB
(Rm) ← (Rm) – (dir16)
SUB WRj,dir16
Binary Mode
Source Mode
Bytes:
5
4
4
3
States:
[Encoding]
1 0 0 1
1 1 1 0
t t t t
0 1 1 1
direct addr
direct addr
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
SUB
(WRj) ← (WRj) – (dir16)
SUB Rm,@WRj
Binary Mode
Source Mode
Bytes:
4
3
3
2
States:
[Encoding]
1 0 0 1
1 1 1 0
t t t t
1 0 0 1
s s s s
0 0 0 0
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
SUB
(Rm) ← (Rm) – ((WRj))
SUB Rm,@DRk
Binary Mode
Source Mode
Bytes:
States:
4
4
3
3
A-126
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INSTRUCTION SET REFERENCE
[Encoding]
1 0 0 1
1 1 1 0
u u u u
1 0 1 1
s s s s
0 0 0 0
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
SUB
(Rm) ← (Rm) – ((DRk))
SUBB A,<src–byte>
Function:
Subtract with borrow
Description:
SUBB subtracts the specified variable and the CY flag together from the accumulator,
leaving the result in the accumulator. SUBB sets the CY (borrow) flag if a borrow is needed
for bit 7, and clears CY otherwise. (If CY was set before executing a SUBB instruction, this
indicates that a borrow was needed for the previous step in a multiple precision subtraction,
so the CY flag is subtracted from the accumulator along with the source operand.) AC is set
if a borrow is needed for bit 3, and cleared otherwise. OV is set if a borrow is needed into bit
6, but not into bit 7, or into bit 7, but not bit 6.
When subtracting signed integers the OV flag indicates a negative number produced when a
negative value is subtracted from a positive value, or a positive result when a positive
number is subtracted from a negative number.
Bit 6 and bit 7 in this description refer to the most significant byte of the operand (8, 16, or 32
bit).
The source operand allows four addressing modes: register, direct, register-indirect, or
immediate.
Flags:
CY
AC
OV
N
Z
✓
✓
✓
✓
✓
Example:
The accumulator contains 0C9H (11001001B), register 2 contains 54H (01010100B), and
the CY flag is set. After executing the instruction
SUBB A,R2
the accumulator contains 74H (01110100B), the CY and AC flags are clear, and the OV flag
is set.
Notice that 0C9H minus 54H is 75H. The difference between this and the above result is due
to the CY (borrow) flag being set before the operation. If the state of the carry is not known
before starting a single or multiple-precision subtraction, it should be explicitly cleared by a
CLR CY instruction.
Variations
SUBB A,#data
Binary Mode
Source Mode
Bytes:
States:
2
1
2
1
A-127
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[Encoding]
1 0 0 1
0 1 0 0
immed. data
Hex Code in: Binary Mode = [Encoding]
Source Mode = [Encoding]
Operation:
SUBB
(A) ← (A) – (CY) – #data
SUBB A,dir8
Binary Mode
Source Mode
Bytes:
States:
2
2
1†
1†
†If this instruction addresses a port (Px, x = 0–3), add 1 state.
[Encoding]
1 0 0 1 0 1 0 1 direct addr
Hex Code in: Binary Mode = [Encoding]
Source Mode = [Encoding]
Operation:
SUBB
(A) ← (A) – (CY) – (dir8)
SUBB A,@Ri
Binary Mode
Source Mode
Bytes:
States:
1
2
2
3
[Encoding]
1 0 0 1
0 1 1 i
Hex Code in: Binary Mode = [Encoding]
Source Mode = [A5][Encoding]
Operation:
SUBB A,Rn
SUBB
(A) ← (A) – (CY) – ((Ri))
Binary Mode
Source Mode
Bytes:
States:
1
1
2
2
[Encoding]
1 0 0 1
1 r r r
Hex Code in: Binary Mode = [Encoding]
Source Mode = [A5][Encoding]
Operation:
SUBB
(A) ← (A) – (CY) – (Rn)
A-128
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INSTRUCTION SET REFERENCE
SWAP A
Function:
Description:
Swap nibbles within the accumulator
Interchanges the low and high nibbles (4-bit fields) of the accumulator (bits 3–0 and bits 7–
4). This operation can also be thought of as a 4-bit rotate instruction.
Flags:
CY
—
AC
—
OV
—
N
Z
—
—
Example:
The accumulator contains 0C5H (11000101B). After executing the instruction
SWAP A
the accumulator contains 5CH (01011100B).
Binary Mode
Source Mode
Bytes:
States:
1
2
1
2
[Encoding]
1 1 0 0
0 1 0 0
Hex Code in: Binary Mode = [Encoding]
Source Mode = [Encoding]
Operation:
SWAP
(A).3:0 → ← (A).7:4
TRAP
Function:
Description:
Causes interrupt call
Causes an interrupt call that is vectored through location 0FF007BH. The operation of this
instruction is not affected by the state of the interrupt enable flag in PSW0 and PSW1.
Interrupt calls can not occur immediately following this instruction. This instruction is
intended for use by Intel-provided development tools. These tools do not support user
application of this instruction.
Flags:
CY
—
AC
—
OV
—
N
Z
—
—
Example:
The instruction
TRAP
causes an interrupt call to location 0FF007BH during normal operation.
A-129
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Binary Mode
Source Mode
Bytes:
2
1
States (2 bytes):
States (4 bytes):
11
16
10
15
[Encoding]
1 0 1 1
1 0 0 1
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
TRAP
SP ← SP – 2
(SP) ← PC
PC ← (0FF007BH)
XCH A,<byte>
Function:
Exchange accumulator with byte variable
Description:
Loads the accumulator with the contents of the specified variable, at the same time writing
the original accumulator contents to the specified variable. The source/destination operand
can use register, direct, or register-indirect addressing.
Flags:
CY
—
AC
—
OV
—
N
Z
—
—
Example:
R0 contains the address 20H, the accumulator contains 3FH (00111111B) and on-chip RAM
location 20H contains 75H (01110101B). After executing the instruction
XCH A,@R0
RAM location 20H contains 3FH (00111111B) and the accumulator contains 75H
(01110101B).
Variations
XCH A,dir8
Binary Mode
Source Mode
Bytes:
States:
2
2
3†
3†
†If this instruction addresses a port (Px, x = 0–3), add 2 states.
[Encoding]
1 1 0 0 0 1 0 1 direct addr
Hex Code in: Binary Mode = [Encoding]
Source Mode = [Encoding]
Operation:
XCH
(A) → ← (dir8)
A-130
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INSTRUCTION SET REFERENCE
XCH A,@Ri
Binary Mode
Source Mode
Bytes:
States:
1
4
2
5
[Encoding]
1 1 0 0
0 1 1 i
Hex Code in: Binary Mode = [Encoding]
Source Mode = [A5][Encoding]
Operation:
XCH A,Rn
XCH
(A) → ← ((Ri))
Binary Mode
Source Mode
Bytes:
States:
1
3
2
4
[Encoding]
1 1 0 0
1 r r r
Hex Code in: Binary Mode = [Encoding]
Source Mode = [A5][Encoding]
Operation:
XCH
(A) → ← (Rn)
Variations
XCHD A,@Ri
Function:
Exchange digit
Description:
Exchanges the low nibble of the accumulator (bits 3-0), generally representing a
hexadecimal or BCD digit, with that of the on-chip RAM location indirectly addressed by the
specified register. Does not affect the high nibble (bits 7-4) of either register.
Flags:
CY
—
AC
—
OV
—
N
Z
—
—
Example:
R0 contains the address 20H, the accumulator contains 36H (00110110B), and on-chip RAM
location 20H contains 75H (01110101B). After executing the instruction
XCHD A,@R0
on-chip RAM location 20H contains 76H (01110110B) and 35H (00110101B) in the accumu-
lator.
A-131
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Binary Mode
Source Mode
Bytes:
States:
1
4
2
5
[Encoding]
1 1 0 1
0 1 1 i
Hex Code in: Binary Mode = [Encoding]
Source Mode = [Encoding]
Operation:
XCHD
(A).3:0 → ← ((Ri)).3:0
XRL <dest>,<src>
Function:
Logical Exclusive-OR for byte variables
Description:
Performs the bitwise logical Exclusive-OR operation (∀) between the specified variables,
storing the results in the destination. The destination operand can be the accumulator, a
register, or a direct address.
The two operands allow 12 addressing mode combinations. When the destination is the
accumulator or a register, the source addressing can be register, direct, register-indirect, or
immediate; when the destination is a direct address, the source can be the accumulator or
immediate data.
(Note: When this instruction is used to modify an output port, the value used as the original
port data is read from the output data latch, not the input pins.)
Flags:
CY
—
AC
—
OV
—
N
Z
✓
✓
Example:
The accumulator contains 0C3H (11000011B) and R0 contains 0AAH (10101010B). After
executing the instruction
XRL A,R0
the accumulator contains 69H (01101001B).
When the destination is a directly addressed byte, this instruction can complement combina-
tions of bits in any RAM location or hardware register. The pattern of bits to be comple-
mented is then determined by a mask byte, either a constant contained in the instruction or
a variable computed in the accumulator at run time. The instruction
XRL P1,#00110001B
complements bits 5, 4, and 0 of output Port 1.
Variations
XRL dir8,A
Binary Mode
Source Mode
Bytes:
States:
2
2
2†
2†
†If this instruction addresses a port (Px, x = 0–3), add 2 states.
A-132
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INSTRUCTION SET REFERENCE
[Encoding]
0 1 1 0
0 0 1 0
direct addr
Hex Code in: Binary Mode = [Encoding]
Source Mode = [Encoding]
Operation:
XRL
(dir8) ← (dir8) ∀ (A)
XRL dir8,#data
Binary Mode
Source Mode
Bytes:
States:
3
3
3†
3†
†If this instruction addresses a port (Px, x = 0–3), add 1 state.
[Encoding]
0 1 1 0
0 0 1 1
direct addr
immed. data
Hex Code in: Binary Mode = [Encoding]
Source Mode = [Encoding]
Operation:
XRL
(dir8) ← (dir8) ∀ #data
XRL A,#data
Binary Mode
Source Mode
Bytes:
States:
2
1
2
1
[Encoding]
0 1 1 0
0 1 0 0
immed. data
Hex Code in: Binary Mode = [Encoding]
Source Mode = [Encoding]
Operation:
XRL A,dir8
XRL
(A) ← (A) ∀ #data
Binary Mode
Source Mode
Bytes:
States:
2
2
1†
1†
†If this instruction addresses a port (Px, x = 0–3), add 1 state.
[Encoding]
0 1 1 0 0 1 0 1 direct addr
Hex Code in: Binary Mode = [Encoding]
Source Mode = [Encoding]
Operation:
XRL
(A) ← (A) ∀ (dir8)
A-133
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XRL A,@Ri
Binary Mode
Source Mode
Bytes:
States:
1
2
2
3
[Encoding]
0 1 1 0
0 1 1 i
Hex Code in: Binary Mode = [Encoding]
Source Mode = [A5][Encoding]
Operation:
XRL A,Rn
XRL
(A) ← (A) ∀ ((Ri))
Binary Mode
Source Mode
Bytes:
States:
1
1
2
2
[Encoding]
0 1 1 0
1 r r r
Hex Code in: Binary Mode = [Encoding]
Source Mode = [A5][Encoding]
Operation:
XRL
(A) ← (A) ∀ (Rn)
XRL Rmd,Rms
Binary Mode
Source Mode
Bytes:
States:
3
2
2
1
[Encoding]
0 1 1 0
1 1 0 0
s s s s
S S S S
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
XRL
(Rmd) ← (Rmd) ∀ (Rms)
XRL WRjd,WRjs
Binary Mode
Source Mode
Bytes:
States:
3
3
2
2
[Encoding]
0 1 1 0
1 1 0 1
t t t t
T T T T
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
A-134
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INSTRUCTION SET REFERENCE
Operation:
XRL
(WRds) ← (WRjd) ∀ (WRjs)
XRL Rm,#data
Binary Mode
Source Mode
Bytes:
States:
4
3
3
2
[Encoding]
0 1 1 0
1 1 1 0
s s s s
0 0 0 0
#data
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
XRL
(Rm) ← (Rm) ∀ #data
XRL WRj,#data16
Binary Mode
Source Mode
Bytes:
5
4
4
3
States:
[Encoding]
0 1 1 0
1 1 1 0
t t t t
0 1 0 0
#data hi
#data low
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
XRL
(WRj) ← (WRj) ∀ #data16
XRL Rm,dir8
Binary Mode
Source Mode
Bytes:
States:
4
3
3†
2†
†If this instruction addresses a port (Px, x = 0–3), add 1 state.
[Encoding]
0 1 1 0 1 1 1 0 s s s s 0 0 0 1
direct addr
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
XRL
(Rm) ← (Rm) ∀ (dir8)
XRL WRj,dir8
Binary Mode
Source Mode
Bytes:
States:
4
4
3
3
[Encoding]
0 1 1 0
1 1 1 0
t t t t
0 1 0 1
direct addr
A-135
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Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
XRL
(WRj) ← (WRj) ∀ (dir8)
XRL Rm,dir16
Binary Mode
Source Mode
Bytes:
5
3
4
2
States:
[Encoding]
0 1 1 0
1 1 1 0
s s s s
0 0 1 1
direct addr
dir8 addr
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
XRL
(Rm) ← (Rm) ∀ (dir16)
\XRL WRj,dir16
Binary Mode
Source Mode
Bytes:
5
4
4
3
States:
[Encoding]
0 1 1 0
1 1 1 0
t t t t
0 1 1 1
direct addr
direct addr
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
XRL
(WRj) ← (WRj) ∀ (dir16)
XRL Rm,@Wrj
Binary Mode
Source Mode
Bytes:
4
3
3
2
States:
[Encoding]
0 1 1 0
1 1 1 0
t t t t
1 0 0 1
s s s s
0 0 0 0
Hex Code in: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
XRL
(Rm) ← (Rm) ∀ ((WRj))
A-136
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INSTRUCTION SET REFERENCE
XRL Rm,@Drk
Binary Mode
Source Mode
Bytes:
4
4
3
3
States:
[Encoding]
0 1 1 0
1 1 1 0
u u u u
1 0 1 1
s s s s
0 0 0 0
Hex Code In: Binary Mode = [A5][Encoding]
Source Mode = [Encoding]
Operation:
XRL
(Rm) ← (Rm) ∀ ((DRk))
A-137
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B
Signal Descriptions
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SIGNAL DESCRIPTIONS
signments are shown in Figures B-1 (PLCC package) and B-2 (DIP package) and are listed by
functional category in Table B-1.
Table B-2 describes each of the signals. It lists the signal type (input, output, power, or ground)
and the alternative functions of multifunction pins. Table B-3 shows how configuration bits
RD1:0 (referred to in Table B-2) configure the A17, A16. RD#, WR# and PSEN# pins for exter-
nal memory accesses.
P1.5 / CEX2
P1.6 / CEX3 / WAIT#
P1.7 / CEX4 / A17 / WCLK
RST
7
8
9
39
38
37
36
35
34
33
32
31
30
29
AD4 / P0.4
AD5 / P0.5
AD6 / P0.6
AD7 / P0.7
8XC251SA
8XC251SB
8XC251SP
8XC251SQ
10
11
12
13
14
15
16
17
P3.0 / RXD
EA# / V
PP
V
V
CC2
SS2
P3.1 / TXD
P3.2 / INT0#
P3.3 / INT1#
P3.4 / T0
ALE / PROG#
PSEN#
A15 / P2.7
A14 / P2.6
A13 / P2.5
View of component as
mounted on PC board
P3.5 / T1
A4205-02
Figure B-1. 8XC251SA, SB, SP, SQ 44-pin PLCC Package
B-1
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Table B-1. PLCC/DIP Pin Assignments Listed by Functional Category
Address & Data
Name PLCC
AD0/P0.0
Input/Output
Name PLCC
DIP
39
38
37
36
35
34
33
32
21
22
23
24
25
26
27
28
17
8
DIP
1
43
42
41
40
39
38
37
36
24
25
26
27
28
29
30
31
19
9
P1.0/T2
2
3
AD1/P0.1
AD2/P0.2
AD3/P0.3
AD4/P0.4
AD5/P0.5
AD6/P0.6
AD7/P0.7
A8/P2.0
P1.1/T2EX
P1.2/ECI
2
4
3
P1.3/CEX0
P1.4/CEX1
P1.5/CEX2
P1.6/CEX3/WAIT#
P1.7/CEX4/A17WCLK
P3.0/RXD
5
4
6
5
7
6
8
7
9
8
11
13
16
17
10
11
14
15
A9/P2.1
P3.1/TXD
A10/P2.2
P3.4/T0
A11/P2.3
P3.5/T1
A12/P2.4
A13/P2.5
Power & Ground
A14/P2.6
Name
PLCC
44
DIP
A15/P2.7
VCC
40
P3.7/RD#/A16
P1.7/CEX4/A17/WCLK
VCC2
VSS
12
22
20
31
VSS1
VSS2
1
23, 34
35
Processor Control
Name PLCC
EA#/V
PP
DIP
12
13
31
9
P3.2/INT0#
P3.3/INT1#
EA#/VPP
RST
14
15
35
10
21
20
Bus Control & Status
Name
PLCC
18
DIP
P3.6/WR#
P3.7/RD#/A16
ALE/PROG#
PSEN#
16
19
17
30
29
XTAL1
18
19
33
XTAL2
32
B-2
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SIGNAL DESCRIPTIONS
V
P1.0 / T2
P1.1 / T2EX
P1.2 / ECI
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
1
CC
AD0 / P0.0
AD1 / P0.1
AD2 / P0.2
AD3 / P0.3
AD4 / P0.4
AD5 / P0.5
AD6 / P0.6
AD7 / P0.7
2
3
P1.3 / CEX0
P1.4 / CEX1
P1.5 / CEX2
P1.6 / CEX3 / WAIT#
P1.7 / CEX4 / A17 / WCLK
RST
4
5
8XC251SA
8XC251SB
8XC251SP
8XC251SQ
6
7
8
9
V
P3.0 / RXD
EA# /
10
11
12
13
14
15
16
17
18
19
20
PP
P3.1 / TXD
ALE / PROG#
PSEN#
P3.2 / INT0#
P3.3 / INT1#
P3.4 / T0
A15 / P2.7
A14 / P2.6
A13 / P2.5
A12 / P2.4
A11 / P2.3
A10 / P2.2
A9 / P2.1
View of
component
as mounted
on PC board
P3.5 / T1
P3.6 / WR#
P3.7 / RD# / A16
XTAL2
XTAL1
V
A8 / P2.0
SS
A4206-03
Figure B-2. 8XC251SA, SB, SP, SQ 40-pin PDIP and Ceramic DIP Packages
Table B-2. Signal Descriptions
Signal
Name
Alternate
Function
Type
Description
A17
O
Address Line A17. Eighteenth external address bit (A17) in
extended bus applications. Selected by configuration byte
UCONFIG0, bits RD1:0 (Table B-3). Also see RD# and PSEN#.
P1.7/CEX4/
WCLK
A16
O
Address Line A16. Seventeenth external address bit (A16) in
extended bus applications. Selected by configuration byte
UCONFIG0, bits RD1:0 (Table B-3). Also see RD#.
P3.7/RD#
†
A15:8
O
Address Lines. Upper address lines for the external bus.
P2.7:0
P0.7:0
†
AD7:0
I/O
Address/Data Lines. Multiplexed lower address lines and data
lines for external memory.
ALE
O
Address Latch Enable. ALE signals the start of an external bus
cycle and indicates that valid address information is available on
lines A15:8 and AD7:0. An external latch can use ALE to
demultiplex the address from the address/data bus.
PROG#
†
The descriptions of A15:8/P2.7:0 and AD7:0/P0.7:0 are for the nonpage mode chip configuration (com-
patible with 44-pin PLCC and 40-pin DIP MCS 51 microcontrollers). If the chip is configured for page
®
mode operation, port 0 carries the lower address bits (A7:0), and port 2 carries the upper address bits
(A15:8) and the data (D7:0).
B-3
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8XC251SA, SB, SP, SQ USER’S MANUAL
Table B-2. Signal Descriptions (Continued)
Signal
Name
Alternate
Function
Type
Description
CEX2:0
CEX3
CEX4
I/O
Programmable Counter Array (PCA) Input/Output Pins. These
are input signals for the PCA capture mode and output signals for
the PCA compare mode and PCA PWM mode.
P1.5:3
P1.6/WAIT#
P1.7/A17/WCLK
EA#
I
External Access. Directs program memory accesses to on-chip or VPP
off-chip code memory. For EA# = 0, all program memory accesses
are off-chip. For EA# = 1, an access is to on-chip program memory
if the address is within the range of the on-chip program memory;
otherwise the access is off-chip. The value of EA# is latched at
reset. For devices without on-chip program memory, EA# must be
strapped to ground.
ECI
I
I
PCA External Clock Input. External clock input to the 16-bit PCA P1.2
timer.
INT1:0#
External Interrupts 0 and 1. These inputs set bits IE1:0 in the
TCON register. If bits IT1:0 in the TCON register are set, bits IE1:0
are set by a falling edge on INT1#/INT0#. If bits INT1:0 are clear,
bits IE1:0 are set by a low level on INT1:0#.
P3.3:2
P0.7:0
I/O
I/O
Port 0. This is an 8-bit, open-drain, bidirectional I/O port.
AD7:0
P1.0
P1.1
P1.2
P1.5:3
P1.6
P1.7
Port 1. This is an 8-bit, bidirectional I/O port with internal pullups.
T2
T2EX
ECI
CEX2:0
CEX3/WAIT#
CEX4/A17/WCLK
P2.7:0
I/O
I/O
Port 2. This is an 8-bit, bidirectional I/O port with internal pullups.
Port 3. This is an 8-bit, bidirectional I/O port with internal pullups.
A15:8
P3.0
P3.1
RXD
TXD
P3.3:2
P3.5:4
P3.6
INT1:0#
T1:0
WR#
P3.7
RD#/A16
PROG#
PSEN#
I
for programming the on-chip nonvolatile memory.
O
Program Store Enable. Read signal output to external memory.
Asserted for the address range specified by configuration byte
UCONFIG0, bits RD1:0 (Table B-3). Also see RD#.
—
RD#
O
Read. Read signal output to external data memory. Asserted for
the address range specified by configuration byte UCONFIG0, bits
RD1:0 (Table B-3). Also see PSEN# and A16.
P3.7/A16
†
The descriptions of A15:8/P2.7:0 and AD7:0/P0.7:0 are for the nonpage mode chip configuration (com-
patible with 44-pin PLCC and 40-pin DIP MCS 51 microcontrollers). If the chip is configured for page
®
mode operation, port 0 carries the lower address bits (A7:0), and port 2 carries the upper address bits
(A15:8) and the data (D7:0).
B-4
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SIGNAL DESCRIPTIONS
Table B-2. Signal Descriptions (Continued)
Signal
Name
Alternate
Function
Type
Description
RST
I
Reset. Reset input to the chip. Holding this pin high for 64 oscillator
periods while the oscillator is running resets the device. The port
pins are driven to their reset conditions when a voltage greater than
—
V
is applied, whether or not the oscillator is running. This signal
IH1
has a Schmitt trigger input. Connecting the RST pin to V through
CC
a capacitor provides power-on reset.
Asserting RST when the chip is in idle mode or powerdown mode
returns the chip to normal operation.
RXD
T1:0
T2
I/O
I
Receive Serial Data. RXD sends and receives data in serial I/O
mode 0 and receives data in serial I/O modes 1, 2, and 3.
P3.0
Timer 1:0 External Clock Inputs. When timer 1:0 operates as a
counter, a falling edge on the T1:0 pin increments the count.
P3.5:4
P1.0
I/O
Timer 2 Clock Input/Output. For the timer 2 capture mode, this
signal is the external clock input. For the clock-out mode, it is the
timer 2 clock output.
T2EX
TXD
I
Timer 2 External Input. In timer 2 capture mode, a falling edge
initiates a capture of the timer 2 registers. In auto-reload mode, a
falling edge causes the timer 2 registers to be reloaded. In the up-
down counter mode, this signal determines the count direction: 1 =
up, 0 = down.
P1.1
O
Transmit Serial Data. TXD outputs the shift clock in serial I/O
P3.1
mode 0 and transmits serial data in serial I/O modes 1, 2, and 3.
VCC
PWR Supply Voltage. Connect this pin to the +5V supply voltage.
—
—
VCC2
PWR Secondary Supply Voltage 2. This supply voltage connection is
provided to reduce power supply noise. Connection of this pin to
the +5V supply voltage is recommended. However, when using the
8XC251SB as a pin-for-pin replacement for the 8XC51FX, VSS2 can
be unconnected without loss of compatibility. (Not available on
DIP.)
VPP
I
Programming Supply Voltage. The programming supply voltage
EA#
is applied to this pin for programming on-chip nonvolatile memory.
VSS
GND Circuit Ground. Connect this pin to ground.
—
—
VSS1
GND Secondary Ground. This ground is provided to reduce ground
bounce and improve power supply bypassing. Connection of this
pin to ground is recommended. However, when using the
8XC251SA, SB, SP, SQ as a pin-for-pin replacement for the
8XC51BH, VSS1 can be unconnected without loss of compatibility.
(Not available on DIP.)
†
The descriptions of A15:8/P2.7:0 and AD7:0/P0.7:0 are for the nonpage mode chip configuration (com-
patible with 44-pin PLCC and 40-pin DIP MCS 51 microcontrollers). If the chip is configured for page
®
mode operation, port 0 carries the lower address bits (A7:0), and port 2 carries the upper address bits
(A15:8) and the data (D7:0).
B-5
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8XC251SA, SB, SP, SQ USER’S MANUAL
Table B-2. Signal Descriptions (Continued)
Signal
Name
Alternate
Function
Type
Description
VSS2
GND Secondary Ground 2. This ground is provided to reduce ground
bounce and improve power supply bypassing. Connection of this
pin to ground is recommended. However, when using the
8XC251SB as a pin-for-pin replacement for the 8XC51FX, VSS2 can
be unconnected without loss of compatibility. (Not available on
DIP.)
—
WAIT#
WCLK
I
Real-time Wait State Input. The real-time WAIT# input is enabled P1.6/CEX3
by writing a logical ‘1’ to the WCON.0 (RTWE) bit at S:A7H. During
bus cycles, the external memory system can signal ‘system ready’
to the microcontroller in real time by controlling the WAIT# input
signal on the port 1.6 input.
O
Wait Clock Output. The real-time WCLK output is driven at port
1.7 (WCLK) by writing a logical ‘1’ to the WCON.1 (RTWCE) bit at
S:A7H. When enabled, the WCLK output produces a square wave
signal with a period of one-half the oscillator frequency.
P1.7/CEX4/A17
WR#
O
I
Write. Write signal output to external memory. Asserted for the
memory address range specified by configuration byte UCONFIG0,
bits RD1:0 (Table B-3). Also see RD#.
P3.6
—
XTAL1
Input to the On-chip, Inverting, Oscillator Amplifier. To use the
internal oscillator, a crystal/resonator circuit is connected to this pin.
If an external oscillator is used, its output is connected to this pin.
XTAL1 is the clock source for internal timing.
XTAL2
O
Output of the On-chip, Inverting, Oscillator Amplifier. To use
the internal oscillator, a crystal/resonator circuit is connected to this
pin. If an external oscillator is used, leave XTAL2 unconnected.
—
†
The descriptions of A15:8/P2.7:0 and AD7:0/P0.7:0 are for the nonpage mode chip configuration (com-
patible with 44-pin PLCC and 40-pin DIP MCS 51 microcontrollers). If the chip is configured for page
®
mode operation, port 0 carries the lower address bits (A7:0), and port 2 carries the upper address bits
(A15:8) and the data (D7:0).
B-6
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SIGNAL DESCRIPTIONS
Table B-3. Memory Signal Selections (RD1:0)
P1.7/CEX/
A17/WCLK
RD1:0
P3.7/RD#/A16/
PSEN#
WR#
Features
0
0
1
0
1
0
A17
A16
Asserted for
all addresses all memory locations
Asserted for writes to 256-Kbyte external
memory
P1.7/CEX4/
WCLK
A16
Asserted for Asserted for writes to 128-Kbyte external
all addresses all memory locations memory
P1.7/CEX4/
WCLK
P3.7 only
Asserted for Asserted for writes to 64-Kbyte external
all addresses all memory locations
memory. One
additional port pin.
1
1
P1.7/CEX4/
WCLK
RD# asserted
for addresses
≤ 7F:FFFFH
Asserted for
≥ 80:0000H
Asserted only for
writes to MCS 51
microcontroller data
memory locations.
64-Kbyte external
memory. Compatible
with MCS 51 micro-
controllers.
®
NOTE: RD1:0 are bits 3:2 of configuration byte UCONFIG0 (See Figure 4-3 on page 4-6).
B-7
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C
Registers
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APPENDIX C
REGISTERS
This appendix is a reference source of information for the 8XC251Sx special function registers
(SFRs) and the register file. The SFR map in Table C-1 provides the address and reset value for
each SFR. Tables C-2 through C-6 list the SFRs by functional category. Table C-7 lists the regis-
ters that make up the register file.
The remainder of the appendix contains descriptions of the SFRs arranged in alphabetical order.
For additional information see section 3.3, “8XC251SA, SB, SP, SQ Register File,” and section
3.4, “Special Function Registers (SFRs).”
NOTE
Use the prefix “S:” with SFR addresses to distinguish them from other
addresses.
C-1
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8XC251SA, SB, SP, SQ USER’S MANUAL
Table C-1. 8XC251SA, SB, SP, SQ SFR Map
0/8
1/9
CH
2/A
3/B
4/C
5/D
6/E
7/F
CCAP0H
CCAP1H
xxxxxxxx
CCAP2H
xxxxxxxx
CCAP3H
xxxxxxxx
CCAP4H
xxxxxxxx
F8
F0
E8
E0
D8
D0
C8
C0
B8
B0
A8
A0
98
90
88
80
FF
F7
EF
E7
DF
D7
CF
C7
BF
B7
AF
A7
9F
97
8F
87
00000000 xxxxxxxx
B
00000000
CL
CCAP0L
CCAP1L
xxxxxxxx
CCAP2L
xxxxxxxx
CCAP3L
xxxxxxxx
CCAP4L
xxxxxxxx
00000000 xxxxxxxx
ACC
00000000
CCON
CMOD
CCAPM0 CCAPM1 CCAPM2 CCAPM3 CCAPM4
00x00000 00xxx000 x0000000 x0000000 x0000000 x0000000 x0000000
PSW PSW1
00000000 00000000
T2CON T2MOD
00000000 xxxxxx00 00000000 00000000 00000000 00000000
RCAP2L
RCAP2H
TL2
TH2
IPL0
SADEN
SPH
x0000000 00000000
00000000
P3
IPH0
11111111
x0000000
IE0
SADDR
00000000 00000000
P2
WDTRST
xxxxxxxx
WCON
11111111
xxxxxx00
SCON
SBUF
00000000 xxxxxxxx
P1
11111111
TCON
TMOD
TL0
TL1
TH0
TH1
00000000 00000000 00000000 00000000 00000000 00000000
P0
SP
DPL
DPH
DPXL
PCON
11111111
00000111 00000000 00000000 00000001
00xx0000
0/8
1/9 2/A 3/B 4/C
5/D
6/E
7/F
NOTE: Shaded areas represent unimplemented SFR locations. Locations S:000H–S:07FH and
S:100H–S:1FFH are also unimplemented.
C-2
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REGISTERS
Table C-2. Core SFRs
Mnemonic
Name
Address
ACC†
B†
Accumulator
S:E0H
S:F0H
S:D0H
S:D1H
S:81H
S:BEH
—
B Register
PSW
PSW1
SP†
Program Status Word
Program Status Word 1
Stack Pointer – LSB of SPX
Stack Pointer High – MSB of SPX
Data Pointer (2 bytes)
Low Byte of DPTR
SPH†
DPTR†
DPL†
DPH†
DPXL†
PCON
IE0
S:82H
S:83H
S:84H
S:87H
S:A8H
S:B7H
S:B8H
S:A7H
High Byte of DPTR
Data Pointer, Extended Low
Power Control
Interrupt Enable Control 0
Interrupt Priority Control High 0
Interrupt Priority Control Low 0
Wait State Control Register
IPH0
IPL0
WCON
†
These SFRs can also be accessed by their corresponding registers in the
register file (see Table 3-4 on page 3-15 and Table C-7).
Table C-3. I/O Port SFRs
Mnemonic
Name
Address
P0
P1
P2
P3
Port 0
Port 1
Port 2
Port 3
S:80H
S:90H
S:A0H
S:B0H
C-3
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8XC251SA, SB, SP, SQ USER’S MANUAL
Table C-4. Serial I/O SFRs
Mnemonic
Name
Address
SCON
SBUF
Serial Control
S:98H
S:99H
S:B9H
S:A9H
Serial Data Buffer
Slave Address Mask
Slave Address
SADEN
SADDR
Table C-5. Timer/Counter and Watchdog Timer SFRs
Name
Mnemonic
Address
TL0
Timer/Counter 0 Low Byte
Timer/Counter 0 High Byte
Timer/Counter 1 Low Byte
Timer/Counter 1 High Byte
Timer/Counter 2 Low Byte
Timer/Counter 2 High Byte
Timer/Counter 0 and 1 Control
Timer/Counter 0 and 1 Mode Control
Timer/Counter 2 Control
S:8AH
S:8CH
S:8BH
S:8DH
S:CCH
S:CDH
S:88H
S:89H
S:C8H
S:C9H
S:CAH
S:CBH
S:A6H
TH0
TL1
TH1
TL2
TH2
TCON
TMOD
T2CON
T2MOD
RCAP2L
RCAP2H
WDTRST
Timer/Counter 2 Mode Control
Timer 2 Reload/Capture Low Byte
Timer 2 Reload/Capture High Byte
WatchDog Timer Reset
C-4
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REGISTERS
Table C-6. Programmable Counter Array (PCA) SFRs
Name
Mnemonic
Address
CCON
PCA Timer/Counter Control
S:D8H
S:D9H
S:DAH
S:DBH
S:DCH
S:DDH
S:DEH
S:E9H
S:F9H
S:EAH
S:EBH
S:ECH
S:EDH
S:EEH
S:FAH
S:FBH
S:FCH
S:FDH
S:FEH
CMOD
PCA Timer/Counter Mode
CCAPM0
CCAPM1
CCAPM2
CCAPM3
CCAPM4
CL
PCA Timer/Counter Mode 0
PCA Timer/Counter Mode 1
PCA Timer/Counter Mode 2
PCA Timer/Counter Mode 3
PCA Timer/Counter Mode 4
PCA Timer/Counter Low Byte
CH
PCA Timer/Counter High Byte
CCAP0L
CCAP1L
CCAP2L
CCAP3L
CCAP4L
CCAP0H
CCAP1H
CCAP2H
CCAP3H
CCAP4H
PCA Compare/Capture Module 0 Low Byte
PCA Compare/Capture Module 1 Low Byte
PCA Compare/Capture Module 2 Low Byte
PCA Compare/Capture Module 3 Low Byte
PCA Compare/Capture Module 4 Low Byte
PCA Compare/Capture Module 0 High Byte
PCA Compare/Capture Module 1 High Byte
PCA Compare/Capture Module 2 High Byte
PCA Compare/Capture Module 3 High Byte
PCA Compare/Capture Module 4 High Byte
C-5
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8XC251SA, SB, SP, SQ USER’S MANUAL
Table C-7. Register File
Mnemonic
Address
R0 – R7
Four banks of 8 registers. Select bank 0-3 with bits
RS1:0 of PSW.
1, 2
R8 – R31
R11 = Accumulator (ACC)
R10 = B Register.
1, 3
R32 – R55
R56 – R63
Reserved
3
DR56 = the extended data pointer (DPXL, DPH, DPL).
DR60 = the extended stack pointer (SPH, SPL).
1, 3
NOTE:
1. The registers in the register file are normally accessed by mnemonic. Depending on its loca-
tion, a register can be addressed as a byte, word, and/or dword. See Figure 3-7 on page
3-12.
2. The four banks of registers are implemented as the lowest bytes of on-chip RAM and are
always accessible via addresses 00:0000H–00:001FH.
3. Special function registers ACC, B, DPXL, DPH, DPL, SPH, and SPL are located in the regis-
ter file and can be accessed as R11, R10, DR56, and DR60).
C-6
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REGISTERS
Address:
Reset State:
E0H
0000 0000B
ACC
Accumulator. ACC provides SFR access to the accumulator, which resides in the register file as byte
®
register R11 (also named ACC). Instructions in the MCS 51 architecture use the accumulator as both
source and destination for calculations and moves. Instructions in the MCS 251 architecture assign no
special significance to R11. These instructions can use byte registers Rm (m = 0–15) interchangeably.
7
0
Accumulator Contents
Bit
Number
Bit
Mnemonic
Function
7:0
ACC.7:0
Accumulator.
Address:
Reset State:
F0H
0000 0000B
B
B Register. The B register provides SFR access to byte register R10 (also named B) in the register
file. The B register is used as both a source and destination in multiply and divide operations. For all
other operations, the B register is available for use as one of the byte registers Rm, m = 0–15.
7
0
B Register Contents
Bit
Number
Bit
Mnemonic
Function
7:0
B.7:0
B Register.
C-7
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8XC251SA, SB, SP, SQ USER’S MANUAL
CCAPxH, CCAPxL (x = 0–4)
Address: CCAP0H,L S:FAH, S:EAH
CCAP1H,L S:FBH, S:EBH
CCAP2H,L S:FCH, S:ECH
CCAP3H,L S:FDH, S:EDH
CCAP4H,L S:FEH, S:EEH
Reset State: XXXX XXXXB
PCA Module Compare/Capture Registers. These five register pairs store the 16-bit comparison value
or captured value for the corresponding compare/capture modules. In the PWM mode, the low-byte
register controls the duty cycle of the output waveform.
7
0
High/Low Byte of Compare/Capture Values
Bit
Number
Bit
Mnemonic
Function
7:0
CCAPxH.7:0
CCAPxL.7:0
High byte of PCA comparison or capture values.
Low byte of PCA comparison or capture values.
C-8
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REGISTERS
Address: CCAPM0 S:DAH
CCAPMx (x = 0–4)
CCAPM1 S:DBH
CCAPM2 S:DCH
CCAPM3 S:DDH
CCAPM4 S:DEH
Reset State: X000 0000B
PCA Compare/Capture Module Mode Registers. These five registers select the operating mode of the
corresponding compare/capture module. Each register also contains an enable interrupt bit (ECCFx)
for generating an interrupt request when the module’s compare/capture flag (CCFx in the CCON
register) is set. See Table 9-3 on page 9-14 for mode select bit combinations.
7
0
—
ECOMx
CAPPx
CAPNx
MATx
TOGx
PWMx
ECCFx
Bit
Number
Bit
Mnemonic
Function
7
—
Reserved:
The value read from this bit is indeterminate. Write a zero to this bit.
Compare Modes:
6
ECOMx
ECOMx = 1 enables the module comparator function. The comparator is
used to implement the software timer, high-speed output, pulse width
modulation, and watchdog timer modes.
5
4
3
CAPPx
CAPNx
MATx
Capture Mode (Positive):
CAPPx = 1 enables the capture function with capture triggered by a
positive edge on pin CEXx.
Capture Mode (Negative):
CAPNx = 1 enables the capture function with capture triggered by a
negative edge on pin CEXx.
Match:
Set ECOMx and MATx to implement the software timer mode. When
MATx = 1, a match of the PCA timer/counter with the compare/capture
register sets the CCFx bit in the CCON register, flagging an interrupt.
2
TOGx
Toggle:
Set ECOMx, MATx, and TOGx to implement the high-speed output
mode. When TOGx = 1, a match of the PCA timer/counter with the
compare/capture register toggles the CEXx pin.
1
0
PWMx
ECCFx
Pulse Width Modulation Mode:
PWMx = 1 configures the module for operation as an 8-bit pulse width
modulator with output waveform on the CEXx pin.
Enable CCFx Interrupt:
Enables compare/capture flag CCFx in the CCON register to generate
an interrupt request.
C-9
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8XC251SA, SB, SP, SQ USER’S MANUAL
Address:
Reset State:
S:D8H
00X0 0000B
CCON
PCA Timer/Counter Control Register. Contains the run control bit and overflow flag for the PCA
timer/counter, and the compare/capture flags for the five PCA compare/capture modules.
7
0
CF
CR
—
CCF4
CCF3
CCF2
CCF1
CCF0
Bit
Number
Bit
Mnemonic
Function
PCA Timer/Counter Overflow Flag:
7
CF
Set by hardware when the PCA timer/counter rolls over. This generates
an interrupt request if the ECF interrupt enable bit in CMOD is set. CF
can be set by hardware or software but can be cleared only by software.
6
CR
PCA Timer/Counter Run Control Bit:
Set and cleared by software to turn the PCA timer/counter on and off.
5
—
Reserved:
The value read from this bit is indeterminate. Write a zero to this bit.
4:0
CCF4:0
PCA Module Compare/Capture Flags:
Set by hardware when a match or capture occurs. This generates a PCA
interrupt request if the ECCFx interrupt enable bit in the corresponding
CCAPMx register is set. Must be cleared by software.
Address:
S:F9H
S:E9H
CH, CL
Reset State:
0000 0000B
CH, CL Registers. These registers operate in cascade to form the 16-bit PCA timer/counter.
7
0
High/Low Byte PCA Timer/Counter
Bit
Number
Bit
Mnemonic
Function
7:0
CH.7:0
CL.7:0
High byte of the PCA timer/counter
Low byte of the PCA timer/counter
C-10
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REGISTERS
Address:
Reset State: 00XX X000B
S:D9H
CMOD
PCA Timer/Counter Mode Register. Contains bits for selecting the PCA timer/counter input, disabling
the PCA timer/counter during idle mode, enabling the PCA WDT reset output (module 4 only), and
enabling the PCA timer/counter overflow interrupt.
7
0
CIDL
WDTE
—
—
—
CPS1
CPS0
ECF
Bit
Number
Bit
Mnemonic
Function
PCA Timer/Counter Idle Control:
7
CIDL
CIDL = 1 disables the PCA timer/counter during idle mode. CIDL = 0
allows the PCA timer/counter to run during idle mode.
6
WDTE
—
Watchdog Timer Enable:
WDTE = 1 enables the watchdog timer output on PCA module 4.
WDTE = 0 disables the PCA watchdog timer output.
5:3
2:1
Reserved:
The values read from these bits are indeterminate. Write zeros to these
bits.
CPS1:0
PCA Timer/Counter Input Select:
CPS1 CPS0
0
0
1
1
0
1
0
1
F
F
OSC /12
OSC /4
Timer 0 overflow
External clock at ECI pin (maximum rate = FOSC /8 )
0
ECF
PCA Timer/Counter Interrupt Enable:
ECF = 1 enables the CF bit in the CCON register to generate an interrupt
request.
C-11
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Address:
Reset State:
S:83H
0000 0000B
DPH
Data Pointer High. DPH provides SFR access to register file location 58 (also named DPH). DPH is
®
the upper byte of the 16-bit data pointer, DPTR. Instructions in the MCS 51 architecture use DPTR
for data moves, code moves, and for a jump instruction (JMP @A+DPTR). See also DPL and DPXL.
7
0
DPH Contents
Bit
Number
Bit
Mnemonic
Function
7:0
DPH.7:0
Data Pointer High:
Bits 8–15 of the extended data pointer, DPX (DR56).
Address:
Reset State:
S:82H
0000 0000B
DPL
Data Pointer Low. DPL provides SFR access to register file location 59 (also named DPL). DPL is the
®
low byte of the 16-bit data pointer, DPTR. Instructions in the MCS 51 architecture use the 16-bit data
pointer for data moves, code moves, and for a jump instruction (JMP @A+DPTR). See also DPH and
DPXL.
7
0
DPL Contents
Bit
Number
Bit
Mnemonic
Function
7:0
DPL.7:0
Data Pointer Low:
Bits 0–7 of the extended data pointer, DPX (DR56).
C-12
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REGISTERS
Address:
Reset State:
S:84H
0000 0001B
DPXL
Data Pointer Extended Low. DPXL provides SFR access to register file location 57 (also named
DPXL). Location 57 is the lower byte of the upper word of the extended data pointer, DPX = DR56,
whose lower word is the 16-bit data pointer, DPTR. See also DPH and DPL.
7
0
DPXL Contents
Bit
Number
Bit
Mnemonic
Function
7:0
DPXL.7:0
Data Pointer Extended Low:
Bits 16–23 of the extended data pointer, DPX (DR56).
C-13
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8XC251SA, SB, SP, SQ USER’S MANUAL
Address:
Reset State:
S:A8H
0000 0000B
IE0
Interrupt Enable Register 0. IE0 contains two types of interrupt enable bits. The global enable bit (EA)
enables/disables all of the interrupts, except the TRAP interrupt, which is always enabled. The
remaining bits enable/disable the other individual interrupts.
7
0
EA
EC
ET2
ES
ET1
EX1
ET0
EX0
Bit
Number
Bit
Mnemonic
Function
7
EA
Global Interrupt Enable:
Setting this bit enables all interrupts that are individually enabled by bits
0–6. Clearing this bit disables all interrupts, except the TRAP interrupt,
which is always enabled.
6
5
4
3
2
1
0
EC
PCA Interrupt Enable:
Setting this bit enables the PCA interrupt.
ET2
ES
Timer 2 Overflow Interrupt Enable:
Setting this bit enables the timer 2 overflow interrupt.
Serial I/O Port Interrupt Enable:
Setting this bit enables the serial I/O port interrupt.
ET1
EX1
ET0
EX0
Timer 1 Overflow Interrupt Enable:
Setting this bit enables the timer 1 overflow interrupt.
External Interrupt 1 Enable:
Setting this bit enables external interrupt 1.
Timer 0 Overflow Interrupt Enable:
Setting this bit enables the timer 0 overflow interrupt.
External Interrupt 0 Enable:
Setting this bit enables external interrupt 0.
C-14
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REGISTERS
Address:
Reset State:
S:B7H
X000 0000B
IPH0
Interrupt Priority High Control Register 0. IPH0, together with IPL0, assigns each interrupt a priority
level from 0 (lowest) to 3 (highest):
IPH0.x IPL0.x
Priority Level
0
0
1
1
0
1
0
1
0 (lowest priority)
1
2
3 (highest priority)
7
0
—
IPH0.6
IPH0.5
IPH0.4
IPH0.3
IPH0.2
IPH0.1
IPH0.0
Bit
Number
Bit
Mnemonic
Function
7
—
Reserved. The value read from this bit is indeterminate. Write a zero to
this bit.
6
5
4
3
2
1
0
IPH0.6
IPH0.5
IPH0.4
IPH0.3
IPH0.2
IPH0.1
IPH0.0
PCA Interrupt Priority Bit High
Timer 2 Overflow Interrupt Priority Bit High
Serial I/O Port Interrupt Priority Bit High
Timer 1 Overflow Interrupt Priority Bit High
External Interrupt 1 Priority Bit High
Timer 0 Overflow Interrupt Priority Bit High
External Interrupt 0 Priority Bit High
C-15
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8XC251SA, SB, SP, SQ USER’S MANUAL
Address:
Reset State:
S:B8H
X000 0000B
IPL0
Interrupt Priority Low Control Register 0. IPL0, together with IPH0, assigns each interrupt a priority
level from 0 (lowest) to 3 (highest):
IPH0.x IPL0.x
Priority Level
0
0
1
1
0
1
0
1
0 (lowest priority)
1
2
3 (highest priority)
7
0
—
IPL0.6
IPL0.5
IPL0.4
IPL0.3
IPL0.2
IPL0.1
IPL0.0
Bit
Number
Bit
Mnemonic
Function
7
—
Reserved. The value read from this bit is indeterminate. Write a zero to
this bit.
6
5
4
3
2
1
0
IPL0.6
IPL0.5
IPL0.4
IPL0.3
IPL0.2
IPL0.1
IPL0.0
PCA Interrupt Priority Bit Low
Timer 2 Overflow Interrupt Priority Bit Low
Serial I/O Port Interrupt Priority Bit Low
Timer 1 Overflow Interrupt Priority Bit Low
External Interrupt 1 Priority Bit Low
Timer 0 Overflow Interrupt Priority Bit Low
External Interrupt 0 Priority Bit Low
C-16
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REGISTERS
Address:
Reset State:
S:80H
1111 1111B
P0
Port 0. P0 is the SFR that contains data to be driven out from the port 0 pins. Read-modify-write
instructions that read port 0 read this register. The other instructions that read port 0 read the port 0
pins. When port 0 is used for an external bus cycle, the CPU always writes FFH to P0, and the former
contents of P0 are lost.
7
0
P0 Contents
Bit
Number
Bit
Mnemonic
Function
7:0
P0.7:0
Port 0 Register:
Write data to be driven onto the port 0 pins to these bits.
Address:
Reset State:
S:90H
1111 1111B
P1
Port 1. P1 is the SFR that contains data to be driven out from the port 1 pins. Read-write-modify
instructions that read port 1 read this register. Other instructions that read port 1 read the port 1 pins.
7
0
P1 Contents
Bit
Number
Bit
Mnemonic
Function
7:0
P1.7:0
Port 1 Register:
Write data to be driven onto the port 1 pins to these bits.
C-17
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Address:
Reset State:
S:A0H
1111 1111B
P2
Port 2. P2 is the SFR that contains data to be driven out from the port 2 pins. Read-modify-write
instructions that read port 2 read this register. Other instructions that read port 2 read the port 2 pins.
7
0
P2 Contents
Bit
Number
Bit
Mnemonic
Function
7:0
P2.7:0
Port 2 Register:
Write data to be driven onto the port 2 pins to these bits.
Address:
Reset State:
S:B0H
1111 1111B
P3
Port 3. P3 is the SFR that contains data to be driven out from the port 3 pins. Read-modify-write
instructions that read port 3 read this register. Other instructions that read port 3 read the port 3 pins.
7
0
P3 Contents
Bit
Number
Bit
Mnemonic
Function
7:0
P3.7:0
Port 3 Register:
Write data to be driven onto the port 3 pins to these bits.
C-18
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REGISTERS
Address:
Reset State:
S:87H
00XX 0000B
PCON
Power Control Register. Contains the power off flag (POF) and bits for enabling the idle and
powerdown modes. Also contains two general-purpose flags and two bits that control serial I/O
functions—the double baud rate bit and a bit that selects whether accesses to SCON.7 are to the FE
bit or the SM0 bit.
7
0
SMOD1
SMOD0
—
POF
GF1
GF0
PD
IDL
Bit
Number
Bit
Mnemonic
Function
7
SMOD1
Double Baud Rate Bit:
When set, doubles the baud rate when timer 1 is used and mode 1, 2, or
3 is selected in the SCON register. See section 10.6, “Baud Rates.”
6
SMOD0
SCON.7 Select:
When set, read/write accesses to SCON.7 are to the FE bit.
When clear, read/write accesses to SCON.7 are to the SM0 bit.
See Figure 10-2 on page 10-3.
5
4
—
Reserved:
The value read from this bit is indeterminate. Write a zero to this bit.
POF
Power Off Flag:
Set by hardware as V rises above 3 V to indicate that power has been
CC
off or V had fallen below 3 V and that on-chip volatile memory is
CC
indeterminate. Set or cleared by software.
3
2
1
0
GF1
GF0
PD
General Purpose Flag:
Set or cleared by software. One use is to indicate whether an interrupt
occurred during normal operation or during idle mode.
General Purpose Flag:
Set or cleared by software. One use is to indicate whether an interrupt
occurred during normal operation or during idle mode.
Powerdown Mode Bit:
When set, activates powerdown mode.
Cleared by hardware when an interrupt or reset occurs.
IDL
Idle Mode Bit:
When set, activates idle mode.
Cleared by hardware when an interrupt or reset occurs.
If IDL and PD are both set, PD takes precedence.
C-19
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.
Address:
Reset State:
S:D0H
0000 0000B
PSW
Program Status Word. PSW contains bits that reflect the results of operations, bits that select the
register bank for registers R0–R7, and two general-purpose flags that are available to the user.
7
0
CY
AC
F0
RS1
RS0
OV
UD
P
Bit
Number
Bit
Mnemonic
Function
7
CY
Carry Flag:
The carry flag is set by an addition instruction (ADD, ADDC) if there is a
carry out of the MSB. It is set by a subtraction (SUB, SUBB) or compare
(CMP) if a borrow is needed for the MSB. The carry flag is also affected
by some rotate and shift instructions, logical bit instructions and bit move
instructions, and the multiply (MUL) and decimal adjust (DA) instructions
(see Table 5-10 on page 5-17).
6
AC
Auxiliary Carry Flag:
The auxiliary carry flag is affected only by instructions that address 8-bit
operands. The AC flag is set if an arithmetic instruction with an 8-bit
operand produces a carry out of bit 3 (from addition) or a borrow into bit
3 (from subtraction). Otherwise it is cleared. This flag is useful for BCD
arithmetic (see Table 5-10 on page 5-17).
5
F0
Flag 0:
This general-purpose flag is available to the user.
4:3
RS1:0
Register Bank Select Bits 1 and 0:
These bits select the memory locations that comprise the active bank of
the register file (registers R0–R7).
RS1 RS0
Bank Address
0
0
1
1
0
1
0
1
0
1
2
3
00H–07H
08H–0FH
10H–17H
18H–1FH
2
OV
Overflow Flag:
This bit is set if an addition or subtraction of signed variables results in
an overflow error (i.e., if the magnitude of the sum or difference is too
great for the seven LSBs in 2’s-complement representation). The
overflow flag is also set if a multiplication product overflows one byte or if
a division by zero is attempted.
1
0
UD
P
User-definable Flag:
This general-purpose flag is available to the user.
Parity Bit:
This bit indicates the parity of the accumulator. It is set if an odd number
of bits in the accumulator are set. Otherwise, it is cleared. Not all instruc-
tions update the parity bit. The parity bit is set or cleared by instructions
that change the contents of the accumulator (ACC, Register R11).
C-20
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REGISTERS
Address:
Reset State:
S:D1H
0000 0000B
PSW1
Program Status Word 1. PSW1 contains bits that reflect the results of operations and bits that select
the register bank for registers R0–R7.
7
0
CY
AC
N
RS1
RS0
OV
Z
—
Bit
Number
Bit
Mnemonic
Function
7
CY
Carry Flag:
Identical to the CY bit in the PSW register.
6
5
AC
N
Auxiliary Carry Flag:
Identical to the AC bit in the PSW register.
Negative Flag:
This bit is set if the result of the last logical or arithmetic operation was
negative. Otherwise it is cleared.
4:3
2
RS1:0
OV
Register Bank Select Bits 0 and 1:
Identical to the RS1:0 bits in the PSW register.
Overflow Flag:
Identical to the OV bit in the PSW register.
1
Z
Zero Flag:
This flag is set if the result of the last logical or arithmetic operation is
zero. Otherwise it is cleared.
0
—
Reserved:
The value read from this bit is indeterminate. Write a zero to this bit.
Address: RCAP2H S:CBH
RCAP2L S:CAH
RCAP2H, RCAP2L
Reset State: 0000 0000B
Timer 2 Reload/Capture Registers. This register pair stores 16-bit values to be loaded into or captured
from the timer register (TH2/TL2) in timer 2.
7
0
High/Low Byte of Timer 2 Reload/Capture Value
Bit
Number
Bit
Mnemonic
Function
7:0
RCAP2H.7:0
RCAP2L.7:0
High byte of the timer 2 reload/recapture register
Low byte of the timer 2 reload/recapture register
C-21
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Address:
Reset State:
S:A9H
0000 0000B
SADDR
Slave Individual Address Register. SADDR contains the device’s individual address for multiprocessor
communication.
7
0
Slave Individual Address
Bit
Number
Bit
Mnemonic
Function
7:0
SADDR.7:0
C-22
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REGISTERS
Address:
Reset State:
S:B9H
0000 0000B
SADEN
Mask Byte Register. This register masks bits in the SADDR register to form the device’s given address
for multiprocessor communication.
7
0
Mask for SADDR
Bit
Number
Bit
Mnemonic
Function
7:0
SADEN.7:0
Address:
Reset State: XXXX XXXXB
S:99H
SBUF
Serial Data Buffer. Writing to SBUF loads the transmit buffer of the serial I/O port. Reading SBUF
reads the receive buffer of the serial I/O port.
7
0
Data Sent/Received by Serial I/O Port
Bit
Number
Bit
Mnemonic
Function
7:0
SBUF.7:0
C-23
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Address:
Reset State:
98H
0000 0000B
SCON
Serial Port Control Register. SCON contains serial I/O control and status bits, including the mode
select bits and the interrupt flag bits.
7
0
FE/SM0
SM1
SM2
REN
TB8
RB8
TI
RI
Bit
Number
Bit
Mnemonic
Function
7
FE
Framing Error Bit:
To select this function, set the SMOD0 bit in the PCON register. Set by
hardware to indicate an invalid stop bit. Cleared by software, not by valid
frames.
SM0
SM1
Serial Port Mode Bit 0:
To select this function, clear the SMOD0 bit in the PCON register.
Software writes to bits SM0 and SM1 to select the serial port operating
mode. Refer to the SM1 bit for the mode selections.
6
Serial Port Mode Bit 1:
Software writes to bits SM1 and SM0 (above) to select the serial port
operating mode.
SM0 SM1 Mode
Description
Shift register
8-bit UART
9-bit UART
9-bit UART
Baud Rate
OSC/12
Variable
0
0
1
1
†
0
1
0
1
0
1
2
3
F
†
†
F
OSC/32 or FOSC/64
Variable
Select by programming the SMOD bit in the PCON register (see section
10.6, “Baud Rates).”
5
SM2
Serial Port Mode Bit 2:
Software writes to bit SM2 to enable and disable the multiprocessor
communication and automatic address recognition features. This allows
the serial port to differentiate between data and command frames and to
recognize slave and broadcast addresses.
4
3
REN
TB8
Receiver Enable Bit:
To enable reception, set this bit. To enable transmission, clear this bit.
Transmit Bit 8:
In modes 2 and 3, software writes the ninth data bit to be transmitted to
TB8. Not used in modes 0 and 1.
2
RB8
Receiver Bit 8:
Mode 0: Not used.
Mode 1 (SM2 clear): Set or cleared by hardware to reflect the stop bit
received.
Modes 2 and 3 (SM2 set): Set or cleared by hardware to reflect the ninth
data bit received.
C-24
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REGISTERS
Address:
Reset State:
98H
0000 0000B
SCON
Serial Port Control Register. SCON contains serial I/O control and status bits, including the mode
select bits and the interrupt flag bits.
7
0
FE/SM0
SM1
SM2
REN
TB8
RB8
TI
RI
Bit
Number
Bit
Mnemonic
Function
1
TI
Transmit Interrupt Flag Bit:
Set by the transmitter after the last data bit is transmitted. Cleared by
software.
0
RI
Receive Interrupt Flag Bit:
Set by the receiver after the last data bit of a frame has been received.
Cleared by software.
Address:
Reset State:
S:81H
0000 0111B
SP
Stack Pointer. SP provides SFR access to location 63 in the register file (also named SP). SP is the
lowest byte of the extended stack pointer (SPX = DR60). The extended stack pointer points to the
current top of stack. When a byte is saved (PUSHed) on the stack, SPX is incremented, and then the
byte is written to the top of stack. When a byte is retrieved (POPped) from the stack, it is copied from
the top of stack, and then SPX is decremented.
7
0
SP Contents
Bit
Number
Bit
Mnemonic
Function
7:0
SP.7:0
Stack Pointer:
Bits 0–7 of the extended stack pointer, SPX (DR60).
C-25
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8XC251SA, SB, SP, SQ USER’S MANUAL
Address:
Reset State:
S:BEH
0000 0000B
SPH
Stack Pointer High. SPH provides SFR access to location 62 in the register file (also named SPH).
SPH is the upper byte of the lower word of DR60, the extended stack pointer (SPX). The extended
stack pointer points to the current top of stack. When a byte is saved (PUSHed) on the stack, SPX is
incremented, and then the byte is written to the top of stack. When a byte is retrieved (POPped) from
the stack, it is copied from the top of stack, and then SPX is decremented.
7
0
SPH Contents
Bit
Number
Bit
Mnemonic
Function
7:0
SPH.7:0
Stack Pointer High:
Bits 8–15 of the extended stack pointer, SPX (DR60).
C-26
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REGISTERS
Address:
Reset State:
S:C8H
0000 0000B
T2CON
Timer 2 Control Register. Contains the receive clock, transmit clock, and capture/reload bits used to
configure timer 2. Also contains the run control bit, counter/timer select bit, overflow flag, external flag,
and external enable for timer 2.
7
0
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
C/T2#
CP/RL2#
Bit
Number
Bit
Mnemonic
Function
7
TF2
Timer 2 Overflow Flag:
Set by timer 2 overflow. Must be cleared by software. TF2 is not set if
RCLK = 1 or TCLK = 1.
6
EXF2
Timer 2 External Flag:
If EXEN2 = 1, capture or reload caused by a negative transition on T2EX
sets EFX2. EXF2 does not cause an interrupt in up/down counter mode
(DCEN = 1).
5
4
3
RCLK
TCLK
Receive Clock Bit:
Selects timer 2 overflow pulses (RCLK = 1) or timer 1 overflow pulses
(RCLK = 0) as the baud rate generator for serial port modes 1 and 3.
Transmit Clock Bit:
Selects timer 2 overflow pulses (TCLK = 1) or timer 1 overflow pulses
(TCLK = 0) as the baud rate generator for serial port modes 1 and 3.
EXEN2
Timer 2 External Enable Bit:
Setting EXEN2 causes a capture or reload to occur as a result of a
negative transition on T2EX unless timer 2 is being used as the baud
rate generator for the serial port. Clearing EXEN2 causes timer 2 to
ignore events at T2EX.
2
1
TR2
Timer 2 Run Control Bit:
Setting this bit starts the timer.
C/T2#
Timer 2 Counter/Timer Select:
C/T2# = 0 selects timer operation: timer 2 counts the divided-down
system clock. C/T2# = 1 selects counter operation: timer 2 counts
negative transitions on external pin T2.
0
CP/RL2#
Capture/Reload Bit:
When set, captures occur on negative transitions at T2EX if EXEN2 = 1.
When cleared, auto-reloads occur on timer 2 overflows or negative
transitions at T2EX if EXEN2 = 1. The CP/RL2# bit is ignored and timer 2
forced to auto-reload on timer 2 overflow, if RCLK = 1 or TCLK = 1.
C-27
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Address:
Reset State: XXXX XX00B
S:C9H
T2MOD
Timer 2 Mode Control Register. Contains the timer 2 down count enable and clock-out enable bits for
timer 2 .
7
0
—
—
—
—
—
—
T2OE
DCEN
Bit
Number
Bit
Mnemonic
Function
7:2
—
Reserved:
The values read from these bits are indeterminate. Write zeros to these
bits.
1
0
T2OE
DCEN
Timer 2 Output Enable Bit:
In the timer 2 clock-out mode, connects the programmable clock output
to external pin T2.
Down Count Enable Bit:
Configures timer 2 as an up/down counter.
C-28
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REGISTERS
Address:
Reset State:
S:88H
0000 0000B
TCON
Timer/Counter Control Register. Contains the overflow and external interrupt flags and the run control
and interrupt transition select bits for timer 0 and timer 1.
7
0
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
Bit
Number
Bit
Mnemonic
Function
7
TF1
Timer 1 Overflow Flag:
Set by hardware when the timer 1 register overflows. Cleared by
hardware when the processor vectors to the interrupt routine.
6
5
TR1
TF0
Timer 1 Run Control Bit:
Set/cleared by software to turn timer 1 on/off.
Timer 0 Overflow Flag:
Set by hardware when the timer 0 register overflows. Cleared by
hardware when the processor vectors to the interrupt routine.
4
3
TR0
IE1
Timer 0 Run Control Bit:
Set/cleared by software to turn timer 1 on/off.
Interrupt 1 Flag:
Set by hardware when an external interrupt is detected on the INT1# pin.
Edge- or level- triggered (see IT1). Cleared when interrupt is processed
if edge-triggered.
2
1
IT1
IE0
Interrupt 1 Type Control Bit:
Set this bit to select edge-triggered (high-to-low) for external interrupt 1.
Clear this bit to select level-triggered (active low).
Interrupt 1 Flag:
Set by hardware when an external interrupt is detected on the INT0# pin.
Edge- or level- triggered (see IT0). Cleared when interrupt is processed
if edge-triggered.
0
IT0
Interrupt 0 Type Control Bit:
Set this bit to select edge-triggered (high-to-low) for external interrupt 0.
Clear this bit to select level-triggered (active low).
C-29
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8XC251SA, SB, SP, SQ USER’S MANUAL
Address:
Reset State:
S:89H
0000 0000B
TMOD
Timer/Counter Mode Control Register. Contains mode select, run control select, and counter/timer
select bits for controlling timer 0 and timer 1.
7
0
GATE1
C/T1#
M11
M01
GATE0
C/T0#
M10
M00
Bit
Number
Bit
Mnemonic
Function
7
GATE1
Timer 1 Gate:
When GATE1 = 0, run control bit TR1 gates the input signal to the timer
register. When GATE1 = 1 and TR1 = 1, external signal INT1 gates the
timer input.
6
C/T1#
Timer 1 Counter/Timer Select:
C/T1# = 0 selects timer operation: timer 1 counts the divided-down
system clock. C/T1# = 1 selects counter operation: timer 1 counts
negative transitions on external pin T1.
5, 4
M11, M01
Timer 1 Mode Select:
M11 M01
0
0
1
0
1
0
Mode 0: 8-bit timer/counter (TH1) with 5-bit prescalar (TL1)
Mode 1: 16-bit timer/counter
Mode 2: 8-bit auto-reload timer/counter (TL1). Reloaded
from TH1 at overflow.
1
1
Mode 3: Timer 1 halted. Retains count.
3
GATE0
C/T0#
Timer 0 Gate:
When GATE0 = 0, run control bit TR0 gates the input signal to the timer
register. When GATE0 = 1 and TR0 = 1, external signal INT0 gates the
timer input.
2
Timer 0 Counter/Timer Select:
C/T0# = 0 selects timer operation: timer 0 counts the divided-down
system clock. C/T0# = 1 selects counter operation: timer 0 counts
negative transitions on external pin T0.
1, 0
M10, M00
Timer 0 Mode Select:
M10 M00
0
0
1
0
1
0
Mode 0: 8-bit timer/counter (T0) with 5-bit prescaler (TL0)
Mode 1: 16-bit timer/counter
Mode 2: 8-bit auto-reload timer/counter (TL0). Reloaded
from TH0 at overflow.
1
1
Mode 3: TL0 is an 8-bit timer/counter. TH0 is an 8-bit timer
using timer 1’s TR1 and TF1 bits.
C-30
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REGISTERS
Address:
TH0 S:8CH
TL0 S:8AH
TH0, TL0
Reset State:
0000 0000B
TH0, TL0 Timer Registers. These registers operate in cascade to form the 16-bit timer register in timer
0 or separately as 8-bit timer/counters.
7
0
High/Low Byte of Timer 0 Register
Bit
Number
Bit
Mnemonic
Function
7:0
TH0.7:0
TL0.7:0
High byte of the timer 0 timer register.
Low byte of the timer 0 timer register.
Address:
TH1 S:8DH
TL1 S:8BH
TH1, TL1
Reset State:
0000 0000B
TH1, TL1 Timer Registers. These registers operate in cascade to form the 16-bit timer register in timer
1 or separately as 8-bit timer/counters.
7
0
High/Low Byte of Timer 1 Register
Bit
Number
Bit
Mnemonic
Function
7:0
TH1.7:0
TL1.7:0
High byte of the timer 1 timer register.
Low byte of the timer 1 timer register.
C-31
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Address:
TH2 S:CDH
TL2 S:CCH
TH2, TL2
Reset State:
0000 0000B
TH2, TL2 Timer Registers. These registers operate in cascade to form the 16-bit timer register in timer
2.
7
0
High/Low Byte of Timer 2 Register
Bit
Number
Bit
Mnemonic
Function
7:0
TH2.7:0
TL2.7:0
High byte of the timer 2 timer register.
Low byte of the timer 2 timer register.
Address:
Reset State: XXXX XX00B
S:A7H
WCON
Wait State Control Register. Use this register to enable the real time wait state input signal and/or the
wait state output clock.
7
0
—
—
—
—
—
—
RTWCE
RTWE
Bit
Number
Bit
Mnemonic
Function
7:2
—
Reserved:
The values read from these bits are indeterminate. Write “0” to these
bits.
1
0
RTWCE
RTWE
Real time WAIT CLOCK enable. Write a ‘1’ to this bit to enable the WAIT
CLOCK on port 1.7 (WCLK). The square wave output signal is one-half
the oscillator frequency.
Real time WAIT# enable. Write a ‘1’ to this bit to enable real-time wait-
state input on port 1.6 (WAIT#).
C-32
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REGISTERS
Address:
Reset State: XXXX XXXXB
S:A6H
WDTRST
Watchdog Timer Reset Register. Writing the two-byte sequence 1EH-E1H to the WDTRST register
clears and enables the hardware WDT. The WDTRST register is a write-only register. Attempts to
read it return FFH. The WDT itself is not read or write accessible. See section 8.7, “Watchdog Timer.”
7
0
WDTRST Contents (Write-only)
Bit
Number
Bit
Mnemonic
Function
7:0
WDTRST.7:0 Provides user control of the hardware WDT.
C-33
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Glossary
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GLOSSARY
This glossary defines acronyms, abbreviations, and terms that have special meaning in this man-
ual. (Chapter 1, “Guide to this Manual,” discusses notational conventions and general terminol-
ogy.)
#0data16
#1data16
#data
A 32-bit constant that is immediately addressed in an
instruction. The upper word is filled with zeros.
A 32-bit constant that is immediately addressed in an
instruction. The upper word is filled with ones.
An 8-bit constant that is immediately addressed in an
instruction.
#data16
#short
A 16-bit constant that is immediately addressed in an
instruction.
A constant, equal to 1, 2, or 4, that is immediately
addressed in an instruction.
accumulator
addr11
A register or storage location that forms the result of
an arithmetic or logical operation.
An 11-bit destination address. The destination can be
anywhere in the same 2-Kbyte block of memory as
the first byte of the next instruction.
addr16
A 16-bit destination address. The destination can be
anywhere within the same 64-Kbyte region as the first
byte of the next instruction.
addr24
ALU
A 24-bit destination address. The destination can be
anywhere within the 16-Mbyte address space.
Arithmetic-logic unit. The part of the CPU that
processes arithmetic and logical operations.
assert
The term assert refers to the act of making a signal
active (enabled). The polarity (high/low) is defined by
the signal name. Active-low signals are designated by
a pound symbol (#) suffix; active-high signals have no
suffix. To assert RD# is to drive it low; to assert ALE
is to drive it high.
Glossary-1
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8XC251SA, SB, SP, SQ USER’S MANUAL
big endien form
Memory storage format in which the most significant
byte (MSB) of the word or double word is stored in
the memory byte specified in the instruction. The
remaining bytes are stored at higher addresses, with
the least significant byte (LSB) at the highest address.
binary-code compatibility
binary mode
The ability of an MCS® 251 microcontroller to
execute, without modification, binary code written for
an MCS 51 microcontroller.
An operating mode, selected by a configuration bit,
that enables an MCS 251 microcontroller to execute,
without modification, binary code written for an MCS
51 microcontroller.
bit
A binary digit.
bit (operand)
bit51
An addressable bit in the MCS 251 architecture.
An addressable bit in the MCS 51 architecture.
Any 8-bit unit of data.
byte
clear
The term clear refers to the value of a bit or the act of
giving it a value. If a bit is clear, its value is “0”;
clearing a bit gives it a “0” value.
code memory
See program memory.
configuration bytes
Bytes, residing in on-chip OTPROM/ROM, that
determine a set of operating parameters for the
8XC251SB.
dir8
An 8-bit direct address. This can be a memory address
or an SFR address.
dir16
DPTR
A 16-bit memory address (00:0000H–00:FFFFH)
used in direct addressing.
The 16-bit data pointer. In MCS 251 microcontrollers,
DPTR is the lower 16 bits of the 24-bit extended data
pointer, DPX.
DPX
The 24-bit extended data pointer in MCS 251 micro-
controllers. See also DPTR.
Glossary-2
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GLOSSARY
deassert
The term deassert refers to the act of making a signal
inactive (disabled). The polarity (high/low) is defined
by the signal name. Active-low signals are designated
by a pound symbol (#) suffix; active-high signals have
no suffix. To deassert RD# is to drive it high; to
deassert ALE is to drive it low.
doping
The process of introducing a periodic table Group III
or Group V element into a Group IV element (e.g.,
silicon). A Group III impurity (e.g., indium or
gallium) results in a p-type material. A Group V
impurity (e.g., arsenic or antimony) results in an n-
type material.
double word
A 32-bit unit of data. In memory, a double word
comprises four contiguous bytes.
dword
See double word.
edge-triggered
The mode in which a device or component recognizes
a falling edge (high-to-low transition), a rising edge
(low-to-high transition), or a rising or falling edge of
an input signal as the assertion of that signal. See also
level-triggered.
encryption array
An array of key bytes used to encrypt user code in the
on-chip code memory as that code is read; protects
against unauthorized access to user’s code.
EPROM
Erasable, programmable read-only memory
external address
A 16-bit or 17-bit address presented on the device
pins. The address decoded by an external device
depends on how many of these address bits the
external system uses. See also internal address.
FET
Field-effect transistor.
idle mode
The power conservation mode that freezes the core
clocks but leaves the peripheral clocks running.
input leakage
integer
Current leakage from an input pin to power or ground.
Any member of the set consisting of the positive and
negative whole numbers and zero.
internal address
The 24-bit address that the device generates. See also
external address.
Glossary-3
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8XC251SA, SB, SP, SQ USER’S MANUAL
interrupt handler
The module responsible for handling interrupts that
are to be serviced by user-written interrupt service
routines.
interrupt latency
The delay between an interrupt request and the time
when the first instruction in the interrupt service
routine begins execution.
interrupt response time
The time delay between an interrupt request and the
resulting break in the current instruction stream.
interrupt service routine (ISR)
latency
The software routine that services an interrupt.
The amount of time between the interrupt request and
the execution of the first instruction in the interrupt
service routine.
level-triggered
The mode in which a device or component recognizes
a high level (logic one) or a low level (logic zero) of
an input signal as the assertion of that signal. See also
edge-triggered.
LSB
Least-significant bit of a byte or least-significant byte
of a word.
maskable interrupt
An interrupt that can be disabled (masked) by its
individual mask bit in an interrupt enable register. All
8XC251SB interrupts, except the software trap
(TRAP), are maskable.
MSB
Most-significant bit of a byte or most-significant byte
of a word.
multiplexed bus
n-channel FET
n-type material
A bus on which the data is time-multiplexed with
(some of) the address bits.
A field-effect transistor with an n-type conducting
path (channel).
Semiconductor material with introduced impurities
(doping) causing it to have an excess of negatively
charged carriers.
nibble
A half-byte or four bits.
nonmaskable interrupt
An interrupt that cannot be disabled (masked). The
software trap (TRAP) is the 8XC251SB’s only
nonmaskable interrupt.
Glossary-4
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GLOSSARY
nonpage mode
Conventional method for accessing external memory
where code fetches require a two-state bus cycle. See
also page mode.
npn transistor
OTPROM
A transistor consisting of one part p-type material and
two parts n-type material.
One-time-programmable read-only memory, a version
of EPROM.
p-channel FET
p-type material
A field-effect transistor with a p-type conducting
path.
Semiconductor material with introduced impurities
(doping) causing it to have an excess of positively
charged carriers.
page mode
Method for reducing the time for external code
fetches where subsequent code fetches to the same
256-byte “page” of memory require only a one-state
bus cycle.
PC
Program counter.
peripheral cycle
The cycle at which the 8XC251SA, SB, SP, SQ
peripherals operate. This is equal to six state times.
program memory
powerdown mode
A part of memory where instructions can be stored for
fetching and execution.
The power conservation mode that freezes both the
core clocks and the peripheral clocks.
PWM
Pulse-width modulated (outputs).
real-time wait state
A wait state whose delay time can be adjusted
dynamically by the programmer by means of
registers.
rel
A
signed (two's complement) 8-bit, relative
destination address. The destination is -128 to +127
bytes relative to the first byte of the next instruction.
reserved bits
Register bits that are not used in this device but may
be used in future implementations. Avoid any
software dependence on these bits. In the 8XC251SB,
the value read from a reserved bit is indeterminate; do
not write a “1” to a reserved bit.
response time
The amount of time between the interrupt request and
the resulting break in the current instruction stream.
Glossary-5
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8XC251SA, SB, SP, SQ USER’S MANUAL
set
The term set refers to the value of a bit or the act of
giving it a value. If a bit is set, its value is “1”; setting
a bit gives it a “1” value.
SFR
Special-function register.
sign extension
A method for converting data to a larger format by
filling the extra bit positions with the value of the
sign. This conversion preserves the positive or
negative value of signed integers.
sink current
Current flowing into a device to ground. Always a
positive value.
source-code compatibility
The ability of an MCS 251 microcontroller to execute
recompiled source code written for an MCS 51 micro-
controller.
source current
source mode
Current flowing out of a device from VCC. Always a
negative value.
An operating mode that is selected by a configuration
bit. In source mode, an MCS 251 microcontroller can
execute recompiled source code written for an MCS
51 microcontroller. In source mode, the MCS 251
microcontroller cannot execute unmodified binary
code written for an MCS 51 microcontroller. See
binary mode.
SP
Stack pointer.
SPX
Extended stack pointer.
state time (or state)
The basic time unit of the device; the combined
period of the two internal timing signals, PH1 and
PH2. (The internal clock generator produces PH1 and
PH2 by halving the frequency of the signal on
XTAL1.) With a 16-MHz crystal, one state time
equals 125 ns. Because the device can operate at
many frequencies, this manual defines time require-
ments in terms of state times rather than in specific
units of time.
UART
WDT
Universal asynchronous receiver and transmitter. A
part of the serial I/O port.
Watchdog timer, an internal timer that resets the
device if the software fails to operate properly.
Glossary-6
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GLOSSARY
word
A 16-bit unit of data. In memory, a word comprises
two contiguous bytes.
wraparound
The result of interpreting an address whose
hexadecimal expression uses more bits than the
number of available address lines. Wraparound
ignores the upper address bits and directs access to the
value expressed by the lower bits.
Glossary-7
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Index
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INDEX
#0data16, A-3
#1data16, A-3
#data
programming and verifying nonvolatile
memory, 14-3
ANL instruction, 5-9, 5-11
for bits, A-23
definition, A-3
#data16, A-3
#short, A-3
ANL/ instruction, 5-11
for bits, A-23
8XC251SA, SB, SP, SQ, 1-1
block diagram, 2-2
on-chip peripherals, 2-3
8XC251Sx, 1-1
Arithmetic instructions, 5-8, 5-9
table of, A-14, A-15, A-16
B
8XC51FX, 2-1
B register, 3-15, C-7
as SFR, 3-17, 3-18, C-2, C-3
in register file, 3-13
Base address, 5-4
A
A15:8, 7-1
description, 13-2
Baud rate, See Serial I/O port, Timer 1, Timer 2
Big endien form, 5-2
A16
description, 13-2
Binary and source modes, 2-4, 4-13–4-15, 5-1
opcode maps, 4-14
selection guidelines, 2-4, 4-14
Bit address
AC flag, 5-18, 5-19, C-20
ACALL instruction, 5-15, A-24, A-26
ACC, 3-13, 3-17, 3-18, C-2, C-3, C-7
Accumulator, 3-15
addressing modes, 5-12
definition, A-3
examples, 5-11
in register file, 3-13
See also ACC
AD7:0, 7-1
Bit instructions, 5-1, 5-11–5-12
addressing modes, 5-4, 5-11
bit51, 5-11, A-3
Broadcast address, See Serial I/O port
Bulletin board service (BBS), 1-7, 1-8
Bus cycles, 13-3
description, 13-2
ADD instruction, 5-8, A-14
ADDC instruction, 5-8, A-14
addr11, 5-13, A-3
addr16, 5-13, A-3
addr24, 5-13, A-3
nonpage mode, 13-4
Address spaces, See Memory space, SFRs, Register
file, External memory, Compatibility
Addresses
internal vs external, 4-9
Addressing modes, 3-8, 5-4
See also Data instructions, Bit instructions,
Control instructions
AJMP instruction, 5-15, A-24
ALE
page mode, 13-5
C
Call instructions, 5-15
Capacitors
bypass, 11-2
CCAP1H–CCAP4H, CCAP1L–CCAP4L, 3-17, 3-
20, C-2, C-5, C-8
CCAPM1–4, 3-17, 3-19, 9-15, C-2, C-5, C-9
interrupts, 6-5
CCON, 3-17, 3-19, 9-14, C-2, C-5, C-10
Ceramic resonator, 11-4
CEX4:0, 7-1
caution, 11-7
description, 13-2
extending, 4-13
following reset, 11-7
idle mode, 12-4
CH, CL, 3-17, 3-20, C-2, C-5, C-10
Index-1
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8XC251SA, SB, SP, SQ USER’S MANUAL
CJNE instruction, A-25
Clock, 2-6
CPL instruction, 5-9, 5-11, A-17, A-23
CPU, 2-5
external, 11-4, 11-5
block diagram, 2-5
external source, 11-3
idle and powerdown modes, 12-5
idle mode, 12-4
Crystal
for on-chip oscillator, 11-3
CY flag, 5-18, 5-19, C-20
powerdown mode, 12-5, 12-6
sources, 11-3
CLR instruction, 5-9, 5-11, A-17, A-23
CMOD, 3-17, 3-19, 9-13, C-2, C-5, C-11
interrupts, 6-5
D
DA instruction, A-16
Data instructions, 5-1, 5-4–5-10
addressing modes, 5-4
Data pointer, See DPH, DPL, DPTR, DPX, DPXL
Data transfer instructions, 5-10
table of, A-22
See also Move instructions
Data types, 5-2
Datasheets
CMP instruction, 5-8, 5-14, A-15
Code constants, 4-16
Code fetches
external, 13-1, 13-5
internal, 13-5
page hit and page miss, 13-6
page mode, 13-6
on WWW, 1-7
Code memory
DEC instruction, 5-8, A-16
Destination register, 5-3
Device
signal descriptions, B-3
dir16, A-3
MCS 51 architecture, 3-3
See also On-chip code memory, External code
memory
Compatibility (MCS 251 and MCS 51
architectures), 2-1, 3-2–3-5
address spaces, 3-2, 3-4
external memory, 3-5
instruction set, 5-1
SFR space, 3-5
See also Binary and source modes
CompuServe, 1-7
dir8, A-3
Direct addressing, 5-4
in control instructions, 5-13
Displacement addressing, 5-4, 5-8
DIV instruction, 5-9, A-16
Division, 5-9
DJNZ instruction, A-25
Documents
Configuration
external memory, 4-8
overview, 4-1
wait states, 4-1–4-2
ordering, 1-7
related, 1-5
DPH, DPL, 3-15, C-12
as SFRs, 3-17, 3-18, C-2, C-3
DPTR, 3-15
in jump instruction, 5-13
DPX, 3-5, 3-13, 3-15, 5-4
DPXL, 3-15, C-13
Configuration array, 4-1–4-4
on-chip, 4-2
Configuration bits, 4-4–4-6
UCON bit, 4-4
Configuration bytes, 4-1
bus cycles, 13-15
programming and verifying, 14-1
UCONFIG0 (table), 4-6
UCONFIG1 (table), 4-7
Control instructions, 5-1, 5-12–5-16
addressing modes, 5-12, 5-13
table of, A-24
as SFR, 3-17, 3-18, C-2, C-3
external data memory mapping, 3-5, 5-4, 5-10
reset value, 3-5
E
EA#, 3-8
description, 13-2
ECALL instruction, 5-15, A-24
Core, 2-4
SFRs, 3-18, C-3
Index-2
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INDEX
ECI, 7-1
G
EJMP instruction, 5-15, A-24
EMAP# bit, 3-9, 4-16
Encryption, 14-2
Given address, See Serial I/O port
Ground bounce, 11-2
Encryption array
H
key bytes, 14-8
Hardware
programming, 14-1, 14-8
setup for programming, 14-4–14-5
ERET instruction, 5-15, A-24
Escape prefix (A5H), 4-14
Extended stack pointer, See SPX
Extending ALE, A-1
extending ALE, A-11
External address lines
number of, 4-9
application notes, 1-6
Help desk, 1-7
I
I/O ports, 7-1–7-9
external memory access, 7-7, 7-8
latches, 7-2
loading, 7-7
pullups, 7-6
External bus
quasi-bidirectional, 7-6
SFRs, 3-18
See also Ports 0–3
Idle mode, 2-4, 12-1, 12-4–12-5
entering, 12-4
inactive, 13-3
pin status, 13-16, 13-17
structure in page mode, nonpage mode, 13-5
External bus cycles, 13-3
definitions, 13-3
exiting, 11-6, 12-5
external bus, 13-3
IE, 6-3, 6-5
IE0, 3-17, 3-18, 6-6, 6-14, 10-11, C-2, C-3, C-14
Immediate addressing, 5-4
INC instruction, 5-8, A-16
Indirect addressing, 5-4
in control instructions, 5-13
in data instructions, 5-6
Instruction set
extended ALE wait state, 13-10
extended RD#/WR#/PSEN# wait state, 13-8
nonpage mode, 13-4, 13-5
page mode, 13-5–13-7
page-hit vs page-miss, 13-5
External code memory
example, 13-20, 13-30
idle mode, 12-4
powerdown mode, 12-5
External memory, 3-10
design examples, 13-18–13-30
MCS 51 architecture, 3-2, 3-4, 3-5
External memory interface
configuring, 4-8–4-16
signals, 13-1
MCS 251 architecture, 5-1
MCS 51 architecture, 5-1
Instructions
arithmetic, 5-8
bit, 5-11
data, 5-4
data transfer, 5-10
External RAM
example, 13-26
exiting idle mode, 12-5
logical, 5-9
INT1:0#, 6-1, 7-1, 8-1, 8-3
pulse width measurements, 8-10
Interrupt request, 6-1
cleared by hardware, 6-4
Interrupt service routine
exiting idle mode, 12-5
exiting powerdown mode, 12-6
Interrupts, 6-1–6-15
F
F0 flag, 5-18, C-20
FaxBack service, 1-7, 1-8
Flash memory
example, 13-18, 13-20, 13-30
blocking conditions, 6-14
Index-3
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detection, 6-3
edge-triggered, 6-4
JSLE instruction, A-25
Jump instructions
enable/disable, 6-5
bit-conditional, 5-14
compare-conditional, 5-14
unconditional, 5-15
JZ instruction, A-24
exiting idle mode, 12-5
exiting powerdown mode, 12-6
external, 6-3, 6-11
global enable, 6-5
instruction completion time, 6-10
latency, 6-9–6-13
level-triggered, 6-4
K
Key bytes, See Encryption array
PCA, 6-5
polling, 6-9, 6-10
L
Latency, 6-9
priority, 6-1, 6-3, 6-4, 6-7
priority within level, 6-7
processing, 6-9–6-15
request, See Interrupt request
response time, 6-9, 6-10
sampling, 6-3, 6-10
serial port, 6-5
service routine (ISR), 6-4, 6-9, 6-14, 6-15
sources, 6-3
LCALL instruction, 5-15, A-24
LJMP instruction, 5-15, A-24
Lock bits
programming and verifying, 14-1, 14-7
protection types, 14-8
setup for programming and verifying, 14-4–
14-5
Logical instructions, 5-9
table of, A-17
timer/counters, 6-4
vector cycle, 6-14
vectors, 3-3, 6-4
M
MCS 251 microcontroller, 2-1
core, 2-4
INTR bit
and RETI instruction, 4-16, 5-16
IPH0, 3-17, 3-18, 6-3, 6-8, 6-14, C-2, C-3, C-15
bit definitions, 6-7
IPL0, 3-17, 3-18, 6-3, 6-8, 6-14, C-2, C-3, C-16
bit definitions, 6-7
features, 2-1
MCS 51 microcontroller, 2-1
Memory space, 2-4, 3-1, 3-5–3-10
compatibility, See Compatibility (MCS 251
and MCS 51 architectures)
regions, 3-2, 3-5
ISR, See Interrupts, service routine
reserved locations, 3-5
Miller effect, 11-5
MOV instruction, A-19, A-20, A-21
for bits, 5-11, A-23
MOVC instruction, 3-2, 5-10, A-21
Move instructions
J
JB instruction, 5-14, A-24
JBC instruction, 5-14, A-24
JC instruction, A-24
JE instruction, A-24
JG instruction, A-24
JLE instruction, A-24
JMP instruction, A-24
JNB instruction, 5-14, A-24
JNC instruction, A-24
JNE instruction, A-24
JNZ instruction, A-24
JSG instruction, A-25
JSGE instruction, A-25
JSL instruction, A-24
table of, A-19
MOVH instruction, 5-10, A-21
MOVS instruction, 5-10, A-21
MOVX instruction, 3-2, 5-10, A-21
MOVZ instruction, 5-10, A-21
MUL instruction, 5-9
Multiplication, 5-9
Index-4
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INDEX
for bits, A-23
Oscillator, 2-6
N
N flag, 5-9, 5-19
at startup, 11-7
during reset, 11-5
on-chip, 11-3
ONCE mode, 12-7
powerdown mode, 12-5, 12-6
programming and verifying nonvolatile
memory, 14-3
Noise reduction, 11-2, 11-3, 11-5
Nonpage mode
bus cycles, See External bus cycles, Nonpage
mode
bus structure, 13-1
configuration, 4-8
design example, 13-22, 13-26
port pin status, 13-16
Nonpage Mode Bus Cycles, 13-4
Nonvolatile memory
programming and verifying, 14-1–14-9
NOP instruction, 5-15, A-25
OTPROM/EPROM (on-chip)
programming algorithm, 14-5
programming and verifying, 14-3
verify algorithm, 14-6
See also On-chipcode memory, Configuration
bytes, Lock bits, Encryption array,
Signature bytes
O
OV bit, 5-18, 5-19, C-20
Overflow See OV bit
On-chip code memory, 3-2, 13-8
accessing in data memory, 4-16
accessing in region 00:, 3-9
idle mode, 12-4
P
P bit, 5-18, C-20
powerdown mode, 12-5
programming and verifying, 14-1, 14-7
setup for programming and verifying, 14-3–
14-5
P0, 3-17, 3-18, 7-2, C-2, C-3, C-17
P1, 3-17, 3-18, 7-2, C-2, C-3, C-17
P2, 3-17, 3-18, 7-2, C-2, C-3, C-18
P3, 3-17, 3-18, 7-2, C-2, C-3, C-18
Page mode, 2-5
starting address, 3-8, 14-2
top eight bytes, 3-9, 14-2
See also OTPROM/EPROM, ROM
On-chip oscillator
hardware setup, 11-1
On-chip RAM, 3-2, 3-8
bit addressable, 3-8, 5-11
bit addressable in MCS 51 architecture, 5-11
idle mode, 12-4
address access time, 13-6
bus cycles, See External bus cycles, page
mode
configuration, 4-8
design example, 13-20, 13-29
port pin status, 13-17
PAGE# bit, 4-8
PCA
MCS 51 architecture, 3-3, 3-4
reset, 11-6
compare/capture modules, 9-1
idle mode, 12-4
pulse width modulation, 9-11
SFRs, 3-19, C-5
ONCE mode, 12-1, 12-7
entering, 12-7
exiting, 12-7
timer/counter, 9-1
Opcodes
watchdog timer, 9-1, 9-9
PCON, 3-17, 3-18, 10-7, 12-1, 12-2, 12-5, C-2, C-
3, C-19
for binary and source modes, 4-13, 5-1
map, A-4
binary mode, 4-15
source mode, 4-15
idle mode, 12-4
powerdown mode, 12-6
reset, 11-6
See also Binary and source modes
ORL instruction, 5-9, 5-11
for bits, A-23
Peripheral cycle, 2-6
Phase 1 and phase 2, 2-6
ORL/ instruction, 5-11
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Phone numbers, customer support, 1-7
Pin conditions, 12-3
Pins
ports 1, 2, 3, 7-6
Pulse width measurements, 8-10
PUSH instruction, 3-15, 5-10, A-22
unused inputs, 11-2
Pipeline, 2-5
POP instruction, 3-15, 5-10, A-22
Port 0, 7-2
Q
Quick-pulse algorithm, 14-1
and top of on-chip code memory, 14-2
pullups, 7-8
structure, 7-3
R
RCAP2H, RCAP2L, 3-17, 3-19, 8-2, 10-12, C-2,
C-4, C-21
See also External bus
Port 1, 7-2
RD#, 7-1
described, 13-2
structure, 7-3
regions for asserting, 4-9
RD1:0 configuration bits, 4-9
Read-modify-write instructions, 7-2, 7-5
Real-time wait states, 13-10
Register addressing, 5-4, 5-5
Register banks, 3-2, 3-12
accessing in memory address space, 5-4
implementation, 3-12, 3-13
MCS 51 architecture, 3-3
selection bits (RS1:0), 5-18, 5-19, C-20
Register file, 2-5, 3-1, 3-5, 3-10–3-15
address space, 3-2
Port 2, 7-2
and top of on-chip code memory, 14-2
structure, 7-4
See also External bus
Port 3, 7-2
structure, 7-3
Ports
at power on, 11-7
exiting idle mode, 12-5
exiting powerdown mode, 12-5
extended execution times, 5-1, A-1, A-11
programming and verifying nonvolatile
memory, 14-3, 14-5, 14-6
Power supply, 11-2
Powerdown mode, 2-4, 12-1, 12-5–12-6
accidental entry, 12-4
entering, 12-6
exiting, 11-6, 12-6
external bus, 13-3
PROG#, 14-1
Program status word See PSW, PSW1
PSEN#
addressing locations in, 3-13
and reset, 11-6
MCS 51 architecture, 3-4
naming registers, 3-13
register types, 3-13
Registers, See Register addressing, Register banks,
Register file
rel, A-3
Relative addressing, 5-4, 5-13
Reset, 11-5–11-8
cold start, 11-6, 12-1
caution, 11-7
description, 13-2
idle mode, 12-4
programming and verifying nonvolatile
memory, 14-3
entering ONCE mode, 12-7
exiting idle mode, 12-5
exiting powerdown mode, 12-6
externally initiated, 11-6
need for, 11-7
operation, 11-6
power on, 11-7
power-on setup, 11-1
regions for asserting, 4-9
PSW, A-26
PSW, PSW1, 3-17, 3-18, 5-16–5-17, C-2, C-3, C-
21
conditional jumps, 5-14
effects of instructions on flags, 5-17
PSW1, A-26
timing sequence, 11-6, 11-8
warm start, 11-6, 12-1
Response time, 6-9
RET instruction, 5-15, A-24
Pullups, 7-8
Index-6
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RETI instruction, 6-1, 6-14, 6-15, A-24
Return instructions, 5-15
RL instruction, A-17
full-duplex, 10-6
given address, 10-8
half-duplex, 10-4
RLC instruction, A-17
ROM (on-chip), 14-1
interrupts, 10-1, 10-8
mode 0, 10-4–10-5
verifying, 14-1–14-9
modes 1, 2, 3, 10-6
See also On-chip code memory, Configuration
bytes, Lock bits, Encryption array,
Signature bytes.
multiprocessor communication, 10-7
SFRs, 3-19, 10-1, 10-2, C-4
synchronous mode, 10-4
timer 1 baud rate, 10-11, 10-12
timer 2 baud rate, 10-12–10-14
timing, mode 0, 10-5
SETB instruction, 5-11, A-23
SFRs
Rotate instructions, 5-9
RR instruction, A-17
RRC instruction, A-17
RST, 11-6, 11-7
exiting idle mode, 12-5
exiting powerdown mode, 12-6
ONCE mode, 12-7
accessing, 3-16
address space, 3-1, 3-2
idle mode, 12-4
power-on reset, 11-7
programming and verifying nonvolatile
memory, 14-3
RTWCE (Real Time WAIT CLOCK Enable) Bit,
13-12
RTWE (Real Time WAIT# Enable) Control Bit,
13-12
map, 3-17, C-2
MCS 51 architecture, 3-4
powerdown mode, 12-5
reset initialization, 11-6
reset values, 3-16
tables of, 3-18
RXD, 7-1, 10-1
unimplemented, 3-2, 3-16
Shift instruction, 5-9
Signal descriptions, B-3
Signature bytes
mode 0, 10-4
modes 1, 2, 3, 10-6
values, 14-8
S
verifying, 14-1, 14-8
SJMP instruction, 5-15, A-24
SLL instruction, 5-9, A-17
Software
application notes, 1-6
Source register, 5-3
SP, 3-15, 3-17, 3-18, C-2, C-3, C-25
Special function registers See SFRs
SPH, 3-15, 3-17, 3-18, C-2, C-3, C-26
SPX, 3-13, 3-15
SRA instruction, 5-9, A-18
SRL instruction, 5-9, A-18
State time, 2-6
SADDR, 3-17, 3-19, 10-2, 10-8, 10-9, 10-10, C-2,
C-4, C-22
SADEN, 3-17, 3-19, 10-2, 10-8, 10-9, 10-10, C-2,
C-4, C-23
SBUF, 3-17, 3-19, 10-2, 10-4, 10-5, C-2, C-4, C-23
SCON, 3-17, 3-19, 10-2, 10-3, 10-4, 10-5, 10-6,
10-7, C-2, C-4, C-24, C-25
bit definitions, 10-3
interrupts, 6-5
Security, 14-2
Serial I/O port, 10-1–10-14
asynchronous modes, 10-6
automatic address recognition, 10-7–10-10
baud rate generator, 8-8
SUB instruction, 5-8, A-14
SUBB instruction, 5-8, A-14
SWAP instruction, 5-9, A-18
baud rate, mode 0, 10-4, 10-10
baud rate, modes 1, 2, 3, 10-6, 10-10–10-14
broadcast address, 10-9
T
data frame, modes 1, 2, 3, 10-6
framing bit error detection, 10-7
T1:0, 7-1, 8-3
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T2, 7-1, 8-3
SFRs, 3-19, C-4
T2CON, 3-17, 3-19, 8-1, 8-2, 8-10, 8-17, 10-13, C-
2, C-4, C-27
baud rate generator, 10-12
T2EX, 7-1, 8-3, 8-11, 10-12
T2MOD, 3-17, 3-19, 8-1, 8-2, 8-10, 8-16, 13-11,
C-2, C-4, C-28
signal descriptions, 8-3
See also Timer 0, Timer 1, Timer 2
TMOD, 3-17, 3-19, 8-1, 8-2, 8-3, 8-6, 8-7, 10-11,
C-2, C-4, C-30
Tosc, 2-6
See also Oscillator
Target address, 5-4
TCON, 3-17, 3-19, 8-1, 8-2, 8-3, 8-6, 8-8, C-2, C-
4, C-29
TRAP instruction, 5-16, 6-3, 6-5, 6-15, A-25
TXD, 7-1, 10-1
mode 0, 10-4
interrupts, 6-1
modes 1, 2, 3, 10-6
Tech support, 1-7
TH2, TL2
U
baud rate generator, 10-12, 10-14
THx, TLx (x = 0, 1, 2), 3-17, 3-19, 8-2, C-2, C-4,
C-31, C-32
UART, 10-1
UCON, 4-4–4-6
UCONFIG0, 4-2
UCONFIG1, 4-2
UD flag, 5-18, C-20
Timer 0, 8-3–8-8
applications, 8-9
auto-reload, 8-5
interrupt, 8-3
mode 0, 8-3
mode 1, 8-4
V
Vcc, 11-2
during reset, 11-5
power off flag, 12-1
power-on reset, 11-7
powerdown mode, 12-5, 12-6
See also Power supply
Vcc2, 11-2
Vpp, 14-1
requirements, 14-3
Vss1, 11-2
mode 2, 8-5
mode 3, 8-5
pulse width measurements, 8-10
Timer 1
applications, 8-9
auto-reload, 8-9
baud rate generator, 8-6
interrupt, 8-6
mode 0, 8-6
Vss2, 11-2
mode 1, 8-9
mode 2, 8-9
mode 3, 8-9
W
Wait states, 4-12, 5-1, 13-8, A-1, A-11
configurable, 13-8
pulse width measurements, 8-10
Timer 2, 8-10–8-17
auto-reload mode, 8-12
baud rate generator, 8-14
capture mode, 8-11
clock out mode, 8-14
interrupt, 8-11
configuration bits, 4-12
extending ALE, 4-13, 13-10
extending RD#/WR#/PSEN#, 13-8
RD#/WR#/PSEN#, 4-12, 4-13
real-time, 13-10
WAIT# (Wait State) Input, 13-2
Watchdog timer (hardware), 8-16–8-18
enabling, disabling, 8-16
in idle mode, 8-18
mode select, 8-15
Timer/counters, 8-1–8-17
external input sampling, 8-3
internal clock, 8-3
interrupts, 8-1
in powerdown mode, 8-18
initiating reset, 11-6
overflow, 8-16
overview, 8-1–8-3
registers, 8-2
Index-8
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INDEX
SFR (WDTRST), 3-19, C-4
WCLK (Wait Clock) Output, 13-2
WCON, 3-17, 13-11, C-2, C-3, C-32
WDTRST, 3-17, 3-19, 8-2, 8-16, C-2, C-4, C-33
World Wide Web, 1-7
WR#, 7-1
described, 13-2
X
XALE# bit, 4-13
XCH instruction, 5-10, A-22
XCHD instruction, 5-10, A-22
XRL instruction, 5-9
XTAL1, XTAL2, 11-3
capacitance loading, 11-5
Z
Z flag, 5-9, 5-19
Index-9
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