Intel Computer Hardware 31154 User Manual
®
Intel 31154 133 MHz PCI Bridge  
Design Guide  
Design Guide  
April 2004  
Order Number: 278944-001  
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Contents  
Contents  
1
About This Document......................................................................................................................7  
1.1 Terminology and Definitions .................................................................................................7  
Introduction......................................................................................................................................9  
2
2.1  
2.2  
2.3  
2.4  
Product Overview .................................................................................................................9  
Features List.......................................................................................................................10  
Related External Specifications ..........................................................................................11  
References .........................................................................................................................11  
3
Package Information......................................................................................................................13  
3.1 Total Signal Count ..............................................................................................................17  
4
5
Terminations..................................................................................................................................19  
PCI/PCI-X Interface .......................................................................................................................29  
5.1  
5.2  
5.3  
PCI/PCI-X Voltage Levels...................................................................................................29  
Interrupt Routing.................................................................................................................29  
IDSEL Lines........................................................................................................................30  
5.3.1 Primary IDSEL Line ...............................................................................................30  
5.3.2 Secondary IDSEL Lines.........................................................................................30  
5.3.3 Secondary IDSEL Masking....................................................................................31  
5.3.4 Secondary Clock Control .......................................................................................31  
CompactPCI* Hot Swap Mode Select ................................................................................31  
Opaque Memory Region Enable ........................................................................................31  
PCI-X Initialization Clocking Modes....................................................................................32  
5.6.1 Primary PCI Clocking Mode...................................................................................32  
5.6.2 Secondary PCI Clocking Mode..............................................................................32  
5.6.3 Primary-to-Secondary Frequency Limits................................................................34  
5.4  
5.5  
5.6  
6
7
Routing Guidelines ........................................................................................................................35  
6.1  
6.2  
6.3  
Crosstalk.............................................................................................................................36  
EMI Considerations ............................................................................................................37  
Power Distribution and Decoupling.....................................................................................38  
6.3.1 Decoupling Recommendations..............................................................................38  
Trace Impedance................................................................................................................39  
6.4  
PCI-X Layout Guidelines ...............................................................................................................41  
7.1  
7.2  
PCI Clock Layout Guidelines..............................................................................................42  
PCI-X Topology Layout Guidelines.....................................................................................44  
7.2.1 Single Slot at 133 MHz ..........................................................................................45  
®
7.2.1.1 Intel 31154 133 MHz PCI Bridge Embedded Application at 133 MHz.46  
7.2.2 Dual-Slot at 100 MHz.............................................................................................47  
®
7.2.2.1 Embedded Intel 31154 133 MHz PCI Bridge Application at 100 MHz.48  
7.2.3 Quad-Slots at 66 MHz ...........................................................................................49  
®
7.2.3.1 Embedded Intel 31154 133 MHz PCI Bridge Application at 66 MHz...51  
7.2.4 PCI-X at 33 MHz....................................................................................................52  
7.2.4.1 Embedded PCI-X Specification PICMG 1.2 Overview...........................52  
®
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7.2.4.2 PICMG 1.2 System Overview ................................................................52  
Power Considerations ...................................................................................................................57  
8
8.1  
8.2  
Analog Power Pins .............................................................................................................57  
Power Sequencing..............................................................................................................58  
9
Customer Reference Board...........................................................................................................59  
10  
Debug Connectors and Logic Analyzer Connectivity ....................................................................61  
10.1 Probing PCI-X Signals........................................................................................................61  
11  
12  
Thermal Solutions..........................................................................................................................69  
References....................................................................................................................................71  
12.1 Related Documents ............................................................................................................71  
Figures  
®
1
2
3
4
5
6
7
8
9
Intel 31154 133 MHz PCI Bridge Applications............................................................................ 9  
®
Intel 31154 133 MHz PCI Bridge Package...............................................................................14  
®
Intel 31154 133 MHz PCI Bridge Ball Map—Top View, Left Side ............................................15  
®
Intel 31154 133 MHz PCI Bridge Ball Map—Top View, Right Side..........................................16  
IDSEL Mapping ..........................................................................................................................30  
Crosstalk Effects on Trace Distance and Height........................................................................36  
PCB Ground Layout Around Connectors ...................................................................................37  
PCI Clock Distribution and Matching Requirements...................................................................43  
Single-Slot Point-to-Point Topology............................................................................................45  
®
10 Embedded Intel 31154 133 MHz PCI Bridge Design 133 MHz PCI-X Layout..........................46  
11 Dual-Slot Configuration ..............................................................................................................47  
12 Embedded Intel 31154 133 MHz PCI Bridge Design 100 MHz PCI-X Layout..........................48  
®
13 Quad-Slots 66 MHz Topology ....................................................................................................49  
®
14 Embedded Intel 31154 133 MHz PCI Bridge Wiring for 66 MHz..............................................51  
15 An Example of an ePCI-X System..............................................................................................53  
16 PCI-X Data Bus PICMG 1.2 Style Backplane.............................................................................54  
17 PCI-X Clock PICMG 1.2 Style Backplane ..................................................................................55  
18 P_VCCA Filter ............................................................................................................................57  
19 S_VCCA Filter ............................................................................................................................57  
20 PVIO Voltage Protection Diode ..................................................................................................58  
®
21 Intel IQ31154 Customer Reference Board Block Diagram.......................................................59  
Tables  
1
Terminology and Definition........................................................................................................... 7  
2
3
4
5
6
7
8
PCI-to-PCI Bridge Configurations................................................................................................. 9  
Features List...............................................................................................................................10  
Total Signal Count......................................................................................................................17  
Pull-Up/Pull-Down Terminations.................................................................................................19  
PCI/PCI-X Voltage Levels ..........................................................................................................29  
HS_FREQ Encoding...................................................................................................................31  
PCI-X Clocking Modes ...............................................................................................................33  
®
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Contents  
9
Secondary Bus Frequency Initialization......................................................................................33  
10 PCI-X Initialization Pattern..........................................................................................................34  
®
11 Intel 31154 133 MHz PCI Bridge Decoupling Recommendations............................................38  
12 Add-in Card Routing Parameters................................................................................................41  
13 PCI-X Slot Guidelines.................................................................................................................44  
14 Wiring Lengths for 133 MHz Slot................................................................................................45  
15 Wiring Lengths for Embedded 133 MHz Design.........................................................................46  
16 Wiring Lengths for 100 MHz Dual-Slot .......................................................................................47  
17 Wiring Lengths for Embedded 100 MHz Design.........................................................................48  
18 Wiring Lengths for 66 MHz Quad-Slot........................................................................................49  
19 Wiring Lengths for Embedded 66 MHz Design...........................................................................51  
20 Wiring Lengths for PICMG 1.2 Backplane..................................................................................54  
21 PCI-X Clock Wiring Lengths for PICMG Backplane ...................................................................55  
22 Customer Reference Board Stackup..........................................................................................60  
23 Logic Analyzer Pod 1..................................................................................................................62  
24 Logic Analyzer Pod 2..................................................................................................................63  
25 Logic Analyzer Pod 3..................................................................................................................64  
26 Logic Analyzer Pod 4..................................................................................................................65  
27 Logic Analyzer Pod 5..................................................................................................................66  
28 Logic Analyzer Pod 6..................................................................................................................67  
29 Operational Power......................................................................................................................69  
30 Design Reference Material .........................................................................................................71  
®
31 Intel Related Documentation ....................................................................................................71  
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Contents  
Revision History  
Date  
Revision  
001  
Description  
April 2004  
Initial release  
®
6
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About This Document  
About This Document  
1
This document provides layout information and guidelines for designing platform or add-in board  
®
applications with the Intel 31154 133 MHz PCI Bridge.  
This document is intended to be used as a guideline only. Intel recommends that you employ best-  
known design practices with board-level simulation, signal-integrity testing, and validation for a  
robust design. Please note that this design guide focuses on specific design considerations for the  
31154 Bridge and is not intended to be an all-inclusive list of all good design practices. Use this  
guide as a starting point, and use empirical data to optimize your particular design.  
1.1  
Terminology and Definitions  
Table 1.  
Terminology and Definition (Sheet 1 of 2)  
Term  
Definition  
31154  
Intel® 31154 133 MHz PCI Bridge  
Stripline in a PCB is composed of the  
conductor inserted in a dielectric with GND  
planes to the top and bottom, as shown in the  
cross-section diagram at left.  
Stripline  
NOTE: An easy way to distinguish stripline  
from microstrip is that you need to  
strip away layers of the board to view  
the trace on stripline.  
Microstrip in a PCB is composed of the  
conductor on the top layer above the  
dielectric with a ground plane below, as  
shown in the cross-section diagram at left.  
Microstrip  
Prepreg is material used for the lamination process of manufacturing PCBs. It consists of a  
layer of epoxy material that is placed between two cores. This layer melts into epoxy when  
heated and forms around adjacent traces.  
Prepreg  
Core  
Core material is used for the lamination process of manufacturing PCBs. This material is two-  
sided laminate with copper on each side. The core is an internal layer that is etched.  
Printed circuit board: An example PCB  
manufacturing process consists of the  
following steps:  
Layer 1: copper  
Prepreg  
Layer 2: GND  
•
A PCB consists of alternating layers of  
core and prepreg stacked.  
Core  
•
•
•
•
•
The finished PCB is heated and cured.  
The via holes are drilled.  
PCB  
Layer 3: VCC  
Prepreg  
Layer 4: copper  
Plating covers holes and outer surfaces.  
Etching removes unwanted copper.  
Example of a cross-section of  
a four-layer stack  
The PCB is tinned, coated with solder  
mask, and silk-screened.  
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About This Document  
Table 1.  
Terminology and Definition (Sheet 2 of 2)  
Term  
Definition  
An aggressor network is a network that transmits a coupled signal to another network.  
Zo  
Zo  
Aggressor  
Victim Network  
Zo  
Zo  
Aggressor Network  
B3337-01  
A network that receives a coupled cross-talk signal from another network is a called the victim  
network.  
Victim  
A network is the trace of a PCB that completes an electrical connection between two or more  
components.  
Network  
Stub  
A stub is a branch from a trunk terminating at the pad of an agent.  
Inter-Symbol Interference (ISI) occurs when a transition that has not been completely  
dissipated interferes with a signal being transmitted down a transmission line. ISI can impact  
both timing and signal integrity. It is dependent on frequency, time delay of the line, and the  
refection coefficient at the driver and receiver. Examples of ISI patterns that can be used in  
testing at the maximum allowable frequencies are the sequences shown below:  
ISI  
0101 0101 0101 0101  
0011 0011 0011 0011  
000 1110 0011 1000 1111  
A device is a component of a PCI system that connects to a PCI bus. As defined by PCI 2.3,  
a device can be a single-function or a multi-function device.  
Device  
Downstream A transaction that targets the secondary side of the bridge is a downstream transaction.  
Upstream  
SHB  
A transaction that targets the primary side of the bridge is an upstream transaction.  
SHB is a system host board in a PICMIG 1.2 backplane. The removable CPU board provides  
clocks and arbitration signals as well as an optional ATX power supply control.  
ePCI-X  
CRB  
Embedded PCI-X specification  
Customer Reference Board  
§ §  
®
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Introduction  
Introduction  
2
2.1  
Product Overview  
®
The Intel 31154 133 MHz PCI Bridge (called hereafter the “31154”) is a PCI component that  
functions as a highly concurrent, low-latency transparent bridge between two PCI buses. The  
31154 can operate as a PCI-to-PCI bridge in the configurations shown in Table 2.  
Table 2.  
PCI-to-PCI Bridge Configurations  
Primary Bus Interface  
Secondary Bus Interface  
PCI 2.3  
PCI 2.3  
PCI-X  
PCI 2.3  
PCI-X  
PCI 2.3  
PCI-X  
PCI-X  
The 31154 is used on motherboards to provide additional I/O expansion slots. It is also used on PCI  
add-in cards to mitigate the restrictive electrical loading constraints imposed on an expansion slot,  
enabling multiple conventional PCI or multiple PCI-X devices to reside on a single PCI I/O  
adapter. The 31154 block diagram in Figure 1 indicates potential 31154 applications for a range of  
PCI bus speeds.  
®
Figure 1.  
Intel 31154 133 MHz PCI Bridge Applications  
Legacy  
33 MHz  
Legacy  
66 MHz  
Multi PCI-X  
Devices  
High-End  
Application  
CPU Host  
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Introduction  
The 31154 has additional hardware support for CompactPCI* Hot Swap and Redundant System  
Slot via queue flush, arbiter lock, and clock output tristating.  
The 31154 supports any combination of 32-bit and 64-bit data transfers on its primary and  
secondary bus interfaces. The 31154 is 33/66 MHz capable in conventional PCI mode, and can run  
at 66 MHz, 100 MHz, or 133 MHz when operating in PCI-X mode, depending upon its  
surrounding environment.  
2.2  
Features List  
Table 3.  
Features List  
• PCI bus interfaces (2):  
• Secondary bus arbitration:  
— PCI Local Bus Specification,  
— Internal arbiter supports nine agents in  
addition to the 31154.  
Revision 2.3 compliant  
— PCI-to-PCI Bridge Architecture  
Specification, Revision 1.2 compliant  
— Internal arbiter can be disabled.  
— Optimized for PCI-X mode  
— PCI Bus Power Management  
Interface Specification, Revision 1.1  
compliant  
— Bus parking on bridge or last master  
• Improved buffer architecture:  
— PCI-X Addendum to the PCI Local  
Bus Specification, Revision 1.0b  
compliant  
— 8 KBytes data buffers in each  
direction  
— Improved level of concurrency:  
— External SROM support  
— Vital Products Data (VPD) support  
— 64-bit initiator/target capable  
— 64-bit addressing  
Up to nine outstanding transactions on  
each bus simultaneously  
• Scalability and flexibility:  
— Conventional PCI 32/64-bit  
33/66 MHz, 3.3 V  
• Hardware support for dual-host cPCI  
configurations  
— 5 V tolerant inputs  
— PCI-X 32/64-bit 66/100/133 MHz,  
3.3 V  
• Compact PCI Hot Swap Specification,  
Revision 2.1 R2.0 support  
• JTAG interface  
• GPIO interface:  
• Secondary clock generation with 10 clock  
outputs  
— Allows simple software-controlled  
signaling protocols  
®
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Introduction  
2.3  
2.4  
Related External Specifications  
• PCI Local Bus Specification, Revision 2.3  
• PCI-to-PCI Bridge Architecture Specification, Revision 1.1  
• PCI Bus Power Management Interface Specification, Revision 1.1  
• Compact PCI Hot Swap Specification, Revision 2.1 R2.0  
• PCI-X Addendum to the PCI Local Bus Specification, Revision 1.1  
• Embedded PCI-X Specification PICMG 1.2 R1.0  
References  
This section lists references that can be useful with a 31154 application. These documents are  
available on the Intel Developer website (http://developer.intel.com):  
®
• Intel 31154 133 MHz PCI Bridge Datasheet (278821)  
®
• Intel 31154 133 MHz PCI Bridge Developer’s Manual (278848)  
®
• Intel 31154 133 MHz PCI Bridge Specification Update (300826)  
®
• Intel 31154 133 MHz PCI Bridge Design Checklist (300959)  
®
• Intel 31154 133 MHz PCI Bridge Evaluation Board Schematics (278839)  
§ §  
®
Intel 31154 133 MHz PCI Bridge Design Guide Design Guide  
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Introduction  
THIS PAGE INTENTIONALLY LEFT BLANK  
®
12  
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Package Information  
Package Information  
3
®
The Intel 31154 133 MHz PCI Bridge is offered in a 421-lead PBGA package. The mechanical  
dimensions for this package are provided in Figure 2 on page 14.  
Figure 3 on page 15 and Figure 4 on page 16 show the 421-lead PBGA, mapped by pin function.  
These figures are helpful in placing components around the 31154 for the layout of a PCB. To  
simplify routing and minimize the number of cross traces, keep this layout in mind when placing  
components on your board. The signals, by design, are located on the PBGA package to simplify  
signal routing and system implementation. Figure 3 shows the left side of the 31154 ball map, and  
Figure 4 shows the right side of the ball map.  
®
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Package Information  
®
Figure 2.  
Intel 31154 133 MHz PCI Bridge Package  
Notes:  
1. All dimensions and tolerances conform to ANSI Y14.5M-1982.  
PIN #1  
CORNER  
Dimension is measured at the maximum solder ball  
diameter, parallel to primary datum  
0.90  
0.60  
Ø
2
3
22  
23 21  
20 18  
19  
16 14 12 10  
17 15 13 11  
8
6
4
2
2
9
7
5
3
1
Primary datum  
and seating plane are defined by the  
Ø
0.30  
C
A
B
S
S
S
A
B
C
D
E
F
spherical crowns of the solder balls.  
1.27  
4. All dimensions, unless otherwise specified, are in millimeters.  
G
H
J
K
L
M
N
P
R
T
1.27  
// 0.127  
A
U
V
W
Y
AA  
AB  
AC  
31.00 ± 0.10  
26.00 ± 0.20  
1.53 REF  
SEE DETAIL "A"  
1.53 REF  
1.27  
-B-  
BOTTOM VIEW  
31.00 ± 0.10  
(22.10 REF)  
26.00 ± 0.20  
0.127  
A
3 X Ø1.00 THRU  
45˚ CHAMFER  
4 PLACES  
(22.10 REF)  
PIN #1 CORNER  
NO RADIUS  
TOP VIEW  
Au GATE  
1.70  
2.38 ± 0.21  
1.17 ± 0.05  
30˚  
PIN #1 I.D. (SHINY)  
90.0˚  
1.0 DIA. X 0.15 DEPTH  
9.0 X 9.0 FROM CENTER LINE  
// 0.15  
0.15  
C
-C-  
0.61 ± 0.06  
0.60 ± 0.10  
3
SEATING PLANE  
SIDE VIEW  
DETAIL "A"  
NOT TO SCALE  
B1290-01  
®
14  
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Package Information  
®
Figure 3.  
Intel 31154 133 MHz PCI Bridge Ball Map—Top View, Left Side  
1
2
3
4
5
6
7
8
VCCP  
P_  
9
10  
VSS  
P_  
11  
VSS  
P_  
12  
VCCP  
P_  
P_  
P_  
P_  
P_  
P_  
CBE7#  
P_  
PAR64  
VSS  
VSS  
A
B
ACK64# AD56  
AD60 CBE4#  
P_  
AD43  
P_  
P_ P_  
P_  
AD50  
P_  
P_  
VSS  
AD54 SERR# AD49  
AD52 AD55  
AD57 AD59  
AD63 CBE6#  
SCAN_  
EN  
P_  
AD48  
P_  
STOP#  
S_CLK  
P_ P_  
P_ P_  
P_ P_  
VSS  
VCCP  
VCCP  
C
D
E
OEN3 AD53 PERR# AD58 AD61 CBE5# REQ64#  
S_CLK  
OEN2 AD47  
P_  
P_  
AD51  
P_  
AD62  
QE  
P_  
VSS  
VCCP  
VSS  
HS_  
VCC  
HS_  
VCC  
VSS  
HS_  
HS_  
LED_  
OUT  
P_  
S_CLK  
S_TRI  
VCCP R_REF VSS  
VSS  
VCC  
AD38 OEN1 AD45  
LSTAT ENUM#  
STATE FREQ0  
P_  
AD42  
P_  
AD44  
P_  
AD46  
VSS  
VSS  
VCC  
VSS  
VCC  
VSS  
VCC  
VSS  
VCC  
VSS  
F
G
H
P_  
S_CLK  
P_  
HS_  
SM  
VCCP  
AD36 OEN0 AD41  
P_  
AD35  
P_  
AD39  
P_  
AD40  
P_  
M66EN  
VSS  
VCC  
P_  
AD33  
P_  
AD34  
P_  
AD37  
SR_  
CLK  
J
K
L
M
N
P
R
T
S_  
AD34  
S_  
AD33  
S_  
AD32  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
P_  
AD32  
S_  
AD36  
S_  
AD35  
VCC SR_CS  
VSS SR_DO  
VCC SR_DI  
S_  
AD39  
S_  
AD38  
VCCP  
S_  
AD41  
S_  
AD40  
VSS  
VSS  
S_  
AD47  
S_  
AD45  
S_  
VSS  
AD43  
VSS  
VCC  
VSS  
VCC  
S_  
AD37  
S_  
AD49  
S_  
AD48  
S_  
VCC  
GNT7#  
S_  
AD51  
S_  
AD50  
S_  
VSS  
S_VIO  
REQ7#  
S_  
AD42  
S_  
AD53  
S_  
AD52  
S_  
VCCP  
U
GNT6#  
S_  
AD55  
S_MAX  
100  
S_  
VSS  
VSS  
AD54  
VSS  
VSS  
VCC  
VSS  
VSS  
VSS  
VCC  
VSS  
VSS  
VSS  
V
W
Y
S_  
S_  
S_CLK  
S_  
VCCP  
VSS  
VSS  
AD44 REQ2# STABLE  
REQ6#  
S_ S_ S_  
S_  
AD57  
S_  
CBE7#  
VSS  
VCCP  
VCCP  
VSS  
VCC  
VCC  
VSS  
AD46 GNT2# AD56  
S_  
S_  
AD58  
S_  
AD59  
S_  
S_  
S_  
S_  
S_  
S_  
TMODE  
2
VSS  
NC  
AA  
AB  
AC  
REQ1#  
AD61 ACK64# AD00 PAR64 CBE5# AD06  
S_  
GNT1#  
S_  
S_  
S_  
S_  
S_  
S_  
S_  
S_  
S_  
S_  
REQ3#  
VSS  
GNT4# REQ4# AD60  
AD62 AD63  
AD01 CBE6# AD04 CBE0#  
S_  
S_  
S_  
CRS  
TEN  
S_  
S_  
S_  
AD03  
VSS  
VCCP  
VSS  
VSS  
VCCP  
REQ5# GNT5# GNT3#  
CBE4# AD02  
1
2
3
4
5
6
7
8
9
10  
11  
12  
B2240-01  
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Package Information  
®
Figure 4.  
Intel 31154 133 MHz PCI Bridge Ball Map—Top View, Right Side  
13  
14  
VSS  
P_  
15  
16  
17  
18  
VSS  
P_  
19  
20  
21  
22  
23  
P_  
CBE0#  
P_  
P_  
P_  
P_  
P_  
P_  
VCCP  
VSS  
A
B
CBE3# IRDY# FRAME#  
AD04 AD07 VCCA  
P_  
AD00  
P_ P_ P_  
P_ P_ P_  
VSS  
TDO  
AD02 TRDY# AD05  
AD08 CBE1# IDSEL AD15 REQ#  
P_  
AD01  
P_  
AD03  
P_  
AD06  
P_  
AD09  
P_  
PAR  
P_  
P_  
MT0#  
VSS  
TDI  
TRST#  
C
D
E
AD10 GNT#  
P_  
CBE2#  
P_  
AD11  
P_DEV  
SEL#  
P_  
AD22  
VCC  
VCC  
VSS  
VCCP  
VCCP  
VSS  
TMS  
HS_  
FREQ1  
NT_  
MASK#  
P_  
CLK  
P_  
RST#  
P_  
AD24  
VSS  
VSS  
GPIO0 GPIO1  
VSS  
VSS  
VCC  
GPIO2 VCCP  
P_  
VSS  
P_  
AD12  
VCC  
VSS  
VCC  
TCK  
VSS  
F
G
H
J
AD13  
P_  
AD16  
P_  
AD14  
P_  
AD26  
VSS  
VCCP  
VSS  
P_  
AD18  
P_  
AD17  
VSS  
VCC  
P_VIO  
S_  
S_  
P_  
AD20  
P_  
AD19  
P_  
AD31  
VCC  
CLKO0 CLKO2  
S_ S_  
P_  
P_  
AD23  
P_  
AD21  
VSS  
VSS  
VSS  
VSS  
VSS  
K
L
CLKO1 CLKO4 AD25  
S_  
CLKO3  
P_  
AD28  
P_  
AD27  
VCC  
VSS  
VSS  
VSS  
VSS  
S_  
CLKO5  
P_  
AD30  
P_  
AD29  
S_  
AD27  
VSS  
VSS  
VSS  
VSS  
M
N
P
S_  
CLKO6  
S_  
AD30  
S_  
AD31  
S_  
AD25  
VCC  
S_BRG  
S_  
S_  
S_  
AD28  
S_  
AD29  
VSS  
CLKO CLK07 AD26  
S_  
S_  
S_  
AD22  
S_  
AD24  
S_PCIX  
CAP  
VCC  
VSS  
R
T
M66EN CLKO8  
S_ARB  
_DIS  
ABLE  
S_  
AD20  
S_  
AD23  
VCC  
VSS  
VCC  
VCC  
S_  
S_  
AD18  
S_  
AD19  
S_  
RST#  
GCLK VCCP  
OEN  
U
S_  
GNT8#  
S_  
VSS  
S_  
AD16  
S_  
AD17  
VCC GPIO3 GPIO5  
VSS  
V
AD14  
S_  
S_  
AD15  
S_  
AD21  
TMODE  
0
VCC  
VSS  
GPIO4 GPIO6 GPIO7  
VSS  
VCCP  
W
Y
REQ8#  
VCC  
S_  
S_  
TRDY#  
S_  
AD11  
TMODE DEV_ TMODE  
1
VCC  
VSS  
VCCP  
VCCP  
VSS  
64BIT#  
3
S_  
S_  
S_  
S_  
PAR  
S_  
S_  
S_  
REQ0#  
OPAQUE  
_EN  
VSS RSRV0  
AA  
AB  
AC  
AD07 FRAME# CBE3# AD10  
GNT0# AD13  
S_ S_ S_ S_  
REQ64# CBE2# AD09 CBE1# PERR# AD12 SERR# STOP# VCCA  
S_  
S_  
S_ S_  
S_  
S_  
CLKI  
VSS  
S_  
AD05  
S_  
AD08  
S_  
IRDY#  
S_  
DEVSEL#  
IDSEL_  
MASK  
VSS  
VSS  
VCCP  
VSS  
MT1#  
VSS  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
B2241-01  
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Package Information  
3.1  
Total Signal Count  
Table 4.  
Total Signal Count  
Interface  
Signals  
PCI bus interface  
PCI 64-bit extensions  
Clock and reset  
JTAG  
112  
78  
20  
12  
4
Serial ROM interface  
CompactPCI* Hot Swap  
Hardware strap  
Miscellaneous  
Total  
6
5
17  
254  
§ §  
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Package Information  
THIS PAGE INTENTIONALLY LEFT BLANK  
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Terminations  
Terminations  
4
®
This chapter details all the recommended Intel 31154 133 MHz PCI Bridge terminations required  
for the different operating modes.  
The chapter provides the recommended pull-up and pull-down terminations for a 31154 layout.  
Table 5 lists these 31154 termination values. Note that for motherboards, the PCI Local Bus  
Specification, Revision 2.3 requires that the PCI signals provide the termination resistors.  
Table 5.  
Pull-Up/Pull-Down Terminations (Sheet 1 of 9)  
Signal  
Pull-Up/Pull-Down or Termination (See Note 1)  
Comments  
PCI Reset  
P_RST#  
Connect to bus RST# signal on primary PCI bus.  
Connect to bus RST# signal on secondary PCI  
bus.  
S_RST#  
Primary PCI Signals  
P_AD[31:0]  
Connect to primary PCI bus AD[31:0].  
For 64-bit primary PCI bus:  
•
Connect to the AD[63:32] bits of the primary  
PCI bus.  
P_AD[63:32]  
P_CBE[3:0]  
P_CBE[7:4]#  
For 32 bit Primary PCI Bus:  
•
Pull up through individual external resistors  
(see Note 2 and Note 3).  
Connect to the CBE[3:0}# bits of the primary PCI  
bus.  
For 64-bit primary PCI bus:  
•
Connect to the CBE[7:4]# bits of the primary  
PCI bus.  
For 32-bit primary PCI Bus:  
•
Pull up through individual external resistors  
(see Note 2 and Note 3).  
P_FRAME#  
P_DEVSEL#  
P_IRDY#  
Connect to FRAME# of the primary PCI bus.  
Connect to DEVSEL# of the primary PCI bus.  
Connect to IRDY# of the primary PCI bus.  
Connect to TRDY# of the primary PCI bus.  
Connect to STOP# of the primary PCI bus.  
P_TRDY#  
P_STOP#  
NOTES:  
1. The recommended value for pull-up resistors for PCI applications is 5.6 KΩ (note that the minimum value for PCI 3.3 V  
signaling RMIN = 2.42 KΩ, RTYP = 8.2 KΩ, as per the PCI Local Bus Specification, Revision 2.3, section 4.3.3).  
2. The recommended value for pull-up resistors for PCI-X applications is 8.2 KΩ. For PCI-X, the minimum pull-up resistor value  
is 5 KΩ, as per the PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0b, section 9.7.  
3. For plug-in card implementations, the pull-up must be on the motherboard.  
4. Connect PVIO and SVIO pull-up resistors to 5 V or 3.3 V power supply through an external resistor—25 Ω (5 V) or  
0 Ω (3.3 V), depending on the signaling level of the primary/secondary PCI bus. Refer to the power-sequencing guidelines in  
Section 8.2 on page 58.  
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Terminations  
Table 5.  
Pull-Up/Pull-Down Terminations (Sheet 2 of 9)  
Signal  
Pull-Up/Pull-Down or Termination (See Note 1)  
Comments  
P_GNT#  
Connect to GNT# of the primary PCI bus.  
Connect to one of the AD lines of the primary PCI  
bus or to the IDSEL# signal of the PCI edge  
connector (for add-in card applications).  
Refer to Section 5.3, “IDSEL Lines” on page 30 for  
more details.  
P_IDSEL#  
P_M66EN  
Connect to the M66EN signal of the primary PCI  
bus of the PCI add-in card finger.  
P_PAR  
Connect to PAR of the primary PCI bus.  
Connect to PERR# of the primary PCI bus.  
Connect to PERR# of the primary PCI bus.  
P_PAR64  
P_PERR#  
Connect to one of the PCI bus request signals of  
the primary PCI bus.  
P_REQ#  
P_SERR#  
Connect to SERR# of the primary PCI bus.  
Secondary PCI Signals  
Pull up to VCC33 through external 8.2 KΩ  
resistors.  
S_AD[63:32]  
Pull up to VCC33 through external 8.2 KΩ  
S_CBE[7:4]#  
S_REQ64#  
S_ACK64#  
resistors.  
Pull up to VCC33 through external 8.2 KΩ  
resistors.  
Pull up to VCC33 through external 8.2 KΩ  
resistors.  
S_FRAME#,  
S_IRDY#,  
S_TRDY#,  
S_STOP#,  
S_DEVSEL#,  
S_PERR#,  
S_SERR#  
Pull up to VCC33 voltage through external 8.2 KΩ  
resistors.  
S_REQ[8:1]#,  
S_REQ0#/BR_GNT#,  
S_GNT0#/BR_REQ#  
Pull up to VCC33 voltage through external 8.2 KΩ  
resistors.  
Pull-up for both internal and external arbiter mode.  
Secondary GNT#  
S_GNT1#,  
S_GNT2#,  
S_GNT3#,  
S_GNT4#,  
S_GNT5#,  
S_GNT6#,  
S_GNT7#,  
S_GNT8#  
Connect to GNT# input of the PCI devices on the  
secondary PCI bus.  
NC when not used.  
NOTES:  
1. The recommended value for pull-up resistors for PCI applications is 5.6 KΩ (note that the minimum value for PCI 3.3 V  
signaling RMIN = 2.42 KΩ, RTYP = 8.2 KΩ, as per the PCI Local Bus Specification, Revision 2.3, section 4.3.3).  
2. The recommended value for pull-up resistors for PCI-X applications is 8.2 KΩ. For PCI-X, the minimum pull-up resistor value  
is 5 KΩ, as per the PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0b, section 9.7.  
3. For plug-in card implementations, the pull-up must be on the motherboard.  
4. Connect PVIO and SVIO pull-up resistors to 5 V or 3.3 V power supply through an external resistor—25 Ω (5 V) or  
0 Ω (3.3 V), depending on the signaling level of the primary/secondary PCI bus. Refer to the power-sequencing guidelines in  
Section 8.2 on page 58.  
®
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Terminations  
Table 5.  
Pull-Up/Pull-Down Terminations (Sheet 3 of 9)  
Signal  
Pull-Up/Pull-Down or Termination (See Note 1)  
Comments  
These signals can be used as IDSEL lines and are  
connected to IDSEL of the secondary PCI bus  
through an external series coupling resistor (a  
resistor of 2 KΩ is used on the customer reference  
board).  
S_AD[31:17]  
PCI Clocks  
P_CLK  
Connect to the PCI clock on the primary PCI bus.  
•
•
All S_CLKO[8:0] and S_BRGCLKO must  
match in length.  
When the internal clock of the 31154 is used,  
connect to S_CLKI through a 33.2 Ω series  
resistor.  
When there are PCI slots in the design,  
S_BRGCLKO must be 3" longer to  
compensate for the 2.5" trace length from the  
connector to the PCI device on a PCI add-in  
card.  
S_BRGCLKO  
NC when external clock is used.  
•
•
•
These clocks can be disabled by strapping the  
S_CLKOEN[3:0] during reset.  
When the internal clock of the 31154 is used,  
connect to the PCI clock input of the secondary  
PCI devices through a 33.2 Ω series resistor.  
Each clock can be connected to only one PCI  
device.  
All S_CLKO[8:0] and S_BRGCLKO must  
match in length.  
S_CLKO[8:0]  
For asynchronous mode, there is no maximum  
skew between P_CLK and S_CLKI.  
NOTE: These clocks can be disabled by  
strapping the S_CLKOEN[3:0] during  
reset.  
•
When using the internal clock, refer to  
S_BRGCLKO (above) for additional  
information.  
When the internal clock of the 31154 is used,  
connect to S_BRGCLKO.  
•
•
When using an external clock source, all  
secondary clocks must have matching length.  
S_CLKI  
When an external clock is used, connect to  
external clock source.  
When using PCI slots in the design,  
S_BRGCLKO must be 3" longer to  
compensate for the 2.5" trace length from the  
connector to the PCI device on a PCI add-in  
card.  
When the internal clock of the 31154 is used,  
S_CLKSTABLE must be tied high to VCC33  
through an external 8.2 KΩ resistor.  
When an external clock source is used, connect to  
logic that outputs high after the secondary clocks  
are stable.  
S_CLKSTABLE  
NOTES:  
1. The recommended value for pull-up resistors for PCI applications is 5.6 KΩ (note that the minimum value for PCI 3.3 V  
signaling RMIN = 2.42 KΩ, RTYP = 8.2 KΩ, as per the PCI Local Bus Specification, Revision 2.3, section 4.3.3).  
2. The recommended value for pull-up resistors for PCI-X applications is 8.2 KΩ. For PCI-X, the minimum pull-up resistor value  
is 5 KΩ, as per the PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0b, section 9.7.  
3. For plug-in card implementations, the pull-up must be on the motherboard.  
4. Connect PVIO and SVIO pull-up resistors to 5 V or 3.3 V power supply through an external resistor—25 Ω (5 V) or  
0 Ω (3.3 V), depending on the signaling level of the primary/secondary PCI bus. Refer to the power-sequencing guidelines in  
Section 8.2 on page 58.  
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Terminations  
Table 5.  
Pull-Up/Pull-Down Terminations (Sheet 4 of 9)  
Signal  
Pull-Up/Pull-Down or Termination (See Note 1)  
Comments  
When the internal clock of the 31154 is used, pull  
high to VCC33 through an external 8.2 KΩ resistor.  
When an external clock source is used, tie to GND  
through a 330 Ω external resistor. All secondary  
clock outputs (S_CLKO[8:0] and S_BRGCLKO)  
asynchronously tristate.  
S_GCLKOEN  
When an external clock source is used, tie  
S_CLKOEN[3:0] to a stable value. Refer to  
S_CLKOEN[3:0], below.  
These are strapping pins to enable or tristate  
S_CLKO[8:0] after reset.  
NOTE: This strapping is meaningful only when  
S_GCLKOEN is pulled high.  
•
To enable all S_CLKO[8:0], pull each  
S_CLKOEN[3:0] pin to 3.3 V through an  
external 8.2 KΩ resistor.  
When external clocks are used, tie S_GCLKOEN  
low and tie S_CLKOEN[3:0] to some stable value  
(0000b, for example).  
S_CLKOEN[3:0]  
•
To selectively disable some of the  
S_CLKO[8:0], refer to 31154 Control  
Register 2, bits[8:0].  
Hot Swap  
For Hot Swap:  
•
Connect the interrupt input pin to the host.  
HS_ENUM#  
When not using Hot Swap:  
•
NC (there is a weak internal pull-up).  
For Hot Swap:  
•
Connect to cPCI ejector switch.  
HS_LSTAT  
When not using Hot Swap:  
•
Tie low to GND.  
For Hot Swap:  
•
Connect to cPCI blue LED.  
HS_LED_OUT  
When not using Hot Swap:  
•
NC  
For Hot Swap:  
0 = The 31154 retries any Type 0 configuration  
cycles addressed to it until serial ROM  
preload has completed (default)  
0 = Tie low to GND.  
1 = The 31154 ignores (causes master abort) any  
Type 0 configuration cycles addressed to it  
until its serial ROM preload has completed.  
HS_SM  
1 = Pull high to 3.3 V through an external 8.2 KΩ  
resistor.  
When not using Hot Swap:  
•
Tie low to GND.  
NOTES:  
1. The recommended value for pull-up resistors for PCI applications is 5.6 KΩ (note that the minimum value for PCI 3.3 V  
signaling RMIN = 2.42 KΩ, RTYP = 8.2 KΩ, as per the PCI Local Bus Specification, Revision 2.3, section 4.3.3).  
2. The recommended value for pull-up resistors for PCI-X applications is 8.2 KΩ. For PCI-X, the minimum pull-up resistor value  
is 5 KΩ, as per the PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0b, section 9.7.  
3. For plug-in card implementations, the pull-up must be on the motherboard.  
4. Connect PVIO and SVIO pull-up resistors to 5 V or 3.3 V power supply through an external resistor—25 Ω (5 V) or  
0 Ω (3.3 V), depending on the signaling level of the primary/secondary PCI bus. Refer to the power-sequencing guidelines in  
Section 8.2 on page 58.  
®
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Terminations  
Table 5.  
Pull-Up/Pull-Down Terminations (Sheet 5 of 9)  
Signal  
Pull-Up/Pull-Down or Termination (See Note 1)  
Comments  
For Hot Swap:  
•
Depending on Primary PCI Bus frequency  
00 = PCI Mode, 33 or 66 MHz (default)  
01 = PCI-X 66 MHz  
Only valid when HS_SM = 1.  
0 = Tie low to GND.  
HS_FREQ[1:0]  
10 = PCI-X 100 MHz  
1 = Pull high to 3.3 V through external 8.2 KΩ  
resistor.  
11 = PCI-X 133 MHz  
When not using Hot Swap:  
•
Tie low to GND.  
Hardware Straps (sampled at the edge of P_RST#)  
To disable internal secondary arbiter:  
NOTE: S_ARB_LOCK has an effect only when  
the internal arbiter is enabled.  
•
Pull up to 3.3 V through an external 8.2 KΩ  
resistor.  
•
S_GNT0# becomes the secondary PCI bus  
request output of the 31154, and S_REQ0#  
becomes the secondary PCI bus grant input of  
the 31154.  
To enable internal secondary arbiter:  
S_ARB_DISABLE/  
S_ARB_LOCK  
•
Pull down to GND through an external 220 Ω  
resistor (default).  
S_ARB_LOCK (after trailing edge of P_RST#):  
•
Sampled as 1b, the internal secondary bus  
arbiter of the 31154 locks and provides the  
grant only to itself.  
•
When internal arbiter is used and 1b is  
sampled after the trailing edge of P_RST#, the  
internal secondary bus arbiter of the 31154  
locks and provide grant only to itself.  
To limit secondary bus frequency to maximum of  
100 MHz:  
•
Pull high to 3.3 V through an external 8.2 KΩ  
resistor.  
S_MAX100  
Otherwise:  
Pull low to GND through an external 330 Ω  
resistor (default).  
GND during normal operation  
•
S_TRISTATE  
NOTES:  
1. The recommended value for pull-up resistors for PCI applications is 5.6 KΩ (note that the minimum value for PCI 3.3 V  
signaling RMIN = 2.42 KΩ, RTYP = 8.2 KΩ, as per the PCI Local Bus Specification, Revision 2.3, section 4.3.3).  
2. The recommended value for pull-up resistors for PCI-X applications is 8.2 KΩ. For PCI-X, the minimum pull-up resistor value  
is 5 KΩ, as per the PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0b, section 9.7.  
3. For plug-in card implementations, the pull-up must be on the motherboard.  
4. Connect PVIO and SVIO pull-up resistors to 5 V or 3.3 V power supply through an external resistor—25 Ω (5 V) or  
0 Ω (3.3 V), depending on the signaling level of the primary/secondary PCI bus. Refer to the power-sequencing guidelines in  
Section 8.2 on page 58.  
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Terminations  
Table 5.  
Pull-Up/Pull-Down Terminations (Sheet 6 of 9)  
Signal  
Pull-Up/Pull-Down or Termination (See Note 1)  
Comments  
To enable Opaque Memory Base/Limit Registers  
to establish a private memory space for secondary  
bus usage:  
•
Pull high to 3.3 V through an external 8.2 KΩ  
resistor.  
OPAQUE_EN  
To disable Opaque Memory Base/Limit Registers:  
•
Pull low to GND through an external 220 Ω  
resistor (default).  
To enable device hiding after reset (in other words,  
to hide device numbers 16–21 from the host):  
•
Pull high to 3.3 V through an external resistor.  
To disable device hiding after reset:  
IDSEL_MASK  
•
Pull low to GND through an external 220 Ω  
resistor (default).  
After reset, device hiding can be performed  
through software through the Secondary IDSEL  
Select Register (Offset 5Ch).  
This bit is used by the system management  
software to help the user identify the best slot for  
an add-in card:  
•
When the 31154 is installed on an add-in card  
and the add-in card implements a 64-bit PCI  
connector, pull up to 3.3 V through an external  
8.2 KΩ resistor.  
DEV_64BIT#  
•
When the 31154 is not installed on an add-in  
card or the add-in card implements only a  
32-bit PCI connector, pull low to GND through  
a 220 Ω external resistor (default).  
Serial EEPROM  
Serial ROM clock input:  
SR_CLK  
•
•
Connect to the clock input of the EEPROM.  
NC when EEPROM is not required in design.  
Serial ROM data input:  
SR_DI  
•
•
Connect to the DI input of the EEPROM.  
NC when EEPROM is not required in design.  
Serial ROM data output:  
NOTE: When EEPROM is present but register  
preload is not desired, bits[7:6] of the first  
byte can be any value except the preload  
enable value (10b).  
•
•
Connect to the DO output of the EEPROM.  
SR_DO  
Tie high or pull to GND when EEPROM is not  
required in design.  
Serial ROM chip select:  
SR_CS  
•
•
Connect to the chip select of the EEPROM.  
NC when EEPROM is not required in design.  
NOTES:  
1. The recommended value for pull-up resistors for PCI applications is 5.6 KΩ (note that the minimum value for PCI 3.3 V  
signaling RMIN = 2.42 KΩ, RTYP = 8.2 KΩ, as per the PCI Local Bus Specification, Revision 2.3, section 4.3.3).  
2. The recommended value for pull-up resistors for PCI-X applications is 8.2 KΩ. For PCI-X, the minimum pull-up resistor value  
is 5 KΩ, as per the PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0b, section 9.7.  
3. For plug-in card implementations, the pull-up must be on the motherboard.  
4. Connect PVIO and SVIO pull-up resistors to 5 V or 3.3 V power supply through an external resistor—25 Ω (5 V) or  
0 Ω (3.3 V), depending on the signaling level of the primary/secondary PCI bus. Refer to the power-sequencing guidelines in  
Section 8.2 on page 58.  
®
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Terminations  
Table 5.  
Pull-Up/Pull-Down Terminations (Sheet 7 of 9)  
Signal  
Pull-Up/Pull-Down or Termination (See Note 1)  
Comments  
JTAG  
TCK  
Pull low when not used.  
When not used, pull up to 3.3 V through an  
external 8.2 KΩ resistor.  
TDI  
TDO  
TRST#  
NC when not used  
When not used, pull low to GND through an  
external 1 KΩ resistor.  
When not used, pull up to 3.3 V through an  
external 8.2 KΩ resistor.  
TMS  
SCAN_EN  
For normal operation, tie low to GND.  
For normal operation, tie to 0000 or 0111.  
0 = Pull low to GND.  
TMODE[3:0]  
1 = Pull high to 3.3 V through an external 8.2 KΩ  
resistor.  
Voltages  
•
Ensure that the voltage at the input pin is  
within the min./max. range for S_VCCA  
(1.235 V and 1.365 V).  
Connect to 1.3 V supply through a low-pass filter to  
reduce noise-induced jitter. The 4.7 µF capacitor  
must be low ESR solid tantalum, the 0.01 µF  
capacitor must be of type X7R, and the node  
connecting VCCPLL must be as short as possible.  
S_VCCA  
P_VCCA  
•
•
For power sequencing, see Section 8.2,  
“Power Sequencing” on page 58.  
Ensure that the voltage at the input pin is  
within the min./max. range for P_VCCA  
(1.235 V and 1.365 V).  
Connect to 1.3 V supply through a low-pass filter to  
reduce noise-induced jitter. The 4.7 µF capacitor  
must be low ESR solid tantalum, the 0.01 µF  
capacitor must be of type X7R, and the node  
connecting VCCPLL must be as short as possible.  
•
For power sequencing, see Section 8.2,  
“Power Sequencing” on page 58.  
VCC  
Connect to 1.3 V supply.  
Connect to 3.3 V supply.  
VCCP  
Connect to 5 V or 3.3 V power supply through an  
external resistor, depending on the signaling level  
of primary PCI bus (see Note 4).  
PVIO  
SVIO  
Connect to 5 V or 3.3 V power supply through an  
external resistor, depending on the signaling level  
of secondary PCI bus (see Note 4).  
Miscellaneous  
Pull down to GND through an external 30 Ω 1%  
resistor.  
R_REF  
Pull up to 3.3 V through an external 8.2 KΩ series  
resistor.  
MT0# and MT1#  
NOTES:  
1. The recommended value for pull-up resistors for PCI applications is 5.6 KΩ (note that the minimum value for PCI 3.3 V  
signaling RMIN = 2.42 KΩ, RTYP = 8.2 KΩ, as per the PCI Local Bus Specification, Revision 2.3, section 4.3.3).  
2. The recommended value for pull-up resistors for PCI-X applications is 8.2 KΩ. For PCI-X, the minimum pull-up resistor value  
is 5 KΩ, as per the PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0b, section 9.7.  
3. For plug-in card implementations, the pull-up must be on the motherboard.  
4. Connect PVIO and SVIO pull-up resistors to 5 V or 3.3 V power supply through an external resistor—25 Ω (5 V) or  
0 Ω (3.3 V), depending on the signaling level of the primary/secondary PCI bus. Refer to the power-sequencing guidelines in  
Section 8.2 on page 58.  
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Terminations  
Table 5.  
Pull-Up/Pull-Down Terminations (Sheet 8 of 9)  
Signal  
Pull-Up/Pull-Down or Termination (See Note 1)  
Comments  
RSTV0  
Tie to GND through a 0 Ω external resistor.  
Tie to GND through a 0 Ω external resistor.  
RSRV1/CRSTEN  
S_M66EN is meaningful only when S_PCIXCAP is  
connected to GND (that is, when the secondary  
PCI bus is in legacy PCI mode).  
For designs without secondary PCI slot:  
•
When the secondary PCI devices (and  
loading) support 66 MHz PCI bus, pull up to  
3.3 V through an 8.2 KΩ series resistor.  
•
When the secondary PCI devices (and  
loading) do not supports 66 MHz PCI bus,  
GND this pin.  
Refer to PCI-X Addendum to the PCI Local Bus  
Specification, Revision 1.0b, Table 6-1.  
S_M66EN  
For designs with secondary PCI slot:  
•
When the on-board PCI device does not  
support 66 MHz PCI bus, GND this pin.  
•
When the on-board PCI device does support  
66 MHz PCI bus, connect this pin to M66EN  
(pin 49B) of the PCI connector.  
For designs without secondary PCI slot:  
•
When there is at least one legacy PCI device  
on the secondary PCI bus, tie this pin directly  
to GND.  
•
When there is at least one PCI-X device that  
supports maximum PCI-X of only 66 MHz on  
the secondary PCI bus, pull down to GND  
through a 10 KΩ series resistor.  
•
When all secondary PCI-X devices (and the  
bus loading) support PCI-X 133 MHz, leave  
this pin unconnected (except for decoupling  
capacitor).  
Refer to PCI-X Addendum to the PCI Local Bus  
Specification, Revision 1.0b, Table 6-1.  
S_PCIXCAP  
For designs with secondary PCI slot:  
•
When there is at least one on-board legacy  
PCI device on the secondary PCI bus, tie this  
pin directly to GND.  
•
Otherwise, connect this pin to PCIXCAP  
(pin B38) of the PCI connector (assuming that  
the bus loading supports up to PCI-X  
133 MHz)  
NOTES:  
1. The recommended value for pull-up resistors for PCI applications is 5.6 KΩ (note that the minimum value for PCI 3.3 V  
signaling RMIN = 2.42 KΩ, RTYP = 8.2 KΩ, as per the PCI Local Bus Specification, Revision 2.3, section 4.3.3).  
2. The recommended value for pull-up resistors for PCI-X applications is 8.2 KΩ. For PCI-X, the minimum pull-up resistor value  
is 5 KΩ, as per the PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0b, section 9.7.  
3. For plug-in card implementations, the pull-up must be on the motherboard.  
4. Connect PVIO and SVIO pull-up resistors to 5 V or 3.3 V power supply through an external resistor—25 Ω (5 V) or  
0 Ω (3.3 V), depending on the signaling level of the primary/secondary PCI bus. Refer to the power-sequencing guidelines in  
Section 8.2 on page 58.  
®
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Terminations  
Table 5.  
Pull-Up/Pull-Down Terminations (Sheet 9 of 9)  
Signal  
Pull-Up/Pull-Down or Termination (See Note 1)  
Comments  
•
•
When forced retirement of the 31154 internal  
request queues and data buffer is not desired  
in the application, this pin must be pulled up to  
3.3 V through an 8.2 KΩ resistor.  
When forced retirement of the 31154 internal  
request queues and data buffer is desired in  
the application, this pin must be connected to  
external logic (or using the GPIO of the 31154)  
that drives this pin low when masking new  
transactions is desired.  
•
As soon as NT_MASK# is asserted, it must  
not be de-asserted until the QE pin is  
asserted.  
•
•
NT_MASK# must not be reasserted until the  
QE pin is cleared.  
NT_MASK#  
Setting the New Transaction Mask bit to 1b in  
VCR0 has the same effect as asserting  
NT_MASK#.  
Connection depends on application. This is an  
output signal that indicates the state of the 31154  
internal request and data queues. When high, this  
signal indicates that the 31154 internal queues are  
completely empty.  
NOTE: The state of this output is valid only when  
the NT_MASK# pin is asserted.  
QE  
SCAN_EN  
TMODE[3:0]  
NOTES:  
For normal operation, tie low to GND.  
For normal operation, tie to 0000 or 0111.  
0 = Pull low to GND.  
1 = Pull high to 3.3 V through an external 8.2 KΩ  
resistor.  
1. The recommended value for pull-up resistors for PCI applications is 5.6 KΩ (note that the minimum value for PCI 3.3 V  
signaling RMIN = 2.42 KΩ, RTYP = 8.2 KΩ, as per the PCI Local Bus Specification, Revision 2.3, section 4.3.3).  
2. The recommended value for pull-up resistors for PCI-X applications is 8.2 KΩ. For PCI-X, the minimum pull-up resistor value  
is 5 KΩ, as per the PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0b, section 9.7.  
3. For plug-in card implementations, the pull-up must be on the motherboard.  
4. Connect PVIO and SVIO pull-up resistors to 5 V or 3.3 V power supply through an external resistor—25 Ω (5 V) or  
0 Ω (3.3 V), depending on the signaling level of the primary/secondary PCI bus. Refer to the power-sequencing guidelines in  
Section 8.2 on page 58.  
§ §  
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Terminations  
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PCI/PCI-X Interface  
PCI/PCI-X Interface  
5
®
This chapter provides guidelines for designing with the Intel 31154 133 MHz PCI Bridge  
PCI/PCI-X bus interface in your application.  
5.1  
PCI/PCI-X Voltage Levels  
®
The Intel 31154 133 MHz PCI Bridge supports the 5 V PCI signaling interface as well as 3.3 V.  
Table 6 is provided as a reference for the PCI/PCI-X signaling levels. A complete PCI-X  
Addendum to the PCI Local Bus Specification, Revision 1.0a can be found on the www.pcisig.com  
website.  
Table 6.  
PCI/PCI-X Voltage Levels  
Symbol  
Parameter  
Minimum  
Maximum  
Units  
VIL3  
VIH3  
VIL4  
Input low voltage (PCI-X)  
Input high voltage (PCI-X/PCI)  
Input low voltage (PCI)  
-0.5  
0.5 × VCC33  
-0.5  
0.35 × VCC33  
VCC33 + 0.5  
0.3 × VCC33  
0.1 × VCC33  
V
V
V
V
V
VOL3  
VOH3  
Output low voltage (PCI-X)  
Output high voltage (PCI-X)  
0.9 × VCC33  
5.2  
Interrupt Routing  
The 31154 does not use PCI INT lines (INTA, INTB, INTC and INTD). These pins are usually  
routed from the primary to secondary PCI buses, bypassing the bridge.  
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PCI/PCI-X Interface  
5.3  
IDSEL Lines  
The IDSEL lines act as chip selects during the configuration cycles. Configuration cycles allow  
read and write access to one of the device configuration space registers. As in PCI, the IDSEL lines  
can be mapped to upper address lines, which are unused during the configuration cycles.  
5.3.1  
Primary IDSEL Line  
Figure 5 provides an example of the 31154 used as an embedded controller connected to four PCI  
devices. Note that AD16 is typically reserved for a PCI/PCI-X bridge.  
• When the 31154 is used as the primary interface to a plug-in card, the primary IDSEL line  
must be routed from the PCI connector to the P_IDSEL pin.  
• When the 31154 is used in an embedded application, PCI AD16 is used for source bridges.  
This line (AD16) must be connected to the P_IDSEL line through a 2 KΩ resistor.  
Figure 5.  
IDSEL Mapping  
Intel 31154  
I/O Processor  
Note:  
5.3.2  
Secondary IDSEL Lines  
The PCI specification recommends a specific resistor value of 2 KΩ ±5%. A smaller value may be  
used as long as system analysis ensures that timing and noise budgets for the AD bit are met.  
®
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PCI/PCI-X Interface  
5.3.3  
Secondary IDSEL Masking  
The 31154 supports private devices through the use of IDSEL masking. When the IDSEL_MASK  
pin is sampled as 1b on the trailing edge of P_RST#, the default value for the Secondary IDSEL  
®
Select Register (SISR) is 001Fh to mask devices 0–4 (refer to the Intel 31154 133 MHz PCI  
Bridge Developer’s Manual for more information).  
5.3.4  
Secondary Clock Control  
The 31154 can disable its secondary clock outputs individually or globally. The straps  
S_CLKOEN[3:0] determine the number of S_CLKO[8:0] outputs that are enabled. The  
S_BRCLKO output is dedicated for the bridge feedback clock and cannot be individually disabled.  
When the global clock output enable S_GCLKOEN is sampled as 0b, all secondary clock outputs  
are disabled, and an external clock source is required. The 31154 Bridge still drives the PCI-X  
initialization pattern, so any external clock source must be consistent with the clock generation  
scheme of the bridge, as defined in Table 9, “Secondary Bus Frequency Initialization” on page 33.  
5.4  
CompactPCI* Hot Swap Mode Select  
Hot Swap Mode Select (HS_SM) must be asserted (1b) to enable hot-swap functionality.  
HS_FREQ[1:0] pins allow the bridge to determine the cPCI backplane operating frequency on its  
primary interface without needing to see a PCI-X initialization pattern. These pins are valid only  
when HS_SM is sampled as 1b during P_RST#.  
Table 7.  
HS_FREQ Encoding  
HS_FREQ[1:0]  
P_M66EN  
Operating Mode  
Bus Frequency  
00  
00  
01  
10  
11  
0
1
–
–
–
PCI  
PCI  
33 MHz  
66 MHz  
66 MHz  
100 MHz  
133 MHz  
PCI-X  
PCI-X  
PCI-X  
5.5  
Opaque Memory Region Enable  
The 31154 supports an opaque memory region to enable private memory space for secondary  
devices. When OPAQUE_EN is sampled as 1b at the trailing edge of P_RST#, the Opaque  
Memory Enable bit in the “VCR2 Bridge Control Register 2” is set. The default base and limit  
reserve the upper half of memory (AD[63] = 1) for the private memory region.  
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PCI/PCI-X Interface  
5.6  
PCI-X Initialization Clocking Modes  
Both of the PCI bus interfaces can operate at a variety of frequencies, and in either conventional  
PCI mode, or in PCI-X mode. Each interface establishes the bus mode and frequency when coming  
out of its corresponding bus segment reset sequence. The resultant mode and frequency is  
dependent upon the device capabilities reported, in addition to any system-specific loading  
information.  
5.6.1  
5.6.2  
Primary PCI Clocking Mode  
The 31154 reports its primary bus operating capabilities to the originating device (typically the host  
bridge) of the primary bus segments. The 31154 indicates to the originating device of the primary  
bus segments that its primary interface is PCI-X–capable at frequencies of up to 133 MHz. It also  
indicates that the 31154 is capable of running at 66 MHz when operating in conventional PCI  
mode.  
Secondary PCI Clocking Mode  
The 31154 is the originating device for its secondary bus, and as such sets the bus mode and  
frequency when exiting out of the secondary bus reset sequence. The two key components that  
factor into the resultant secondary bus mode and frequency are the PCI-X standard sampling of  
downstream device capabilities, and the system-specific physical bus loading characteristics for  
which the PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0b does not provide  
any standard means of reporting.  
Downstream device capabilities are indicated by the values of S_M66EN and S_PCIXCAP during  
S_RST# assertion. Knowledge of the device capabilities alone is insufficient information to  
robustly select the bus frequency. In order to know with certainty at what frequency to set the bus,  
knowledge of the bus layout (for example, the number of slots) is also necessary. The 31154  
provides the S_MAX100 strapping pin for reporting system-specific secondary bus loading  
information that is used in determining the maximum operating frequency of the secondary bus.  
The 31154 considers S_MAX100 along with S_PCIXCAP and S_M66EN# to determine the  
secondary bus mode and frequency when emerging from S_RST#. For example, when a card is  
plugged into a two-slot secondary bus, the S_MAX100 strapping of 1b ensures that the bus runs at  
no greater than 100 MHz, regardless of the reported downstream device capabilities.  
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PCI/PCI-X Interface  
Table 8.  
PCI-X Clocking Modes  
PCIXCAP (pin on  
PCI connector)  
PCI-X Mode  
PCI Mode  
P_M66EN  
Not capable  
Not capable  
33 MHz  
66 MHz  
33 MHz  
66 MHz  
33 MHz  
66 MHz  
GND  
GND  
GND  
Not connected  
GND  
PCI-X/66 MHz  
PCI-X/66 MHz  
PCI-X/133 MHz  
PCI-X/133 MHz  
Pull down  
Pull down  
Not connected  
Not connected  
Not connected  
Ground  
Not connected  
Table 9.  
Secondary Bus Frequency Initialization  
Conventional PCI  
Frequency  
Typical Slot  
S_M66EN  
S_PCIXCAP  
S_MAX100  
PCI-X Frequency  
Loading1  
Ground  
Ground  
Ground  
–
–
33 MHz  
66 MHz  
Not capable  
Not capable  
Not connected  
Typical setting for  
four slots  
Ground  
Pull-down  
–
33 MHz  
PCI-X 66 MHz  
Not connected  
Ground  
Pull-down  
–
1
66 MHz  
33 MHz  
PCI-X 66 MHz  
PCI-X 100 MHz  
Not connected  
Typical setting for  
two slots  
Not Connected  
Ground  
Not Connected  
Not Connected  
Not Connected  
1
0
0
66 MHz  
33 MHz  
66 MHz  
PCI-X 100 MHz  
PCI-X 133 MHz  
PCI-X 133 MHz  
Typical setting for  
one slot  
Not Connected  
NOTE:  
1. Simulation is suggested for any deviation from typical slot loading recommendations.  
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PCI/PCI-X Interface  
Table 10 describes the bus mode and frequency initialization pattern that the 31154 signals on its  
secondary bus when coming out of S_RST#, after having evaluated the above information.  
Table 10.  
PCI-X Initialization Pattern  
Clock Period  
(Ns)  
Clock Frequency  
(MHz)  
DEVSEL#  
STOP#  
TRDY#  
Mode  
Max.  
Min.  
30  
Min.  
62.51  
33  
Max.  
33  
PCI 33  
PCI 66  
PCI-X  
PCI-X  
PCI-X  
PCI-X  
PCI-X  
PCI-X  
PCI-X  
62.51  
Deasserted Deasserted Deasserted  
30  
15  
66  
Deasserted Deasserted  
Asserted  
Deasserted  
Asserted  
20  
15  
50  
66  
Deasserted  
Deasserted  
Asserted  
Asserted  
Asserted  
Asserted  
NOTE:  
Asserted  
Asserted  
15  
10  
66  
100  
133  
10  
7.5  
100  
Deasserted Deasserted  
Deasserted  
Asserted  
Asserted  
Asserted  
Deasserted  
Asserted  
Reserved  
1. When the internal PLLs are operational, the minimum input frequency is 16 MHz. See Section 5.6.3,  
“Primary-to-Secondary Frequency Limits” on page 34 for more information.  
5.6.3  
Primary-to-Secondary Frequency Limits  
When operating in PCI 33 MHz mode, the bridge bypasses the PLL to allow the full range of  
0–33 MHz operations defined in the PCI specifications.  
However, the PLL is used to generate the secondary clock outputs when the secondary side is  
operating at a frequency greater than 33 MHz (PCI-66 MHz or PCI-X). The primary clock input  
must operate above 25 MHz to ensure that the secondary frequencies are within the ranges defined  
in the PCI specifications.  
When both the primary and secondary sides are operating in PCI-33 MHz mode, then the  
secondary clock equals the primary clock in frequency.  
An external clock source can be used on the secondary interface to remove any dependencies on  
the primary clock input.  
§ §  
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Routing Guidelines  
Routing Guidelines  
6
This chapter provides some basic routing guidelines for layout and design of a printed circuit board  
®
(PCB) using the Intel 31154 133 MHz PCI Bridge. The high-speed clocking required when  
designing with the 31154 requires special attention to signal integrity. In fact, it is highly  
recommended that the board design be simulated to determine optimum layout for signal integrity.  
The information in this chapter provides guidelines to aid the designer with board layout. Several  
factors influence the signal integrity of a 31154 design, including the following:  
• Power distribution  
• Decoupling  
• Minimizing crosstalk  
• Layout considerations when routing the PCI-X bus interfaces  
The order in which signals are routed varies from designer to designer. Some designers prefer to  
route all clock signals first, while others prefer to route all high-speed bus signals first. Either order  
can be used, provided the guidelines listed here are followed.  
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Routing Guidelines  
6.1  
Crosstalk  
Crosstalk is caused by capacitive and inductive coupling between signals. Crosstalk is composed of  
both backward and forward crosstalk components. Backward crosstalk creates an induced signal on  
a victim network that propagates in the opposite direction of the aggressor signal. Forward  
crosstalk creates a signal that propagates in the same direction as the aggressor signal.  
Circuit-board analysis software is used to analyze your board layout for crosstalk problems.  
Examples of 2D analysis tools include Ansoft* Parasitic Parameters* and Quad Design* XFS*.  
Crosstalk problems occur when circuit etch lines run in parallel. When board analysis software is  
not available, the layout must be designed to maintain at least the minimum recommended spacing  
for bus interfaces:  
• As a general guideline, the distance between adjacent signals must be a least 3.3 times the  
distance from signal trace to the nearest return plane. The coupled noise between adjacent  
traces decreases by the square of the distance between the adjacent traces.  
• It is also recommended that you specify the height of the above-referenced plane when laying  
out traces and that you provide this parameter to the PCB manufacturer. By moving traces  
closer to the nearest reference plane, the coupled noise decreases by the square of the distance  
to the reference plane.  
These design guidelines are illustrated in Figure 5:  
Figure 6.  
Crosstalk Effects on Trace Distance and Height  
Reduce Crosstalk:  
P
- Maximize P  
H
aggressor  
victim  
Reference Plane  
- Minimize H  
A9259-01  
Additional crosstalk guidelines include the following:  
• Avoid slots in the ground plane. Slots increase mutual inductance and thus increase crosstalk.  
• Ensure that the ground plane surrounding the connector-pin fields is not completely cleared  
out. When the area around the connector pins is completely cleared out, all the return current  
must flow together around the pin field, increasing crosstalk. The preferred method of laying  
out a connector in the GND layer is shown in Figure 7.  
®
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Routing Guidelines  
Figure 7.  
PCB Ground Layout Around Connectors  
Connector  
Connector Pins  
GND PCB Layer  
A. Incorrect method  
B. Correct method  
A9260-01  
6.2  
EMI Considerations  
It is highly recommended that you follow good EMI design practices when designing with the  
31154:  
• To minimize EMI on your PCB, a useful technique is not to extend the power planes to the  
edge of the board.  
• Another technique is to surround the perimeter of your PCB layers with a GND trace. This  
helps to shield the PCB with grounds, minimizing radiation.  
The AP-711 EMI Design Techniques Application Note discusses how to identify and prevent many  
common EMI problems at the design stage. Although the document addresses a range of solutions,  
emphasis is on printed circuit board design methods. This document is available at the following  
link:  
http://developer.intel.com/design/auto/mcs96/applnots/272673.htm  
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Routing Guidelines  
6.3  
Power Distribution and Decoupling  
Ensure that there is ample decoupling to ground for the power planes, to minimize the effects of the  
switching currents.  
Inadequate high-frequency decoupling results in intermittent and unreliable behavior.  
As a general guideline, it is recommended that you use the largest easily available capacitor in the  
lowest-inductance package. The high-speed decoupling capacitor must be placed as close to the pin  
as possible, with a short, wide trace.  
Three types of decoupling are described below:  
• Bulk capacitor: Bulk capacitors consist of electrolytic or tantalum capacitors. These  
capacitors supply large reservoirs of charge, but they are useful only at lower frequencies due  
to lead-inductance effects. Bulk capacitors can be located anywhere on the board.  
• High-frequency ceramic capacitor: For fast switching currents, high-frequency low-  
inductance capacitors are most effective. Place these capacitors as close to the device being  
decoupled as possible. This placement minimizes the parasitic resistance and inductance  
associated with board traces and vias.  
• Inter-plane capacitor: Use an inter-plane capacitor between power and ground planes to  
reduce the effective plane impedance at high frequencies. The general guideline for placing  
capacitors is to place high-frequency ceramic capacitors as close as possible to the module.  
6.3.1  
Decoupling Recommendations  
This section describes the recommended high-frequency and bulk decoupling for each of the 31154  
power supplies based on our simulations. The recommendations are listed in Table 11.  
®
Table 11.  
Intel 31154 133 MHz PCI Bridge Decoupling Recommendations  
Capacitor Value  
Capacitor  
Package  
Number of  
Capacitors  
Pins  
Voltage  
Notes  
(µF)  
VCC33  
3.3 V  
3.3 V  
22  
0.1  
150  
22  
1210  
603  
3
12  
1
2, 3, 4  
2, 3, 4  
2, 3, 4  
2, 3, 4  
2, 3, 4  
2, 3, 4  
2, 3, 4  
VCC33  
VCC33  
3.3 V  
7343  
1210  
603  
VCC  
1.3 V  
3
VCC  
1.3 V  
0.1  
22  
12  
1
P_VIO, S_VIO  
P_VIO, S_VIO  
3.3 V/5.0 V  
3.3 V/5.0 V  
1210  
603  
0.1  
4
Refer to  
Section 8.1 on  
page 57.  
P_VCCA,  
S_VCCA  
1.3 V  
–
–
1, 2, 3, 4  
NOTES:  
1. Separate capacitor required only when P_VIO and S_VIO are not connected to VCC33.  
2. Polymerized organic capacitors are recommended for bulk.  
3. X5R, X7R, or COG are recommended for ceramics.  
4. Place all capacitors as close as possible to associated pins to minimize inductance.  
®
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Routing Guidelines  
6.4  
Trace Impedance  
The PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0b, recommends that all  
signal layers have a controlled impedance of 57 Ω ±10% for add-in card applications. The  
characteristic impedance of a signal trace is 60–100 Ω for PCI add-in card applications.  
Selecting the appropriate board stack-up to minimize impedance variations is very important.  
When calculating flight times, it is important to consider the minimum and maximum trace  
impedance based on the switching neighboring traces. The PCI Local Bus Specification,  
Revision 2.3, recommends a trace velocity of 150 ps/in to 190 ps/in. Use wider spaces between  
traces, since this can minimize trace-to-trace coupling, and reduce crosstalk.  
When a different stack-up is used, the trace widths must be adjusted appropriately. When wider  
traces are used, the trace spacing must be adjusted accordingly (linearly).  
It is highly recommended that a 2D field solver be used to design the high-speed traces. An  
impedance calculator, available at http://emclab.umr.edu/pcbtlc, provides approximations for the  
trace impedance of various topologies. These approximations may be used to generate the starting  
point for a full 2D field solver.  
The following website provides a useful basic guideline for calculating trace parameters:  
http://www.ultracad.com/calc.htm  
Note: Using stripline transmission lines may give better results than microstrip. This is due to the  
difficulty of precisely controlling the dielectric constant of the solder mask, and the difficulty in  
limiting the plated thickness of microstrip conductors, which can substantially increase crosstalk.  
§ §  
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Routing Guidelines  
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PCI-X Layout Guidelines  
7
For acceptable signal integrity with bus speeds up to 133 MHz, it is important for the PCB design  
layout to have controlled impedance.  
The list below provides general guidelines for routing your PCI bus signals:  
• Avoid routing signal traces longer than 8".  
• All clock nets must be on the top layer.  
• All 32-bit interface signals from the PCI edge fingers must be no longer than 1.5" and no  
shorter than 0.75".  
• All 64-bit extension signals from the PCI edge fingers must be no longer than 2.75" and no  
shorter than 1.75".  
• P_CLK from the PCI edge finger must be 2.5" ± 0.1".  
• P_RST# from the PCI edge finger must be no longer than 3.0" and no shorter than 0.75".  
Table 12 provides information on maximum lengths for routing add-on card signals.  
Table 12.  
Add-in Card Routing Parameters  
PCI-X  
Parameter  
Minimum  
Length  
Maximum  
Length  
(inches)  
(inches)  
P_CLK  
2.40  
0.75  
1.75  
0.75  
2.60  
1.50  
2.75  
3.00  
P_AD[31:0]  
P_AD[63:32]  
P_RST#  
Note: Do not use more than one via for the primary PCI bus signals.  
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PCI-X Layout Guidelines  
7.1  
PCI Clock Layout Guidelines  
The PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0a, allows a maximum of  
0.5 ns clock skew timing for each of the PCI-X frequencies: 66 MHz, 100 MHz, and 133 MHz.  
• Total length of P_CLK for an add-in card is 2.4"–2.6"  
• Total length of P_CLK in non-add-in card design is less than 8".  
A typical PCI-X application requires separate clock point-to-point connections distributed to each  
PCI device. The 31154 clock buffer also provides secondary clock fanout of up to nine PCI-X  
devices. Figure 8, “PCI Clock Distribution and Matching Requirements” on page 43 shows the use  
of eight secondary clocks going to individual PCI-X devices with S_BRGCLKO fed back into  
S_CLKIN. The recommended clock buffer layout is specified as follows (refer to Figure 8):  
1. The distance between each series resistor and S_CLKO# output clock buffer must be less  
than 0.5".  
2. The segment length from secondary output clock buffer S_CLKO# to the end of the series  
resistor must be matched less than 0.1".  
3. You must match the end of series resistor to the device clock input to less than 0.1" to help  
keep the timing within the 0.5 ns maximum budget.  
4. You must match the length of S_BRGCLKO to the series resistor to less than 0.1" to all the  
other resistor secondary clock segment lengths listed in item 2, above.  
5. Match the length of the other end of the series resistor to S_CLKIN to all the other secondary  
clock segments lengths labelled in Figure 8 on page 43 as segment length “b”.  
6. Keep the distance between the clock lines and other signals (“d”) at least 25 mils from each  
other.  
7. When using a serpentine clock layout, keep the distance between different segments of the  
same clock line a minimum of 25 mils apart.  
8. When there are PCI devices and PCI slots in the design, an extra 2.5" trace length from  
connector to PCI device must be considered in calculating clock lengths going to PCI slots.  
9. When there are PCI slots in the design, S_BRGCLKO must be 3" longer to compensate for the  
2.5" trace length from connector to PCI device (and 0.5" for the connector skew) on a PCI  
add-in card.  
®
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PCI-X Layout Guidelines  
Figure 8.  
PCI Clock Distribution and Matching Requirements  
Device  
8
Intel 31154  
133 MHz PCI Bridge  
Device  
7
Device  
6
Device  
5
Device  
4
Device  
3
Device  
2
Device  
1
Notes:  
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PCI-X Layout Guidelines  
7.2  
PCI-X Topology Layout Guidelines  
The PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0a, recommends the  
following guidelines for the number of loads for your PCI-X designs (Table 13). Any deviation  
from these maximum values requires close attention to layout with regard to loading and trace  
lengths.  
Table 13.  
PCI-X Slot Guidelines  
Maximum  
Number of Slots  
Frequency  
Maximum Loads  
66 MHz  
100 MHz  
133 MHz  
8
4
2
4
2
1
The following PCI-X design layout considerations are compiled from the white paper Design,  
Modeling and Simulation Methodology for High Frequency PCI-X Subsystems, available on the  
http://www.pcisig.com website.  
The following results are compiled from the simulation of system models that included system  
board and add-in cards for different slot configurations and bus speeds (discussed in the white  
paper mentioned above). This simulation addressed signal-integrity issues including reflective  
noise, crosstalk noise, overshoot/undershoot voltage, ring-back voltage, settling time, inter-symbol  
interference, input reference voltage offset, and ground-bounce effects. These results for the slot  
configurations met the required PCI-X timing characteristics and were within appropriate noise  
margins.  
• 133 MHz Single-Slot—Included a single connection from the bridge to a single slot.  
• 133 MHz Embedded—Included a single connection from the bridge to one additional device  
on the system board. Note that this topology was interpolated from the above 133 MHz One-  
Slot (not based on actual simulation results).  
• 100 MHz Two-Slot Non-Hot-Plug, Balance Star—Included a single connection from the  
bridge to two slots without hot-plug devices. The connections to the bridge and to each slot  
came together such that each of the three branches is approximately the same length.  
• 100 MHz Embedded Non-Hot-Plug, Balance Star—Included a single connection from the  
bridge to three devices. The connections to the bridge and to each device came together such  
that each of the three branches was approximately the same length. Note that this topology was  
interpolated from the above 100 MHz Two-Slot (not based on actual simulation results).  
• 66 MHz Four-Slot Non-Hot-Plug—Included a single connection from the bridge to four hot-  
plug slots.  
• 66 MHz Embedded Non-Hot-Plug—Included a single connection from the bridge to four hot-  
plug slots. Note that this topology was interpolated from the above 66 MHz Four-Slot (not  
based on actual simulation results).  
®
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7.2.1  
Single Slot at 133 MHz  
Figure 9 shows one of the chipset PCI AD lines connected through the W1 and W12 line segments  
to a single-slot connector through the W13 line segment to the 31154. This AD line is also used as  
an IDSEL line from line segment W14 to a resistor through W15 to the PCI connector. The other  
end of the PCI connector IDSEL line connects through W16 to the 31154 IDSEL line input buffer.  
Figure 9.  
Single-Slot Point-to-Point Topology  
W1  
W12  
W13  
W16  
PCI Agent 1  
W14  
W15  
I/O Buffer  
Slot 1  
B3057-01  
Note: Stub lengths are represented by W#s.  
Table 14.  
Wiring Lengths for 133 MHz Slot  
Lower AD Bus  
Segment  
Upper AD Bus  
Units  
Minimum  
Length  
Maximum  
Minimum  
Length  
Maximum  
Length  
Length  
W1 + W12  
W13  
5.5  
0.75  
0.1  
10.5  
1.5  
4.5  
1.75  
–
9.5  
2.75  
–
inches  
inches  
inches  
inches  
inches  
W14  
0.1  
W15  
0.6  
0.6  
–
–
W16  
1.125  
1.125  
–
–
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®
7.2.1.1  
Intel 31154 133 MHz PCI Bridge Embedded Application at 133 MHz  
Figure 10 shows the 31154 application in a stand-alone embedded application. In this application  
the 31154 is shown driving a single PCI device. Table 15 shows the corresponding wiring lengths  
to use as a reference.  
®
Figure 10.  
Embedded Intel 31154 133 MHz PCI Bridge Design 133 MHz PCI-X Layout  
W2  
W4  
W1  
PCI  
Agent  
IDSEL  
I/O Buffer  
W3  
B3058-01  
Table 15.  
Wiring Lengths for Embedded 133 MHz Design  
Lower AD Bus  
Segment  
Upper AD Bus  
Units  
Minimum  
Length  
Maximum  
Length  
Minimum  
Maximum  
Length  
Length  
W1  
W2  
W3  
W4  
5.5  
0.75  
0.1  
10.5  
1.5  
4.5  
1.75  
–
9.5  
2.75  
–
inches  
inches  
inches  
inches  
0.1  
1.725  
1.725  
–
–
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7.2.2  
Dual-Slot at 100 MHz  
Figure 11 shows one of the secondary bridge PCI AD lines branching into two segments with each  
going through slot connectors to a buffer on an add-in card. Table 16 shows the corresponding  
wiring lengths to use as a reference. This two-slot design uses a balanced-star topology.  
Figure 11.  
Dual-Slot Configuration  
W1  
W11  
W12  
W13  
W16  
PCI Agent 1  
W14  
W15  
I/O Buffer  
Slot 1  
W21  
W22  
W23  
PCI Agent 2  
Slot 2  
B3059-01  
Table 16.  
Wiring Lengths for 100 MHz Dual-Slot  
Lower AD Bus  
Segment  
Upper AD Bus  
Units  
Minimum  
Length  
Maximum  
Length  
Minimum  
Length  
Maximum  
Length  
W1  
W21  
3.5  
2.0  
6
4.5  
0.5  
1.5  
0.1  
0.6  
1.125  
4.5  
0.5  
1.5  
3.5  
1.0  
6
inches  
inches  
inches  
inches  
inches  
inches  
inches  
inches  
inches  
inches  
3.5  
W11+W12  
W13  
0.5  
0.5  
0.5  
0.75  
0.1  
1.75  
N/A  
N/A  
N/A  
1.0  
2.75  
N/A  
N/A  
N/A  
3.5  
W14  
W15  
0.6  
W16  
1.125  
2.0  
W21  
W22  
0.5  
0.5  
0.5  
WW23  
0.75  
1.75  
2.75  
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®
7.2.2.1  
Embedded Intel 31154 133 MHz PCI Bridge Application at 100 MHz  
Figure 12 shows the PCI-X layout for a embedded 133 MHz design. In this application the 31154  
is driving three loads. Table 17 shows the corresponding wiring lengths to use as a reference.  
®
Figure 12.  
Embedded Intel 31154 133 MHz PCI Bridge Design 100 MHz PCI-X Layout  
W1  
W2  
W3  
PCI  
Agent 1  
I/O Buffer  
IDSEL  
W5  
W4  
W6  
W7  
PCI Agent 2  
PCI Agent 3  
B3062-02  
Table 17.  
Wiring Lengths for Embedded 100 MHz Design  
Lower AD Bus  
Segment  
Upper AD Bus  
Units  
Minimum Length Maximum Length Minimum Length Maximum Length  
W1  
W2  
W3  
W4  
W5  
W6  
W7  
3.5  
2.5  
6
5.0  
3.5  
1.5  
1.75  
–
6.0  
4.0  
2.75  
–
inches  
inches  
inches  
inches  
inches  
inches  
inches  
0.75  
0.1  
1.5  
0.1  
1.725  
3.25  
3.25  
1.725  
6.5  
–
–
3.25  
3.25  
6.75  
6.75  
6.5  
®
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7.2.3  
Quad-Slots at 66 MHz  
Figure 13 shows one of the bridge secondary AD lines branching to four segments with each  
segment connecting to a slot connector to a buffer on an add-in card. The first segment representing  
an upper address line branches to a series resistor to become the IDSEL line for slot 1. Table 18  
shows the corresponding wiring lengths to use as a reference.  
Figure 13.  
Quad-Slots 66 MHz Topology  
W1  
W13  
PCI Agent 1  
I/O Buffer  
W14  
W22  
W15  
W16  
W23  
Slot 1  
Slot 2  
Slot 3  
Slot 4  
PCI Agent 2  
W32  
W42  
W33  
W43  
PCI Agent 3  
PCI Agent 4  
B3060-01  
Table 18.  
Wiring Lengths for 66 MHz Quad-Slot (Sheet 1 of 2)  
Lower AD Bus  
Segment  
Upper AD Bus  
Units  
Minimum  
Length  
Maximum  
Length  
Minimum  
Maximum  
Length  
Length  
W1  
W13  
W14  
5
7
2.5  
1.75  
–
7
2.75  
–
inches  
inches  
inches  
0.75  
0.1  
1.5  
0.1  
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PCI-X Layout Guidelines  
Table 18.  
Wiring Lengths for 66 MHz Quad-Slot (Sheet 2 of 2)  
Lower AD Bus  
Upper AD Bus  
Segment  
Units  
Minimum  
Length  
Maximum  
Length  
Minimum  
Length  
Maximum  
Length  
W15  
W16  
W21  
W22  
W23  
W32  
W33  
W42  
W43  
0.6  
1.125  
0.8  
0.6  
1.125  
1.2  
–
–
inches  
inches  
inches  
inches  
inches  
inches  
inches  
inches  
inches  
–
–
0.8  
0.1  
1.75  
0.1  
1.75  
0.1  
1.75  
1.2  
0.5  
2.75  
0.5  
2.75  
0.5  
2.75  
0.1  
0.5  
0.75  
0.1  
1.5  
0.5  
0.75  
0.1  
1.5  
0.5  
0.75  
1.5  
®
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®
7.2.3.1  
Embedded Intel 31154 133 MHz PCI Bridge Application at 66 MHz  
Figure 14 shows an 31154 in a stand-alone embedded application. In this application the 31154 is  
shown driving four loads. Additional loads might be possible with careful simulation. Table 19  
shows the corresponding wiring lengths to use as a reference.  
®
Figure 14.  
Embedded Intel 31154 133 MHz PCI Bridge Wiring for 66 MHz  
W2  
W1  
PCI Agent 1  
IDSEL  
I/O Buffer  
W4  
W6  
W3  
W5  
PCI Agent 2  
W7  
W9  
W8  
PCI Agent 3  
PCI Agent 4  
W10  
B3247-01  
Table 19.  
Wiring Lengths for Embedded 66 MHz Design  
Lower AD Bus  
Segment  
Upper AD Bus  
Units  
Minimum Length Maximum Length Minimum Length Maximum Length  
W1  
W2  
W3  
W4  
W5  
W6  
W7  
W8  
W9  
W10  
5
0.75  
0.1  
1.725  
1
7
1.5  
0.1  
1.725  
1
5
1.75  
–
7
2.75  
–
inches  
inches  
inches  
inches  
inches  
inches  
inches  
inches  
inches  
inches  
–
–
1
1
0.75  
1
1.5  
1
1.75  
1
2.75  
1
0.75  
1
1.5  
1
1.75  
1
2.75  
1
0.75  
1.5  
1.75  
2.75  
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7.2.4  
PCI-X at 33 MHz  
The 31154 supports running in an eight-slot PICMG 1.2 style passive backplane environment at  
33 MHz. To verify this, simulations were run based on the trace impedance of 57 Ω ± 10%.  
7.2.4.1  
Embedded PCI-X Specification PICMG 1.2 Overview  
The Embedded PCI-X (ePCI-X) Specification PICMG 1.2 is a specification supported by the PCI  
Industrial Computer Manufacturers Group. ePCI-X system host boards (SHBs) are defined in two  
form factors: full-size and half-size. The full-size SHB length is identical to the ISA long board  
length. Half-size SHB form factor is based on the popular half-size ISA board.  
7.2.4.2  
PICMG 1.2 System Overview  
An ePCI-X system is composed of one ePCI-X system host board (SHB) and an ePCI-X  
backplane. The SHB provides arbitration, clock distribution, and reset functions for all expansion  
boards. The SHB is responsible for performing system initialization by managing the IDSEL signal  
of each local board. Physically, the SHB slot can be located at any slot in the backplane.  
Electrically, it must be at the end of each of primary PCI/PCI-X bus.  
®
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Figure 15 shows an example of this system with dual 64-bit buses with four expansion slots on  
each bus. The backplane example shows the SHB in an ISA chassis. The SHB slot is in the center  
of the board. Figure 16 shows the data bus segments for this eight-slot topology, and Table 20 lists  
the segment lengths for the wiring segments. Figure 17 shows the clock segment lengths and  
Table 21 lists the clock segments lengths.  
Figure 15.  
An Example of an ePCI-X System  
Option Bracket Front Plate  
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PCI-X Layout Guidelines  
Figure 16.  
PCI-X Data Bus PICMG 1.2 Style Backplane  
Intel® 31154 133 MHz  
PCI Bridge  
Slot1  
Slot2  
Slot3  
Slot4  
Slot5  
Slot6  
Slot7  
Slot8  
Device  
W1  
W2  
W3  
W4  
W5  
W6  
W7  
W8  
Card Stub  
Edge Connector  
W9  
W10  
W11  
W12  
W13  
W14  
W15  
Backplane  
B3331-01  
Table 20.  
Wiring Lengths for PICMG 1.2 Backplane  
AD Bus  
Segment  
Units  
Minimum Length Maximum Length  
W1  
W2  
0.75  
0.75  
0.75  
0.75  
0.75  
0.75  
0.75  
0.75  
1.2  
2.75  
2.75  
2.75  
2.75  
2.75  
2.75  
2.75  
2.75  
1.2  
inches  
inches  
inches  
inches  
inches  
inches  
inches  
inches  
inches  
inches  
inches  
inches  
inches  
inches  
inches  
W3  
W4  
W5  
W6  
W7  
W8  
W9  
W10  
W11  
W12  
W13  
W14  
W15  
0.8  
0.8  
0.8  
0.8  
0.8  
0.8  
0.8  
0.8  
0.8  
0.8  
0.8  
0.8  
®
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PCI-X Layout Guidelines  
Figure 17.  
PCI-X Clock PICMG 1.2 Style Backplane  
Slot1  
SlotN  
WN  
Intel® 31154 133 MHz  
PCI Bridge Clock Buffer  
Device  
S1  
39 Ohms  
Card Stub  
S2  
Edge Connector  
Backplane  
BN  
B3332-01  
Table 21.  
PCI-X Clock Wiring Lengths for PICMG Backplane  
Clock Point to Point  
Segment  
Units  
Minimum Length Maximum Length  
S1  
S2  
0
0.3  
inches  
inches  
inches  
inches  
0.75  
0.75  
6.5  
2.75  
2.75  
16.2  
WN  
BN  
§ §  
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Power Considerations  
Power Considerations  
8
8.1  
Analog Power Pins  
The analog voltage pins S_VCCA and P_VCCA require a low-pass filter. This is implemented by  
connecting the P_VCCA and S_VCCA pins to a 10 Ω series resistor and 0.01 µF and 4.7 µF (low-  
ESR) capacitors in parallel going to ground. The opposite end of the 10 Ω resistor is connected to  
the 1.3 V supply. This arrangement is shown in Figure 18 and Figure 19.  
When implementing these circuits, use the following filter circuit layout and component  
recommendations:  
1. Low-ESR, polymerized organic capacitors are recommended for 4.7 µF.  
2. The 0.01 µF capacitor must be a X5R, X7R, or COG.  
3. The capacitors must be placed as close as possible to associated pins to minimize inductance.  
4. The connections from the P_VCCA and S_VCCA must be kept as short as possible.  
Figure 18.  
P_VCCA Filter  
Figure 19.  
S_VCCA Filter  
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8.2  
Power Sequencing  
When either P_VIO or S_VIO is connected to a power supply other than VCCP, you must perform  
one of the following steps (listed in order from most favorably recommended to least favorably  
recommended):  
1. Ensure that the P_VIO or S_VIO power comes up before or simultaneously with VCCP, and  
ensure that the P_VIO or S_VIO power goes down after or simultaneously with VCCP  
.
2. Alternatively, when the recommendation in item 1 is not followed, install a Schottky diode, as  
shown in Figure 20, between VCCP and the VIO pin(s) (as appropriate). The diode must be  
sized appropriately for the power environment of the system.  
3. Alternatively, when the recommendations in item 1 and item 2 are not followed, connect a  
25 Ω current-limiting resistor in series with the P_VIO and S_VIO supply. P_VIO and S_VIO  
must never be at a voltage lower than VCCP except in the case of a 25 Ω current-limiting  
resistor in series with the P_VIO and S_VIO supply.  
Figure 20.  
PVIO Voltage Protection Diode  
VCP  
VIO  
Intel® 31154  
133 MHz PCI Bridge  
§ §  
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Customer Reference Board  
Customer Reference Board  
9
®
This chapter provides information on the customer reference board based on the Intel 31154  
®
133 MHz PCI Bridge—the Intel IQ31154 Customer Reference Board (CRB). Figure 21 shows  
the block diagram for this CRB. The schematics for this board are provided on the Intel  
1
Developer’s website (document number 278839) .  
®
Figure 21.  
Intel IQ31154 Customer Reference Board Block Diagram  
PCI Optional Bus  
Logic Analyzer Mictors Logic Analyzer Mictors  
Quick  
Switch  
Enable  
Quick Switches  
Quick Switches  
PCI Secondary Bus - 133 MHz  
Serial  
EEPROM  
Intel® 31154  
133 MHz PCI Bridge  
Clock  
Circuit  
Strapping  
Options  
PCI Primary Bus  
B3336-01  
1. The schematics are included in the download at http://downloadfinder.intel.com/scripts-  
df/license_agr.asp?url=/6810/eng/31154_eval.zip&sType=&ProductID=&PrdMap=  
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Customer Reference Board  
The IQ31154 CRB is implemented on eight layers. These layers are detailed in Table 22. This  
example is provided as a reference; each individual 31154 application may vary.  
Table 22.  
Customer Reference Board Stackup  
Layers  
Signal  
Top layer  
2nd layer  
3rd layer  
4th layer  
5th layer  
6th layer  
7th layer  
8th layer  
Signal layer—critical nets (clocks, S/P AD buses)  
Ground plane  
Signal layer  
Power plane—(split voltage plane 3.3 and 1.3 for I/O and core)  
Power plane—(also a split voltage plane 5 and 12 V)  
Signal—(some minor 25 mil wide power runs included)  
Ground plane  
Signal layer (critical nets)  
FR-4, 0.062 in. ± 0.008, 1.0 oz. copper power/GND; ½ oz. copper signal.  
§ §  
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Debug Connectors and Logic Analyzer Connectivity  
Debug Connectors and Logic Analyzer  
Connectivity  
10  
10.1  
Probing PCI-X Signals  
To ease the probing and debugging of the PCI-X signals, you are recommended to passively probe  
the PCI-X bus signals with a logic analyzer. This can be done by placing six AMP* Mictor-38  
connectors on the board or by probing the bus with an interposer card such as the  
FuturePlus* Systems* FS2007 that works with an Agilent Technologies* logic analyzer.  
For ease of debugging the pinout of the AMP* Mictor-38 connectors, the recommended pin-out  
matches the FuturePlus* Systems* configuration setup, which allows ease of viewing the PCI  
signals on an Agilent Technologies* logic analyzer. Refer to the following test equipment that is  
used for this analysis:  
• Two AMP* 2-767004-2 surface-mount connectors mounted on the target board and routed to  
the PCI-X local bus  
• Two Agilent Technologies* E5346A or E5351A high-density adapter cables from  
FuturePlus* Systems or Agilent Technologies  
• Four logic analyzer PODS  
• FS1104 software from FuturePlus* Systems  
Equivalent analyzers can be substituted. A FuturePlus* Systems* configuration file with the  
FS1104 product that matches the pinout is listed in Table 23 through Table 28.  
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Debug Connectors and Logic Analyzer Connectivity  
Table 23.  
Logic Analyzer Pod 1  
Mictor-38 #1 Pin Number Odd Pod Logic Analyzer Channel Number  
PCI-X Name  
6
CLKC/16  
CLK  
C/BE4  
C/BE5  
C/BE6  
C/BE7  
ACK64  
REQ64  
UNUSED  
PME  
8
15  
14  
13  
12  
11  
10  
9
10  
12  
14  
16  
18  
20  
22  
24  
26  
28  
30  
32  
34  
36  
38  
8
7
C/BEO  
M66EN  
C/BE1  
SERR  
PAR  
6
5
4
3
2
PERR  
LOCK  
STOP  
1
0
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Debug Connectors and Logic Analyzer Connectivity  
Table 24.  
Logic Analyzer Pod 2  
Mictor-38 #1 Pin Number Odd Pod Logic Analyzer Channel Number  
PCI-X Signal Name  
5
CLK/16  
FRAME  
DEVSEL  
TRDY  
7
15  
14  
13  
12  
11  
10  
9
9
11  
13  
15  
17  
19  
21  
23  
25  
27  
29  
31  
33  
35  
37  
C/BE2  
C/BE3  
IDSEL  
REQ  
GNT  
8
INTD  
7
INTC  
6
INTB  
5
INTA  
4
UNUSED  
UNUSED  
UNUSED  
UNUSED  
UNUSED  
3
2
1
0
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Debug Connectors and Logic Analyzer Connectivity  
Table 25.  
Logic Analyzer Pod 3  
Mictor-38 #2 Pin Number Odd Pod Logic Analyzer Channel Number  
PCI-X Signal Name  
6
CLK/16  
IRDY  
AD15  
AD14  
AD13  
AD12  
AD11  
AD10  
AD09  
AD08  
AD07  
AD06  
AD05  
AD04  
AD03  
AD02  
AD01  
AD00  
8
15  
14  
13  
12  
11  
10  
9
10  
12  
14  
16  
18  
20  
22  
24  
26  
28  
30  
32  
34  
36  
38  
8
7
6
5
4
3
2
1
0
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Debug Connectors and Logic Analyzer Connectivity  
Table 26.  
Logic Analyzer Pod 4  
Mictor-38 #2 Pin Number Odd Pod Logic Analyzer Channel Number  
PCI-X Signal Name  
5
CLK/16  
UNUSED  
AD31  
AD30  
AD29  
AD28  
AD27  
AD26  
AD25  
AD24  
AD23  
AD22  
AD21  
AD20  
AD19  
AD18  
AD17  
AD16  
7
15  
14  
13  
12  
11  
10  
9
9
11  
13  
15  
17  
19  
21  
23  
25  
27  
29  
31  
33  
35  
37  
8
7
6
5
4
3
2
1
0
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Debug Connectors and Logic Analyzer Connectivity  
Table 27.  
Logic Analyzer Pod 5  
Mictor-38 #3 Pin Number Odd Pod Logic Analyzer Channel Number  
PCI-X Signal Name  
6
CLK/16  
PAR64  
AD47  
AD46  
AD45  
AD44  
AD43  
AD42  
AD41  
AD40  
AD39  
AD38  
AD37  
AD36  
AD35  
AD34  
AD33  
AD32  
8
15  
14  
13  
12  
11  
10  
9
10  
12  
14  
16  
18  
20  
22  
24  
26  
28  
30  
32  
34  
36  
38  
8
7
6
5
4
3
2
1
0
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Debug Connectors and Logic Analyzer Connectivity  
Table 28.  
Logic Analyzer Pod 6  
Mictor-38 Pin Number Even Pod Logic Analyzer Channel Number  
PCI-X Signal Name  
5
CLK/16  
Unused  
AD63  
AD62  
AD60  
AD59  
AD58  
AD57  
AD56  
AD55  
AD54  
AD53  
AD52  
AD51  
AD50  
AD49  
AD48  
AD48  
7
15  
14  
13  
12  
11  
10  
9
9
11  
13  
15  
17  
19  
21  
23  
25  
27  
29  
31  
33  
35  
37  
8
7
6
5
4
3
2
1
0
The recommended placement of the Mictor connectors is at either end of the bus segment. The  
Mictors are placed at the end of a stub that must be as short as possible, and are then daisy-chained  
off either end of the bus. When there is not enough room to place the Mictors at least 0.5" from the  
target, an alternate method can be used. This alternate method is to place the logic analyzer  
termination circuitry on the target and then extend the etch from the end of the termination circuitry  
over to the Mictor connectors. The connection from the Mictors to the logic analyzer must then be  
made with the E5351A. The E5346A contains the logic analyzer termination circuitry, and the  
E5351A does not.  
§ §  
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Thermal Solutions  
Thermal Solutions  
11  
®
The Intel 31154 133 MHz PCI Bridge is packaged in a 421-lead PBGA package. The mechanical  
®
dimensions for this package are provided in Figure 2, “Intel 31154 133 MHz PCI Bridge  
Package” on page 14.  
Table 29 gives the operational power specifications.  
Table 29.  
Operational Power  
Voltage  
Maximum Power  
3.3 V  
1.3 V  
2.5 W  
0.7 W  
§ §  
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References  
References  
12  
12.1  
Related Documents  
®
Table 30 lists several books and specifications that are helpful for designing with the Intel 31154  
133 MHz PCI Bridge.  
Table 30.  
Design Reference Material  
Design Reference Material  
Brian C. Wadell, Transmission Line Design Handbook (Artech House, 1991)  
K. C. Gupta, et al., Microstrip Lines and Slotlines (Artech House, 1996)  
Moises Cases, Nam Pham, and Dan Neal, Design, Modeling and Simulation Methodology for High Frequency  
PCI-X Subsystems, (http://www.pcisig.com)  
PCI Local Bus Specification, Revision 2.3, (PCI Special Interest Group, 800-433-5177)  
Howard W. Johnson and Martin Graham, High-Speed Digital Design: A Handbook of Black Magic (Prentice  
Hall Professional Technical Reference, 1993)  
PCI Bus Power Management Interface Specification, Revision 1.1 (PCI Special Interest Group)  
Steve Kaufer and Kelee Crisafulli, “Terminating Differential Signals on PCBs” (Printed Circuit Design  
magazine, March 1999)  
®
®
Table 30 lists Intel documentation that is helpful for designing with the Intel 31154 133 MHz  
®
PCI Bridge. This documentation can be found at the Intel website at  
http://www.intel.com/design/bridge/docs/31154_documentation.htm.  
®
Table 31.  
Intel Related Documentation  
Document  
Document Title  
Number  
Intel® Packaging Databook (http://www.intel.com/design/packtech/packbook.htm)  
Intel® 31154 133 MHz PCI Bridge Evaluation Board Schematics  
Intel® 31154 133 MHz PCI Bridge Product Brief  
Intel® 31154 133 MHz PCI Bridge Datasheet  
Intel® 31154 133 MHz PCI Bridge Developer’s Manual  
240800  
278839  
252974  
278821  
278848  
§ §  
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References  
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