CMX158886 cpuModules™
User’s Manual
BDM-610000049 Revision G
®
www.rtd.com
An ISO9001:2000 Company
“Accessing the Analog World”
®
Download from Www.Somanuals.com. All Manuals Search And Download.
CMX158886 cpuModules™
®
www.rtd.com
An ISO9001:2000 Company
“Accessing the Analog World”
®
Download from Www.Somanuals.com. All Manuals Search And Download.
iv CMX158886 cpuModule
BDM-610000049 Rev G
Download from Www.Somanuals.com. All Manuals Search And Download.
Table of Contents
CMX158886 cpuModules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Error-Correction Codes (Selected Models Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CMX158886 Model Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5
Board Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7
Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Physical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Connector Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Connecting the Utility Cable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Connecting a Keyboard. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Connecting to the PC/104-Plus (PCI) Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Slot Selection Switches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Booting the CMX158886 cpuModule for the First Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Proper Grounding Techniques. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Connector Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Auxiliary Power (CN3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Utility Port Connector (CN5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
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SVGA Video Connector (CN18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
LVDS Flat Panel Video Connector (CN19) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
EIDE Connector (CN10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
ATA/IDE Disk Chip Socket (U16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Serial Port 1 (CN7) and Serial Port 2 (CN8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
multiPort™ (CN6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
multiPort Configured as an Advanced Digital I/O (aDIO™) Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
multiPort Configured as a Parallel Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
USB 2.0 Connector (CN17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Ethernet (10/100Base-T and -TX) Connector (CN20). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Audio (CN11). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
PC/104-Plus PCI Bus (CN16). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Error Reporting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bridge Link (CN4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
External Power Management (CN12). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Optional RTC Battery Input (CN13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Fan Power, +5 V (CN14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Fan Power, Switched (CN15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
The RTD Enhanced AMI BIOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
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Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
I/O Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
multiPort: Advanced Digital I/O Ports (aDIO™) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Port 1 Data register is a read/write byte direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Event Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Match Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Strobe Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Wake-on-aDIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
multiPort: Parallel Port Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
multiPort: Floppy Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
AC’97 Audio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Ethernet (10/100Base-T and -TX). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
IDE Controller Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Cable Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Host Determination of Cable Type. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device Detect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Real Time Clock Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Watchdog Timer Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Thermal Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Fan Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Further Temperature Reduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Advanced Configuration and Power Interface (ACPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Button Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multi-Color LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Reset Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
DVMT Mode Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
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User EEPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Features and Settings That Can Affect Boot Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Monitor Type. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Basic Interrupt Information for Programmers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Jumper Settings and Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Onboard PCI Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Physical Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Common Problems and Solutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Troubleshooting a PC/104-Plus System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
How to Obtain Technical Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
IDAN Dimensions and Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
External I/O Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
IDAN Dimensions and Connectors (BRG version only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
External I/O Connections (BRG version only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Drivers and Example Programs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Interrupt Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Serial Port Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
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PC/104 and PC/104-Plus Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
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Chapter 1
Introduction
This manual provides comprehensive hardware and software information for users developing with the
CMX158886 PC/104-Plus cpuModule.
This manual is organized as follows:
introduces main features and specifications
provides abbreviated instructions to get started quickly
provides information on connecting the cpuModule to peripherals
provides information to develop applications for the cpuModule, including general
cpuModule information, detailed information on storing both applications and system
functions, and using utility programs
lists jumper locations and settings, physical dimensions, and processor thermal
management
offers advice on debugging problems with your system
provides connector pinouts for the cpuModule installed in an RTD Intelligent Data
Acquisition Node (IDAN) frame
lists sources and websites to support the cpuModule installation and configuration
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CMX158886 cpuModules
RTD's CMX158886 cpuModule represents the latest in high-performance embedded computing solutions. It
includes 400 MHz source-synchronous Front Side Bus (FSB), on-die 2 MB (PX) or 512kB (CX) L2 cache, and data
pre-fetch logic. It uses a 333MHz DDR-SDRAM controller that can support up to 2.7 G-Bytes per second of
memory bandwidth. All memory chips are soldered directly onto the board. The Pentium-M (PX) processor
features Enhanced Intel SpeedStep® technology, which enables real-time dynamic switching between multiple
voltage and frequency points. This results in optimal performance without compromising low power.
The video interface is provided by an Analog SVGA output and an LVDS flat panel output. The two outputs are
independent, and can display separate images and display timings. Maximum resolution is 2048 x 1536.
High-speed peripheral connections include USB 2.0, with up to 480 Mb/sec data throughput. An ATA-100/66/33
IDE controller provides a fast connection to the hard drive. Network connectivity is provided by an integrated
10/100 Mbps Ethernet controller. Other features include two RS-232/422/485 COM ports, Parallel Port, and
AC97 audio.
RTD has gone the extra mile to include additional advanced features for maximum flexibility. These include an
ATA/IDE Disk Chip socket that allows a true IDE drive to be attached to the board, either socketed or soldered.
A MultiPort can be configured as a standard EPP/ECP parallel port, a floppy drive port, or an Advanced Digital
I/O (aDIO) port. The DDR-SDRAM controller on selected models uses Error-Correcting-Codes (ECC) to correct
single bit memory errors, and detect two-bit memory errors, providing for a more robust memory system.
SDRAM is soldered directly to the board for high vibration resistance. The CMX158886 is also available in a
rugged, fanless IDAN enclosure.
Cont. Fan
(CN14)
Power
Mngmt.
(CN12)
SVGA
Video
(CN18)
PCI Bus (CN16)
Audio
(CN11)
LVDS Flat
Panel
(CN19)
COM1
(CN7)
Switched
Fan
(CN15)
COM2
(CN8)
multiPort
(CN6)
USB 2.0
(CN17)
Ethernet
(CN20)
Multi-
Function
(CN5)
ATA/IDE
Disk Chip
(U16)
Battery
(CN13)
ISA Bridge Link
Auxiliary Power
(CN3)
(CN4)
EIDE (CN10)
Figure 1 CMX158886 cpuModule (top view)
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Enhanced Intel SpeedStep (PX only)
Enhanced Intel® SpeedStep® Technology has revolutionized thermal and power management by giving
application software greater control over the processor’s operating frequency and input voltage. Systems can
easily manage power consumption dynamically. Today’s embedded systems are demanding greater performance
at equivalent levels of power consumption. Legacy hardware support for backplanes, board sizes and thermal
solutions have forced design teams to place greater emphasis on power and thermal budgets. Intel has extended
architectural innovation for saving power by implementing new features such as Enhanced Intel SpeedStep
Technology. Enhanced Intel SpeedStep Technology allows the processor performance and power consumption
levels to be modified while a system is functioning. This is accomplished via application software, which changes
the processor speed and the processor core voltage while the system is operating. A variety of inputs such as
system power source, processor thermal state, or operating system policy are used to determine the proper
operating state.
The software model behind Enhanced Intel SpeedStep Technology has ultimate control over the frequency and
voltage transitions. This software model is a major step forward over previous implementations of Intel
SpeedStep technology. Legacy versions of Intel SpeedStep technology required hardware support through the
chipset. Enhanced Intel SpeedStep Technology has removed the chipset hardware requirement and only requires
the support of the voltage regulator, processor and operating system. Centralization of the control mechanism
and software interface to the processor, and reduced hardware overhead has reduced processor core
unavailability time to 10 μs from the previous generation unavailability of 250 μs.
Thermal Monitor
The Intel ® Thermal Monitor is a feature on the CMX158886 that automatically initiates a SpeedStep transition
or throttles the CPU when the CPU exceeds its thermal limit. The maximum temperature of the processor is
defined as the temperature that the Thermal Monitor is activated. The thermal limit and duty cycle of the
Thermal Monitor cannot be modified.
Error-Correction Codes (Selected Models Only)
The Graphics and Memory Controller Hub (GMCH) may be configured in the BIOS setup to operate in an
Error-Correction-Code (ECC) data integrity mode. ECC mode allows multiple bit error detection and single bit
error correction. The GMCH generate an 8-bit code word for each 64-bit Qword of memory, and performs a full
Qword write at a time so that an 8-bit code is sent with each write. Since the code word covers a full Qword,
writes of less than a Qword require a read-merge-write operation. Consider a Dword write to memory. In this
case, when in ECC mode, GMCH will read the Qword where the addressed Dword will be written, merge in the
new Dword, generate a code covering the new Qword and finally write the entire Qword and code back to
memory. Any correctable (single-bit) errors detected during the initial Qword read are corrected before merging
the new Dword.
Memory with ECC enabled requires additional system memory resources. This will cause the integrated graphics
engine to have less memory bandwidth for access to the graphics frame buffer. Because of this, the display may
flicker at high resolutions when the graphics processor is fully utilized and ECC is enabled. ECC memory is
supported with internal graphics only.
aDIO with Wake-on-aDIO
RTD’s exclusive multiPort™ allows the parallel port to be configured as an Advanced Digital I/O (aDIO™), ECP/
EPP parallel port, or a floppy drive. aDIO™ is 16 digital bits configured as 8 bit-direction programmable and 8-bit
port-direction programmable I/O giving you any combination of inputs and outputs. Match, event, and strobe
interrupt modes mean no more wasting valuable processor time polling digital inputs. Interrupts are generated
when the 8 bit-direction programmable digital inputs match a pattern or on any value change event. Bit masking
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allows selecting any subgroup of eight bits. The strobe input latches data into the bit-programmable port and
generates an interrupt. Any of the interrupt modes can be used to generate a wake event from any
standby/powerdown mode.
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Ordering Information
The CMX158886 cpuModule is available with a 1.4 GHz Pentium-M processor, or a 1.0 GHz Celeron-M processor
and 512 or 1024 MB of DDR SDRAM. The cpuModule can also be purchased as part of an Intelligent Data
Acquisition Node (IDAN™) building block, which consists of the cpuModule and a milled aluminum IDAN frame.
The IDAN building block can be used in just about any combination with other IDAN building blocks to create
a simple but rugged PC/104 stack. Refer to Appendix C, IDAN™ Dimensions and Pinout, for more information. The
CMX158886 cpuModule can also be purchased as part of a custom-built RTD HiDAN™ or HiDANplus High
Reliability Intelligent Data Acquisition Node. Contact RTD for more information on its high reliability
PC/PCI-104 systems.
CMX158886 Model Options
The basic cpuModule model options are shown below. Refer to the RTD website (www.rtd.com) for more
detailed ordering information.
Table 1 CMX158886 cpuModule Model Options
Part Number
Description
CMX158886PX1400HR-512
CMX158886PX1400HR-E512
CMX158886PX1400HR-1024
CMX158886CX1000HR-512
CMX158886CX1000HR-E512
CMX158886CX1000HR-1024
1.4 GHz Pentium-M, 512MB DDR-SDRAM cpuModule
1.4 GHz Pentium-M, 512MB DDR-SDRAM cpuModule with ECC
1.4 GHz Pentium-M, 1024MB DDR-SDRAM cpuModule
1.0 GHz Celeron-M, 512MB DDR-SDRAM cpuModule
1.0 GHz Celeron-M, 512MB DDR-SDRAM cpuModule with ECC
1.0 GHz Celeron-M, 1024MB DDR-SDRAM cpuModule
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Cable Kits and Accessories
For maximum flexibility, RTD does not provide cables with the cpuModule. You may wish to purchase the
CMX158886 cpuModule cable kit (P/N XK-CM65), which contains:
•
•
•
•
•
•
•
•
•
Multi-function utility harness (keyboard socket, battery, reset, speaker)
Two serial port cables (DIL-10 to DSUB-9)
Parallel port cable (DIL-26 to DSUB-25)
Two IDE cables
VGA monitor cable (DIL-10 to high density 15-pin DSUB)
Power cable (DIL-12 to wire leads)
Two USB cables (5-pin SIL to USB A)
Audio Cable (DIL-10 to three Mini-Jacks)
One Ethernet cable (DIL-10 to RJ-45)
A floppy drive cable kit (P/N XK-CM49) is also available for connecting to the multiPort. This cable kit comes
with:
•
•
3.5” HDD Floppy Drive with a multiPort interface board
Two floppy cables
For additional accessories, refer to the RTD website.
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Board Features
•
1.4 GHz Intel Pentium M with thermal throttling
–
–
400 MHz, source-synchronous Front Side Bus
Math coprocessor
•
Supports MMX and SSE2 instructions
Internal Cache
L1 - 32KB of instruction and 32KB data; L2 - 2 MB
1.0 GHz Intel Celeron M with thermal throttling
–
•
•
–
–
400 MHz, source-synchronous Front Side Bus
Math coprocessor
•
Supports MMX and SSE2 instructions
Internal Cache
L1 - 32KB of instruction and 32KB data; L2 - 512kB
512 or 1024 Mbytes BGA DDR SDRAM
–
•
•
•
–
–
Up to 333 MHz Data Rate
ECC corrects single-bit memory errors and detects 2-bit errors (selected models)
Stackable 120-pin PCI bus
–
–
4 Bus master add-on cards capable
3.3V or 5V PCI bus signaling
•
•
Advanced power management features including Enhanced Intel SpeedStep Technology (PX only)
Advanced Thermal Management
–
–
–
–
Auto Fan Control only runs fan when needed
SMBus Temperature Monitor for CPU and board temperature
Mini Fan Heatsink with Auto Fan control
Passive Structural Heatsink & Heatpipes in IDAN and HiDAN System Configurations
•
•
Advanced Programmable Interrupt Controller (APIC)
–
–
High resolution 100 MHz APIC timer
24 interrupt channels with APIC enabled (15 in legacy PIC mode)
Advanced Configuration and Power Interface (ACPI)
–
–
ACPI 1.0 Compliant
Supported power down modes: S1 (Power On Suspend), S3 (Suspend to RAM), S4 (Hibernate),
and S5 (Soft-Off)
–
–
CPU Clock Throttling and Clock Stop for C0 to C3 Support
Wake events include:
•
•
•
•
•
•
aDIO Interrupt
Wake-on-LAN
Real Time Clock
COM port Ring
Power Switch
etc.
•
Network Boot supported by Intel PXE
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•
•
•
•
•
•
Three (3) counter/timers (Intel 8254 compatible)
Seven (7) DMA channels (Intel 8237 compatible)
Y2K compliant Real-Time Clock (external battery required)
Nonvolatile storage of CMOS settings without battery
Watchdog timer
Complete PC-compatible Single Board Computer
I/O
•
AC97 Audio Support
–
–
–
Selectable Headphone or Line level output
Line level input
Microphone input
•
Fast Ethernet
–
–
–
Ethernet Controller
•
•
Intel 82562 Fast Ethernet PCI Controller
Integrated 3KByte Transmit and 3Kbyte Receive FIFOs
Physical Layer
•
•
100Base-Tx and 10Base-T
Full Duplex support
Easy to Use
•
•
•
Low Power Features
LED Status
Software configuration
•
855GME SVGA controller Onboard with 3D Acceleration
–
–
–
–
–
–
–
–
DirectX & OpenGL 3D Accelerator
Analog SVGA Output
LVDS Flat Panel output
Resolution up to 2048 x 1536 pixels with 32K colors
VGA, SVGA, XGA, SXGA, UXGA
Up to 16 million colors
64-bit AGP Hardware graphics-accelerator
1MB to 64MB of shared DDR high-performance memory
•
•
Software-configurable RS-232/422/485 serial ports
–
–
–
16550 compatible UARTs for high-speed
Termination resistors for RS-422/485
Each serial port connector can be configured as two limited serial ports, for a total of four serial
ports
multiPort function connector
–
Parallel port
•
SPP, PS/2 bi-directional, EPP & ECP
–
Advanced Digital I/O (aDIO)
8
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•
•
•
•
•
•
One 8-bit port programmable as input or output
Eight bit-programmable I/O with Advanced Digital Interrupt Modes
Event Mode Interrupt generates an interrupt when any input bit changes
Match Mode Interrupt generates an interrupt when input bits match a preset value
External Strobe Mode latches 8 data inputs and generates and interrupt
Two Strobes can be configured as readable inputs
–
–
Floppy controller interface
•
Interfaces with RTD's multiPort Floppy Drive and Cable Kit
ESD protection
•
•
Two USB 2.0 (Universal Serial Bus) Ports
–
–
–
Supports 480 Mb/s (high-speed), 12Mb/s (full-speed), and 1.5Mbs (low speed) peripherals
500 mA @ 5 Vdc provided per port
USB Boot capability
UltraDMA-100 / 66 / 33 Master Mode PCI EIDE Controller
–
–
–
–
Transfer rate up to 100MB/sec using UltraDMA
Increased reliability using UltraDMA-66 transfer protocols
Support ATAPI compliant devices including DVD drives
48-bit LBA support for hard drives up to 2.2 terabytes.
•
•
32 pin ATA/IDE Disk Chip Socket
–
–
–
Miniature ATA/IDE Flash Disk Chip
Capacities up to 4GB1
Natively supported by all major operating systems
Utility port
–
–
–
–
–
–
PC/AT compatible keyboard port
PS/2 Mouse Port
Speaker port (0.1W output)
Hardware Reset input
Battery input for Real Time Clock
Soft Power Button input
•
Power I/O
–
–
Access to PCI-104 Bus pins
Power ground, 12, 5 & 3.3 VDC
BIOS
•
•
•
•
RTD Enhanced AMI BIOS
User-configurable using built-in Setup program
Nonvolatile storage of CMOS settings without battery
Boot Devices
–
–
Standard Devices (floppy disk, hard disk, etc.)
ATA/IDE Disk Chip
1.
During the time of this manual’s publication, 4GB was the largest available ATA/IDE Disk Chip capacity
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–
–
–
USB Device
Network
Fail Safe Boot ROM
•
Surface-mount Flash chip that holds ROM-DOS™
•
Quick Boot mode
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Block Diagram
The next figure shows a simplified block diagram of the CMX158886 cpuModule.
855 G M E
N orthB ridge
D D R S D R A M
333 M H z
Intel P rocessor
S V G A /
LV D S Flat P anel
2 x U S B 2.0
E ID E
IC H -4
S outh B ridge
A C 97 A udio
10/100 Ethernet
P C I B us 32-bit, 33 M H z
LP C B us
R TD aD IO /
W atchdog
R TD E nhanced BIO S/
Failsafe B oot R O M
2 x R S -232/422/485
P arallel P ort
K eyboard/M ouse
Floppy D rive
S uper I/O
Figure 2 CMX158886 cpuModule Simplified Block Diagram
You can easily customize the cpuModule by stacking PCI-104 modules such as video controllers, modems, LAN
controllers, or analog and digital data acquisition modules. Stacking modules onto the cpuModule avoids
expensive installations of backplanes and card cages, and preserves the module's compactness.
The cpuModule uses the RTD Enhanced AMI BIOS. Drivers in the BIOS allow booting from floppy disk, hard disk,
ATA/IDE Disk Chip, or boot block flash, thus enabling the system to be used with traditional disk drives or
nonmechanical drives. Boot from USB devices and network are also supported.
The cpuModule and BIOS are also compatible with most real-time operating systems for PC compatible
computers, although these may require creation of custom drivers to use the aDIO and watchdog timer.
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Specifications
Physical Characteristics
•
•
Dimensions: 117mm L x 97mm W x 15mm H (4.6"L x 3.8"W x 0.6"H)
Weight: Approximately 0.19 Kg (0.40 lbs.)
Power Consumption
Exact power consumption depends on the actual application. Table 2 lists power consumption for typical
configurations and clock speeds.
Table 2 cpuModule Power Consumption
Module
Speed
RAM
Power, typ. Power, Max.
CMX158886PX
CMX158886CX
1.4 GHz
1.0 GHz
512 MB
512 MB
12.7 W
10.9 W
15.2 W
12.2 W
Operating Conditions
Table 3 Operating Conditions
Symbol Parameter
Test Condition
Min.
Max.
VCC5
5V Supply Voltage
4.75V
n/a1
n/a1
n/a1
4.75V
-
5.25V
n/a
VCC3
3.3V Supply Voltage
12V Supply Voltage
-12V Supply Voltage
VCC12
VCC-12
n/a
n/a
VCCSTBY 5V Standby Voltage2
5.25V
500mA
+85C
ICCSTBY
Ta
5V Standby Current2
Ambient Operating
Temperature
Standard
-40C
Ts
Storage Temperature
Humidity
-40C
0
+85C
90%
Rh
Non-Condensing
23 C
MTBF
Mean Time Before
Failure
110,000
hours
1. The 12V, -12V, and external +3.3V rails are not used by the cpuModule. Any requirements on
these signals are driven by other components in the system, such as an LVDS Flat Panel or PCI
device.
2. 5V Standby is used to power the board when the main supply is turned off (power down modes
S3-S5). It is not required for board operation.
Electrical Characteristics
The table below lists the Electrical Characteristics of the CMX158886. Operating outside of these parameters
may cause permanent damage to the cpuModule.
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Table 4 Electrical Characteristics
Symbol Parameter
Test Condition
Min.
Max.
PCI
VOH
VOL
VIH
VIL
Output Voltage High
IOH = –0.5 mA
2.9 V
0.0 V
1.8 V
-0.5 V
—
3.3 V
0.55 V
5.5 V
0.9
Output Voltage Low
Input Voltage High
Input Voltage Low
IOL = 6.0 mA
—
—
—
I3.3V
3.3V supplied to PCI
bus from power
2 A
connector (CN3)
Bridge Link (CN4)
VOH
VOL
VIH
VIL
Output Voltage High
Output Voltage Low
Input Voltage High
Input Voltage Low
IOH = –0.5 mA
2.4 V
0.0 V
2.0 V
-0.5 V
3.3 V
0.55 V
5.5 V
0.8 V
IOL = 6.0 mA
—
—
IDE & ATA/IDE Disk Chip Socket1
VOH
VOL
VIH
VIL
Output Voltage High
IOH = –6.0 mA
IOL = 6.0 mA
—
2.8 V
0.0 V
2.0 V
-0.5 V
3.3 V
0.51 V
5.5 V
0.8 V
Output Voltage Low
Input Voltage High
Input Voltage Low
—
USB Ports
Ioc
Overcurrent Limit
Total of both
ports on a
connector
1.0A
5.0A
LVDS Port
VOD
Differential Output
Voltage
250 mV
450 mV
Vos
Ivcc
Offset Voltage
1.125 V
—
1.375 V
2 A
Supply Current for
Panel Electronics
—
IBKLT
VOH
VOL
VIH
Supply Current for
Backlight
—
IOH = –1.0 mA
IOL = 1.0 mA
—
—
2.97 V
0
2 A
3.3 V
0.33 V
3.6 V
0.8 V
Output Voltage High
DDC_*, FP_ENABLK
Output Voltage Low
DDC_*, FP_ENABLK
Input Voltage High
DDC_*
2.0
VIL
Input Voltage Low
DDC_*
—
-0.3
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Table 4 Electrical Characteristics
Symbol Parameter
Test Condition
Min.
Max.
SVGA Port
VOH
VOL
Output Voltage High
HSYNC, VSYNC
IOH = –32.0 mA
3.8 V
0.0 V
2.4 V
0.0 V
2.0 V
-0.3 V
5.0 V
0.55 V
3.3 V
Output Voltage Low
HSYNC, VSYNC
IOL = 32.0 mA
VOH
VOL
Output Voltage High
DDC_*
IOH = –4.0 mA
Output Voltage Low
DDC_*
IOL = 8.0 mA
0.4 V
VIH
Input Voltage High
DDC_*
—
—
—
5.5 V
VIL
Input Voltage Low
DDC_*
0.8 V
IDDCvcc
Supply Current for
DDC Electronics
100 mA
Serial Ports - RS-232
VOH
VOL
VIH
VIL
Output Voltage High
Output Voltage Low
Input Voltage High
Input Voltage Low
RL = 3 k
RL = 3 k
—
5.0 V
-10.0 V
2.4 V
10.0 V
-5.0 V
25 V
—
-25 V
0.8 V
Serial Ports - RS-422/485
VOD1
VOD2
VOC
Differential Output
RL = 50 Ohm
RL = 27 Ohm
2.0 V
1.5 V
0.0 V
6.0 V
6.0 V
3.0 V
Differential Output
Common Mode
Output
RL = 27 or 50
Ohm
VTH
VI
Differential Input
Threshold
-7V < VCM < 7V
-0.3 V
-25 V
0.3 V
25 V
Absolute Max Input
Voltage
—
multiPort - all modes
VOH
VOL
VIH
VIL
Output Voltage High
Output Voltage Low
Input Voltage High2
Input Voltage Low2
IOH = –4.0 mA
2.4 V
0.0 V
2.0 V
-0.5 V
3.3 V
0.4 V
IOL = 8.0 mA
—
5.5 V
—
0.8 V
IADIOvcc Supply current
—
500 mA
Utility Port Connector (CN5)
VRTC
Input RTC Voltage3
—
—
2.0V
3.6 V
IUTILvcc
Utility Supply
Current
500 mA
External Power Management (CN12) - PME#
VIH
VIL
Input Voltage High
Input Voltage Low
—
—
2.0 V
5.5 V
0.8 V
-0.5 V
1. Applies to modes up to UltraDMA Mode 4 (ATA/66)
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2. Maximum DC undershoot below ground must be limited to either 0.5V or 10mA. During
transitions, the device pins may undershoot to -2.0V or overshoot to 7.0V, provided it is less
than 10ns, with the forcing current limited to 200 mA.
3. Only required to maintain date and time when power is completely removed from the system.
Not required for board operation.
Contact Information
RTD Embedded Technologies, Inc.
103 Innovation Blvd.
State College, PA 16803-0906
USA
Phone:
Fax:
+1-814-234-8087
+1-814-234-5218
E-mail:
Internet:
http://www.rtd.com
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Chapter 2
Getting Started
For many users, the factory configuration of the CMX158886 cpuModule can be used to get a PC/104 system
operational. You can get your system up and running quickly by following the simple steps described in this
chapter, which are:
1. Before connecting the cpuModule, the user must be properly grounded to prevent electrostatic
2. Connect power.
3. Connect the utility harness.
4. Connect a keyboard.
5. Default BIOS configuration.
6. Fail Safe Boot ROM.
7. Connect a VGA monitor to the SVGA connector.
Refer to the remainder of this chapter for details on each of these steps.
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Connector Locations
Figure 3 shows the connectors and the ATA/IDE Disk Chip socket of the CMX158886 cpuModule.
Cont. Fan
(CN14)
Power
Mngmt.
(CN12)
SVGA
Video
(CN18)
PCI Bus (CN16)
Audio
(CN11)
LVDS Flat
Panel
(CN19)
COM1
(CN7)
Switched
Fan
(CN15)
COM2
(CN8)
multiPort
(CN6)
USB 2.0
(CN17)
Ethernet
(CN20)
Multi-
Function
(CN5)
ATA/IDE
Disk Chip
(U16)
Battery
(CN13)
ISA Bridge Link
(CN4)
Auxiliary Power
(CN3)
EIDE (CN10)
Figure 3 CMX158886 Connector Locations
Note Pin 1 of each connector is indicated by a white silk-screened square on the top side of the board
and a square solder pad on the bottom side of the board. Pin 1 of the bus connectors match when
stacking PC104-Plus or PCI-104 modules.
18 CMX158886 cpuModule
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Table 5 CMX158886 Basic Connectors
Connector
Function
Size
CN3
Auxiliary Power
12-pin
4-pin
CN4
Bridge Link
CN5
Utility Port
10-pin
26-pin
10-pin
10-pin
44-pin
10-pin
3-pin
CN6
multiPort
CN7
Serial Port 1 (COM1)
Serial Port 2 (COM2)
EIDE Connector
CN8
CN10
CN11
CN12
CN13
CN14
CN15
CN16
CN17
CN18
CN19
CN20
U16
Audio Connector
External Power Management
RTC Battery Input (optional)
Fan Power (+5V)
Fan Power (switched)
PC/104-Plus (PCI) Bus
USB 2.0
2-pin
2-pin
2-pin
120-pin
10-pin
10-pin
30-pin
10-pin
32-pin
Video (SVGA)
Flat Panel Video (LVDS)
Ethernet
ATA/IDE Disk Chip Socket
WARNING If you connect power incorrectly, the module will almost certainly be damaged or destroyed.
Such damage is not covered by the RTD warranty! Please verify connections to the module before
applying power.
Power is normally supplied to the cpuModule through the PCI bus connectors (CN16). If you are placing the
cpuModule onto a PC/104-Plus or PCI-104 stack that has a power supply, you do not need to make additional
connections to supply power.
If you are using the cpuModule without a PCI-104 or PC/104-Plus stack or with a stack that does not include a
Some PCI-104 and PC/104-Plus expansion cards may require +3.3V supplied on the PC/104-Plus (PCI) connector
(CN16). To learn how to supply this voltage, refer to Auxiliary Power (CN3) on page 26 and Jumper Settings and
BDM-610000049 Rev G
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Connecting the Utility Cable
The multi-function connector (CN5) implements the following interfaces:
•
•
•
•
•
•
PC/AT compatible keyboard
PS/2 mouse port
Speaker port (0.1W output)
Hardware Reset input
Battery input for Real Time Clock
Soft Power Button input
To use these interfaces, you must connect to the utility port connector (CN5). The utility harness from the RTD
cable kit provides a small speaker, two connectors for the keyboard and mouse, a push-button for resetting the
PCI-104 system, a soft-power button, and a lithium battery to provide backup power for the real time clock.
Connecting a Keyboard
You may plug a PC/AT compatible keyboard directly into the PS/2 connector of the utility harness in the cable
kit.
Note Many keyboards are switchable between PC/XT and AT operating modes, with the mode usually
selected by a switch on the back or bottom of the keyboard. For correct operation with this cpuModule,
you must select AT mode.
Connecting to the PC/104-Plus (PCI) Bus
Other PC/104-Plus or PCI-104 expansion boards may be connected to the cpuModule’s PC/104-Plus (PCI) bus
connector. To connect expansion modules to the PC/104-Plus bus, follow the procedure below to ensure that
stacking of the modules does not damage connectors or electronics.
WARNING Do not force the module onto the stack! Wiggling the module or applying too much pressure
may damage it. If the module does not readily press into place, remove it, check for bent pins or
out-of-place keying pins, and try again.
1. Turn off power to the PC/104-Plus or PCI-104 system or stack.
2. Select and install stand-offs to properly position the cpuModule on the stack.
3. Touch a grounded metal part of the rack to discharge any buildup of static electricity.
4. Remove the cpuModule from its anti-static bag.
5. Check that keying pins in the bus connector are properly positioned.
6. Check the stacking order; if a PCI to ISA bridge card is used to connect any PC/104 modules, make sure
an XT bus card will not be placed between two AT bus cards or it will interrupt the AT bus signals.
7. Hold the cpuModule by its edges and orient it so the bus connector pins line up with the matching
connector on the stack.
8. Gently and evenly press the cpuModule onto the PC/104-Plus or PCI-104 stack.
There are three additional considerations to make when using the PCI bus:
•
Slot selection switches on add-in boards
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•
•
PCI bus expansion card power
PCI bus signaling levels
Slot Selection Switches
Unlike PC/104 cards, PC/104-Plus and PCI-104 expansion cards have a “slot” selection switch or jumpers. In total,
there are 4 PCI cards that can be stacked onto the cpuModule with switch positions 0 through 3. The distance
from the CPU determines these switch settings. The card closest to the CPU is said to be in slot 0, the next closest
slot 1 and so on to the final card as slot 3.
Note This requirement means that all PC/104-Plus and PCI-104 cards must be stacked either on the top
or the bottom of the CPU, not on both sides.
The “slot” setting method may vary from manufacturer to manufacturer, but the concept is the same. The CPU
is designed to provide the correct delay to the clock signals to compensate for the bus length. The correct switch
setting ensures the proper clock delay setting, interrupt assignment, and bus grant/request channel assignment.
Refer to the expansion board’s manual for the proper settings. Each expansion card must be in a different slot.
PCI Bus Expansion Card Power
+5 Volt DC
The +5 V power pins on the PC/104-Plus (PCI) bus are connected directly to the +5 V pins on the auxiliary power
connector, CN3 (pins 2 and 8).
+3.3 Volt DC
The +3.3V pins on the PCI bus can be configured to be supplied from the power connector (CN3) or the onboard
+3.3V power supply. The factory default configuration connects the +3.3 V pins on the PCI bus to the auxiliary
power connector (CN3). This is to ensure that the cpuModule’s onboard +3.3V supply will not supply power to
the PC/104-Plus connector while a PC/104-Plus or PCI-104 power supply is already powering the +3.3V pins.
For more information on configuring the +3.3V pins on the PCI bus, contact RTD Technical Support.
PCI Bus Signaling Levels
The PCI bus can operate at +3.3 V or +5 V signaling levels. The default PCI bus signaling level is +3.3 V. For more
information, contact RTD Technical Support.
WARNING You will have to ensure that all your expansion cards can operate together at a single
signaling level.
BDM-610000049 Rev G
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Booting the CMX158886 cpuModule for the First Time
You can now apply power to the cpuModule. You will see:
•
•
•
A greeting message from the VGA BIOS (if the VGA BIOS has a sign-on message)
The cpuModule BIOS version information
A message requesting you press Delete to enter the Setup program
If you don’t press Delete, the cpuModule will try to boot from the current settings. If you press Delete, the
cpuModule will enter Setup. Once you have configured the cpuModule using Setup, save your changes and
reboot.
Note You may miss the initial sign-on messages if your monitor takes a while to power on.
Note By default, cpuModules are shipped with Fail Safe Boot ROM enabled. When Fail Safe Boot ROM
is enabled, the system will boot to it exclusively.
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Proper Grounding Techniques
Before removing the CMX158886 from its static bag, proper grounding techniques must be used to prevent
electrostatic discharge (ESD) damage to the cpuModule. Common grounding procedures include an anti-static
mat on a workbench, which may connect to an anti-static wrist strap (also known as an ESD wrist strap) on the
wrist of the technician or engineer.
Connector Locations
Figure 4 shows the connectors and the ATA/IDE Disk Chip socket of the CMX158886 cpuModule.
Cont. Fan
(CN14)
Power
Mngmt.
(CN12)
SVGA
Video
(CN18)
PCI Bus (CN16)
Audio
(CN11)
LVDS Flat
Panel
(CN19)
COM1
(CN7)
Switched
Fan
(CN15)
COM2
(CN8)
multiPort
(CN6)
USB 2.0
(CN17)
Ethernet
(CN20)
Multi-
Function
(CN5)
ATA/IDE
Disk Chip
(U16)
Battery
(CN13)
ISA Bridge Link
(CN4)
Auxiliary Power
(CN3)
EIDE (CN10)
Figure 4 CMX158886 Connector Locations
Note Pin 1 of each connector is indicated by a white silk-screened square on the top side of the board
and a square solder pad on the bottom side of the board. Pin 1 of the bus connectors match when
stacking PC104-Plus or PCI-104 modules.
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Table 6 CMX158886 Basic Connectors
Connector
Function
Size
CN3
Auxiliary Power
12-pin
4-pin
CN4
Bridge Link
CN5
Utility Port
10-pin
26-pin
10-pin
10-pin
44-pin
10-pin
3-pin
CN6
multiPort
CN7
Serial Port 1 (COM1)
Serial Port 2 (COM2)
EIDE Connector
CN8
CN10
CN11
CN12
CN13
CN14
CN15
CN16
CN17
CN18
CN19
CN20
U16
Audio Connector
External Power Management
RTC Battery Input (optional)
Fan Power (+5V)
Fan Power (switched)
PC/104-Plus (PCI) Bus
USB 2.0
2-pin
2-pin
2-pin
120-pin
10-pin
10-pin
30-pin
10-pin
32-pin
Video (SVGA)
Flat Panel Video (LVDS)
Ethernet
ATA/IDE Disk Chip Socket
BDM-610000049 Rev G
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Auxiliary Power (CN3)
The Auxiliary Power connector (CN3) can be used to supply power to devices that are attached to the
cpuModule. These devices include hard drive, front-end boards for data acquisition systems, and other devices.
Power can also be conveyed to the module through the Auxiliary Power connector (CN3). The cpuModule only
requires +5 VDC and ground for operation; however, other modules in the system may require +3.3V, +12 VDC,
–12 VDC, and –5 VDC. In these instances, the corresponding pins on the Auxiliary Power Connector (CN3) may
be used to supply these voltages.
Note Although it is possible to power the cpuModule through the Auxiliary Power connector, the
preferred method is to power it through the bus connector from a power supply in the stack. The
cpuModule can have large current transients during operation, which make powering it through wires
difficult. Powering through the bus eliminates such problems as voltage drop and lead inductance.
If using the Auxiliary Power connector to power the system, care must be taken to ensure a good power
connections. The power and ground leads must be twisted together, or as close together as possible to reduce
lead inductance. A separate lead must be used for each of the power pins. Both 5V pins must be connected. The
gauge of wire must be selected taking into account the total power of the system. A good rule of thumb is to use
wire that can supply twice the power required by the system, and do not use less than 18 gauge wire. The length
of the wire must not exceed 3 ft. The power supply solution must be verified by measuring voltage at the
Auxiliary Power Connector and verifying that it does not drop below 4.75 V. The voltage at the connector should
be checked with an oscilloscope while the system is operational.
WARNING If you connect power incorrectly, the module will almost certainly be destroyed. Please verify
power connections to the module before applying power.
Table 7 Auxiliary Power Connector (CN3)1
Pin
Signal
Function
1
2
GND
+5 V
Ground
+5 Volts DC
+5V Standby (ATX)
+12 Volts DC
Reserved
3
+5V_STDBY
+12 V
4
5
Reserved
–12 V
6
–12 Volts DC
Ground
7
GND
8
+5 V
+5 Volts DC
Ground
9
GND
10
11
12
+3.3 V
PSON#
+3.3 V
See note below
Power Supply On (ATX)
See note below
1. For more information on the ATX style signals, +5V Standby and
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Note The +3.3 V pins (10 and 12) on the auxiliary power connector (CN3) are connected to the +3.3 V
pins on the PC/104-Plus bus by default. These pins are also configured to supply +3.3V to FP_VCC on the
LVDS Flat Panel Video connector (CN19).
Note For more information on configuring the +3.3V pins on the auxiliary power connector (CN3) the
PCI bus connector (CN16), or the LVDS FLat Panel Video connector (CN19), contact RTD Technical
Support.
Facing the connector pins, the pinout of the Auxiliary Power connector is:
11
9
7
5
3
1
PSON#
GND
GND
Reserved
+5V_STDBY
GND
+3.3 V
+3.3 V
+5 V
–12 V
+12 V
+5 V
12
10
8
6
4
2
BDM-610000049 Rev G
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Utility Port Connector (CN5)
The utility port connector implements the following functions:
•
•
•
•
•
•
PC/AT compatible keyboard port
PS/2 mouse port
Speaker port (0.1W output)
Hardware Reset input
Battery input for Real Time Clock
Soft Power Button input
Table 8 provides the pinout of the multi-function connector.
Table 8 Utility Port Connector (CN5)
Pin
Signal
SPKR+
Function
Speaker Output (open collector)
In/Out
1
2
out
out
in
PWR
RESET
PWRSW
KBD
+5 V
3
Manual Push-Button Reset
Soft Power Button
Keyboard Data
Keyboard Clock
Ground
4
in
5
in/out
out
—
6
KBC
7
GND
MSC
8
Mouse Clock
out
in
9
BAT
RTC Battery Input
Mouse Data
10
MSD
in/out
Facing the connector pins, the pinout is:
9
7
5
3
1
BAT
GND
KBD
RESET
SPKR+
MSD
MSC
KBC
PWRSW
PWR
10
8
6
4
2
Speaker
A speaker output is available on pins 1 and 2 of the multi-function connector. These outputs are controlled by a
transistor to supply 0.1 W of power to an external speaker. The external speaker should have 8 Ω impedance and
be connected between pins 1 and 2.
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Keyboard
A PS/2 compatible keyboard can be connected to the multi-function connector. Usually PC keyboards come
with a cable ending with a 5-pin male PS/2 connector. Table 9 lists the relationship between the multi-function
connector pins and a standard PS/2 keyboard connector.
Table 9 Keyboard Connector Pins (CN5)
Pin
Signal
Function
PS/2
5
6
7
2
KBD
KBC
Keyboard Data
Keyboard Clock
Ground
1
5
3
4
GND
PWR
Keyboard Power (+5 V)
To ensure correct operation, check that the keyboard is either an AT compatible keyboard or a switchable XT/AT
keyboard set to AT mode. Switchable keyboards are usually set by a switch on the back or bottom of the
keyboard.
Mouse
A PS/2 compatible mouse can be connected to the multi-function connector. Table 10 lists the relationship
between the multi-function connector pins and a standard PS/2 mouse connector.
Table 10 Mouse Connector Pins (CN5)
Pin
Signal
Function
PS/2
10
8
MSD
MSC
GND
PWR
Mouse Data
1
5
3
4
Mouse Clock
Ground
7
2
Keyboard Power (+5 V)
System Reset
Pin 3 of the multi-function connector allows connection of an external push-button to manually reset the
system. The push-button should be normally open, and connect to ground when pushed.
Soft Power Button
Pin 4 of the multi-function connector allows connection of an external push-button to send a soft power signal
to the system. The push-button should be normally open, and connect to ground when pushed. For more
information on the modes of the Soft Power Button, refer to the Power Management section in Chapter 4, Using
BDM-610000049 Rev G
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Battery
Pin 9 of the multi-function connector is the connection for an external backup battery. This battery is used by
the cpuModule when system power is removed in order to preserve the date and time in the real time clock.
Connecting a battery is only required to maintain time when power is completely removed from the cpuModule.
A battery is not required for board operation.
WARNING The optional RTC battery input connector (CN13) should be left unconnected if the
multi-function connector (CN5) has a battery connected to pin 9.
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SVGA Video Connector (CN18)
Table 11 provides the pinout of the video connector.
Table 11 SVGA Video Connector (CN18)
Pin
Signal
Function
In/Out
1
2
VSYNC
HSYNC
DDCSCL
RED
Vertical Sync
out
out
Horizontal Sync
3
Monitor Communications Clock
Red Analog Output
Monitor Communications Data
Green Analog Output
+5 V
out
4
out
5
DDCSDA
GREEN
PWR
bidirectional
out
6
7
out
8
BLUE
Blue Analog Output
Ground
out
9
GND
out
10
GND
Ground
out
Facing the connector pins of the SVGA Video connector (CN18), the pinout is:
9
7
5
3
1
GND
PWR
DDCSDA
DDCSCL
VSYNC
GND
BLUE
GREEN
RED
HSYNC
10
8
6
4
2
BDM-610000049 Rev G
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The following table lists the supported video resolutions.
Table 12 SVGA Video Resolutions
Resolution
Colors
Refresh Rates
640 x 480
720 x 480
16, 256, 64k, 16M 60, 70, 72, 75, 85, 100, 120 Hz
256, 64k, 16M
256, 64k, 16M
60 Hz
50 Hz
720 x 576
800 x 600
16, 256, 64k, 16M 60, 70, 72, 75, 85, 100, 120 Hz
960 x 540
256, 64k, 16M
256, 64k, 16M
256, 64k, 16M
256, 64k, 16M
256, 64k, 16M
256, 64k, 16M
256, 64k, 16M
256, 64k, 16M
256, 64k, 16M
256, 64k, 16M
256, 64k, 16M
256, 64k, 16M
256, 64k, 16M
256, 64k, 16M
256, 64k, 16M
60 Hz
1024 x 768
1152 x 864
1280 x 720
1280 x 768
1280 x 960
1280 x 1024
1400 x 1050
1600 x 900
1600 x 1200
1856 x 1392
1920 x 1080
1920 x 1200
1920 x 1440
2048 x 1536
60, 70, 75, 85, 100, 120 Hz
60, 70, 72, 75, 85, 100 Hz
60, 75, 85, 100 Hz
60, 75, 85 Hz
60, 75, 85 Hz
60, 70, 72, 75, 85, 100, 120 Hz
60, 75, 85 Hz
60, 75, 85, 100, 120 Hz
60, 65, 70, 72, 75, 85, 100, 120 Hz
60, 75 Hz
50, 60, 75, 85, 100 Hz
60, 75 Hz
60, 75, 85 Hz
60, 75 Hz
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LVDS Flat Panel Video Connector (CN19)
Table 13 provides the pinout of the Flat Panel Video connector (CN19). FP_VCC is configured for +3.3V by
default. Contact RTD to have FP_VCC configured for +5 V. FP_VBKLT can be either +5 V or +12 V, and can be
Table 13 Flat Panel Video Connector (CN19)
Pin
Signal
Function
In/Out
1
2
Y0P
Y0M
DDC_CLK1
LVDS Data 0+
LVDS Data 0-
out
out
3
Panel Detection Clock
Ground
out
4
GND
GND
out
5
Y1P
LVDS Data 1+
LVDS Data 1-
6
Y1M
out
7
DDC_DATA1
Panel Detection Data
Ground
in/out
GND
out
8
GND
9
Y2P
LVDS Data 2+
LVDS Data 2-
10
11
12
13
14
15
16
17
18
19
20
Y2M
out
GND
Ground
GND
GND
out
GND
Ground
YCP
LVDS Clock+
YCM
LVDS Clock-
out
Y3P
LVDS Data 3+
LVDS Data 3-
out
Y3M
out
GND
Ground
GND
out
FP_VCC2
FP_VBKLT
FP_ENABLK
Power for flat panel electronics
Power for flat panel backlight
Enable for Backlight Power
out
out
1. The DDC signals use a +3.3 V signal level, and are not +5 V tolerant.
2. When configured for +3.3 V, FP_VCC is sourced from the auxiliary power connector (CN3)
or PC/104-Plus connector (CN16).
Table 14 lists several LVDS panels that were tested with this cpuModule. When evaluating a panel to be used with
this cpuModule, review the specifications of the tested panels to assure compatability.
Table 14 Tested LVDS Panels
Manufacturer
Model Number
Resolution Color Depth
Optrex
Optrex
T-51756D121J-FW-A-AA
1024 x 768
18 bit
24 bit
T-51639D084JU-FW-A-AB 1024 x 768
BDM-610000049 Rev G
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EIDE Connector (CN10)
The EIDE connector is a 44-pin, 2 mm connector that can connect to a variety of EIDE or IDE devices. The
connector provides all signals and power needed to use a 2.5-inch form factor (laptop) hard drive. Also, the first
40 pins of the connector provide all of the signals needed to interface to a 3.5-inch or 5-inch form factor hard
drive, CD-ROM drive, or other EIDE device. The larger form factors use a 40-pin, 0.1 inch spacing connector, so
an adapter cable or adapter board is needed to connect to CN10.
Table 15 EIDE Connector (CN10)1
Pin
Signal
Pin
Signal
1
RESET#
2
GND
DD8
3
DD7
4
5
DD6
6
DD9
7
DD5
8
DD10
DD11
DD12
DD13
DD14
DD15
N/C
9
DD4
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
DD3
DD2
DD1
DD0
GND
DMARQ
GND
GND
GND
GND
GND
N/C
DIOW#:STOP
DIOR#:HDMARDY#:HSTROBE
IORDY:DDMARDY#:DSTROB
DMACK#
INTRQ
DA1
PDIAG
DA2
DA0
CS0#
CS1#
DASP#
+5 V (logic)
GND
GND
+5 V (motor)
N/C
1. Signals marked with (#) are active low.
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ATA/IDE Disk Chip Socket (U16)
The ATA/IDE Disk Chip socket is a 32-pin socket that supports +3.3V or +5V miniature ATA/IDE flash disk chips.
The socket allows a true IDE device to be attached to the board with either a socketed or soldered connection.
Such true IDE devices are supported by all major operating systems, and do not require special drivers.
WARNING The ATA/IDE Disk Chip socket does not support conventional SSD memory devices or
devices that install as a BIOS extension (such as the M-Systems DiskOnChip®). If such a device is installed,
the cpuModule and device will almost certainly be destroyed.
Table 16 ATA/IDE Disk Chip Socket (U16)1
Pin
Signal
Pin
Signal
1
2
RESET#
D7
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VDD2
D8
3
D6
D9
4
D5
D10
5
D4
D11
6
D3
D12
7
D2
D13
8
D1
D14
9
D0
D15
10
11
12
13
14
15
16
DMARQ/WP#
IORD#
INTRQ
A1
IOWR#
DMACK/CSEL
IOCS16#
PDIAG#
A2
A0
CS1FX#
GND
CS3FX#
DASP#
1. Signals marked with (#) are active low.
2. The hardware default configuration for VDD is +3.3 V, but this pin may also be configured as +5 V. For
more information, contact RTD Technical Support.
Installing and Configuring the ATA/IDE Disk Chip
To ensure proper installation and of the ATA/IDE Disk Chip, follow the following configuration steps. Note that
the first few steps must be performed before installing the Disk Chip.
1. Before installing the ATA/IDE Disk Chip in the Disk Chip Socket (U16), verify that cpuModule is
configured for the correct Disk Chip supply voltage. The hardware default configuration is +3.3V. To use
a +5 V Disk Chip with cpuModules, contact RTD Technical Support.
2. Next, apply power to the system, and press the delete key repeatedly to enter the BIOS setup screen.
Once in the BIOS, specify the following settings:
a. Enable the cpuModule’s secondary IDE channel.
b. Specify the IDE mode of the ATA/IDE Disk Chip. For more information on the supported IDE
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c. Save the settings in the BIOS setup
3. Remove power from the system.
WARNING The preceding steps should be performed before installing the Disk Chip in the ATA/IDE Disk
Chip Socket. These steps ensure that the system is properly configured for the correct device and supply
voltage, so neither the Disk Chip or cpuModule are damaged.
4. Insert the Disk Chip in the ATA/IDE Disk Chip Socket (U16) aligning pin 1 with the square solder pad
on the board.
5. Apply power to the system.
6. Re-enter the BIOS and set the boot order of the system accordingly.
ATA/IDE Disk Chip
Pin 1 indicated by arrow
ATA/IDE Disk Chip Socket (U16)
Pin 1 indicated by arrow
Figure 5 CMX158886 before and after ATA/IDE Disk Chip Installation
36 CMX158886 cpuModule
BDM-610000049 Rev G
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Serial Port 1 (CN7) and Serial Port 2 (CN8)
Serial Port 1 (COM1) is implemented on connector CN7, and Serial Port 2 is implemented on connector CN8.
The serial ports are normally configured as PC compatible full-duplex RS-232 ports, but you may use the BIOS
Setup program to reconfigure these ports as half-duplex RS-422 or full-duplex RS-422 or RS-485. If you
reconfigure the ports, you must also select the I/O address and corresponding interrupt using Setup. Table 17
provides the available I/O addresses and corresponding interrupts.
Table 17 Serial Port Settings
I/O Address (hex)
IRQ
03F8
02F8
03E8
02E8
IRQ4
IRQ3
IRQ4
IRQ3
Serial Port UART
The serial ports are implemented with a 16550-compatible UART (Universal Asynchronous
Receiver/Transmitter). This UART is capable of baud rates up to 115.2 kbaud in 16450 and 16550A compatible
mode, and includes a 16-byte FIFO. Refer to any standard PC-AT hardware reference for the register map of the
UART. For more information about programming UARTs, refer to Appendix D.
RS-232 Serial Port (Default)
The default serial port mode is full-duplex RS-232. With this mode enabled, the serial port connectors must be
connected to RS-232 compatible devices. Table 18 provides the serial port connector pinout and shows how to
connect to an external DB-25 or DB-9 compatible serial connector.
Table 18 Serial Port in RS-232 Mode
Pin
Signal
Function
In/Out
DB-25
DB-9
1
2
DCD
DSR
RXD
RTS
Data Carrier Detect
Data Set Ready
Receive Data
in
in
8
6
1
6
2
7
3
8
4
9
5
3
in
3
4
Request To Send
Transmit Data
Clear To Send
out
out
in
4
5
TXD
CTS
DTR
RI
2
6
5
7
Data Terminal Ready
Ring Indicate
out
in
20
22
7
8
9,10
GND
Signal Ground
—
BDM-610000049 Rev G
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Facing the serial port’s connector pins, the pinout is:
9
7
5
3
1
GND
DTR
TXD
RXD
DCD
GND
RI
CTS
RTS
DSR
10
8
6
4
2
RS-422 or RS-485 Serial Port
You may use Setup to configure the serial ports as RS-422 or RS-485. In this case, you must connect the serial
port to an RS-422 or RS-485 compatible device.
When using RS-422 or RS-485 mode, you can use the serial ports in either half-duplex (two-wire) or full-duplex
(four-wire) configurations. For half-duplex (2-wire) operation, you must connect RXD+ to TXD+, and connect
RXD– to TXD–.
Note The cpuModule has a 120 Ω termination resistor. Termination is usually necessary on all RS-422
receivers and at the ends of the RS-485 bus.
Note If required, the termination resistor can be enabled by closing jumper JP1 for Serial Port 1
(COM1),JP2 for Serial Port 2 (COM2), JP11 for Serial Port 3 (COM3), and JP13 for Serial Port 4 (COM4).
When using full-duplex (typically in RS-422 mode), connect the ports as shown in Table 19.
Table 19 Full-Duplex Connections
Port 1
Port 2
RXD+
TXD+
RXD–
TXD–
TXD+
RXD+
TXD–
RXD–
When using half-duplex in RS-485 mode, connect the ports as shown in Table 20.
Table 20 Half-Duplex RS-485 Mode
From
To
Port 1 TXD+
Port 1 TXD–
Port 1 TXD+
Port 1 RXD–
Port 1 RXD+
Port 1 RXD–
Port 2 RXD+
Port 2 TXD–
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RS-422 and RS-485 Mode Pinout
Table 21 provides the serial port connector pinout when RS-422 or RS-485 modes are enabled.
Table 21 Serial Port in RS-422/485 Mode
Pin
Signal
Function
In/Out
DB-9
1
2
—
—
Reserved
—
—
1
6
2
7
3
8
4
9
5
Reserved
3
RXD–
TXD+
TXD–
RXD+
—
Receive Data (–)
Transmit Data (+)
Transmit Data (–)
Receive Data (+)
Reseved
in
4
out
out
in
5
6
7
—
8
—
Reseved
—
9,10
GND
Signal Ground
out
Facing the serial port connector, the pinout is:
9
7
5
3
1
GND
Rsvd
TXD-
RXD-
Rsvd
GND
Rsvd
RXD+
TXD+
Rsvd
10
8
6
4
2
Note When using the serial port in RS-485 mode, the serial transmitters are enabled and disabled under
software control. The transmitters are enabled by manipulating the Request To Send (RTS*) signal of the
serial port controller. This signal is controlled by writing bit 1 of the Modem Control Register (MCR) as
follows:
•
•
If MCR bit 1 = 1, then RTS* = 0, and serial transmitters are disabled
If MCR bit 1 = 0, then RTS* = 1, and serial transmitters are enabled
Note For more information on the serial port registers, including the MCR, refer to the Serial Port
BDM-610000049 Rev G
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Dual Serial Port Modes
The serial port connectors can be configured as dual serial ports in the BIOS. The mapping between the
connectors and COM port numbers is shown in Table 22. The supported combinations of serial port modes are
listed in Table 23, which also includes a reference to the corresponding connector pinout. For the configurations
that have RS-422 or RS-485 on COM B, a jumper must be installed.
Table 22 Dual Serial Port Connections
Connector
COM A
COM B
CN7
CN8
COM 1
COM 2
COM 3
COM 4
Table 23 Dual Serial Port Modes
COM A
COM B
Pinout
JP12/JP14
Reference
RS-232
RS-422
RS-422
RS-232
RS-232
RS-422
Not Installed
Not Installed
CN7: JP12
CN8: JP14
RS-485
RS-485
RS-232
RS-485
Not Installed
CN7: JP12
CN8: JP14
Table 24 COM A (RS-232) and COM B(RS-232)
Pin
Signal
Function
In/Out
DB-9
1
2
DCD1
RXD2
RXD1
RTS1
TXD1
CTS1
TXD2
RI1
COM A- Data Carrier Detect
COM B- Receive Data
COM A - Receive Data
COM A - Request To Send
COM A - Transmit Data
COM A - Clear To Send
COM B - Transmit Data
COM A - Ring Indicate
Signal Ground
in
in
1
6
2
7
3
8
4
9
5
3
in
4
out
out
in
5
6
7
out
in
8
9,10
GND
—
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Table 25 COM A (RS-422/485) and COM B (RS-232)
Pin
Signal
Function
In/Out
DB-9
1
2
DCD1
RXD2
RXD1-
TXD1+
TXD1-
RXD1+
TXD2
RI1
COM A - Data Carrier Detect
COM B - Receive Data
COM A - Receive Data (–)
COM A - Transmit Data (+)
COM A - Transmit Data (–)
COM A - Receive Data (+)
COM B - Transmit Data
COM A - Ring Indicate
Signal Ground
in
in
1
6
2
7
3
8
4
9
5
3
in
4
out
out
in
5
6
7
out
in
8
9,10
GND
—
Table 26 COM A (RS-422/485) and COM B (RS-422/485)
Pin
Signal
Function
In/Out
DB-9
1
2
RXD2+
RXD2-
RXD1-
TXD1+
TXD1-
RXD1+
TXD2-
TXD2+
GND
COM B - Receive Data (+)
COM B - Receive Data (–)
COM A - Receive Data (–)
COM A - Transmit Data (+)
COM A - Transmit Data (–)
COM A - Receive Data (+)
COM B - Transmit Data (–)
COM B - Transmit Data (+)
Signal Ground
in
in
1
6
2
7
3
8
4
9
5
3
in
4
out
out
in
5
6
7
out
out
—
8
9,10
BDM-610000049 Rev G
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multiPort™ (CN6)
RTD’s exclusive multiPort can be configured as an Advanced Digital I/O (aDIO™), a parallel port, or a floppy drive.
multiPort Electrostatic Discharge (ESD) and Undershoot Protection
The multiPort interface provides electrostatic discharge (ESD) protection allowing the aDIO port, parallel port,
and floppy port circuits to be protected from electrically charged external objects that may come in contact with
the cpuModule.
The ESD protection minimizes susceptibility of the circuitry to ESD from human contact, and is rated to
withstand up to 2000V with the Human Body Model (HBM) standardized ESD test. The protected circuitry is
also rated to protect against up to 1000V with the Charged Device Model (CDM) standardized ESD test.
In addition to the ESD protection, the circuitry also provides -2V undershoot protection by ensuring that the
pins remain in the off state when such voltage levels are connected as inputs to the cpuModule.
For specific electrical characteristics, refer to Table 4 on page 13.
multiPort Configured as an Advanced Digital I/O (aDIO™) Port
The mulitPort connector (CN6) can be configured as an aDIO port. aDIO is 16 digital bits configured as 8-bit
programmable and 8-bit port programmable I/O, providing any combination of inputs and outputs. Match,
event, and strobe interrupt modes mean no more wasting valuable processor time polling digital inputs.
Interrupts are generated when the 8-bit programmable digital inputs match a pattern, or on any value change
event. Bit masking allows selecting any subgroup of 8 bits. The strobe input latches data into the bit
programmable port and generates an interrupt. Refer to multiPort: Advanced Digital I/O Ports (aDIO™) on page
62 for information on programming the multiPort.
Table 27 multiPort aDIO Pinout
CN6 Pin
Function
CN6 Pin
Function
1
strobe 0
P1-0
P1-1
P1-2
P1-3
P1-4
P1-5
P1-6
P1-7
P0-0
P0-1
P0-2
P0-3
2
P0-4
P0-5
3
4
5
6
P0-6
7
8
P0-7
9
10
12
14
16
18
20
22
24
26
strobe 1
GND
GND
GND
GND
GND
GND
GND
+5 V
11
13
15
17
19
21
23
25
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multiPort Configured as a Parallel Port
The parallel port is available on connector CN6. Make sure the multiPort in the BIOS Setup is configured to
parallel port. You can use the BIOS Setup to select the parallel port’s address and associated interrupt, and
choose between its operational modes (SPP, ECP, EPP 1.7, and EPP 1.9).
The pinout of the connector enables a ribbon cable to be connected directly to a DB-25 connector, thus
providing a standard PC compatible port.
Note For correct operation, keep the length of the cable connecting the cpuModule and parallel device
less than 3 meters (10 feet).
Table 28 lists the parallel port signals and explains how to connect it to a DB-25 connector to obtain a PC
compatible port.
Table 28 multiPort Connector (CN6) as a Parallel Port
CN6 Pin
Signal
Function
In/Out
DB-25
1
STB
AFD
PD0
ERR
Strobe Data
out
out
out
in
1
2
Autofeed
14
2
3
Printer Data 0 (LSB)
Printer Error
Parallel Data 1
Initialize Printer
Printer Data 2
Select Printer
Printer Data 3
Signal Ground
Printer Data 4
Signal Ground
Printer Data 5
Signal Ground
Printer Data 6
Signal Ground
Printer Data 7 (MSB)
Signal Ground
Acknowledge
Signal Ground
Busy
4
15
3
5
PD1
INIT
PD2
SLIN
PD3
GND
PD4
GND
PD5
GND
PD6
GND
PD7
GND
ACK
GND
BSY
out
out
out
out
out
—
6
16
4
7
8
17
5
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
18
6
out
—
19
7
out
—
20
8
out
—
21
9
out
—
22
10
23
11
24
12
25
13
—
in
—
in
GND
PE
Signal Ground
Paper End
—
in
GND
SLCT
—
Signal Ground
Ready To Receive
+5 V
—
in
—
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multiPort Configured as a Floppy Drive Controller
The multiPort (CN6) can be configured to be a floppy drive controller. This can be configured in the BIOS Setup
under Integrated Peripherals. For more information on configuring the multiPort in the BIOS Setup, refer to
Table 29 shows the pin assignments to connect a floppy drive to the multiPort.
Table 29 multiPort Connector Floppy Pinout (CN6)1
CN6 Pin
Function
DB-25
Floppy Drive Pin
1
DS0#
DR0
1
14
2
14
2
2
82
3
INDEX#
HDSEL#
TRK0#
DIR#
4
15
3
32
262
5
6
16
4
18
282
7
WRTPRT#
STEP#
RDATA#
GND
8
17
5
20
302
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
18
6
—
342
DSKCHG
GND
19
7
odd pins
—
—
GND
20
8
odd pins
10
MTR0#
GND
21
9
odd pins
—
—
GND
22
10
23
11
24
12
25
13
—
odd pins
12
DS1#
GND
odd pins
16
MTR1#
GND
odd pins
22
WDATA#
GND
odd pins
24
WGATE#
+5 V
—
1. Signals marked with (#) are active low.
2. These signals must be pulled to 5V with separate 470 Ohm resistors.
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USB 2.0 Connector (CN17)
Two USB 2.0 compliant connectors are available on connector CN17. Table 30 provides the pinout of the USB
connector.
Note For proper operation at USB 2.0 speeds, be sure to use a cable that is rated for USB 2.0, such as the
cable kit supplied by RTD.
Table 30 USB Connector (CN17)
Pin
Signal
Function
In/Out
1
2
VCC1
Supply +5 V to USB1
Supply +5 V to USB2
Bidirectional data line for USB1
Bidirectional data line for USB2
Bidirectional data line for USB1
Bidirectional data line for USB2
Ground
out
out
VCC2
3
DATA1–
DATA2–
DATA1+
DATA2+
GND
in/out
in/out
in/out
in/out
out
4
5
6
7
8
GND
Ground
out
9
GND
Ground
out
10
GND
Ground
out
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Facing the connector pins, the pinout of CN17 is:
9
7
5
3
1
GND
GND
DATA1+
DATA1–
VCC1
GND
GND
DATA2+
DATA2–
VCC2
10
8
6
4
2
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Ethernet (10/100Base-T and -TX) Connector (CN20)
The functionality of the Ethernet port is based on the Intel 82562 Fast Ethernet PCI controller. Table 31 provides
the pinout of the Ethernet connector.
Table 31 Ethernet Connector (CN20)
RJ-45 Pin 10-Pin DIL Pin Signal
Function
In/Out
3
6
1
2
RX+
RX–
TX+
TX–
CT
Receive+
in
in
Receive–
1
5
Transmit+
out
out
—
—
—
—
—
—
2
6
Transmit–
4
3
Termination connected to pin 4
Termination connected to pin 3
Termination connected to pin 8
Termination connected to pin 7
Ground
5
4
CT
7
7
CT
8
8
CT
—
—
9
AGND
AGND
10
Ground
9
7
5
3
1
AGND
CT
TX+
CT
RX+
AGND
CT
TX–
CT
RX–
10
8
6
4
2
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Audio (CN11)
A full featured AC97 compliant audio port is available on CN11. It provides a mono microphone input, stereo
line level input, and a stereo output that can be configured as line level or headphone level. The output is
configured in the BIOS setup utility. When used as a headphone output, it will drive 32 Ohm speaker at 50mW.
Table 32 Audio Connector (CN11)
10-Pin DIL Pin Signal
Function
In/Out
1
MIC_VREF
2.2V Supply to bias
out
microphones. 5mA max.
2
MIC_IN
Microphone input. 1V RMS or
0.1V RMS.
in
3
4
GND
Signal GND
GND
in
LINE_IN_LEFT
Line level input for left channel.
1V RMS nominal.
5
6
GND
Signal GND
GND
in
LINE_IN_RIGHT
Line level input for right channel.
1V RMS nominal.
7
8
GND
Signal GND
GND
out
OUTPUT_LEFT
Left channel output. Selectable
as line level (1V RMS) or
headphone.
9
GND
Signal GND
GND
out
10
OUTPUT_RIGHT Left channel output. Selectable
as line level (1V RMS) or
headphone.
9
7
5
3
1
GND
GND
GND
GND
MIC_VREF
OUTPUT_RIGHT
OUTPUT_LEFT
LINE_IN_RIGHT
LINE_IN_LEFT
MIC_IN
10
8
6
4
2
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PC/104-Plus PCI Bus (CN16)
Connector CN16 carries the signals of the PC/104-Plus PCI bus. These signals match definitions of the PCI Local
Table 33 PC/104-Plus Bus Signal Assignments1
Pin
A
B
C
D
1
GND
VIO
Reserved/+5V_STDBY2
AD02
+5 V
AD01
AD00
+5 V
2
3
AD05
C/BE0#
GND
GND
AD04
AD03
4
AD07
GND
AD06
5
AD09
AD08
GND
6
AD11
AD14
+3.3 V
SERR#
GND
VIO
AD10
M66EN
AD12
7
AD13
GND
8
C/BE1#
GND
AD15
+3.3 V
PAR
9
Reserved / PSON#2
+3.3 V
LOCK#
GND
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
PERR#
+3.3 V
TRDY#
GND
Reserved / PME#2
STOP#
+3.3 V
FRAME#
GND
GND
DEVSEL#
+3.3 V
C/BE2#
GND
IRDY#
+3.3 V
AD17
AD16
AD18
AD21
+3.3 V
IDSEL0
AD24
GND
+3.3 V
AD20
GND
AD19
AD23
AD22
+3.3 V
IDSEL2
IDSEL3
GND
GND
IDSEL1
VIO
C/BE3#
AD26
AD25
AD29
+5 V
+5 V
AD28
AD27
AD30
GND
AD31
REQ0#
GND
GND
REQ1#
+5 V
VIO
REQ2#
VIO
GNT0#
GND
GNT1#
+5V
GNT2#
GND
CLK0
CLK1
CLK2
+5 V
CLK3
GND
GND
INTD#
INTA#
REQ3#
+5 V
RST#
+12 V
–12V
INTB#
GNT3#
INTC#
GND
1. Signals marked with (#) are active low.
2. Optional signals for ATX power management
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PC/104-Plus PCI Bus Signals
The following are brief descriptions of the PC/104-Plus PCI bus signals.
Address and Data
AD[31:00] — Address and Data are multiplexed. A bus transaction consists of an address cycle followed by
one or more data cycles.
C/BE[3:0]# — Bus Command/Byte Enables are multiplexed. During the address cycle, the command is
defined. During the Data cycle, they define the byte enables.
PAR — Parity is even on AD[31:00] and C/BE[3:0]# and is required.
Interface Control Pins
FRAME# — Frame is driven by the current master to indicate the start of a transaction and will remain
active until the final data cycle.
TRDY# — Target Ready indicates the selected devices ability to complete the current data cycle of the
transaction. Both IRDY# and TRDY# must be asserted to terminate a data cycle.
IRDY# — Initiator Ready indicates the master's ability to complete the current data cycle of the transaction.
STOP# — Stop indicates the current selected device is requesting the master to stop the current
transaction.
DEVSEL# — Device Select is driven by the target device when its address is decoded.
IDSEL[3:0] — Initialization Device Select is used as a chip-select during configuration.
LOCK# — Lock indicates an operation that may require multiple transactions to complete.
Error Reporting
PERR# — Parity Error is for reporting data parity errors.
SERR# — System Error is for reporting address parity errors.
Arbitration (Bus Masters Only)
REQ[3:0]# — Request indicates to the arbitrator that this device desires use of the bus.
GNT[3:0]# — Grant indicates to the requesting device that access has been granted.
System
CLK — Clock provides timing for all transactions on the PCI bus.
RST# — Reset is used to bring PCI-specific registers to a known state.
Interrupts
INTA# — Interrupt A is used to request Interrupts.
INTB# — Interrupt B is used to request Interrupts only for multi-function devices.
INTC# — Interrupt C is used to request Interrupts only for multi-function devices.
INTD# — Interrupt D is used to request Interrupts only for multi-function devices.
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Power Supplies and VIO
+5 V — +5 V supply connected to the PC/104 bus and Auxiliary Power Connector (CN3) +5 V supplies. This
is the only power supply that is required for board operation.
+12 V — +12 V supply connected to the PC/104 bus and Auxiliary Power Connector (CN3) +12 V supplies.
–12 V — –12 V supply connected to the PC/104 bus and Auxiliary Power Connector (CN3) –12 V supplies.
+3.3 V — The +3.3 V pins on the PC/104-Plus (PCI) connector are connected to the Auxiliary Power
Connector (CN3) by default. To supply +3.3V via the onboard +3.3V power supply, contact RTD Technical
Support.
VIO — This signal is typically the I/O power to the bus drivers on a PCI bus card, or used by the clamp diodes
on a PCI bus card. This is always driven by the cpuModule. By default, the signaling level is set to +3.3 V. For
information on configuring VIO for +5 V, contact RTD Technical Support.
ATX Power Management Signals (optional)
If an ATX power supply is connected to the system, the following signals listed below may be used to wake the
system from low power modes. For more information on these signals, refer to the Power Management section
+5V_STDBY — Some low power modes require that +5 V standby power is applied to the cpuModule
during the wake event. This signal is an input to the CPU.
PME# — Power Management Event input
PSON# — This is an active low open-drain output used to turn the power supply on when the system is
exiting a low power state.
Note Use of these signals will require board customization. For more information, contact the RTD.
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Bridge Link (CN4)
The Bridge Link connector allows devices that requires Legacy/ISA interrupts to interface with the cpuModule.
When ISA devices are installed in the system (via a PCI to ISA bridge card), the Bridge Link connector provides
Legacy/ISA DMA request signals, as well as a serial interrupt signal which permits access to all available system
interrupts.
Multiple devices may utilize the serial interrupt signal, SERIRQ, which is decoded on the cpuModule. Only one
device may use the DMA request and grant signal pair.
Table 34 Bridge Link (CN4)
Pin
Signal
Function
1
2
3
4
GND
Ground
DMAREQ
SERIRQ
Legacy/ISA DMA Request
Serial Interrupt Request
Legacy/ISA DMA Grant
DMAGNT
Facing the connector pins, the pinout is:
3
1
SERIRQ
GND
DMAGNT
DMAREQ
4
2
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External Power Management (CN12)
An external power management connector (CN12) is available for external devices to wake the system from low
power states. Some low power modes require that +5 V standby power is applied to the cpuModule during the
wake event.
For more information on power management, including a description of the board’s supported wake options,
Table 35 External Power Management (CN12)
Pin
Signal
Function
1
2
2
+5V_STDBY
GND
+5 V standby Power
Ground
PME#
Power Management Event input
Optional RTC Battery Input (CN13)
The optional RTC battery input is the connection for an external backup battery. This battery is used by the
cpuModule when system power is removed in order to preserve the date and time in the real time clock.
Connecting a battery is only required to maintain time when power is completely removed from the cpuModule.
A battery is not required for board operation.
Table 36 Optional RTC Battery Input (CN13)
Pin
Signal
Function
1
2
BAT
RTC Battery Input
Ground
GND
WARNING This optional RTC battery connector (CN13) should be left unconnected if the utility port
connector (CN5) has a battery connected.
Fan Power, +5 V (CN14)
If a fan is required to cool the cpuModule, it can be wired to CN14, which provides a continuous connection to
+5 V and ground.
Table 37 Fan Power, +5 V (CN14)
Pin
Signal
Function
1
2
+5V
+5 Volts DC
Ground
GND
Note To utilize the thermal fan mode feature in the BIOS, the fan must be connected to CN15
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Fan Power, Switched (CN15)
The switched fan power connector (CN15) is an optional fan connector which allows the system to power the
fan only when the processor temperature reaches high temperatures.
Table 38 Fan Power, Switched (CN15)
Pin
Signal
Function
1
2
CPU_FAN_PWM
GND
+5 Volts DC, switched
Ground
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Chapter 4
Using the cpuModule
This chapter provides information for users who wish to develop their own applications programs for the
CMX158886 cpuModule.
This chapter includes information on the following topics:
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The RTD Enhanced AMI BIOS
The RTD Enhanced AMI BIOS is software that interfaces hardware-specific features of the cpuModule to an
operating system (OS). Physically, the BIOS software is stored in a Flash EPROM on the cpuModule. Functions of
the BIOS are divided into two parts.
The first part of the BIOS is known as POST (power-on self-test) software, and it is active from the time power is
applied until an OS boots (begins execution). POST software performs a series of hardware tests, sets up the
machine as defined in Setup, and begins the boot of the OS.
The second part of the BIOS is known as the CORE BIOS. It is the normal interface between cpuModule hardware
and the OS which is in control. It is active from the time the OS boots until the cpuModule is turned off. The
CORE BIOS provides the system with a series of software interrupts to control various hardware devices.
Configuring the RTD Enhanced AMI BIOS
The cpuModule Setup program allows you to customize the cpuModule's configuration. Selections made in
Setup are stored on the board and are read by the BIOS at power-on.
Entering the BIOS Setup
You can run Setup by rebooting the cpuModule and repeatedly pressing the Delete key. When you are finished
with Setup, save your changes and exit. The system will automatically reboot
Field Selection
To move between fields in Setup, use the keys listed below.
Table 39 Setup Keys
Key
Function
,
,
,
Æ Å È Ç
+, –, PgUp, PgDn
Enter
Move between fields
Selects next/previous values in fields
Go to the submenu for the field
To previous menu then to exit menu
Esc
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Main Menu Setup Fields
The following is a list of Main Menu Setup fields.
Table 40 Main Menu Setup Fields
Field
Active Keys
Selections
Main
Press Enter to select
Access system information such as BIOS version, EPLD
version, and CMOS time and date settings
Advanced
PCIPnP
Boot
Press Enter to select
Press Enter to select
Press Enter to select
Press Enter to select
Setup advanced cpuModule features
Set PnP and PCI options and control system resources
Set the system boot sequence
Security
Setup the supervisor and user access passwords or
enable boot sector virus protection
Power
Thermal
Exit
Press Enter to select
Press Enter to select
Press Enter to select
Control power management settings, including power
supply type, and system wake functions
Monitor the cpuModule temperature, or activate
thermal or fan modes.
Save or discard changes and exit the BIOS, or load the
default BIOS settings
Note Future BIOS versions may have slightly different setup menus and options.
Power On Self Test (POST) Codes
Each POST Code represents a series of events that take place in a system during the POST. If the POST fails during
a particular POST Code, the system will not boot as expected.
The BIOS uses I/O port 80h to store the active POST Code. A POST Code board is a tool that is used to display
the POST Codes on I/O port 80h. This is usually accomplished with two 7-segment LEDs. Such a board is useful
for debugging a system that is unable to boot.
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Booting to Boot Block Flash with Fail Safe Boot ROM
Note Boards are shipped with Fail Safe Boot ROM enabled. When Fail Safe Boot ROM is enabled, the
system will boot to it exclusively.
The Fail Safe Boot ROM is a minimal build of ROM-DOS™ located inside a surface-mounted Boot Block Flash
chip. Boot Block Flash is a write-protected flash device that contains the BIOS and extra room where the Fail Safe
Boot ROM is stored. Additionally, Fail Safe Boot ROM is an emergency interface accessible by an external
computer. The ROM DISK contains utilities for remote access to the system’s disk drives. Due to the size of the
flash chip, Fail Safe Boot ROM contains an abbreviated selection of the ROM-DOS™ utilities; however, the
complete ROM-DOS™ is contained on a CD shipped with the cpuModule.
The purpose of the Fail Safe Boot ROM is to make the cpuModule bootable upon receipt. The Fail Safe Boot
ROM can be used as an indicator of the module’s functionality when booting problems arise with another
operating system. This test can be accomplished by enabling the Fail Safe Boot ROM in the Boot section of the
BIOS Setup Utility. Enabling this option forces the cpuModule to boot to Fail Safe Boot ROM.
To boot to the Fail Safe Boot ROM, install jumper JP5, and apply power to the system.
Note If power is applied to the system while JP5 is installed, the multi-color LED will turn red.
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Memory Map
Table 41 shows how memory in the first megabyte is allocated in the system.
Table 41 First Megabyte Memory Map
Address (hex)
Description
C0000–FFFFFh ROM 256 KB BIOS in Flash EPROM, shadowed into DRAM during runtime.
C0000–EFFFFh
Run time user memory space. Usually, memory between C0000h and CFFFFh
is used for the BIOS of add-on VGA video cards.
A0000–BFFFFh
Normally used for video RAM as follows:
EGA/VGA
Monochrome
CGA
0A0000–0AFFFFh
0B0000–0B7FFFh
0B8000–0BFFFFh
00502–9FFFFh
00400–00501h
00000–003FFh
DOS reserved memory area
BIOS data area
Interrupt vector area
Memory beyond the first megabyte can be accessed in real mode by using EMS or a similar memory manager.
See your OS or programming language references for information on memory managers.
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I/O Address Map
As with all standard PC/104 boards, the I/O total I/O space is 64k in size. However, because early processors only
addressed 0 address lines (SA0–SA9), the first 1k is used for legacy I/O devices. Any ISA add-on modules you
install must therefore use I/O addresses in the range of 0–1023 (decimal) or 000–3FF (hex). The upper I/O
addresses are used for PCI I/O devices, and are automatically assigned by the BIOS or operating system at boot
time.
Note If you add any PC/104 modules or other peripherals to the system you must ensure they do not use
reserved addresses listed below, or malfunctions will occur. The exception to this is if the resource has been
released by the user.
Table 42 lists I/O addresses reserved for the CMX158886 cpuModule.
Table 42 I/O Addresses Reserved for the CMX158886 cpuModule
Address Range (hex)
Bytes
Device
000–00Fh
010–01Fh
020–021h
022–02Fh
040–043h
060–064h
070–071h
080–08Fh
0A0–0A1h
0C0–0DFh
0F0–0FFh
100–101h
1F0–1FFh
200–201h
238–23Bh
2E8–2EFh
2F8–2FFh
3E8–3EFh
3F0–3F7h
3F8–3FFh
450-454h
455h
16
16
2
DMA Controller
Reserved for CPU
Interrupt Controller 1
Reserved
13
4
Timer
5
Keyboard Interface
Real Time Clock Port
DMA Page Register
Interrupt Controller 2
DMA Controller 2
Math Coprocessor
Video Initialization
Hard Disk1
2
16
2
32
16
2
16
2
Reserved
Bus Mouse2
Serial Port3
Serial Port3
Serial Port3
Floppy Disk1
Serial Port3
aDIO4
4
8
8
8
8
8
4
1
Watchdog Timer5
456-45F
9
EPLD
1. If a floppy or IDE controller is not connected to the system, the I/O addresses listed will not be occupied.
2. If a PS/2 mouse is not connected to the system, the I/O addresses listed will not be occupied.
3. The I/O addresses for the serial port are selected in the BIOS Setup utility.
4. If aDIO is disabled, the I/O addresses listed will not be occupied.
5. If watchdog timer is disabled, the I/O addresses listed will not be occupied.
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Hardware Interrupts
Note If you add any expansion modules or other peripherals to the system, you must ensure they do not
use interrupts needed by the cpuModule, or malfunctions will occur.
The CMX158886 cpuModule supports the standard PC interrupts listed in Table 43. Interrupts not in use by
hardware on the cpuModule itself are listed as available. Similarly, if the operating system is using APIC, more
IRQs will be available.
Table 43 Hardware Interrupts Used on the CMX158886 cpuModule
Interrupt
Normal Use
0
1
Timer 0
Keyboard
2
Cascade of IRQ 8–15
COM2
3
4
COM1
5
Available
6
Floppy
7
Printer
8
Real Time Clock
Available, routed to IRQ 2
Available
9
10
11
12
141
151
Available
Bus Mouse
Primary IDE hard disk
ATA/IDE Disk Chip socket
1. IRQs 14 and 15 may be available if the IDE controller is
configured in Native Mode (refer to IDE Controller
Note The cpuModule has onboard PCI devices that will claim IRQ lines. In some instances, a PCI device
will claim an IRQ line that is required by a legacy device. To reserve an IRQ for a legacy device, refer to the
PnP/PCI Configuration Setup fields in the BIOS.
Note A device’s hardware interrupt will be available for use if the given device is not present in the system
and the device is disabled in Setup.
For external devices that require Legacy/ISA interrupts, a serial interrupt signal is available which permits access
to the CPU’s hardware interrupts. One pair of Legacy/ISA DMA request/grant signals are also available. For more
information on the serial interrupt signal, and the DMA request/grand pair, refer to Bridge Link (CN4) in
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multiPort: Advanced Digital I/O Ports (aDIO™)
Ensure that the BIOS setup has the multiPort set to aDIO mode. This board supports 16 bits of TTL/CMOS
compatible digital I/O (TTL signaling). These I/O lines are grouped into two ports, Port 0 and Port 1. Port 0 is bit
programmable; Port 1 is byte programmable. Port 0 supports RTD’s Advanced Digital Interrupt modes. The
three modes are strobe, match and event. Strobe mode generates an interrupt and latches Port 0 when the strobe
input transitions from low to high. Match mode generates an interrupt when an 8-bit pattern is received in
parallel that matches the match mask register. Event mode generates an interrupt when a change occurs on any
bit. In any mode, masking can be used to monitor selected lines.
When the CPU boots, all digital I/O lines are programmed as inputs, meaning that the digital I/O line’s initial
state is undetermined. If the digital I/O lines must power up to a known state, an external 10 kΩ resistor must
be added to pull the line high or low.
The 8-bit control read/write registers for the digital I/O lines are located from I/O address 450h to 454h. These
registers are written to zero upon power up. From 450h to 454h, the name of these registers are Port 0 data,
Port 1 data, Multi-Function, DIO-Control, and Wake Control register.
Note RTD provides drivers that support the aDIO interface on popular operating systems. RTD
recommends using these drivers instead of accessing the registers directly.
Digital I/O Register Set
Table 44 Port 0 Data I/O Address 450h
D7
D6
D5
D4
D3
D2
D1
D0
P0.7
P0.6
P0.5
P0.4
P0.3
P0.2
P0.1
P0.0
Port 0 Data register is a read/write bit direction programmable register. A particular bit can be set to input or
output. A read of an input bit returns the value of port 0. A read of an output bit returns the last value written
to Port 0. A write to an output bit sends that value to port 0.
Table 45 Port 1 Data I/O Address 451h
D7
D6
D5
D4
D3
D2
D1
D0
P1.7
P1.6
P1.5
P1.4
P1.3
P1.2
P1.1
P1.0
Port 1 Data register is a read/write byte direction programmable register. A read on this register when it is
programmed to input will read the value at the aDIO connector. A write on this register when it is programmed
as output will write the value to the aDIO connector. A read on this register when it is set to output will read the
last value sent to the aDIO connector.
Table 46 Multi-Function I/O Address 452h
D7
D6
D5
D4
D3
D2
D1
D0
The multi-function register is a read/write register whose contents are set by the DIO-Control register. See the
DIO-Control register description for a description of this register.
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Table 47 DIO-Control I/O Address 453h—Read Access
D7
D6
D5
D4
D3
D2
D1
D0
Strobe 1 Status
0 = no strobe
1 = strobe
Strobe 0 Status
0 = no strobe
1 = strobe
Multi-Function
Digital IRQ Mode
00 = Disabled
01 = strobe Mode
10 = event mode
11 = match mode
Register Select
00 = clear mode
Digital IRQ Status
Port 1 Direction
0 = input
1 = output
01 = port 0 direction
10 = mask register
11 = compare register
0 = no digital interrupt
1 = digital interrupt
Table 48 DIO-Control I/O Address 453h—Write Access
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
Multi-Function
Register Select
Digital IRQ Mode
00 = Disabled
00 = clear mode
01 = strobe Mode
10 = event mode
11 = match mode
Port 1 Direction
0 = input
1 = output
01 = port 0 direction
10 = mask register
11 = compare register
Table 49 Multi-Function at Address 452h1
read/write
00 clear
X
X
X
X
X
X
X
X
0 in, 1 out
01 Port 0 direction
10 DIO mask
I/O
M7
C7
I/O
M6
C6
I/O
M5
C5
I/O
M4
C4
I/O
M3
C3
I/O
M2
C2
I/O
M1
C1
I/O
M0
C0
0 no mask, 1 mask
read/write
11 compare
1. Contents based on bits D0 and D1 of DIO-Control.
Clear Register:
A read to this register Clears the IRQs and a write to this register sets the DIO-Compare, DIO- Mask,
DIO-Control, Port 1, and Port 0 to zeros. A write to this register is used to clear the board.
Port 0 Direction Register:
Writing a zero to a bit in this register makes the corresponding pin of the aDIO connector an input. Writing
a one to a bit in this register makes the corresponding pin of the aDIO connector an output.
Mask Register:
Writing a zero to a bit in this register will not mask off the corresponding bit in the DIO-Compare register.
Writing a one to a bit in this register masks off the corresponding bit in the DIO-Compare register. When all
bits are masked off the aDIOs comparator is disabled. This condition means Event and Match mode will not
generate an interrupt. This register is used by Event and Match modes.
Compare Register:
A Read/Write register used for Match Mode. Bit values in this register that are not masked off are compared
against the value on Port 0. A Match or Event causes bit 6 of DIO-Control to be set and if the aDIO is in
Advanced interrupt mode, the Match or Event causes an interrupt.
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Table 50 Wake Control I/O Address 451h
D7 D6 D5 D4 D3 D2
Reserved
D1
D0
Int Mask
Wake Enable
1 = Interrupt is masked 1=Interrupt triggers a Wake Event
0=Interrupt is enabled
0=Interrupt does not trigger a wake event.
Port 1 Data register is a read/write byte direction
Interrupts
In order to use an interrupt with aDIO, the interrupt must first be selected in the BIOS setup utility under
Advanced, I/O Devices, aDIO Configuration, aDIO Interrupt. The Digital I/O can use interrupts 3, 5, 6, 7, 10,
11, and 12. The interrupt must also be reserved so that is it not assigned to PCI devices. To reserve the interrupt,
enter the BIOS under PCIPnP and change the interrupt you wish to use to “Reserved.” Then, select the
appropriate interrupt mode in the DIO Control register. Also, verify that the Int Mask bit is cleared in the Wake
Control register
Advanced Digital Interrupts
There are three Advanced Digital Interrupt modes available. These three modes are Event, Match, and Strobe.
The use of these three modes is to monitor state changes at the aDIO connector. Interrupts are enabled by
writing to the Digital IRQ Mode field in the DIO-Control register.
Event Mode
When this mode is enabled, Port 0 is latched into the DIO-Compare register at 8.33 MHz. The aDIO circuitry
includes deglitching logic. The deglitching requires pulses on Port 0 to be at least 120 ns in width. As long as
changes are present longer than that, the event is guaranteed to register. Pulses as small as 60 ns can register as
an event, but they must occur between the rising and falling edge of the 8.33 MHz clock. To enter Event mode,
set bits [4:3] of the DIO-Control register to “10”.
Match Mode
When this mode is enabled, Port 0 is latched into the DIO-Compare register at 8.33 MHz. The aDIO circuitry
includes deglitching logic. The deglitching requires pulses on Port 0 to be at least 120 ns in width. As long as
changes are present longer than that, the match is guaranteed to register. Pulses as small as 60 ns can register as
a match, but they must occur between the rising and falling edge of the 8.33 MHz clock. To enter Match mode,
set bits [4:3] of the DIO-Control register to “11”.
Note Make sure bits [4:3] are set BEFORE writing the DIO-Compare register. If you do not set them first,
the contents of the DIO-Compare register could be lost because the Event mode latches in Port 0 into the
DIO-Compare register.
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Figure 6 aDIO Match Mode
Strobe Mode
Another interrupt mode supported by aDIO is Strobe mode. This allows the strobe pin of the DIO connector to
trigger an interrupt. A low to high transition on the strobe pin will cause an interrupt request. The request will
remain high until the Clear Register is read from. Additionally, the Compare Register latched in the value at Port
0 when the Strobe pin made a low to high transition. No further strobes will be available until a read of the
Compare Register is made. You must read the Compare Register, and then clear interrupts so that the latched
value in the compare register is not lost. To enter Strobe mode, set bits [4:3] of the DIO-Control register to “01”.
Wake-on-aDIO
The aDIO Strobe, Match and Event interrupt can be used to generate a wake event. This event can wake the CPU
from any power-down mode, including Soft-Off (S5). Wake from aDIO will work as long at +5V Standby power
is applied to the board. To use the aDIO to wake the system, Wake from aDIO must first be enabled in the BIOS
setup utility. Then the aDIO is configured in the appropriate interrupt mode. The “Wake Enable” bit is then set
in the Wake Control Register at 0x454. The CPU can then be placed in a standby mode, and the aDIO interrupt
will wake the system.
During system standby, a 32kHz clock is used for the aDIO instead of an 8.33 MHz clock. Therefore, transitions
must be at least 30 us in order to trigger a wake event.
If the aDIO is to be used for a wake event only, and not an interrupt, the “Int Mask” bit can be set in the Wake
Control Register. This will block the interrupt, but still allow a wake event to occur. The various settings for “Wake
Table 51 Interrupt and Wake Event Generation
WakeEnable Int Mask
Function
0
0
1
1
0
1
0
1
Interrupt Only
No Interrupt or Wake event is generated
Interrupt and Wake Event
Wake Event Only
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multiPort: Parallel Port Control
The parallel port may be operated in SPP (output-only), EPP (bidirectional), and ECP (extended capabilities)
modes. The mode may be selected in the BIOS, or by application software.
To configure the parallel port in the BIOS, enter the BIOS, and follow the steps below:
1. Under the “Advanced” menu in the BIOS, select the “I/O Device Configuration” submenu
2. Set the multiPort mode to “Parallel Port”
3. When a new “Parallel Port Configuration” appears, select it and configure the parallel port base address,
parallel port mode, and IRQ
multiPort: Floppy Drive
The multiPort connector can be configured as a floppy drive. To utilize the floppy controller, the multiPort mode
must be first be set to Floppy Drive in the BIOS. The complete process for setting up the multiPort as a floppy
drive is described below.
1. With the system powered off, attach a floppy drive with an adapter board to CN6.
2. Power on the system and enter the BIOS setup screen by pressing the delete key as the system boots.
3. Set Drive A to 1.44 MB in the Standard CMOS Settings section of BIOS Setup.
4. Set the multiPort to Floppy in the BIOS Setup.
5. If booting to the floppy drive is required, set the first boot device in the boot sequence to floppy drive
When the floppy drive is enabled, a special cable and adapter board is required. For more information about this
AC’97 Audio
To use the CPU’s onboard audio, it must first be enabled in the BIOS. Two signaling levels are supported, so a line
out connection can be used for powered speakers, as well as a headphone connection for non-powered speakers.
Once enabled, two audio output modes can be selected:
•
•
Line Out: This signaling level should be used for powered speakers.
Headphone: This signaling level should be used for non-powered speakers.
Ethernet (10/100Base-T and -TX)
To use the onboard 10/100 Ethernet controller, Ethernet must first be enabled in the BIOS.
When enabled, the multi-color LED will blink to indicate an Ethernet connection. For more information, refer to
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IDE Controller Configuration
The CPU’s onboard EIDE connector (CN10) supports several different drive speed modes, which are BIOS
configurable. Supported drive modes will depend on whether a 40-conductor or 80-conductor cable is
connecting the EIDE device. The modes and cable detection schemes described below may be set in the BIOS
Setup. Similarly, the ATA/IDE Disk Chip socket (U16) is BIOS configurable.
Cable Modes
There are two types of cables that may be used for connecting drives to the EIDE connector: 40 conductor cables
or 80 conductor cables. Depending on the cable used, different drive speeds are supported. A 40 conductor cable
can be used for speeds up to UDMA Mode 2 (Ultra ATA/33).
In order to use drive speeds faster than UDMA Mode 2 (Ultra ATA/33), an 80 conductor cable is required. The
BIOS can be configured to detect the presence of an 80 conductor cable. The 80 conductor cable adds a ground
wire between each signal, and uses standard 40 pin connectors.
Cable Detection
Every time the cpuModule is powered on or a hardware reset is issued, the BIOS will automatically detect the
presence of a 80 conductor cable connecting a device to CN10. The user selectable cable detection modes are
described below.
Device and Host Mode
For this method, there is a capacitor on the CBLID pin at the CPU, and a pull-up at the hard drive. The CPU sends
a command to the hard drive to drive the CBLID pin low, and then release it. The CPU then waits a certain
amount of time, and instructs the hard drive to read the status of the CBLID pin. If an 80 conductor cable is
attached, the CBLID signal is not connected between the CPU and the hard drive, and the hard drive will read
the signal as a logic high. If a 40 conductor cable is attached, the CBLID pin is connected between the CPU and
the hard drive, the capacitor delays the signal from going high, and the hard drive reads it as a logic low.
Host Determination of Cable Type
For this method of detection, the CPU reads the CPBLID pin, which determines if a 40-conductor or 80-
conductor cable is connected between the CPU and device. An 80-conductor cable has this signal grounded at
the CPU end, and not connected to the hard drive. A 40-conductor cable connects the CBLID signal to the hard
drive, where it is pulled to a logic high.
Device Detect
For device detect mode, the CPU issues a command to the device, which tells the CPU the fastest drive speed
mode it can use. The CPU then sets the transfer mode to the fastest speed supported by the device.
WARNING When this cable detection method is enabled, the highest transfer speed supported by the
device will be used regardless of whether a 40-conductor or 80-conductor cable is used. If the device speed
does not match the cable, data corruption and unexpected behaviors may occur. This mode should not
be selected unless the user knows the cable type and the modes supported by the connected EIDE device.
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Legacy Mode and Native Mode IDE
The onboard EIDE controller may be configured as a either a Legacy or Native Mode IDE controller in the BIOS
Setup. However, the operating system must support the selected mode for the device to operate correctly. The
default configuration for the controller is Legacy Mode, as this is supported by most operating systems.
Legacy Mode
Legacy mode is the default configuration of the onboard EIDE controller. When in this mode, the controller will
be fixed to use two interrupts: IRQs 14 and 15. Similarly, the I/O address of the controller will be fixed in the
system. When in Legacy Mode, only a primary and secondary channel may be used in the system.
Native Mode
Native Mode allows more flexibility, as the system resources used by the IDE controller may be modified. When
in Native Mode, the IDE controller only requires a single IRQ. Unlike Legacy Mode, this IRQ may be changed by
the user or the operating system for better distribution of the system IRQs. When IRQs in the system are more
evenly distributed, interrupt latency is minimized. The base address of the controller may also be modified.
Configuring the ATA/IDE Disk Chip Socket
The cpuModule was designed to be used in embedded computing applications. In such environments, rotating
media like hard disks and floppy disks are not very desirable. It is possible to eliminate rotating storage devices
by placing your operating system and application software into the cpuModule's ATA/IDE Disk Chip socket.
WARNING Before installing a device in the ATA/IDE Disk Chip socket, the system must be configured in
the correct mode. For details on configuring the socket, refer to Chapter 4, Using the cpuModule
Before installing a device in the ATA/IDE Disk Chip socket, it is highly recommend to first configure the secondary
IDE controller and device mode in the BIOS setup.
The secondary IDE controller must be enabled in the BIOS to allow read and write access to the device. When a
device is installed in the socket, it will always appear as a master on the cpuModule’s secondary IDE controller.
From the BIOS setup screen, the user can also configure whether the socket contains a DMA mode or PIO mode
device.
•
•
DMA Mode: DMA mode will reduce CPU overhead.
PIO Mode: When the socket is in PIO mode, PIO transfers are supported. PIO mode supports write
protection.
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Real Time Clock Control
Overview
The cpuModule is equipped with a Real Time Clock (RTC) which provides system date and time functions.
When the cpuModule is turned off, a battery must be attached to the utility connector to provide power to the
RTC. Without power, the RTC will lose the date/time information when the system is turned off.
The RTC also provides an “alarm” function. This may be used to generate an interrupt at a particular time and
day. This feature is commonly used to wake up the system from Sleep/Standby to run a scheduled task
(defragment the hard drive, back up files, etc.).
In addition to the date/time/alarm functions, the RTC contains several bytes of battery-backed RAM, commonly
called CMOS memory. In a typical desktop PC, the CMOS memory is used by the BIOS to store user settings.
This RTD cpuModule uses onboard flash to store user BIOS settings. To preserve compatibility with traditional
PCs, the RTD Enhanced BIOS also mirrors the user settings from flash in CMOS. Therefore, the contents of
CMOS may be overwritten at boot time, and should be treated as “read only”.
Accessing the RTC Registers
You may access the RTC date/time and CMOS memory using the Index and Data Registers located at I/O
addresses 70h and 71h.
•
Address 70h is the Index register. It must be written with the number of the register to read or write.
Valid values are 00h to 7Fh.
•
Address 71h is the Data register. It contains the contents of the register pointed to by the Index.
To read/write an RTC register, you must first set the Index register with the register number, and then read/write
the Data register.
.
Table 52 Real Time Clock Registers
Registers
(hex)
Registers
(decimal)
Function
00h
02h
04h
06h
07h
08h
09h
0Ah
0
2
RTC Seconds
RTC Minutes
4
RTC Hours
6
RTC Day of Week
RTC Day of Month
RTC Month
7
8
9
RTC Year
10
RTC Status Register A
•
Bit 7: RTC Update In Progress (Read Only) - RTC registers
should not be accessed when this bit is high.
•
•
Bits 6-4: Divider for 32.768 KHz input (should always be 010)
Bits 3-0: Rate select for periodic interrupt.
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Table 52 Real Time Clock Registers
Registers
(hex)
Registers
(decimal)
Function
0Bh
11
RTC Status Register B
•
•
•
•
Bit 7: Inhibit Update - When high, the RTC is prevented from
updating.
Bit 6: Periodic Interrupt Enable - When high, the RTC IRQ will
be asserted by the periodic interrupt.
Bit 5: Alarm Interrupt Enable - When high, the RTC IRQ will be
asserted when the current time matches the alarm time.
Bit 4: Update Ended Interrupt Enable - When high, the RTC IRQ
will be asserted every time the RTC updates (once per second).
•
•
Bit 3: Square Wave Enable - Not used.
Bit 2: Data Mode - Sets the data format of the RTC
clock/calendar registers (0=BCD, 1=binary). This is typically set
to BCD mode.
•
•
Bit 1: Hours Byte Format - Sets the hour byte to 12 or 24 hour
time (0=12 hour, 1=24 hour). This is typically set to 24 hour
mode.
Bit 0: Daylight Savings Enable - When high, the RTC will
automatically update itself for Daylight Savings Time. It is
recommended to leave this bit low and let the operating system
manage time zones and DST.
0Ch
12
RTC Status Register C (Read Only)
•
Bit 7: IRQ Flag - Indicates that the Real Time Clock IRQ is
asserted. Goes high whenever one of the enabled interrupt
conditions in Register B occurs.
•
•
•
•
Bit 6: Periodic Flag
Bit 5: Alarm Flag
Bit 4: Update Ended Flag
Bit 3-0: Reserved
Reading this register will also clear any of set flag (IRQ, Periodic, Alarm, Update
Ended). Note that even if the interrupt source is not enabled in Register B, the
flags in Register C bits 4, 5, and 6 may still be set.
0Dh
13
RTC Status Register D
•
•
•
Bit 7: Valid Time/Date (always reads 1)
Bit 6: Reserved
Bits 5-0: RTC Alarm Day of the Month
Note RTC registers that are not listed above are used by the BIOS and should be considered “Reserved”.
Altering the contents of any unlisted RTC register may interfere with the operation of your cpuModule.
The specific uses of the unlisted RTC registers will depend on the BIOS version loaded on the cpuModule.
Contact RTD's technical support for more information.
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Watchdog Timer Control
The cpuModule includes a watchdog timer, which provides protection against programs “hanging”, or getting
stuck in an execution loop where they cannot respond correctly. When enabled, the watchdog timer must be
periodically reset by your application program. If it is not refreshed before the time-out period expires, it will
cause a hardware reset of the cpuModule.
The watchdog time-out period is typically 1.1 seconds, but can vary between 550 ms and 1.65 seconds. Because
of operating system latency, it is recommended that the watchdog be refreshed at half of the period, or every
275 ms.
Before using the Watchdog timer, it must be enabled in the BIOS setup utility. When it is disabled in the BIOS,
the watchdog register does not appear in I/O space and it will not generate an a reset.
Note Enabling the watchdog timer in the BIOS does not actually arm it. The watchdog timer can be
armed by accessing I/O address 455h, as explained below.
Three functions have been implemented on the cpuModule for controlling watchdog timer control. These are:
•
•
•
Arm: The watchdog timer can be enabled by writing a 1 to bit 7 of I/O port 0x455. To ensure
compatability with future designs, you should read the register and only change the bit you need to
change.
Disarm: The watchdog timer is disabled by writing a 0 to bit 7 of I/O port 0x455. To ensure
compatability with future designs, you should read the register and only change the bit you need to
change.
Refresh: The watchdog timer is refreshed by reading from I/O port 0x455. After you enable the
watchdog timer, you must refresh it at least once every 550 ms.
Table 53 Watchdog Timer Control I/O Address 455h
D7
D6 D5 D4 D3 D2 D1 D0
Watchdog Enable
0=Watchdog timer is disabled and will not
generate an interrupt
1=Watchdog Timer is enabled and needs
to be refreshed
Reserved
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Thermal Management
The cpuModule has several thermal features which can be used to monitor and control the board’s temperature
when extreme operating conditions are prevalent.
Thermal Monitor
The Intel ® Thermal Monitor is a feature on the CMX158886 that automatically initiates a SpeedStep transition
or throttles the CPU when the CPU exceeds its thermal limit. The maximum temperature of the processor is
defined as the temperature that the Thermal Monitor is activated. The thermal limit and duty cycle of the
Thermal Monitor cannot be modified.
Note The CPU and PCB temperatures displayed in the BIOS are approximate and should not be used to
validate a cooling solution.
Fan Mode
The CPU fan can be controlled by the CPU when connected to the switched fan power connector (CN15). Three
fan modes are supported, which can be toggled in the BIOS setup. When the fan is not always on, the CPU’s
power consumption is reduced, and the life of the fan is increased.
•
•
Always On: When in this mode, the fan is always powered by the CPU.
On At 70C: This mode allows the system to keep the fan turned off until the CPU reaches 70C. In this
mode, the fan will slowly transition between on and off to prevent oscillations. This is the best mode
for applications that will spend most of the time below 0C.
•
Variable: The fan will spin slowly until the CPU reaches 60C, and then will increase speed. Maximum
speed is reached when the CPU reaches 75C.
Note If the CPU fan is connected to the continuous +5 V fan connector (CN14), changing the fan mode
options in the BIOS will not affect the fan, as it will always be turned on.
Further Temperature Reduction
The cpuModule’s temperature is directly related to power consumption. Reducing the power consumption of
the CPU will have an effect on the CPU’s temperature. Suggested methods for reducing the CPU’s power
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Power Management
The CMX158886 cpuModule supports various powering mechanisms which allow the cpuModule to monitor
power consumption and temperature, and achieve minimal power consumption states. These unique features
include Enhanced Intel® SpeedStep® Technology (PX only), thermal monitoring and thermal throttling, as well as
low power modes including ACPI configurations. Various wake options are also available to resume normal
system power.
Enabling Enhanced Intel SpeedStep Technology (PX only)
When enabled, Enhanced Intel® SpeedStep® Technology can give application software greater control over the
processor’s operating frequency and input voltage. This allows the system to easily manage power consumption
dynamically. This feature can be enabled or disabled in the BIOS. When enabled, the feature can be set to several
different modes, which are described below.
•
•
•
Maximum Speed: The processor speed is set to its maximum operating frequency.
Minimum Speed: The processor speed is set to its minimum operating frequency.
Automatic: When set to automatic mode, the processor speed is controlled by the operating system.
Advanced Configuration and Power Interface (ACPI)
The cpuModule supports several different ACPI low power modes, including the S1, S3, S4, and S5 sleeping states.
The BIOS setup utility provides an option to select between S1 and S3 as the Standby state. Sleep modes S4 and
S5 are setup by the operating system.
The cpuModule’s ACPI suspend modes are described below
•
S1 (Power on Suspend): The S1 low power state consumes the most power of all supported ACPI sleep
modes. In this mode, the CPU stops executing instructions, but power to the CPU and RAM is
maintained.
•
S3 (Suspend to RAM): Everything in the system is powered off except for the system memory. When
the system wakes from this mode, operating systems allow applications to resume where they left off,
as the state of the application is preserved in memory.
•
•
S4 (Hibernate): When the system enters this state, the operating system will save the current state of
applications and relevant data to disk, thus allowing the system RAM to be powered down.
S5 (Soft-Off): The system is in a soft off state, and must be rebooted when it wakes.
Power Button Modes
The soft power button input of the utility port connector (CN5) can be configured by the operating system as
a suspend button (transition to S1 or S3) or as soft power button (transition to S5). Consult your operating
system documentation for information on how to configure it. The power button will always cause a transition
to S5 if pressed for 4 seconds or longer, without interaction from the operating system.
Low-Power Wake Options
The cpuModule supports several methods of waking from a low power state. Several of these wake options are
BIOS configurable, and can be accessed directly from the “Power” menu in the BIOS setup:
•
Resume on Ring: While in a low power mode, the ring indicator input of either COM port may be used
to wake the system.
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•
•
•
Resume on aDIO: This option allows the system to use an aDIO Strobe, Match, or Event interrupt to
generate a wake event. This event can wake the CPU from any power-down mode, including Soft-Off
Resume on PME#: When enabled, the system can wake when a signal is applied to the External Power
Management connector (CN12). This includes wake-up on onboard LAN controller. The PME# signal
is also available on the PC/104-Plus (PCI) bus connector.
Resume on RTC Alarm: The RTC Alarm allows the system to turn on at a certain time every day.
AT vs. ATX Power Supplies
Both AT and ATX power supplies may be used with the CMX158886 cpuModule, however AT power supplies do
not provide any standby power to the cpuModule. When an AT power supply is used to power the system, low
power modes that require a standby power to wake the system will not be fully supported.
ATX power supplies do provide a standby power, thus allowing the system to utilize all low power modes
supported by the hardware. When an ATX supply is used to power the cpuModule, lower power modes can be
achieved. During these low power modes, the standby power from the ATX power supply provides power to a
small circuit on the CPU, which is used to watch for a system wake event.
ATX Power Supply Signals
The auxiliary power connector (CN3) provides two ATX style signals., +5V Standby and PSON#. The +5V
Standby rail is used to power certain parts of the cpuModule when the main power supply is turned off, i.e.
during Suspend-to-RAM (S3), Hibernate (S4), or Soft-Off (S5) power modes. The PSON# signal is an active low
open-drain output that signals the power supply to turn on. Use of these signals allows the power consumption
to drop to below 1W during standby modes, and still enable any of the wake events.
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Reducing Power Consumption
In addition to the CPU’s low power modes, power consumption can further be reduced by making some
modifications to the BIOS setup. When the following features are modified, the CPU’s power consumption will
decreases:
•
•
CPU Speed: Setting the processor to its minimum speed in the BIOS will reduce power consumption
Memory Speed: Changing the DDR DRAM clock frequency will reduce power consumption, however
memory performance will also be reduced.
•
•
•
Ethernet: Can be disabled in the BIOS
Serial Ports: Can be disabled in the BIOS
LVDS Flat Panel: If an LVDS panel is not connected to the cpuModule while using a VGA monitor,
setting the BIOS to use only a CRT (VGA) monitor will reduce power consumption.
•
•
Fan Mode: Set the fan to auto mode so it is used only when the processor reaches high temperatures.
This option will only effect the fan if it is connected to the switched fan power connector (CN15).
Multi-Color LED: Can be disabled in the BIOS
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Multi-Color LED
The CMX158886 has a Multi-Color LED located beside the EIDE connector (CN10) which can be enabled or
disabled in the BIOS setup screen. The color of the LED indicates the status of the board, as shown in Table 54.
Table 54 LED Colors
Color
Description
Green
Blue
Red
Normal Operation
On Board IDE Activity
cpuModule is in reset1
Yellow (Red + Green)
White (R+G+B)
Cyan (Blue + Green)
Magenta (Blue + Red)
Blink
cpuModule is in Standby
cpuModule is approaching thermal limit2
Ethernet Link at 10 Mbps
Ethernet Link at 100 Mbps
Ethernet Activity
1. If power is applied to the cpuModule while jumper JP5 is installed, the LED will be red. This does not
indicate that the board is in reset
2. The LED will remain White until the system is shut down.
The LED can also be controlled manually by writing to I/O Port 456h, as shown in Table 55 and Table 56.
Table 55 Multi-Color LED I/O Address 456h
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
(User
Reserved
(User
Reserved
(User
Reserved
Reserved
Multi-Color LED
EEPROM)
EEPROM)
EEPROM)
Note When writing to I/O Port 456h, only the lower three bits of the register should be modified.
Modifying the upper bits will effect the User EEPROM
The following table lists the color displayed and the value written.
Table 56 Manual LED Colors
I/O Port 456h Value
0x00
Color
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
Off (will reduce system power consumption.)
Blue
Green
Cyan (Green + Blue)
Red
Magenta (Red + Blue)
Yellow (Red + Green)
White (Red + Green + Blue)
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Reset Status Register
The cpuModule has several different signals on board which can cause a system reset. If a reset occurs, the reset
status register can be used to see which reset or resets have been asserted on the cpuModule.
The user has the ability to see which resets have been asserted. Resets can also be cleared.
•
•
Examine Resets: Reading from I/O port 0x457 will indicate if a reset has been asserted. If a 1 is read, the
corresponding reset has been asserted. If a 0 is read from the bit, the reset has not been asserted
Clear Reset: Each reset can be cleared by writing a 1 to the selected bit of I/O port 0x457.
Table 57 Reset Status I/O Address 457h - Read Access
D7
D6
D5
D4
D3
D2
D1
D0
Main Power (+5V)
1 = reset asserted
0 = no reset
PCI Reset
1 = reset asserted
0 = no reset
Standby Power
1 = reset asserted
0 = no reset
Non-Standby Power
1 = reset asserted
0 = no reset
CPU Core Power
1 = reset asserted
0 = no reset
Utility Reset
1 = reset asserted
0 = no reset
Reserved
Memory Power
1 = reset asserted
0 = no reset
Table 58 Reset Status I/O Address 457h - Write Access
D7
D6
D5
D4
D3
D2
D1
D0
Main Power (+5V)
1 = clear reset
PCI Reset
1 = clear reset
Standby Power
1 = clear reset
Non-Standby Power
1 = clear reset
CPU Core Power
1 = clear reset
Utility Reset
1 = clear reset
Reserved
Memory Power
1 = clear reset
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Table 59 Reset Status Description and Priorities
I/O Address
457h
Reset
Signal
Reset
Description
Priority1
D7
D6
D5
Main Power (+5V)
CPU Core Power
2
3
3
Main input power to cpuModule (+5V)
CPU core powers supply
Non-Standby Power
Power supplies that are not for standby
power
D4
D3
D2
D1
D0
Memory Power
Standby Power
reserved
3
1
-
Power to onboard memory banks
Standby power supplies
reserved
PCI Reset
4
-
PCI bus reset signal
Utility Reset
Utility connector push button reset2
1. When a reset is asserted, all resets with a higher reset priority will also be asserted. For example, if the standby
power reset is asserted, all other resets will also be asserted.
2. The BIOS allows the user to change the function of the utility connector’s push button reset. Even if the push
button is not configured as a reset, this bit will always read a 1(asserted) when the reset button has been
pushed.
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DVMT Mode Select
The CMX158886 supports Dynamic Video Memory Technology (DVMT). DVMT allows the CPU to allocate
memory to system processing or graphics processing on the fly based on changing processing requirements.
For example, a graphics intensive program will require the operating system to request a larger amount of video
memory than one that does not require large amounts of graphics processing. For the graphics intensive process,
DVMT will allocate a larger portion of system memory. When the process is complete, DVMT will allocate the
memory back to the system.
The CMX158886 supports three user-selectable modes, including Fixed Mode, DVMT Mode, and Combo Mode.
•
•
•
Fixed Mode: A fixed amount of system memory is reserved for video.
DVMT Mode: Video memory is dynamically allocated as needed.
Combo Mode: A fixed amount of memory is allocated, but more can be claimed as needed.
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User EEPROM
A 512kB serial EEPROM (Atmel AT93C66) is available on the cpuModule for the user to save nonvolatile
parameters on the cpuModule. The EEPROM can be accessed by reading and writting to I/O address 456h, as
shown in the following table.
Table 60 User EEPROM I/O Address 456h
D7
CS
D6
SK
D5
DI
D4
D3
D2
D1
D0
DO
Reserved
(Multi-Color LED)
Table 61 EEPROM Register Description
Bit
Signal
Function
Read / Write
D7
D6
D5
D4
D3
D2
D1
D0
CS
SK
Chip Select
Serial Data Clock
Serial Data Input
Serial Data Output
Reserved
Read / Write
Read / Write
Read / Write
Read Only
DI
DO
(Multi-Color LED)
(Multi-Color LED)
(Multi-Color LED)
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Features and Settings That Can Affect Boot Time
The boot time of a system is dependent upon numerous system settings as well as devices attached to a system.
This section addresses some devices and settings that can increase or decrease a system’s boot time.
Quick Boot
The BIOS contains a Quick Boot option that minimizes the boot time of the system. Quick Boot eliminates the
exhaustive tests that are performed during Power On Self Test (POST) while maintaining the functionality of the
board. By enabling the Quick Boot feature, your system can achieve 5-second boot times.
Add-On Cards With BIOS Extensions
Some add-on cards have an integrated BIOS extension. The most common examples are SCSI controllers and
network cards with boot ROMs. During POST, the BIOS executes the card's extension code. This extension code
is third-party code, which is beyond RTD's control. The BIOS extension will most likely increase the boot time.
Exactly how much it increases boot time will depend on the particular card and firmware version.
VGA Controller
VGA controllers have a VGA BIOS that must be initialized during POST. It can take some time to initialize the
VGA BIOS. Exactly how long will depend on the particular VGA controller and BIOS version.
Hard Drive Type
During IDE initialization, each IDE device must be probed. Some devices take longer to probe. 2.5-inch hard
drives tend to take longer than 3.5-inch ones, because they spin at a lower RPM.
Monitor Type
Some monitors take a while to power on. Desktop flat panels are especially slow. This does not affect the actual
boot time of the CPU. However, the CPU may boot before the monitor powers on.
NVRAM Updates
System configuration data is stored in the onboard NVRAM. When the system configuration changes, this
information must be updated. If an update is necessary, it will happen at the end of POST (the BIOS will display
an “Updating NVRAM…” message). The NVRAM update takes a few seconds and increases the boot time. Once
the NVRAM is updated, boot times will return to normal.
NVRAM updates only happen when the system configuration changes. They do not happen spuriously. They are
usually triggered by adding or removing a PCI device from a stack. Updates can also be triggered by altering the
Plug-n-Play configuration of the BIOS.
Boot Device Order
The BIOS contains a list of devices to try booting from. If you wish to boot to a particular device (for example, a
hard drive), make sure that it is first in the boot order. This will speed up boot times.
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System Recovery
Loading Default BIOS Settings
The default BIOS can be restored either by using the “Load Defaults” option in the BIOS, or by installing jumper
JP5 (see Figure 7 on page 87). In most cases, the easiest way to load default settings is by setting them in the BIOS.
For other unique cases, jumper JP5 provides an alternative method of restoring the BIOS settings.
To restore the default BIOS settings with jumper JP5, follow the procedure below.
1. Remove power from the system.
2. Install JP5.
3. Apply power to the system. The cpuModule will then load its default settings. Note that the
multi-color LED will be red if power is applied while JP5 is installed.
4. Reboot and press Delete to enter BIOS Setup.
5. Save the BIOS settings and exit, allowing the system to boot to the FSBR.
6. The next time the system is powered, the BIOS Setup will be configured to use the default settings.
Booting to the Fail Safe Boot ROM (FSBR)
If your system is in configuration that will not allow it to boot, the Fail Safe Boot ROM is a minimal build of
ROM-DOS which can be booted to for system debugging. To boot to the FSBR, follow the instructions below.
1. Reboot the system and press Delete to enter BIOS Setup.
2. In the Boot menu, select Bootup Options, and change RTD Fail Safe Boot ROM to Enabled.
3. Save the BIOS settings and exit.
If you are unable to enter the BIOS Setup, an alternate method is to use JP5 as described below:
1. Remove power from the system.
2. Install JP5. This will force the cpuModule to boot using the default BIOS configuration.
3. Apply power to the system. The cpuModule will then boot to the Fail Safe Boot ROM image. Note that
the multi-color LED will be red if power is applied while JP5 is installed.
4. Press the Delete key to enter Setup, or allow the cpuModule to boot to Failsafe
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Basic Interrupt Information for Programmers
An interrupt is a subroutine called asynchronously by external hardware (usually an I/O device) during the
execution of another application. The CPU halts execution of its current process by saving the system state and
next instruction, and then jumps to the interrupt service routine, executes it, loads the saved system state and
saved next instruction, and continues execution. Interrupts are good for handling infrequent events such as
keyboard activity. Interrupts on this cpuModule are controlled by two Intel 8259-equivalent interrupt
controllers containing 13 available interrupt request lines.
What happens when an interrupt occurs?
An IRQx pin on the PC/104 bus makes a low to high transition while the corresponding interrupt mask bit is
unmasked and the PIC determines that the IRQ has priority, that is, the PIC interrupts the processor. The current
code segment (CS), instruction pointer (IP), and flags are pushed onto the stack. The CPU then reads the 8-bit
vector number from the PIC, and a new CS and IP are loaded from a vector—indicated by the vector number—
from the interrupt vector table that exists in the lowest 1024 bytes of memory. The processor then begins
executing instructions located at CS:IP. When the interrupt service routine is completed the CS, IP, and flags that
were pushed onto the stack are popped from the stack into their appropriate registers and execution resumes
from the point where it was interrupted.
How long does it take to respond to an interrupt?
A DOS system can respond to an interrupt between 6 and 15 μs. A Windows system can take a much longer time
when a service routine has been installed by a device driver implemented as a DLL—from 250 to 1500 μs or
longer. The time the CPU spends in the interrupt depends on the efficiency of the code in the ISR. These
numbers are general guidelines and will fluctuate depending on operating system and version. Minimum time
between two IRQ requests is 125 ns per ISA specification.
Interrupt Request Lines
To allow different peripheral devices to generate interrupts on the same computer, the ISA bus has eight different
interrupt request (IRQ) lines. On the ISA bus, a transition from low to high on one of these lines generates an
interrupt request, which is handled by the PC’s interrupt controller. On the PCI bus, an interrupt request is
level-triggered.
The interrupt controller checks to see if interrupts are to be acknowledged from that IRQ and, if another
interrupt is already in progress, it decides if the new request should supersede the one in progress or if it has to
wait until the one in progress is done. This prioritizing allows an interrupt to be interrupted if the second request
has a higher priority. The priority level is based on the number of the IRQ; IRQ0 has the highest priority, IRQ1 is
second-highest, and so on through IRQ7, which has the lowest. Many of the IRQs are used by the standard system
resources. IRQ0 is used by the system timer, IRQ1 is used by the keyboard, IRQ3 by COM2, IRQ4 by COM1, and
IRQ6 by the disk drives. Therefore, it is important to know which IRQ lines are available in your system for use by
the cpuModule.
BDM-610000049 Rev G
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Intel 8259 Programmable Interrupt Controller
The chip responsible for handling interrupt requests in the PC is the Intel 8259 Programmable Interrupt
Controller. To use interrupts, you need to know how to read and set the Intel 8259’s interrupt mask register (IMR)
and how to send the end-of-interrupt (EOI) command to the Intel 8259.
Each bit in the IMR contains the mask status of an IRQ line; bit 0 is for IRQ0, bit 1 is for IRQ1, and so on. If a bit is
set (1), then the corresponding IRQ is masked and will not generate an interrupt. If a bit is clear (0), then the
corresponding IRQ is unmasked and can generate interrupts. The IMR is programmed through port 21h.
Note When in APIC mode, the PIC is programmed differently, and IRQ routing behaves differently. For
more information, refer to the APIC datasheets and specifications provided by Intel.
PCI Interrupts
PCI devices can share interrupts. The BIOS or operating system may assign multiple PCI devices to the same IRQ
line. Any interrupt service routine (ISR) written for PCI devices must be able to handle shared interrupts. Refer
to Interrupt-Driven PC System Design (ISBN: 0-929392-50-7) for more information on PCI interrupts.
Writing an Interrupt Service Routine (ISR)
The first step in adding interrupts to your software is to write the ISR. This is the routine that will automatically
be executed each time an interrupt request occurs on the specified IRQ. An ISR is different than standard
routines that you write. First, on entrance, the processor registers should be pushed onto the stack BEFORE you
do anything else. Second, just before exiting your ISR, you must clear the interrupt status flag and write an
end-of-interrupt command to the Intel 8259 controller. Finally, when exiting the ISR, in addition to popping all
the registers you pushed on entrance, you must use the IRET instruction and not a plain RET. The IRET
automatically pops the flags, CS, and IP that were pushed when the interrupt was called.
Most C compilers allow you to identify a procedure (function) as an interrupt type and will automatically add
these instructions to your ISR, with one important exception: most compilers do not automatically add the
end-of-interrupt command to the procedure; you must do this yourself. Other than this and the few exceptions
discussed below, you can write your ISR just like any other routine. It can call other functions and procedures in
your program and it can access global data. If you are writing your first ISR, RTD recommends focusing on the
basics, such as incrementing a global variable.
Most operating systems have restrictions on what instructions can be called in your ISR. Consult your OS
documentation for details on writing your ISR.
Note A complete explanation of interrupt programming is beyond the scope of this manual. For more
information on interrupts, refer to the Appendix.
Sample Code
RTD’s drivers provide examples of ISR’s and interrupt handling. Refer to them as working examples. These drivers
were shipped with your cpuModule, but they can also be downloaded from RTD’s website (www.rtd.com).
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Jumper Settings and Locations
Many cpuModule options are configured by positioning jumpers. Jumpers are labeled on the board as JP
followed by a number.
Some jumpers have three pins, allowing three settings:
•
•
•
Pins 1 and 2 connected (indicated as “1–2”)
Pins 2 and 3 connected (indicated as “2–3”)
No pins connected
3
1
2
Some jumpers have two pins, allowing two settings:
•
•
Pins 1 and 2 connected (indicated as “closed”)
Pins 1 and 2 unconnected (indicated as “open”)
1
2
Figure 7 shows the jumper locations that are used to configure the cpuModule. Table 62 lists the jumpers and
their settings.
JP1
JP12
JP11
JP9
JP2
JP13
JP14
JP5
JP6
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Figure 7 CMX158886 Jumper Locations (top side)
Table 62 CMX158886 Jumpers
Jumper
Pins
Function
Default
JP1
JP2
JP5
2
2
2
Enable/disable 120 Ω series termination to COM1 (CN7) in RS-422/485 modes
Enable/disable 120 Ω series termination to COM2 (CN8) in RS-422/485 modes
open
open
open
Install to load the default BIOS settings and boot to Fail Safe (for more
will be red if JP5 is installed.
JP6
JP9
2
3
Reserved
open
Select power for flat panel backlight
pins 1–2: +12 V
pins 2–3
pins 2–3: +5 V
JP11
2
Enable/disable 120 Ω series termination to second serial port on CN7 in
open
RS-422/485 modes
JP12
JP13
2
2
Install to support RS-422/485 modes for second serial port on CN7
open
open
Enable/disable 120 Ω series termination to second serial port on CN8 in
RS-422/485 modes
JP14
2
Install to support RS-422/485 modes for second serial port on CN8
open
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Appendix A: Hardware Reference 87
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Onboard PCI Devices
The CMX158886 cpuModule has several onboard PCI devices, all of which are listed in the table below.
Table 63 Onboard PCI Devices
Device ID
Vendor ID
Description
103E
244E
24C0
24C2
24C3
24C5
24CB
24CD
3580
3582
3584
3585
-
8086
8086
8086
8086
8086
8086
8086
8086
8086
8086
8086
8086
-
LAN Controller
Hub to PCI Bridge
PCI to LPC Bridge
USB UHCI Controller
SMBus Controller
AC’97 Audio Controller
IDE Controller
USB EHCI Controller
Host-Hub
Graphics Device
Main Memory
Configuration Process
PCI Slot 1
-
-
PCI Slot 2
-
-
PCI Slot 3
-
-
PCI Slot 4
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Physical Dimensions
Figure 8 shows the mechanical dimensions of the CMX158886 cpuModule.
Figure 8 CMX158886 Physical Dimensions ( 0.005 inches)
Heatsink height: The mini fan heatsink on the CMX158886 extends 0.6” inches above the top side of the PCB.
BDM-610000049 Rev G
Appendix A: Hardware Reference 89
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Appendix B
Troubleshooting
Many problems you may encounter with operation of your CMX158886 cpuModule are due to common errors.
This appendix includes the following sections to help you get your system operating properly.
BDM-610000049 Rev G
Appendix B: Troubleshooting 91
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Common Problems and Solutions
Table 64 lists some of the common problems you may encounter while using your CMX158886 cpuModule, and
suggests possible solutions.
If you are having problems with your cpuModule, review this table before contacting RTD Technical Support.
Table 64 Troubleshooting
Problem
Cause
Solution
cpuModule
“will not boot”
no power or wrong polarity
incorrect Setup
•
•
check for correct power on the PC/104-Plus (PCI) bus connector
reboot and press Delete to run Setup
defective or misconnected
device on bus
•
•
check for misaligned bus connectors
remove other cards from stack
cable connected backwards
SSD installed backwards
•
•
•
•
•
verify all cables are connected correctly
check for an SSD memory installed in socket backwards
check for correct power on the PC/104-Plus (PCI) bus connector
check that the reset button is not pushed in
cpuModule keeps rebooting problem with power supply
reset switch is on
watchdog timer is not being
serviced quickly enough
verify that the watchdog timer is being refreshed before it times
out
cpuModule will not boot
from particular drive or
device
device not bootable
•
use sys command on drive or reformat the device using
the /s switch
device not formatted
•
•
format drive using /s switch
power not connected to
boot drive
connect power cable to floppy or hard drive
erratic operation
excessive bus loading
power supply noise
power supply limiting
•
•
•
reduce number of modules in stack
remove termination components from bus signals
remove any power supply bus terminations
•
•
•
examine power supply output with oscilloscope
glitches below 4.75 VDC will trigger a reset
add bypass caps
•
•
examine power supply output with oscilloscope
check for voltage drop below 4.75 VDC when hard drive or floppy
drive starts
•
add bypass caps
insufficient cabling through
power connector
•
•
increase wire gauge to connector
power through bus connectors
temperature too high
•
•
add fan, processor heatsink, or other cooling device(s)
memory address conflict
•
•
•
•
check for two hardware devices (e.g. Ethernet, SSD, Arcnet,
PCMCIA) trying to use the same memory address
check for two software devices (e.g. EMM386, PCMCIA drivers,
etc.) trying to use the same memory addresses
check for hardware and software devices trying to use the same
memory address
check for an address range shadowed (see Advanced Setup screen)
while in use by another hardware or software device
I/O address conflict
•
•
check for another module trying to use I/O addresses reserved for
the cpuModule between 010h and 01Fh
check for two modules (e.g. dataModules, PCMCIA cards,
Ethernet) trying to use the same I/O addresses
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Table 64 Troubleshooting (cont’d)
Problem
Cause
Solution
keyboard does not work
keyboard interface damaged
by misconnection
•
check if keyboard LEDs light
wrong keyboard type
•
•
•
verify keyboard is an “AT” type or switch to “AT” mode
check for floppy drive cable connected backwards
floppy drive light always on cable misconnected
two hard drives will not
work, but one does
both drives configured for
master
set one drive for master and the other for slave operation (consult
drive documentation)
floppy does not work
“data error” due to drive
upside down
•
•
orient drive properly (upright or on side)
will not boot when video
card is removed
illegal calls to video controller
look for software trying to access nonexistent video controller for
video, sound, or beep commands
abnormal video
flat panel is enabled
•
•
•
•
disable the flat panel in the BIOS
disable the flat panel in the BIOS
install the video drivers
can only use 640 x 480
resolution in Windows
flat panel is enabled
video drivers not installed
will not boot from PCMCIA booting from PCMCIA is not
hard drive supported
boot from SSD, use autoexec.bat to load PCMCIA drivers, run
application from PCMCIA card
COM port will not work in not configured for RS-422/485
RS-422 or RS-485 modes
•
•
•
•
correctly configure serial port in Setup program
COM port will not transmit not enabling transmitters
in RS-422 or RS-485 mode
control RTS* bit of Modem Control Register to enable transmitters;
see Serial Port descriptions
date and time not saved
when power is off
no backup battery
connect a backup battery to the multi-function connector
screen flickers at high
memory with ECC enabled
disable ECC
resolutions when processor requires additional system
is fully utilized
memory resources; the
integrated graphics engine
has less memory bandwidth
for access to the graphics
frame buffer
Troubleshooting a PC/104-Plus System
If you have reviewed the preceding table and still cannot isolate the problem with your CMX158886 cpuModule,
please try the following troubleshooting steps. Even if the resulting information does not help you find the
problem, it will be very helpful if you need to contact technical support.
1. Simplify the system. Remove items one at a time and see if one particular item seems to cause the
problem.
2. Swap components. Try replacing items in the system one-at-a-time with similar items.
BDM-610000049 Rev G
Appendix B: Troubleshooting 93
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How to Obtain Technical Support
If after following the above steps, you still cannot resolve a problem with your CMX158886 cpuModule, please
gather the following information:
•
•
•
•
•
•
cpuModule model, BIOS version, and serial number
List of all boards in system
List of settings from cpuModule Setup program
Printout of autoexec.bat and config.sys files (if applicable)
Description of problem
Circumstances under which problem occurs
Then contact RTD Technical Support:
Phone: 814-234-8087
Fax:
814-234-5218
E-mail: [email protected]
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Appendix C
IDAN™ Dimensions and Pinout
cpuModules, like all other RTD PC/PCI-104 modules, can be packaged in Intelligent Data Acquisition Node
(IDAN) frames, which are milled aluminum frames with integrated heat sinks and heat pipes for fanless
operation. RTD modules installed in IDAN frames are called building blocks. IDAN building blocks maintain the
simple but rugged stacking concept of PC/104 and PC/104-Plus. Each RTD module is mounted in its own IDAN
frame and all I/O connections are brought to the walls of each frame using standard PC connectors. No
connections are made from module to module internal to the system other than through the PC/104 and
PC/104-Plus bus, enabling quick interchangeability and system expansion without hours of rewiring and board
redesign.
The CMX158886 cpuModule can also be purchased as part of a custom-built RTD HiDAN™ or HiDANplus™ High
Reliability Intelligent Data Acquisition Node. This appendix provides the dimensions and pinouts of the
CMX158886 installed in an IDAN frame. Contact RTD for more information on high reliability IDAN, HiDAN, and
HiDANplus PC/PCI-104 systems.
IDAN—Adhering to the PC/104 stacking concept,
IDAN allows you to build a customized system
with any combination of RTD modules.
IDAN Heat Pipes—Advanced heat pipe technology
maximizes heat transfer to heat sink fins.
HiDANplus—Integrating the modularity of
IDAN with the ruggedization of HiDAN,
HiDANplus enables connectors on all system
frames, with signals running between frames
through a dedicated stack-through raceway.
BDM-610000049 Rev G
Appendix C: IDAN™ Dimensions and Pinout 95
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IDAN Dimensions and Connectors
6-pin mini-DIN (female)
module P/N: Adam Tech MDE006W
mating P/N: Adam Tech MDP006
9-pin D (male)
module P/N: Adam Tech DE09PD
mating P/N: Adam Tech DE09SD
FRONT
25-pin D (female)
module P/N: Adam Tech DB25SD
mating P/N: Adam Tech DB25PD
9-pin D (female)
module P/N: Adam Tech DE09SD
mating P/N: Adam Tech DE09PD
20-pin mini D (female)
module P/N: 3M 10220-6212VC
mating P/N: 3M
15-pin high-density D (female)
module P/N: Adam Tech HDT15SD
REAR
9-pin D (male)
module P/N: Adam Tech DE09PD
mating P/N: Adam Tech DE09SD
Figure 9 IDAN-CMX158886 Connectors1
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External I/O Connections
Table 65 PS/2 Mouse — 6-Pin mini-DIN Connector (female)
IDAN Pin #
Signal
Function
1
2
3
4
5
6
MDAT
Reserved
GND
Mouse Data
—
Ground
+5 Volts
Mouse Clock
—
+5 V
MCLK
Reserved
Table 66 Keyboard — 6-Pin mini-DIN Connector (female)
IDAN Pin #
Signal
Function
1
2
3
4
5
6
KDAT
Keyboard Data
Reserved
GND
—
Ground
+5 V
+5 V
KCLK
Keyboard Clock
—
Reserved
BDM-610000049 Rev G
Appendix C: IDAN™ Dimensions and Pinout 97
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Table 67 COM1/COM2 (RS-232) — 9-Pin D Connector (male)
IDAN Pin #
Signal
Function
Mode
1
2
3
4
5
6
7
8
9
DCD
RXD
TXD
DTR
GND
DSR
RTS
CTS
RI
Data Carrier Detect
Receive Data
Input
Input
Transmit Data
Output
Data Terminal Ready Output
Ground
—
Data Set Ready
Request To Send
Clear To Send
Ring Indicator
Input
Output
Input
Input
Table 68 COM1/COM2 (RS-422/485) — 9-Pin D Connector (male)
IDAN Pin #
Signal
Function
Mode
1
2
3
4
5
6
7
8
9
Reserved
RXD–
—
—
Receive Data –
Transmit Data –
—
Input
Output
—
TXD–
Reserved
GND
Ground
—
Reserved
TXD+
—
—
Transmit Data +
Receive Data +
—
Output
Input
—
RXD+
Reserved
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Table 69 multiPort — 25-Pin D Connector (female)
IDAN Pin #
aDIO Port Parallel Port Floppy Port CPU Pin #
1
strobe 0
P1-0
STB
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
ACK
BSY
—
INDEX#
TRK0#
WRTPRT#
RDATA#
DSKCHG
—
1
3
2
3
P1-1
5
4
P1-2
7
5
P1-3
9
6
P1-4
11
13
15
17
19
21
23
25
2
7
P1-5
8
P1-6
—
9
P1-7
—
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
P0-0
DS1#
P0-1
MTR#
WDATA#
WGATE#
DR0#
P0-2
PE
P0-3
SLCT
AFD
ERR
P0-4
P0-5
HDSEL#
DIR#
4
P0-6
INIT
SLIN
GND
GND
GND
GND
GND
GND
GND
GND
6
P0-7
STEP#
GND
8
strobe 1
GND
GND
GND
GND
GND
GND
GND
10
12
14
16
18
20
22
24
GND
GND
GND
GND
GND
GND
GND
BDM-610000049 Rev G
Appendix C: IDAN™ Dimensions and Pinout 99
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Table 70 Panel — 20-Pin mini D Connector (female)
IDAN Pin #
Signal Name
CPU Pin #
1
2
LVDS_YAP0
LVDS_DDCPCLK
LVDS_YAP1
LVDS_DDCPDATA
LVDS_YAP2
GND
1
3
3
5
4
7
5
9
6
11
13
15
17
19
2
7
LVDS_CLKAP
LVDS_YAP3
GND
8
9
10
11
12
13
14
15
16
17
18
19
20
FP_BKLT
LVDS_YAM0
GND
4
LVDS_YAM1
GND
6
8
LVDS_YAM2
GND
10
12
14
16
18
20
LVDS_CLKAM
LVDS_YAM3
FP_VCC
LVDS_BKLTCTL
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Table 71 SVGA — 15-Pin High Density D Connector (female)
IDAN Pin #
Signal
Function
CPU Pin #
1
2
Red
Red Analog Output
Green Analog Output
Blue Analog Output
Reserved
4
6
Green
Blue
3
8
4
Reserved
GND
—
9
5
Ground
6
GND
Ground
9
7
GND
Ground
9
8
GND
Ground
10
7
9
+5 V
+ 5 Volts
10
11
12
13
14
15
GND
Ground
10
—
5
Reserved
DDC Data
HSYNC
VSYNC
DDC CLK
Reserved
Monitor data
Horizontal Sync
Vertical Sync
Monitor Clock
2
1
3
BDM-610000049 Rev G
Appendix C: IDAN™ Dimensions and Pinout 101
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Table 72 USB — 9-Pin D Connector (male)
IDAN Pin #
Signal
Function
Mode
1
2
3
4
5
6
7
8
9
VCC1
Data USB1–
Data USB1+
GND
+5 V to USB1
USB1 Data–
USB1 Data+
Ground
output
input/output
input/output
—
GND
Ground
—
VCC2
+5 V to USB2
USB2 Data–
USB2 Data+
Ground
output
Data USB2–
Data USB2+
GND
input/output
input/output
—
Table 73 Ethernet — 9-Pin D Connector (female)
IDAN Pin #
10Base-T
Signal
CPU Pin #
Adapter Pin #
1
2
3
4
5
6
7
8
9
1
2
Receive +
Reserved
Transmit +
Reserved
Ground
1
3
5
7
9
2
4
6
8
3
4
5
6
Receive -
Reserved
Transmit -
Reserved
7
8
—
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Table 74 Audio — 9-Pin D Connector (female)
IDAN Pin #
Signal
MIC_VREF
CPU Pin #
5
4
3
2
2
9
8
7
6
1
1
3
GND
LINE_IN_GND
GND
5
7
GND
9
MIC_IN
2
LINE_IN_LEFT
LINE_IN_RIGHT
OUTPUT_LEFT
OUTPUT_RIGHT
4
6
8
10
BDM-610000049 Rev G
Appendix C: IDAN™ Dimensions and Pinout 103
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IDAN Dimensions and Connectors (BRG version only)
This section describes some of the primary physical differences between the standard dual height IDAN
cpuModule and the IDAN cpuModule that comes with a PCI to ISA bridge module (“BRG” version).
6-pin mini-DIN (female)
9-pin D (male)
module P/N: Adam Tech MDE006W
mating P/N: Adam Tech MDP006
module P/N: Adam Tech DE09PD
mating P/N: Adam Tech DE09SD
FRONT
25-pin D (female)
module P/N: Adam Tech DB25SD
mating P/N: Adam Tech DB25PD
9-pin D (female)
module P/N: Adam Tech DE09SD
mating P/N: Adam Tech DE09PD
15-pin high-density D (female)
module P/N: Adam Tech HDT15SD
mating P/N: Adam Tech HDT15PD
20-pin mini D (female)
module P/N: 3M 10220-6212VC
mating P/N: 3M 10120-3000VE
REAR
37-pin high-density D (female)
9-pin D (male)
module P/N: Adam Tech HDT37SD
mating P/N: Adam Tech HDT37PD
module P/N: Adam Tech DE09PD
mating P/N: Adam Tech DE09SD
Figure 10 IDAN-CMX158886-BRG Connectors1
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External I/O Connections (BRG version only)
An additional connector is added to the IDAN PCI to ISA bridge configuration to allow additional digital I/O
signals to be accessible from outside the IDAN frame. The pinout for this connection is shown in the table below.
Table 75 aDIO — 37-Pin D Connector (female)
BRG Pin #
Function
IDAN Pin #
1
P1-0
GND
P1-1
1
2
20
2
3
4
GND
P1-2
21
3
5
6
GND
P1-3
22
4
7
8
GND
P1-4
23
5
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
GND
P1-5
24
6
GND
P1-6
25
7
GND
P1-7
26
8
GND
P1-Strobe
GND
P2-0
27
9
28
10
29
11
30
12
31
13
32
14
33
15
34
16
35
17
GND
P2-1
GND
P2-2
GND
P2-3
GND
P2-4
GND
P2-5
GND
P2-6
GND
P2-7
BDM-610000049 Rev G
Appendix C: IDAN™ Dimensions and Pinout 105
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BRG Pin #
Function
IDAN Pin #
34
35
36
37
38
39
40
GND
P2-Strobe
GND
36
18
37
+5 Volts Fused @ 2A
GND
19
N/C
N/C
N/C
GND
GND
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Appendix D Additional Information
Application Notes
RTD offers many application notes that provide assistance with the unique feature set of the CMX158886
cpuModule. For the latest application notes, refer to the RTD website.
Drivers and Example Programs
To obtain the latest versions of drivers and example programs for this cpuModule, refer to the RTD website.
Interrupt Programming
For more information about interrupts and writing interrupt service routines, refer to the following book:
Interrupt-Driven PC System Design
by Joseph McGivern
ISBN: 0929392507
Serial Port Programming
For more information about programming serial port UARTs, consult the following book:
Serial Communications Developer's Guide
by Mark Nielson
ISBN: 0764545701
PC/104 and PC/104-Plus Specifications
A copy of the latest PC/104 and PC/104-Plus specifications can be found on the webpage for the PC/104
Embedded Consortium:
http://www.pc104.org
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Appendix E
Limited Warranty
RTD Embedded Technologies, Inc. warrants the hardware and software products it manufactures and produces
to be free from defects in materials and workmanship for one year following the date of shipment from RTD
Embedded Technologies, Inc. This warranty is limited to the original purchaser of product and is not transferable.
During the one year warranty period, RTD Embedded Technologies will repair or replace, at its option, any
defective products or parts at no additional charge, provided that the product is returned, shipping prepaid, to
RTD Embedded Technologies. All replaced parts and products become the property of RTD Embedded
Technologies. Before returning any product for repair, customers are required to contact the factory for a Return
Material Authorization number.
This limited warranty does not extend to any products which have been damaged as a result of accident, misuse,
abuse (such as: use of incorrect input voltages, improper or insufficient ventilation, failure to follow the
operating instructions that are provided by RTD Embedded Technologies, “acts of god” or other contingencies
beyond the control of RTD Embedded Technologies), or as a result of service or modification by anyone other
than RTD Embedded Technologies. Except as expressly set forth above, no other warranties are expressed or
implied, including, but not limited to, any implied warranties of merchantability and fitness for a particular
purpose, and RTD Embedded Technologies expressly disclaims all warranties not stated herein. All implied
warranties, including implied warranties for merchantability and fitness for a particular purpose, are limited to
the duration of this warranty. In the event the product is not free from defects as warranted above, the
purchaser's sole remedy shall be repair or replacement as provided above. Under no circumstances will RTD
Embedded Technologies be liable to the purchaser or any user for any damages, including any incidental or
consequential damages, expenses, lost profits, lost savings, or other damages arising out of the use or inability to
use the product.
Some states do not allow the exclusion or limitation of incidental or consequential damages for consumer
products, and some states do not allow limitations on how long an implied warranty lasts, so the above
limitations or exclusions may not apply to you.
This warranty gives you specific legal rights, and you may also have other rights which vary from state to state.
RTD Embedded Technologies, Inc.
103 Innovation Blvd.
State College PA 16803-0906
USA
Website: www.rtd.com
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