HP Hewlett Packard Computer Hardware VL 5 xxx Series 5 User Manual

Technical Reference Manual

Hardware and BIOS

HP Vectra VL 5/xxx Series 5

and XA 5/xxx PC

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Preface

This manual is a technical reference and BIOS document for engineers and

technicians providing system level support. It is assumed that the reader

possesses a detailed understanding of AT-compatible microprocessor

functions and digital addressing techniques.

Technical information that is readily available from other sources, such as

manufacturer’s proprietary publications, has not been reproduced.

This manual contains summary information only. For additional reference

material, refer to the bibliography, on the next page.

Conventions

The following conventions are used throughout this manual to identify

specific numeric elements:

❒ Hexadecimal numbers are identified by a lower case h.

For example, 0FFFFFFFh or 32F5h

❒ Binary numbers and bit patterns are identified by a lower case b.

For example, 1101b or 10011011b

iii

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Bibliography

❒ HP Vectra VL 5/xxx Series 5 User’s Guide (D4550-90001).

❒ HP Vectra VL 5/xxx Series 5 Minitower User’s Guide (D4570-90001).

❒ HP Vectra XA 5/xxx User’s Guide (D3984-90001).

❒ HP Vectra XA 5/xxx Minitower User’s Guide (D3985-90001).

❒ HP Vectra VL 5/xxx Series 5 PC Familiarization Guide (D4550-90901).

❒ HP Vectra XA 5/xxx PC Familiarization Guide (D3984-90901).

❒ HP Network Administrator’s Guide (online).

❒ HP Vectra Accessories Service Handbook - 7th edition

(5965-4074).

❒ HP Vectra PC Service Handbook (Volume 1) - 11th edition

(5965-4075).

❒ HP Support Assistant CD-ROM (by subscription).

The following Intel® publications provide more detailed information:

❒ Pentium Microprocessor Data Sheet (241595-002)

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Contents

Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii

Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii

Bibliography. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iv

1 System Overview

Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Desktop Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Minitower Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Plan view of the Chassis Base of the Desktop Package . . . . . . . . . . . . . 12

Specifications and Characteristic Data . . . . . . . . . . . . . . . . . . . . . . . 13

Status Panel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Physical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Environmental Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Electrical Specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Where to Find the Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2 System Board

System Board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Architectural View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Chip-Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

PL/PCI Bridge Chip (82439HX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

PCI/ISA Bridge Chip (82371SB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Super I/O Chip (37C932) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Backplane boards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

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Contents

Devices on the Processor-Local Bus. . . . . . . . . . . . . . . . . . . . . . . . . . 30

The Intel Pentium Microprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Cache Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Main Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Devices on the PCI Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Integrated Drive Electronics (IDE). . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Universal Serial Bus (USB) Controller . . . . . . . . . . . . . . . . . . . . . . . . . .

Devices on the ISA Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Super I/O Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Little Ben . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Other PCI and ISA Accessory Devices Under Plug and Play. . . . . . . . .

3 Interface Devices and Mass-Storage Drives

S3 Trio 64V2 Graphics Controller Chip. . . . . . . . . . . . . . . . . . . . . . . . 42

Video Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Video Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Available Video Resolutions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Troubleshooting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Matrox MGA Millennium Graphics Controller Board. . . . . . . . . . . . 48

Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Video Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Available Video Resolutions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Video BIOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

HP Ethernet 10/100 BaseT Network Board . . . . . . . . . . . . . . . . . . . . 52

HP Enhanced Ethernet Network Board . . . . . . . . . . . . . . . . . . . . . . . 54

Audio Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

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Contents

Mass-Storage Drives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Hard Disk Drives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Flexible Disk Drives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

CD-ROM Drives. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Connectors and Sockets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

4 Summary of the HP/Phoenix BIOS

HP/Phoenix BIOS Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Setup Program. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Main Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Configuration Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Security Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Power Menu. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Power Saving and Ergonometry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Power-On from Space-Bar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Soft Power Down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

HP Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Remote Power-On (RPO). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Advanced Power Management (APM). . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Desktop Management Interface (DMI) . . . . . . . . . . . . . . . . . . . . . . . . . . 78

HP Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

BIOS Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

System Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Product Identification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

HP I/O Port Map (I/O Addresses Used by the System). . . . . . . . . . . . . . 80

vii

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Contents

5 Power-On Self-Test and Error Messages

Order in Which the Tests are Performed . . . . . . . . . . . . . . . . . . . . . . 86

Error Message Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Beep Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Lights on the Status Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

viii

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System Overview

This manual describes the HP Vectra VL 5/xxx Series 5 and XA 5/xxx PC,

and provides detailed system specifications.

This chapter introduces the external features, and lists the specifications

and characteristic data of the system. It also summarizes the documentation

which is available.

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1 System Overview

Package

Desktop Package

Front view of VL

Front logo does

not show processor speed

or series information

Product information

Model VL 5/200 series 5

Prod: D4570A #ABU

S/N: FR63412345

Wty: WBK@

Sup: SAB@

appears on a label on

the lower front recess or

the right hand side panel

Rear view of XA

Network connectors:

100 BaseT supports Remote Wake-Up

(RWU) only.

10 BaseT supports Remote Power-On

(RPO) as well as RWU.

Front label does not show processor

speed or series information. Instead

this information appears on a label

on the lower front recess (desktop

models) or on the right hand side

panel (minitower models).

2 ✕USB

Inside view of VL

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1 System Overview

Package

Minitower Package

Rear view of XA

Line

Mic

Line

Out

Spkr

Out

Front label does not show processor

speed or series information. Instead

this information appears on a label

on the right hand side panel

Model XA 5/200

Wty: WBK@

Sup: SAB@

Prod: D3993A #ABA

S/N: FR63498765

Voltage selection

Power connector

Inside view of VL

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1 System Overview

Package

Plan view of the Chassis Base of the Desktop Package

The above illustrations shows a plan view of the desktop model, seen from

above. All dimensions are in millimeters.

The mounting holes for the second hard disk (95.20✕44.45 mm), and those

for mounting the computer on a solid surface (275.00✕210.00 mm), are

indicated.

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1 System Overview

Specifications and Characteristic Data

Status Panel

RESET

HP Vectra XA 5/xxx

Cover lock on back panel

HP Vectra VL 5/xxx MT or

HP Vectra XA 5/xxx MT

HP Vectra VL 5/xxx

Cover lock on back panel

Multimedia control panel on front

Physical Characteristics

System Processing Unit

Desktop

Minitower

Weight

9 kg (20 lbs)

15 kg (33 lbs)

Dimensions

39 cm (D) by 42 cm (W) by 12.5 cm (H)

15.3 inches by 16.5 inches by 4.9 inches

40.5 cm (D) by 21 cm (W) by 41.5 cm (H)

16.0 inches by 8.3 inches by 16.3 inches

Footprint

0.17 m (1.8 sq ft)

0.085 m (0.91 sq ft)

Keyboard

Flat

464 mm (W) by 178 mm (D) by 33 mm (H) (18.3 inches by 7 inches by 1.3 inches)

464 mm (W) by 178 mm (D) by 51 mm (H) (18.3 inches by 7 inches by 2 inches)

Standing

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1 System Overview

Specifications and Characteristic Data

Environmental Specification

System Processing Unit with a Hard Disk

Typical power consumption

Acoustic noise emission

30 W to 40 W (before installing any customer-specific accessories)

less than 40 dB in the workplace under normal conditions as

defined by DIN 45635 T.19 and ISO 7779

Operating temperature

Recommended operating temperature

Storage temperature

Over temperature shutdown

Operating humidity

+5°C to +40°C

(+40°F to 104° F)

(+59°F to +104°F)

(-40°F to +158°F)

(+122°F)

+15°C to +40°C

-40°C to +70°C

+50°C

15% to 80% RH (non-condensing)

8% to 80% RH (non-condensing)

3100 m max

Storage humidity

Operating altitude

(10000 ft max)

(15000 ft max)

Storage altitude

4600 m max

Operating temperature and humidity ranges may vary depending upon the

mass storage devices installed. High humidity levels can cause improper

operation of disk drives. Low humidity levels can aggravate static electricity

problems and cause excessive wear of the disk surface.

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1 System Overview

Specifications and Characteristic Data

Electrical Specification

For the desktop models:

Limit per PCI

Accessory

Slot

Limit per ISA

Accessory

Slot

Limit for the Power

Parameter

Notes

Supply

Input voltage

100-127, 200-240 Vac

Auto-ranging

—

Input voltage range

Input current (max)

Input power (max)

90-264 Vac

3 A

150 W

Input power (typical )

< 44 W

< 29 W

< 24 W

< 5 W

Fully-on mode

Standby mode

Suspend mode

Off (but plugged)

Input frequency

45 Hz to 66 Hz

100 W (continuous)

13.5 A

—

25 W (max)

4.5 A

—

7 W (max)

4.5 A

Available power

Max current at +5 V

Max current at +3.3 V

Together, these

two must not

exceed 13.5 A

6 A

—

Max current at -5 V

Max current at +12 V

Max current at -12 V

0.1 A

4.5 A

—

0.1 A

0.5 A

0.3 A

1.5 A

0.1 A

0.3 A

Input power (when

turned Off)

Less than 5 W

When the PC is Off, but still

plugged in, an independent mini

power supply keeps the network

board active enough to watch out

for the “Remote Power-On” (RPO)

signal (see page 71 for

Available power

(when Off)

0.25 W

0.05 A

Available current

(when Off)

description)

Dependant on operating system and PC configuration

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1 System Overview

Specifications and Characteristic Data

For the minitower models:

Limit per PCI

Accessory

Slot

Limit per ISA

Accessory

Slot

Limit for the Power

Supply

Parameter

Notes

Input voltage

100-127

Vac

200-240 Switch selectable

Vac

Input voltage range

90-140

Vac

180-264

Vac

Input current (max)

Input power (max)

5 A

3 A

200 W

< 44 W

Input power (typical )

Fully-on mode

Standby mode

Suspend mode

Off (but plugged)

—

< 29 W

< 24 W

< 5 W

Input frequency

45 Hz to 66 Hz

160 W (continuous)

20 A

Available power

25 W (max)

4.5 A

7 W (max)

4.5 A

Max current at +5 V

Max current at +3.3 V

Together, these

two must not

exceed 20 A

12 A

—

Max current at -5 V

Max current at +12 V

Max current at -12 V

0.2 A

4.4 A

0.5 A

0.05 A

—

1.5 A

0.1 A

—

0.1 A

0.5 A

0.3 A

—

Max current at +5 Vst

Dependant on operating system and PC configuration

When the computer is turned off, but left plugged in at the mains, the power

consumption falls below 5 watts, but is not zero. A small trickle current

continues to flow, supplying power to the CMOS memory, considerably

extending the lifetime of the on-board battery.

If the computer is completely unplugged from the mains, the real time clock

continues to operate, from the charge stored in the battery.

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1 System Overview

Documentation

The table below summarizes the availability of documentation that is

appropriate to the HP Vectra VL and XA 5/xxx PCs. Three dots, ‘...’, are

used to indicate ‘VL’ or ‘XA’, as appropriate. Only selected publications are

available on paper. Most are available as printable files from the HP division

support servers, and as viewable files (which can also be printed) on the

HP Support Assistant CD-ROM.

Division Support Server

Support Assistant CD-ROM

Paper-based

Line of HP Vectra 6/xxx:

HP Vectra ... 5/xxx User’s Guide

PDF file

DT: D4550A

MT: D4570A

D4550-90901

DT: D3984A

MT: D3985A

D3984-90901

HP Vectra ... 5/xxx

Familiarization Guide

PDF file

HP Vectra VL and XA 5/xxx

Technical Reference Manual

PDF file

HP Vectra PC Service

Handbook (Vol 1, 11th Edition)

5965-4075

5965-4074

HP Vectra Accessory Service

Handbook (7th Edition)

PDF file

Network Administrators Guide

Each PDF file (portable document format) can be viewed on the screen by

opening the file with Acrobat Reader. You can use the page-up, page-down,

goto page, search string functions to read the document on the screen.

(Note, though, that there is difference between the page number that is

printed on the page, and the page number that Acrobat Reader indicates,

because of the presence of the front matter pages). To print the document,

press Ctrl+P whilst you have the document on the screen.

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1 System Overview

Documentation

Where to Find the Information

The following table summarizes the availability of information within the

HP Vectra VL and XA 5/xxx PC documentation set.

Technical

Reference

Manual

Familiarization

Guide

Service

Handbook

User Guide

User Online

Introducing the computer

Product features

Key features

Exploring

New features

Exploded view

Key features

Parts list

Product model numbers

Product range

CPL dates

Using the computer

Connecting cables and

turning on

Keyboard, mouse, display,

network, printer, power

Finding on-line

information

Finding READ.MEs and on-

line documentation

Environmental

Working in

comfort

System overview

Formal documents

Software license agreement S/w license

agreement

Warranty information

Upgrading the computer

Opening the computer

Supported accessories

Replacing accessories

Configuring devices

Full details

Some part number details

How to install

Full PN details

New procedures

Configuring

peripherals

Problem fixes

Key fields

Fields and their options

within Setup

Repairing the computer

New symptoms

Detailed

Troubleshooting

Technical information

System board

Basic

Service notes

Advanced

Jumpers, switches

and connectors

Jumpers, switches and

connectors

Jumpers,switches Jumpers,

and connectors

switches and

connectors

How to replace

Upgrading

Chip-set details

Technical details

BIOS

Basic details

Memory maps

Order of tests

Power-On Self-Test

routines (POST)

Key error codes and

suggestions for corrective

action

Complete list

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System Board

The next chapter describes the video, disk, audio and network devices

which are supplied with the various models of the computer.

This chapter describes the components of the system board, taking in turn

the components of the Processor-Local Bus, the Peripheral Component

Interconnect (PCI) bus and the Industry Standard Architecture (ISA) bus.

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2 System Board

System Board

HP ASIC

Only on some

VL models

280 mm

The video memory, video memory upgrade sockets, graphics controller and

display connector are not loaded on any models that are supplied with a

Matrox MGA Millennium board in a PCI accessories slot. This includes all

models of the HP Vectra XA 5/xxx PC (desktop and minitower), and some

models of the HP Vectra VL 5/xxx Series 5 PC (desktop and minitower).

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2 System Board

Architectural View

ISA Bus

(16 bit, 7.5/8.33 MHz)

Processor-Local Bus

(64 bit, 60/66 MHz)

PCI Bus

(32 bit, 30/33 MHz)

82371 SB

PCI/ISA Bridge (PIIX3)

Pentium

Processor

Interrupt

controller

DMA

controller

Graphics

Controller

Main

Memory

PCI bus

ISA bus

interface

2✕USB

2✕IDE

controller

Hard

disk

82439 HX

PL/PCI Bridge (TXC)

Memory

controller

Data path

Serial

EEPROM

Little Ben

(HP ASIC)

PL bus

PCI bus

interface

Cache

controller

37C932

Super I/O

Keyboard

Mouse

controller

Parallel

ISA bus

Level-

Two

Cache

controller

interface

2✕serial

FDD

controller

Controller

Flexible

disk

System

ROM

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2 System Board

Chip-Set

The chip-set comprises three chips. These interface between the three main

buses (the Processor-Local bus, the PCI bus and the ISA bus).

• The TXC chip (82439HX) is a combined PL/PCI bridge and cache

controller and main memory controller and PCI-to-PL bus data path.

• The PIIX3 chip (82371SB) is a combined PCI/ISA bridge and IDE

controller and USB controller.

• The Super I/O chip (37C932) is a combined serial interface and parallel

interface and keyboard controller and mouse controller and flexible

disk drive controller.

The TXC and PIIX3 chips are PCI 2.1 compliant, and provide for PCI

Concurrency. Concurrent data transfers that do not contest for the same

resources (such as processor to memory concurrent with PCI peer to peer,

or processor to ISA device concurrent with PCI device to memory) are

allowed to interleave their transfers more finely than with previous chip

sets. This has little effect on the throughput of the system, but results in a

greatly reduced worst-case latency. This leads to a much smoother

operation of video capture, MPEG clips and audio clips.

To find out more about how this is achieved, the reader is referred to the

Intel documentation on the 82430HX chip set. Relevant key words include:

the multi-transaction timer (MTT), the passive release mechanism, and

the PCI delayed transaction mechanism.

PL/PCI Bridge Chip (82439HX)

The bridge between the Processor Local Bus (PL Bus) and the PCI Bus is

encapsulated in a 324 pin ball grid array (BGA) package.

PL Bus Interface

The TXC chip monitors each cycle that is initiated by the processor, and

forwards those to the PCI bus that are not targeted at the local memory. It

translates PL bus cycles into PCI bus cycles.

The chip supports the SMM mode of the Pentium processor, the CPU stop

clock hardware function, and the keyboard lock function. These are used by

the LittleBen chip, as described on page 73.

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2 System Board

Chip-Set

PCI Bus Interface

Sequential PL-to-PCI memory write cycles are translated into PCI zero wait

state burst cycles. The maximum PCI burst transfer can be from 256 bytes to

4 KB. The chip supports advanced snooping for PCI master bursting, and

provides a pre-fetch mechanism dedicated for IDE read.

The PCI arbiter supports PCI bus arbitration for up to four masters using a

rotating priority mechanism. Its hidden arbitration scheme minimizes

arbitration overhead.

Data Path

Storage elements are provided for bidirectional data buffering among the 64-

bit PL data bus, the 64/32-bit memory data bus, and the 32-bit PCI address/

data bus.

There are three FIFO (first-in first-out) queues, and one read buffer for the

bridges of the PL, PCI, and Memory buses. This buffering is used, partly, to

smooth the differences in bandwidths between the three buses, thereby

improving the overall system performance. During bus operations between

the PL, PCI and Memory buses, the chip receives control signals from the

TXC, performs functions such as latching data, forwarding data to

destination bus, data assemble and disassemble.

Error correcting code (ECC) and parity bits are generated for memory

writes, and optional parity checking for memory reads. This operation

always sustains zero wait performance on PL-to-Memory, and always

streams zero wait performance on PCI-to-Memory and Memory-to-PCI.

Whilst accesses to the local memory are in progress, whether it be from the

PL or PCI bus, the TXC maintains control of the secondary cache, DRAMs,

and the datapath.

Level-2 Cache Memory This unit controls the L2 cache memory, adopting a write back policy, in a

direct mapped organization. An 8-bit tag is used to allow the lowermost

64 MB of main memory to be cached (if more than 64 MB of main memory is

installed, accesses to the uppermost regions will be made directly to the main

memory modules, and not via the cache memory mechanism). When a

512 KB cache memory module is installed, the chip set allows provision for

an 11-bit tag to be used to allow 512 MB of main memory to be cached, but

this facility has not been enabled in the HP BIOS. More details on the use of

HP cache memory are given on page 32.

Controller

The cache memory line width is 32-bytes (256-bits), four times the width of

the Processor-Local data bus. Reads and writes always involve a full cache

line, and so require four back-to-back cycles on the bus. Since they involve

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2 System Board

Chip-Set

accesses to related addresses, they do not need four independent accesses

to main memory, but can be organized as a pipelined burst. The second,

third and fourth cycles in each burst require less time to complete than the

first. This is because the first cycle includes the addressing phase and

memory pre-charge timing. The read and write access timing has the

pattern 3-1-1-1. However, the timing for 64-byte burst reads can be even

better than this (3-1-1-1,2-1-1-1 for a dual bank back-to-back burst read¹,

and 3-1-1-1,1-1-1-1 for a single bank back-to-back burst read²) provided

that the main memory banks have been filled contiguously.

There are two programmable non-cacheable regions, with an option to

disable local memory in these regions. A 64 KB to 1 MB cache summary is

provided.

Main Memory Controller The main memory controller supports up to 512 MB of main memory

(dynamic random access memory, DRAM), arranged in banks of any

mixture of memory capacities, provided that each bank contains a pair of

identical single interline memory modules (SIMMs). The HP Vectra VL 5/

xxx Series 5 and XA 5/xxx PCs have provision for three banks. With the

32 MB module from HP, this gives a total capacity of 192 MB. With a future

64 MB module from HP, it will give a total capacity of 384 MB.

In the case of 66 MHz PL bus operation, memory accesses have a timing

pattern of 5-2-2-2 for a page-hit. This degrades to 8-2-2-2 for a row-miss,

and to 11-2-2-2 for a page-miss. When the banks have been filled in an

arbitrary order, back-to-back burst reads keep to the 5-2-2-2,5-2-2-2 timing

pattern. When the banks have been filled contiguously (bank A, then bank

B, then bank C), back-to-back burst reads are improved to a 5-2-2-2,3-2-2-2

timing pattern.

The controller supports relocation of system management memory. It

supports a read cycle power saving mode, and a CAS before RAS Intelligent

Refresh mode of operation, with a CAS# driving current that is

programmable.

The controller is fully configurable for the characteristics of the shadow

RAM (640 KB to 1 MB). It supports concurrent write back. To implement

the optional error correcting code (ECC) or parity checking, 36-bit SIMMs

must be installed exclusively (see page 33 for more details).

1. As used for the HP 512 KB cache memory module.

2. As used for the HP 256 KB cache memory module.

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2 System Board

Chip-Set

PCI/ISA Bridge Chip (82371SB)

This chip is encapsulated in a 208 pin plastic quad flat pack (PQFP)

package.

PCI Bus Interface

ISA Bus Interface

This part of the chip performs PCI-to-ISA, and ISA-to-PCI bus cycle

translation. It supports the Plug-and-Play mechanism.

As well as accepting cycles from the PCI bus interface, and translating them

for the ISA bus, the ISA bus interface also requests the PCI master bridge to

generate PCI cycles on behalf of a DMA or ISA master. The ISA bus interface

contains a standard ISA bus controller and data buffering logic. It can directly

support six ISA slots without external data or address buffering.

IDE Controller

The PCI master/slave IDE controller, supporting four devices, two on each of

two channels, is described on page 34.

USB Controller

DMA Controller

The PCI USB controller, supporting two connectors, is described on page 36.

The seven channel DMA controller incorporates the functionality of two

82C37 DMA controllers. Channels 0 to 3 are for 8-bit DMA devices, while

channels 5 to 7 are for 16-bit devices (see page 82). The channels can be

programmed for any of the four transfer modes: the three active modes

(single, demand, block), can perform three different types of transfer: read,

write and verify. The address generation circuitry can only support a 24-bit

address for DMA devices.

Interrupt Controller

Counter / Timer

The sixteen channel interrupt controller incorporates the functionality of

two 82C59 interrupt controllers. The two controllers are cascaded, giving 14

external and two internal interrupt sources (see page 82).

The chip contains a three-channel 82C54 counter/timer. The counters use a

division of the 14.31818 MHz OSC input as the clock source.

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2 System Board

Chip-Set

Super I/O Chip (37C932)

The Super I/O chip (FDC37C932) is contained within a 160-pin PQFP

package. The chip provides the control for the following devices.

Function

Logical device number

Flexible disk controller

Parallel port controller

UART1 controller

UART2 controller

RTC

Keyboard controller

Mouse controller

General purpose I/O (GPIO)

Serial / parallel

communications ports

The two 9-pin serial ports (whose pin layouts are depicted on page 58)

support RS-232-C and are buffered by 16550 UARTs, with 16 Byte FIFOs.

They can be programmed as COM1, COM2, COM3, COM4, or disabled.

The 25-pin parallel port (also depicted on page 58) is Centronics

compatible, supporting IEEE 1284. It can be programmed as LPT1, LPT2, or

disabled. It can operate the four modes:

❒ Standard mode (PC/XT, PC/AT, and PS/2 compatible).

❒ Bidirectional mode (PC/XT, PC/AT, and PS/2 compatible).

❒ Enhanced mode (enhanced parallel port, EPP, compatible).

❒ High speed mode (MS/HP extended capabilities port, ECP, compatible).

FDC

The integrated flexible drive controller (FDC) supports any combination of

two from the following: tape drives, 3.5-inch flexible disk drives, 5.25-inch

flexible disk drives. It is software and register compatible with the 82077AA,

and 100% IBM compatible. It has an A and B drive-swapping capability and a

non-burst DMA option.

Keyboard and Mouse

Controller

The computer has an 8042-based keyboard and mouse controller. The

connector pin layouts are shown on page 58. The Windows 95 keyboard is

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2 System Board

Chip-Set

described on page 37.

RTC

The real-time clock (RTC) is 146818A-compatible. With an accuracy of

20 ppm (parts per million). The configuration RAM is implemented as 256

bytes of CMOS memory.

Serial EEPROM

This is the non-volatile memory which holds the default values for the CMOS

memory (in the event of battery failure, or the user pressing

in Setup).

General Purpose I/O

There are several general purpose I/O pins. Some of these are used on the

HP Vectra to sense the current settings of system board switches (page 31

and page 39).

Description

Reserved (HP security from Little Ben IRQ)

GPIO number

GPIO10

GPIO11

GPIO12

GPIO13

GPIO14

GPIO15

GPIO16

GPIO17

GPIO20

GPIO21

GPIO22

GPIO23

GPIO24

GPIO25

Ratio of processor frequency to processor local bus frequency (as per SW-4)

Auto soft lock

Backplane identification BPID0 (always =0); (see BPID1, below)

Host bus frequency selection, as indicated by SW-1

Host bus frequency selection, as indicated by SW-2

Serial EEPROM clear (as per SW-6)

Ratio of processor frequency to processor local bus frequency (as per SW-3)

Backplane identification BPID1 (desktop=1, minitower=0)

Serial EEPROM data out

Serial EEPROM data in

Serial EEPROM clock

Serial EEPROM chip select

Reserved (for fax or general purpose light)

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2 System Board

Backplane boards

Desktop (front view)

Desktop (rear view)

Minitower (top view)

PCI Slot #3

(J1)

PCI Slot #2

(J3)

PCI Slot #1

(J4)

Half length PCI

(proprietary network)

slot

PCI Slot #4

(J12)

PCI Slot #3

(J5)

PCI Slot #2

(J11)

PCI Slot #1

(J6)

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2 System Board

Backplane boards

Desktop

Minitower

Occupied in

base models

Occupied in

top models

Occupied in

top models

Total

base models

PCI slots (normal)

1✕Graphics

1✕Network

Proprietary PCI slots (short length, network)

1✕Network

—

PCI/ISA combination slots

—

PCI/ISA (short length) combination slots

—

1✕Audio

ISA slots (full length)

—

ISA slots (short length)

1✕Audio

—

HP proprietary slot on the rear side of the desktop back plane board

To accommodate ISA boards up to a maximum length of 16 cm (6.3 inches)

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2 System Board

Devices on the Processor-Local Bus

The Intel Pentium Microprocessor

The Pentium processor is packaged in a pin-grid-array (PGA), and is

seated on the system board in a zero-insertion-force (ZIF) socket 7. Only

upgrades that are pin compatible with the original processor, manufactured

by Intel, are supported.

P54CS chips working at 133 and 150 MHz (along with P54C chips working at

75, 90, 100 MHz and new versions of the 120 MHz chip) require a 3.3 V

supply. A passive shorting block is sufficient to connect the regulated 3.3 V

output of the power supply directly to the Pentium processor.

P54CS chips working at 166 and 200 MHz require between 3.45 and 3.60 V.

They need an VRE voltage regulator module (VRM), in which the voltage

is actively derived from the 3.3 V, 5 V and 0 V outlets of the power supply.

P55C chips, with MMX technology, require two voltage supplies: 3.3 V for

the input and output buffers, and 2.8 V for the core logic. It requires an

active VRM that is specifically designed for use with the MMX processor.

This VRM can be identified by the inscription “2.8 V” marked on the board.

Any thermal contact material between the processor and the heat-sink must

not be removed or disturbed. The cooling needs of the processor are critical.

MMX Technology

The instruction set of the MMX processor includes 57 new instructions, four

new 64-bit data formats (depicted below) and eight new 64-bit MMX

registers. As well as the pipelined parallelism of the traditional Pentium

architecture, MMX is capable of SIMD parallelism (single-instruction/

multiple-data). Instead of combining a pair of operands to produce a single

result, each instruction is able to gang each operation over a large number of

pairs of operands, so producing a large number of results concurrently. This

type of parallelism is particularly useful when processing large vectors and

arrays of data (in graphics and audio processing, for example).

Quadword

64 bit

Packed double word

Packed word

32 bit

16 bit

Packed byte

8 bit

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2 System Board

Devices on the Processor-Local Bus

Bus Frequencies

The location of the system board switches is shown in the diagram on page

20. Five of these switches (SW-1,2,3,4 and 7) determine the working

frequencies of the PC, and the three frequency multipliers (M1, M2 and M3),

as summarized in the table below. The uses of the other switches are

summarized on page 39.

There is a 14.318 MHz crystal oscillator on the system board whose

frequency is multiplied, by a phase locked loop, to 50, 60 or 66 MHz for the

Processor Local (PL) bus, according to the settings of SW-1 and SW-2. This

is further multiplied, to the processor core frequency, by a factor of 1.5, 2,

2.5 or 3, according to the settings of SW-3 and SW-4. The PCI bus works at

half the frequency of the PL bus. The ISA bus works at a third or a quarter of

the frequency of the PCI bus, according to the setting of SW-7.

You will need to change these switches when you replace the original system

board, for a repair, so as to match the processor. You will not need to change

the switches if you upgrade the original processor using the correct Intel

Overdrive. It is not recommended to upgrade to another processor that may

have different voltage requirements.

PL Frequency

Multiplier M1 M3

Processor

PL Bus

Frequency

PCI Bus

Frequency

ISA Bus

Frequency

VRM

Frequency

SW-1 SW-2 SW-8 SW-3 SW-4 SW-7

Closed Closed Closed Open Open Open

Closed Open Closed Open Open Closed

Open Closed Closed Open Open Closed

Closed Open Closed Closed Open Closed

Open Closed Closed Closed Open Closed

Closed Open Closed Closed Closed Closed

Open Closed Closed Closed Closed Closed

Open Closed Closed Open Closed Closed

Open Closed Open Open Open Closed

75 MHz

90 MHz

1.5

50 MHz

60 MHz

66 MHz

60 MHz

66 MHz

60 MHz

66 MHz

25 MHz

30 MHz

33 MHz

30 MHz

33 MHz

30 MHz

33 MHz

8.33 MHz

7.5 MHz

Vcc

100 MHz

120 MHz

8.25 MHz

7.5 MHz

Vcc,Vre

Vcc

133 MHz

8.25 MHz

7.5 MHz

150 MHz 2.5

166 MHz 2.5

Vcc,Vmmx

Vre,Vmmx

Vmmx

8.25 MHz

200 MHz

233 MHz

3.5

Where there is a choice indicated, install the one that is appropriate for the given processor.

These processors are not available for these models of HP Vectra PC at the time of printing. This

information is provided for completeness only.

The computer may execute erratically, if at all, or may overheat, if it is

configured to operate at a higher processor speed than the processor is

capable of supporting. This can cause damage to the computer.

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2 System Board

Devices on the Processor-Local Bus

Setting the switches to operate at a slower speed, than the processor is

capable of supporting, can still cause erratic behavior in some case, and

would reduce the instruction throughput in others.

Cache Memory

The computer supports two levels of cache memory, each with a 32-byte line

width. The Level-1 (L1) cache memory is fabricated on the processor chip.

The Level-2 (L2) cache memory is a slower module on the system board.

Each acts as temporary storage for data and instructions from the main

memory. Since the system is likely to use the same, or adjacent, data several

times, it is faster to get it from the on-chip or on-board cache memory than

from the main memory.

The L1 cache memory is divided into two separate banks: an L1 I-cache for

instruction words, and an L1 D-cache for data words. On a P54 processor,

each has a capacity of 8 KB; on an MMX (P55) processor, each has a

capacity of 16 KB.

The L2 cache memory is controlled by the PL/PCI bridge chip in the system

board chip-set (see page 23 for a description, and details of timing patterns

and tag size). A single HP cache memory module consists of 256 KB or

512 KB of direct mapped, write-back, synchronous pipelined burst, 8.5 ns

static random access memory (SRAM). The chip-set does not support

asynchronous or burst SRAM modules.

Main Memory

There are six main memory module sockets, arranged in three banks

(A to C). One bank is already occupied by the pair of single interline

memory modules (SIMMs) that contain the 16 MB or 32 MB of memory

that is supplied with the computer.

Different banks can have different capacities (8, 16, 32 or 64 MB), but must

be composed of identical pairs of modules (2✕4, 2✕8, 2✕16 or 2✕32 MB).

By installing a pair of 32 MB SIMMs in every bank, first removing the

memory modules that were supplied with the computer, the maximum

capacity of 192 MB of main memory can be attained.

The banks can be filled, or left empty, in any order. However, there is a

performance advantage to filling the banks in the order A, B, C. The

explanation for this is outlined in the description of the cache memory

controller on page 23.

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2 System Board

Devices on the Processor-Local Bus

Each bank that is used must contain a pair of identical modules: the same

speed (60 or 70 ns), the same width (32-bit or 36-bit), and the same

technology (extended data out, EDO, or fast page mode, FPM). Different

banks can contain different speed modules (but the computer will work at

the speed of the slowest bank). Different banks can contain different width

modules (but parity and error correcting codes, ECC, are not enabled if any

32-bit width pairs of modules are used). Different banks can contain

different technology modules.

The following table indicates the recommended capacities of main memory.

Operating System

Windows 3.11

Minimum Memory Capacity

4 to 8 MB

Recommended Memory Capacity

12 to 16 MB

16 to 24 MB

24 to 32 MB

16 MB

Windows 95

Windows NT

OS/2

8 MB

12 MB

4 to 8 MB

The Setup program automatically detects which memory module capacity,

speed, and type is installed in each bank. Individual pages of memory can be

configured as cacheable or non-cacheable by software or hardware. They

can also be enabled and disabled by hardware or software.

Error Correcting Code

Operation

Error correcting code (ECC) is available when using 36-bit memory

modules. The original 32-bit modules must be removed so that the memory

is populated exclusively by 36-bit modules. The appropriate field must be set

in the Memorysub-menu of the Configurationmenu of the Setup program.

Using ECC, a single bit error in any 72-bit line of memory (64 data bits plus

8 parity bits) is corrected automatically and transparently. A double bit

error causes an NMI to be generated, and the computer to be halted.

If more than two bits are faulty within any given 72-bit line, the effect is the

same as it would have been without error correction. The effect of executing

a faulty instruction is always unpredictable, and might cause the program to

‘hang’. The effect of reading a faulty data word is often similarly

unpredictable, but can sometimes be tolerated (for instance, it might merely

appear as a corrupted pixel on a video display).

An extra delay is introduced in the chip set while it is performing the ECC

conversions, so causing ECC memory to have a slower access than non-ECC

memory. Moreover, ECC memory modules are available only in 70 ns FPM

technology.

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2 System Board

Devices on the PCI Bus

Device Name

Device

Chip-set Interrupt Connection

PCI Device

Function AD[xx]

Number

INTA INTB INTC INTD

PL/PCI bridge

PCI/ISA bridge

IDE controller

USB controller

TXC

PIIX3

0 (00h)

—

15 (0Fh)

Integrated graphics controller

PCI slot #1

S3 Trio 64V2

13 (0Dh)

7 (07h)

—

J11

—

PCI slot #2

10 (0Ah)

6 (06h)

PCI slot #3

PCI slot #4 (minitower models)

PCI Proprietary slot (desktop models)

J12

—

12 (0Ch)

11 (0Bh)

—

The distribution of the interrupt lines is described more fully on page 82.

Models without any PCI boards, such as the Matrox Millennium Graphics

controller or the Ethernet Network controller, are supplied with a PCI

terminator. This should be plugged into any PCI slot, and removed if ever a

PCI accessory board is subsequently installed.

Integrated Drive Electronics (IDE)

The IDE controller is implemented as part of the PIIX3 chip (the PCI/ISA

bridge). It is driven from the PCI bus, and has PCI-Master capability. It

supports Enhanced IDE (EIDE) and Standard IDE. To use the Enhanced

IDE features the drives must be compliant with Enhanced IDE.

Up to four IDE devices are supported: two (one master and one slave)

connected to the primary channel, and two (one master and one slave) to

the secondary channel. The primary channel is fitted with an IDE cable with

two connectors. The secondary channel is fitted with an IDE cable with one

or two connectors (one for the desktop models, two for the minitower

models). If a single device (a hard disk drive or a CD-ROM drive) is attached

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2 System Board

Devices on the PCI Bus

to a channel, it should be in the master position (the connector that is

closest to the system board, unless the markings on the cables state

otherwise).

It is possible to mix a fast and a slow device, such as a hard disk drive and a

a CD-ROM, on the same channel without affecting the performance of the

fast device. The BIOS sends a command to each drive to determine,

automatically, the fastest configuration that it supports. However, in general,

the primary channel cable is recommended for hard disk drives, and the

secondary channel cable for CD-ROM drives.

Transfer Rates Versus The controller supports 32-bit Windows I/O transfers. Five PIO modes, and

three DMA modes are supported. The five supported PIO modes allow the

following transfer rates.

Modes of Operation

Mode

Cycle time (ns)

Transfer rate (MB/s)

600

3.33

383

5.22

240

8.33

180

11.1

120

16.7

The three DMA modes allow the following transfer rates:

Mode

Cycle time (ns)

Transfer rate (MB/s)

480

4.2

150

13.3

120

16.7

Disk Capacity Versus

Modes of Addressing

The amount of addressable space on a hard disk is limited by three factors:

the physical size of the hard disk, the addressing limit of the IDE hardware,

and the addressing limit of the BIOS. The Extended-CHS addressing scheme

allows larger disk capacities to be addressed than under CHS, by performing

a translation. If the Setup field has been set to automatic, the logical block

addressing (LBA) mode will be selected for each device that supports it.

Cylinders per

Device

Heads per

Cylinder

Bytes per

Sector

Bytes per

Device

Sectors per Track

CHS

ECHS

LBA

256

1024

512

528 M

8.4 G

1024

256 M (=2

)

137 G

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2 System Board

Devices on the PCI Bus

Universal Serial Bus (USB) Controller

When the HP Vectra VL 5/xxx Series 5 and XA 5/xxx PCs were first

released, they were preloaded with the Microsoft Windows 95 operating

system, version SR2. The Microsoft Supplement 2.1 software, which

provides support of the Universal Serial Bus, was not available. When it

becomes available, it can be obtained from the Hewlett-Packard World Wide

Web site: http://www.hp.com/go/vectrasupport/

You can verify that your PC has Windows 95 support for the USB installed by

clicking on the “Add Software” folder in the Windows 95 Control Panel, and

see if OSR 2.1 WDM/supplement is installed. If it is not listed, you should

install the Microsoft Supplement 2.1 software.

USB works only if the USB interface has been enabled within the HP Setup

program. Currently, only the Microsoft Windows 95 operating system

provides support for the USB.

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2 System Board

Devices on the ISA Bus

ISA Device

Index

Data

Super I/O

15Ch

496h

15Dh

497h

Little Ben (HP ASIC)

Super I/O Controller

The Super I/O chip (37C932) is part of the chip set, and is described on

page 26.

The computer is supplied with a Logitech 2-button mouse, and a C3758A

keyboard with the following features:

❒ Space bar power on, to start the computer from the Off state (if power on

from keyboardis enabled in the Setup program).

❒ Windows key (next to the

keys), which has the same effect as

clicking the “Start” button on the Windows 95 task bar.

❒ Pull-down key (next to the right

key), which has the same effect as

clicking the right mouse button.

Serial EEPROM

The computer uses 4 Kbit of Serial EEPROM implemented within a single

512 K ✕ 8-bit ROM chip. Serial EEPROM is ROM in which one byte at a time

can be returned to its unprogrammed state by the application of appropriate

electrical signals. In effect, it can be made to behave like very slow, non-

volatile RAM. It is used for storing the contents of the CMOS memory (the

tatoo string, the serial number, and the parameter settings for the Setup

program), even during long periods of the computer being unplugged from

the mains supply.

When installing a new system board, the Serial EEPROM will have a blank

serial number field. This will be detected automatically by the BIOS, which

will then prompt the user to enter the serial number which is printed on the

identification label on the back of the computer.

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2 System Board

Devices on the ISA Bus

Flash EEPROM (the System ROM)

The computer uses 256 KB of Flash EEPROM implemented within a single

256 K ✕ 8-bit ROM chip (or in two 128 K ✕ 8-bit chips). Flash EEPROM is

ROM in which the whole memory can be returned to its unprogrammed

state by the application of appropriate electrical signals to its pins. It can

then be reprogrammed with the latest firmware.

The System ROM contains: 64 KB of system BIOS (including the boot code,

the ISA and PCI initialization, RPO, DMI, the Setup program and the Power-

On Self-Test routines, plus their error messages); 32 KB of video BIOS;

32 KB of Plug-and-Play code; and 32 KB of power management code. The

functions of these are summarized in Chapters 4 and 5.

Updating the System ROM

The System ROM can be updated with the latest BIOS. This can be

downloaded, as a compressed file, from the HP Electronic Services. You

must specify the model of the computer since the utility which is supplied

for a different model cannot be used with this one. (More information is

given in the “Hewlett-Packard Support and Information Services” chapter in

the User’s Guide that was supplied with the computer).

The compressed file, once downloaded, can be executed. This causes it to

be expanded out into a number of files, including:

• the Flash EEPROM reprogramming utility program, phlash.exe

• the BIOS upgrade file, HA0700xx.FUL

• the binary file, PFMHA106.bin

• the batch file, flash.bat

• a number of *.txtfiles, giving information about the new version of the

BIOS, and instructions on how to install it.

The Phlash utility must be run from a diskette.

Do not switch off the computer until the system BIOS update procedure has

completed, successfully or not, otherwise irrecoverable damage to the ROM

may be caused. The control panel switches are automatically disabled to

prevent accidental interruption of the flash programming process.

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2 System Board

Devices on the ISA Bus

System Board Switches

Five of the system board switches (whose location is shown on page 20) set

the working frequencies for the computer, as summarized on page 31. The

others set the configuration for the computer, as summarized in the table on

the next page.

Switch

Functions of the System Board Switches

1-4,7-8

Bus frequencies (see the table on page 31)

Password:

Open = enabled (default)

Closed = disabled / clear User and Administrator passwords

Clear CMOS:

Open = normal (default)

Closed = clear CMOS (to reload the Setup program defaults)

Keyboard space-bar power-on:

Open = disabled

Closed = enabled (default)

Product identification:

Open = normal operation (default)

Closed = clear the product identification field in the CMOS memory

By setting switch SW6 in the Closedposition, not only is the configuration

data cleared (in the CMOS memory and the Serial EEPROM), but also all the

Plug-and-Play data that had been saved in the Serial EEPROM. However,

the serial number, the tattooing string, the date and the time are each

retained.

By setting switch SW9 in the Closed position, the Power-On Space-Bar

function is enabled. Note, though, that it must also be enabled in the

Power-On Space-Barfield of the Power Menu in the Setup program.

Turning the computer on, with switch SW10 in the Closedposition, clears

the product identification field in the BIOS, and causes the computer to

prompt for the new information. By identifying the product correctly (after

replacing a defective system board by a new one), the BIOS is able to tailor

itself for the particular product, and to enable the appropriate features.

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2 System Board

Devices on the ISA Bus

Updating the BIOS Before Considering Replacing the System Board

If the computer is faulty, but it starts up correctly, and the fault is not clearly

due to the system board hardware, then it is advisable to check the BIOS

version number. The BIOS version number can be found from the summary

screen, or the Setup program, obtained by pressing

, respectively,

when the computer has just been restarted, as described in Chapter 4.

If it is not the current version of the BIOS, the System ROM should be

flashed with the new version, as described on the previous page. The

computer should then be re-run to see if this has cleared the problem.

Little Ben

Little Ben is an HP application specific integrated circuit (ASIC), designed

to be a companion to the Super I/O chip. It is described on page 73.

Other PCI and ISA Accessory Devices Under Plug and Play

Plug and Play is an industry standard for automatically configuring the

computer’s hardware. When you start the computer, the Plug and Play

system BIOS can detect automatically which hardware resources (IRQs,

DMAs, memory ranges, and I/O addresses) are used by the system-based

components.

All PCI accessory boards are Plug and Play, although not all ISA boards are.

Check the accessory board’s documentation if you are unsure.

The computer is PCI 2.1 compliant, and PnP 1.1 compliant. This meets the

“Windows 95 Required” level for Plug and Play. Accessory boards which are

Plug and Play are automatically configured by the operating system

(Windows 95) or by the BIOS (other operating systems).

In general, in a Plug and Play configuration, resources for an ISA board have

to be reserved first (using a utility under Windows 95 or ICU for DOS/

Windows) and then you can plug in your board. If you want to install an ISA

board when running a non Plug-and-Play operating system, such as

Windows for Workgroups, you have to reserve the resources for the board

using the ICU (for Windows). Failure to do so may lead to resource conflicts.

The procedure for installing an ISA accessory board that is not Plug and

Play in Windows 3.11 or Windows 95 is described in the User’s Guide that is

supplied with the computer.

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Interface Devices and Mass-Storage Drives

This chapter describes the video, mass storage, audio and network devices

which are supplied with the computer. It also summarizes the pin connec-

tions on internal and external connectors.

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3 Interface Devices and Mass-Storage Drives

S3 Trio 64V2 Graphics Controller Chip

Most models of the HP Vectra VL 5/xxx Series 5 PC are supplied with a

graphics controller chip integrated on the system board. This 64-bit PCI

Ultra VGA graphics controller can be characterized as follows:

• 100% compatible with IBM VGA display standard

• 32-bit video memory access with 1 MB, 50 ns, EDO, video DRAM.

Increased to 64-bit access when an additional 1 MB DRAM is installed

• integrated 24-bit RAMDAC

• fully programmable Pixel Clock Generator up to 170 MHz

• 60 MHz clock for video memory

• fast linear addressing with full software relocation

• green power saving features

• playback acceleration, continuous interpolation on X, continuous interpo-

lation on Y

• DDC 2B compliant.

Video Memory

1 MB is fitted as standard. Two sockets are provided for installation of an

additional 1 MB (two modules, each with a 512 KB, 60 ns surface mount

chip). The installed video memory capacity is detected automatically by the

BIOS.

The controller gives 32-bit video memory access, with 1 MB of video RAM

fitted. This is increased to 64-bit access when the additional 1 MB upgrade is

installed.

There is no orientation key to determine the polarity of the upgrade chips,

so care must be exercised to align the point on the chips with the cut edge

of the socket. A special extraction tool (5041-2553) is needed when

removing them again.

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3 Interface Devices and Mass-Storage Drives

S3 Trio 64V2 Graphics Controller Chip

Video Modes

Standard and Enhanced Video Graphics Array (VGA) modes are available.

Hardware acceleration of graphical user interface (GUI) operations is

provided, and acceleration for 8, 16 and 32-bit pixel depths.

The following table details the standard VGA modes which are currently

implemented in the video BIOS. These modes are supported by standard

BIOS functions. The video BIOS (which is mapped contiguously in the

address range C0000h to C7FFFh) contains all the routines required to

configure and access the graphics subsystem.

Standard VGA Modes

Vertical

Refresh

(Hz)

Horizontal

Refresh

(kHz)

Interface

Type

No. of

Colors

Dot Clock

(MHz)

Mode No.

Standard

Resolution

00h

00h*

00h+

01h

VGA

text

40 x 25 chars

80 x 25 chars

320 x 200

b/w

31.5

25.175

28.322

25.175

28.322

25.175

28.322

25.175

28.322

25.175

28.322

25.175

text

01h*

01h+

02h

text

b/w

02h*

02h+

03h

text

03h*

03h+

04h

text

graphics

text

05h

320 x 200

06h

640 x 200

07h

80 x 25 chars

320 x 200

b/w

07h+

0Dh

text

graphics

0Eh

640 x 200

0Fh

640 x 350

b/w

10h

640 x 350

11h

640 x 480

12h

640 x 480

13h

320 x 200

256

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3 Interface Devices and Mass-Storage Drives

S3 Trio 64V2 Graphics Controller Chip

The extended modes supported by the video BIOS are:

Extended Video Modes with 1 MB DRAM

Vertical

Refresh

(Hz)

Horizontal

Refresh

(kHz)

Extended

Mode No.

VESA

Mode No.

Interface

Type

No. of

Colors

Dot Clock

(MHz)

Resolution

4Eh

4Fh

51h

52h

54h

55h

65h

66h

67h

68h

69h

6Ah

6Bh

6Ch

6Dh

6Eh

70h

207h

208h

212h

213h

10Ah

109h

10Dh

10Eh

10Fh

100h

101h

102h

103h

104h

105h

106h

110h

graphics

text

1152 x 864

1280 x 1024

640 x 480

640 x 400

132 x 43 chars

132 x 25 chars

320 x 200

640 x 400

640 x 480

800 x 600

1024 x 768

1280 x 1024

640 x 480

256

80.000

110.000

25.000

40.000

12.540

25.175

31.500

36.000

40.000

50.000

49.500

56.000

40.000

50.000

49.500

56.000

65.000

75.000

80.000

95.000

65.000

75.000

80.000

95.000

110.000

25.175

31.500

36.000

63.7

31.5

16.7 M

text

graphics

32,768

65,536

16.7 M

256

31.5

37.9

37.5

256

37.9

48.1

47.5

53.6

37.9

48.1

46.8

53.6

48.4

56.5

60.2

68.7

48.4

56.5

60.0

68.7

256

32,768

31.5

37.5

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3 Interface Devices and Mass-Storage Drives

S3 Trio 64V2 Graphics Controller Chip

Vertical

Refresh

(Hz)

Horizontal

Refresh

(kHz)

Extended

Mode No.

VESA

Mode No.

Interface

Type

No. of

Colors

Dot Clock

(MHz)

Resolution

71h

72h

73h

74h

111h

112h

113h

114h

graphics

640 x 480

800 x 600

65,536

16.7 M

32,768

65,536

31.5

37.5

25.175

31.500

36.000

25.175

31.500

36.000

40.000

50.000

49.500

57.000

40.000

50.000

49.500

57.000

31.5

37.9

37.5

37.9

48.1

46.8

53.6

37.9

48.1

46.8

53.6

Extended Video Modes with 2 MB DRAM

Vertical

Refresh

(Hz)

Horizontal

Refresh

(kHz)

Extended

Mode No.

VESA

Mode No.

Interface

Type

No. of

Colors

Dot Clock

(MHz)

Resolution

6Fh

75h

76h

77h

7Ch

107h

115h

116h

117h

120h

graphics

1280 x 1024

800 x 600

256

48.5i

77.7

79.5

37.9

41.8

46.8

53.6

48.9

56.5

60.2

68.7

48.9

56.5

60.2

68.7

62.00

55.000

65.000

67.000

40.000

50.000

49.500

57.000

65.000

75.000

80.000

95.000

65.000

75.000

80.000

95.000

67.000

256

16.7 M

32,768

65,536

256

800 x 600

1024 x 768

1600 x 1200

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3 Interface Devices and Mass-Storage Drives

S3 Trio 64V2 Graphics Controller Chip

Available Video Resolutions

Drivers are supplied with the computer. At the time of release, these bear

the version number: A.02.04. The following table lists the available video

resolutions using these drivers. The available resolutions may be different

with later versions of each of these drivers.

Resolution

Number of colors

Refresh Rate (Hz)

Memory

16, 16M

256, 64K

1 MB

Windows 95

640 x 480

60, 72, 75, 85

800 x 600

1024 x 768

640 x 480

16, 256, 64K

256

16M

64K

60, 72, 75, 85

60, 75, 85

2 MB

800 x 600

1024 x 768

1280 x 1024

1600 x 1200

256

1 MB

2 MB

Windows 3.11

640 x 480

256, 32K, 64K

60, 72, 75, 85

800 x 600

1024 x 768

640 x 480

256, 32K, 64K

256

16M

32K, 64K

256

60, 72, 75, 85

60, 75, 85

800 x 600

1024 x 768

1280 x 1024

1600 x 1200

256

1 MB

2 MB

Windows NT 4.0 or 3.5x

640 x 480

256, 64K

60, 72, 75, 85

800 x 600

1024 x 768

640 x 480

256, 64K

256

16M

64K

60, 72, 75, 85

60, 75, 85

800 x 600

1024 x 768

1280 x 1024

1600 x 1200

256

1 MB

2 MB

Windows OS/2 Warp

640 x 480

256, 64K

60, 72, 75, 85

800 x 600

1024 x 768

640 x 480

800 x 600

1024 x 768

1280 x 1024

256

16M

64K

256

60, 72, 75, 85

60, 75

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3 Interface Devices and Mass-Storage Drives

S3 Trio 64V2 Graphics Controller Chip

If Video Plug and Play is enabledin Setup, and a DDC monitor is detected,

Setup will automatically configure the best refresh rate. For non DDC

monitors, or when video Plug and Play is disabled, refresh rates can be

changed in Setup.

The number of colors supported is limited by the graphics card and the

video RAM. The resolution/refresh-rate combination is limited by a

combination of the display, the graphics card, and the video RAM.

Connectors

The layout of the pins for the DB15 VGA socket are depicted on page 62.

The Video Electronics Standards Association (VESA) defines a standard

video connector, variously known as the VESA feature connector,

auxiliary connector, or pass-through connector. This connector (whose

pin names are listed in a table on page 58) is integrated on the system board,

and is connected directly to the pixel data bus and the synchronization

signals.

The graphics controller supports an output-only VESA feature connector in

VGA mode. It is disabled by default and must be enabled in the Setup

program. Use of the VESA feature connector will disable the 1 MB video

memory upgrade, if one is installed. Only the standard 1 MB of video

memory will be used.

Troubleshooting

To get the hardware configuration information, click on the “Control Panel/

Display/Settings/Advanced Properties” menu in Windows 95. This gives

information of the form: Manufacturer=S3, Chip Type=775 Rev E, DAC

Type=Internal, Memory=1 MB, Features=DirectDraw, Software Version=4.0.

The “Software Version” is the version number of the driver builder. To obtain

the driver version, you need to click on the “System/Device Manager/Display

Adapter/S3 Trio 64V2 Hewlett-Packard VL5” menu. To obtain the version

number of Microsoft DirectDraw, find the Ddraw.dllfile, and click on

Properties with the right mouse button.

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3 Interface Devices and Mass-Storage Drives

Matrox MGA Millennium Graphics Controller Board

All models of the HP Vectra XA 5/xxx PC and a few models of the

HP Vectra VL 5/xxx Series 5 PC are supplied with a Matrox MGA

Millennium PCI graphics controller on a board fitted in a PCI accessory slot.

The on-board MGA-2064W processor communicates with the Pentium

processor along the PCI bus. The controller can be characterized as follows:

• 100% hardware- and BIOS-compatible with IBM VGA display standard

• 64-bit video memory access

• Hardware acceleration of graphical user interface (GUI) operations

• Support for up to 8 MB Window RAM (WRAM) at 50 ns

• Integrated 24-bit, 220 MHz RAMDAC

• Pixel clock maximum frequency of 135 MHz

• Green power saving features

• Standard and Enhanced Video Graphics Array (VGA) modes

• Acceleration for 3D, playback, MPEG (when an optional upgrade module

from Matrox is fitted), continuous interpolation on X, replication on Y

• DDC 2B compliant.

VESA pass-through connector Top half of upgrade socket

Top and bottom halves of the

2 MB memory chips

upgrade socket. (For the

Matrox VESA connector

Media XL connector

installation of a video memory

upgrade module or the Matrox

MPEG module).

Graphics processor chips

Bottom half of upgrade socket

Configuration switches

Configuration switches. (Set to

their bottom position for

normal operation).

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3 Interface Devices and Mass-Storage Drives

Matrox MGA Millennium Graphics Controller Board

Connectors

The Video Electronics Standards Association (VESA) defines a standard

video connector, variously known as the VESA feature connector,

auxiliary connector, or pass-through connector. The video controller

supports an output-only VESA feature connector in VGA mode. This

connector (whose pin names are listed in a table on page 58) is integrated

on the PCI board, is connected directly to the pixel data bus and the

synchronization signals, and is automatically enabled all of the time.

There are two connectors on the back panel: the normal DB15 VGA

connector, for connecting to HP displays, and a Media XL connector (used

by the MPEG accessory, not supported by HP). The layout of the pins for the

DB15 VGA connector are shown on page 62.

If you install a VESA-standard video accessory board that uses the MGA

video adapter, connect the accessory board’s cable to the VESA pass-

through connector on the board.

Video Memory

The video memory (also known as window RAM, or WRAM) is a local block

of RAM for holding two major data structures: the double buffer (to hold one

frame steady on the screen whilst the next one is being processed), and the

Z-buffer (for storing depth information for each pixel). It is dual ported, so

that it can be inputting and outputting simultaneously. There is also

hardware support for Gouraud shading, Phong shading and texture

mapping.

The Matrox MGA Millennium graphics controller board is supplied with 2

MB of video memory. This can be upgraded to 4 MB with a D3557B upgrade

module, or to 8 MB with an MGA-MIL/MOD6 upgrade module (ordered from

Matrox). The upgrade socket can alternatively be used for the installation of

the Matrox MGA Media XL upgrade module (also ordered from Matrox) to

support MPEG. The switch settings do not have to be changed.

Available Video Resolutions

The number of colors supported is limited by the graphics device and the

video memory. The resolution/color/refresh-rate combination is limited by a

combination of the display driver, the graphics device, and the video

memory. If the resolution/refresh-rate combination is set higher than the

display can support, you risk damaging the display.

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3 Interface Devices and Mass-Storage Drives

Matrox MGA Millennium Graphics Controller Board

Resolution

Number of colors

Maximum Refresh Rate

(Hz)

Memory

640 x 480

256, 64K, 16M

256, 64K

200

2 MB

800 x 600

1024 x 768

1280 x 1024

1600 x 1200

640 x 480

120

110

256

256, 64K, 16M

256, 64K, 16M (24 bpp)

256, 64K

200

4 MB

8 MB

800 x 600

1024 x 768

1280 x 1024

1600 x 1200

640 x 480

120

110

256, 64K, 16M

256, 64K, 16M (24 bpp)

200

800 x 600

1024 x 768

1280 x 1024

1600 x 1200

120

110

The table below summarizes the 2D video resolutions which are supported.

Note, though, SCO Unix only supports 15 bpp (bits per pixel), instead of

16 bpp, and does not support 32 bpp; OS/2 does not support 24 bpp.

256

64 K

Hi-Color

16.7 M

True-Color

16.7 M

True-Color

Number of

Colors

Bits per Pixel

640 ✕480

800 ✕600

1024 ✕768

2 MB, 200 Hz

2 MB, 120 Hz

4 MB, 120Hz

4 MB, 120 Hz

8 MB, 110 Hz

Not supported

1152 ✕882

1280 ✕1024

1600 ✕120

2 MB, 110 Hz

2 MB, 85 Hz

4 MB, 110 Hz

4 MB, 85 Hz

8 MB, 85 Hz

1152 ✕882 is not preset on HP displays

The maximum 2D resolutions for any given video memory capacity and

color scale can be found from the following table:

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3 Interface Devices and Mass-Storage Drives

Matrox MGA Millennium Graphics Controller Board

256

64 K

Hi-Color

16.7 M

True-Color

16.7 M

True-Color

Number of

Colors

Bits per Pixel

2 MB

4 MB

8 MB

1600 ✕1200 1024 ✕768

1600 ✕1200 1600 ✕1200

800 ✕600

1280 ✕1024

1152 ✕882

1600 ✕1200 Not supported

1152 ✕882 is not preset on HP displays

Drivers are supplied with the computer. At the time of release, these bear

the following version numbers:

❒ 1.22p for Windows for Workgroups 3.11

❒ 3.17b61 for Windows 95

❒ 2.30 for Windows NT 4.0.

Video BIOS

The Matrox MGA Millennium board has a flash video BIOS that can be

updated like a system BIOS, using a flash utility. This is achieved as follows:

1 Create a DOS boot diskette, and copy the following files to it:

• xxxxxxxx.bin (a binary file whose name depends on the version)

• dos4gw.exe

• progbios.exe

• updbios.bat

2 Switch off the PC, and take out the Matrox board (this is necessary since

the board switches are not accessible whilst it is in place).

3 Set SW-1, on the Matrox board, to ON (BIOS unprotected).

4 Reinstall the Matrox board, insert the boot diskette, and switch on the PC.

5 Run the updbios.batcommand file or progbios.exe -i *.bin.

6 Switch off the PC, and take out the boot diskette and the Matrox board.

7 Set SW-1, on the Matrox board, to OFF (BIOS protected).

8 Reinstall the Matrox board, and switch on the PC.

Executing progbios.exe -dallows the BIOS revision date to be checked.

The video BIOS revision number can be checked by clicking on the MGA

control panel (Display Properties/MGA Settings/Advanced for Windows 95).

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3 Interface Devices and Mass-Storage Drives

HP Ethernet 10/100 BaseT Network Board

The HP Ethernet 10/100 BaseT Network Board is supplied on all models of

the HP Vectra XA 5/xxx PC. It is based on the AMD PCnet-PCI-II 79C971

network processor chip.

On desktop models, it is installed in a dedicated PCI accessory slot

underneath the internal, hard disk drive, rear-shelf, plugged into the PCI

Junior slot that is situated on the rear of the double-sided backplane board.

On the rear panel there are two RJ-45 unshielded twisted-pair (UTP)

connectors, whose pin-out is shown in the diagram on page 62. One is fully

compliant with the 10-BaseT, 10 Mbits per second, ISO 8802-3 (IEEE/ANSI

802.3) standard. It supports the Remote Power-On (RPO) feature that is

described on page 71.

The other RJ-45 connector is fully compliant with the 100-BaseT, 100 Mbits

per second, ISO 8802-3 (IEEE/ANSI 802.3u) standard. This connector

supports the Remote Wake-Up feature, but not Remote Power-On.

The two lights indicate which of the network sockets is connected (they are

not link lights or activity lights). The controller automatically detects which

of the two connectors is presently in use.

There is a socket, on the network board, to support an Option ROM of up to

256 KB. This is not compatible with the Option ROM chip from the

Enhanced Ethernet Network board.

RJ-45 UTP 10 BaseT network

Network

Filter

Processor

Remote start

Network connected light

Chip

RPO logic

20 MHz

clock

RJ-45 UTP 100 BaseT network

Network connected light

SRAM

100BT Phy layer

Filter

50 MHz clock

Option ROM socket

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3 Interface Devices and Mass-Storage Drives

HP Ethernet 10/100 BaseT Network Board

Remote Power-On (RPO) There is a cable from the Remote Start connector, on the network board, to

the External Start connector, on the system board. This is used by the

Remote Power-On feature (RPO) that is described on page 71. This cable

must be routed through the hole in the chassis. Not doing so, and allowing

the cable to be routed with the flexible disk drive and IDE cables, will raise

the risk of radio frequency interference (RFI) cross-talk.

The board is supplied with power, even whilst the rest of the computer is

turned off, via a line called VStandby on the External Start Connector. This

connector also carries the control lines which the network board uses to

turn on the main power supply, and to send or receive other control and

status information.

When shutdown into its RPO state, the 10 BaseT side of the board draws 30

mA, well within the 50 mA capability of the special RPO power supply. (The

100 BaseT side of the board would draw more than 50 mA if connected, and

hence does not support RPO).

Look-Ahead Packet

Processing (LAPP)

Standard drivers wait until a complete frame has been received before

processing it, and passing it to the application buffer. They then wait for the

controller buffer to be empty before starting to receive the next frame.

If there are many small frames, and a large amount of Windows application

switching, the network utilization rate can fall below 50%. The PC-Net

controller utilization of the system bus is about 4%. The remaining 96% can

be used by suitable LAPP drivers to start inter-frame data transfers to the

application stack buffer. By reducing the latency between frame reception,

the network utilization and throughput is increased.

Drivers

The board can be configured completely by software (no switches or

jumpers need changing). Drivers for the network board are supplied with

the computer. At the time of release, these bear the version number P.01.05.

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3 Interface Devices and Mass-Storage Drives

HP Enhanced Ethernet Network Board

The HP Enhanced Ethernet Network Board is supplied on some models of

the HP Vectra VL 5/xxx Series 5 PC. It is based on the AMD PCnet-PCI-II

79C970 network processor chip.

On desktop models, it is installed in a dedicated PCI accessory slot

underneath the internal, hard disk drive, rear-shelf, plugged into the PCI

Junior slot that is situated on the rear of the double-sided backplane board.

This controller is fully compliant with the 10-BaseT, 10 Mbits per second,

ISO 8802-3 (IEEE/ANSI 802.3) standard. There is a socket to support an

Option ROM of up to 32 KB. On the rear panel there is an RJ-45 unshielded

twisted-pair (UTP) connector, whose pin-out is shown in the diagram on

page 62.

RJ-45 UTP 10 BaseT network

Remote start

Network controller

Coax adapter board

Hole to accept network coax BNC

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3 Interface Devices and Mass-Storage Drives

Audio Controller

Remote Power-On (RPO) There is a cable from the Remote Start connector, on the network board, to

the External Start connector, on the system board. This is used by the

Remote Power-On feature (RPO) that is described on page 71. This cable

must be routed through the hole in the chassis. Not doing so, and allowing

the cable to be routed with the flexible disk drive and IDE cables, will raise

the risk of radio frequency interference (RFI) cross-talk.

The board is supplied with power, even whilst the rest of the computer is

turned off, via a line called VStandby on the External Start Connector. This

connector also carries the control lines which the network board uses to

turn on the main power supply, and to send or receive other control and

status information.

When shutdown into its RPO state, the board draws 20 mA, well within the

50 mA capability of the special RPO power supply.

Drivers

The board can be configured completely by software (no switches or

jumpers need changing). Drivers for the network board are supplied with

the computer. At the time of release, these bear the version number T.01.00.

Audio Controller

The Creative Labs CT2970 SoundBlaster 16 audio interface, supplied on

some models in an ISA slot, can be summarized as follows:

• line-out (stereo) jack: 20 Hz to 20 kHz frequency response, 83 dB signal

to noise ratio, 0.2% total harmonic distortion

• headphones jack: 2 W PMPO per channel, 32 Ω load

• speaker connector: 0.2% total harmonic distortion

• line-in (stereo) jack: 15 kΩ, 0 V to 2 V peak-to-peak

• CD audio-in connector: 15 kΩ, 0 V to 2 V peak-to-peak

• microphone input: 600 Ω, dynamic, 30 mV to 200 mV peak-to-peak

• MIDI /joystick interface connector: MPU-401 UART compatible

• 8-bit and 16-bit stereo sampling: 5 kHz to 44.1 kHz

• Creative OPL3 synthesizer: 20 polyphonic voices

• typical electrical current: +5 V (250 mA), +12 V (250 mA), -12 V (50 mA)

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3 Interface Devices and Mass-Storage Drives

Audio Controller

Aux2 (MPEG)

CD-Audio

Front panel

Wavetable

Goldfinch

Microphone

Line-In

MIC-In

Modem

Line-Out

Speaker-Out

Internal

speaker

Joystick

Audio control chip

The board is compliant with Microsoft PC 95 revised / PC 96. It has a full

duplex codec, and supports a volume control on the front panel.

Drivers

Drivers for the audio board, working with the Windows NT operating system,

are supplied with the computer. These are required since the board is Plug-

and-Play, but the operating system is not. It is the user’s responsibility to

avoid conflicts with other devices using the same resources (such as IRQ,

DMA and I/O lines). The user can use the configuration manager to change

the board settings, choosing either the default configuration, or changes to

any of the parameters.

Windows for Workgroups 3.11 drivers rely on ICU and its configuration

manager, which must be installed. Windows 95 is a true Plug-and-Play

operating system, and does not need such drivers.

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3 Interface Devices and Mass-Storage Drives

Mass-Storage Drives

The IDE controller is described on page 34. The flexible disk controller is

described on page 26.

Hard Disk Drives

A 3.5-inch hard disk drive is supplied on an internal shelf in some models.

2.5 GB IDE

1.6 GB IDE

HP product number

Manufacturer

D2784-69001

Quantum

D4621-69001

Quantum

Product name

Fireball TM 2550

Fireball TM 1700

Flexible Disk Drives

A 3.5-inch, 1.44 MB flexible disk drive (D2035B) is supplied on the top

front-access shelf of all models.

CD-ROM Drives

Most models have a 8✕ IDE CD-ROM drive (D4381A) supplied in a 5.25-inch

front-access shelf.

8✕ IDE

HP product number

Manufacturer

D4381A

Hitachi

Product name

Formatted storage capacity

CDR-7930

650 MB

If a disk is still in the drive after power failure or drive failure, the disk can

be reclaimed by inserting a stout wire, not unlike a straightened paper-clip,

into the dedicated hole at the bottom of the door.

In order to allow correct CD-ROM drive detection by the Setup program,

leave the device configuration jumper on the rear connector in the cable

select (CS) or master (MA) positions.

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3 Interface Devices and Mass-Storage Drives

Connectors and Sockets

IDE Hard Disk Drive Data Connector

Flexible Disk Drive Data Connector

11 HD3

13 HD2

15 HD1

17 HD0

19 Ground

21 DMARQ

23 DIOW#

25 DIOR#

27 IORDY

29 DMACK#

31 INTRQ

33 DA1

Signal

Reset#

HD7

HD6

HD5

HD4

10 HD11

12 HD12

14 HD13

16 HD14

Signal

Ground

HD8

HD9

HD10

11 Ground

13 Ground

15 Ground

17 Ground

19 Ground

21 Ground

23 Ground

25 Ground

27 Ground

29 Ground

31 Ground

33 Ground

Signal

Ground

Signal

LDENSEL#

Microfloppy

EDENSEL

INDX#

10 MTEN1#

12 DRSEL0#

14 DRSEL1#

16 DTEN0#

18 DIR#

18 HD15

20 orientation key

22 Ground

24 Ground

26 Ground

28 SPSYNC:CSEL

30 Ground

32 IOCS16#

34 PDIAG#

36 DA2

20 STP#

22 WRDATA#

24 WREN#

26 TRK0#

28 WRPRDT#

30 RDDATA#

32 HDSEL1#

34 DSKCHG#

35 DA0

37 CS0#

39 DASP#

38 CS1#

40 Ground

Status Panel Connector

Signal Pin

Signal

1 LCK_LED_K

3 PWR_LED_K

5 not connected

7 Push_On

2 LCK_LED_A

4 PWR_LED_A

6 common

8 RED_LED_A

9 HDD_LED_K

11 _Reset

10 HDD_LED_A

12 Ground

13 LCK_PUSH2

14 LCK_PUSH2

External Start and Remote Start Connectors

Signal

1 ExternalStart

3 Wake1#

Signal

2 Ground

4 Wake2#

5 not connected

7 PowerGood

9 Vstandby

6 Wake3#

8 not connected

10 orientation key

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3 Interface Devices and Mass-Storage Drives

Connectors and Sockets

Audio Board Connectors

Wavetable Connector

Signal Pin

Goldfinch Connector

Signal

1 Ground

3 Ground

5 Ground

7 Ground

9 Ground

2 not connected

4 MIDI input

6 Vcc

8 MIDI output

10 Vcc

1 Line-in (right)

3 Line-in (left)

5 orientation key

7 Analog ground

2 Analog ground

4 Analog ground

6 Analog ground

8 Analog ground

11 Ground

13 not connected

15 Ground

17 Ground

19 Ground

21 Ground

23 Ground

25 Ground

12 not connected

14 Vcc

16 not connected

18 +12 V

20 Line-in (right)

22 -12 V

24 Line-in (left)

26 Reset B

Aux2 MPEG Connector

Signal

1 Left channel

2 Ground

3 Ground

4 Right channel

CD Audio Connector

Pin Signal

1 Ground

Int. Speaker Connector

Signal

1 Power signal out

2 Analog ground

2 Left channel

3 Ground

4 Right channel

Modem Connector

Front Panel Connector

Signal Pin

1 Ground

Signal

1 Analog ground

3 Line-in

5 Line-out (left)

7 Line-out (right)

9 Analog ground

2 orientation key

4 Analog ground

6 Analog ground

8 Modem speaker

2 orientation key

4 Head return left

6 Head return right

8 Volume DC cntl

3 Headphones left

5 Headphones right

7 Volume low limit

9 Volume high limit

10 Microphone in

10 not used

Microphone Connector

Signal

2nd ring:

3rd ring:

1st ring:

3 Signal and power

2 Ground

1 Signal and power

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3 Interface Devices and Mass-Storage Drives

Connectors and Sockets

PCI Connector

B1 -12 V

B2 TCK

B3 Ground

B4 TDO

Signal

A1 TRST#

A2 +12 V

A3 TMS

A4 TDI

A5 +5 V

A6 INTA#

A7 INTC#

A8 +5 V

A9 reserved

A10 PRSNT#

A11 reserved

B47 AD[12]

A47 AD[11]

A48 Ground

A49 AD[09]

A50 C/BE#[0]

A51 + 3.3 V

A52 AD[06]

A53 AD[04]

A54 Ground

A55 AD[02]

A56 AD[00]

A57 +5 V

B48 AD[10]

B49 + 3.3 V

B50 AD[08]

B51 AD[07]

B52 Ground

B53 AD[05]

B54 AD[03]

B55 Ground

B56 AD[01]

B57 +5 V

B58 +5 V

B59 +5 V

B60 ACK64#

B5 +5 V

B6 +5 V

B7 INTB#

B8 INTD#

B9 Ground

B10 reserved

B11 + 3.3 V

orientation key

A58 +5 V

A59 +5 V

A60 REQ64#

B12 reserved

B13 Ground

B14 CLK

B15 Ground

B16 REQ#

A12 reserved

A13 RESET#

A14 + 3.3 V

A15 GNT#

A16 Ground

A17 reserved

A18 AD[30]

A19 Ground

A20 AD[28]

A21 AD[26]

A22 + 3.3 V

A23 AD[24]

A24 IDSEL

A25 Ground

A26 AD[22]

A27 AD[20]

A28 Ground

A29 AD[18]

A30 AD[16]

A31 + 3.3 V

A32 FRAME#

A33 Ground

A34 TRDY#

A35 Ground

A36 STOP#

A37 + 3.3 V

A38 SDONE

A39 SBO#

orientation key

B61 reserved

B62 Ground

B63 C/BE#[5]

B64 C/BE#[4]

B65 Ground

B66 AD[63]

B67 AD[61]

B68 + 3.3 V

B69 AD[59]

B70 AD[57]

B71 Ground

B72 AD[55]

B73 AD[53]

B74 Ground

B75 AD[51]

B76 AD[49]

B77 + 3.3 V

B78 AD[47]

B79 AD[45]

B80 Ground

B81 AD[43]

B82 AD[41]

B83 Ground

B84 AD[39]

B85 AD[37]

B86 + 3.3 V

B87 AD[35]

B88 AD[33]

B89 Ground

B90 reserved

B91 reserved

B92 Ground

A61 Ground

A62 C/BE#[7]

A63 C/BE#[6]

A64 + 3.3 V

A65 PAR64

A66 AD[62]

A67 Ground

A68 AD[60]

A69 AD[58]

A70 Ground

A71 AD[56]

A72 AD[54]

A73 + 3.3 V

A74 AD[52]

A75 AD[50]

A76 Ground

A77 AD[48]

A78 AD[46]

A79 Ground

A80 AD[44]

A81 AD[42]

A82 + 3.3 V

A83 AD[40]

A84 AD[38]

A85 Ground

A86 AD[36]

A87 AD[34]

A88 Ground

A89 AD[32]

A90 reserved

A91 Ground

A92 reserved

B17 + 3.3 V

B18 AD[31]

B19 AD[29]

B20 Ground

B21 AD[27]

B22 AD[25]

B23 Ground

B24 C/BE#[3]

B25 AD[23]

B26 + 3.3 V

B27 AD[21]

B28 AD[19]

B29 Ground

B30 AD[17]

B31 C/BE#[2]

B32 Ground

B33 IRDY#

B34 + 3.3 V

B35 DEVSEL#

B36 Ground

B37 LOCK#

B38 PERR#

B39 Ground

B40 SERR#

B41 + 3.3 V

B42 AD[15]

B43 + 3.3 V

B44 + 3.3 V

B45 AD[14]

B46 Ground

A40 Ground

A41 C/BE#[1]

A42 PAR

A43 + 3.3 V

A44 + 3.3 V

A45 + 3.3 V

A46 AD[13]

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3 Interface Devices and Mass-Storage Drives

Connectors and Sockets

16-bit ISA Connector

(8-bit ISA uses the A and B connectors)

Signal

Ground

Signal

CHCHK#

RESDRV

+5 V

SD7

SD6

IRQ9

SD5

-5 V

SD4

DRQ2

-12 V

SD3

SD2

NOWS#

+ 12 V

Ground

SMWTC#

SMRDC#

IOWC#

IORC#

DEK3#

DRQ3

DAK1#

DRQ1

REFRESH#

BCLK

IRQ7

IRQ6

IRQ5

IRQ4

IRQ3

DAK2#

BALE

+5 V

SD1

SD0

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

B21

B22

B23

B24

B25

B26

B27

B28

B29

B30

B31

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

A26

A27

A28

A29

A30

A31

CHRDY

AENx

SA19

SA18

SA17

SA16

SA15

SA14

SA13

SA12

SA11

SA10

SA9

SA8

SA7

SA6

SA5

SA4

SA3

SA2

SA1

OSC

Ground

SA0

D10

D11

D12

D13

D14

D15

D16

D17

D18

M16#

IO16#

C10

C11

C12

C13

C14

C15

C16

C17

C18

SBHE#

LA23

LA22

LA21

LA20

LA19

LA18

LA17

MRDC#

MWTC#

SD8

IRQ10

IRQ11

IRQ12

IRQ15

IRQ14

DAK0#

DRQ0

DAK5#

DRQ5

DAK6#

DRQ6

DAK7#

DRQ7

+5 V

MASTER16#

Ground

SD9

SD10

SD11

SD12

SD13

SD14

SD15

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3 Interface Devices and Mass-Storage Drives

Connectors and Sockets

Battery Pack

Connector

Power Supply Connector for System Board

Signal

PwrGood

VSTDBY

+5 V supply

+3.3 V supply

Signal

13 Remote_On

14 -5 V supply

15 -12 V supply

16 +12 V supply

17 Ground

18 Ground

19 Ground

20 Ground

21 Ground

VBATT

orientation key

reserved

Ground

USB Connector

Signal

Vcc

10 +3.3 V supply

11 +3.3 V supply

12 +3.3 V supply

22 Ground

23 Ground

24 Ground

Data +

Data —

Ground

Socket Pin Layouts

RJ-45 UTP Connector

VGA Connector

6- Ground

Red -1

11- Not Used

7- Ground

8- Ground

9- Not used

10- Ground

Green- 2

Blue- 3

12- Not Used

13- H-Sync

14- V-Sync

15- Not Used

Not Used- 4

Ground- 5

Keyboard and Mouse Connector

Serial Port Connector

Parallel Port Connector

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Summary of the HP/Phoenix BIOS

This chapter and the following two chapters give an overview of the

features of the HP/Phoenix BIOS.

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4 Summary of the HP/Phoenix BIOS

HP/Phoenix BIOS Summary

The System ROM contains the POST (power-on self-test) routines, and the

BIOS: the System BIOS, video BIOS (for models with an integrated video

controller), network BIOS (for models with a network controller), and low

option ROM. This chapter, and the following one, give an overview of the

following aspects:

• menu-driven Setup with context-sensitive help (in US English only), de-

scribed next in this chapter.

• The address space, with details of the interrupts used, described at the

end of this chapter.

• The Remote Power-On (RPO), which is the mechanism for turning on the

computer remotely from the network, described later in this chapter.

• The Power-On-Self-Test or POST, which is the sequence of tests the com-

puter performs to ensure that the system is functioning correctly, de-

scribed in the next chapter.

The system BIOS is identified by the version number HA.07.xx. The

procedure for updating the System ROM firmware is described on page 38.

Press

, to run the Setup program, while the initial “Vectra” logo is being

displayed immediately after restarting the PC. Alternatively, press

view the summary configuration screen, an example of which is depicted on

the next page. By default, this remains on the screen for 20 seconds, but by

pressing

once, it can be held on the screen indefinitely until

pressed. Pressing

will cause the computer to be turned off.

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4 Summary of the HP/Phoenix BIOS

HP/Phoenix BIOS Summary

X A / 2 0 0 — C o p y r i g h t 1 9 9 7 H e w l e t t - P a c k a r d — H A . 0 7 . x x

Any line of text can be entered here as a ‘tatoo’ for the computer

BIOS version

HA.07.xx

N/A

PC Serial Number

LAN MAC address

FR54011111

CPU Date Code

08-0009-85-03-00

System RAM

Bank A

: 32 MB

Processor type

COM1

: Pentium

: 3F8H (Serial A)

: 2F8H (Serial B)

: None

: 32 MB (EDO)

: None

Bank B

COM2

Bank C

: None

COM3

Video RAM

System Cache

Video Device

1st IDE Device

2nd IDE Device

3rd IDE Device

4th IDE Device

: Not available

: 512KB (Synchronous)

: Matrox (External)

: HDD 2500 MB

: None

COM4

: None

LPT1

: 378H

LPT2

: None

LPT3

: None

Flexible Disk A

Flexible Disk B

Display type

: 1.44 MB

: None

: CD-ROM

: None

: Not Available

ISA PnP

: Not Installed

PCI Slot #1

PCI Slot #2

PCI Slot #3

: Not Installed

<F1> to continue, <F2> to run Setup, <F10> to power off, <F5> to retain

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4 Summary of the HP/Phoenix BIOS

Setup Program

To run the Setup program, interrupt the POST by pressing

F2=Setupmessage appears on the initial “Vectra” logo screen.

when the

The band along the top of the screen offers five menus: Main, Configuration,

Security, Power, and Exit. These are selected using the left and right arrow

keys. Each menu is discussed in the following sub-sections. For a more

complete description, see the User’s Guide that was supplied with the PC.

Main Menu

The Main Menu presents the user with a list of fields, such as “System Time”

and “Key auto-repeat speed”. These can be selected using the up and down

arrow keys, and can have their values changed using the

and

keys.

The “Item-Specific Help” field changes automatically as the user moves the

cursor between the fields. It tells the user what the presently highlighted

field is for, and what the options are.

Some fields are not changeable. Examples include fields that are for

information only, and fields whose contents become “frozen” by the setting

of a value in some other field. Such fields are displayed in a different color,

without the “[” and “]” brackets. When the user moves the cursor with the up

and down arrow keys, these fields are skipped.

Some fields disappear completely when a choice in another field makes their

appearance inappropriate (for example, the “Key auto-repeat speed” and

“Delay before auto-repeat” fields disappear when the user selects Yesin the

“Running Windows 95” field, since these parameters can be set within the

Windows 95 operating system).

Configuration Menu

The Configuration Menu does not have the same structure as the Main Menu

and Power Menu. Instead of presenting a list of fields, it offers the user a list

of sub-menus. Again, the user steps between the options using the up and

down arrow keys, but presses the

key to enter the chosen sub-

menu (and the key to go back again when finished).

If access to devices has been disabled in the Security Menu, then the

configuration of those devices on the Configuration Menu becomes frozen,

as shown in the diagram below for Serial port A. The field becomes starred,

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4 Summary of the HP/Phoenix BIOS

Setup Program

appears in a different color, and cannot be changed.

P h o e n i x B I O S S e t u p — C o p y r i g h t 1 9 8 5 - 9 5 P h o e n i x T e c h n o l o g i e s L t d .

C o p y r i g h t 1 9 9 7 H e w l e t t - P a c k a r d R e v . H A . 0 7 . x x

Configuration

I n t e g r a t e d I / O P o r t s

I t e m - S p e c i f i c H e l p

Enables or disables the

on-board parallel port at

the specific address.

‘Disabled’ frees

resources used by the

port.

Parallel port

[378h IRQ7]

Parallel port mode

Serial port A

[Centronix TM]

* 3F8h IRQ4

[Disabled]

Serial port B

[*] = The device is disabled for security reasons.

To enable it, use the Security/Hardware Protection menu.

F1 Help

ESC Exit

↕

↔

Select Item

Select Menu

F7/F8 Change Values

Enter Select >Sub-Menu

F9 Setup Defaults

F10 Previous Values

Disabling a device in the Configuration Menu (for example, Serial port B in

the diagram above) has the advantage of freeing the resources (such as

IRQs and peripheral addresses). Disabling a device in the Security Menu

disables the access, not the device. It does not have the advantage of freeing

the resources, but has the advantage of temporarily disabling the device

without losing the configuration settings.

The USB interface field, in the USB Devices sub-menu, is disabledby

default.

The Modem IRQ field, in the Modem sub-menu, is used when a modem

accessory has been installed. It does not enable the IRQ on the modem. It is

used to indicate, to the System BIOS, which of the IRQ lines should wake up

the PC when the modem receives a ringing tone. It is only applicable with an

APM 1.2 compatible operating system, such as Windows 95.

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4 Summary of the HP/Phoenix BIOS

Setup Program

Security Menu

Sub-menus are presented for changing the characteristics and values of the

User Password, the System Administrator Password, the amount of

protection against use of the system’s drives and network connections

(using the Hardware Protection sub-menu), and the amount of protection

against being able to boot from the system’s drives and network connections

(using the Start-Up Center sub-menu).

The minimum lengths of either type of password can be set to a specific

number of characters, or to none. The maximum length of each is 32

characters. A limit can be set for the maximum number of retries that are

permitted if the password is mistyped, and whether a delay should be

imposed (of successively increasing lengths: 4 seconds, 8 seconds, 16

seconds, and finally 32 seconds) before successive retries are accepted

(using the exponentialsetting for the “Lock Time Between Attempts”

field).

The “User Password” sub-menu grants access to the keyboard lock timer

option. Once this password has been set, the menu gives access to the main

sub-menu of user preferences.

Under the “Hardware Protection” sub-menu, the following devices can have

their access enabled/disabled: flexible disk controller, IDE controllers,

serial and parallel ports, network controller. Writes to the flexible disk can

be disabled, so as to prevent the exporting of data. Writes to the hard disk

drive boot sector can be disabled, for instance as a protection against

viruses.

Under the “Start-Up Center” sub-menu, the Setup program not only allows

the user to select which devices are enabledor disabledfor booting up

the system, but also indicates their order of precedence when more than one

is enabled: network, flexible disk drive, CD-ROM drive, or hard disk drive.

If the “Start from Network” field is not changeable with

wait until the 50% position on the histogram has been reached before

and

, either

from

pressing

there.

, or use

to go to the summary screen, and press

If the system will not boot from the network when there is a hard disk drive

present, disable the IDE and remove the hard disk drive.

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4 Summary of the HP/Phoenix BIOS

Setup Program

Power Menu

The “Power” menu allows the user to set the standby delay. It also allows the

system administrator to decide whether the network, serial ports, mouse, or

space bar are enabled as a means of reactivating the system from Standby

or Suspend. It is also possible to specify whether the network is enabled as

a means of reactivating the system from Off, using the remote power-on

(RPO) facility (as described in the next section of this chapter).

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4 Summary of the HP/Phoenix BIOS

Power Saving and Ergonometry

Power-On from Space-Bar

The power-on from the space-bar function is enabled, provided that:

• The computer is connected to a Windows 95 keyboard (recognizable by

the Power-On icon on the space bar).

• The computer is running the Windows 95 operating system.

• The function has not been disabled by setting SW-9 to closedon the sys-

tem board switches.

• The function has not been disabled in the “Power” menu of the Setup pro-

gram.

Soft Power Down

When the user requests the operating system to shutdown, the environment

is cleared, and the computer is powered off. At the time of release, the

drivers bear the version number A.01.00 (or SPD.02.01 for Windows NT

4.0). They are supplied with Windows NT and Windows 95. Soft Power

Down is not available with OS/2.

The hardware to do this, and the complement function, HP Off (as

described in the next section), is contained within the HP ASIC chip,

LittleBen. This chip is described on page 73.

HP Off

If the user attempts to turn the PC off at the status panel, the PC logic will

delay the shutting down of the power supply until it is safe to do so. HP Off

protects the user from some types of unintentional data loss, providing a

safe shutdown of running applications and unsaved files. It is available under

the Windows 95 operating system provided that the appropriate driver is

installed.

1 In the control panel, double-click on the Power icon.

2 Click on the HP Offtab to select HP Off, or on Immediate Power Offto

cancel it.

3 Select the time-out period, between one and five seconds.

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4 Summary of the HP/Phoenix BIOS

Power Saving and Ergonometry

The time-out period is the delay during which the power-down command

can be cancelled (whilst the About to shut down Windowsmessage is

displayed on the screen). If the user cancels, the computer is returned to

normal operation; otherwise, the computer goes on to check if there are any

unsaved files. If there are, it offers three choices: yes(to saving the unsaved

changes, followed by shutdown), no(thereby shutting down without saving

the changes), and cancel(to return to normal operation).

Remote Power-On (RPO)

Remote power-on (RPO) provides a way to turn on the computer from a

communication channel, such as a Network or Modem, using facilities that

have been incorporated in the Little Ben chip and the ExtStart connector. It

allows system administrators, and authorized users, switch on the computer

from anywhere over an Ethernet network, perform remote administration or

other tasks, and return it to Off or Suspend mode afterwards.

Magic Packet

Magic packet is a standard for remote power-on and remote wake-up

developed by HP and Advanced Micro Devices (AMD). The standard defines

a Magic Packet frame as the computer’s unique Ethernet Media Access

Control (MAC) address (which it has stored in an EEPROM on the network

board), repeated 16 times and encoded in a valid network packet.

Any Magic Packet-compatible management application (such as HP Open-

View Workgroup Node Manager) can send a Magic Packet frame. An

administrator can do this manually, or can incorporate it into a management

script.

The packet travels over any type of Ethernet LAN to the target PC.

The only component not completely off in the computer is the network chip,

which rests in a special low power mode. Power is supplied by a line called

VStandby, on the ExtStart connector, whose pin layout is shown in the table

on page 58, as long as the power cord is plugged in. The independent mini

power supply provides the power necessary to keep one part of the network

chip ready to receive a wake-up signal (see page 15 for electrical

specifications). This is the only signal it can respond to in this state.

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4 Summary of the HP/Phoenix BIOS

Power Saving and Ergonometry

The network chip sends a signal over the External Start connector, where it

is received by the special network remote power chip. This in turn switches

on the main power supply.

The PC starts normally from whatever operating system is installed, just as if

the power supply had been switched on from the external power switch.

The display does not itself need to have RPO. If a password has been set, the

Start with keyboard lockedoption must be enabled, to allow the oper-

ating system to boot.

Activity within the Setup Program

Since the user is not physically present, the level of security must be tighter.

There must be a distinction between the user-boot process, and the RPO-

boot process. HP provides all the necessary Setup options to keep users

from interfering with the computer during the remote session.

Administrators can set the management package to toggle on options like:

• Keyboard lock mode: This offers the same suite of security features as the

external “keyboard lock” button (keyboard, mouse, reset and power but-

ton disabled).

• Floppy disable: this makes sure the computer cannot be disrupted by re-

booting from a diskette.

RPO is available when the POST routines have finished executing. It is

initialized by an SMI signal which is triggered from the mains power button.

A power failure when the computer is in RPO mode will deactivate the RPO

feature. RPO is intended for resource management (such as virus cleaners,

nightly backups, etc.), not for crisis management (thunderstorm recovery,

power failure, etc.).

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4 Summary of the HP/Phoenix BIOS

Power Saving and Ergonometry

Little Ben

Little Ben is an HP application specific integrated circuit (ASIC), designed

to be a companion to the Super I/O chip, that is connected between the

chip-set and the processor. It contains the following:

• BIOS timer

❒ hardware wired 50 ms long 880 Hz beep module.

❒ automatic blinker that feeds the LEDs module with a 1 Hz oscillator

signal.

• security protection (access, flash and anti-virus protection)

❒ For 128, 256 or 512 KB Flash EEPROMs.

❒ For the Super I/O space: the Serial EEPROM, serial ports, parallel port

and mass storage drives (disable write on Flexible Disk Drive, disable

boot on any drive, disable use of any embedded drive)

• hard and soft control for the power supply (available with Windows NT

and Windows 95, but not with OS/2)

• Advanced power management (APM) version 1.2 (available with Win-

dows 95 and OS/2, but not with Windows NT)

• glue logic (such as programmable chip selects)

The computer can be turned on by typing the space-bar on the keyboard, or

when it receives an external signal from a network board. The power

consumption has been kept as low as possible. When VccState and

PowerGood pins are both low, all output pins are in tri-state mode, except

for RemoteOnBen which continues to be driven. This allows the computer

to be powered from the standby power supply, and to be restarted even

after a power loss has occurred.

When the user requests a ShutDown from the operating system, the

environment is first cleared. Any request to turn off the computer, from the

control panel, or from the operating system, can only be granted if the

computer is not locked by Little Ben’s lock bit (otherwise the power remains

on, a red light is illuminated, and the buzzer is sounded).

The SMI_OFF signal is asserted if the Hard Soft Power Down mode (HSPD)

is enabled when Little Ben is instructed to turn off the computer (via the

status panel or soft power down). The BIOS first performs some RPO

initialization, and then proceeds to power down the computer. If the watch-

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4 Summary of the HP/Phoenix BIOS

Power Saving and Ergonometry

dog timer detects that the BIOS is inactive (and not reloading the timer

once every 6 seconds), the computer is turned off without further BIOS

acknowledgment.

The following table summarizes the main signals that drive or are driven by

the Little Ben chip.

Signal

SMI_OFF

Address

Description

User wants to power off: computer enters RPO shutdown mode

(computer clock, HDDs all stopped; only RTC, Little Ben and

network board still active)

SMI_RWU ➹

pin 69, LBen channel 7 Signal from RTC, FAX, control panel, and power key on keyboard.

Magic Frame from network board: computer wakes up from RPO

mode.

CoffeeBreak# ➷

ASL# ➷

pin 66, LBen channel 0 Connected to the lock button (coffee break) on the control panel.

pin 65, LBen channel 4 Connected to the Super IO Auto Soft Lock (ASL) timer.

Reset by an interrupt from the keyboard or mouse.

APM chip-set SMI# ➷ pin 67, LBen channel 2 SMIs from the chip set pass first to Little Ben, then are sent on to

the processor on the SMI# line

SMI#

StopClk#

Stops the processor clock

SMI_CONFIG

SMI_ACT#

SMI_TRIG_EN

SMI channels

SMI_EN

Tells Little Ben that the processor is in SMM

index Ah

index Bh, bit 0

index 10h

index 11h, bit 1

index 11h, bit 2

Used to enable individual SMI channels during the boot process

Enable general SMI generation (during the boot process)

This register is cleared when the computer is re-booted

When set, computer mains button is disabled

When set, Flash ROM is write protected; Super IO space is write

protected (Serial EEPROM access, serial ports configuration,

parallel port configuration, flexible disk drive configuration)

SMI status register

index 11h, bit 4

pin 21

When set, flexible disk drive is write protected

Not used

PWD_EN

index Dh, bit 3

Super Secure Mode

pin 64 (shared with

FLPWPT#)

Not used

➹ indicates triggered on a rising edge; ➷ indicates triggered on a falling

edge

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4 Summary of the HP/Phoenix BIOS

Power Saving and Ergonometry

Advanced Power Management (APM)

The BIOS is APM 1.2 compliant, providing it with facilities for advanced

power management (APM). APM is incorporated in Windows for

Workgroups 3.11, Windows 95 and OS/2, but not Windows NT. A file called

power.exeis needed for APM under DOS.

APM is a standard, defined by Intel and Microsoft, for a power-saving mode

that is applicable under a wide range of operating systems. It supports the

following modes: Fully-on, Standby, Suspend, Hibernation and Off. Of

these, APM 1.2 supports Fully-on, Standby, Suspend and Off, as

summarized in the following table.

Fully-On

Standby

Setup menu

Suspend

Off

Brought about using:

Resume events:

Operating system

Status panel button

Keyboard

Mouse

Keyboard

Space-bar

Fax / Modem

Network (RWU)

Network (RPO)

Resume delay:

Processor

Instantaneous

A few seconds

Halted

Boot delay

Halted

Normal speed

Clock throttled (divided

by 8)

Hard disk drive

Display

Normal speed

Normal operation

24 W to 47 W

Normal speed

Halted

Blanked (<30 W)

Blanked (<5 W typ)

< 30 W

Blanked (<5 W typ)

< 3 W

Power consumption

The Suspend mode is managed at the operating system level only, from the

Windows 95 Start menu. There is no longer the inter-activity between the

Setup program and the operating system, and no longer a “sleep at” item on

the Setup program menus, to avoid the BIOS from shutting down the system

at the wrong moment.

RPO defines a variation from the standard Off state. In RPO mode, the main

CPU hardware is off while a RPO function is powered by a power supply

called VStandby. VStandby is active as soon as the computer is plugged in.

RPO hardware can produce a triggering signal which turns on the computer.

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4 Summary of the HP/Phoenix BIOS

Power Saving and Ergonometry

The following diagram gives a simplified view of the useful states that the

computer can be in: the three On states (Fully-On, Standby and

Suspend), the RPO state (when the CPU is Off, and the RPO hardware is

the state that is caused by power failure or unplugging the computer.

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4 Summary of the HP/Phoenix BIOS

Power Saving and Ergonometry

The following diagram gives a more accurate, more detailed account of the

valid state changes.

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4 Summary of the HP/Phoenix BIOS

Power Saving and Ergonometry

Desktop Management Interface (DMI)

HP TopTOOLS 2 is an integrated, easy-to-use desktop management

application for efficient inventory, configuration, fault and security

management. It is fully DMI compliant. It provides facilities for real-time

monitoring and management of over 300 attributes of the PC (both the local

PC, and remote ones over the network).

HP Lock

The purpose of the HP Lock utility is to provide a more convenient, and

more dynamic access to the security features of the PC than was previously

possible. (Previously, it had been necessary to restart the PC, and to call the

Setup program). It is available, on the HP Vectra VL 5/xxx Series 5 PC

only, running the Windows 95 operation system.

Facilities are provided for:

• Passwords

• Lock options (such as screen hiding and screen saving)

• Start-up protection

• Disk drive access (enabled or disabled)

• Communications port access (enabled or disabled)

These can be accessed by clicking on the “Lock my HP Vectra PC” menu in

the Control Panel. You can then use the “How to Lock”, “Lock Options” and

“Advanced” menus.

The two options “Lock when entering Energy Saving Mode” and “Lock when

activating Screen Saver” are currently under development. You will be able

to download the completed software form the HP World Wide Web site:

http://www.hp.com/go/vectrasupport/.

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4 Summary of the HP/Phoenix BIOS

BIOS Addresses

This section provides a summary of the main features of the HP system

BIOS. This is software that provides an interface between the computer

hardware and the operating system.

System Memory Map

Reserved memory used by accessory boards must be located in the area

from C8000h to EFFFFh.

0 - 3FFh

Interrupt vector table

BIOS data area

640 KB: The addresses

0-9FFFFh are collectively

known as the Base

memory area

400h - 4FFh

500h - 9EFFFh

9F000h - 9FFFFh

A0000h - BFFFFh

C0000h - C7FFFh

C8000h - D7FFFh

Extended BIOS data area

128 KB: Video memory area

32 KB: Video BIOS area

64 KB: available for accessory boards

(used by the boot ROM, if configured in the Setup program)

96 KB: available after the POST (for upper memory block, UMB, for example)

64 KB: System BIOS area

D8000h - EFFFFh

F0000h - FFFFFh

100000h - FFFFFFFFh

1 MB plus: Extended memory

Product Identification

The reserved addresses in the 64 KB BIOS ROM data area, which contain

various product identification and BIOS identification strings, are no longer

accessed directly. Instead, the information is obtained from utilities in the

Desk Management Interface (DMI).

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4 Summary of the HP/Phoenix BIOS

BIOS Addresses

HP I/O Port Map (I/O Addresses Used by the System )

Peripheral devices, accessory devices and system controllers are accessed

via the system I/O space, which is not located in system memory space. The

64 KB of addressable I/O space comprises 8-bit and 16-bit registers (called

I/O ports) located in the various system components. When installing an

accessory board, ensure that the I/O address space selected is in the free

area of the space reserved for accessory boards (100h to 3FFh).

The following address map is not BIOS dependent, but is determined by the

operating system. However, the Setup program can be used to change some

settings. Beware that some of the I/O addresses are allocated dynamically.

I/O Address Ports

Function

0000h - 000Fh

0020h - 0021h

0040h - 0043h

0060h, 0064h

0061h

DMA controller 1

Interrupt controller 1

Interval timer 1

Keyboard controller

System speaker, or NMI status and control

NMI mask register, RTC and CMOS address

RTC and CMOS data

0070h

0071h

0081h - 0083h, 008Fh

0092h

DMA low page register

Alternate reset and A20 Function

Interrupt controller 2

00A0h - 00A1h

00C0h - 00DFh

00EAh - 00EBh

00F0h - 00FFh

0102h

DMA controller 2

Internal port

Co-processor error

Graphics controller (Matrox MGA)

IDE hard disk drive controller secondary channel

IDE hard disk drive controller primary channel

Joystick port (Soundblaster)

0170h - 0177h

01F0h - 01F7h

0200h - 0207h

1. If configured (legacy resources only).

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4 Summary of the HP/Phoenix BIOS

BIOS Addresses

I/O Address Ports

Function

0220h - 022Fh

0240h - 024Fh

0260h - 026Fh

0278h - 027Fh

0279h

Audio interface 1 (Soundblaster)

Audio interface 2 (Soundblaster)

Audio interface 3 (Soundblaster)

Parallel port 2

IO read data port for ISA Plug and Play enumerator

Audio interface 4 (Soundblaster)

Serial port 4

0280h - 028Fh

02E8h - 02EFh

02F8h - 02FFh

0300h - 0301h

0330h - 0331h

0370h - 0371h

0372h - 0375h

0376h

Serial port 2

MPU-401 MIDI interface 2 (Soundblaster)

MPU-401 MIDI interface 1 (Soundblaster)

Ultra I/O controller

Secondary flexible disk drive controller

IDE hard disk drive controller secondary channel

Secondary flexible disk drive controller

Parallel port 1

0377h

0378h - 037Ah

0388h - 038Bh

03B0h - 03DFh

03E8h - 03EFh

03F0h - 03F5h

03F6h

Ad-lib / FM synthesized music (Soundblaster)

Graphics controller (Matrox MGA)

Serial port 3

Primary flexible disk drive controller

IDE hard disk drive controller primary channel

Primary flexible disk drive controller

Serial port 1

03F7h

03F8h - 03FFh

0496h - 049Fh

0678h - 067Bh

0778h - 077Bh

0CF8h - 0CFFh

Internal ports (Little Ben)

Parallel port 2 if ECP mode is selected

Parallel port 1 if ECP mode is selected

Configuration registers for PCI devices

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4 Summary of the HP/Phoenix BIOS

BIOS Addresses

DMA Channel Controllers

Only “I/O-to-memory” and “memory-to-I/O” transfers are allowed.

“I/O-to-I/O” and “memory-to-memory” transfers are disallowed by the

hardware configuration.

The system controller supports seven DMA channels, each with a page

following table summarizes how the DMA channels are allocated.

First DMA controller (used for 8-bit transfers)

Channel

Function

Available

SoundBlaster or ECP mode for parallel port

Flexible disk I/O

ECP mode for parallel port or SoundBlaster

Second DMA controller (used for 16-bit transfers)

Channel

Function

Cascade from first DMA controller

SoundBlaster or Available

Available

Available or SoundBlaster

Interrupt Controllers

The system has two 8259A compatible interrupt controllers. They are

arranged as a master interrupt controller and a slave that is cascaded

through the master.

The following table shows how the master and slave controllers are con-

nected. The Interrupt Requests (IRQ) are numbered sequentially, starting

with the master controller, and followed by the slave.

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4 Summary of the HP/Phoenix BIOS

BIOS Addresses

IRQ (Interrupt Vector)

IRQ0(08h)

Interrupt Request Description

System Timer

Keyboard Controller

IRQ1(09h)

IRQ2(0Ah)

Slave IRQ

IRQ8(70h)

IRQ9(71h)

IRQ10(72h)

IRQ11(73h)

IRQ12(74h)

IRQ13(75h)

IRQ14(76h)

IRQ15(77h)

Cascade connection from INTC2 (Interrupt Controller 2)

Real Time Clock

Available for accessory board (ISA/PCI)

SoundBlaster 3, or Available for accessory board (ISA/PCI)

Available for accessory board (ISA/PCI)

Mouse, or ISA accessory board

Co-processor

IDE, or ISA accessory board

Secondary IDE or ISA/PCI accessory board

Serial Port 2, Serial Port 4, or ISA accessory board

Serial Port 1, Serial Port 3, or ISA accessory board

SoundBlaster 1, Parallel Port 2, or ISA accessory board

Flexible Disk Controller

IRQ3(0Bh)

IRQ4(0Ch)

IRQ5(0Dh)

IRQ6(0Eh)

IRQ7(0Fh)

SoundBlaster 2, Parallel Port 1, or ISA accessory board

Using the Setup program:

• IRQ3 can be made available by disabling serial ports 2 and 4.

• IRQ4 can be made available by disabling serial ports 1 and 3.

• IRQ5 can be made available by disabling the parallel port 2.

• IRQ7 can be made available by disabling parallel ports 1 and 2.

PCI Interrupt Request Lines

PCI devices generate interrupt requests using up to four PCI interrupt

request lines (INTA#, INTB#, INTC#, and INTD#).

When a PCI device makes an interrupt request, the request is re-directed to

the system interrupt controller. The interrupt request will be re-directed to

one of the IRQ lines made available for PCI devices.

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4 Summary of the HP/Phoenix BIOS

BIOS Addresses

The PCI interrupt lines A, B, C and D are spread across the four inputs of

the interrupt router (which is part of the PCI/ISA bridge, in the PIIX3 chip).

Since most PCI devices are single-function, this allows for an even

distribution of the lines. The distribution is shown in the following diagram.

In this, Slot 4 is present only on minitower models (and is omitted on

desktop models); Slot R refers to the PCI proprietary slot on the rear side of

the double sided backplane of desktop models (and is omitted on minitower

models).

Integrated

graphics

Slot 2

Slot 1

Slot 3 or R

Slot 4 (MT)

A B C D

PCI/ISA

Bridge

PCI interrupts are then mapped into ISA interrupts inside the PCI/ISA

Bridge (in the PIIX3 chip), by configuring registers 60h through 63h.

Bit

Description

Routing of interrupts: when enabled, this bit routes the PCI interrupt signal to the PC-

compatible interrupt signal specified in bits[3:0]. At reset, this bit is disabled (set to 1)

6:4

3:0

Reserved: read as 000

IRQx# Routing Bits: these bits specify which IRQ signal to generate.

Possible values are: 3, 4, 5, 6, 7, 9, 10, 11, 12, 14, 15.

The possible choices given by the Setup program are 9, 10, 11, 15. If some of

these are unavailable due to ISA cards, some interrupts will have to be

shared.

The IDE controller is actually configured in legacy mode, and uses IRQ 14

(IRQ 15 for the secondary channel). The mode setting is in configuration

byte 09h of the IDE controller, device 01h.

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Power-On Self-Test and Error Messages

This chapter describes the Power-On Self-Test (POST) routines, which are

contained in the computer’s ROM BIOS, the error messages which can

result, and the suggestions for corrective action.

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5 Power-On Self-Test and Error Messages

Order in Which the Tests are Performed

Each time the system is powered on, or a reset is performed, the POST is

executed. The POST process verifies the basic functionality of the system

components and initializes certain system parameters.

The POST starts by displaying a graphic screen with the initial “Vectra” logo

when the PC is restarted. If the POST detects an error, the error message is

displayed inside a view system errors screen, in which the error message

utility (EMU) not only displays the error diagnosis, but the suggestions for

corrective action (see page 89 for a brief summary). Error codes are no

longer displayed.

Devices, such as memory and newly installed hard disks, are configured

automatically. The user is not requested to confirm the change. Newly

removed hard disks are detected, and the user is prompted to confirm the

new configuration by pressing

. Note, though, that the POST does not

detect when a hard disk drive has been changed.

During the POST, the BIOS and other ROM data is copied into high-speed

shadow RAM. The shadow RAM is addressed at the same physical location

as the original ROM in a manner which is completely transparent to

applications. It therefore appears to behave as very fast ROM. This

technique provides faster access to the system BIOS firmware.

The following table lists the POST routines in the order in which they are

executed (from the shadow RAM). If the POST is initiated by a soft reset

De le te

and

, the RAM tests are not executed and shadow RAM is

not cleared. In all other respects, the POST executes in the same way

following power-on or a soft reset.

Test

Description

System BIOS Tests

Tests the LEDs on the control panel.

LED Test

Calculates an 8-bit checksum. Test failure causes the boot process to abort.

System (BIOS) ROM Test

Tests the RAM refresh timer circuitry. Test failure causes the boot process

to abort.

RAM Refresh Timer Test

Interrupt RAM Test

Checks the first 64 KB of system RAM used to store data corresponding to

various system interrupt vector addresses. Test failures cause the boot

process to abort.

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5 Power-On Self-Test and Error Messages

Order in Which the Tests are Performed

Tests the system ROM BIOS and shadows it. Failure to shadow the ROM

BIOS will cause an error code to display. The boot process will continue, but

the system will execute from ROM. This test is not performed after a soft

De le te

Shadow the System ROM BIOS

reset (using

and

Checks the serial EEPROM and returns an error code if it has been

corrupted. Copies the contents of the EEPROM into CMOS RAM.

Load CMOS Memory

CMOS RAM Test

Checks the CMOS RAM for start-up power loss, verifies the CMOS RAM

checksums. Test failure causes error codes to display.

Tests the processor’s internal level-one cache RAM. Test failure causes an

error code to display and the boot process to abort.

CPU Cache Memory Test

Video Tests

Initializes the video subsystem, tests the video shadow RAM, and, if

required, shadows the video BIOS. A failure causes an error code to display,

but the boot process continues.

Initialize the Video

System Board Tests

Downloads the 8042 and invokes the 8042 internal self-test. A failure

causes an error code to display.

8042 Self-Test

Tests Timer 0 and Timer 2. Test failure causes an error code to display.

Timer 0/Timer 2 Test

DMA Subsystem Test

Checks the DMA controller registers. Test failure causes an error code to

display.

Tests the Interrupt masks, the master controller interrupt path (by forcing

an IRQ0), and the industry-standard slave controller (by forcing an IRQ8).

Test failure causes an error code to display.

Interrupt Controller Test

Checks the real-time clock registers and performs a test that ensures that

the clock is running. Test failure causes an error code to display.

Real-Time Clock Test

Audio Test

If the audio board is present, invokes a built-in self-test. Test failure causes

an error code to display.

Memory Tests

Verifies the address independence of real-mode RAM (no address lines stuck

together). Test failure causes an error code to display.

RAM Address Line

Independence Test

Sizes and clears the protected mode (extended) memory and writes the

value into CMOS bytes 30h and 31h. If the system fails to switch to

protected mode, an error code is displayed.

Size Extended Memory

Read/write test on real-mode RAM. (This test is not done during a reset

De le te

Real-Mode Memory Test (First using

and

). The test checks each block of

640KB)

system RAM to determine how much is present. Test failure of a 64 KB

block of memory causes an error code to display, and the test is aborted.

Tests shadow RAM in 64 KB segments (except for segments beginning at

A000h, B000h, and F000h). If they are not being used, segments C000h,

D000h and E000h are tested. Test failure causes an error code to display.

Shadow RAM Test

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5 Power-On Self-Test and Error Messages

Order in Which the Tests are Performed

Tests protected RAM in 64 KB segments above 1 MB. (This test is not done

Protected Mode RAM Test

(Extended RAM)

De le te

during a reset using

error code to display.

and

). Test failure causes an

Keyboard / Mouse Tests

Invokes a built-in keyboard self-test of the keyboard’s microprocessor and

tests for the presence of a keyboard and for stuck keyboard keys. Test

failure causes an error code to display.

Keyboard Test

If a mouse is present, invokes a built-in mouse self-test of the mouse’s

microprocessor and for stuck mouse buttons. Test failure causes an error

code to display.

Mouse Test

If the network board is present, invokes a built-in self-test. Test failure

causes an error code to display.

Network Test

Tests of Flexible Disk Drive A

Tests for proper operation of the flexible disk controller. Test failure causes

an error code to display.

Flexible Disk Controller

Subsystem Test

Coprocessor Tests

Checks for proper operation of the numeric coprocessor part of the

processor. Test failure causes an error code to display.

Internal Numeric Coprocessor

Test

Communication Port Tests

Tests the integrated parallel port registers, as well as any other parallel

ports. Test failure causes an error code to display.

Parallel Port Test

Serial Port Test

Tests the integrated serial port registers, as well as any other serial ports.

Test failure causes an error code to display.

Hard Disk Drive Tests

Tests for proper operation of the hard disk controller. Test failure causes an

error code to display. The test does not detect hard disk replacement or

changes in the size of the hard disk.

Hard Disk Controller Subsystem

Test

System Configuration Tests

Initiation of the system generation (SYSGEN) process, which compares the

configuration information stored in the CMOS memory with the actual

system. If a discrepancy is found, an error code will be displayed.

System Generation

Configures any Plug and Play device detected (either PCI or ISA):

❒ All PCI devices, and any ISA device necessary for loading the operating

system will be configured for use.

❒ Any ISA device that is not required for loading the operating system, will

be initialized (prepared for loading of a device driver), but not fully

configured for use.

Plug and Play

Configuration

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5 Power-On Self-Test and Error Messages

Error Message Summary

The POST section of the HP BIOS no longer displays numeric error codes

(such as 910B) but gives a self-explanatory, descriptive diagnosis, and a list

of suggestions for corrective action. The following table summarizes the

most significant of the problems that can be reported.

Message

Explanation or Suggestions for Corrective Action

Operating system not found

Check whether the disk, HDD, FDD or CD-ROM disk drive is

connected.

If it is connected, check that it is detected by POST.

Check that your boot device is enabled on the Setup Security

menu.

If the problem persists, check that the boot device contains the

operating system.

Missing operating system

If you have configured HDD user parameters, check that they are

correct. Otherwise, use HDD type “Auto” parameters.

Failure fixed disk

(preceded by a 30” time-out)

Check that HDD is connected.

Check that HDD is detected in POST.

Check that boot on hard disk drive is enabled in Setup.

Diskette Drive A (or B) error

System battery is dead

Check whether the diskette drive is connected. Check Setup for

the configuration.

You may get this message if the computer is disconnected for a

few days. When you Power-on the computer, run Setup to update

the configuration information. The message should no longer be

displayed. Should the problem persist, replace the battery.

Keyboard error

Check that the keyboard is connected.

Clear CMOS.

Resource Allocation Conflict -PCI

device 0079 on system board

Video Plug and Play interrupted or

You may have powered your computer Off/On too quickly and the

failed. Re-enable in Setup and try again computer turned off Video plug and play as a protection.

System CMOS checksum bad - run

Setup

CMOS contents have changed between 2 power-on sessions. Run

Setup for configuration.

I/O device IRQ conflict

Serial ports A and B may have been assigned the same IRQ. Assign

a different IRQ to each serial port and save the configuration.

No message, system “hangs” after

POST

Check that cache memory and main memory are correctly set in

their sockets.

Other

An error message may be displayed and the computer may “hang”

for 20 seconds and then beep. The POST is probably checking for a

mass storage device which it cannot find and the computer is in

Time-out Mode. After Time-out, run Setup to check the

configuration.

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5 Power-On Self-Test and Error Messages

Beep Codes

If a terminal error occurs during POST, the system issues a beep code before

attempting to display the error. Beep codes are useful for identifying the

error when the system is unable to display the error message.

Beep Numeric

Beep Pattern

Description

Code

B4h

This does not indicate an error. There is one short beep before

system startup.

— - -

98h

16h

20h

22h

2Ch

2Eh

30h

46h

58h

Video configuration failure or option ROMs check-sum failure

BIOS ROM check-sum failure

— - - - - - - -

— - - - — —

— - - - — - - -

— - - - - - - - —

— - - - - - - - - - -

— - - - - — —

- - — - - - - -

- - - - - - - —

0223

0300

0303

0340

0343

0400

2023

2230

DRAM refresh test failure

8742 Keyboard controller test failure

RAM failure

RAM failure on data bits in low byte of memory bus

RAM failure on data bits in high byte of memory bus

ROM copyright notice check failure

Unexpected interrupts test failure

— - - — - - - -

02022

Continuous beeps. Keyboard error

Where digits 1, 2, 3, 4 represent the number of short beeps, and 0

represents the occurrence of a single long beep.

Lights on the Status Panel

When the computer is first powered on, the power-on light on the status

panel illuminates yellow for about a second before changing to green. This

change of color is caused by the execution of an instruction early in the

System BIOS code.

If the light remains at yellow, therefore, it indicates a failure of the processor

or the System ROM in the instruction-fetch process. Check that the

processor is correctly seated in its socket, and that its VRM is also correctly

seated.

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