Freescale Semiconductor Computer Hardware 56F8122 User Manual

—

Enable lead time

Master

Slave

10-12

ELD

ELG

—

Enable lag time

Master

Slave

—

100

—

Clock (SCK) high time

Master

Slave

10-9, 10-10,

17.6

—

Clock (SCK) low time

Master

Slave

10-12

16.67

—

Data set up time required for inputs

Master

Slave

10-9, 10-10,

—

Data hold time required for inputs

Master

Slave

10-9, 10-10,

—

Access time (time to data active from high-impedance

state)

Slave

10-12

4.8

3.7

Disable time (hold time to high-impedance state)

Slave

15.2

Data Valid for outputs

Master

Slave (after enable edge)

10-9, 10-10,

—

4.5

20.4

Data invalid

Master

Slave

10-9, 10-10,

—

Rise time

Master

Slave

10-9, 10-10,

—

11.5

10.0

Fall time

Master

Slave

10-9, 10-10,

—

9.7

9.0

1. Parameters listed are guaranteed by design.

56F8322 Technical Data, Rev. 10.0

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Preliminary

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(Input)

SS is held High on master

SCLK (CPOL = 0)

(Output)

SCLK (CPOL = 1)

(Output)

MISO

MSB in

Bits 14–1

LSB in

t (ref)

(Input)

MOSI

Master MSB out

Bits 14–1

Master LSB out

(Output)

Figure 10-9 SPI Master Timing (CPHA = 0)

(Input)

SS is held High on master

SCLK (CPOL = 0)

(Output)

SCLK (CPOL = 1)

(Output)

MISO

MSB in

Bits 14–1

LSB in

(Input)

_DV(ref)

t (ref)

MOSI

Master MSB out

Bits 14– 1

Master LSB out

(Output)

Figure 10-10 SPI Master Timing (CPHA = 1)

56F8322 Techncial Data, Rev. 10.0

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Serial Peripheral Interface (SPI) Timing

(Input)

ELG

SCLK (CPOL = 0)

(Input)

ELD

SCLK (CPOL = 1)

(Input)

MISO

Slave MSB out

Bits 14–1

Slave LSB out

(Output)

MOSI

MSB in

Bits 14–1

LSB in

(Input)

Figure 10-11 SPI Slave Timing (CPHA = 0)

(Input)

SCLK (CPOL = 0)

(Input)

ELG

ELD

SCLK (CPOL = 1)

(Input)

MISO

Slave MSB out

Bits 14–1

Slave LSB out

(Output)

MOSI

MSB in

Bits 14–1

LSB in

(Input)

Figure 10-12 SPI Slave Timing (CPHA = 1)

56F8322 Technical Data, Rev. 10.0

Freescale Semiconductor

Preliminary

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10.10 Quad Timer Timing

1, 2

Table 10-19 Timer Timing

Characteristic

Timer input period

Symbol

Min

Max

—

Unit

See Figure

2T + 6

1T + 3

1T - 3

Timer input high / low period

Timer output period

—

INHL

—

OUT

Timer output high / low period

0.5T - 3

—

OUTHL

1. In the formulas listed, T = the clock cycle. For 60MHz operation, T = 16.67ns.

2. Parameters listed are guaranteed by design.

Timer Inputs

INHL

Timer Outputs

OUTHL

OUT

Figure 10-13 Timer Timing

10.11 Quadrature Decoder Timing

Note: The Quadrature Decoder is NOT available in the 56F8122 device.

1, 2

Table 10-20 Quadrature Decoder Timing

Characteristic

Quadrature input period

Symbol

Min

Max

Unit

See Figure

10-14

4T + 12

—

Quadrature input high / low period

Quadrature phase period

2T + 6

1T + 3

—

10-14

1. In the formulas listed, T = the clock cycle. For 60MHz operation, T=16.67ns.

2. Parameters listed are guaranteed by design.

56F8322 Techncial Data, Rev. 10.0

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Serial Communication Interface (SCI) Timing

Phase A

(Input)

Phase B

(Input)

Figure 10-14 Quadrature Decoder Timing

10.12 Serial Communication Interface (SCI) Timing

Table 10-21 SCI Timing

Characteristic

Symbol

Min

—

Max

/16)

Unit

See Figure

—

Mbps

Baud Rate

MAX

RXD

0.965/BR

1.04/BR

10-15

RXD Pulse Width

TXD

10-16

TXD Pulse Width

1. Parameters listed are guaranteed by design.

2. f is the frequency of operation of the system clock in MHz, which is 60MHz for the 56F8322 device and 40MHz for the

MAX

56F8122 device.

3. The RXD pin in SCI0 is named RXD0 and the RXD pin in SCI1 is named RXD1.

4. The TXD pin in SCI0 is named TXD0 and the TXD pin in SCI1 is named TXD1.

RXD

SCI receive

data pin

RXD

(Input)

Figure 10-15 RXD Pulse Width

TXD

SCI receive

data pin

TXD

(Input)

Figure 10-16 TXD Pulse Width

56F8322 Technical Data, Rev. 10.0

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Preliminary

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10.13 Controller Area Network (CAN) Timing

Note: CAN is NOT available in the 56F8122 device.

Table 10-22 CAN Timing

Characteristic

Baud Rate

Bus Wake-up detection

Symbol

Min

Max

Unit

See Figure

—

Mbps

—

CAN

µs

10-17

—

WAKEUP

IPBUS

1. Parameters listed are guaranteed by design

MSCAN_RX

CAN receive

data pin

WAKEUP

(Input)

Figure 10-17 Bus Wakeup Detection

10.14 JTAG Timing

Table 10-23 JTAG Timing

Characteristic

Symbol

Min

Max

Unit

See Figure

TCK frequency of operation using

SYS_CLK/8

MHz

10-18

EOnCE

TCK frequency of operation not

SYS_CLK/4

using EOnCE

TCK clock pulse width

—

10-18

10-19

TMS, TDI data set-up time

TMS, TDI data hold time

TCK low to TDO data valid

TCK low to TDO tri-state

—

1. TCK frequency of operation must be less than 1/8 the processor rate.

56F8322 Techncial Data, Rev. 10.0

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JTAG Timing

1/f

V_M

V_IL

V_IH

TCK

(Input)

V_M= V_IL+ (V_IH– V_IL)/2

Figure 10-18 Test Clock Input Timing Diagram

TCK

(Input)

TDI

TMS

Input Data Valid

(Input)

TDO

(Output)

Output Data Valid

TDO

(Output)

TDO

(Output)

Output Data Valid

Figure 10-19 Test Access Port Timing Diagram

56F8322 Technical Data, Rev. 10.0

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Preliminary

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10.15 Analog-to-Digital Converter (ADC) Parameters

Table 10-24 ADC Parameters

Characteristic

Symbol

Min

Typ

—

Max

Unit

Input voltages

Resolution

REFH

ADIN

REFL

—

Bits

INL

—

+/- 2.4

+/- 0.7

+/- 3.2

< +1

Integral Non-Linearity

LSB

Differential Non-Linearity

DNL

Monotonicity

GUARANTEED

—

ADC internal clock

0.5

MHz

ADIC

Conversion range

—

REFH

REFL

ADC channel power-up time

ADPU

cycles

AIC

—

ADC reference circuit power-up time

Conversion time

VREF

ADC

cycles

AIC

Sample time

—

ADS

cycles

Input capacitance

—

ADI

—

Input injection current , per pin

ADI

Input injection current, total

—

ADIT

current

1.2

REFH

VREFH

ADC A current

ADC B current

—

ADCA

ADCB

µA

Quiescent current

+/- .004

+/- 26

ADCQ

Uncalibrated Gain Error (ideal)

Uncalibrated Offset Voltage

+/- .01

+/- 32

—

GAIN

OFFSET

See Figure 10-20

0.008597

-2.8

LSBs

—

Calibrated Absolute Error

CAL

CF1

—

Calibration Factor 1

CF2

—

Calibration Factor 2

Crosstalk between channels

Common Mode Voltage

—

-60

—

- V

) / 2

common

REFH

REFLO

Signal-to-noise ratio

SNR

—

64.6

—

56F8322 Techncial Data, Rev. 10.0

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Analog-to-Digital Converter (ADC) Parameters

Table 10-24 ADC Parameters (Continued)

Characteristic

Signal-to-noise plus distortion ratio

Total Harmonic Distortion

Symbol

Min

Typ

Max

Unit

SINAD

THD

—

59.1

60.6

61.1

9.6

—

Spurious Free Dynamic Range

SFDR

ENOB

Bits

Effective Number Of Bits

1. INL measured from V = .1V

to V = .9V

in REFH

REFH

10% to 90% Input Signal Range

2. LSB = Least Significant Bit

3. ADC clock cycles

4. Assumes each voltage reference pin is bypassed with 0.1µF ceramic capacitors to ground

5. The current that can be injected or sourced from an unselected ADC signal input without impacting the performance of

the ADC. This allows the ADC to operate in noisy industrial environments where inductive flyback is possible.

6. Absolute error includes the effects of both gain error and offset error.

7. Please see the 56F8300 Peripheral User’s Manual for additional information on ADC calibration.

8. ENOB = (SINAD - 1.76)/6.02

56F8322 Technical Data, Rev. 10.0

Freescale Semiconductor

Preliminary

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Figure 10-20 ADC Absolute Error Over Processing and Temperature Extremes Before

and After Calibration for VDC = 0.60V and 2.70V

Note: The absolute error data shown in the graphs above reflects the effects of both gain error and offset

error. The data was taken on 15 parts: three each from four processing corner lots as well as three from one

nominally processed lot, each at three temperatures: -40°C, 27°C, and 150°C (giving the 45 data points

shown above), for two input DC voltages: 0.60V and 2.70V. The data indicates that for the given

population of parts, calibration significantly reduced (by as much as 34%) the collective variation (spread)

of the absolute error of the population. It also significantly reduced (by as much as 80% when VDCin was

0.6V) the mean (average) of the absolute error and thereby brought it significantly closer to the ideal value

of zero. Although not guaranteed, it is believed that calibration will produce results similar to those shown

above for any population of parts, including those which represent processing and temperature extremes.

56F8322 Techncial Data, Rev. 10.0

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Equivalent Circuit for ADC Inputs

10.16 Equivalent Circuit for ADC Inputs

Figure 10-21 illustrates the ADC input circuit during sample and hold. S1 and S2 are always open/closed

at the same time that S3 is closed/open. When S1/S2 closed & S3 open, one input of the sample and hold

circuit moves to (V

-V

)/2, while the other charges to the analog input voltage. When the

REFH REFLO

switches are flipped, the charge on C1 and C2 are averaged via S3, with the result that a single-ended

analog input is switched to a differential voltage centered about (V -V )/2. The switches switch

REFH REFLO

on every cycle of the ADC clock (open one-half ADC clock, closed one-half ADC clock). Note that there

are additional capacitances associated with the analog input pad, routing, etc., but these do not filter into

the S/H output voltage, as S1 provides isolation during the charge-sharing phase.

One aspect of this circuit is that there is an on-going input current, which is a function of the analog input

voltage, V

and the ADC clock frequency.

REF

Analog Input

S/H

- V / 2

REFLO )

REFH

C1 = C2 = 1pF

1. Parasitic capacitance due to package, pin-to-pin and pin-to-package base coupling; 1.8pf

2. Parasitic capacitance due to the chip bond pad, ESD protection devices and signal routing; 2.04pf

3. Equivalent resistance for the ESD isolation resistor and the channel select mux; 500 ohms

4. Sampling capacitor at the sample and hold circuit. Capacitor C1 is normally disconnected from the input and is only

connected to it at sampling time; 1pf

Figure 10-21 Equivalent Circuit for A/D Loading

10.17 Power Consumption

See Section 10.1 for a list of IDD requirements for the device. This section provides additional detail

which can be used to optimize power consumption for a given application.

Power consumption is given by the following equation:

Total power =

A: internal [static component]

+B: internal [state-dependent component]

+C: internal [dynamic component]

+D: external [dynamic component]

+E: external [static]

A, the internal [static component], is comprised of the DC bias currents for the oscillator, leakage currents,

PLL, and voltage references. These sources operate independently of processor state or operating

frequency.

56F8322 Technical Data, Rev. 10.0

Freescale Semiconductor

Preliminary

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B, the internal [state-dependent component], reflects the supply current required by certain on-chip

resources only when those resources are in use. These include RAM, Flash memory and the ADCs.

C, the internal [dynamic component], is classic C*V *F CMOS power dissipation corresponding to the

56800E core and standard cell logic.

D, the external [dynamic component], reflects power dissipated on-chip as a result of capacitive loading

on the external pins of the chip. This is also commonly described as C*V *F, although simulations on two

of the IO cell types used on the 56800E reveal that the power-versus-load curve does have a non-zero

Y-intercept.

Note: V

is tied to V

and V

is tied to V

inside this package.

SSA

REFH

DDA

REFLO

Table 10-25 IO Loading Coefficients at 10MHz

Intercept

Slope

PDU08DGZ_ME

PDU04DGZ_ME

1.3

0.11mW / pF

1.15mW

Power due to capacitive loading on output pins is (first order) a function of the capacitive load and

frequency at which the outputs change. Table 10-25 provides coefficients for calculating power dissipated

in the IO cells as a function of capacitive load. In these cases:

TotalPower = Σ((Intercept + Slope*Cload)*frequency/10MHz)

where:

•

Summation is performed over all output pins with capacitive loads

TotalPower is expressed in mW

Cload is expressed in pF

Because of the low duty cycle on most device pins, power dissipation due to capacitive loads was found

to be fairly low when averaged over a period of time.

E, the external [static component], reflects the effects of placing resistive loads on the outputs of the

device. Sum the total of all V /R or IV to arrive at the resistive load contribution to power. Assume V =

0.5 for the purposes of these rough calculations. For instance, if there is a total of eight PWM outputs

driving 10mA into LEDs, then P = 8*.5*.01 = 40mW.

In previous discussions, power consumption due to parasitics associated with pure input pins is ignored,

as it is assumed to be negligible.

56F8322 Techncial Data, Rev. 10.0

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56F8322 Package and Pin-Out Information

Part 11 Packaging

11.1 56F8322 Package and Pin-Out Information

This section contains package and pin-out information for the 56F8322. This device comes in a 48-pin

Low-profile Quad Flat Pack (LQFP). Figure 11-1 shows the package outline for the 48-pin LQFP,

Figure 12-1 shows the mechanical parameters for this package, and Table 11-1 lists the pin-out for the

48-pin LQFP.

ORIENTATION

TC0

RESET

PWMA0

PWMA1

MARK

INDEX0

HOME0

PIN 1

DD_IO

XTAL

EXTAL

Freescale

56F8322

DD_IO

PWMA2

PWMA3

PWMA4

PWMA5

DDA_ADC

SSA_ADC

REFP

REFMID

REFN

IRQA

FAULTA0

ANA6

Figure 11-1 Top View, 56F8322 48-Pin LQFP Package

56F8322 Technical Data, Rev. 10.0

Freescale Semiconductor

Preliminary

127

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Table 11-1 56F8322 48-Pin LQFP Package Identification by Pin Number

Pin No.

Signal Name

TC0

Pin No.

Signal Name

Pin No.

Signal Name

Pin No.

Signal Name

PHASEB

PHASEA

TCK

ANA6

RESET

DD_IO

REFN

PWMA0

PWMA1

SS0

REFMID

MISO0

TMS

REFP

TDI

DD_IO

CAP

SSA_ADC

DDA_ADC

PWMA2

PWMA3

PWMA4

PWMA5

MOSI0

SCLK0

ANA0

ANA1

ANA2

TDO

CAP

EXTAL

XTAL

DD_IO

CAN_RX

DD_IO

IRQA

ANA4

ANA5

HOME0

INDEX0

CAN_TX

TC1

FAULTA0

56F8322 Techncial Data, Rev. 10.0

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56F8122 Package and Pin-Out Information

11.2 56F8122 Package and Pin-Out Information

This section contains package and pin-out information for the 56F8122. This device comes in a 48-pin

Low-profile Quad Flat Pack (LQFP). Figure 11-1 shows the package outline for the 48-pin LQFP,

Figure 12-1 shows the mechanical parameters for this package, and Table 11-1 lists the pin-out for the

48-pin LQFP.

ORIENTATION

TC0

RESET

GPIOA0

GPIOA1

MARK

TA2

TA3

PIN 1

DD_IO

XTAL

EXTAL

Freescale

56F8122

DD_IO

SS1

MISO1

MOSI1

SCLK1

DDA_ADC

SSA_ADC

REFP

REFMID

REFN

IRQA

GPIOA6

ANA6

Figure 11-2 Top View, 56F8122 48-Pin LQFP Package

56F8322 Technical Data, Rev. 10.0

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Preliminary

129

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Table 11-2 56F8122 48-Pin LQFP Package Identification by Pin Number

Pin No.

Signal Name

TC0

Pin No.

Signal Name

Pin No.

Signal Name

Pin No.

Signal Name

TA1

ANA6

RESET

TA0

DD_IO

REFN

GPIOA0

GPIOA1

SS0

TCK

REFMID

MISO0

TMS

REFP

TDI

DD_IO

CAP

SSA_ADC

DDA_ADC

SS1

MOSI0

SCLK0

ANA0

ANA1

ANA2

TDO

MISO1

MOSI1

SCLK1

CAP

EXTAL

XTAL

DD_IO

GPIOC2

DD_IO

IRQA

ANA4

ANA5

TA3

GPIOC3

TC1

GPIOA6

TA2

56F8322 Techncial Data, Rev. 10.0

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56F8122 Package and Pin-Out Information

0.200 AB T-U Z

NOTES:

DETAIL Y

1. DIMENSIONING AND TOLERANCING PER ASME

Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DATUM PLANE AB IS LOCATED AT BOTTOM OF LEAD

AND IS COINCIDENT WITH THE LEAD WHERE THE

LEAD EXITS THE PLASTIC BODY AT THEBOTTOM OF

THE PARTING LINE.

4. DATUMS T, U, AND Z TO BE DETERMINED AT DATUM

PLANE AB.

5. DIMENSIONS S AND V TO BE DETERMINED AT

SEATING PLANE AC.

6. DIMENSIONS A AND B DO NOT INCLUDE MOLD

PROTRUSION. ALLOWABLE PROTRUSION IS 0.250

PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD

MISMATCH AND ARE DETERMINED ATDATUMPLANE

AB.

7. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. DAMBAR PROTRUSION SHALL NOT

CAUSE THE D DIMENSION TO EXCEED 0.350.

8. MINIMUM SOLDER PLATE THICKNESS SHALL BE

0.0076.

9. EXACT SHAPE OF EACH CORNER IS OPTIONAL.

MILLIMETERS

DIM MIN

MAX

7.000 BSC

3.500 BSC

T, U, Z

7.000 BSC

3.500 BSC

DETAIL Y

1.400 1.600

0.170 0.270

1.350 1.450

0.170 0.230

0.500 BSC

0.050 0.150

0.090 0.200

0.500 0.700

0.200 AC T-U

0.080 AC

12 REF

0.090 0.160

0.250 BSC

0.150 0.250

9.000 BSC

4.500 BSC

9.000 BSC

4.500 BSC

0.200 REF

1.000 REF

TOP & BOTTOM

BASE METAL

0.080

AC T-U Z

SECTION AE-AE

DETAIL AD

Figure 11-3 48-Pin LQFP Mechanical Information

56F8322 Technical Data, Rev. 10.0

Freescale Semiconductor

Preliminary

131

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Part 12 Design Considerations

12.1 Thermal Design Considerations

An estimation of the chip junction temperature, T , can be obtained from the equation:

T = T + (R

x P )

θJΑ

where:

= Ambient temperature for the package ( C)

= Junction to ambient thermal resistance ( C/W)

θJΑ

= Power dissipation in the package (W)

The junction to ambient thermal resistance is an industry-standard value that provides a quick and easy

estimation of thermal performance. Unfortunately, there are two values in common usage: the value

determined on a single-layer board and the value obtained on a board with two planes. For packages such

as the PBGA, these values can be different by a factor of two. Which value is closer to the application

depends on the power dissipated by other components on the board. The value obtained on a single layer

board is appropriate for the tightly packed printed circuit board. The value obtained on the board with the

internal planes is usually appropriate if the board has low-power dissipation and the components are well

separated.

When a heat sink is used, the thermal resistance is expressed as the sum of a junction-to-case thermal

resistance and a case-to-ambient thermal resistance:

= R

+ R

θJC θCA

θJA

where:

Package junction to ambient thermal resistance °C/W

Package junction to case thermal resistance °C/W

Package case to ambient thermal resistance °C/W

θJA

θJC

θCA

is device related and cannot be influenced by the user. The user controls the thermal environment to

θJC

change the case-to-ambient thermal resistance, R

sink, the air flow around the device, the interface material, the mounting arrangement on printed circuit

board, or change the thermal dissipation on the printed circuit board surrounding the device.

. For instance, the user can change the size of the heat

θCA

To determine the junction temperature of the device in the application when heat sinks are not used, the

Thermal Characterization Parameter (Ψ ) can be used to determine the junction temperature with a

measurement of the temperature at the top center of the package case using the following equation:

T = T + (Ψ x P )

where:

= Thermocouple temperature on top of package ( C)

= Thermal characterization parameter ( C)/W

= Power dissipation in package (W)

56F8322 Techncial Data, Rev. 10.0

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Electrical Design Considerations

The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T

thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so

that the thermocouple junction rests on the package. A small amount of epoxy is placed over the

thermocouple junction and over about 1mm of wire extending from the junction. The thermocouple wire

is placed flat against the package case to avoid measurement errors caused by cooling effects of the

thermocouple wire.

When heat sink is used, the junction temperature is determined from a thermocouple inserted at the

interface between the case of the package and the interface material. A clearance slot or hole is normally

required in the heat sink. Minimizing the size of the clearance is important to minimize the change in

thermal performance caused by removing part of the thermal interface to the heat sink. Because of the

experimental difficulties with this technique, many engineers measure the heat sink temperature and then

back-calculate the case temperature using a separate measurement of the thermal resistance of the

interface. From this case temperature, the junction temperature is determined from the junction-to-case

thermal resistance.

12.2 Electrical Design Considerations

CAUTION

This device contains protective circuitry to guard

against damage due to high static voltage or electrical

fields. However, normal precautions are advised to

avoid application of any voltages higher than

maximum-rated voltages to this high-impedance circuit.

Reliability of operation is enhanced if unused inputs are

tied to an appropriate voltage level.

Use the following list of considerations to assure correct operation of the 56F8322/56F8122:

•

Provide a low-impedance path from the board power supply to each V pin on the device and from the

board ground to each V (GND) pin

•

The minimum bypass requirement is to place six 0.01–0.1µF capacitors positioned as close as possible to

the package supply pins. The recommended bypass configuration is to place one bypass capacitor on each

of the V /V pairs, including V

Ceramic and tantalum capacitors tend to provide better

DD SS

DDA SSA.

tolerances.

•

Ensure that capacitor leads and associated printed circuit traces that connect to the chip V and V (GND)

DD SS

pins are less than 0.5 inch per capacitor lead

•

Use at least a four-layer Printed Circuit Board (PCB) with two inner layers for V and V

Bypass the V and V layers of the PCB with approximately 100µF, preferably with a high-grade

capacitor such as a tantalum capacitor

56F8322 Technical Data, Rev. 10.0

Freescale Semiconductor

Preliminary

133

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•

Because the device’s output signals have fast rise and fall times, PCB trace lengths should be minimal

Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance.

This is especially critical in systems with higher capacitive loads that could create higher transient currents

in the V and V circuits.

•

Take special care to minimize noise levels on the V , V

and V

pins

SSA

REF DDA

Because the Flash memory is programmed through the JTAG/EOnCE port, the designer should provide an

interface to this port to allow in-circuit Flash programming

12.3 Power Distribution and I/O Ring Implementation

Figure 12-1 illustrates the general power control incorporated in the 56F8322/56F8122. This chip

contains two internal power regulators. One of them is powered from the V

pin and cannot

DDA_OSC_PLL

be turned off. This regulator controls power to the internal clock generation circuitry. The other regulator

is powered from the V pins and provides power to all of the internal digital logic of the core, all

DD_IO

peripherals and the internal memories. This regulator can be turned off, if an external V

voltage

DD_CORE

is externally applied to the V

pins.

CAP

In summary, the entire chip can be supplied from a single 3.3 volt supply if the large core regulator is

enabled. If the regulator is not enabled, a dual supply 3.3V/2.5V configuration can also be used.

Notes:

•

Flash, RAM and internal logic are powered from the core regulator output

V 1 and V 2 are not connected in the customer system

•

All circuitry, analog and digital, shares a common V bus

V_{DDA_OSC_PLL}

V_DD

V_{DDA_ADC}

V_REFH

V_REFP

V_REFMID

V_REFN

V_REFLO

V_CAP

REG

OCS

I/O

ADC

CORE

ROSC

V_SS

V_{SSA_ADC}

Figure 12-1 Power Management

56F8322 Techncial Data, Rev. 10.0

134

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Power Distribution and I/O Ring Implementation

Part 13 Ordering Information

Table 13-1 lists the pertinent information needed to place an order. Consult a Freescale Semiconductor

sales office or authorized distributor to determine availability and to order parts.

Table 13-1 Ordering Information

Supply

Voltage

Count

Frequency Temperature

Part

Package Type

Order Number

(MHz)

Range

Low-Profile Quad Flat Pack (LQFP)

MC56F8322

MC56F8122

3.0–3.6 V

-40° to + 105° C

-40° to + 125° C

-40° to + 105° C

MC56F8322VFA60

MC56F8322MFA60

MC56F8122VFA

56F8322 Technical Data, Rev. 10.0

Freescale Semiconductor

Preliminary

135

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