Cypress NoBL CY7C1372DV25 User Manual

CY7C1370DV25

CY7C1372DV25

18-Mbit (512K x 36/1M x 18)

Pipelined SRAM with NoBL™ Architecture

Functional Description

Features

• Pin-compatible and functionally equivalent to ZBT™

• Supports 250-MHz bus operations with zero wait states

— Available speed grades are 250, 200 and 167 MHz

The CY7C1370DV25 and CY7C1372DV25 are 2.5V, 512K x

36 and 1 Mbit x 18 Synchronous pipelined burst SRAMs with

No Bus Latency™ (NoBL™) logic, respectively. They are

designed to support unlimited true back-to-back Read/Write

operations with no wait states. The CY7C1370DV25 and

CY7C1372DV25 are equipped with the advanced (NoBL) logic

required to enable consecutive Read/Write operations with

data being transferred on every clock cycle. This feature

dramatically improves the throughput of data in systems that

require frequent Write/Read transitions. The CY7C1370DV25

and CY7C1372DV25 are pin-compatible and functionally

equivalent to ZBT devices.

• Internally self-timed output buffer control to eliminate

the need to use asynchronous OE

• Fully registered (inputs and outputs) for pipelined

operation

• Byte Write capability

• Single 2.5V core power supply (V

)

• 2.5V I/O power supply (V

)

DDQ

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. All data outputs pass through

output registers controlled by the rising edge of the clock. The

clock input is qualified by the Clock Enable (CEN) signal,

which when deasserted suspends operation and extends the

previous clock cycle.

• Fast clock-to-output times

— 2.6 ns (for 250-MHz device)

• Clock Enable (CEN) pin to suspend operation

• Synchronous self-timed writes

• Available in JEDEC-standard lead-free 100-Pin TQFP,

lead-free and non-lead-free 119-Ball BGA and 165-Ball

FBGA packages

Write operations are controlled by the Byte Write Selects

(BW –BW

for CY7C1370DV25 and BW –BW

for

CY7C1372DV25) and a Write Enable (WE) input. All writes are

conducted with on-chip synchronous self-timed write circuitry.

• IEEE 1149.1 JTAG-Compatible Boundary Scan

• Burst capability—linear or interleaved burst order

• “ZZ” Sleep Mode option and Stop Clock option

Three synchronous Chip Enables (CE , CE , CE ) and an

asynchronous Output Enable (OE) provide for easy bank

selection and output three-state control. In order to avoid bus

contention, the output drivers are synchronously three-stated

during the data portion of a write sequence.

Logic Block Diagram-CY7C1370DV25 (512K x 36)

ADDRESS

A0, A1, A

A1'

A0'

BURST

LOGIC

MODE

ADV/LD

CLK

CEN

WRITE ADDRESS

ADV/LD

BWa

BWb

BWc

BWd

WRITE REGISTRY

AND DATA COHERENCY

CONTROL LOGIC

MEMORY

ARRAY

DQs

WRITE

DRIVERS

DQPa

DQPb

DQPc

DQPd

INPUT

READ LOGIC

CE1

CE2

CE3

SLEEP

CONTROL

Cypress Semiconductor Corporation

Document #: 38-05558 Rev. *D

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised June 29, 2006

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CY7C1370DV25

CY7C1372DV25

Pin Configurations

100-Pin TQFP Pinout

DQPc

DQc

DDQ

DQPb

DQb

DDQ

DQPa

DQa

DDQ

DQc

DQb

DQc

DQb

DDQ

DQa

DDQ

DQc

DQb

CY7C1370DV25

(512K × 36)

CY7C1372DV25

(1M × 18)

DQa

DQd

DQb

DQa

DQd

DQb

DDQ

DQa

DDQ

DQd

DQa

DQb

DQa DQPb

DQa

DDQ

DQd

DQPd

DQa

DQPa

Document #: 38-05558 Rev. *D

Page 3 of 27

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CY7C1370DV25

CY7C1372DV25

Pin Configurations (continued)

119-Ball BGA

Pinout

CY7C1370DV25 (512K × 36)

DDQ

NC/576M

NC/1G

ADV/LD

DQP

DDQ

CLK

DDQ

CEN

DDQ

DQP

NC/144M

MODE

NC/288M

NC/72M

TMS

NC/36M

TDI

TCK

TDO

DDQ

CY7C1372DV25 (1M x 18)

DDQ

NC/576M

NC/1G

ADV/LD

DQP

DDQ

CLK

CEN

DDQ

DQP

NC/144M

NC/72M

MODE

NC/288M

NC/36M

TCK

TMS

TDI

TDO

DDQ

Document #: 38-05558 Rev. *D

Page 4 of 27

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CY7C1370DV25

CY7C1372DV25

Pin Configurations (continued)

165-Ball FBGA Pinout

CY7C1370DV25 (512K × 36)

NC/576M

NC/1G

DQP_c

ADV/LD

CE₁

BW_c

BW_d

V_SS

V_DD

BW_b

BW_a

V_SS

CEN

CE2

V_DDQ

CLK

V_SS

V_DD

DQ_c

V_SS

V_DDQ

DQ_b

DQP_b

DQ_b

DQ_c

V_DDQ

V_DD

V_SS

V_DD

V_DDQ

DQ_b

DQ_d

V_DDQ

DQ_a

DQ_d

V_DDQ

V_DD

V_SS

V_DD

V_SS

V_DDQ

DQ_a

DQP_a

DQP_d

NC/144M NC/72M

MODE NC/36M

TDI

TDO

NC/288M

TMS

TCK

CY7C1372DV25 (1M × 18)

NC/576M

NC/1G

CE₁

BW_b

CEN

ADV/LD

CE2

V_DDQ

BW_a

V_SS

CLK

V_SS

V_DD

DQ_b

V_SS

V_DD

V_DDQ

DQP_a

DQ_a

DQ_b

V_DDQ

V_DD

V_SS

V_DD

V_DDQ

DQ_a

DQ_b

V_DDQ

DQ_a

DQ_b

V_DDQ

V_DD

V_SS

V_DD

V_SS

V_DDQ

DQ_a

DQP_b

NC/144M NC/72M

MODE NC/36M

TDI

TDO

NC/288M

TMS

TCK

Document #: 38-05558 Rev. *D

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CY7C1370DV25

CY7C1372DV25

Pin Definitions

Pin Name

I/O Type

Pin Description

Address Inputs used to select one of the address locations. Sampled at the rising edge of

Input-

Synchronous the CLK.

Input-

Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the SRAM.

Synchronous Sampled on the rising edge of CLK. BW controls DQ and DQP , BW controls DQ and DQP ,

BW controls DQ and DQP , BW controls DQ and DQP .

Input-

Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This

Synchronous signal must be asserted LOW to initiate a write sequence.

ADV/LD

Input- Advance/Load Input used to advance the on-chip address counter or load a new address.

Synchronous When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a

new address can be loaded into the device for an access. After being deselected, ADV/LD should

be driven LOW in order to load a new address.

CLK

Input-

Clock

Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN.

CLK is only recognized if CEN is active LOW.

Input-

Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with

Synchronous CE and CE to select/deselect the device.

Input-

Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction

Synchronous with CE and CE to select/deselect the device.

Input-

Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with

Synchronous CE and CE to select/deselect the device.

Input-

Output Enable, active LOW. Combined with the synchronous logic block inside the device to

Asynchronous control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs.

When deasserted HIGH, I/O pins are three-stated, and act as input data pins. OE is masked

during the data portion of a write sequence, during the first clock when emerging from a

deselected state and when the device has been deselected.

CEN

Input-

Clock Enable Input, active LOW. When asserted LOW the clock signal is recognized by the

Synchronous SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN does not

deselect the device, CEN can be used to extend the previous cycle when required.

I/O-

Synchronous by the rising edge of CLK. As outputs, they deliver the data contained in the memory location

specified by A during the previous clock rise of the read cycle. The direction of the pins is

Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered

[17:0]

controlled by OE and the internal control logic. When OE is asserted LOW, the pins can behave

as outputs. When HIGH, DQ –DQ are placed in a three-state condition. The outputs are

automatically three-stated during the data portion of a write sequence, during the first clock when

emerging from a deselected state, and when the device is deselected, regardless of the state of

OE.

DQP

I/O-

Bidirectional Data Parity I/O lines. Functionally, these signals are identical to DQ . During write

Synchronous sequences, DQP is controlled by BW , DQP is controlled by BW , DQP is controlled by BW ,

and DQP is controlled by BW .

MODE

TDO

TDI

Input Strap Pin Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order.

Pulled LOW selects the linear burst order. MODE should not change states during operation.

When left floating MODE will default HIGH, to an interleaved burst order.

JTAG serial Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK.

output

Synchronous

JTAG serial Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK.

input

Synchronous

TMS

TCK

Test Mode This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK.

Select

Synchronous

JTAG-Clock Clock input to the JTAG circuitry.

Document #: 38-05558 Rev. *D

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CY7C1370DV25

CY7C1372DV25

Pin Definitions (continued)

Pin Name

I/O Type

Pin Description

Power Supply Power supply inputs to the core of the device.

I/O Power Power supply for the I/O circuitry.

Supply

DDQ

Ground

Ground for the device. Should be connected to ground of the system.

–

No connects. This pin is not connected to the die.

NC/(36M,72M,

144M, 288M,

576M, 1G)

These pins are not connected. They will be used for expansion to the 36M, 72M, 144M, 288M,

576M, and 1G densities.

Input-

ZZ “Sleep” Input. This active HIGH input places the device in a non-time critical “sleep”

Asynchronous condition with data integrity preserved. For normal operation, this pin has to be LOW or left

floating. ZZ pin has an internal pull-down.

order for the device to drive out the requested data. During the

second clock, a subsequent operation (Read/Write/Deselect)

can be initiated. Deselecting the device is also pipelined.

Therefore, when the SRAM is deselected at clock rise by one

of the chip enable signals, its output will three-state following

the next clock rise.

Introduction

Functional Overview

The CY7C1370DV25

and

CY7C1372DV25

are

synchronous-pipelined Burst NoBL SRAMs designed specifi-

cally to eliminate wait states during Write/Read transitions. All

synchronous inputs pass through input registers controlled by

the rising edge of the clock. The clock signal is qualified with

the Clock Enable input signal (CEN). If CEN is HIGH, the clock

signal is not recognized and all internal states are maintained.

All synchronous operations are qualified with CEN. All data

outputs pass through output registers controlled by the rising

edge of the clock. Maximum access delay from the clock rise

Burst Read Accesses

The CY7C1370DV25 and CY7C1372DV25 have an on-chip

burst counter that allows the user the ability to supply a single

address and conduct up to four Reads without reasserting the

address inputs. ADV/LD must be driven LOW in order to load

a new address into the SRAM, as described in the Single Read

Access section above. The sequence of the burst counter is

determined by the MODE input signal. A LOW input on MODE

selects a linear burst mode, a HIGH selects an interleaved

burst sequence. Both burst counters use A0 and A1 in the

burst sequence, and will wrap around when incremented suffi-

ciently. A HIGH input on ADV/LD will increment the internal

burst counter regardless of the state of chip enables inputs or

WE. WE is latched at the beginning of a burst cycle. Therefore,

the type of access (Read or Write) is maintained throughout

the burst sequence.

(t ) is 2.6 ns (250-MHz device).

Accesses can be initiated by asserting all three Chip Enables

(CE , CE , CE ) active at the rising edge of the clock. If Clock

Enable (CEN) is active LOW and ADV/LD is asserted LOW,

the address presented to the device will be latched. The

access can either be a read or write operation, depending on

the status of the Write Enable (WE). BW can be used to

conduct byte write operations.

Write operations are qualified by the Write Enable (WE). All

writes are simplified with on-chip synchronous self-timed write

circuitry.

Single Write Accesses

Write access are initiated when the following conditions are

satisfied at clock rise: (1) CEN is asserted LOW, (2) CE , CE ,

Three synchronous Chip Enables (CE , CE , CE ) and an

asynchronous Output Enable (OE) simplify depth expansion.

All operations (Reads, Writes, and Deselects) are pipelined.

ADV/LD should be driven LOW once the device has been

deselected in order to load a new address for the next

operation.

and CE are ALL asserted active, and (3) the write signal WE

is asserted LOW. The address presented is loaded into the

Address Register. The write signals are latched into the

Control Logic block.

On the subsequent clock rise the data lines are automatically

three-stated regardless of the state of the OE input signal. This

allows the external logic to present the data on DQ and DQP

Single Read Accesses

A read access is initiated when the following conditions are

satisfied at clock rise: (1) CEN is asserted LOW, (2) CE , CE ,

(DQ

/DQP

for CY7C1370DV25 and DQ /DQP

a,b,c,d

a,b,c,d a,b a,b

and CE are ALL asserted active, (3) the Write Enable input

for CY7C1372DV25). In addition, the address for the subse-

quent access (Read/Write/Deselect) is latched into the

Address Register (provided the appropriate control signals are

asserted).

signal WE is deasserted HIGH, and (4) ADV/LD is asserted

LOW. The address presented to the address inputs is latched

into the Address Register and presented to the memory core

and control logic. The control logic determines that a read

access is in progress and allows the requested data to

propagate to the input of the output register. At the rising edge

of the next clock the requested data is allowed to propagate

through the output register and onto the data bus within 2.6 ns

(250-MHz device) provided OE is active LOW. After the first

clock of the read access the output buffers are controlled by

OE and the internal control logic. OE must be driven LOW in

On the next clock rise the data presented to DQ and DQP

(DQ

/DQP

for CY7C1370DV25 & DQ /DQP for

a,b,c,d

a,b,c,d a,b a,b

CY7C1372DV25) (or a subset for byte write operations, see

Write Cycle Description table for details) inputs is latched into

the device and the write is complete.

The data written during the write operation is controlled by BW

(BW

for CY7C1370DV25 and BW for CY7C1372DV25)

a,b,c,d

a,b

Document #: 38-05558 Rev. *D

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CY7C1370DV25

CY7C1372DV25

signals. The CY7C1370DV25/CY7C1372DV25 provides byte

write capability that is described in the Write Cycle Description

table. Asserting the Write Enable input (WE) with the selected

Byte Write Select (BW) input will selectively write to only the

desired bytes. Bytes not selected during a byte write operation

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ

places the SRAM in a power conservation “sleep” mode. Two

clock cycles are required to enter into or exit from this “sleep”

mode. While in this mode, data integrity is guaranteed.

Accesses pending when entering the “sleep” mode are not

considered valid nor is the completion of the operation

guaranteed. The device must be deselected prior to entering

will remain unaltered.

synchronous self-timed write

mechanism has been provided to simplify the write operations.

Byte write capability has been included in order to greatly

simplify Read/Modify/Write sequences, which can be reduced

to simple byte write operations.

the “sleep” mode. CE , CE , and CE , must remain inactive

for the duration of t

after the ZZ input returns LOW.

ZZREC

Because the CY7C1370DV25 and CY7C1372DV25 are

common I/O devices, data should not be driven into the device

while the outputs are active. The Output Enable (OE) can be

deasserted HIGH before presenting data to the DQ and DQP

Interleaved Burst Address Table

(MODE = Floating or V_DD

)

First

Second

Address

Third

Address

Fourth

Address

(DQ

/DQP

for CY7C1370DV25 and DQ /DQP

a,b,c,d

a,b,c,d a,b a,b

Address

for CY7C1372DV25) inputs. Doing so will three-state the

output drivers. As a safety precaution, DQ and DQP

A1,A0

(DQ

/DQP

for CY7C1370DV25 and DQ /DQP

a,b,c,d

a,b,c,d a,b a,b

for CY7C1372DV25) are automatically three-stated during the

data portion of a write cycle, regardless of the state of OE.

Burst Write Accesses

The CY7C1370DV25/CY7C1372DV25 has an on-chip burst

counter that allows the user the ability to supply a single

address and conduct up to four WRITE operations without

reasserting the address inputs. ADV/LD must be driven LOW

in order to load the initial address, as described in the Single

Write Access section above. When ADV/LD is driven HIGH on

Linear Burst Address Table (MODE = GND)

First

Address

Second

Address

Third

Address

Fourth

Address

A1,A0

the subsequent clock rise, the chip enables (CE , CE , and

CE ) and WE inputs are ignored and the burst counter is incre-

mented. The correct BW (BW

for CY7C1370DV25 and

a,b,c,d

for CY7C1372DV25) inputs must be driven in each

a,b

cycle of the burst write in order to write the correct bytes of

data.

ZZ Mode Electrical Characteristics

Parameter

Description

Sleep mode standby current

Device operation to ZZ

ZZ recovery time

Test Conditions

Min.

Max.

Unit

ZZ > V − 0.2V

DDZZ

ZZ > V − 0.2V

ZZS

CYC

ZZ < 0.2V

ZZREC

ZZI

CYC

ZZ active to sleep current

ZZ Inactive to exit sleep current

This parameter is sampled

CYC

RZZI

Document #: 38-05558 Rev. *D

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CY7C1370DV25

CY7C1372DV25

Truth Table^{[1, 2, 3, 4, 5, 6, 7]}

Address

Used

Operation

Deselect Cycle

ADV/LD WE BW

CEN CLK

L-H

Tri-state

Data Out (Q)

Tri-state

Data In (D)

Tri-state

–

None

Continue Deselect Cycle

Read Cycle (Begin Burst)

Read Cycle (Continue Burst)

NOP/Dummy Read (Begin Burst)

Dummy Read (Continue Burst)

Write Cycle (Begin Burst)

Write Cycle (Continue Burst)

NOP/Write Abort (Begin Burst)

Write Abort (Continue Burst)

Ignore Clock Edge (Stall)

Sleep Mode

None

L-H

External

L-H

External

L-H

External

L-H

None

L-H

Current

None

L-H

Tri-state

Partial Write Cycle Description^{[1, 2, 3, 8]}

Function (CY7C1370DV25)

Read

Write – No bytes written

Write Byte a – (DQ and DQP )

Write Byte b – (DQ and DQP )

Write Bytes b, a

Write Byte c – (DQ and DQP )

Write Bytes c, a

Write Bytes c, b

Write Bytes c, b, a

Write Byte d – (DQ and DQP )

Write Bytes d, a

Write Bytes d, b

Write Bytes d, b, a

Write Bytes d, c

Write Bytes d, c, a

Write Bytes d, c, b

Write All Bytes

Notes:

1. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for ALL Chip Enables active. BWx = L signifies at least one Byte Write Select is active, BW = Valid

signifies that the desired byte write selects are asserted, see Write Cycle Description table for details.

2. Write is defined by WE and BW . See Write Cycle Description table for details.

3. When a write cycle is detected, all I/Os are tri-stated, even during byte writes.

4. The DQ and DQP pins are controlled by the current cycle and the OE signal.

5. CEN = H inserts wait states.

6. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE.

7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles.During a read cycle DQ and DQP = Three-state when

OE is inactive or when the device is deselected, and DQ = data when OE is active.

8. Table only lists a partial listing of the byte write combinations. Any Combination of BW is valid. Appropriate write will be done based on which byte write is active.

Document #: 38-05558 Rev. *D

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CY7C1370DV25

CY7C1372DV25

Function (CY7C1372DV25)

Read

Write – No Bytes Written

Write Byte a – (DQ and DQP )

Write Byte b – (DQ and DQP )

Write Both Bytes

Test Mode Select (TMS)

IEEE 1149.1 Serial Boundary Scan (JTAG)

The TMS input is used to give commands to the TAP controller

and is sampled on the rising edge of TCK. It is allowable to

leave this ball unconnected if the TAP is not used. The ball is

pulled up internally, resulting in a logic HIGH level.

The CY7C1370DV25/CY7C1372DV25 incorporates a serial

boundary scan test access port (TAP).This part is fully

compliant with 1149.1. The TAP operates using

JEDEC-standard 3.3V or 2.5V I/O logic levels.

Test Data-In (TDI)

The CY7C1370DV25/CY7C1372DV25 contains

TAP

controller, instruction register, boundary scan register, bypass

The TDI ball is used to serially input information into the

registers and can be connected to the input of any of the

registers. The register between TDI and TDO is chosen by the

instruction that is loaded into the TAP instruction register. For

information on loading the instruction register, see TAP

Controller State Diagram. TDI is internally pulled up and can

be unconnected if the TAP is unused in an application. TDI is

connected to the most significant bit (MSB) of any register.

(See Tap Controller Block Diagram.)

Disabling the JTAG Feature

It is possible to operate the SRAM without using the JTAG

feature. To disable the TAP controller, TCK must be tied LOW

(V ) to prevent clocking of the device. TDI and TMS are inter-

nally pulled up and may be unconnected. They may alternately

be connected to V through a pull-up resistor. TDO should be

left unconnected. Upon power-up, the device will come up in

a reset state which will not interfere with the operation of the

device.

Test Data-Out (TDO)

The TDO output ball is used to serially clock data-out from the

registers. The output is active depending upon the current

state of the TAP state machine. The output changes on the

falling edge of TCK. TDO is connected to the least significant

bit (LSB) of any register. (See Tap Controller State Diagram.)

TAP Controller State Diagram

TEST-LOGIC

RESET

TAP Controller Block Diagram

RUN-TEST/

IDLE

SELECT

DR-SCAN

SELECT

IR-SCAN

CAPTURE-DR

CAPTURE-IR

Bypass Register

SHIFT-DR

SHIFT-IR

Selection

Circuitry

Instruction Register

31 30 29

Identification Register

Selection

Circuitry

TDI

TDO

EXIT1-DR

EXIT1-IR

PAUSE-DR

PAUSE-IR

Boundary Scan Register

EXIT2-DR

EXIT2-IR

TCK

TMS

UPDATE-DR

UPDATE-IR

TAP CONTROLLER

The 0/1 next to each state represents the value of TMS at the

rising edge of TCK.

Performing a TAP Reset

A RESET is performed by forcing TMS HIGH (V ) for five

Test Access Port (TAP)

rising edges of TCK. This RESET does not affect the operation

of the SRAM and may be performed while the SRAM is

operating.

Test Clock (TCK)

The test clock is used only with the TAP controller. All inputs

are captured on the rising edge of TCK. All outputs are driven

from the falling edge of TCK.

At power-up, the TAP is reset internally to ensure that TDO

comes up in a High-Z state.

Document #: 38-05558 Rev. *D

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CY7C1370DV25

CY7C1372DV25

TAP Registers

through the instruction register through the TDI and TDO balls.

To execute the instruction once it is shifted in, the TAP

controller needs to be moved into the Update-IR state.

Registers are connected between the TDI and TDO balls and

allow data to be scanned into and out of the SRAM test

circuitry. Only one register can be selected at a time through

the instruction register. Data is serially loaded into the TDI ball

on the rising edge of TCK. Data is output on the TDO ball on

the falling edge of TCK.

EXTEST

The EXTEST instruction enables the preloaded data to be

driven out through the system output pins. This instruction also

selects the boundary scan register to be connected for serial

access between the TDI and TDO in the shift-DR controller

state.

Instruction Register

Three-bit instructions can be serially loaded into the instruction

TDI and TDO balls as shown in the Tap Controller Block

Diagram. Upon power-up, the instruction register is loaded

with the IDCODE instruction. It is also loaded with the IDCODE

instruction if the controller is placed in a reset state as

described in the previous section.

IDCODE

The IDCODE instruction causes a vendor-specific, 32-bit code

to be loaded into the instruction register. It also places the

instruction register between the TDI and TDO balls and allows

the IDCODE to be shifted out of the device when the TAP

controller enters the Shift-DR state.

When the TAP controller is in the Capture-IR state, the two

least significant bits are loaded with a binary “01” pattern to

allow for fault isolation of the board-level serial test data path.

The IDCODE instruction is loaded into the instruction register

upon power-up or whenever the TAP controller is given a test

logic reset state.

Bypass Register

SAMPLE Z

To save time when serially shifting data through registers, it is

sometimes advantageous to skip certain chips. The bypass

TDI and TDO balls. This allows data to be shifted through the

SRAM with minimal delay. The bypass register is set LOW

The SAMPLE Z instruction causes the boundary scan register

to be connected between the TDI and TDO balls when the TAP

controller is in a Shift-DR state. It also places all SRAM outputs

into a High-Z state.

(V ) when the BYPASS instruction is executed.

SAMPLE/PRELOAD

Boundary Scan Register

SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When

the SAMPLE/PRELOAD instructions are loaded into the in-

struction register and the TAP controller is in the Capture-DR

state, a snapshot of data on the inputs and output pins is cap-

tured in the boundary scan register.

The boundary scan register is connected to all the input and

bidirectional balls on the SRAM.

The boundary scan register is loaded with the contents of the

RAM I/O ring when the TAP controller is in the Capture-DR

state and is then placed between the TDI and TDO balls when

the controller is moved to the Shift-DR state. The EXTEST,

SAMPLE/PRELOAD and SAMPLE Z instructions can be used

to capture the contents of the I/O ring.

The user must be aware that the TAP controller clock can only

operate at a frequency up to 20 MHz, while the SRAM clock

operates more than an order of magnitude faster. Because

there is a large difference in the clock frequencies, it is possi-

ble that during the Capture-DR state, an input or output will

undergo a transition. The TAP may then try to capture a signal

while in transition (metastable state). This will not harm the

device, but there is no guarantee as to the value that will be

captured. Repeatable results may not be possible.

The Boundary Scan Order tables show the order in which the

bits are connected. Each bit corresponds to one of the bumps

on the SRAM package. The MSB of the register is connected

to TDI and the LSB is connected to TDO.

Identification (ID) Register

To guarantee that the boundary scan register will capture the

correct value of a signal, the SRAM signal must be stabilized

long enough to meet the TAP controller's capture set-up plus

The ID register is loaded with a vendor-specific, 32-bit code

during the Capture-DR state when the IDCODE command is

loaded in the instruction register. The IDCODE is hardwired

into the SRAM and can be shifted out when the TAP controller

is in the Shift-DR state. The ID register has a vendor code and

other information described in the Identification Register

Definitions table.

hold times (t and t ). The SRAM clock input might not be

captured correctly if there is no way in a design to stop (or

slow) the clock during a SAMPLE/PRELOAD instruction. If this

is an issue, it is still possible to capture all other signals and

simply ignore the value of the CK and CK captured in the

boundary scan register.

TAP Instruction Set

Once the data is captured, it is possible to shift out the data by

putting the TAP into the Shift-DR state. This places the bound-

ary scan register between the TDI and TDO pins.

Overview

Eight different instructions are possible with the three bit

instruction register. All combinations are listed in the

Instruction Codes table. Three of these instructions are listed

as RESERVED and should not be used. The other five instruc-

tions are described in detail below.

PRELOAD allows an initial data pattern to be placed at the

latched parallel outputs of the boundary scan register cells pri-

or to the selection of another boundary scan test operation.

The shifting of data for the SAMPLE and PRELOAD phases

can occur concurrently when required—that is, while data

captured is shifted out, the preloaded data can be shifted in.

Instructions are loaded into the TAP controller during the

Shift-IR state when the instruction register is placed between

TDI and TDO. During this state, instructions are shifted

Document #: 38-05558 Rev. *D

Page 11 of 27

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CY7C1370DV25

CY7C1372DV25

BYPASS

current instruction. When HIGH, it will enable the output

buffers to drive the output bus. When LOW, this bit will place

the output bus into a High-Z condition.

When the BYPASS instruction is loaded in the instruction

advantage of the BYPASS instruction is that it shortens the

boundary scan path when multiple devices are connected

together on a board.

This bit can be set by entering the SAMPLE/PRELOAD or

EXTEST command, and then shifting the desired bit into that

cell, during the “Shift-DR” state. During “Update-DR,” the value

loaded into that shift-register cell will latch into the preload

directly control the output Q-bus pins. Note that this bit is

preset HIGH to enable the output when the device is

powered-up, and also when the TAP controller is in the

“Test-Logic-Reset” state.

EXTEST Output Bus Tri-State

IEEE Standard 1149.1 mandates that the TAP controller be

able to put the output bus into a tri-state mode.

The boundary scan register has a special bit located at bit #85

(for 119-BGA package) or bit #89 (for 165-fBGA package).

When this scan cell, called the “extest output bus tri-state,” is

latched into the preload register during the “Update-DR” state

in the TAP controller, it will directly control the state of the

output (Q-bus) pins, when the EXTEST is entered as the

Reserved

These instructions are not implemented but are reserved for

future use. Do not use these instructions.

TAP Timing

Test Clock

(TCK)

CYC

TMSS

TDIS

TMSH

Test Mode Select

(TMS)

TDIH

Test Data-In

(TDI)

TDOV

TDOX

Test Data-Out

(TDO)

DON’T CARE

UNDEFINED

Document #: 38-05558 Rev. *D

Page 12 of 27

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CY7C1370DV25

CY7C1372DV25

[9, 10]

TAP AC Switching Characteristics Over the Operating Range

Parameter

Clock

Description

Min.

Max.

Unit

TCK Clock Cycle Time

TCK Clock Frequency

TCK Clock HIGH time

TCK Clock LOW time

MHz

TCYC

Output Times

TCK Clock LOW to TDO Valid

TCK Clock LOW to TDO Invalid

TDOV

TDOX

Set-up Times

TMS Set-up to TCK Clock Rise

TDI Set-up to TCK Clock Rise

Capture Set-up to TCK Rise

TMSS

TDIS

Hold Times

TMS Hold after TCK Clock Rise

TDI Hold after Clock Rise

TMSH

TDIH

Capture Hold after Clock Rise

Notes:

9. t and t refer to the set-up and hold time requirements of latching data from the boundary scan register.

10. Test conditions are specified using the load in TAP AC test Conditions. t /t = 1 ns.

Document #: 38-05558 Rev. *D

Page 13 of 27

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CY7C1372DV25

2.5V TAP AC Test Conditions

2.5V TAP AC Output Load Equivalent

1.25V

Input pulse levels ................................................ V to 2.5V

Input rise and fall time..................................................... 1 ns

Input timing reference levels.........................................1.25V

Output reference levels.................................................1.25V

Test load termination supply voltage.............................1.25V

50Ω

TDO

Z_O= 50Ω

20pF

TAP DC Electrical Characteristics And Operating Conditions

[11]

(0°C < TA < +70°C; V = 2.5V ±0.125V unless otherwise noted)

Parameter

Description

Test Conditions

Min.

Max.

Unit

Output HIGH Voltage

Output LOW Voltage

Input HIGH Voltage

Input LOW Voltage

Input Load Current

= –1.0 mA, V

= –100 µA, V

= 2.5V

2.0

2.1

OH1

DDQ

OH2

OL1

OL2

= 8.0 mA, V

= 100 µA

= 2.5V

0.4

0.2

DDQ

= 2.5V

DDQ

1.7

–0.3

–5

+ 0.3

0.7

GND < V < V

µA

DDQ

Scan Register Sizes

Bit Size (x18)

Bit Size (x36)

Instruction

Bypass

Boundary Scan Order (119-ball BGA package)

Boundary Scan Order (165-ball fBGA package)

Identification Register Definitions

Instruction Field

Revision Number (31:29)

Cypress Device ID (28:12)

Cypress JEDEC ID (11:1)

CY7C1372DV25

CY7C1370DV25

Description

Reserved for version number.

000

01011001000100101

00000110100

01011001000010101 Reserved for future use.

00000110100

Allows unique identification of

SRAM vendor.

ID Register Presence (0)

Indicate the presence of an ID

Note:

11.All voltages referenced to V (GND).

Document #: 38-05558 Rev. *D

Page 14 of 27

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CY7C1372DV25

Identification Codes

Instruction

Code

Description

EXTEST

000

Captures I/O ring contents. Places the boundary scan register between TDI and TDO.

Forces all SRAM outputs to High-Z state.

IDCODE

001

010

Loads the ID register with the vendor ID code and places the register between TDI and

TDO. This operation does not affect SRAM operations.

SAMPLE Z

Captures I/O ring contents. Places the boundary scan register between TDI and TDO.

Forces all SRAM output drivers to a High-Z state.

RESERVED

011

100

Do Not Use: This instruction is reserved for future use.

SAMPLE/PRELOAD

Captures I/O ring contents. Places the boundary scan register between TDI and TDO.

Does not affect SRAM operation.

RESERVED

BYPASS

101

110

111

Do Not Use: This instruction is reserved for future use.

Places the bypass register between TDI and TDO. This operation does not affect SRAM

operations.

119-Ball BGA Boundary Scan Order ^{[12, 13]}

Bit #

Ball ID

Bit #

Ball ID

Bit #

Ball ID

Bit #

Ball ID

Internal

Notes:

12. Balls which are NC (No Connect) are pre-set LOW.

13. Bit# 85 is pre-set HIGH.

Document #: 38-05558 Rev. *D

Page 15 of 27

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CY7C1370DV25

CY7C1372DV25

165-Ball FBGA Boundary Scan Order ^{[12, 14]}

Bit #

Ball ID

Bit #

Ball ID

D10

C11

A11

B11

A10

B10

Bit #

Ball ID

N10

P11

P10

R10

R11

H11

N11

M11

L11

K11

J11

M10

L10

K10

J10

C10

H10

G11

F11

E11

D11

G10

F10

E10

Internal

Note:

14. Bit# 89 is pre-set HIGH.

Document #: 38-05558 Rev. *D

Page 16 of 27

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CY7C1370DV25

CY7C1372DV25

DC Input Voltage ................................... –0.5V to V + 0.5V

Maximum Ratings

Current into Outputs (LOW)......................................... 20 mA

(Above which the useful life may be impaired. For user guide-

lines, not tested.)

Static Discharge Voltage.......................................... > 2001V

(per MIL-STD-883, Method 3015)

Storage Temperature .................................–65°C to +150°C

Latch-up Current.................................................... > 200 mA

Ambient Temperature with

Power Applied.............................................–55°C to +125°C

Operating Range

Supply Voltage on V Relative to GND........ –0.5V to +3.6V

Ambient

DD DDQ

Supply Voltage on V

Relative to GND ......–0.5V to +V

Range

Commercial

Industrial

Temperature

DDQ

DC to Outputs in Tri-State................... –0.5V to V

+ 0.5V

0°C to +70°C

2.5V ±5%

DDQ

–40°C to +85°C

[15, 16]

Electrical Characteristics Over the Operating Range

Parameter

Description

Test Conditions

Min.

2.375

2.0

Max.

Unit

Power Supply Voltage

I/O Supply Voltage

Output HIGH Voltage

Output LOW Voltage

2.625

DDQ

for 2.5V I/O

for 2.5V I/O, I = −1.0 mA

for 2.5V I/O, I = 1.0 mA

0.4

+ 0.3V

[17]

Input HIGH Voltage

for 2.5V I/O

1.7

–0.3

–5

[17]

Input LOW Voltage

0.7

Input Leakage Current GND ≤ V ≤ V

except ZZ and MODE

µA

DDQ

Input Current of MODE Input = V

–30

–5

µA

Input = V

Input Current of ZZ

Input = V

µA

Output Leakage Current GND ≤ V ≤ V

Output Disabled

–5

µA

DD,

Operating Supply

f = f

= Max., I

= 0 mA,

4.0-ns cycle, 250 MHz

5.0-ns cycle, 200 MHz

6.0-ns cycle, 167 MHz

350

300

275

160

150

140

OUT

= 1/t

CYC

MAX

Automatic CE

Power-down

Current—TTL Inputs

Max. V , Device Deselected, 4.0-ns cycle, 250 MHz

SB1

≥ V or V ≤ V , f = f

MAX

5.0-ns cycle, 200 MHz

6.0-ns cycle, 167 MHz

1/t

CYC

Automatic CE

Power-down

Current—CMOS Inputs f = 0

Max. V , Device Deselected, All speed grades

SB2

≤ 0.3V or V > V

− 0.3V,

DDQ

Automatic CE

Power-down

Current—CMOS Inputs f = f

Max. V , Device Deselected, 4.0-ns cycle, 250 MHz

135

130

125

SB3

≤ 0.3V or V > V

− 0.3V,

CYC

DDQ

5.0-ns cycle, 200 MHz

6.0-ns cycle, 167 MHz

= 1/t

MAX

Automatic CE

Max. V , Device Deselected, All speed grades

SB4

Power-down

Current—TTL Inputs

≥ V or V ≤ V , f = 0

Notes:

15. Overshoot: V (AC) < V +1.5V (Pulse width less than t

/2), undershoot: V (AC)> –2V (Pulse width less than t

/2).

CYC

16. T

: Assumes a linear ramp from 0V to V (min.) within 200 ms. During this time V < V and V

< V

Power-up

DDQ DD

17. Tested initially and after any design or process change that may affect these parameters.

Document #: 38-05558 Rev. *D

Page 17 of 27

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CY7C1370DV25

CY7C1372DV25

Capacitance^[17]

100 TQFP

Package

119 BGA

Package

165 FBGA

Parameter

Description

Test Conditions

Package

Unit

Input Capacitance

T = 25°C, f = 1 MHz,

= 2.5V.

Clock Input Capacitance

Input/Output Capacitance

CLK

I/O

= 2.5V

DDQ

Thermal Resistance^[17]

100 TQFP

Package

119 BGA

Package

165 FBGA

Package

Parameter

Description

Test Conditions

Unit

Thermal Resistance

(Junction to Ambient)

Test conditions follow standard

test methods and procedures

for measuring thermal

28.66

23.8

20.7

°C/W

Thermal Resistance

(Junction to Case)

4.08

6.2

4.0

°C/W

impedance, per EIA/JESD51.

AC Test Loads and Waveforms

2.5V I/O Test Load

R = 1667Ω

2.5V

OUTPUT

R = 50Ω

OUTPUT

ALL INPUT PULSES

90%

V_DDQ

GND

90%

10%

Z = 50Ω

10%

5 pF

R = 1538Ω

≤ 1 ns

V = 1.25V

INCLUDING

JIG AND

SCOPE

(c)

(a)

(b)

Document #: 38-05558 Rev. *D

Page 18 of 27

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CY7C1370DV25

CY7C1372DV25

[22, 23]

Switching Characteristics Over the Operating Range

–250

–200

–167

Parameter

Description

(typical) to the first access read or write

Min. Max. Min.

Max. Min. Max.

Unit

[18]

Power

Clock

Clock Cycle Time

Maximum Operating Frequency

Clock HIGH

4.0

MHz

CYC

250

200

167

MAX

1.7

2.0

2.2

Clock LOW

Output Times

Data Output Valid After CLK Rise

OE LOW to Output Valid

2.6

3.0

3.4

EOV

DOH

CHZ

CLZ

Data Output Hold After CLK Rise

1.0

1.3

[19, 20, 21]

Clock to High-Z

2.6

3.0

3.4

[19, 20, 21]

Clock to Low-Z

[19, 20, 21]

OE HIGH to Output High-Z

EOHZ

EOLZ

[19, 20, 21]

OE LOW to Output Low-Z

Set-up Times

Address Set-up Before CLK Rise

Data Input Set-up Before CLK Rise

CEN Set-up Before CLK Rise

1.2

1.4

1.5

CENS

WES

ALS

CES

WE, BW Set-up Before CLK Rise

ADV/LD Set-up Before CLK Rise

Chip Select Set-up

Hold Times

Address Hold After CLK Rise

Data Input Hold After CLK Rise

CEN Hold After CLK Rise

0.3

0.4

0.5

CENH

WEH

ALH

CEH

WE, BW Hold After CLK Rise

ADV/LD Hold after CLK Rise

Chip Select Hold After CLK Rise

Notes:

18. This part has a voltage regulator internally; t

is the time power needs to be supplied above V minimum initially, before a Read or Write operation can

Power

be initiated.

19. t

, t

, and t

are specified with AC test conditions shown in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.

EOHZ

CHZ CLZ EOLZ

20. At any given voltage and temperature, t

is less than t

and t

is less than t

to eliminate bus contention between SRAMs when sharing the same

EOHZ

EOLZ

CHZ

CLZ

data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed

to achieve High-Z prior to Low-Z under the same system conditions.

21. This parameter is sampled and not 100% tested.

22. Timing reference 1.25V when V

= 2.5V.

DDQ

23. Test conditions shown in (a) of AC Test Loads unless otherwise noted.

Document #: 38-05558 Rev. *D

Page 19 of 27

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CY7C1370DV25

CY7C1372DV25

Switching Waveforms

[24, 25, 26]

Read/Write/Timing

CYC

CLK

CENS CENH

CEN

CES

CEH

ADV/LD

BWx

ADDRESS

DOH

OEV

CLZ

CHZ

Data

D(A1)

D(A2)

D(A2+1)

Q(A3)

Q(A4)

Q(A4+1)

D(A5)

Q(A6)

In-Out (DQ)

OEHZ

DOH

OELZ

WRITE

D(A1)

WRITE

D(A2)

BURST

WRITE

READ

Q(A3)

READ

Q(A4)

BURST

READ

WRITE

D(A5)

READ

Q(A6)

WRITE

D(A7)

DESELECT

D(A2+1)

Q(A4+1)

DON’T CARE

UNDEFINED

Notes:

24. For this waveform ZZ is tied LOW.

25. When CE is LOW, CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH, CE is HIGH or CE is LOW or CE is HIGH.

26. Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved). Burst operations are optional.

Document #: 38-05558 Rev. *D

Page 20 of 27

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CY7C1370DV25

CY7C1372DV25

Switching Waveforms (continued)

[24, 25, 27]

NOP,STALL and DESELECT Cycles

CLK

CEN

ADV/LD

BWx

ADDRESS

CHZ

D(A4)

D(A1)

Q(A2)

Q(A3)

Q(A5)

Data

In-Out (DQ)

WRITE

D(A1)

READ

Q(A2)

STALL

READ

Q(A3)

WRITE

D(A4)

STALL

NOP

READ

Q(A5)

DESELECT

CONTINUE

DESELECT

DON’T CARE

UNDEFINED

[28, 29]

ZZ Mode Timing

CLK

ZZREC

ZZI

SUPPLY

DDZZ

RZZI

ALL INPUTS

(except ZZ)

DESELECT or READ Only

Outputs (Q)

High-Z

DON’T CARE

Notes:

27. The Ignore Clock Edge or Stall cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle

28. Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device.

29. I/Os are in High-Z when exiting ZZ sleep mode.

Document #: 38-05558 Rev. *D

Page 21 of 27

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CY7C1370DV25

CY7C1372DV25

Ordering Information

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or

visit www.cypress.com for actual products offered.

Speed

(MHz)

Package

Diagram

Operating

Range

Ordering Code

Part and Package Type

167

CY7C1370DV25-167AXC

CY7C1372DV25-167AXC

CY7C1370DV25-167BGC

CY7C1372DV25-167BGC

51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free

Commercial

51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)

CY7C1370DV25-167BGXC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free

CY7C1372DV25-167BGXC

CY7C1370DV25-167BZC

CY7C1372DV25-167BZC

51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)

CY7C1370DV25-167BZXC 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)

Lead-Free

CY7C1372DV25-167BZXC

CY7C1370DV25-167AXI

CY7C1372DV25-167AXI

CY7C1370DV25-167BGI

CY7C1372DV25-167BGI

51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free

Industrial

51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)

CY7C1370DV25-167BGXI 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free

CY7C1372DV25-167BGXI

CY7C1370DV25-167BZI

CY7C1372DV25-167BZI

CY7C1370DV25-167BZXI

CY7C1372DV25-167BZXI

CY7C1370DV25-200AXC

CY7C1372DV25-200AXC

CY7C1370DV25-200BGC

CY7C1372DV25-200BGC

51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)

Lead-Free

200

51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free

Commercial

51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)

CY7C1370DV25-200BGXC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free

CY7C1372DV25-200BGXC

CY7C1370DV25-200BZC

CY7C1372DV25-200BZC

51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)

CY7C1370DV25-200BZXC 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)

Lead-Free

CY7C1372DV25-200BZXC

CY7C1370DV25-200AXI

CY7C1372DV25-200AXI

CY7C1370DV25-200BGI

CY7C1372DV25-200BGI

51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free

Industrial

51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)

CY7C1370DV25-200BGXI 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free

CY7C1372DV25-200BGXI

CY7C1370DV25-200BZI

CY7C1372DV25-200BZI

CY7C1370DV25-200BZXI

CY7C1372DV25-200BZXI

51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)

Lead-Free

Document #: 38-05558 Rev. *D

Page 22 of 27

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CY7C1370DV25

CY7C1372DV25

Ordering Information (continued)

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or

visit www.cypress.com for actual products offered.

250

CY7C1370DV25-250AXC

CY7C1372DV25-250AXC

CY7C1370DV25-250BGC

CY7C1372DV25-250BGC

51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free

Commercial

51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)

CY7C1370DV25-250BGXC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free

CY7C1372DV25-250BGXC

CY7C1370DV25-250BZC

CY7C1372DV25-250BZC

51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)

CY7C1370DV25-250BZXC 51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)

Lead-Free

CY7C1372DV25-250BZXC

CY7C1370DV25-250AXI

CY7C1372DV25-250AXI

CY7C1370DV25-250BGI

CY7C1372DV25-250BGI

51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free

Industrial

51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)

CY7C1370DV25-250BGXI 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free

CY7C1372DV25-250BGXI

CY7C1370DV25-250BZI

CY7C1372DV25-250BZI

CY7C1370DV25-250BZXI

CY7C1372DV25-250BZXI

51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)

Lead-Free

Document #: 38-05558 Rev. *D

Page 23 of 27

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CY7C1370DV25

CY7C1372DV25

Package Diagrams

100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) (51-85050)

16.00 0.20

14.00 0.10

1.40 0.05

100

0.30 0.08

0.65

TYP.

12° 1°

(8X)

SEE DETAIL

0.20 MAX.

1.60 MAX.

R 0.08 MIN.

0.20 MAX.

0° MIN.

SEATING PLANE

STAND-OFF

0.05 MIN.

0.15 MAX.

NOTE:

1. JEDEC STD REF MS-026

0.25

GAUGE PLANE

2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH

MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE

R 0.08 MIN.

0.20 MAX.

BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH

3. DIMENSIONS IN MILLIMETERS

0°-7°

0.60 0.15

0.20 MIN.

51-85050-*B

1.00 REF.

DETAIL

Document #: 38-05558 Rev. *D

Page 24 of 27

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CY7C1370DV25

CY7C1372DV25

Package Diagrams (continued)

119-Ball BGA (14 x 22 x 2.4 mm) (51-85115)

51-85115-*B

Document #: 38-05558 Rev. *D

Page 25 of 27

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CY7C1370DV25

CY7C1372DV25

Package Diagrams (continued)

165-Ball FBGA (13 x 15 x 1.4 mm) (51-85180)

BOTTOM VIEW

PIN 1 CORNER

TOP VIEW

Ø0.05 M C

Ø0.25 M C A B

PIN 1 CORNER

-0.06

Ø0.50 (165X)

-0.06

Ø0.50

(165X)

+0.14

11 10

1.00

5.00

10.00

13.00 0.10

0.15(4X)

NOTES :

SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD)

PACKAGE WEIGHT : 0.475g

JEDEC REFERENCE : MO-216 / DESIGN 4.6C

PACKAGE CODE : BB0AC

SEATING PLANE

51-85180-*A

NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device

Technology, Inc. All product and company names mentioned in this document are the trademarks of their respective holders.

Document #: 38-05558 Rev. *D

Page 26 of 27

of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be

used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its

products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

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CY7C1370DV25

CY7C1372DV25

Document History Page

Document Title: CY7C1370DV25/CY7C1372DV25 18-Mbit (512K x 36/1M x 18)

Pipelined SRAM with NoBL™ Architecture

Document Number: 38-05558

Orig. of

REV.

ECN No. Issue Date Change

Description of Change

254509

288531

See ECN

RKF

SYT

New data sheet

Edited description under “IEEE 1149.1 Serial Boundary Scan (JTAG)” for

non-compliance with 1149.1

Removed 225 Mhz Speed Bin

Added lead-free information for 100-Pin TQFP, 119 BGA and 165 FBGA

package

Added comment of ‘Lead-free BG packages availability’ below the Ordering

Information

326078

See ECN

PCI

Address expansion pins/balls in the pinouts for all packages are modified as

per JEDEC standard

Added description on EXTEST Output Bus Tri-State

Changed description on the Tap Instruction Set Overview and Extest

Changed Θ and Θ for TQFP Package from 31 and 6 °C/W to 28.66 and

4.08 °C/W respectively

Changed Θ and Θ for BGA Package from 45 and 7 °C/W to 23.8 and 6.2

°C/W respectively

Changed Θ and Θ for FBGA Package from 46 and 3 °C/W to 20.7 and

4.0 °C/W respectively

Modified V test conditions

OL, OH

Removed comment of ‘Lead-free BG packages availability’ below the

Ordering Information

Updated Ordering Information Table

418125

See ECN

NXR

Converted from Preliminary to Final

Changed address of Cypress Semiconductor Corporation on Page# 1 from

“3901 North First Street” to “198 Champion Court”

Changed the description of I from Input Load Current to Input Leakage

Current on page# 18

Changed the I current values of MODE on page # 18 from –5 µA and 30 µA

to –30 µA and 5 µA

Changed the I current values of ZZ on page # 18 from –30 µA and 5 µA

to –5 µA and 30 µA

Changed V < V to V < V on page # 18

Updated Ordering Information Table

475677

See ECN

VKN

Added the Maximum Rating for Supply Voltage on V

Relative to GND.

DDQ

Changed t , t from 25 ns to 20 ns and t

from 5 ns to 10 ns in TAP

TH TL

TDOV

AC Switching Characteristics table.

Updated the Ordering Information table.

Document #: 38-05558 Rev. *D

Page 27 of 27

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