CY7C1471BV33
CY7C1473BV33, CY7C1475BV33
72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through
SRAM with NoBL™ Architecture
Features
Functional Description
■ No Bus Latency™ (NoBL™) architecture eliminates dead
cycles between write and read cycles
The CY7C1471BV33, CY7C1473BV33, and CY7C1475BV33
are 3.3V, 2M x 36/4M x 18/1M x 72 synchronous flow through
burst SRAMs designed specifically to support unlimited true
back-to-back read or write operations without the insertion of
wait states. The CY7C1471BV33, CY7C1473BV33, and
CY7C1475BV33 are equipped with the advanced No Bus
Latency (NoBL) logic. NoBL™ is required to enable consecutive
read or write operations with data being transferred on every
clock cycle. This feature dramatically improves the throughput of
data through the SRAM, especially in systems that require
frequent write-read transitions.
■ Supports up to 133 MHz bus operations with zero wait states
■ Data is transferred on every clock
■ Pin compatible and functionally equivalent to ZBT™ devices
■ Internally self timed output buffer control to eliminate the need
to use OE
■ Registered inputs for flow through operation
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock input is qualified by the
Clock Enable (CEN) signal, which when deasserted suspends
operation and extends the previous clock cycle. Maximum
access delay from the clock rise is 6.5 ns (133 MHz device).
■ Byte Write capability
■ 3.3V/2.5V IO supply (V
)
DDQ
■ Fast clock-to-output times
❐ 6.5 ns (for 133 MHz device)
Write operations are controlled by two or four Byte Write Select
■ Clock Enable (CEN) pin to enable clock and suspend operation
■ Synchronous self-timed writes
(BW ) and a Write Enable (WE) input. All writes are conducted
X
with on-chip synchronous self timed write circuitry.
Three synchronous Chip Enables (CE , CE , CE ) and an
1
2
3
■ Asynchronous Output Enable (OE)
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. To avoid bus contention,
the output drivers are synchronously tri-stated during the data
portion of a write sequence. For best practice recommendations,
Guidelines”.
■ CY7C1471BV33, CY7C1473BV33 available in
JEDEC-standard Pb-free 100-pin TQFP, Pb-free and
non-Pb-free 165-Ball FBGA package. CY7C1475BV33
available in Pb-free and non-Pb-free 209-Ball FBGA package
■ Three Chip Enables (CE , CE , CE ) for simple depth
1
2
3
expansion
■ Automatic power down feature available using ZZ mode or CE
deselect
■ IEEE 1149.1 JTAG Boundary Scan compatible
■ Burst Capability—linear or interleaved burst order
■ Low standby power
Selection Guide
Description
Maximum Access Time
133 MHz
6.5
117 MHz
8.5
Unit
ns
Maximum Operating Current
Maximum CMOS Standby Current
305
275
mA
mA
120
120
Cypress Semiconductor Corporation
Document #: 001-15029 Rev. *B
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised March 05, 2008
CY7C1471BV33
CY7C1473BV33, CY7C1475BV33
Logic Block Diagram – CY7C1475BV33 (1M x 72)
ADDRESS
REGISTER
A0, A1,
A
0
A1
A0
A1'
A0'
D1
D0
Q1
Q0
BURST
LOGIC
MODE
C
ADV/LD
CLK
CEN
C
WRITE ADDRESS
WRITE ADDRESS
REGISTER
1
REGISTER
2
O
U
T
O
U
T
P
U
T
S
E
N
S
E
P
U
T
D
A
T
A
ADV/LD
BW
BW
BW
BW
BW
BW
BW
a
R
E
G
I
MEMORY
ARRAY
B
U
F
DQ s
WRITE
DRIVERS
b
c
S
T
E
E
R
I
A
M
P
DQ Pa
DQ Pb
DQ Pc
DQ Pd
DQ Pe
DQ Pf
DQ Pg
DQ Ph
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
F
S
T
E
R
S
d
e
E
R
S
S
f
N
G
g
E
E
BW
h
WE
INPUT
REGISTER 1
INPUT
REGISTER 0
E
E
OE
CE1
CE2
CE3
READ LOGIC
Sleep Control
ZZ
Document #: 001-15029 Rev. *B
Page 3 of 32
CY7C1471BV33
CY7C1473BV33, CY7C1475BV33
Pin Configuration
Figure 1. 100-Pin TQFP Pinout
DQPC
DQC
DQC
VDDQ
VSS
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
DQPB
DQB
DQB
VDDQ
VSS
2
3
4
5
DQC
6
DQB
DQB
DQB
DQB
VSS
BYTE C
BYTE B
DQC
DQC
DQC
VSS
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VDDQ
DQC
DQC
NC
VDDQ
DQB
DQB
VSS
CY7C1471BV33
VDD
NC
NC
VDD
ZZ
VSS
DQD
DQD
VDDQ
VSS
DQA
DQA
VDDQ
VSS
DQD
DQA
DQA
DQA
DQA
VSS
DQD
BYTE D
BYTE A
DQD
DQD
VSS
VDDQ
DQD
DQD
DQPD
VDDQ
DQA
DQA
DQPA
Document #: 001-15029 Rev. *B
Page 4 of 32
CY7C1471BV33
CY7C1473BV33, CY7C1475BV33
Pin Configuration (continued)
Figure 2. 100-Pin TQFP Pinout
NC
1
NC
2
NC
3
VDDQ
4
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
NC
NC
VDDQ
VSS
NC
VSS
NC
5
6
NC
7
DQPA
DQA
DQA
VSS
VDDQ
DQA
DQA
VSS
NC
DQB
DQB
VSS
VDDQ
DQB
DQB
NC
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1473BV33
BYTE A
VDD
NC
BYTE B
VDD
ZZ
VSS
DQB
DQB
VDDQ
VSS
DQB
DQB
DQPB
NC
DQA
DQA
VDDQ
VSS
DQA
DQA
NC
NC
VSS
VDDQ
NC
VSS
VDDQ
NC
NC
NC
NC
NC
Document #: 001-15029 Rev. *B
Page 5 of 32
CY7C1471BV33
CY7C1473BV33, CY7C1475BV33
Pin Configuration (continued)
165-Ball FBGA (15 x 17 x 1.4 mm) Pinout
CY7C1471BV33 (2M x 36)
1
2
A
3
CE1
4
BWC
5
BWB
6
CE
7
8
9
A
10
A
11
NC
NC/576M
NC/1G
DQPC
DQC
CEN
WE
VSS
VSS
ADV/LD
A
B
C
D
3
A
CE2
VDDQ
VDDQ
BWD
VSS
BWA
VSS
VSS
CLK
VSS
VSS
OE
VSS
VDD
A
A
NC
NC
DQC
VDDQ
VDDQ
NC
DQPB
DQB
VDD
DQB
DQC
DQC
DQC
NC
DQC
DQC
DQC
NC
VDDQ
VDDQ
VDDQ
NC
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
NC
DQB
DQB
DQB
NC
DQB
DQB
DQB
ZZ
E
F
G
H
J
DQD
DQD
DQD
DQD
DQD
DQD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQA
DQA
DQA
DQA
DQA
DQA
K
L
DQD
DQPD
DQD
NC
A
VDDQ
VDDQ
A
VDD
VSS
A
VSS
NC
VSS
NC
A1
VSS
NC
VDD
VSS
A
VDDQ
VDDQ
A
DQA
NC
A
DQA
DQPA
M
N
P
NC/144M
TDI
TDO
NC/288M
A0
MODE
A
A
A
TMS
TCK
A
A
A
A
R
CY7C1473BV33 (4M x 18)
1
NC/576M
NC/1G
NC
2
A
3
CE1
4
BWB
5
NC
6
CE
7
8
9
A
10
A
11
A
CEN
WE
VSS
VSS
ADV/LD
A
B
C
D
3
A
CE2
VDDQ
VDDQ
NC
VSS
VDD
BWA
VSS
VSS
CLK
VSS
VSS
OE
VSS
VDD
A
A
NC
NC
DQB
VDDQ
VDDQ
NC
NC
DQPA
DQA
NC
NC
NC
DQB
DQB
DQB
NC
VDDQ
VDDQ
VDDQ
NC
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
NC
NC
NC
DQA
DQA
DQA
ZZ
E
F
NC
NC
G
H
J
NC
NC
DQB
DQB
DQB
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQA
DQA
DQA
NC
NC
NC
K
L
NC
NC
DQB
DQPB
NC
NC
A
VDDQ
VDDQ
A
VDD
VSS
A
VSS
NC
VSS
NC
A1
VSS
NC
VDD
VSS
A
VDDQ
VDDQ
A
DQA
NC
A
NC
NC
M
N
P
NC/144M
TDI
TDO
NC/288M
A0
MODE
A
A
A
TMS
TCK
A
A
A
A
R
Document #: 001-15029 Rev. *B
Page 6 of 32
CY7C1471BV33
CY7C1473BV33, CY7C1475BV33
Pin Configuration (continued)
209-Ball FBGA (14 x 22 x 1.76 mm) Pinout
CY7C1475BV33 (1M × 72)
1
2
3
4
5
6
7
8
9
10
11
DQg
DQg
DQg
DQg
DQg
DQg
DQg
DQg
DQPc
DQc
DQc
A
CE
A
ADV/LD
WE
A
A
CE
A
DQb
DQb
DQb
DQb
DQb
DQb
A
B
2
3
BWS
BWS
BWS
NC
BWS
BWS
NC
BWS
BWS
c
g
b
e
f
BWS NC/576M CE
NC
NC
C
D
h
d
1
a
V
NC/1G
OE
V
NC
SS
DQb
SS
DQb
DQPb
DQf
E
F
DQPg
DQc
V
V
V
V
V
V
V
DD
DDQ
DDQ
DDQ
DDQ
DD
DD
DQPf
DQf
V
V
V
V
V
NC
NC
NC
NC
CEN
NC
NC
V
SS
SS
SS
SS
SS
SS
G
H
J
DQc
DQc
V
V
V
V
V
V
V
DD
V
DDQ
DDQ
DQf
DQf
DD
DDQ
DQf
DDQ
V
V
V
V
V
V
V
DQc
DQc
NC
SS
SS
SS
SS
SS
SS
DQf
DQf
NC
V
DQc
NC
V
V
DDQ
DD
DD
DDQ
DDQ
DDQ
DQf
NC
K
L
CLK
V
V
NC
SS
SS
DD
NC
NC
DQh
DQh
DQh
V
V
V
V
V
V
DDQ
DD
DDQ
DDQ
DQa
DQa
DQa
DDQ
M
N
P
R
T
V
V
V
V
V
SS
DQh
DQh
DQh
V
V
SS
SS
SS
SS
SS
DQa
DQa
DQa
V
V
V
DQh
DQh
DQPd
DQd
DQd
V
V
V
NC
ZZ
DD
DD
DDQ
DDQ
DDQ
DDQ
DQa
DQa
DQPa
DQe
DQe
V
V
V
V
V
V
SS
SS
SS
SS
DD
SS
SS
V
V
V
V
DQPh
DQd
DQd
DQd
DQd
V
V
DDQ
DD
DDQ
DDQ
DDQ
DD
DQPe
DQe
DQe
DQe
DQe
V
NC
A
V
NC
A
NC
A
NC
A
MODE
A
SS
SS
U
V
W
NC/288M
NC/144M
A
A
A1
A
DQd
DQd
A
A
A
A
DQe
DQe
TDI
TDO
TCK
A0
A
TMS
Document #: 001-15029 Rev. *B
Page 7 of 32
CY7C1471BV33
CY7C1473BV33, CY7C1475BV33
Pin Definitions
Name
IO
Description
A , A , A
Input-
Address Inputs used to select one of the Address Locations. Sampled at the rising edge
0
1
Synchronous of the CLK. A
is fed to the two-bit burst counter.
[1:0]
BW , BW ,
Input-
Byte Write Inputs, Active LOW. Qualified with WE to conduct writes to the SRAM. Sampled
A
B
BW , BW ,
Synchronous on the rising edge of CLK.
C
D
BW , BW ,
E
F
BW , BW
G
H
WE
Input-
Write Enable Input, Active LOW. Sampled on the rising edge of CLK if CEN is active LOW.
Synchronous This signal must be asserted LOW to initiate a write sequence.
ADV/LD
Input-
Advance/Load Input. Advances the on-chip address counter or loads a new address. When
Synchronous HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new
address can be loaded into the device for an access. After deselection, drive ADV/LD LOW to
load a new address.
CLK
Input-
Clock
Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN.
CLK is only recognized if CEN is active LOW.
CE
CE
CE
Input-
Chip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction
1
2
3
Synchronous with CE and CE to select or deselect the device.
2
3
Input-
Chip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction
Synchronous with CE and CE to select or deselect the device.
1
3
Input-
Chip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction
Synchronous with CE and CE to select or deselect the device.
1
2
OE
Input-
Output Enable, Asynchronous Input, Active LOW. Combined with the synchronous logic
Asynchronous block inside the device to control the direction of the IO pins. When LOW, the IO pins are enabled
to behave as outputs. When deasserted HIGH, IO pins are tri-stated, and act as input data pins.
OE is masked during the data portion of a write sequence, during the first clock when emerging
from a deselected state, and when the device is deselected.
CEN
ZZ
Input-
Clock Enable Input, Active LOW. When asserted LOW the clock signal is recognized by the
Synchronous SRAM. When deasserted HIGH the clock signal is masked. Because deasserting CEN does
not deselect the device, CEN can be used to extend the previous cycle when required.
Input-
ZZ “Sleep” Input. This active HIGH input places the device in a non-time critical “sleep”
Asynchronous condition with data integrity preserved. During normal operation, this pin must be LOW or left
floating. ZZ pin has an internal pull down.
DQ
IO-
Synchronous by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by the addresses presented during the previous read cycle. The
Bidirectional Data IO Lines. As inputs, they feed into an on-chip data register that is triggered
s
clock rise of the
direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs.
When HIGH, DQ and DQP are placed in a tri-state condition.The outputs are automatically
s
X
tri-stated during the data portion of a write sequence, during the first clock when emerging from
a deselected state, and when the device is deselected, regardless of the state of OE.
DQP
IO-
Bidirectional Data Parity IO Lines. Functionally, these signals are identical to DQ . During
X
s
Synchronous write sequences, DQP is controlled by BW correspondingly.
X
X
MODE
Input Strap Pin Mode Input. Selects the Burst Order of the Device. When tied to Gnd selects linear burst
sequence. When tied to V or left floating selects interleaved burst sequence.
DD
V
V
V
Power Supply Power Supply Inputs to the Core of the Device.
DD
IO Power Supply Power Supply for the IO Circuitry.
DDQ
SS
Ground
Ground for the Device.
Document #: 001-15029 Rev. *B
Page 8 of 32
CY7C1471BV33
CY7C1473BV33, CY7C1475BV33
Pin Definitions (continued)
Name
IO
Description
TDO
JTAG serial
output
Serial Data-Out to the JTAG Circuit. Delivers data on the negative edge of TCK. If the JTAG
feature is not used, this pin must be left unconnected. This pin is not available on TQFP
Synchronous packages.
TDI
JTAG serial input Serial Data-In to the JTAG Circuit. Sampled on the rising edge of TCK. If the JTAG feature is
Synchronous not used, this pin can be left floating or connected to V through a pull up resistor. This pin is
DD
not available on TQFP packages.
TMS
JTAG serial input Serial Data-In to the JTAG Circuit. Sampled on the rising edge of TCK. If the JTAG feature is
Synchronous not used, this pin can be disconnected or connected to V . This pin is not available on TQFP
DD
packages.
TCK
NC
JTAG
-Clock
Clock Input to the JTAG Circuitry. If the JTAG feature is not used, this pin must be connected
to V . This pin is not available on TQFP packages.
SS
-
No Connects. Not internally connected to the die. 144M, 288M, 576M, and 1G are address
expansion pins and are not internally connected to the die.
Single Read Accesses
Functional Overview
A read access is initiated when these conditions are satisfied at
clock rise:
The CY7C1471BV33, CY7C1473BV33, and CY7C1475BV33
are synchronous flow through burst SRAMs designed
specifically to eliminate wait states during write-read transitions.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock signal is qualified with the
Clock Enable input signal (CEN). If CEN is HIGH, the clock signal
is not recognized and all internal states are maintained. All
synchronous operations are qualified with CEN. Maximum
■ CEN is asserted LOW
■ CE , CE , and CE are ALL asserted active
1
2
3
■ WE is deasserted HIGH
■ ADV/LD is asserted LOW
access delay from the clock rise (t
device).
) is 6.5 ns (133 MHz
The address presented to the address inputs is latched into the
Address Register and presented to the memory array and control
logic. The control logic determines that a read access is in
progress and allows the requested data to propagate to the
output buffers. The data is available within 6.5 ns (133 MHz
device) provided OE is active LOW. After the first clock of the
read access, the output buffers are controlled by OE and the
internal control logic. OE must be driven LOW to drive out the
requested data. On the subsequent clock, another operation
(read/write/deselect) can be initiated. When the SRAM is
deselected at clock rise by one of the chip enable signals, output
is tri-stated immediately.
CDV
Accesses may be initiated by asserting all three Chip Enables
(CE , CE , CE ) active at the rising edge of the clock. If (CEN)
1
2
3
is active LOW and ADV/LD is asserted LOW, the address
presented to the device is latched. The access can either be a
read or write operation, depending on the status of the Write
Enable (WE). Byte Write Select (BW ) can be used to conduct
X
Byte Write operations.
Write operations are qualified by the Write Enable (WE). All
writes are simplified with on-chip synchronous self timed write
circuitry.
Burst Read Accesses
Three synchronous Chip Enables (CE , CE , CE ) and an
1
2
3
asynchronous Output Enable (OE) simplify depth expansion. All
operations (reads, writes, and deselects) are pipelined. ADV/LD
must be driven LOW after the device is deselected to load a new
address for the next operation.
The CY7C1471BV33, CY7C1473BV33, and CY7C1475BV33
have an on-chip burst counter that enables the user to supply a
single address and conduct up to four reads without reasserting
the address inputs. ADV/LD must be driven LOW to load a new
address into the SRAM, as described in the Single Read Access
section. The sequence of the burst counter is determined by the
MODE input signal. A LOW input on MODE selects a linear burst
mode, a HIGH selects an interleaved burst sequence. Both burst
counters use A0 and A1 in the burst sequence, and wrap around
when incremented sufficiently. A HIGH input on ADV/LD
increments the internal burst counter regardless of the state of
chip enable inputs or WE. WE is latched at the beginning of a
burst cycle. Therefore, the type of access (read or write) is
maintained throughout the burst sequence.
Document #: 001-15029 Rev. *B
Page 9 of 32
CY7C1471BV33
CY7C1473BV33, CY7C1475BV33
subsequent clock rise, the Chip Enables (CE , CE , and CE )
and WE inputs are ignored and the burst counter is incremented.
Single Write Accesses
1
2
3
Write accesses are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE , CE ,
Drive the correct BW inputs in each cycle of the burst write to
X
1
2
write the correct bytes of data.
and CE are all asserted active, and (3) WE is asserted LOW.
3
The address presented to the address bus is loaded into the
Address Register. The Write signals are latched into the Control
Logic block. The data lines are automatically tri-stated
regardless of the state of the OE input signal. This allows the
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered valid
and the completion of the operation is not guaranteed. The
device must be deselected before entering the “sleep” mode.
external logic to present the data on DQs and DQP .
X
On the next clock rise the data presented to DQs and DQP (or
X
device and the write is complete. Additional accesses
(read/write/deselect) can be initiated on this cycle.
CE , CE , and CE , must remain inactive for the duration of
1
2
3
t
after the ZZ input returns LOW.
ZZREC
The data written during the write operation is controlled by BW
X
Interleaved Burst Address Table
signals.
The
CY7C1471BV33,
CY7C1473BV33,
and
CY7C1475BV33 provide Byte Write capability that is described
(MODE = Floating or V
)
DD
WE with the selected BW input selectively writes to only the
First
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
X
Address
A1: A0
desired bytes. Bytes not selected during a Byte Write operation
remain unaltered. A synchronous self timed write mechanism is
provided to simplify the write operations. Byte write capability is
included to greatly simplify read/modify/write sequences, which
can be reduced to simple byte write operations.
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Because the CY7C1471BV33, CY7C1473BV33, and
CY7C1475BV33 are common IO devices, do not drive data into
the device when the outputs are active. The Output Enable (OE)
can be deasserted HIGH before presenting data to the DQs and
Linear Burst Address Table
(MODE = GND)
DQP inputs. Doing so tri-states the output drivers. As a safety
X
precaution, DQs and DQP are automatically tri-stated during
X
the data portion of a write cycle, regardless of the state of OE.
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
Burst Write Accesses
The CY7C1471BV33, CY7C1473BV33, and CY7C1475BV33
have an on-chip burst counter that enables the user to supply a
single address and conduct up to four write operations without
reasserting the address inputs. ADV/LD must be driven LOW to
load the initial address, as described in section Single Write
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
Description
Sleep mode standby current
Device operation to ZZ
Test Conditions
Min
Max
Unit
I
t
t
t
t
ZZ > V – 0.2V
120
mA
ns
ns
ns
ns
DDZZ
DD
ZZ > V – 0.2V
2t
ZZS
DD
CYC
CYC
ZZ recovery time
ZZ < 0.2V
2t
CYC
ZZREC
ZZI
ZZ active to sleep current
ZZ Inactive to exit sleep current
This parameter is sampled
This parameter is sampled
2t
0
RZZI
Document #: 001-15029 Rev. *B
Page 10 of 32
CY7C1471BV33
CY7C1473BV33, CY7C1475BV33
The truth table for CY7C1471BV33, CY7C1473BV33, and CY7C1475BV33 follows.
Truth Table
Address
Used
Operation
CE CE
ZZ ADV/LD
WE
BW
X
OE
CEN CLK
DQ
CE
1
2
3
Deselect Cycle
None
None
H
X
X
X
L
X
X
L
X
H
X
X
L
L
L
L
L
L
L
L
L
H
L
X
X
X
X
H
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L->H
L->H
L->H
L->H
Tri-State
Tri-State
Tri-State
Tri-State
Deselect Cycle
Deselect Cycle
None
Continue Deselect Cycle
None
X
H
Read Cycle
External
L->H Data Out (Q)
(Begin Burst)
Read Cycle
(Continue Burst)
Next
External
Next
X
L
X
H
X
H
X
H
X
X
L
L
L
L
L
L
L
L
H
L
X
H
X
L
X
X
X
L
L
H
H
X
X
X
X
L
L
L
L
L
L
L
L->H Data Out (Q)
NOP/Dummy Read
(Begin Burst)
L->H
L->H
Tri-State
Tri-State
Dummy Read
(Continue Burst)
X
L
X
L
H
L
Write Cycle
(Begin Burst)
External
Next
L->H Data In (D)
L->H Data In (D)
Write Cycle
(Continue Burst)
X
L
X
L
H
L
X
L
L
NOP/Write Abort
(Begin Burst)
None
H
H
L->H
L->H
Tri-State
Tri-State
Write Abort
Next
X
X
H
X
(Continue Burst)
Ignore Clock Edge (Stall)
Sleep Mode
Current
None
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
H
X
L->H
X
-
H
Tri-State
Notes
1. X = “Don't Care.” H = Logic HIGH, L = Logic LOW. BW = L signifies at least one Byte Write Select is active, BW = Valid signifies that the desired Byte Write Selects
X
X
X
3. When a Write cycle is detected, all IOs are tri-stated, even during Byte Writes.
4. The DQs and DQP pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
X
5. CEN = H, inserts wait states.
6. Device powers up deselected with the IOs in a tri-state condition, regardless of OE.
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQP = tri-state when OE is
X
inactive or when the device is deselected, and DQs and DQP = data when OE is active.
X
Document #: 001-15029 Rev. *B
Page 11 of 32
CY7C1471BV33
CY7C1473BV33, CY7C1475BV33
The read/write truth table for CY7C1471BV33 follows.
Truth Table for Read/Write
Function
WE
BW
BW
X
BW
X
BW
X
A
B
C
D
Read
H
L
L
L
L
L
L
X
H
L
Write No bytes written
H
H
L
H
H
H
L
H
H
H
H
L
Write Byte A – (DQ and DQP )
A
A
Write Byte B – (DQ and DQP )
H
H
H
L
B
B
Write Byte C – (DQ and DQP )
H
H
L
C
C
Write Byte D – (DQ and DQP )
H
L
D
D
Write All Bytes
L
The read/write truth table for CY7C1473BV33 follows.
Truth Table for Read/Write
Function
WE
H
L
BW
BW
X
a
b
Read
X
H
L
Write – No Bytes Written
H
Write Byte a – (DQ and DQP )
L
H
a
a
Write Byte b – (DQ and DQP )
L
H
L
L
b
b
Write Both Bytes
L
L
The read/write truth table for CY7C1475BV33 follows.
Truth Table for Read/Write
Function
WE
H
BW
X
x
Read
Write – No Bytes Written
Write Byte X − (DQ and DQP
L
H
L
L
x
x)
Write All Bytes
L
All BW = L
Note
8. Table only lists a partial listing of the byte write combinations. Any combination of BW is valid. Appropriate write is based on which byte write is active.
X
Document #: 001-15029 Rev. *B
Page 12 of 32
CY7C1471BV33
CY7C1473BV33, CY7C1475BV33
Performing a TAP Reset
IEEE 1149.1 Serial Boundary Scan (JTAG)
A RESET is performed by forcing TMS HIGH (V ) for five rising
edges of TCK. This RESET does not affect the operation of the
SRAM and may be performed while the SRAM is operating.
DD
The CY7C1471BV33, CY7C1473BV33, and CY7C1475BV33
incorporate a serial boundary scan test access port (TAP). This
port operates in accordance with IEEE Standard 1149.1-1990
but does not have the set of functions required for full 1149.1
compliance. These functions from the IEEE specification are
excluded because their inclusion places an added delay in the
critical speed path of the SRAM. Note that the TAP controller
functions in a manner that does not conflict with the operation of
other devices using 1149.1 fully compliant TAPs. The TAP
operates using JEDEC-standard 3.3V or 2.5V IO logic levels.
During power up, the TAP is reset internally to ensure that TDO
comes up in a High-Z state.
TAP Registers
Registers are connected between the TDI and TDO balls and
enable data to be scanned into and out of the SRAM test circuitry.
Only one register is selected at a time through the instruction
register. Data is serially loaded into the TDI ball on the rising
edge of TCK. Data is output on the TDO ball on the falling edge
of TCK.
The CY7C1471BV33, CY7C1473BV33, and CY7C1475BV33
contain a TAP controller, instruction register, boundary scan
register, bypass register, and ID register.
nstruction Register
Disabling the JTAG Feature
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
page 16. During power up, the instruction register is loaded with
the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as described
in the previous section.
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(V ) to prevent clocking of the device. TDI and TMS are
SS
internally pulled up and may be unconnected. They may
alternately be connected to V through a pull up resistor. TDO
DD
must be left unconnected. During power up, the device comes
up in a reset state, which does not interfere with the operation of
the device.
When the TAP controller is in the Capture-IR state, the two least
significant bits are loaded with a binary ‘01’ pattern to enable fault
isolation of the board-level serial test data path.
The 0/1 next to each state represents the value of TMS at the
rising edge of TCK.
Bypass Register
Test Access Port (TAP)
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This allows the shifting of data through the
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
SRAM with minimal delay. The bypass register is set LOW (V
)
SS
when the BYPASS instruction is executed.
Test MODE SELECT (TMS)
Boundary Scan Register
The TMS input gives commands to the TAP controller and is
sampled on the rising edge of TCK. This ball may be left
unconnected if the TAP is not used. The ball is pulled up
internally, resulting in a logic HIGH level.
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM.
The boundary scan register is loaded with the contents of the
RAM IO ring when the TAP controller is in the Capture-DR state
and is then placed between the TDI and TDO balls when the
controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE Z instructions can be used to
capture the contents of the IO ring.
Test Data-In (TDI)
The TDI ball serially inputs information into the registers and can
be connected to the input of any of the registers. The register
between TDI and TDO is chosen by the instruction that is loaded
into the TAP instruction register. For information about loading
page 15. TDI is internally pulled up and can be unconnected if
the TAP is unused in an application. TDI is connected to the most
significant bit (MSB) of any register. (See the TAP Controller
The Boundary Scan Order tables show the order in which the bits
are connected. Each bit corresponds to one of the bumps on the
SRAM package. The MSB of the register is connected to TDI and
the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and can be shifted out when the TAP controller is in
the Shift-DR state. The ID register has a vendor code and other
information described in the section Identification Register
Test Data-Out (TDO)
The TDO output ball serially clocks data-out from the registers.
The output is active depending upon the current state of the TAP
state machine. The output changes on the falling edge of TCK.
TDO is connected to the least significant bit (LSB) of any register.
Document #: 001-15029 Rev. *B
Page 13 of 32
CY7C1471BV33
CY7C1473BV33, CY7C1475BV33
SAMPLE/PRELOAD
TAP Instruction Set
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The
PRELOAD portion of this instruction is not implemented, so the
device TAP controller is not fully 1149.1 compliant.
Overview
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in “Identification
RESERVED and must not be used. The other five instructions
are described in detail in this section.
When the SAMPLE/PRELOAD instruction is loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and bidirectional balls is
captured in the boundary scan register.
The TAP controller used in this SRAM is not fully compliant to the
1149.1 convention because some of the mandatory 1149.1
instructions are not fully implemented.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because there
is a large difference in the clock frequencies, it is possible that
during the Capture-DR state, an input or output may undergo a
transition. The TAP may then try to capture a signal when in
transition (metastable state). This does not harm the device, but
there is no guarantee as to the value that is captured.
Repeatable results may not be possible.
The TAP controller cannot be used to load address data or
control signals into the SRAM and cannot preload the IO buffers.
The SRAM does not implement the 1149.1 commands EXTEST
or INTEST or the PRELOAD portion of SAMPLE/PRELOAD;
rather, it performs a capture of the IO ring when these
instructions are executed.
Instructions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO balls. To execute
the instruction after it is shifted in, the TAP controller must be
moved into the Update-IR state.
To guarantee that the boundary scan register captures the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture setup plus hold
time (t plus t ).
CS
CH
The SRAM clock input might not be captured correctly if there is
no way in a design to stop (or slow) the clock during a
SAMPLE/PRELOAD instruction. If this is an issue, it is still
possible to capture all other signals and simply ignore the value
of the CLK captured in the boundary scan register.
EXTEST
EXTEST is a mandatory 1149.1 instruction which must be
executed whenever the instruction register is loaded with all 0s.
EXTEST is not implemented in this SRAM TAP controller, and
therefore this device is not compliant to 1149.1. The TAP
controller does recognize an all-0 instruction.
After the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO balls.
Note that because the PRELOAD part of the command is not
implemented, putting the TAP to the Update-DR state when
performing a SAMPLE/PRELOAD instruction has the same
effect as the Pause-DR command.
When an EXTEST instruction is loaded into the instruction
register, the SRAM responds as if a SAMPLE/PRELOAD
instruction has been loaded. There is one difference between the
two instructions. Unlike the SAMPLE/PRELOAD instruction,
EXTEST places the SRAM outputs in a High-Z state.
BYPASS
IDCODE
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO balls. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and enables
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state.
Reserved
The IDCODE instruction is loaded into the instruction register
during power up or whenever the TAP controller is in a test logic
reset state.
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register to
be connected between the TDI and TDO balls when the TAP
controller is in a Shift-DR state. It also places all SRAM outputs
into a High-Z state.
Document #: 001-15029 Rev. *B
Page 14 of 32
CY7C1471BV33
CY7C1473BV33, CY7C1475BV33
TAP Controller State Diagram
TEST-LOGIC
1
RESET
0
1
1
1
RUN-TEST/
IDLE
SELECT
DR-SCAN
SELECT
IR-SCAN
0
0
0
1
1
CAPTURE-DR
CAPTURE-IR
0
0
SHIFT-DR
0
SHIFT-IR
0
1
1
1
1
EXIT1-DR
EXIT1-IR
0
0
PAUSE-DR
0
PAUSE-IR
1
0
1
0
0
EXIT2-DR
1
EXIT2-IR
1
UPDATE-DR
UPDATE-IR
1
0
1
0
Document #: 001-15029 Rev. *B
Page 15 of 32
CY7C1471BV33
CY7C1473BV33, CY7C1475BV33
TAP Controller Block Diagram
0
Bypass Register
2
1
0
0
0
Selection
Circuitry
Selection
Circuitry
Instruction Register
31 30 29
Identification Register
TDI
TDO
.
.
.
2
1
x
.
.
.
.
.
2
1
Boundary Scan Register
TCK
TAP CONTROLLER
TM S
Document #: 001-15029 Rev. *B
Page 16 of 32
CY7C1471BV33
CY7C1473BV33, CY7C1475BV33
3.3V TAP AC Test Conditions
2.5V TAP AC Test Conditions
Input pulse levels.................................................V to 3.3V
Input pulse levels................................................ V to 2.5V
SS
SS
Input rise and fall times................................................... 1 ns
Input timing reference levels...........................................1.5V
Output reference levels...................................................1.5V
Test load termination supply voltage...............................1.5V
Input rise and fall time..................................................... 1 ns
Input timing reference levels.........................................1.25V
Output reference levels.................................................1.25V
Test load termination supply voltage.............................1.25V
3.3V TAP AC Output Load Equivalent
2.5V TAP AC Output Load Equivalent
1.25V
1.5V
50Ω
50Ω
TDO
TDO
ZO= 50Ω
20pF
ZO= 50Ω
20pF
TAP DC Electrical Characteristics and Operating Conditions
(0°C < T < +70°C; V = 3.3V ±0.165V unless otherwise noted)
A
DD
Parameter
Description
Test Conditions
Min
2.4
2.0
2.9
2.1
Max
Unit
V
V
V
V
V
V
V
Output HIGH Voltage
Output HIGH Voltage
Output LOW Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
I
I
I
= –4.0 mA, V
= –1.0 mA, V
= –100 µA
= 3.3V
= 2.5V
OH1
OH
OH
OH
DDQ
DDQ
V
V
V
V
V
V
V
V
V
V
V
= 3.3V
= 2.5V
= 3.3V
= 2.5V
= 3.3V
= 2.5V
= 3.3V
= 2.5V
= 3.3V
= 2.5V
V
OH2
OL1
OL2
IH
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
V
I
I
I
= 8.0 mA
= 1.0 mA
= 100 µA
0.4
0.4
0.2
0.2
V
OL
OL
OL
V
V
V
2.0
1.7
V
V
+ 0.3
V
DD
DD
+ 0.3
V
–0.3
–0.3
–5
0.8
V
IL
0.7
5
V
I
GND < V < V
DDQ
µA
X
IN
Note
9. All voltages refer to V (GND).
SS
Document #: 001-15029 Rev. *B
Page 17 of 32
CY7C1471BV33
CY7C1473BV33, CY7C1475BV33
TAP AC Switching Characteristics
Over the Operating Range
Parameter
Clock
Description
Min
Max
Unit
t
t
t
t
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH time
TCK Clock LOW time
50
ns
MHz
ns
TCYC
TF
20
20
20
TH
ns
TL
Output Times
t
t
TCK Clock LOW to TDO Valid
TCK Clock LOW to TDO Invalid
5
ns
ns
TDOV
TDOX
0
Setup Times
t
t
t
TMS Setup to TCK Clock Rise
TDI Setup to TCK Clock Rise
Capture Setup to TCK Rise
5
5
5
ns
ns
ns
TMSS
TDIS
CS
Hold Times
t
t
t
TMS Hold after TCK Clock Rise
TDI Hold after Clock Rise
5
5
5
ns
ns
ns
TMSH
TDIH
CH
Capture Hold after Clock Rise
TAP Timing
Figure 3. TAP Timing
1
2
3
4
5
6
Test Clock
(TCK)
t
t
t
TH
CYC
TL
t
t
t
TM SS
TM SH
Test M ode Select
(TM S)
t
TDIS
TDIH
Test Data-In
(TDI)
t
TDOV
t
TDOX
Test Data-Out
(TDO)
DON’T CARE
UNDEFINED
Notes
10.t and t refer to the setup and hold time requirements of latching data from the boundary scan register.
CS
CH
11.Test conditions are specified using the load in TAP AC Test Conditions. t /t = 1 ns.
R
F
Document #: 001-15029 Rev. *B
Page 18 of 32
CY7C1471BV33
CY7C1473BV33, CY7C1475BV33
Identification Register Definitions
CY7C1471BV33 CY7C1473BV33 CY7C1475BV33
Instruction Field
Description
(2Mx36)
(4Mx18)
(1Mx72)
Revision Number (31:29)
000
01011
000
000
Describes the version number
Reserved for internal use
Device Depth (28:24)
01011
01011
001001
110100
Architecture/Memory Type(23:18)
Bus Width/Density(17:12)
001001
001001
010100
00000110100
Defines memory type and architecture
Defines width and density
100100
Cypress JEDEC ID Code (11:1)
00000110100
00000110100 EnablesuniqueidentificationofSRAM
vendor
ID Register Presence Indicator (0)
1
1
1
Indicates the presence of an ID
register
Scan Register Sizes
Register Name
Bit Size (x36)
Bit Size (x18)
Bit Size (x72)
Instruction
3
1
3
1
3
1
Bypass
ID
32
71
-
32
52
-
32
-
Boundary Scan Order – 165FBGA
Boundary Scan Order – 209BGA
110
Identification Codes
Instruction
Code
Description
EXTEST
000 Captures IO ring contents. Places the boundary scan register between TDI
and TDO. Forces all SRAM outputs to High-Z state. This instruction is not
1149.1-compliant.
IDCODE
001 Loads the ID register with the vendor ID code and places the register
between TDI and TDO. This operation does not affect SRAM operations.
SAMPLE Z
010 Captures IO ring contents. Places the boundary scan register between TDI
and TDO. Forces all SRAM output drivers to a High-Z state.
RESERVED
011
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
100 Captures IO ring contents. Places the boundary scan register between TDI
and TDO. Does not affect SRAM operation. This instruction does not
implement 1149.1 preload function and is therefore not 1149.1 compliant.
RESERVED
RESERVED
BYPASS
101 Do Not Use: This instruction is reserved for future use.
110
111
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not
affect SRAM operations.
Note
12. Bit #24 is “1” in the ID Register Definitions for both 2.5V and 3.3V versions of this device.
Document #: 001-15029 Rev. *B
Page 19 of 32
CY7C1471BV33
CY7C1473BV33, CY7C1475BV33
Boundary Scan Exit Order (2M x 36)
Bit #
1
165-Ball ID
C1
Bit #
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
165-Ball ID
R3
Bit #
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
165-Ball ID
J11
Bit #
61
62
63
64
65
66
67
68
69
70
71
165-Ball ID
B7
B6
A6
B5
A5
A4
B4
B3
A3
A2
B2
2
D1
P2
K10
J10
3
E1
R4
4
D2
P6
H11
G11
F11
E11
D10
D11
C11
G10
F10
E10
A9
5
E2
R6
6
F1
R8
7
G1
F2
P3
8
P4
9
G2
J1
P8
10
11
12
13
14
15
16
17
18
19
20
P9
K1
P10
R9
L1
J2
R10
R11
N11
M11
L11
M10
L10
K11
M1
N1
B9
K2
A10
B10
A8
L2
M2
R1
B8
R2
A7
Boundary Scan Exit Order (4M x 18)
Bit #
1
165-Ball ID
Bit #
14
15
16
17
18
19
20
21
22
23
24
25
26
165-Ball ID
R4
Bit #
27
28
29
30
31
32
33
34
35
36
37
38
39
165-Ball ID
L10
Bit #
40
41
42
43
44
45
46
47
48
49
50
51
52
165-Ball ID
B10
A8
D2
E2
F2
G2
J1
2
P6
K10
J10
3
R6
B8
4
R8
H11
G11
F11
A7
5
P3
B7
6
K1
L1
P4
B6
7
P8
E11
A6
8
M1
N1
R1
R2
R3
P2
P9
D11
C11
A11
B5
9
P10
R9
A4
10
11
12
13
B3
R10
R11
M10
A9
A3
B9
A2
A10
B2
Document #: 001-15029 Rev. *B
Page 20 of 32
CY7C1471BV33
CY7C1473BV33, CY7C1475BV33
Boundary Scan Exit Order (1M x 72)
Bit #
1
209-Ball ID
A1
Bit #
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
209-Ball ID
T1
Bit #
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
209-Ball ID
U10
T11
Bit #
85
209-Ball ID
B11
B10
A11
A10
A7
2
A2
T2
86
3
B1
U1
T10
R11
R10
P11
P10
N11
N10
M11
M10
L11
87
4
B2
U2
88
5
C1
C2
D1
D2
E1
V1
89
6
V2
90
A5
7
W1
W2
T6
91
A9
8
92
U8
9
93
A6
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
E2
V3
94
D6
F1
V4
95
K6
F2
U4
96
B6
G1
G2
H1
H2
J1
W5
V6
L10
97
K3
P6
98
A8
W6
V5
J11
99
B4
J10
100
101
102
103
104
105
106
107
108
109
110
B3
U5
H11
H10
G11
G10
F11
C3
J2
U6
C4
L1
W7
V7
C8
L2
C9
M1
M2
N1
N2
P1
U7
B9
V8
F10
E10
E11
D11
D10
C11
C10
B8
V9
A4
W11
W10
V11
V10
U11
C6
B7
P2
A3
R2
R1
Document #: 001-15029 Rev. *B
Page 21 of 32
CY7C1471BV33
CY7C1473BV33, CY7C1475BV33
DC Input Voltage ................................... –0.5V to V + 0.5V
Maximum Ratings
DD
Current into Outputs (LOW)......................................... 20 mA
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Static Discharge Voltage........................................... >2001V
(MIL-STD-883, Method 3015)
Storage Temperature ................................. –65°C to +150°C
Latch Up Current .................................................... >200 mA
Ambient Temperature with
Power Applied ............................................ –55°C to +125°C
Operating Range
Supply Voltage on V Relative to GND ........–0.5V to +4.6V
DD
Ambient
Range
V
V
DDQ
DD
Temperature
Supply Voltage on V
Relative to GND...... –0.5V to +V
DD
DDQ
Commercial 0°C to +70°C 3.3V –5%/+10% 2.5V – 5%
DC Voltage Applied to Outputs
in Tri-State ...........................................–0.5V to V
to V
+ 0.5V
DD
Industrial
–40°C to +85°C
DDQ
Electrical Characteristics
Over the Operating Range
Parameter
Description
Power Supply Voltage
IO Supply Voltage
Test Conditions
Min
3.135
3.135
2.375
2.4
Max
Unit
V
V
3.6
DD
V
V
V
V
V
I
For 3.3V IO
For 2.5V IO
V
V
DDQ
DD
2.625
V
Output HIGH Voltage
Output LOW Voltage
For 3.3V IO, I = –4.0 mA
V
OH
OL
IH
OH
For 2.5V IO, I = –1.0 mA
2.0
V
OH
For 3.3V IO, I = 8.0 mA
0.4
0.4
V
OL
For 2.5V IO, I = 1.0 mA
V
OL
Input HIGH Voltage
For 3.3V IO
For 2.5V IO
For 3.3V IO
For 2.5V IO
GND ≤ V ≤ V
2.0
1.7
V
V
+ 0.3V
V
DD
DD
+ 0.3V
V
Input LOW Voltage
–0.3
–0.3
–5
0.8
V
IL
0.7
5
V
Input Leakage Current
except ZZ and MODE
μA
X
I
DDQ
Input Current of MODE
Input = V
Input = V
Input = V
Input = V
–30
–5
μA
μA
SS
DD
SS
DD
5
Input Current of ZZ
μA
30
5
μA
I
I
Output Leakage Current
GND ≤ V ≤ V
Output Disabled
–5
μA
OZ
I
DD,
V
Operating Supply
V
f = f
= Max., I
= 0 mA,
7.5 ns cycle, 133 MHz
10 ns cycle, 117 MHz
305
275
200
200
mA
mA
mA
mA
DD
DD
DD
OUT
CYC
Current
= 1/t
MAX
I
I
I
I
Automatic CE
Power Down
Current—TTL Inputs
V = Max, Device Deselected, 7.5 ns cycle, 133 MHz
DD
SB1
SB2
SB3
SB4
V
≥ V or V ≤ V
IN
IH IN IL
10 ns cycle, 117 MHz
f = f
, inputs switching
MAX
Automatic CE
Power Down
Current—CMOS Inputs
V
V
= Max, Device Deselected, All speeds
≤ 0.3V or V > V – 0.3V,
IN DD
120
mA
DD
IN
f = 0, inputs static
Automatic CE
Power Down
Current—CMOS Inputs
V
V
=Max, DeviceDeselected, or 7.5 ns cycle, 133 MHz
200
200
mA
mA
DD
≤ 0.3V or V > V
– 0.3V
IN
IN
DDQ
10 ns cycle, 117 MHz
f = f
, inputs switching
MAX
Automatic CE
Power Down
Current—TTL Inputs
V
V
= Max, Device Deselected, All Speeds
165
mA
DD
≥ V – 0.3V or V
≤
,
IN
DD
IN 0.3V
f = 0, inputs static
Notes
13. Overshoot: V (AC) < V +1.5V (pulse width less than t
/2). Undershoot: V (AC) > –2V (pulse width less than t /2).
CYC
IH
DD
CYC
IL
14. T
: assumes a linear ramp from 0V to V (min.) within 200 ms. During this time V < V and V
< V
.
Power-up
DD
IH
DD
DDQ
DD
15. The operation current is calculated with 50% read cycle and 50% write cycle.
Document #: 001-15029 Rev. *B
Page 22 of 32
CY7C1471BV33
CY7C1473BV33, CY7C1475BV33
Capacitance
Tested initially and after any design or process change that may affect these parameters.
100 TQFP
Package
165 FBGA
Package
209 BGA
Package
Parameter
Description
Test Conditions
Unit
C
Address Input Capacitance
Data Input Capacitance
Control Input Capacitance
Clock Input Capacitance
Input/Output Capacitance
T = 25°C, f = 1 MHz,
6
5
8
6
5
6
5
8
6
5
6
5
8
6
5
pF
pF
pF
pF
pF
ADDRESS
A
V
= 3.3V
= 2.5V
DD
C
C
C
C
DATA
CTRL
CLK
I/O
V
DDQ
Thermal Resistance
Tested initially and after any design or process change that may affect these parameters.
100 TQFP
165 FBGA
Max
209 FBGA
Max
Parameter
Description
Test Conditions
Unit
Max
Θ
Thermal Resistance
(Junction to Ambient)
Test conditions follow standard
test methods and procedures for
measuring thermal impedance,
according to EIA/JESD51.
24.63
16.3
15.2
°C/W
JA
Θ
Thermal Resistance
(Junction to Case)
2.28
2.1
1.7
°C/W
JC
Figure 4. AC Test Loads and Waveforms
3.3V IO Test Load
R = 317Ω
3.3V
OUTPUT
ALL INPUT PULSES
90%
VDDQ
OUTPUT
90%
10%
Z = 50Ω
0
R = 50Ω
10%
L
GND
5 pF
R = 351Ω
≤ 1 ns
≤ 1 ns
V = 1.5V
L
INCLUDING
JIG AND
SCOPE
(c)
(a)
(b)
2.5V IO Test Load
R = 1667Ω
2.5V
OUTPUT
R = 50Ω
OUTPUT
ALL INPUT PULSES
90%
VDDQ
GND
90%
10%
Z = 50Ω
0
10%
L
5 pF
R = 1538Ω
≤ 1 ns
≤ 1 ns
V = 1.25V
L
INCLUDING
JIG AND
SCOPE
(c)
(a)
(b)
Document #: 001-15029 Rev. *B
Page 23 of 32
CY7C1471BV33
CY7C1473BV33, CY7C1475BV33
Switching Characteristics
Over the Operating Range. Unless otherwise noted in the following table, timing reference level is 1.5V when V
= 3.3V and is
DDQ
1.25V when V
= 2.5V. Test conditions shown in (a) of AC Test Loads and Waveforms on page 23 unless otherwise noted.
DDQ
133 MHz
Max
117 MHz
Min Max
Parameter
Description
Unit
Min
t
1
1
ms
POWER
Clock
t
t
t
Clock Cycle Time
Clock HIGH
7.5
2.5
2.5
10
3.0
3.0
ns
ns
ns
CYC
CH
Clock LOW
CL
Output Times
t
t
t
t
t
t
t
Data Output Valid After CLK Rise
6.5
8.5
ns
ns
ns
ns
ns
ns
ns
CDV
DOH
CLZ
Data Output Hold After CLK Rise
2.5
3.0
2.5
3.0
Clock to Low-Z
Clock to High-Z
3.8
3.0
4.5
3.8
CHZ
OEV
OELZ
OEHZ
OE LOW to Output Valid
OE LOW to Output Low-Z
OE HIGH to Output High-Z
0
0
3.0
4.0
Setup Times
t
t
t
t
t
t
Address Setup Before CLK Rise
ADV/LD Setup Before CLK Rise
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
ns
ns
ns
ns
ns
ns
AS
ALS
WES
CENS
DS
WE, BW Setup Before CLK Rise
X
CEN Setup Before CLK Rise
Data Input Setup Before CLK Rise
Chip Enable Setup Before CLK Rise
CES
Hold Times
t
t
t
t
t
t
Address Hold After CLK Rise
ADV/LD Hold After CLK Rise
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
AH
ALH
WEH
CENH
DH
WE, BW Hold After CLK Rise
X
CEN Hold After CLK Rise
Data Input Hold After CLK Rise
Chip Enable Hold After CLK Rise
CEH
Notes
16. This part has an internal voltage regulator; t
is the time that the power must be supplied above V (minimum) initially, before a read or write operation is initiated.
DD
POWER
17. t
, t
,t
, and t
are specified with AC test conditions shown in part (b) of AC Test Loads and Waveforms on page 23. Transition is measured ±200 mV
CHZ CLZ OELZ
OEHZ
from steady-state voltage.
18. At any supplied voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same data
OEHZ
OELZ
CHZ
CLZ
bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve
High-Z before Low-Z under the same system conditions.
19. This parameter is sampled and not 100% tested.
Document #: 001-15029 Rev. *B
Page 24 of 32
CY7C1471BV33
CY7C1473BV33, CY7C1475BV33
Switching Waveforms
Figure 5 shows read-write timing waveform.
Figure 5. Read/Write Timing
t
1
2
3
4
5
6
7
8
9
10
CYC
t
CLK
t
t
t
t
t
CENS
CES
CENH
CEH
CL
CH
CEN
CE
ADV/LD
W E
BW
X
A1
A2
A4
A3
A5
A6
A7
ADDRESS
DQ
t
CDV
t
t
AS
AH
t
t
t
t
CHZ
DOH
OEV
CLZ
D(A1)
t
D(A2)
D(A2+1)
Q(A3)
Q(A4)
Q(A4+1)
D(A5)
Q(A6)
D(A7)
t
OEHZ
t
DS
DH
t
DOH
t
OELZ
OE
COM M AND
W RITE
D(A1)
W RITE
D(A2)
BURST
W RITE
READ
Q(A3)
READ
Q(A4)
BURST
READ
W RITE
D(A5)
READ
Q(A6)
W RITE
D(A7)
DESELECT
D(A2+1)
Q(A4+1)
DON’T CARE
UNDEFINED
Notes
For this waveform ZZ is tied LOW.
20.
21. When CE is LOW, CE is LOW, CE is HIGH, and CE is LOW. When CE is HIGH, CE is HIGH, CE is LOW or CE is HIGH.
1
2
3
1
2
3
22. Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved). Burst operations are optional.
Document #: 001-15029 Rev. *B
Page 25 of 32
CY7C1471BV33
CY7C1473BV33, CY7C1475BV33
Switching Waveforms (continued)
Figure 6. NOP, STALL, and DESELECT Cycles
1
2
3
4
5
6
7
8
9
10
CLK
CEN
CE
ADV/LD
WE
BW [A:D]
ADDRESS
A1
A2
A3
A4
A5
t
CHZ
D(A1)
Q(A2)
Q(A3)
D(A4)
Q(A5)
DQ
t
DOH
COMMAND
WRITE
D(A1)
READ
Q(A2)
STALL
READ
Q(A3)
WRITE
D(A4)
STALL
NOP
READ
Q(A5)
DESELECT
CONTINUE
DESELECT
DON’T CARE
UNDEFINED
Note
23. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrates CEN being used to create a pause. A write is not performed during this cycle.
Document #: 001-15029 Rev. *B
Page 26 of 32
CY7C1471BV33
CY7C1473BV33, CY7C1475BV33
Switching Waveforms (continued)
Figure 7 shows ZZ Mode timing waveform.
Figure 7. ZZ Mode Timing
CLK
t
t
ZZ
ZZREC
ZZ
t
ZZI
I
SUPPLY
I
DDZZ
t
RZZI
ALL INPUTS
(except ZZ)
DESELECT or READ Only
Outputs (Q)
High-Z
DON’T CARE
Notes
24. Device must be deselected when entering ZZ mode. See the The truth table for CY7C1471BV33, CY7C1473BV33, and CY7C1475BV33 follows.
on page 11 for all possible signal conditions to deselect the device.
Document #: 001-15029 Rev. *B
Page 27 of 32
CY7C1471BV33
CY7C1473BV33, CY7C1475BV33
Ordering Information
Not all of the speed, package, and temperature ranges mentioned here are available. Please contact your local sales
Speed
(MHz)
Package
Diagram
Operating
Range
Ordering Code
Part and Package Type
133 CY7C1471BV33-133AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free
CY7C1473BV33-133AXC
Commercial
CY7C1471BV33-133BZC
CY7C1473BV33-133BZC
51-85165 165-Ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)
CY7C1471BV33-133BZXC 51-85165 165-Ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free
CY7C1473BV33-133BZXC
CY7C1475BV33-133BGC 51-85167 209-Ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)
CY7C1475BV33-133BGXC
CY7C1471BV33-133AXI
CY7C1473BV33-133AXI
CY7C1471BV33-133BZI
CY7C1473BV33-133BZI
209-Ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Pb-Free
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free
lndustrial
51-85165 165-Ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)
CY7C1471BV33-133BZXI 51-85165 165-Ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free
CY7C1473BV33-133BZXI
CY7C1475BV33-133BGI
CY7C1475BV33-133BGXI
117 CY7C1471BV33-117AXC
CY7C1473BV33-117AXC
CY7C1471BV33-117BZC
CY7C1473BV33-117BZC
51-85167 209-Ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)
209-Ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Pb-Free
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free
Commercial
51-85165 165-Ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)
CY7C1471BV33-117BZXC 51-85165 165-Ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free
CY7C1473BV33-117BZXC
CY7C1475BV33-117BGC 51-85167 209-Ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)
CY7C1475BV33-117BGXC
CY7C1471BV33-117AXI
CY7C1473BV33-117AXI
CY7C1471BV33-117BZI
CY7C1473BV33-117BZI
209-Ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Pb-Free
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free
lndustrial
51-85165 165-Ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)
CY7C1471BV33-117BZXI 51-85165 165-Ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free
CY7C1473BV33-117BZXI
CY7C1475BV33-117BGI
CY7C1475BV33-117BGXI
51-85167 209-Ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)
209-Ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Pb-Free
Document #: 001-15029 Rev. *B
Page 28 of 32
CY7C1471BV33
CY7C1473BV33, CY7C1475BV33
Package Diagrams
Figure 8. 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm)
16.00 0.20
14.00 0.10
1.40 0.05
100
81
80
1
0.30 0.08
0.65
TYP.
12° 1°
(8X)
SEE DETAIL
A
30
51
31
50
0.20 MAX.
1.60 MAX.
R 0.08 MIN.
0.20 MAX.
0° MIN.
SEATING PLANE
STAND-OFF
0.05 MIN.
0.15 MAX.
NOTE:
1. JEDEC STD REF MS-026
0.25
GAUGE PLANE
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE
R 0.08 MIN.
0.20 MAX.
BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH
3. DIMENSIONS IN MILLIMETERS
0°-7°
0.60 0.15
0.20 MIN.
1.00 REF.
51-85050 *B
DETAIL
A
Document #: 001-15029 Rev. *B
Page 29 of 32
CY7C1471BV33
CY7C1473BV33, CY7C1475BV33
Package Diagrams (continued)
Figure 9. 165-Ball FBGA (15 x 17 x 1.4 mm)
PIN 1 CORNER
BOTTOM VIEW
TOP VIEW
Ø0.05 M C
PIN 1 CORNER
Ø0.25 M C A B
Ø0.45 0.05(165X)
1
2
3
4
5
6
7
8
9
10
11
11 10
9
8
7
6
5
4
3
2
1
A
B
A
B
C
D
C
D
E
E
F
F
G
G
H
J
H
J
K
K
L
L
M
M
N
P
R
N
P
R
A
1.00
5.00
10.00
B
15.00 0.10
0.15(4X)
SEATING PLANE
C
51-85165 *A
Document #: 001-15029 Rev. *B
Page 30 of 32
CY7C1471BV33
CY7C1473BV33, CY7C1475BV33
Package Diagrams (continued)
Figure 10. 209-Ball FBGA (14 x 22 x 1.76 mm)
51-85167 **
Document #: 001-15029 Rev. *B
Page 31 of 32
CY7C1471BV33
CY7C1473BV33, CY7C1475BV33
Document History Page
Document Title: CY7C1471BV33/CY7C1473BV33/CY7C1475BV33, 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through
SRAM with NoBL™ Architecture
Document Number: 001-15029
Issue
Date
REV. ECN NO.
Orig. of Change
Description of Change
**
*A
*B
1024500 See ECN VKN/KKVTMP New Data Sheet
1274731 See ECN
2183566 See ECN
VKN/AESA
VKN/PYRS
Corrected typo in the “NOP, STALL and DESELECT Cycles” waveform
Converted from preliminary to final
Added footnote 16 related to IDD
© Cypress Semiconductor Corporation, 2007-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 001-15029 Rev. *B
Revised March 05, 2008
Page 32 of 32
NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device Technology, Inc. All product and company names mentioned in this document
are the trademarks of their respective holders.
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