Cypress CY7C139 User Manual

CY7C138, CY7C139  
4K x 8/9 Dual-Port Static RAM  
with Sem, Int, Busy  
Features  
Functional Description  
TrueDual-Portedmemorycellsthatenablesimultaneousreads  
of the same memory location  
The CY7C138 and CY7C139 are high speed CMOS 4K x 8 and  
4K x 9 dual-port static RAMs. Various arbitration schemes are  
included on the CY7C138/9 to handle situations when multiple  
processors access the same piece of data. Two ports are  
provided permitting independent, asynchronous access for  
reads and writes to any location in memory. The CY7C138/9 can  
be used as a standalone 8/9-bit dual-port static RAM or multiple  
devices can be combined to function as a 16/18-bit or wider  
master/slave dual-port static RAM. An M/S pin is provided for  
implementing 16/18-bit or wider memory applications without the  
need for separate master and slave devices or additional  
discrete logic. Application areas include interprocessor/multipro-  
cessor designs, communications status buffering, and dual-port  
video/graphics memory.  
4K x 8 organization (CY7C138)  
4K x 9 organization (CY7C139)  
0.65-micron CMOS for optimum speed and power  
High speed access: 15 ns  
Low operating power: I = 160 mA (max.)  
CC  
Fully asynchronous operation  
Automatic power down  
TTL compatible  
Each port has independent control pins: chip enable (CE), read  
or write enable (R/W), and output enable (OE). Two flags are  
provided on each port (BUSY and INT). BUSY signals that the  
port is trying to access the same location currently being  
accessed by the other port. The interrupt flag (INT) permits  
communication between ports or systems by means of a mail  
box. The semaphores are used to pass a flag, or token, from one  
port to the other to indicate that a shared resource is in use. The  
semaphore logic is comprised of eight shared latches. Only one  
side can control the latch (semaphore) at any time. Control of a  
semaphore indicates that a shared resource is in use. An  
automatic power down feature is controlled independently on  
each port by a chip enable (CE) pin or SEM pin.  
Expandable data bus to 32/36 bits or more using  
Master/Slave chip select when using more than one  
device  
On-chip arbitration logic  
Semaphores included to permit software handshaking  
between ports  
INT flag for port-to-port communication  
Available in 68-pin PLCC  
Pb-free packages available  
The CY7C138 and CY7C139 are available in a 68-pin PLCC.  
Logic Block Diagram  
Notes  
1. BUSY is an output in master mode and an input in slave mode.  
2. Interrupt: push-pull output and requires no pull-up resistor.  
Cypress Semiconductor Corporation  
Document #: 38-06037 Rev. *D  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised March 12, 2009  
CY7C138, CY7C139  
Output Current into Outputs (LOW)............................. 20 mA  
Maximum Ratings  
Static Discharge Voltage........................................... >2001V  
(per MIL-STD-883, Method 3015)  
Exceeding maximum ratings may impair the useful life of the  
device. These user guidelines are not tested.  
Latch-Up Current.................................................... >200 mA  
Storage Temperature ................................. –65°C to +150°C  
Operating Range  
Ambient Temperature with  
Power Applied ............................................ –55°C to +125°C  
Ambient  
Range  
V
CC  
Supply Voltage to Ground Potential................–0.5V to +7.0V  
Temperature  
0°C to +70°C  
–40°C to +85°C  
DC Voltage Applied to Outputs  
in High Z State................................................–0.5V to +7.0V  
Commercial  
Industrial  
5V ± 10%  
5V ± 10%  
DC Input Voltage .........................................–0.5V to +7.0V  
Electrical Characteristics Over the Operating Range  
7C138-15  
7C139-15  
7C138-25  
7C139-25  
Parameter  
Description  
Test Conditions  
Unit  
Min  
Max  
Min  
Max  
V
V
V
V
I
Output HIGH Voltage  
Output LOW Voltage  
V
V
= Min., I = –4.0 mA  
2.4  
2.4  
V
V
OH  
OL  
IH  
CC  
OH  
= Min., I = 4.0 mA  
0.4  
0.4  
CC  
OL  
2.2  
2.2  
V
Input LOW Voltage  
0.8  
+10  
+10  
220  
0.8  
+10  
+10  
180  
190  
V
IL  
Input Leakage Current  
Output Leakage Current  
Operating Current  
GND < V < V  
CC  
–10  
–10  
–10  
–10  
μA  
μA  
mA  
IX  
I
I
I
Output Disabled, GND < V < V  
CC  
OZ  
O
V
= Max.,  
= 0 mA,  
Commercial  
Industrial  
CC  
CC  
I
OUT  
Outputs Disabled  
I
I
I
Standby Current  
(Both Ports TTL Levels)  
CE and CE > V ,  
f = f  
Commercial  
Industrial  
60  
130  
15  
40  
50  
mA  
mA  
mA  
SB1  
SB2  
SB3  
L
R
IH  
[7]  
MAX  
Standby Current  
(One Port TTL Level)  
CE and CE > V ,  
Commercial  
Industrial  
110  
120  
15  
L
f = f  
R
IH  
[7]  
MAX  
Standby Current  
(Both Ports CMOS Levels)  
Both Ports  
Commercial  
Industrial  
CE and CE > V – 0.2V,  
CC  
R
30  
V
> V – 0.2V  
IN  
CC  
[7]  
or V < 0.2V, f = 0  
IN  
I
Standby Current  
(One Port CMOS Level)  
One Port  
Commercial  
Industrial  
125  
100  
115  
mA  
SB4  
CE or CE > V – 0.2V,  
L
R
CC  
V
V
> V – 0.2V or  
IN  
CC  
< 0.2V, Active  
IN  
MAX  
Port Outputs, f = f  
Notes  
5. The Voltage on any input or I/O pin cannot exceed the power pin during power-up.  
6. Pulse width < 20 ns.  
7.  
f
= 1/t = All inputs cycling at f = 1/t (except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level  
MAX RC RC  
standby I  
.
SB3  
Document #: 38-06037 Rev. *D  
Page 3 of 17  
     
CY7C138, CY7C139  
Electrical Characteristics Over the Operating Range (continued)  
7C138-35  
7C139-35  
7C138-55  
7C139-55  
Parameter  
Description  
Test Conditions  
Unit  
Min  
Max  
Min  
Max  
V
V
V
V
I
Output HIGH Voltage  
Output LOW Voltage  
V
V
= Min., I = –4.0 mA  
2.4  
2.4  
V
V
OH  
OL  
IH  
CC  
OH  
= Min., I = 4.0 mA  
0.4  
0.4  
CC  
OL  
2.2  
2.2  
V
Input LOW Voltage  
0.8  
+10  
+10  
160  
180  
0.8  
+10  
+10  
160  
180  
V
IL  
Input Leakage Current  
Output Leakage Current  
Operating Current  
GND < V < V  
CC  
–10  
–10  
–10  
–10  
μA  
μA  
mA  
IX  
I
I
I
Output Disabled, GND < V < V  
CC  
OZ  
O
V
= Max.,  
= 0 mA,  
Commercial  
Industrial  
CC  
CC  
I
OUT  
Outputs Disabled  
I
I
I
Standby Current  
(Both Ports TTL Levels)  
CE and CE > V ,  
f = f  
Commercial  
Industrial  
30  
40  
30  
40  
mA  
mA  
mA  
SB1  
SB2  
SB3  
L
R
IH  
[7]  
MAX  
Standby Current  
(One Port TTL Level)  
CE and CE > V ,  
Commercial  
Industrial  
100  
110  
15  
100  
110  
15  
L
f = f  
R
IH  
[7]  
MAX  
Standby Current  
(Both Ports CMOS Levels)  
Both Ports  
Commercial  
Industrial  
CE and CE > V – 0.2V,  
CC  
R
30  
30  
V
> V – 0.2V  
IN  
CC  
[7]  
or V < 0.2V, f = 0  
IN  
I
Standby Current  
(One Port CMOS Level)  
One Port  
Commercial  
Industrial  
90  
90  
mA  
SB4  
CE or CE > V – 0.2V,  
L
R
CC  
100  
100  
V
V
> V – 0.2V or  
IN  
CC  
< 0.2V, Active  
IN  
MAX  
Port Outputs, f = f  
Capacitance[8]  
Parameter  
Description  
Test Conditions  
T = 25°C, f = 1 MHz,  
Max  
Unit  
C
Input Capacitance  
Output Capacitance  
10  
15  
pF  
pF  
IN  
A
V
= 5.0V  
CC  
C
OUT  
Document #: 38-06037 Rev. *D  
Page 4 of 17  
CY7C138, CY7C139  
Figure 2. AC Test Loads and Waveforms  
5V  
R1 = 893Ω  
5V  
R1 = 893Ω  
R
TH  
= 250Ω  
OUTPUT  
C = 30 pF  
OUTPUT  
C = 30pF  
OUTPUT  
C = 5 pF  
R2 = 347Ω  
R2 = 347Ω  
V
TH  
= 1.4V  
(a) Normal Load (Load 1)  
(b) Thévenin Equivalent(Load 1)  
(c) Three-State Delay (Load 3)  
ALL INPUT PULSES  
OUTPUT  
3.0V  
GND  
90%  
90%  
C = 30 pF  
10%  
< 3 ns  
10%  
< 3 ns  
Load (Load 2)  
Switching Characteristics Over the Operating Range  
7C138-15  
7C139-15  
7C138-25  
7C139-25  
7C138-35  
7C139-35  
7C138-55  
7C139-55  
Parameter  
Description  
Unit  
Min  
Max  
Min  
Max  
Min  
Max  
Min  
Max  
READ CYCLE  
tRC  
Read Cycle Time  
15  
3
25  
3
35  
3
55  
3
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
t
t
t
t
t
t
t
t
t
t
Address to Data Valid  
Output Hold From Address Change  
CE LOW to Data Valid  
OE LOW to Data Valid  
OE Low to Low Z  
15  
25  
35  
55  
AA  
OHA  
ACE  
DOE  
LZOE  
15  
10  
25  
15  
35  
20  
55  
25  
3
3
0
3
3
0
3
3
0
3
3
0
OE HIGH to High Z  
10  
10  
15  
15  
15  
25  
20  
20  
35  
25  
25  
55  
HZOE  
CE LOW to Low Z  
LZCE  
CE HIGH to High Z  
HZCE  
CE LOW to Power-Up  
CE HIGH to Power-Down  
PU  
PD  
WRITE CYCLE  
t
t
t
t
t
t
t
Write Cycle Time  
15  
12  
12  
2
25  
20  
20  
2
35  
30  
30  
2
55  
40  
40  
2
ns  
ns  
ns  
ns  
ns  
ns  
ns  
WC  
SCE  
AW  
HA  
CE LOW to Write End  
Address Set-Up to Write End  
Address Hold From Write End  
Address Set-Up to Write Start  
Write Pulse Width  
0
0
0
0
SA  
12  
10  
20  
15  
25  
15  
30  
20  
PWE  
SD  
Data Set-Up to Write End  
Note  
8. Tested initially and after any design or process changes that may affect these parameters.  
Document #: 38-06037 Rev. *D  
Page 5 of 17  
 
CY7C138, CY7C139  
[9]  
Switching Characteristics Over the Operating Range (continued)  
7C138-15  
7C139-15  
7C138-25  
7C139-25  
7C138-35  
7C139-35  
7C138-55  
7C139-55  
Parameter  
Description  
Unit  
Min  
Max  
Min Max  
Min Max  
Min  
Max  
t
t
t
t
t
Data Hold From Write End  
R/W LOW to High Z  
0
0
0
0
ns  
ns  
ns  
ns  
ns  
HD  
[11,12]  
10  
15  
20  
25  
HZWE  
LZWE  
R/W HIGH to Low Z  
3
3
3
3
Write Pulse to Data Delay  
30  
25  
50  
30  
60  
35  
70  
40  
WDD  
Write Data Valid to Read Data Valid  
DDD  
BUSY TIMING  
t
t
t
t
t
t
t
t
BUSY LOW from Address Match  
15  
15  
15  
15  
20  
20  
20  
20  
20  
20  
20  
20  
45  
40  
40  
35  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
BLA  
BHA  
BLC  
BHC  
PS  
BUSY HIGH from Address Mismatch  
BUSY LOW from CE LOW  
BUSY HIGH from CE HIGH  
Port Set-Up for Priority  
5
0
5
0
5
0
5
0
R/W LOW after BUSY LOW  
R/W HIGH after BUSY HIGH  
WB  
13  
20  
30  
40  
WH  
BDD  
BUSY HIGH to Data Valid  
Note 15  
INTERRUPT TIMING  
t
t
INT Set Time  
INT Reset Time  
15  
15  
25  
25  
25  
25  
30  
30  
ns  
ns  
INS  
INR  
SEMAPHORE TIMING  
t
t
t
SEM Flag Update Pulse (OE or SEM) 10  
10  
5
15  
5
20  
5
ns  
ns  
ns  
SOP  
SEM Flag Write to Read Time  
SEM Flag Contention Window  
5
5
SWRD  
SPS  
5
5
5
Switching Waveforms  
Figure 3. Read Cycle No. 1 (Either Port Address Access)  
t
RC  
ADDRESS  
t
AA  
t
OHA  
DATA OUT  
PREVIOUS DATA VALID  
DATA VALID  
[16, 18, 19]  
Figure 4. Read Cycle No. 2 (Either Port CE/OE Access)  
Notes  
9. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified  
/I and 30-pF load capacitance.  
I
OI OH  
10. At any given temperature and voltage condition for any given device, t  
is less than t  
and t  
is less than t  
.
HZCE  
LZCE  
HZOE  
LZOE  
11. Test conditions used are Load 3.  
12. This parameter is guaranteed but not tested.  
13. For information on part-to-part delay through RAM cells from writing port to reading port, refer to Read Timing with Port-to-Port Delay waveform.  
14. Test conditions used are Load 2.  
15. t  
is a calculated parameter and is the greater of t  
– t  
(actual) or t  
– t (actual).  
BDD  
WDD  
PWE  
DDD SD  
Document #: 38-06037 Rev. *D  
Page 6 of 17  
             
CY7C138, CY7C139  
Switching Waveforms (continued)  
SEMor CE  
OE  
t
HZCE  
t
ACE  
t
HZOE  
t
DOE  
t
LZOE  
t
LZCE  
DATA VALID  
DATA OUT  
t
PU  
t
PD  
I
CC  
I
SB  
Figure 5. Read Timing with Port-to-Port Delay (M/S = L)  
t
WC  
ADDRESS  
R/W  
R
MATCH  
t
PWE  
R
t
t
SD  
HD  
DATA  
VALID  
INR  
ADDRESS  
L
MATCH  
t
DDD  
DATA  
VALID  
OUTL  
t
WDD  
Notes  
16. R/W is HIGH for read cycle.  
17. Device is continuously selected CE = LOW and OE = LOW. This waveform cannot be used for semaphore reads.  
18. Address valid prior to or coincident with CE transition LOW.  
19. CE = L, SEM = H when accessing RAM. CE = H, SEM = L when accessing semaphores.  
L
Figure 6. Write Cycle No. 1: OE Three-States Data I/Os (Either Port)  
Document #: 38-06037 Rev. *D  
Page 7 of 17  
       
CY7C138, CY7C139  
Switching Waveforms (continued)  
t
WC  
ADDRESS  
t
SCE  
SEM OR CE  
t
t
AW  
HA  
t
PWE  
R/W  
t
SA  
t
t
HD  
SD  
DATA IN  
OE  
DATA VALID  
t
t
HZOE  
LZOE  
HIGH IMPEDANCE  
DATA OUT  
Figure 7. Write Cycle No. 2: R/W Three-States Data I/Os (Either Port)  
t
WC  
ADDRESS  
t
t
HA  
SCE  
SEM OR CE  
R/W  
t
AW  
t
SA  
t
PWE  
t
t
HD  
SD  
DATA VALID  
DATA IN  
t
t
LZWE  
HZWE  
HIGH IMPEDANCE  
DATA OUT  
Notes  
20. BUSY = HIGH for the writing port.  
21. CE = CE = LOW.  
L
R
22. The internal write time of the memory is defined by the overlap of CE or SEM LOW and R/W LOW. Both signals must be LOW to initiate a write, and  
either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that  
terminates the write.  
23. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t  
or (t  
+ t ) to allow the I/O drivers to turn off  
PWE  
HZWE SD  
and data to be placed on the bus for the required t . If OE is HIGH during a R/W controlled write cycle (as in this example), this requirement does not  
SD  
apply and the write pulse can be as short as the specified t  
24. R/W must be HIGH during all address transitions.  
.
PWE  
Figure 8. Semaphore Read After Write Timing, Either Side  
Document #: 38-06037 Rev. *D  
Page 8 of 17  
         
CY7C138, CY7C139  
Switching Waveforms (continued)  
t
AA  
t
OHA  
A –A  
0
VALID ADDRESS  
VALID ADDRESS  
2
t
AW  
t
ACE  
t
HA  
SEM  
t
t
SOP  
SCE  
t
SD  
I/O  
0
DATA VALID  
DATA  
VALID  
IN  
OUT  
t
HD  
t
SA  
t
PWE  
R/W  
OE  
t
t
DOE  
SWRD  
t
SOP  
WRITE CYCLE  
READ CYCLE  
Figure 9. Timing Diagram of Semaphore Contention  
A
–A  
0L 2L  
MATCH  
R/W  
L
SEM  
L
t
SPS  
A
–A  
MATCH  
0R 2R  
R/W  
R
SEM  
R
Notes  
25. Data I/O pins enter high impedance when OE is held LOW during write.  
26. CE = HIGH for the duration of the above timing (both write and read cycle).  
Figure 10. Timing Diagram of Read with BUSY (M/S = HIGH)  
Document #: 38-06037 Rev. *D  
Page 9 of 17  
   
CY7C138, CY7C139  
Switching Waveforms (continued)  
t
WC  
ADDRESS  
R
MATCH  
t
PWE  
R/W  
R
t
t
HD  
SD  
DATA IN  
VALID  
R
t
PS  
ADDRESS  
MATCH  
L
t
BLA  
t
BHA  
BUSY  
L
t
BDD  
t
DDD  
DATA  
VALID  
OUTL  
t
WDD  
Figure 11. Write Timing with Busy Input (M/S=LOW)  
t
PWE  
R/W  
t
t
WH  
WB  
BUSY  
Notes  
27. I/O = I/O = LOW (request semaphore); CE = CE = HIGH  
0R  
0L  
R
L
28. Semaphores are reset (available to both ports) at cycle start.  
29. If t  
is violated, the semaphore will definitely be obtained by one side or the other, but there is no guarantee which side will control the semaphore.  
SPS  
Figure 12. Busy Timing Diagram No. 1 (CE Arbitration)  
Document #: 38-06037 Rev. *D  
Page 10 of 17  
     
CY7C138, CY7C139  
Switching Waveforms (continued)  
CE Valid First:  
L
ADDRESS  
L,R  
ADDRESS MATCH  
CE  
L
t
PS  
CE  
R
t
t
BHC  
BLC  
BUSY  
R
CE Valid First:  
R
ADDRESS  
ADDRESS MATCH  
L,R  
CE  
R
t
PS  
CE  
L
t
t
BHC  
BLC  
BUSY  
L
Figure 13. Busy Timing Diagram No. 2 (Address Arbitration)  
Left Address Valid First:  
t
or t  
WC  
RC  
ADDRESS  
L
ADDRESS MATCH  
ADDRESS MISMATCH  
t
PS  
ADDRESS  
R
t
t
BHA  
BLA  
BUSY  
R
Right Address Valid First:  
t
or t  
WC  
RC  
ADDRESS  
R
ADDRESS MATCH  
ADDRESS MISMATCH  
t
PS  
ADDRESS  
L
t
t
BHA  
BLA  
BUSY  
L
Note  
30. If t is violated, the busy signal will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted.  
PS  
Document #: 38-06037 Rev. *D  
Page 11 of 17  
 
CY7C138, CY7C139  
Switching Waveforms (continued)  
Figure 14. Interrupt Timing Diagrams  
Left Side Sets INT :  
R
t
WC  
ADDRESS  
WRITE FFF  
L
t
HA  
CE  
L
L
R/W  
INT  
R
t
INS  
Right Side Clears INT :  
R
t
RC  
ADDRESS  
READ FFF  
R
CE  
R
R
t
INR  
R/W  
OE  
R
R
INT  
Right Side Sets INT :  
L
t
WC  
ADDRESS  
WRITE FFE  
R
HA  
t
CE  
R
R/W  
INT  
R
L
t
INS  
Left Side Clears INT :  
L
t
RC  
ADDRESS  
READ FFE  
R
CE  
L
L
t
INR  
R/W  
OE  
L
L
INT  
Notes  
31. t depends on which enable pin (CE or R/W ) is deasserted first.  
HA  
L
L
32. t  
or t  
depends on which enable pin (CE or R/W ) is asserted last.  
INS  
INR  
L
L
Document #: 38-06037 Rev. *D  
Page 12 of 17  
   
CY7C138, CY7C139  
Master/Slave  
Architecture  
A M/S pin is provided in order to expand the word width by config-  
uring the device as either a master or a slave. The BUSY output  
of the master is connected to the BUSY input of the slave. This  
enables the device to interface to a master device with no  
external components.Writing of slave devices must be delayed  
until after the BUSY input has settled. Otherwise, the slave chip  
may begin a write cycle during a contention situation.When  
presented as a HIGH input, the M/S pin allows the device to be  
used as a master and therefore the BUSY line is an output.  
BUSY can then be used to send the arbitration outcome to a  
slave.  
The CY7C138/9 consists of an array of 4K words of 8/9 bits each  
of dual-port RAM cells, I/O and address lines, and control signals  
(CE, OE, R/W). These control pins permit independent access  
for reads or writes to any location in memory. To handle simulta-  
neous writes and reads to the same location, a BUSY pin is  
provided on each port. Two interrupt (INT) pins can be used for  
port–to–port communication. Two semaphore (SEM) control  
pins are used for allocating shared resources. With the M/S pin,  
the CY7C138/9 can function as a master (BUSY pins are  
outputs) or as a slave (BUSY pins are inputs). The CY7C138/9  
has an automatic power down feature controlled by CE. Each  
port is provided with its own output enable control (OE), which  
enables data to be read from the device.  
Semaphore Operation  
The CY7C138/9 provides eight semaphore latches, which are  
separate from the dual-port memory locations. Semaphores are  
used to reserve resources that are shared between the two  
ports.The state of the semaphore indicates that a resource is in  
use. For example, if the left port wants to request a given  
resource, it sets a latch by writing a zero to a semaphore location.  
The left port then verifies its success in setting the latch by  
reading it. After writing to the semaphore, SEM or OE must be  
Functional Description  
Write Operation  
Data must be set up for a duration of t before the rising edge  
SD  
of R/W in order to guarantee a valid write. A write operation is  
controlled by either the OE pin (see Write Cycle No. 1 waveform)  
or the R/W pin (see Write Cycle No. 2 waveform). Data can be  
deasserted for t  
The semaphore value is available t  
before attempting to read the semaphore.  
SOP  
written to the device t  
after the OE is deasserted or t  
HZOE  
HZWE  
+ t  
after the rising  
SWRD  
DOE  
after the falling edge of R/W. Required inputs for non-contention  
operations are summarized in Table 3.  
edge of the semaphore write. If the left port was successful  
(reads a zero), it assumes control over the shared resource,  
otherwise (reads a one) it assumes the right port has control and  
continues to poll the semaphore.When the right side has relin-  
quished control of the semaphore (by writing a one), the left side  
succeeds in gaining control of the a semaphore.If the left side no  
longer requires the semaphore, a 1 is written to cancel its  
request.  
If a location is being written to by one port and the opposite port  
attempts to read that location, a port-to-port flowthrough delay  
must be met before the data is read on the output; otherwise the  
data read is not deterministic. Data is valid on the port t  
the data is presented on the other port.  
after  
DDD  
Read Operation  
Semaphores are accessed by asserting SEM LOW. The SEM  
pin functions as a chip enable for the semaphore latches (CE  
When reading the device, the user must assert both the OE and  
CE pins. Data is available t after CE or t after OE is  
must remain HIGH during SEM LOW). A represents the  
ACE  
DOE  
0–2  
asserted. If the user of the CY7C138/9 wishes to access a  
semaphore flag, then the SEM pin must be asserted instead of  
the CE pin.  
semaphore address. OE and R/W are used in the same manner  
as a normal memory access. When writing or reading a  
semaphore, the other address pins have no effect.  
When writing to the semaphore, only I/O is used. If a zero is  
0
Interrupts  
written to the left port of an unused semaphore, a one will appear  
at the same semaphore address on the right port. That  
semaphore can now only be modified by the side showing zero  
(the left port in this case). If the left port now relinquishes control  
by writing a one to the semaphore, the semaphore is set to 1 for  
both sides. However, if the right port had requested the  
semaphore (written a zero) while the left port had control, the  
right port immediately owns the semaphore after the left port  
releases it. Table 5 shows sample semaphore operations.  
The interrupt flag (INT) permits communications between  
ports.When the left port writes to location FFF, the right port’s  
interrupt flag (INT ) is set. This flag is cleared when the right port  
R
reads that same location. Setting the left port’s interrupt flag  
(INT ) is accomplished when the right port writes to location FFE.  
L
This flag is cleared when the left port reads location FFE. The  
message at FFF or FFE is user-defined. See Table 4 for input  
requirements for INT. INT and INT are push-pull outputs and  
do not require pull-up resistors to operate. BUSY and BUSY  
in master mode are push-pull outputs and do not require pull-up  
R
L
L
R
When reading a semaphore, all eight or nine data lines output  
the semaphore value. The read value is latched in an output  
register to prevent the semaphore from changing state during a  
write from the other port. If both ports attempt to access the  
resistors to operate.  
Busy  
semaphore within t  
of each other, the semaphore is definitely  
SPS  
The CY7C138/9 provides on-chip arbitration to alleviate simulta-  
neous memory location access (contention). If both ports’ CEs  
are asserted and an address match occurs within t of each  
other the Busy logic determines which port has access. If t is  
violated, one port definitely gains permission to the location, but  
it is not guaranteed which one. BUSY will be asserted t  
an address match or t  
obtained by one side or the other, but there is no guarantee which  
side controls the semaphore.  
PS  
Initialization of the semaphore is not automatic and must be reset  
during initialization program at power up. All semaphores on both  
sides should have a 1 written into them at initialization from both  
sides to assure that they are free when needed.  
PS  
after  
BLA  
after CE is taken LOW.  
BLC  
Document #: 38-06037 Rev. *D  
Page 13 of 17  
CY7C138, CY7C139  
Table 3. Non-Contending Read/Write  
Inputs  
Outputs  
I/O  
Operation  
CE  
H
R/W  
X
OE  
X
SEM  
0-7/8  
H
L
High Z  
Power-Down  
H
H
L
Data Out  
High Z  
Read Data in Semaphore  
I/O Lines Disabled  
X
X
H
X
L
H
X
Data In  
Write to Semaphore  
L
L
L
H
L
L
X
X
H
H
L
Data Out  
Data In  
Read  
Write  
X
Illegal Condition  
Table 4. Interrupt Operation Example (assumes BUSY =BUSY =HIGH)  
L
R
Left Port  
Right Port  
Function  
R/W  
X
CE  
OE  
X
A
INT  
L
R/W  
L
CE  
L
OE  
X
A
INT  
X
0-11  
0-11  
Set Left INT  
X
L
L
X
X
FFE  
X
Reset Left INT  
Set Right INT  
Reset Right INT  
X
L
FFE  
FFF  
X
H
X
X
X
X
L
X
X
X
X
X
X
L
X
X
X
X
L
L
FFF  
H
Table 5. Semaphore Operation Example  
Function  
No action  
I/O  
Left I/O  
Right  
Status  
0-7/8  
0-7/8  
1
0
0
1
1
0
1
1
1
0
1
1
Semaphore free  
Left port writes semaphore  
Right port writes 0 to semaphore  
Left port writes 1 to semaphore  
Left port writes 0 to semaphore  
Right port writes 1 to semaphore  
Left port writes 1 to semaphore  
Right port writes 0 to semaphore  
Right port writes 1 to semaphore  
Left port writes 0 to semaphore  
Left port writes 1 to semaphore  
1
1
0
0
1
1
0
1
1
1
Left port obtains semaphore  
Right side is denied access  
Right port is granted access to semaphore  
No change. Left port is denied access  
Left port obtains semaphore  
No port accessing semaphore address  
Right port obtains semaphore  
No port accessing semaphore  
Left port obtains semaphore  
No port accessing semaphore  
Document #: 38-06037 Rev. *D  
Page 14 of 17  
     
CY7C138, CY7C139  
Figure 15. Typical DC and AC Characteristics  
NORMALIZED SUPPLY CURRENT  
vs. AMBIENT TEMPERATURE  
OUTPUT SOURCE CURRENT  
vs. OUTPUT VOLTAGE  
NORMALIZED SUPPLY CURRENT  
vs. SUPPLY VOLTAGE  
200  
160  
120  
80  
1.4  
1.2  
1.0  
0.8  
1.2  
1.0  
ICC  
ICC  
ISB3  
0.8  
0.6  
0.4  
ISB3  
VCC = 5.0V  
TA = 25°C  
VCC = 5.0V  
VIN = 5.0V  
0.6  
0.4  
40  
0
0.2  
0.6  
0.2  
0.0  
5.0  
–55  
25  
125  
0
1.0  
2.0  
3.0  
4.0  
4.0  
4.5  
5.0  
5.5  
6.0  
AMBIENT TEMPERATURE (°C)  
OUTPUT VOLTAGE (V)  
SUPPLY VOLTAGE (V)  
NORMALIZED ACCESS TIME  
vs. AMBIENT TEMPERATURE  
OUTPUT SINK CURRENT  
vs. OUTPUT VOLTAGE  
NORMALIZED ACCESS TIME  
vs. SUPPLY VOLTAGE  
140  
120  
1.6  
1.4  
1.4  
1.3  
1.2  
1.1  
100  
80  
1.2  
1.0  
60  
TA = 25°C  
V
CC = 5.0V  
1.0  
40  
0.8  
V
CC = 5.0V  
20  
0
0.9  
0.8  
TA = 25°C  
0.6  
–55  
0.0  
1.0  
2.0  
3.0  
4.0  
25  
125  
5.0  
4.0  
4.5  
5.0  
5.5  
6.0  
AMBIENT TEMPERATURE (°C)  
OUTPUT VOLTAGE (V)  
SUPPLY VOLTAGE (V)  
VIN = 5.0V  
TYPICAL POWER-ON CURRENT  
vs. SUPPLY VOLTAGE  
TYPICAL ACCESS TIME CHANGE  
vs. OUTPUT LOADING  
NORMALIZED ICC vs. CYCLE TIME  
1.25  
30.0  
25.0  
1.00  
VCC = 5.0V  
TA = 25°C  
VIN = 5.0V  
0.75  
0.50  
1.0  
20.0  
15.0  
10.0  
0.75  
0.25  
0.0  
V
CC = 4.5V  
5.0  
0
TA = 25°C  
0.50  
40  
CYCLE FREQUENCY (MHz)  
10  
28  
66  
0
1.0  
2.0  
3.0  
4.0 5.0  
0
200 400 600 800 1000  
CAPACITANCE (pF)  
SUPPLY VOLTAGE (V)  
Document #: 38-06037 Rev. *D  
Page 15 of 17  
CY7C138, CY7C139  
Ordering Information  
4K x8 Dual-Port SRAM  
Speed  
Package  
Name  
Operating  
Range  
Ordering Code  
(ns)  
Package Type  
15  
CY7C138-15JC  
CY7C138-15JXC  
CY7C138-25JC  
CY7C138-25JXC  
CY7C138-25JI  
CY7C138-25JXI  
CY7C138-35JC  
CY7C138-35JI  
CY7C138-55JC  
CY7C138-55JI  
J81  
J81  
J81  
J81  
J81  
J81  
J81  
J81  
J81  
J81  
68-Lead Plastic Leaded Chip Carrier  
68-Lead Pb-Free Plastic Leaded Chip Carrier  
68-Lead Plastic Leaded Chip Carrier  
68-Lead Pb-Free Plastic Leaded Chip Carrier  
68-Lead Plastic Leaded Chip Carrier  
68-Lead Pb-Free Plastic Leaded Chip Carrier  
68-Lead Plastic Leaded Chip Carrier  
68-Lead Plastic Leaded Chip Carrier  
68-Lead Plastic Leaded Chip Carrier  
68-Lead Plastic Leaded Chip Carrier  
Commercial  
Commercial  
Industrial  
25  
35  
55  
Commercial  
Industrial  
Commercial  
Industrial  
Package Diagram  
Figure 16. 68-Pin Plastic Leaded Chip Carrier J81 (51-85005)  
51-85005-*A  
Document #: 38-06037 Rev. *D  
Page 16 of 17  
CY7C138, CY7C139  
Document History Page  
Document Title: CY7C138/CY7C139 4K x 8/9 Dual-Port Static RAM with Sem, Int, Busy  
Document Number: 38-06037  
Orig. of  
Change  
Submission  
Date  
Rev.  
ECN No.  
Description of Change  
**  
110180  
122287  
393403  
SZV  
RBI  
YIM  
09/29/01  
12/27/02  
Change from Spec number: 38-00536 to 38-06037  
*A  
*B  
Power up requirements added to Maximum Ratings Information  
See ECN Added Pb-Free Logo  
Added Pb-Free parts to ordering information:  
CY7C138-15JXC, CY7C138-25JXC, CY7C139-25JXC  
*C  
*D  
2623658  
2672737  
VKN/PYRS  
GNKK  
12/17/08  
Added CY7C138-25JXI part  
Removed CY7C139 from the Ordering information table  
03/12/2009 Updated title in the Document History table  
Sales, Solutions and Legal Information  
Worldwide Sales and Design Support  
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office  
closest to you, visit us at cypress.com/sales.  
Products  
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PSoC Solutions  
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© Cypress Semiconductor Corporation, 2005-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of  
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for  
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as  
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems  
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),  
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,  
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the express written permission of Cypress.  
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES  
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not  
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where  
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer  
assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
Use may be limited by and subject to the applicable Cypress software license agreement.  
Document #: 38-06037 Rev. *D  
Revised March 12, 2009  
Page 17 of 17  
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