CY7C1353G
4-Mbit (256K x 18) Flow-through SRAM
Features
• Supports up to 133-MHz bus operations with zero wait
states
The CY7C1353G is a 3.3V, 256K x 18 Synchronous
Flow-through Burst SRAM designed specifically to support
unlimited true back-to-back Read/Write operations without the
insertion of wait states. The CY7C1353G is equipped with the
advanced No Bus Latency™ (NoBL™) logic required to
enable consecutive Read/Write operations with data being
transferred on every clock cycle. This feature dramatically
improves the throughput of data through the SRAM, especially
in systems that require frequent Write-Read transitions.
— Data is transferred on every clock
• PincompatibleandfunctionallyequivalenttoZBT™devices
• Internally self timed output buffer control to eliminate the
need to use OE
• Registered inputs for flow-through operation
• Byte Write capability
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. The clock input is qualified by
the Clock Enable (CEN) signal, which when deasserted
suspends operation and extends the previous clock cycle.
Maximum access delay from the clock rise is 6.5 ns (133-MHz
device).
• 256K x 18 common IO architecture
• 2.5V/3.3V IO power supply (V
• Fast clock-to-output times
)
DDQ
— 6.5 ns (for 133-MHz device)
Write operations are controlled by the two Byte Write Select
• Clock Enable (CEN) pin to suspend operation
• Synchronous self timed writes
(BW
) and a Write Enable (WE) input. All writes are
[A:B]
conducted with on-chip synchronous self timed write circuitry.
• Asynchronous Output Enable
Three synchronous Chip Enables (CE , CE , CE ) and an
1
2
3
• Available in Pb-free 100-Pin TQFP package
• Burst Capability — linear or interleaved burst order
• Low standby power
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. To avoid bus contention,
the output drivers are synchronously tri-stated during the data
portion of a write sequence.
Logic Block Diagram
ADDRESS
REGISTER
A0, A1, A
A1
A0
A1'
A0'
D1
D0
Q1
Q0
MODE
BURST
LOGIC
CE
ADV/LD
CLK
CEN
C
C
WRITE ADDRESS
REGISTER
O
U
T
P
U
T
D
A
T
S
E
N
S
ADV/LD
BWA
A
B
U
F
MEMORY
ARRAY
WRITE
DRIVERS
E
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
S
T
E
E
R
I
DQs
DQPA
DQPB
BWB
A
M
P
F
E
R
S
S
WE
E
N
G
INPUT
REGISTER
E
OE
READ LOGIC
CE1
CE2
CE3
SLEEP
CONTROL
ZZ
Note:
1.For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05515 Rev. *E
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised July 09, 2007
CY7C1353G
Pin Definitions
Name
IO
Input-
Synchronous of the CLK. A
Description
Address Inputs used to select one of the 256K address locations. Sampled at the rising edge
are fed to the two-bit burst counter.
A , A , A
0
1
[1:0]
BW
Input-
Byte Write Inputs, Active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on
[A:B]
Synchronous the rising edge of CLK.
WE
Input-
Write Enable Input, Active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This
Synchronous signal must be asserted LOW to initiate a write sequence.
ADV/LD
Input-
Advance/Load Input. Used to advance the on-chip address counter or load a new address. When
Synchronous HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new
address can be loaded into the device for an access. After being deselected, ADV/LD must be
driven LOW to load a new address.
CLK
Input-Clock Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK
is only recognized if CEN is active LOW.
CE
CE
CE
Input-
Chip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with
1
2
3
Synchronous CE , and CE to select/deselect the device.
2
3
Input-
Chip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction with
Synchronous CE and CE to select/deselect the device.
1
3
Input-
Chip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with
Synchronous CE and CE to select/deselect the device.
1
2
OE
Input-
Output Enable, asynchronous input, Active LOW. Combined with the synchronous logic block
Asynchronous inside the device to control the direction of the IO pins. When LOW, the IO pins are allowed to
behave as outputs. When deasserted HIGH, IO pins are tri-stated, and act as input data pins. OE
is masked during the data portion of a write sequence, during the first clock when emerging from
a deselected state, when the device has been deselected.
CEN
ZZ
Input-
Clock Enable Input, Active LOW. When asserted LOW the Clock signal is recognized by the
Synchronous SRAM. When deasserted HIGH the Clock signal is masked. While deasserting CEN does not
deselect the device, CEN can be used to extend the previous cycle when required.
Input-
ZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition
Asynchronous with data integrity preserved. During normal operation, this pin has to be low or left floating. ZZ pin
has an internal pull down.
DQ
IO-
Bidirectional Data IO Lines. As inputs, they feed into an on-chip data register that is triggered by
s
Synchronous the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified
by address during the clock rise of the read cycle. The direction of the pins is controlled by OE and
the internal control logic. When OE is asserted LOW, the pins can behave as outputs. When HIGH,
DQ and DQP
are placed in a tri-state condition. The outputs are automatically tri-stated during
s
[A:B]
the data portion of a write sequence, during the first clock when emerging from a deselected state,
and when the device is deselected, regardless of the state of OE.
DQP
IO-
Bidirectional Data Parity IO Lines. Functionally, these signals are identical to DQ . During write
[A:B]
s
Synchronous sequences, DQP
is controlled by BW correspondingly.
[A:B]
x
MODE
Input
Strap Pin
MODE Input. Selects the burst order of the device.
When tied to Gnd selects linear burst sequence. When tied to V or left floating selects interleaved
DD
burst sequence.
V
V
Power Supply Power supply inputs to the core of the device.
DD
IO Power
Supply
Power supply for the IO circuitry.
DDQ
V
Ground
–
Ground for the device.
SS
NC,NC/9M,
NC/18M,
NC/36M
No Connects. Not internally connected to the die. NC/9M, NC/18M, NC/72M, NC/144M, NC/288M,
are address expansion pins are not internally connected to the die.
NC/72M,
NC/144M,
NC/288M,
Document #: 38-05515 Rev. *E
Page 3 of 13
CY7C1353G
Therefore, the type of access (Read or Write) is maintained
throughout the burst sequence.
Functional Overview
The CY7C1353G is a synchronous flow-through burst SRAM
designed specifically to eliminate wait states during
Write-Read transitions. All synchronous inputs pass through
input registers controlled by the rising edge of the clock. The
clock signal is qualified with the Clock Enable input signal
(CEN). If CEN is HIGH, the clock signal is not recognized and
all internal states are maintained. All synchronous operations
are qualified with CEN. Maximum access delay from the clock
Single Write Accesses
Write access are initiated when these conditions are satisfied
at clock rise:
• CEN is asserted LOW
• CE , CE , and CE are ALL asserted active
1
2
3
• The write signal WE is asserted LOW.
rise (t
) is 6.5 ns (133-MHz device).
CDV
The address presented to the address bus is loaded into the
Address Register. The write signals are latched into the
Control Logic block. The data lines are automatically tri-stated
regardless of the state of the OE input signal. This allows the
Accesses can be initiated by asserting all three Chip Enables
(CE , CE , CE ) active at the rising edge of the clock. If Clock
1
2
3
Enable (CEN) is active LOW and ADV/LD is asserted LOW,
the address presented to the device is latched. The access
can either be a read or write operation, depending on the
status of the Write Enable (WE). BW
conduct byte write operations.
external logic to present the data on DQs and DQP
.
[A:B]
On the next clock rise the data presented to DQs and DQP
can be used to
[A:B]
[A:B]
(or a subset for byte write operations, see truth table for
details) inputs is latched into the device and the write is
complete. Additional accesses (Read/Write/Deselect) can be
initiated on this cycle.
Write operations are qualified by the Write Enable (WE). All
writes are simplified with on-chip synchronous self timed write
circuitry.
The data written during the Write operation is controlled by
Three synchronous Chip Enables (CE , CE , CE ) and an
1
2
3
BW
signals. The CY7C1353G provides byte write
[A:B]
asynchronous Output Enable (OE) simplify depth expansion.
All operations (Reads, Writes, and Deselects) are pipe lined.
ADV/LD must be driven LOW after the device has been
deselected to load a new address for the next operation.
capability that is described in the truth table. Asserting the
Write Enable input (WE) with the selected Byte Write Select
input selectively writes to only the desired bytes. Bytes not
selected during a byte write operation remains unaltered. A
synchronous self timed write mechanism has been provided
to simplify the write operations. Byte write capability has been
included to greatly simplify Read/Modify/Write sequences,
which can be reduced to simple byte write operations.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE , CE ,
1
2
and CE are ALL asserted active, (3) the Write Enable input
3
Because the CY7C1353G is a common IO device, data must
not be driven into the device while the outputs are active. The
Output Enable (OE) can be deasserted HIGH before
signal WE is deasserted HIGH, and 4) ADV/LD is asserted
LOW. The address presented to the address inputs is latched
into the Address Register and presented to the memory array
and control logic. The control logic determines that a read
access is in progress and allows the requested data to
propagate to the output buffers. The data is available within 6.5
ns (133-MHz device) provided OE is active LOW. After the first
clock of the read access, the output buffers are controlled by
OE and the internal control logic. OE must be driven LOW in
order for the device to drive out the requested data. On the
subsequent clock, another operation (Read/Write/Deselect)
can be initiated. When the SRAM is deselected at clock rise
by one of the chip enable signals, its output is tri-stated
immediately.
presenting data to the DQs and DQP
inputs. Doing so
[A:B]
tri-states the output drivers. As a safety precaution, DQs and
DQP .are automatically tri-stated during the data portion of
[A:B]
a write cycle, regardless of the state of OE.
Burst Write Accesses
The CY7C1353G has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to
four Write operations without reasserting the address inputs.
ADV/LD must be driven LOW to load the initial address, as
described in the Single Write Access section. When ADV/LD
is driven HIGH on the subsequent clock rise, the Chip Enables
Burst Read Accesses
(CE , CE , and CE ) and WE inputs are ignored and the burst
1
2
3
counter is incremented. The correct BW
inputs must be
[A:B]
The CY7C1353G has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to
four Reads without reasserting the address inputs. ADV/LD
must be driven LOW to load a new address into the SRAM, as
described in the Single Read Access section. The sequence
of the burst counter is determined by the MODE input signal.
A LOW input on MODE selects a linear burst mode, a HIGH
selects an interleaved burst sequence. Both burst counters
use A0 and A1 in the burst sequence, and wraps around when
incremented sufficiently. A HIGH input on ADV/LD increments
the internal burst counter regardless of the state of chip enable
inputs or WE. WE is latched at the beginning of a burst cycle.
driven in each cycle of the burst write, to write the correct bytes
of data.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE , CE , and CE , must remain inactive
1
2
3
for the duration of t
after the ZZ input returns LOW.
ZZREC
Document #: 38-05515 Rev. *E
Page 4 of 13
CY7C1353G
Interleaved Burst Address Table
(MODE = Floating or VDD
Linear Burst Address Table (MODE = GND)
)
First
Address
A1, A0
Second
Address
A1, A0
Third
Address
A1, A0
Fourth
Address
A1, A0
First
Address
A1, A0
Second
Address
A1, A0
Third
Address
A1, A0
Fourth
Address
A1, A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
ZZ Mode Electrical Characteristics
Parameter
Description
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
Test Conditions
Min
Max
Unit
mA
ns
I
t
t
t
t
ZZ > V − 0.2V
40
DDZZ
DD
ZZ > V − 0.2V
2t
ZZS
DD
CYC
ZZ < 0.2V
2t
ns
ZZREC
ZZI
CYC
ZZ active to sleep current
ZZ inactive to exit sleep current
This parameter is sampled
This parameter is sampled
2t
ns
CYC
0
ns
RZZI
Address
Used
Operation
Deselect Cycle
CE
H
X
CE CE
ZZ ADV/LD WE BW
X
OE CEN CLK
DQ
1
2
3
None
None
X
X
L
X
H
X
X
L
L
L
L
L
L
L
L
L
L
X
X
X
X
H
X
H
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L
L
L->H Tri-State
L->H Tri-State
L->H Tri-State
L->H Tri-State
L->H Data Out (Q)
L->H Data Out (Q)
L->H Tri-State
Deselect Cycle
Deselect Cycle
None
X
L
Continue Deselect Cycle
READ Cycle (Begin Burst)
READ Cycle (Continue Burst)
None
X
X
H
X
H
H
L
External
Next
L
X
X
L
H
L
L
NOP/DUMMY READ (Begin
Burst)
External
L
H
DUMMY READ (Continue Burst)
WRITE Cycle (Begin Burst)
Next
External
Next
X
L
X
H
X
H
X
L
L
L
L
L
H
L
X
L
X
L
H
X
X
X
L
L
L
L
L->H Tri-State
L->H Data In (D)
L->H Data In (D)
L->H Tri-State
WRITE Cycle (Continue Burst)
X
L
X
L
H
L
X
L
L
NOP/WRITE ABORT (Begin
Burst)
None
H
WRITE ABORT (Continue Burst)
IGNORE CLOCK EDGE (Stall)
SLEEP MODE
Next
Current
None
X
X
X
X
X
X
X
X
X
L
L
H
X
X
X
X
X
H
X
X
X
X
X
L
H
X
L->H Tri-State
L->H
X
–
H
Tri-State
Notes:
2. X =”Don't Care.” H = Logic HIGH, L = Logic LOW. BWx = L signifies at least one Byte Write Select is active, BWx = Valid signifies that the desired byte write
selects are asserted, see truth table for details.
3. Write is defined by BW , and WE. See truth table for Read/Write.
X
4. When a write cycle is detected, all IOs are tri-stated, even during byte writes.
5. The DQs and DQP
pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
[A:B]
6. CEN = H, inserts wait states.
7. Device powers up deselected and the IOs in a tri-state condition, regardless of OE.
8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQP
= tri-state when OE
[A:B]
is inactive or when the device is deselected, and DQs and DQP
= data when OE is active.
[A:B]
Document #: 38-05515 Rev. *E
Page 5 of 13
CY7C1353G
Function
WE
H
L
BW
BW
X
A
B
Read
X
H
L
Write – No bytes written
H
Write Byte A – (DQ and DQP )
L
H
A
A
Write Byte B – (DQ and DQP )
L
H
L
L
B
B
Write All Bytes
L
L
Note:
9. Table only lists a partial listing of the byte write combinations. Any combination of BW[A:D] is valid. Appropriate write is based on which byte write is active.
Document #: 38-05515 Rev. *E
Page 6 of 13
CY7C1353G
Maximum Ratings
DC Input Voltage ................................... –0.5V to V + 0.5V
DD
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage.......................................... > 2001V
(MIL-STD-883, Method 3015)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Latch up Current.................................................... > 200 mA
Supply Voltage on V Relative to GND........ –0.5V to +4.6V
DD
Operating Range
Supply Voltage on V
Relative to GND ......–0.5V to +V
DD
DDQ
Ambient
DC Voltage Applied to Outputs
in tri-state ............................................ –0.5V to V
Range
Commercial
Industrial
Temperature (T )
V
V
DDQ
A
DD
+ 0.5V
DDQ
0°C to +70°C 3.3V – 5%/+10% 2.5V–5%
to V
DD
−40°C to +85°C
Electrical Characteristics Over the Operating Range
Parameter
Description
Power Supply Voltage
IO Supply Voltage
Test Conditions
Min
3.135
2.375
2.4
Max
Unit
V
V
V
V
3.6
DD
V
V
DDQ
OH
DD
Output HIGH Voltage
for 3.3V IO, I = –4.0 mA
V
OH
for 2.5V IO, I = –1.0 mA
2.0
V
OH
V
V
V
I
Output LOW Voltage
for 3.3V IO, I = 8.0 mA
0.4
0.4
V
OL
IH
IL
OH
for 2.5V IO, I = 1.0 mA
V
OH
Input HIGH Voltage
Input HIGH Voltage
for 3.3V IO
for 2.5V IO
for 3.3V IO
for 2.5V IO
GND ≤ V ≤ V
2.0
1.7
V
V
+ 0.3V
+ 0.3V
0.8
V
DD
DD
V
Input LOW Voltage
–0.3
–0.3
−5
V
Input LOW Voltage
0.7
V
Input Leakage Current
except ZZ and MODE
5
µA
X
I
DDQ
Input Current of MODE
Input = V
Input = V
Input = V
Input = V
–30
–5
µA
µA
SS
DD
SS
DD
5
Input Current of ZZ
µA
30
5
µA
I
I
Output Leakage Current
GND ≤ V ≤ V
, Output Disabled
–5
µA
OZ
I
DDQ
V
Operating Supply
V = Max., I
DD
= 0 mA,
7.5-ns cycle, 133 MHz
10-ns cycle, 100 MHz
225
205
90
mA
mA
mA
mA
DD
DD
OUT
Current
f = f
= 1/t
MAX CYC
I
I
I
I
Automatic CE Power down
Current—TTL Inputs
V
= Max, Device Deselected, 7.5-ns cycle, 133 MHz
DD
SB1
V
≥ V or V ≤ V , f = f ,
IN
IH
IN
IL
MAX
10-ns cycle, 100 MHz
= Max, Device Deselected, All speeds
DD
80
inputs switching
Automatic CE Power down
Current—CMOS Inputs
V
V
40
mA
SB2
SB3
SB4
≥ V – 0.3V or V ≤ 0.3V,
IN
DD
IN
f = 0, inputs static
Automatic CE Power down
Current—CMOS Inputs
V
V
f = f
= Max, Device Deselected, 7.5-ns cycle, 133 MHz
75
65
mA
mA
DD
≥ V
– 0.3V or V ≤ 0.3V,
IN
DDQ
IN
10-ns cycle, 100 MHz
, inputs switching
MAX
Automatic CE Power down
Current—TTL Inputs
V
V
= Max, Device Deselected, All speeds
45
mA
DD
≥ V – 0.3V or V ≤ 0.3V,
IN
DD
IN
f = 0, inputs static
Notes:
10. Overshoot: V (AC) < V +1.5V (Pulse width less than t
/2), undershoot: V (AC)> –2V (Pulse width less than t
/2).
IH
DD
CYC
IL
CYC
.
11. T
: Assumes a linear ramp from 0V to V (min.) within 200 ms. During this time V < V and V
< V
Power-up
DD
IH
DD
DDQ DD
Document #: 38-05515 Rev. *E
Page 7 of 13
CY7C1353G
Capacitance[12]
100 TQFP
Parameter
Description
Input Capacitance
Test Conditions
T = 25°C, f = 1 MHz,
Max
Unit
pF
C
C
C
5
5
5
IN
A
V
= 3.3V
=3.3V
DD
Clock Input Capacitance
IO Capacitance
pF
CLOCK
IO
V
DDQ
pF
Thermal Resistance[12]
100 TQFP
Package
Parameters
Description
Test Conditions
Unit
Θ
Thermal Resistance
(Junction to Ambient)
Test conditions follow standard test methods and
procedures for measuring thermal impedance,
according to EIA/JESD51.
30.32
°C/W
JA
Θ
Thermal Resistance
(Junction to Case)
6.85
°C/W
JC
.
AC Test Loads and Waveforms
3.3V IO Test Load
R = 317Ω
3.3V
OUTPUT
ALL INPUT PULSES
90%
VDDQ
OUTPUT
90%
10%
Z = 50Ω
0
10%
R = 50Ω
L
GND
5 pF
R = 351Ω
≤ 1ns
≤ 1ns
V = 1.5V
T
INCLUDING
JIG AND
SCOPE
(a)
(b)
(c)
2.5V IO Test Load
R = 1667Ω
2.5V
OUTPUT
R = 50Ω
OUTPUT
ALL INPUT PULSES
90%
VDDQ
GND
90%
10%
Z = 50Ω
0
10%
L
5 pF
INCLUDING
R =1538Ω
≤ 1ns
≤ 1ns
V = 1.25V
T
JIG AND
SCOPE
(a)
(b)
(c)
Note:
12.Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05515 Rev. *E
Page 8 of 13
CY7C1353G
Switching Characteristics Over the Operating Range
–133
–100
Parameter
Description
Min
Max
Min
Max
Unit
t
V
(Typical) to the first Access
1
1
ms
POWER
DD
Clock
t
t
t
Clock Cycle Time
Clock HIGH
7.5
2.5
2.5
10
4.0
4.0
ns
ns
ns
CYC
CH
Clock LOW
CL
Output Times
t
t
t
t
t
t
t
Data Output Valid After CLK Rise
Data Output Hold After CLK Rise
6.5
8.0
ns
ns
ns
ns
ns
ns
ns
CDV
DOH
CLZ
2.0
0
2.0
0
Clock to Low-Z
Clock to High-Z
3.5
3.5
3.5
3.5
CHZ
OEV
OELZ
OEHZ
OE LOW to Output Valid
OE LOW to Output Low-Z
0
0
OE HIGH to Output High-Z
3.5
3.5
Setup Times
t
t
t
t
t
t
Address Setup Before CLK Rise
ADV/LD Setup Before CLK Rise
1.5
1.5
1.5
1.5
1.5
1.5
2.0
2.0
2.0
2.0
2.0
2.0
ns
ns
ns
ns
ns
ns
AS
ALS
WES
CENS
DS
WE, BW Setup Before CLK Rise
X
CEN Setup Before CLK Rise
Data Input Setup Before CLK Rise
Chip Enable Setup Before CLK Rise
CES
Hold Times
t
t
t
t
t
t
Address Hold After CLK Rise
ADV/LD Hold after CLK Rise
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
AH
ALH
WEH
CENH
DH
WE, BW Hold After CLK Rise
X
CEN Hold After CLK Rise
Data Input Hold After CLK Rise
Chip Enable Hold After CLK Rise
CEH
Notes:
13.This part has a voltage regulator internally; t
is the time that the power needs to be supplied above V minimum initially before a read or write operation
DD
POWER
can be initiated.
14.t
, t
,t
, and t
are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
CHZ CLZ OELZ
OEHZ
15.At any voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same data
OEHZ
OELZ
CHZ
CLZ
bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to
achieve tri-state prior to Low-Z under the same system conditions.
16.This parameter is sampled and not 100% tested.
17.Timing reference level is 1.5V when V
=3.3V and is 1.25V when V
=2.5V.
DDQ
DDQ
18.Test conditions shown in (a) of AC Test Loads, unless otherwise noted.
Document #: 38-05515 Rev. *E
Page 9 of 13
CY7C1353G
Switching Waveforms
Read/Write Waveforms
t
1
2
3
4
5
6
7
8
9
10
CYC
t
CLK
t
t
t
t
t
CENS
CES
CENH
CEH
CL
CH
CEN
CE
ADV/LD
WE
BW[A:B]
A1
A2
A4
A3
A5
A6
A7
ADDRESS
DQ
t
CDV
t
t
AS
AH
t
t
t
t
DOH
OEV
CLZ
CHZ
D(A1)
t
D(A2)
D(A2+1)
Q(A3)
Q(A4)
Q(A4+1)
D(A5)
Q(A6)
D(A7)
t
OEHZ
t
DS
DH
t
DOH
t
OELZ
OE
COMMAND
WRITE
D(A1)
WRITE
D(A2)
BURST
WRITE
READ
Q(A3)
READ
Q(A4)
BURST
READ
WRITE
D(A5)
READ
Q(A6)
WRITE
D(A7)
DESELECT
D(A2+1)
Q(A4+1)
DON’T CARE
UNDEFINED
Notes:
For this waveform ZZ is tied low.
19.
20.When CE is LOW, CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH, CE is HIGH or CE is LOW or CE is HIGH.
1
2
3
1
2
3
21.Order of the Burst sequence is determined by the status of the MODE (0= Linear, 1= Interleaved). Burst operations are optional.
Document #: 38-05515 Rev. *E
Page 10 of 13
CY7C1353G
Switching Waveforms
NOP, STALL and DESELECT Cycles
1
2
3
4
5
6
7
8
9
10
CLK
CEN
CE
ADV/LD
WE
BW[A:B]
ADDRESS
A1
A2
A3
A4
A5
t
CHZ
D(A1)
Q(A2)
Q(A3)
D(A4)
Q(A5)
DQ
t
DOH
COMMAND
WRITE
D(A1)
READ
Q(A2)
STALL
READ
Q(A3)
WRITE
D(A4)
STALL
NOP
READ
Q(A5)
DESELECT
CONTINUE
DESELECT
DON’T CARE
UNDEFINED
CLK
ZZ
t
t
ZZ
ZZREC
t
ZZI
I
SUPPLY
I
DDZZ
t
RZZI
ALL INPUTS
(except ZZ)
DESELECT or READ Only
Outputs (Q)
High-Z
DON’T CARE
Notes:
22.The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrates CEN being used to create a pause. A write is not performed during this cycle.
23.Device must be deselected when entering ZZ mode. See truth table for all possible signal conditions to deselect the device.
24.DQs are in high-Z when exiting ZZ sleep mode
Document #: 38-05515 Rev. *E
Page 11 of 13
CY7C1353G
Ordering Information
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or
Speed
(MHz)
Package
Diagram
Operating
Range
Ordering Code
Part and Package Type
133 CY7C1353G-133AXC
CY7C1353G-133AXI
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free
Commercial
lndustrial
100 CY7C1353G-100AXC
CY7C1353G-100AXI
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free
Commercial
lndustrial
Package Diagrams
100-Pin TQFP (14 x 20 x 1.4 mm) (51-85050)
16.00 0.20
14.00 0.10
1.40 0.05
100
81
80
1
0.30 0.08
0.65
TYP.
12° 1°
(8X)
SEE DETAIL
A
30
51
31
50
0.20 MAX.
1.60 MAX.
R 0.08 MIN.
0.20 MAX.
0° MIN.
SEATING PLANE
STAND-OFF
0.05 MIN.
0.15 MAX.
NOTE:
1. JEDEC STD REF MS-026
0.25
GAUGE PLANE
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE
R 0.08 MIN.
0.20 MAX.
BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH
3. DIMENSIONS IN MILLIMETERS
0°-7°
0.60 0.15
0.20 MIN.
51-85050-*B
1.00 REF.
DETAIL
A
ZBT is a trademark of Integrated Device Technology, Inc. NoBL and No Bus Latency are trademarks of Cypress Semiconductor.
All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05515 Rev. *E
Page 12 of 13
© Cypress Semiconductor Corporation, 2004-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for
the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended
to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY7C1353G
Document History Page
Document Title: CY7C1353G 4-Mbit (256K x 18) Flow-through SRAM with NoBL™ Architecture
Document Number: 38-05515
Orig. of
REV.
**
ECN NO. Issue Date
Change
Description of Change
224363
288431
See ECN
See ECN
RKF
New data sheet
Deleted 66 MHz
*A
VBL
Changed TQFP package in Ordering Information section to Pb-free TQFP
*B
333626
See ECN
SYT
Removed 117-MHz speed bin
Modified Address Expansion balls in the pinouts for 100 TQFP Packages
according to JEDEC standards and updated the Pin Definitions accordingly
Modified V
V
test conditions
OL, OH
Replaced ‘Snooze’ with ‘Sleep’
Replaced TBD’s for Θ and Θ to their respective values on the Thermal
JA
JC
Resistance table
Updated the Ordering Information by shading and unshading MPNs
according to availability
*C
418633
See ECN
RXU
Converted from Preliminary to Final
Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”
Modified test condition from V < V to V < V
IH
DD
IH
DD
Modified test condition from V
< V to V
< V
DDQ
DD
DDQ DD
Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the
Electrical Characteristics Table
Replaced Package Name column with Package Diagram in the Ordering
Information table
Replaced Package Diagram of 51-85050 from *A to *B
Updated the Ordering Information
*D
*E
480124
See ECN
See ECN
VKN
Added the Maximum Rating for Supply Voltage on V
Updated the Ordering Information table.
Relative to GND.
DDQ
1274724
VKN/AESA Corrected typo in the Ordering Information table
Document #: 38-05515 Rev. *E
Page 13 of 13
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