CY7C1381D, CY7C1381F
CY7C1383D, CY7C1383F
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
Features
Functional Description [1]
• Supports 133 MHz bus operations
• 512K × 36 and 1M × 18 common IO
The CY7C1381D/CY7C1383D/CY7C1381F/CY7C1383F is a
3.3V, 512K x 36 and 1M x 18 synchronous flow through
SRAMs,
designed
to
interface
with
high-speed
• 3.3V core power supply (V
)
DD
microprocessors with minimum glue logic. Maximum access
delay from clock rise is 6.5 ns (133 MHz version). A 2-bit
on-chip counter captures the first address in a burst and
increments the address automatically for the rest of the burst
access. All synchronous inputs are gated by registers
controlled by a positive edge triggered clock input (CLK). The
synchronous inputs include all addresses, all data inputs,
• 2.5V or 3.3V IO supply (V
• Fast clock-to-output time
)
DDQ
— 6.5 ns (133 MHz version)
• Provides high performance 2-1-1-1 access rate
®
®
• User selectable burst counter supporting Intel Pentium
address pipelining chip enable (CE ), depth-expansion chip
1
interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed write
enables (CE and CE
), burst control inputs (ADSC, ADSP,
2
3
and ADV), write enables (BW , and BWE), and global write
x
(GW). Asynchronous inputs include the output enable (OE)
and the ZZ pin.
• Asynchronous output enable
The
CY7C1381D/CY7C1383D/CY7C1381F/CY7C1383F
• CY7C1381D/CY7C1383D available in JEDEC-standard
allows interleaved or linear burst sequences, selected by the
MODE input pin. A HIGH selects an interleaved burst
sequence, while a LOW selects a linear burst sequence. Burst
accesses can be initiated with the processor address strobe
(ADSP) or the cache controller address strobe (ADSC) inputs.
Address advancement is controlled by the address
advancement (ADV) input.
Pb-free 100-pin TQFP, Pb-free and non Pb-free 165-ball
FBGA package. CY7C1381F/CY7C1383F available in
Pb-free and non Pb-free 119-ball BGA package
• IEEE 1149.1 JTAG-Compatible Boundary Scan
• ZZ sleep mode option
Addresses and chip enables are registered at rising edge of
clock when address strobe processor (ADSP) or address
strobe controller (ADSC) are active. Subsequent burst
addresses can be internally generated as controlled by the
advance pin (ADV).
The
CY7C1381D/CY7C1383D/CY7C1381F/CY7C1383F
operates from a +3.3V core power supply while all outputs
operate with a +2.5V or +3.3V supply. All inputs and outputs
are JEDEC-standard and JESD8-5-compatible.
Selection Guide
133 MHz
100 MHz
8.5
Unit
ns
Maximum Access Time
6.5
210
70
Maximum Operating Current
Maximum CMOS Standby Current
175
mA
mA
70
Notes:
1. For best practices or recommendations, please refer to the Cypress application note AN1064, SRAM System Design Guidelines on www.cypress.com.
2. CE CE are for TQFP and 165 FBGA packages only. 119 BGA is offered only in 1 chip enable.
3,
2
Cypress Semiconductor Corporation
Document #: 38-05544 Rev. *F
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised Feburary 07, 2007
CY7C1381D, CY7C1381F
CY7C1383D, CY7C1383F
Pin Configurations
100-pin TQFP Pinout (3 Chip Enable)
DQPC
1
DQPB
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQB
DQB
VSSQ
VDDQ
DQB
DQB
VSS
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
NC
NC
VDDQ
VSSQ
NC
A
NC
NC
VDDQ
VSSQ
NC
DQPA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
VSS
NC
1
2
3
4
5
6
7
8
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQC
2
DQC
VDDQ
VSSQ
DQC
3
4
5
6
DQC
7
NC
DQC
8
DQB
DQB
VSSQ
VDDQ
DQB
DQB
VSS/DNU
VDD
DQC
9
10
11
9
VSSQ
VDDQ
DQC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
12
DQC
13
VSS/DNU
14
VDD
15
NC
VDD
ZZ
CY7C1383D
(1M x 18)
CY7C1381D
(512K x 36)
NC
16
NC
VSS
VDD
ZZ
VSS
17
DQD
18
DQA
DQA
VDDQ
VSSQ
DQA
DQA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
DQPA
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQPB
NC
VSSQ
VDDQ
NC
NC
NC
DQA
DQA
VDDQ
VSSQ
DQA
DQA
NC
DQD
19
20
21
VDDQ
VSSQ
DQD
22
DQD
23
DQD
24
DQD
25
26
27
NC
VSSQ
VDDQ
DQD
DQD
29
VSSQ
VDDQ
NC
NC
NC
28
DQPD
30
Document #: 38-05544 Rev. *F
Page 3 of 29
CY7C1381D, CY7C1381F
CY7C1383D, CY7C1383F
Pin Configurations (continued)
119-Ball BGA
Pinout
CY7C1381F (512K x 36)
1
2
3
4
5
6
7
A
V
A
A
A
A
V
DDQ
ADSP
ADSC
DDQ
NC/288M
NC/144M
A
A
A
A
A
A
A
A
NC/576M
NC/1G
B
C
V
DD
D
E
F
DQ
DQ
DQP
DQ
V
NC
V
DQP
DQ
DQ
DQ
C
C
C
SS
SS
SS
SS
SS
SS
B
B
B
V
V
V
V
CE
C
B
1
V
DQ
DQ
V
DDQ
OE
ADV
GW
DDQ
C
B
G
H
J
DQ
DQ
DQ
DQ
DQ
DQ
BW
V
BW
V
C
C
C
C
B
B
B
C
B
DQ
DQ
SS
SS
B
V
V
NC
V
NC
V
V
DDQ
DDQ
DD
DD
DD
K
DQ
DQ
DQ
DQ
DQ
V
CLK
NC
V
DQ
DQ
DQ
DQ
DQ
D
D
D
SS
SS
A
A
A
DQ
DQ
L
M
N
BW
V
BW
A
D
D
D
A
A
A
D
V
V
V
V
DDQ
BWE
A1
DDQ
SS
SS
SS
DQ
V
V
DQ
D
SS
A
P
R
DQ
DQP
A
A0
V
DQP
A
DQ
D
D
SS
SS
A
NC
NC
MODE
V
NC
A
NC
DD
NC/72M
TMS
A
A
A
NC/36M
NC
ZZ
T
U
V
TDI
TCK
TDO
V
DDQ
DDQ
CY7C1383F (1M x 18)
2
A
1
3
A
A
A
4
5
A
A
A
6
7
V
A
V
DDQ
A
B
C
D
E
F
ADSP
ADSC
DDQ
NC/288M
A
NC/576M
A
A
NC/144M
A
V
NC/1G
NC
DD
DQ
NC
V
NC
CE
V
DQP
B
SS
SS
SS
SS
SS
SS
A
NC
DQ
V
V
V
V
NC
DQ
B
A
1
V
NC
DQ
V
OE
ADV
GW
DDQ
A
DDQ
NC
DQ
NC
NC
DQ
G
H
J
BW
V
B
A
B
DQ
NC
V
DQ
NC
B
SS
SS
A
V
V
NC
V
V
V
NC
DDQ
DD
DD
DD
DDQ
K
NC
DQ
V
CLK
NC
V
NC
DQ
A
B
SS
SS
L
M
N
P
DQ
NC
DQ
NC
DQ
NC
BW
B
A
A
V
V
V
V
V
NC
V
DDQ
BWE
A1
DDQ
B
SS
SS
SS
SS
DQ
NC
V
V
DQ
A
NC
B
SS
SS
NC
DQP
A0
NC
DQ
B
A
R
T
NC
A
A
MODE
A
V
NC
A
A
A
NC
ZZ
DD
NC/72M
NC/36M
TCK
U
V
TMS
TDI
TDO
NC
V
DDQ
DDQ
Document #: 38-05544 Rev. *F
Page 4 of 29
CY7C1381D, CY7C1381F
CY7C1383D, CY7C1383F
Pin Configurations (continued)
165-Ball FBGA Pinout(3 Chip Enable)
CY7C1381D (512K x 36)
1
2
A
3
CE1
4
BWC
5
BWB
6
CE
7
8
9
ADV
10
A
11
NC
NC/288M
NC/144M
DQPC
BWE
GW
VSS
VSS
ADSC
A
B
C
D
3
A
CE2
VDDQ
VDDQ
BWD
VSS
BWA
VSS
VSS
CLK
VSS
VSS
OE
VSS
VDD
ADSP
VDDQ
VDDQ
A
NC/576M
DQPB
DQB
NC
DQC
NC/1G
DQB
DQC
VDD
DQC
DQC
DQC
NC
DQC
DQC
DQC
NC
VDDQ
VDDQ
VDDQ
NC
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
NC
DQB
DQB
DQB
NC
DQB
DQB
DQB
ZZ
E
F
G
H
J
DQD
DQD
DQD
DQD
DQD
DQD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQA
DQA
DQA
DQA
DQA
DQA
K
L
DQD
DQPD
NC
DQD
NC
VDDQ
VDDQ
A
VDD
VSS
A
VSS
NC
VSS
A
VSS
NC
VDD
VSS
A
VDDQ
VDDQ
A
DQA
NC
A
DQA
DQPA
A
M
N
P
NC/72M
TDI
A1
TDO
A0
MODE NC/36M
A
A
TMS
TCK
A
A
A
A
R
CY7C1383D (1M x 18)
1
2
A
3
CE1
4
BWB
5
NC
6
CE
7
8
9
ADV
10
A
11
A
NC/288M
NC/144M
NC
BWE
GW
VSS
VSS
ADSC
A
B
C
D
3
A
CE2
NC
BWA
VSS
VSS
CLK
VSS
VSS
OE
VSS
VDD
ADSP
VDDQ
VDDQ
A
NC/576M
DQPA
DQA
NC
VDDQ
VDDQ
VSS
VDD
NC/1G
NC
NC
DQB
NC
NC
DQB
DQB
DQB
NC
VDDQ
VDDQ
VDDQ
NC
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
NC
NC
NC
DQA
DQA
DQA
ZZ
E
F
NC
NC
G
H
J
VSS
DQB
DQB
DQB
NC
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQA
DQA
DQA
NC
NC
NC
K
L
NC
NC
DQB
DQPB
NC
NC
NC
VDDQ
VDDQ
A
VDD
VSS
A
VSS
NC
VSS
A
VSS
NC
VDD
VSS
A
VDDQ
VDDQ
A
DQA
NC
A
NC
NC
A
M
N
P
NC/72M
TDI
A1
TDO
MODE NC/36M
A
A
TMS
A0
TCK
A
A
A
A
R
Document #: 38-05544 Rev. *F
Page 5 of 29
CY7C1381D, CY7C1381F
CY7C1383D, CY7C1383F
Pin Definitions
Name
IO
Description
Address inputs used to select one of the address locations. Sampled at the rising edge
A ,
Input-
Synchronous
A ,
A
0
1
of the CLK if ADSP or ADSC is active LOW, and CE , CE , and CE
are sampled active.
1
2
3
A
feed the 2-bit counter.
[1:0]
BW , BW
Input-
Synchronous
Byte write select inputs, active LOW. Qualified with BWE to conduct byte writes to the
SRAM. Sampled on the rising edge of CLK.
A
B
BW , BW
C
D
GW
Input-
Synchronous
Global write enable input, active LOW. When asserted LOW on the rising edge of CLK, a
global write is conducted (all bytes are written, regardless of the values on BW
and BWE).
[A:D]
CLK
Input-
Clock
Clock input. Used to capture all synchronous inputs to the device. Also used to increment
the burst counter when ADV is asserted LOW, during a burst operation.
CE
CE
CE
Input-
Synchronous
Chip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
1
2
3
[2]
with CE and CE
to select or deselect the device. ADSP is ignored if CE is HIGH. CE
2
3
1
1
is sampled only when a new external address is loaded.
Input-
Synchronous
Chip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction
with CE and CE
to select or deselect the device. CE is sampled only when a new
1
3
2
external address is loaded.
Input-
Synchronous
Chip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE and CE to select or deselect the device. CE is sampled only when a new external
1
2
3
address is loaded.
OE
Input-
Asynchronous
Output enable, asynchronous input, active LOW. Controls the direction of the IO pins.
When LOW, the IO pins behave as outputs. When deasserted HIGH, IO pins are tri-stated,
and act as input data pins. OE is masked during the first clock of a read cycle when emerging
from a deselected state.
ADV
Input-
Synchronous
Advance input signal. Sampled on the rising edge of CLK. When asserted, it automatically
increments the address in a burst cycle.
ADSP
Input-
Synchronous
Address strobe from processor, sampled on the rising edge of CLK, active LOW.
When asserted LOW, addresses presented to the device are captured in the address
registers. A
are also loaded into the burst counter. When ADSP and ADSC are both
[1:0]
asserted, only ADSP is recognized. ASDP is ignored when CE is deasserted HIGH.
1
ADSC
Input-
Synchronous
Address strobe from controller, sampled on the rising edge of CLK, active LOW.
When asserted LOW, addresses presented to the device are captured in the address
registers. A
asserted, only ADSP is recognized
are also loaded into the burst counter. When ADSP and ADSC are both
[1:0]
.
BWE
ZZ
Input-
Synchronous
Byte write enable input, active LOW. Sampled on the rising edge of CLK. This signal
must be asserted LOW to conduct a byte write.
Input-
Asynchronous
ZZ sleep input. This active HIGH input places the device in a non-time critical sleep
condition with data integrity preserved. For normal operation, this pin has to be LOW or left
floating. ZZ pin has an internal pull down.
IO-
Bidirectional data IO lines. As inputs, they feed into an on-chip data register that is
triggered by the rising edge of CLK. As outputs, they deliver the data contained in the
DQ
s
Synchronous
memory location specified by the addresses presented during the previous
clock rise of the
read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the
pins behave as outputs. When HIGH, DQ and DQP are placed in a tri-state condition.The
s
X
outputs are automatically tri-stated during the data portion of a write sequence, during the
first clock when emerging from a deselected state, and when the device is deselected,
regardless of the state of OE.
IO-
Bidirectional data parity IO lines. Functionally, these signals are identical to DQ . During
DQP
s
X
Synchronous
write sequences, DQP is controlled by BW correspondingly.
X
X
Document #: 38-05544 Rev. *F
Page 6 of 29
CY7C1381D, CY7C1381F
CY7C1383D, CY7C1383F
Pin Definitions (continued)
Name
MODE
IO
Description
Selects burst order. When tied to GND selects linear burst sequence. When tied to V
Input-Static
DD
or left floating selects interleaved burst sequence. This is a strap pin and must remain static
during device operation. Mode pin has an internal pull up.
V
V
V
V
Power Supply Power supply inputs to the core of the device.
DD
IO Power Supply Power supply for the IO circuitry.
DDQ
SS
Ground
Ground for the core of the device.
IO Ground
Ground for the IO circuitry.
SSQ
TDO
JTAG serial output Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the
Synchronous
JTAG feature is not being utilized, this pin can be left unconnected. This pin is not available
on TQFP packages.
TDI
JTAG serial input Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature
Synchronous
is not being utilized, this pin can be left floating or connected to V through a pull up
DD
resistor. This pin is not available on TQFP packages.
TMS
JTAG serial input Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature
Synchronous
is not being utilized, this pin can be disconnected or connected to V . This pin is not
DD
available on TQFP packages.
TCK
NC
JTAG-
Clock
Clock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin must
be connected to V . This pin is not available on TQFP packages.
SS
–
No connects. Not internally connected to the die. 36M, 72M, 144M, 288M, 576M, and 1G
are address expansion pins and are not internally connected to the die.
V
/DNU
Ground/DNU
This pin can be connected to ground or can be left floating.
SS
selection and output tri-state control. ADSP is ignored if CE
is HIGH.
Functional Overview
1
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. Maximum access delay from
Single Read Accesses
the clock rise (t
) is 6.5 ns (133 MHz device).
CDV
A single read access is initiated when the following conditions
The
CY7C1381D/CY7C1383D/CY7C1381F/CY7C1383F
are satisfied at clock rise: (1) CE , CE , and CE
are all
1
2
3
supports secondary cache in systems utilizing a linear or
interleaved burst sequence. The interleaved burst order
supports Pentium and i486™ processors. The linear burst
asserted active, and (2) ADSP or ADSC is asserted LOW (if
the access is initiated by ADSC, the write inputs must be
deasserted during this first cycle). The address presented to
the address inputs is latched into the address register and the
burst counter and/or control logic, and later presented to the
memory core. If the OE input is asserted LOW, the requested
data will be available at the data outputs with a maximum to
®
sequence is suited for processors that utilize a linear burst
sequence. The burst order is user selectable, and is
determined by sampling the MODE input. Accesses can be
initiated with the processor address strobe (ADSP) or the
controller address strobe (ADSC). Address advancement
through the burst sequence is controlled by the ADV input. A
two-bit on-chip wraparound burst counter captures the first
address in a burst sequence and automatically increments the
address for the rest of the burst access.
t
after clock rise. ADSP is ignored if CE is HIGH.
CDV
1
Single Write Accesses Initiated by ADSP
This access is initiated when the following conditions are
satisfied at clock rise: (1) CE , CE , CE
are all asserted
1
2
3
active, and (2) ADSP is asserted LOW. The addresses
presented are loaded into the address register and the burst
Byte write operations are qualified with the byte write enable
(BW ) and byte write select (BW ) inputs. A global write
E
X
inputs (GW, BW , and BW ) are ignored during this first clock
E
X
enable (GW) overrides all byte write inputs and writes data to
all four bytes. All writes are simplified with on-chip
synchronous self-timed write circuitry.
indicate a write) on the next clock rise, the appropriate data will
be latched and written into the device. Byte writes are allowed.
All IOs are tri-stated during a byte write. As this is a common
IO device, the asynchronous OE input signal must be
Three synchronous chip selects (CE , CE , CE
3
) and an
1
2
asynchronous output enable (OE) provide for easy bank
Document #: 38-05544 Rev. *F
Page 7 of 29
CY7C1381D, CY7C1381F
CY7C1383D, CY7C1383F
deasserted and the IOs must be tri-stated prior to the presen-
tation of data to DQs. As a safety precaution, the data lines are
tri-stated once a write cycle is detected, regardless of the state
of OE.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation sleep mode. Two
clock cycles are required to enter into or exit from this sleep
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the sleep mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the sleep mode. CE , CE , CE
remain inactive for the duration of t
returns LOW.
Single Write Accesses Initiated by ADSC
This write access is initiated when the following conditions are
satisfied at clock rise: (1) CE , CE , and CE
are all
1
2
3
asserted active, (2) ADSC is asserted LOW, (3) ADSP is
deasserted HIGH, and (4) the write input signals (GW, BWE,
, ADSP, and ADSC must
1
2
3
after the ZZ input
ZZREC
and BW ) indicate a write access. ADSC is ignored if ADSP is
X
active LOW.
Interleaved Burst Address Table
(MODE = Floating or VDD
The addresses presented are loaded into the address register
and the burst counter, the control logic, or both, and delivered
)
to the memory core The information presented to DQ
be written into the specified address location. Byte writes are
allowed. All IOs are tri-stated when a write is detected, even a
will
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
[A:D]
byte write. Since this is
asynchronous OE input signal must be deasserted and the IOs
must be tri-stated prior to the presentation of data to DQ . As
a safety precaution, the data lines are tri-stated once a write
cycle is detected, regardless of the state of OE.
a
common IO device, the
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
s
Linear Burst Address Table (MODE = GND)
Burst Sequences
First
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
The
provides an on-chip two-bit wraparound burst counter inside
the SRAM. The burst counter is fed by A , and can follow
either a linear or interleaved burst order. The burst order is
determined by the state of the MODE input. A LOW on MODE
will select a linear burst sequence. A HIGH on MODE will
select an interleaved burst order. Leaving MODE unconnected
will cause the device to default to a interleaved burst
sequence.
CY7C1381D/CY7C1383D/CY7C1381F/CY7C1383F
Address
A1: A0
[1:0]
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
Description
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
Test Conditions
ZZ > V – 0.2V
Min
Max
Unit
mA
ns
I
t
t
t
t
80
DDZZ
ZZS
DD
ZZ > V – 0.2V
2t
DD
CYC
CYC
ZZ < 0.2V
2t
ns
ZZREC
ZZI
CYC
ZZ active to sleep current
ZZ inactive to exit sleep current
This parameter is sampled
This parameter is sampled
2t
ns
0
ns
RZZI
Document #: 38-05544 Rev. *F
Page 8 of 29
CY7C1381D, CY7C1381F
CY7C1383D, CY7C1383F
ADDRESS
Used
Cycle Description
CE CE CE ZZ
ADSP
ADSC ADV WRITE OE CLK
DQ
1
2
3
Deselected Cycle, Power
Down
None
None
None
None
None
H
L
L
L
X
X
X
X
H
X
X
L
L
L
L
L
X
L
X
X
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L-H Tri-State
L-H Tri-State
L-H Tri-State
L-H Tri-State
L-H Tri-State
Deselected Cycle, Power
Down
L
L
L
Deselected Cycle, Power
Down
X
L
Deselected Cycle, Power
Down
H
H
Deselected Cycle, Power
Down
X
L
Sleep Mode, Power Down
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
None
External
External
External
External
External
Next
X
L
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
L
X
X
X
L
X
X
X
X
X
X
L
X
X
X
L
X
L
X
Tri-State
Q
L-H
L
L
L
H
X
L
L-H Tri-State
L
L
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
L-H
L-H
D
Q
L
L
L
H
H
H
H
H
H
L
L
L
L
H
L
L-H Tri-State
L-H
L-H Tri-State
L-H
L-H Tri-State
X
X
H
H
X
H
X
X
H
H
X
H
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
Q
Next
L
H
L
Next
L
Q
Next
L
H
X
X
L
Next
L
L-H
L-H
L-H
D
D
Q
Next
L
L
Current
Current
Current
Current
Current
Current
H
H
H
H
H
H
H
H
H
H
L
H
L
L-H Tri-State
L-H
L-H Tri-State
Q
H
X
X
L-H
L-H
D
D
L
Notes:
4. X=Don't Care, H = Logic HIGH, L = Logic LOW.
5. WRITE = L when any one or more byte write enable signals, and BWE = L or GW = L. WRITE = H when all byte write enable signals, BWE, GW = H.
6. The DQ pins are controlled by the current cycle and the signal. is asynchronous and is not sampled with the clock.
OE
OE
must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state.
7. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW . Writes may occur only on subsequent clocks after
X
the
or with the assertion of
. As a result,
is a don't
OE
ADSC
care for the remainder of the write cycle.
is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when
OE
ADSP
8.
is
OE
OE
inactive or when the device is deselected, and all data bits behave as output when
is active (LOW).
OE
Document #: 38-05544 Rev. *F
Page 9 of 29
CY7C1381D, CY7C1381F
CY7C1383D, CY7C1383F
Truth Table for Read/Write [4, 9]
Function (CY7C1381D/CY7C1381F)
GW
H
BWE
BW
X
BW
X
BW
X
BW
A
D
C
B
Read
Read
H
L
L
L
L
L
L
L
L
X
H
L
H
H
H
H
H
H
L
H
H
L
Write Byte A (DQ , DQP )
H
H
A
A
Write Byte B(DQ , DQP )
H
H
H
L
B
B
Write Bytes A, B (DQ , DQ , DQP , DQP )
H
H
L
A
B
A
B
Write Byte C (DQ , DQP )
H
H
H
H
L
H
L
C
C
Write Bytes C, A (DQ , DQ DQP , DQP )
H
H
L
C
A,
C
A
Write Bytes C, B (DQ , DQ DQP , DQP )
H
H
L
H
L
C
B,
C
B
Write Bytes C, B, A (DQ , DQ , DQ DQP ,
H
H
L
L
C
B
A,
C
DQP , DQP )
B
A
Write Byte D (DQ , DQP )
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
H
H
L
H
L
D
D
Write Bytes D, A (DQ , DQ DQP , DQP )
D
A,
D
A
Write Bytes D, B (DQ , DQ DQP , DQP )
H
L
D
A,
D
A
Write Bytes D, B, A (DQ , DQ , DQ DQP ,
L
D
B
A,
D
DQP , DQP )
B
A
Write Bytes D, B (DQ , DQ DQP , DQP )
H
H
L
L
L
L
L
L
H
H
H
L
D
B,
D
B
Write Bytes D, B, A (DQ , DQ , DQ DQP ,
D
C
A,
D
DQP , DQP )
C
A
Truth Table for Read/Write [4, 9]
Function (CY7C1383D/CY7C1383F)
Write Bytes D, C, A (DQ , DQ , DQ DQP ,
GW
BWE
BW
BW
A
B
H
L
L
L
D
B
A,
D
DQP , DQP )
B
A
Write All Bytes
Write All Bytes
Read
H
L
L
X
H
L
L
X
X
H
H
L
L
X
X
H
L
H
H
H
H
H
L
Read
Write Byte A – (DQ and DQP )
L
A
A
Write Byte B – (DQ and DQP )
L
H
L
B
B
Write All Bytes
Write All Bytes
L
L
X
X
X
Note:
9. Table only lists a partial listing of the byte write combinations. Any combination of BW is valid. Appropriate write will be done based on which byte write is active.
X
Document #: 38-05544 Rev. *F
Page 10 of 29
CY7C1381D, CY7C1381F
CY7C1383D, CY7C1383F
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. TDI
is internally pulled up and can be unconnected if the TAP is
unused in an application. TDI is connected to the most
significant bit (MSB) of any register. (See TAP Controller Block
Diagram.)
IEEE 1149.1 Serial Boundary Scan (JTAG)
The
CY7C1381D/CY7C1383D/CY7C1381F/CY7C1383F
incorporates a serial boundary scan test access port
(TAP).This part is fully compliant with 1149.1. The TAP
operates using JEDEC-standard 3.3V or 2.5V IO logic levels.
The
CY7C1381D/CY7C1383D/CY7C1381F/CY7C1383F
Test Data-Out (TDO)
contains a TAP controller, instruction register, boundary scan
register, bypass register, and ID register.
The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current
state of the TAP state machine. The output changes on the
falling edge of TCK. TDO is connected to the least significant
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(V ) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be unconnected. They may
SS
TAP Controller Block Diagram
alternately be connected to V
through a pull up resistor.
DD
TDO may be left unconnected. Upon power up, the device will
come up in a reset state, which will not interfere with the
operation of the device.
0
Bypass Register
2
1
0
0
0
Selection
Circuitry
TAP Controller State Diagram
Instruction Register
31 30 29
Identification Register
S
election
TDI
TDO
Circuitr
y
.
.
.
2
1
TEST-LOGIC
1
RESET
0
1
1
1
RUN-TEST/
IDLE
SELECT
DR-SCAN
SELECT
IR-SCAN
x
.
.
.
.
.
2
1
0
0
0
Boundary Scan Register
1
1
CAPTURE-DR
CAPTURE-IR
0
0
TCK
SHIFT-DR
0
SHIFT-IR
0
TMS
TAP CONTROLLER
1
1
1
1
EXIT1-DR
EXIT1-IR
0
0
PAUSE-DR
1
0
PAUSE-IR
1
0
Performing a TAP Reset
0
0
EXIT2-DR
1
EXIT2-IR
1
A Reset is performed by forcing TMS HIGH (V ) for five rising
DD
edges of TCK. This Reset does not affect the operation of the
SRAM and may be performed while the SRAM is operating. At
power up, the TAP is reset internally to ensure that TDO
comes up in a High-Z state.
UPDATE-DR
UPDATE-IR
1
0
1
0
TAP Registers
Registers are connected between the TDI and TDO balls and
allow data to be scanned in and out of the SRAM test circuitry.
Only one register can be selected at a time through the
instruction registers. Data is serially loaded into the TDI ball on
the rising edge of TCK. Data is output on the TDO ball on the
falling edge of TCK.
The 0 or 1 next to each state represents the value of TMS at
the rising edge of TCK.
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
TDI and TDO balls as shown in the TAP Controller Block
Diagram. Upon power up, the instruction register is loaded
with the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as
described in the previous section.
Test MODE SELECT (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. This pin may be left
unconnected if the TAP is not used. The ball is pulled up inter-
nally, resulting in a logic HIGH level.
When the TAP controller is in the Capture-IR state, the two
least significant bits are loaded with a binary ‘01’ pattern to
allow for fault isolation of the board level serial test path.
Test Data-In (TDI)
The TDI ball is used to serially input information into the
registers and can be connected to the input of any of the
Document #: 38-05544 Rev. *F
Page 11 of 29
CY7C1381D, CY7C1381F
CY7C1383D, CY7C1383F
Bypass Register
The IDCODE instruction is loaded into the instruction register
upon power up or whenever the TAP controller is given a test
logic reset state.
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO balls when the TAP
controller is in a Shift-DR state. The SAMPLE Z command
places all SRAM outputs into a High-Z state.
(V ) when the BYPASS instruction is executed.
SS
Boundary Scan Register
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
The boundary scan register is loaded with the contents of the
RAM input and output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and
TDO balls when the controller is moved to the Shift-DR state.
The EXTEST, SAMPLE/PRELOAD, and SAMPLE
Z
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is
possible that during the Capture-DR state, an input or output
will undergo a transition. The TAP may then try to capture a
signal while in transition (metastable state). This will not harm
the device, but there is no guarantee as to the value that will
be captured. Repeatable results may not be possible.
instructions can be used to capture the contents of the input
and output ring.
The boundary scan order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI, and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in Identification Register
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture setup plus
hold times (t and t ). The SRAM clock input might not be
CS
CH
captured correctly if there is no way in a design to stop (or
slow) the clock during a SAMPLE/PRELOAD instruction. If this
is an issue, it is still possible to capture all other signals and
simply ignore the value of the CK and CK captured in the
boundary scan register.
TAP Instruction Set
Overview
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO pins.
Eight different instructions are possible with the three bit
instruction register. All combinations are listed in Identification
Codes on page 15. Three of these instructions are listed as
RESERVED and must not be used. The other five instructions
are described in detail below.
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells
prior to the selection of another boundary scan test operation.
Instructions are loaded into the TAP controller during the
Shift-IR state, when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO balls.
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.
The shifting of data for the SAMPLE and PRELOAD phases
can occur concurrently when required; that is, while data
captured is shifted out, the preloaded data is shifted in.
BYPASS
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO balls. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
EXTEST
The EXTEST instruction enables the preloaded data to be
driven out through the system output pins. This instruction also
selects the boundary scan register to be connected for serial
access between the TDI and TDO in the Shift-DR controller
state.
EXTEST Output Bus Tri-State
IEEE standard 1149.1 mandates that the TAP controller be
able to put the output bus into a tri-state mode.
IDCODE
The IDCODE instruction causes a vendor-specific 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state.
The boundary scan register has a special bit located at bit #85
(for 119-BGA package) or bit #89 (for 165-fBGA package).
When this scan cell, called the “extest output bus tri-state,” is
latched into the preload register during the Update-DR state in
the TAP controller, it will directly control the state of the output
Document #: 38-05544 Rev. *F
Page 12 of 29
CY7C1381D, CY7C1381F
CY7C1383D, CY7C1383F
(Q-bus) pins, when the EXTEST is entered as the current
instruction. When HIGH, it will enable the output buffers to
drive the output bus. When LOW, this bit will place the output
bus into a High-Z condition.
directly control the output Q-bus pins. Note that this bit is
preset HIGH to enable the output when the device is powered
up, and also when the TAP controller is in the Test-Logic-Reset
state.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that
cell, during the Shift-DR state. During Update-DR, the value
loaded into that shift-register cell will latch into the preload
register. When the EXTEST instruction is entered, this bit will
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
TAP Timing
1
2
3
4
5
6
Test Clock
(TCK)
t
t
t
TH
CYC
TL
t
t
t
t
TMSS
TDIS
TMSH
Test Mode Select
(TMS)
TDIH
Test Data-In
(TDI)
t
TDOV
t
TDOX
Test Data-Out
(TDO)
DON’T CARE
UNDEFINED
TAP AC Switching Characteristics
Over the Operating Range
Parameter
Clock
Description
Min
Max
Unit
t
t
t
t
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH time
TCK Clock LOW time
50
ns
MHz
ns
TCYC
TF
20
20
20
TH
ns
TL
Output Times
t
t
TCK Clock LOW to TDO Valid
TCK Clock LOW to TDO Invalid
10
ns
ns
TDOV
TDOX
0
Setup Times
t
t
t
TMS Setup to TCK Clock Rise
TDI Setup to TCK Clock Rise
Capture Setup to TCK Rise
5
5
5
ns
ns
ns
TMSS
TDIS
CS
Hold Times
t
t
t
TMS Hold after TCK Clock Rise
TDI Hold after Clock Rise
5
5
5
ns
ns
ns
TMSH
TDIH
CH
Capture Hold after Clock Rise
Notes:
10. t and t refer to the setup and hold time requirements of latching data from the boundary scan register.
CS
CH
11. Test conditions are specified using the load in TAP AC test conditions. t /t = 1 ns.
R
F
Document #: 38-05544 Rev. *F
Page 13 of 29
CY7C1381D, CY7C1381F
CY7C1383D, CY7C1383F
3.3V TAP AC Test Conditions
2.5V TAP AC Test Conditions
Input pulse levels.................................................V to 3.3V
Input pulse levels.................................................V to 2.5V
SS
SS
Input rise and fall times................................................... 1 ns
Input timing reference levels...........................................1.5V
Output reference levels...................................................1.5V
Test load termination supply voltage...............................1.5V
Input rise and fall time .....................................................1 ns
Input timing reference levels ........................................ 1.25V
Output reference levels ................................................ 1.25V
Test load termination supply voltage ............................ 1.25V
3.3V TAP AC Output Load Equivalent
2.5V TAP AC Output Load Equivalent
1.5V
1.25V
50Ω
50Ω
TDO
TDO
ZO= 50 Ω
20pF
ZO= 50 Ω
20pF
TAP DC Electrical Characteristics And Operating Conditions
(0°C < TA < +70°C; V = 3.3V ±0.165V unless otherwise noted)
DD
Parameter
Description
Conditions
= 3.3V
Min
2.4
2.0
2.9
2.1
Max
Unit
V
V
V
V
V
V
V
Output HIGH Voltage
Output HIGH Voltage
Output LOW Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
I
I
I
= –4.0 mA
= –1.0 mA
= –100 µA
V
V
V
V
V
V
V
V
V
V
V
V
OH1
OH
OH
OH
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
= 2.5V
= 3.3V
= 2.5V
= 3.3V
= 2.5V
= 3.3V
= 2.5V
= 3.3V
= 2.5V
= 3.3V
= 2.5V
V
V
OH2
OL1
OL2
IH
V
I
I
I
= 8.0 mA
= 8.0 mA
= 100 µA
0.4
0.4
0.2
0.2
V
OL
OL
OL
V
V
V
2.0
1.7
V
V
+ 0.3
V
DD
DD
+ 0.3
V
–0.3
–0.3
–5
0.8
V
IL
0.7
5
V
I
GND < V < V
DDQ
µA
X
IN
Note:
12. All voltages referenced to V (GND).
SS
Document #: 38-05544 Rev. *F
Page 14 of 29
CY7C1381D, CY7C1381F
CY7C1383D, CY7C1383F
Identification Register Definitions
CY7C1381D/CY7C1381F CY7C1383D/CY7C1383F
Instruction Field
(512K × 36)
(1M × 18)
Description
Describes the version number.
Reserved for internal use.
Revision Number (31:29)
000
000
Device Depth (28:24)
01011
01011
Device Width (23:18) 119-BGA
Device Width (23:18) 165-FBGA
101001
101001
Defines the memory type and
architecture.
000001
000001
Defines the memory type and
architecture.
Cypress Device ID (17:12)
100101
010101
Defines the width and density.
Cypress JEDEC ID Code (11:1)
00000110100
00000110100
Allows unique identification of SRAM
vendor.
ID Register Presence Indicator (0)
1
1
Indicates the presence of an ID
register.
Scan Register Sizes
Register Name
Bit Size (×36)
Bit Size (×18)
Instruction Bypass
3
3
Bypass
ID
1
1
32
85
89
32
85
89
Boundary Scan Order (119-ball BGA package)
Boundary Scan Order (165-ball fBGA package)
Identification Codes
Instruction
EXTEST
Code
Description
000
Captures Input/Output ring contents. Places the boundary scan register between TDI and
TDO. Forces all SRAM outputs to High-Z state.
IDCODE
001
010
Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operations.
SAMPLE Z
Captures Input/Output ring contents. Places the boundary scan register between TDI and
TDO. Forces all SRAM output drivers to a High-Z state.
RESERVED
011
100
Do Not Use. This instruction is reserved for future use.
SAMPLE/PRELOAD
Captures Input/Output ring contents. Places the boundary scan register between TDI and
TDO. Does not affect SRAM operation.
RESERVED
RESERVED
BYPASS
101
110
111
Do Not Use. This instruction is reserved for future use.
Do Not Use. This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
Note:
13. Bit #24 is “1” in the register definitions for both 2.5V and 3.3V versions of this device.
Document #: 38-05544 Rev. *F
Page 15 of 29
CY7C1381D, CY7C1381F
CY7C1383D, CY7C1383F
Bit #
1
Ball ID
Bit #
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Ball ID
F6
Bit #
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
Ball ID
G4
A4
G3
C3
B2
B3
A3
C2
A2
B1
C1
D2
E1
F2
Bit #
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
Ball ID
L1
H4
T4
T5
T6
R5
L5
2
E7
D7
H7
G6
E6
D6
C7
B7
C6
A6
C5
B5
G5
B6
D4
B4
F4
M2
N1
3
4
P1
5
K1
6
L2
7
R6
U6
R7
T7
P6
N7
M6
L7
N2
P2
8
9
R3
10
11
12
13
14
15
16
17
18
19
20
21
22
T1
R1
T2
L3
R2
K6
P7
N6
L6
G1
H2
D1
E2
G2
H1
J3
T3
L4
N4
P4
K7
J5
M4
A5
K4
E4
Internal
H6
G7
2K
Notes:
14. Balls which are NC (No Connect) are pre-set LOW.
15. Bit# 85 is pre-set HIGH.
Document #: 38-05544 Rev. *F
Page 16 of 29
CY7C1381D, CY7C1381F
CY7C1383D, CY7C1383F
Bit #
1
Ball ID
N6
Bit #
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Ball ID
D10
C11
A11
B11
A10
B10
A9
Bit #
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
Ball ID
G1
D2
E2
2
N7
3
N10
P11
P8
4
F2
5
G2
H1
H3
J1
6
R8
7
R9
8
P9
B9
9
P10
R10
R11
H11
N11
M11
L11
K11
J11
M10
L10
K10
J10
H9
C10
A8
K1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
L1
B8
M1
J2
A7
B7
K2
B6
L2
A6
M2
N1
N2
P1
B5
A5
A4
B4
R1
R2
P3
B3
A3
A2
R3
P2
H10
G11
F11
E11
D11
G10
F10
E10
B2
C2
R4
P4
B1
A1
N5
P6
C1
D1
R6
Internal
E1
F1
Note:
16. Bit# 89 is pre-set HIGH.
Document #: 38-05544 Rev. *F
Page 17 of 29
CY7C1381D, CY7C1381F
CY7C1383D, CY7C1383F
DC Input Voltage ................................... –0.5V to V + 0.5V
Maximum Ratings
DD
Current into Outputs (LOW) ........................................ 20 mA
Exceeding the maximum ratings may impair the useful life of
the device. For user guidelines, not tested.
Static Discharge Voltage........................................... > 2001V
(per MIL-STD-883, Method 3015)
Storage Temperature .................................–65°C to +150°C
Latch-up Current .................................................... > 200 mA
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Operating Range
Supply Voltage on V Relative to GND ....... –0.3V to +4.6V
DD
Ambient
Supply Voltage on V
Relative to GND ...... –0.3V to +V
Range
Temperature
V
V
DDQ
DDQ
DD
DD
DC Voltage Applied to Outputs
in Tri-State........................................... –0.5V to V
Commercial 0°C to +70°C 3.3V –5%/+10% 2.5V – 5%
+ 0.5V
to V
DDQ
DD
Industrial
–40°C to +85°C
Electrical Characteristics
Over the Operating Range
Parameter
Description
Test Conditions
Min
Max
Unit
V
Power Supply Voltage
IO Supply Voltage
3.135
3.135
2.375
2.4
3.6
V
V
DD
V
V
V
V
V
I
for 3.3V IO
for 2.5V IO
for 3.3V IO, I = –4.0 mA
V
DD
DDQ
2.625
V
Output HIGH Voltage
Output LOW Voltage
V
OH
OL
IH
OH
for 2.5V IO, I = –1.0 mA
2.0
V
OH
for 3.3V IO, I = 8.0 mA
0.4
0.4
V
OL
for 2.5V IO, I = 1.0 mA
V
OL
Input HIGH Voltage
Input LOW Voltage
for 3.3V IO
for 2.5V IO
for 3.3V IO
for 2.5V IO
2.0
1.7
V
V
+ 0.3V
V
DD
+ 0.3V
V
DD
–0.3
–0.3
–5
0.8
V
IL
0.7
5
V
Input Leakage Current GND ≤ V ≤ V
except ZZ and MODE
µA
X
I
DDQ
Input Current of MODE Input = V
–30
–5
µA
µA
µA
µA
µA
mA
mA
mA
SS
Input = V
5
DD
Input Current of ZZ
Input = V
Input = V
SS
DD
30
5
I
I
Output Leakage Current GND ≤ V ≤ V
Output Disabled
–5
OZ
I
DD,
V
Operating Supply
V
f = f
= Max, I
= 0 mA,
7.5-ns cycle, 133 MHz
10-ns cycle, 100 MHz
7.5-ns cycle, 133 MHz
10-ns cycle, 100 MHz
210
175
140
120
DD
DD
DD
OUT
CYC
Current
= 1/t
MAX
I
I
I
I
Automatic CE
Power Down
Current—TTL Inputs
Max V , Device Deselected,
DD
SB1
V
≥ V or V ≤ V , f = f
IN IH IN IL MAX,
inputs switching
Automatic CE
Power Down
Current—CMOS Inputs f = 0, inputs static
Max V , Device Deselected,
All speeds
70
mA
SB2
SB3
SB4
DD
V
≥ V – 0.3V or V ≤ 0.3V,
IN
DD IN
Automatic CE
Power Down
Current—CMOS Inputs f = f
Max V , Device Deselected,
7.5-ns cycle, 133 MHz
10-ns cycle, 100 MHz
130
110
mA
mA
DD
V
≥ V
– 0.3V or V ≤ 0.3V,
IN
DDQ IN
, inputs switching
MAX
Automatic CE
Power Down
Current—TTL Inputs
Max V , Device Deselected,
All Speeds
80
mA
DD
V
≥ V – 0.3V or V ≤ 0.3V,
IN DD IN
f = 0, inputs static
Notes:
17. Overshoot: V (AC) < V +1.5V (pulse width less than t
/2), undershoot: V (AC) > –2V (pulse width less than t /2).
CYC
IH
DD
CYC
IL
18. T
: Assumes a linear ramp from 0v to V (min) within 200 ms. During this time V < V and V
< V
.
power up
DD
IH
DD
DDQ
DD
Document #: 38-05544 Rev. *F
Page 18 of 29
CY7C1381D, CY7C1381F
CY7C1383D, CY7C1383F
Capacitance [19]
100 TQFP
Package
119 BGA
Package
165 FBGA
Package
Parameter
Description
Test Conditions
T = 25°C, f = 1 MHz,
Unit
pF
C
C
C
Input Capacitance
5
5
5
8
8
8
9
9
9
IN
A
V
V
= 3.3V.
DD
Clock Input Capacitance
Input/Output Capacitance
pF
CLK
IO
= 2.5V
DDQ
pF
Thermal Resistance [19]
100 TQFP
Package
119 BGA
Package
165 FBGA
Package
Parameter
Description
Test Conditions
Unit
ΘJA
Thermal Resistance
(Junction to Ambient)
Test conditions follow standard
test methods and procedures
for measuring thermal
impedance, in accordance with
EIA/JESD51.
28.66
23.8
20.7
°C/W
ΘJC
Thermal Resistance
(Junction to Case)
4.08
6.2
4.0
°C/W
AC Test Loads and Waveforms
3.3V IO Test Load
R = 317Ω
3.3V
OUTPUT
ALL INPUT PULSES
90%
VDDQ
GND
OUTPUT
90%
10%
Z = 50Ω
0
R = 50Ω
10%
L
5 pF
R = 351Ω
≤ 1 ns
≤ 1 ns
INCLUDING
JIG AND
SCOPE
V = 1.5V
T
(a)
(b)
(c)
2.5V IO Test Load
R = 1667Ω
2.5V
OUTPUT
R = 50Ω
OUTPUT
ALL INPUT PULSES
90%
VDDQ
GND
90%
10%
Z = 50Ω
0
10%
L
5 pF
R = 1538Ω
≤ 1 ns
≤ 1 ns
INCLUDING
JIG AND
SCOPE
V = 1.25V
T
(a)
(b)
(c)
Note:
19. Tested initially and after any design or process change that may affect these parameters.
Document #: 38-05544 Rev. *F
Page 19 of 29
CY7C1381D, CY7C1381F
CY7C1383D, CY7C1383F
Switching Characteristics
Over the Operating Range
133 MHz
100 MHz
Parameter
Description
(Typical) to the first Access
DD
Min
Max
Min
Max
Unit
t
V
1
1
ms
POWER
Clock
t
t
t
Clock Cycle Time
Clock HIGH
7.5
2.1
2.1
10
2.5
2.5
ns
ns
ns
CYC
CH
Clock LOW
CL
Output Times
t
t
t
t
t
t
t
Data Output Valid After CLK Rise
Data Output Hold After CLK Rise
6.5
8.5
ns
ns
ns
ns
ns
ns
ns
CDV
DOH
CLZ
2.0
2.0
0
2.0
2.0
0
Clock to Low-Z
Clock to High-Z
4.0
3.2
5.0
3.8
CHZ
OEV
OELZ
OEHZ
OE LOW to Output Valid
OE LOW to Output Low-Z
OE HIGH to Output High-Z
0
0
4.0
5.0
Setup Times
t
t
t
t
t
t
Address Setup Before CLK Rise
ADSP, ADSC Setup Before CLK Rise
ADV Setup Before CLK Rise
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
ns
ns
ns
ns
ns
ns
AS
ADS
ADVS
WES
DS
GW, BWE, BW
Setup Before CLK Rise
[A:D]
Data Input Setup Before CLK Rise
Chip Enable Setup
CES
Hold Times
t
t
t
t
t
t
Address Hold After CLK Rise
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
AH
ADSP, ADSC Hold After CLK Rise
ADH
WEH
ADVH
DH
GW, BWE, BW
Hold After CLK Rise
[A:D]
ADV Hold After CLK Rise
Data Input Hold After CLK Rise
Chip Enable Hold After CLK Rise
CEH
Notes:
20. Timing reference level is 1.5V when V
= 3.3V and is 1.25V when V
= 2.5V.
DDQ
DDQ
21. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
22. This part has a voltage regulator internally; t
is the time that the power needs to be supplied above V (minimum) initially, before a read or write operation
POWER
DD
can be initiated.
23. t
, t
,t
, and t
are specified with AC test conditions shown in part (b) of AC Test Loads and Waveforms on page 19. Transition is measured ± 200
CHZ CLZ OELZ
OEHZ
mV from steady-state voltage.
24. At any given voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same
OEHZ
OELZ
CHZ
CLZ
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to
achieve High-Z prior to Low-Z under the same system condition.
25. This parameter is sampled and not 100% tested.
Document #: 38-05544 Rev. *F
Page 20 of 29
CY7C1381D, CY7C1381F
CY7C1383D, CY7C1383F
Timing Diagrams
Read Cycle Timing
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
t
t
ADH
ADS
t
t
AH
AS
A1
A2
ADDRESS
t
t
WES
WEH
GW, BWE,BW
X
Deselect Cycle
t
t
CES
CEH
CE
t
t
ADVH
ADVS
ADV
OE
ADV suspends burst
t
t
t
CDV
OEV
OELZ
t
t
OEHZ
CHZ
t
DOH
t
CLZ
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Q(A1)
Data Out (Q)
High-Z
t
CDV
Burst wraps around
to its initial state
Single READ
BURST
READ
DON’T CARE
UNDEFINED
Note:
26. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
Document #: 38-05544 Rev. *F
Page 21 of 29
CY7C1381D, CY7C1381F
CY7C1383D, CY7C1383F
Timing Diagrams (continued)
Write Cycle Timing
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC extends burst
t
t
ADH
ADS
t
t
ADH
ADS
ADSC
t
t
AH
AS
A1
A2
A3
ADDRESS
Byte write signals are ignored for first cycle when
ADSP initiates burst
t
t
WEH
WES
BWE,
BW
X
t
t
WEH
WES
GW
t
t
CEH
CES
CE
t
t
ADVH
ADVS
ADV
ADV suspends burst
OE
t
t
DH
DS
Data in (D)
High-Z
D(A2)
D(A2 + 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
D(A3)
D(A3 + 1)
D(A3 + 2)
D(A1)
t
OEHZ
Data Out (Q)
BURST READ
BURST WRITE
Extended BURST WRITE
Single WRITE
DON’T CARE
UNDEFINED
Note:
27.
Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW LOW.
X
Document #: 38-05544 Rev. *F
Page 22 of 29
CY7C1381D, CY7C1381F
CY7C1383D, CY7C1383F
Timing Diagrams (continued)
Read/Write Cycle Timing
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
t
t
AH
AS
A1
A2
A3
A4
A5
A6
ADDRESS
t
t
WEH
WES
BWE, BW
X
t
t
CEH
CES
CE
ADV
OE
t
t
DH
DS
t
OELZ
t
High-Z
D(A3)
D(A5)
D(A6)
Data In (D)
t
OEHZ
CDV
Data Out (Q)
Q(A1)
Q(A2)
Q(A4)
Q(A4+1)
Q(A4+2)
Q(A4+3)
Back-to-Back
WRITEs
Back-to-Back READs
Single WRITE
BURST READ
DON’T CARE
UNDEFINED
Notes:
28. The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC.
29.
GW is HIGH.
Document #: 38-05544 Rev. *F
Page 23 of 29
CY7C1381D, CY7C1381F
CY7C1383D, CY7C1383F
Timing Diagrams (continued)
ZZ Mode Timing
CLK
ZZ
t
t
ZZ
ZZREC
t
ZZI
I
SUPPLY
I
DDZZ
t
RZZI
ALL INPUTS
(except ZZ)
DESELECT or READ Only
Outputs (Q)
High-Z
DON’T CARE
Notes:
31. DQs are in high-Z when exiting ZZ sleep mode.
on page 9 for all possible signal conditions to deselect the device.
Document #: 38-05544 Rev. *F
Page 24 of 29
CY7C1381D, CY7C1381F
CY7C1383D, CY7C1383F
Ordering Information
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or
Speed
(MHz)
Package
Diagram
Operating
Range
Ordering Code
Part and Package Type
133 CY7C1381D-133AXC
CY7C1383D-133AXC
CY7C1381F-133BGC
CY7C1383F-133BGC
CY7C1381F-133BGXC
CY7C1383F-133BGXC
CY7C1381D-133BZC
CY7C1383D-133BZC
CY7C1381D-133BZXC
CY7C1383D-133BZXC
CY7C1381D-133AXI
CY7C1383D-133AXI
CY7C1381F-133BGI
CY7C1383F-133BGI
CY7C1381F-133BGXI
CY7C1383F-133BGXI
CY7C1381D-133BZI
CY7C1383D-133BZI
CY7C1381D-133BZXI
CY7C1383D-133BZXI
100 CY7C1381D-100AXC
CY7C1383D-100AXC
CY7C1381F-100BGC
CY7C1383F-100BGC
CY7C1381F-100BGXC
CY7C1383F-100BGXC
CY7C1381D-100BZC
CY7C1383D-100BZC
CY7C1381D-100BZXC
CY7C1383D-100BZXC
CY7C1381D-100AXI
CY7C1383D-100AXI
CY7C1381F-100BGI
CY7C1383F-100BGI
CY7C1381F-100BGXI
CY7C1383F-100BGXI
CY7C1381D-100BZI
CY7C1383D-100BZI
CY7C1381D-100BZXI
CY7C1383D-100BZXI
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free
Commercial
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
lndustrial
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
Commercial
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
lndustrial
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free
Document #: 38-05544 Rev. *F
Page 25 of 29
CY7C1381D, CY7C1381F
CY7C1383D, CY7C1383F
Package Diagrams
Figure 1. 100-Pin Thin Plastic Quad Flat pack (14 x 20 x 1.4 mm) (51-85050)
16.00 0.20
14.00 0.10
1.40 0.05
100
81
80
1
0.30 0.08
0.65
TYP.
12° 1°
(8X)
SEE DETAIL
A
30
51
31
50
0.20 MAX.
1.60 MAX.
R 0.08 MIN.
0.20 MAX.
0° MIN.
SEATING PLANE
STAND-OFF
0.05 MIN.
0.15 MAX.
NOTE:
1. JEDEC STD REF MS-026
0.25
GAUGE PLANE
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE
R 0.08 MIN.
0.20 MAX.
BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH
3. DIMENSIONS IN MILLIMETERS
0°-7°
0.60 0.15
0.20 MIN.
51-85050-*B
1.00 REF.
DETAIL
A
Document #: 38-05544 Rev. *F
Page 26 of 29
CY7C1381D, CY7C1381F
CY7C1383D, CY7C1383F
Package Diagrams (continued)
Figure 2. 119-ball BGA (14 x 22 x 2.4 mm) (51-85115)
51-85115-*B
Document #: 38-05544 Rev. *F
Page 27 of 29
CY7C1381D, CY7C1381F
CY7C1383D, CY7C1383F
Package Diagrams (continued)
Figure 3. 165-ball FBGA (13 x 15 x 1.4 mm) (51-85180)
BOTTOM VIEW
PIN 1 CORNER
TOP VIEW
Ø0.05 M C
PIN 1 CORNER
Ø0.25 M C A B
-0.06
Ø0.50
(165X)
+0.14
1
2
3
4
5
6
7
8
9
10
11
11 10
9
8
7
6
5
4
3
2
1
A
A
B
B
C
D
C
D
E
E
F
F
G
G
H
J
H
J
K
K
L
L
M
M
N
P
R
N
P
R
A
A
1.00
5.00
10.00
13.00 0.10
B
B
13.00 0.10
0.15(4X)
NOTES :
SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD)
PACKAGE WEIGHT : 0.475g
JEDECREFERENCE : MO-216 / DESIGN 4.6C
PACKAGE CODE : BB0AC
SEATING PLANE
C
51-85180-*A
Intel and Pentium are registered trademarks, and i486 is a trademark of Intel Corporation. All product and company names
mentioned in this document are the trademarks of their respective holders.
Document #: 38-05544 Rev. *F
Page 28 of 29
© Cypress Semiconductor Corporation, 2006-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for
the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended
to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY7C1381D, CY7C1381F
CY7C1383D, CY7C1383F
Document History Page
Document Title: CY7C1381D/CY7C1383D/CY7C1381F/CY7C1383F 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
Document Number: 38-05544
Orig. of
REV.
**
ECN NO. Issue Date Change
Description of Change
254518
288531
See ECN
See ECN
RKF
SYT
New data sheet
*A
Edited description under “IEEE 1149.1 Serial Boundary Scan (JTAG)” for
non-compliance with 1149.1
Removed 117-MHz Speed Bin
Added Pb-free information for 100-Pin TQFP, 119 BGA and 165 FBGA
package
Added comment of ‘Pb-free BG packages availability’ below the Ordering Infor-
mation
*B
326078
See ECN
PCI
Address expansion pins/balls in the pinouts for all packages are modified as
per JEDEC standard
Added description on EXTEST Output Bus Tri-State
Changed description on the Tap Instruction Set Overview and Extest
Changed Device Width (23:18) for 119-BGA from 000001 to 101001
Added separate row for 165 -FBGA Device Width (23:18)
Changed Θ and Θ for TQFP Package from 31 and 6 °C/W to 28.66 and
JA
JC
4.08 °C/W respectively
Changed Θ and Θ for BGA Package from 45 and 7 °C/W to 23.8 and 6.2
JA
JC
°C/W respectively
Changed Θ and Θ for FBGA Package from 46 and 3 °C/W to 20.7 and 4.0
JA
JC
°C/W respectively
Modified V
V
test conditions
OL, OH
Removed comment of ‘Pb-free BG packages availability’ below the Ordering
Information
Updated Ordering Information Table
Changed from Preliminary to Final
*C
*D
351895
416321
See ECN
See ECN
PCI
Updated Ordering Information Table
NXR
Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”
Changed the description of I from Input Load Current to Input Leakage
X
Current on page# 18
Changed the I current values of MODE on page # 18 from –5 µA and 30 µA
X
to –30 µA and 5 µA
Changed the I current values of ZZ on page # 18 from –30 µA and 5 µA
X
to –5 µA and 30 µA
Changed V < V to V < V on page # 18
IH
DD
IH
DD
Replaced Package Name column with Package Diagram in the Ordering
Information table
Updated Ordering Information Table
*E
*F
475009
776456
See ECN
See ECN
VKN
VKN
Added the Maximum Rating for Supply Voltage on V
Relative to GND
DDQ
Changed t , t from 25 ns to 20 ns and t
from 5 ns to 10 ns in TAP AC
TH TL
TDOV
Switching Characteristics table.
Updated the Ordering Information table.
Added Part numbers CY7C1381F and CY7C1383F and its related information
Added footnote# 3 regarding Chip Enable
Updated Ordering Information table
Document #: 38-05544 Rev. *F
Page 29 of 29
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