CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV
3.3V 4K/8K/16K x 16/18 Dual-Port
Static RAM
■
■
■
Fully asynchronous operation
Automatic power down
Features
■
True dual-ported memory cells which enable simultaneous
access of the same memory location
Expandable data bus to 32 bits, 36 bits or more using Master
and Slave chip select when using more than one device
■
■
■
■
■
■
■
4, 8 or 16K × 16 organization
■
■
On chip arbitration logic
4 or 8K × 18 organization (CY7C0241AV/0251AV)
16K × 18 organization (CY7C036AV)
0.35 micron CMOS for optimum speed and power
High speed access: 20 and 25 ns
Semaphores included to permit software handshaking
between ports
■
■
■
■
■
INT flag for port-to-port communication
Separate upper byte and lower byte control
Pin select for Master or Slave (M/S)
Low operating power
Commercial and industrial temperature ranges
Available in 100-pin Pb-free TQFP and 100-pin TQFP
❐
Active: ICC = 115 mA (typical)
❐
Standby: ISB3 = 10 μA (typical)
Logic Block Diagram
R/WL
UBL
R/WR
UBR
CEL
CER
LBL
LBR
OEL
OER
[2]
8/9
8/9
8/9
[2]
IO8/9L–IO15/17L
IO8/9L–IO15/17R
[3]
8/9
IO
Control
IO
Control
[3]
IO0L–IO7/8L
IO0L–IO7/8R
12/13/14
12/13/14
[4]
A0R–A11/12/13R
Address
Decode
Address
Decode
[4]
True Dual-Ported
RAM Array
A0L–A11/1213L
[4]
[4]
12/13/14
12/13/14
A0L–A11/12/13L
A0R–A11/12/13R
CER
CEL
Interrupt
Semaphore
Arbitration
OEL
R/WL
OER
R/WR
SEML
SEMR
[5]
[5]
BUSYL
INTL
UBL
BUSYR
INTR
UBR
LBL
M/S
LBR
Notes
1. CY7C024AV and CY7C024BV are functionally identical.
2. IO –IO for x16 devices; IO –IO for x18 devices.
8
15
9
17
3. IO –IO for x16 devices; IO –IO for x18 devices.
0
7
0
8
4. A –A for 4K devices; A –A for 8K devices; A –A for 16K devices.
0
11
0
12
0
13
5. BUSY is an output in master mode and an input in slave mode.
Cypress Semiconductor Corporation
Document #: 38-06052 Rev. *J
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised December 10, 2008
CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV
Pin Configurations (continued)
Figure 2. 100-Pin TQFP (Top View)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
75
74
73
NC
NC
NC
NC
1
NC
NC
2
3
4
IO
8L
17L
11L
72
71
70
69
IO
IO
IO
IO
A
5L
5
6
7
8
A
4L
12L
13L
A
A
A
3L
2L
1L
0L
68
IO
14L
67
66
GND
9
A
IO
IO
10
11
12
13
15L
16L
INT
BUSY
L
65
64
63
62
L
V
GND
M/
BUSY
CC
CY7C0241AV (4K × 18)
CY7C0251AV (8K × 18)
GND
IO
0R
IO
1R
S
14
61
60
59
R
INT
15
16
17
R
IO
2R
A
A
A
0R
1R
V
CC
3R
58
IO
18
19
20
21
57
56
55
54
53
2R
3R
IO
IO
IO
IO
A
4R
5R
6R
8R
A
4R
NC
22
23
NC
NC
IO
17R
52
51
NC
NC
24
25
NC
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
10099 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
75
NC
1
NC
NC
NC
2
3
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
NC
A6L
A5L
A4L
A3L
A2L
A1L
A0L
INT
BUSY
GND
NC
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
IO10L
IO11L
IO12L
IO13L
GND
IO14L
IO15L
VCC
GND
IO0R
IO1R
IO2R
VCC
IO3R
IO4R
IO5R
IO6R
NC
L
L
CY7C026AV (16K × 16)
M/
BUSY
INT
S
R
R
A0R
A1R
A2R
A3R
A4R
A5R
NC
NC
NC
NC
24
25
NC
NC
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Notes
8.
9.
A
A
on the CY7C0251AV.
on the CY7C0251AVC.
12L
12R
Document #: 38-06052 Rev. *J
Page 3 of 19
CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV
Pin Configurations (continued)
Figure 3. 100-Pin TQFP (Top View)
100 9998 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
75
74
73
72
71
70
69
NC
NC
NC
1
NC
NC
2
3
4
IO
8L
17L
11L
A
13L
IO
IO
IO
IO
A
5L
5
6
7
8
A
4L
12L
13L
A
3L
A
2L
68
IO
14L
A
1L
67
66
GND
9
A
0L
IO
IO
10
11
12
13
15L
16L
INT
BUSY
GND
M/S
L
65
64
63
62
L
V
CC
CY7C036AV (16K × 18)
GND
IO
0R
IO
1R
14
BUSY
INT
61
60
59
R
15
16
17
R
IO
2R
A
0R
V
CC
3R
A
1R
58
IO
18
19
20
21
A
2R
57
56
55
54
53
IO
IO
IO
IO
A
3R
4R
5R
6R
8R
A
4R
A
13R
22
23
NC
NC
IO
17R
52
51
NC
NC
24
25
NC
26 27 28 29 30 31 32 3334 35 36 37 38 39 40 41 42 43 44 45 46 4748 49 50
Selection Guide
CY7C024AV/024BV/025AV/026AV CY7C024AV/024BV/025AV/026AV
Parameter
CY7C0241AV/0251AV/036AV
-20
CY7C0241AV/0251AV/036AV
-25
Unit
Maximum Access Time
20
120
35
25
115
30
ns
Typical Operating Current
mA
mA
Typical Standby Current for ISB1
(Both ports TTL Level)
Typical Standby Current for ISB3
(Both ports CMOS Level)
10
10
μA
Document #: 38-06052 Rev. *J
Page 4 of 19
CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV
Pin Definitions
Left Port
CEL
Right Port
CER
Description
Chip Enable
R/WL
OEL
R/WR
Read and Write Enable
Output Enable
OER
A0L–A13L
IO0L–IO17L
SEML
UBL
A0R–A13R
IO0R–IO17R
SEMR
UBR
Address (A0–A11 for 4K devices; A0–A12 for 8K devices; A0–A13 for 16K)
Data Bus Input and Output
Semaphore Enable
Upper Byte Select (IO8–IO15 for x16 devices; IO9–IO17 for x18 devices)
LBL
LBR
Lower Byte Select (IO0–IO7 for x16 devices; IO0–IO8 for x18 devices)
INTL
INTR
Interrupt Flag
Busy Flag
BUSYL
M/S
BUSYR
Master or Slave Select
Power
VCC
GND
Ground
NC
No Connect
accessed by the other port. The Interrupt flag (INT) permits
communication between ports or systems by means of a mail
Architecture
box. The semaphores are used to pass a flag, or token, from one
port to the other to indicate that a shared resource is in use. The
semaphore logic has eight shared latches. Only one side can
control the latch (semaphore) at any time. Control of a
semaphore indicates that a shared resource is in use. An
automatic power down feature is controlled independently on
each port by a Chip Select (CE) pin.
The
CY7C024AV/024BV/025AV/026AV
and
CY7C0241AV/0251AV/036AV consist of an array of 4K, 8K, and
16K words of 16 and 18 bits each of dual-port RAM cells, IO and
address lines, and control signals (CE, OE, RW). These control pins
permit independent access for reads or writes to any location in
memory. To handle simultaneous writes and reads to the same
location, a BUSY pin is provided on each port. Two Interrupt (INT)
pins can be used for port to port communication. Two Semaphore
(SEM) control pins are used for allocating shared resources. With
the M/S pin, the devices can function as a master (BUSY pins are
outputs) or as a slave (BUSY pins are inputs). They also have an
automatic power down feature controlled by CE. Each port has its
own output enable control (OE), which enables data to be read from
the device.
The
CY7C024AV/024BV/025AV/026AV
and
CY7C0241AV0251AV/036AV are available in 100-pin Pb-free Thin
Quad Flat Pack (TQFP) and 100-pin TQFP.
Write Operation
Data must be set up for a duration of tSD before the rising edge
of RW to guarantee a valid write. A write operation is controlled
Functional Description
The
CY7C024AV/024BV/025AV/026AV
and
CY7C0241AV/0251AV/036AV are low power CMOS 4K, 8K, and
16K ×16/18 dual port static RAMs. Various arbitration schemes are
included on the devices to handle situations when multiple
processors access the same piece of data. There are two ports
permitting independent, asynchronous access for reads and writes
to any location in memory. The devices can be used as standalone
16 or18-bit dual port static RAMs or multiple devices can be
combined to function as a 32 or 36-bit or wider master and slave
dual port static RAM. An M/S pin is provided for implementing 32 or
36-bit or wider memory applications. It does not need separate
master and slave devices or additional discrete logic. Application
areas include interprocessor/multiprocessor designs, communica-
tions status buffering, and dual port video and graphics memory.
If a location is being written to by one port and the opposite port
tries to read that location, there must be a port to port flowthrough
delay before the data is read on the output; otherwise the data
read is not deterministic. Data is valid on the port tDDD after the
data is presented on the other port.
Read Operation
When reading the device, the user must assert both the OE and
CE pins. Data is available tACE after CE or tDOE after OE is
asserted. If the user wants to access a semaphore flag, then the
SEM pin and OE must be asserted.
Interrupts
Each port has independent control pins: Chip Enable (CE), Read
or Write Enable (R/W), and Output Enable (OE). Two flags are
provided on each port (BUSY and INT). BUSY signals that the
port is trying to access the same location currently being
The upper two memory locations are for message passing. The
highest
memory
location
(FFF
for
the
CY7C024AV/024BV/41AV/1FFF for the CY7C025AV/51AV,
Document #: 38-06052 Rev. *J
Page 5 of 19
CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV
3FFF for the CY7C026AV/36AV) is the mailbox for the right port
and the second highest memory location (FFE for the
CY7C024AV/024BV/41AV/1FFE for the CY7C025AV/51AV,
3FFE for the CY7C026AV/36AV) is the mailbox for the left port.
When one port writes to the other port’s mailbox, an interrupt is
generated to the owner. The interrupt is reset when the owner
reads the contents of the mailbox. The message is user defined.
Semaphore Operation
The CY7C024AV/024BV/025AV/026AV
and
CY7C0241AV/0251AV/036AV provide eight semaphore latches,
which are separate from the dual port memory locations.
Semaphores are used to reserve resources that are shared
between the two ports. The state of the semaphore indicates that
a resource is in use. For example, if the left port wants to request
a given resource, it sets a latch by writing a zero to a semaphore
location. The left port then verifies its success in setting the latch
by reading it. After writing to the semaphore, SEM or OE must
be deasserted for tSOP before attempting to read the semaphore.
The semaphore value is available tSWRD + tDOE after the rising
edge of the semaphore write. If the left port was successful
(reads a zero), it assumes control of the shared resource.
Otherwise (reads a one), it assumes the right port has control
and continues to poll the semaphore. When the right side has
relinquished control of the semaphore (by writing a one), the left
side succeeds in gaining control of the semaphore. If the left side
no longer requires the semaphore, a one is written to cancel its
request.
Each port can read the other port’s mailbox without resetting the
interrupt. The active state of the busy signal (to a port) prevents
the port from setting the interrupt to the winning port. Also, an
active busy to a port prevents that port from reading its own
mailbox and, thus, resetting the interrupt to it.
If an application does not require message passing, do not
connect the interrupt pin to the processor’s interrupt request
input pin.
The operation of the interrupts and their interaction with Busy are
Busy
The
CY7C024AV/024BV/025AV/026AV
and
Semaphores are accessed by asserting SEM LOW. The SEM
pin functions as a chip select for the semaphore latches (CE
must remain HIGH during SEM LOW). A0–2 represents the
semaphore address. OE and RW are used in the same manner
as a normal memory access. When writing or reading a
semaphore, the other address pins have no effect.
CY7C0241AV/0251AV/036AV provide on-chip arbitration to resolve
simultaneous memory location access (contention). If both ports’
CEs are asserted and an address match occurs within tPS of each
other, the busy logic determines which port has access. If tPS is
violated, one port definitely gains permission to the location, but it is
not predictable which port gets that permission. BUSY is asserted
tBLA after an address match or tBLC after CE is taken LOW.
When writing to the semaphore, only IO0 is used. If a zero is
written to the left port of an available semaphore, a one appears
at the same semaphore address on the right port. That
semaphore can now only be modified by the side showing zero
(the left port in this case). If the left port now relinquishes control
by writing a one to the semaphore, the semaphore is set to one
for both sides. However, if the right port had requested the
semaphore (written a zero) while the left port had control, the
right port would immediately own the semaphore as soon as the
operations.
Master/Slave
A M/S pin helps to expand the word width by configuring the
device as a master or a slave. The BUSY output of the master is
connected to the BUSY input of the slave. This enables the
device to interface to a master device with no external compo-
nents. Writing to slave devices must be delayed until after the
BUSY input has settled (tBLC or tBLA). Otherwise, the slave chip
may begin a write cycle during a contention situation. When tied
HIGH, the M/S pin enables the device to be used as a master
and, therefore, the BUSY line is an output. BUSY can then be
used to send the arbitration outcome to a slave.
When reading a semaphore, all 16 and 18 data lines output the
semaphore value. The read value is latched in an output register
to prevent the semaphore from changing state during a write
from the other port. If both ports attempt to access the
semaphore within tSPS of each other, the semaphore is definitely
obtained by one of them. But there is no guarantee which side
controls the semaphore.
Document #: 38-06052 Rev. *J
Page 6 of 19
CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV
Table 1. Non-Contending Read/Write
Inputs
Outputs
Operation
CE
H
X
L
R/W
X
OE
X
X
X
X
X
L
UB
X
H
L
LB
X
H
H
L
SEM
H
H
H
H
H
H
H
H
X
IO9–IO17
High Z
IO0–IO8
High Z
Deselected: Power Down
Deselected: Power Down
Write to Upper Byte Only
Write to Lower Byte Only
Write to Both Bytes
X
High Z
High Z
L
Data In
High Z
High Z
L
L
H
L
Data In
Data In
High Z
L
L
L
Data In
Data Out
High Z
L
H
H
H
X
L
H
L
Read Upper Byte Only
Read Lower Byte Only
Read Both Bytes
L
L
H
L
Data Out
Data Out
High Z
L
L
L
Data Out
High Z
X
H
X
H
H
L
X
X
H
X
X
X
H
X
Outputs Disabled
H
H
L
Data Out
Data Out
Data In
Data Out
Data Out
Data In
Read Data in Semaphore Flag
Read Data in Semaphore Flag
Write DIN0 into Semaphore Flag
L
L
X
L
X
X
H
H
L
Data In
Data In
Write DIN0 into Semaphore Flag
L
L
X
X
X
X
L
X
L
L
L
Not Allowed
Not Allowed
X
Left Port
Right Port
Function
R/WL CEL
OEL
X
A0L–13L
FFF[13]
X
INTL R/WR CER
OER
X
A0R–13R
INTR
L[12]
Set Right INTR Flag
Reset Right INTR Flag
Set Left INTL Flag
Reset Left INTL Flag
L
X
X
X
L
X
X
L
X
X
X
L
X
L
L
X
X
X
X
L
X
X
L[11]
H[12]
X
1FFE (or 1/3FFE)
X
X
X
L
1FFE[13]
X
X
Table 3. Semaphore Operation Example
Function IO0–IO17 Left IO0–IO17 Right
Status
No action
1
0
0
1
1
0
1
1
1
0
1
1
1
1
0
0
1
1
0
1
1
1
Semaphore-free
Left Port has semaphore token
Left port writes 0 to semaphore
Right port writes 0 to semaphore
Left port writes 1 to semaphore
Left port writes 0 to semaphore
Right port writes 1 to semaphore
Left port writes 1 to semaphore
Right port writes 0 to semaphore
Right port writes 1 to semaphore
Left port writes 0 to semaphore
No change. Right side has no write access to semaphore
Right port obtains semaphore token
No change. Left port has no write access to semaphore
Left port obtains semaphore token
Semaphore-free
Right port has semaphore token
Semaphore free
Left port has semaphore token
Semaphore-free
Left port writes 1 to semaphore
Notes
11. If BUSY =L, then no change.
R
12. If BUSY =L, then no change.
L
Document #: 38-06052 Rev. *J
Page 7 of 19
CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV
Output Current into Outputs (LOW).............................20 mA
Static Discharge Voltage.......................................... > 2001V
Latch-up Current.................................................... > 200 mA
Maximum Ratings
device. User guidelines are not tested.
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied ............................................ –55°C to +125°C
Operating Range
Range
Commercial
Ambient Temperature
0°C to +70°C
VCC
Supply Voltage to Ground Potential............... –0.5V to +4.6V
3.3V ± 300 mV
3.3V ± 300 mV
DC Voltage Applied to
Outputs in High-Z State .........................–0.5V to VCC + 0.5V
–40°C to +85°C
Electrical Characteristics
Over the Operating Range
CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV
Parameter
Description
Unit
-20
-25
Min
Typ
Max
Min
Typ
Max
VOH
Output HIGH Voltage (VCC=3.3V)
Output LOW Voltage
2.4
2.4
V
VOL
VIH
VIL
IOZ
IIX
0.4
0.4
V
Input HIGH Voltage
2.0
–10
2.0
V
Input LOW Voltage
0.8
10
0.8
10
V
Output Leakage Current
Input Leakage Current
Operating Current (VCC = Max.,
–10
–10
μA
μA
mA
mA
mA
mA
mA
mA
μA
μA
mA
mA
–10
10
10
ICC
Com’l.
Com’l.
Com’l.
120
35
175
115
135
30
40
65
75
10
10
60
70
165
185
40
I
OUT = 0 mA) Outputs Disabled
ISB1
ISB2
ISB3
ISB4
Standby Current (Both Ports TTL Level)
CEL & CER ≥ VIH, f = fMAX
45
110
500
95
50
Standby Current (One Port TTL Level)
CEL | CER ≥ VIH, f = fMAX
75
95
105
500
500
80
Standby Current (Both Ports CMOS Level) Com’l.
CEL & CER ≥ VCC−0.2V, f = 0
10
Standby Current (One Port CMOS Level)
Com’l.
70
CEL | CER ≥ VIH, f = fMAX
90
Capacitance
Parameter[19]
Description
Input Capacitance
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
CC = 3.3V
Max
10
Unit
CIN
pF
pF
V
COUT
10
Notes
14. The voltage on any input or IO pin cannot exceed the power pin during power up.
15. Pulse width < 20 ns.
16. Industrial parts are available in CY7C026AV and CY7C036AV only.
17. VIL > –1.5V for pulse width less than 10ns.
18. f
= 1/t = All inputs cycling at f = 1/t (except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level
MAX
RC RC
standby I
.
SB3
19. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-06052 Rev. *J
Page 8 of 19
CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV
Figure 4. AC Test Loads and Waveforms
3.3V
3.3V
R
TH
= 250Ω
R1 = 590Ω
OUTPUT
C = 30pF
OUTPUT
C = 30 pF
R1 = 590Ω
OUTPUT
C = 5 pF
R2 = 435Ω
R2 = 435Ω
V
TH
= 1.4V
(a) Normal Load (Load 1)
(c) Three-State Delay (Load 2)
(Used for tLZ, tHZ, tHZWE, and tLZWE
(b) Thévenin Equivalent (Load 1)
ALL INPUTPULSES
including scope and jig)
3.0V
GND
90%
90%
10%
3 ns
10%
3 ns
≤
≤
Switching Characteristics
Over the Operating Range [20]
CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV
Parameter
Description
Unit
-20
-25
Min
20
3
Max
Min
25
3
Max
Read Cycle
tRC
Read Cycle Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to Data Valid
Output Hold From Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE Low to Low Z
20
25
tOHA
[21]
tACE
tDOE
tLZOE
20
12
25
13
3
3
0
3
3
0
tHZOE
OE HIGH to High Z
12
12
15
15
tLZCE
CE LOW to Low Z
tHZCE
CE HIGH to High Z
tPU
tPD
CE LOW to Power Up
CE HIGH to Power Down
Byte Enable Access Time
20
20
25
25
tABE
Write Cycle
tWC
Write Cycle Time
20
15
15
0
25
20
20
0
ns
ns
ns
ns
ns
[21]
tSCE
tAW
tHA
CE LOW to Write End
Address Valid to Write End
Address Hold From Write End
Address Setup to Write Start
[21]
tSA
0
0
Notes
20. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified I /I
OI OH
and 30 pF load capacitance.
21. To access RAM, CE = L, UB = L, SEM = H. To access semaphore, CE = H and SEM = L. Either condition must be valid for the entire t
time.
SCE
22. At any given temperature and voltage condition for any given device, t
23. Test conditions used are Load 3.
is less than t
and t
is less than t
.
HZCE
LZCE
HZOE
LZOE
24. This parameter is guaranteed but not tested. For information on port to port delay through RAM cells from writing port to reading port, refer to Figure 12.
Document #: 38-06052 Rev. *J
Page 9 of 19
CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV
Switching Characteristics
Over the Operating Range (continued)[20]
CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV
Unit
Parameter
Description
-20
-25
Min
15
15
0
Max
Min
20
15
0
Max
tPWE
tSD
Write Pulse Width
ns
ns
ns
ns
ns
ns
ns
Data Setup to Write End
Data Hold From Write End
R/W LOW to High Z
tHD
tHZWE
12
15
tLZWE
R/W HIGH to Low Z
3
0
tWDD
Write Pulse to Data Delay
Write Data Valid to Read Data Valid
45
30
50
35
[25]
tDDD
tBLA
BUSY LOW from Address Match
BUSY HIGH from Address Mismatch
BUSY LOW from CE LOW
20
20
20
17
20
20
20
17
ns
ns
ns
ns
ns
ns
ns
ns
tBHA
tBLC
tBHC
tPS
BUSY HIGH from CE HIGH
Port Setup for Priority
5
0
5
0
tWB
R/W HIGH after BUSY (Slave)
R/W HIGH after BUSY HIGH (Slave)
BUSY HIGH to Data Valid
tWH
15
17
tBDD
Interrupt Timing[26]
tINS
tINR
Semaphore Timing
20
25
INT Set Time
20
20
20
20
ns
ns
INT Reset Time
tSOP
tSWRD
tSPS
SEM Flag Update Pulse (OE or SEM)
SEM Flag Write to Read Time
SEM Flag Contention Window
SEM Address Access Time
10
5
12
5
ns
ns
ns
ns
5
5
tSAA
20
25
Data Retention Mode
Timing
The
CY7C024AV/024BV/025AV/026AV
and
Data Retention Mode
3.0V
CY7C0241AV/0251AV/036AV are designed for battery backup.
Data retention voltage and supply current are guaranteed over
temperature. The following rules ensure data retention:
V
CC
3.0V
V
CC
> 2.0V
t
RC
1. Chip Enable (CE) must be held HIGH during data retention,
within VCC to VCC – 0.2V.
V
CC
to V – 0.2V
CC
V
IH
CE
2. CE must be kept between VCC – 0.2V and 70 percent of VCC
during the power up and power down transitions.
3. The RAM can begin operation >tRC after VCC reaches the
minimum operating voltage (3.0V).
Parameter
Test Conditions[28]
at VCCDR = 2V
Max
Unit
ICCDR1
50
μA
Notes
25. For information on port to port delay through RAM cells from writing port to reading port, refer to Figure 12.
26. Test conditions used are Load 2.
27. t
is a calculated parameter and is the greater of t
– t
(actual) or t
– t (actual).
BDD
WDD
PWE
DDD SD
28. CE = V , V = GND to V , T = 25°C. This parameter is guaranteed but not tested.
CC
in
CC
A
Document #: 38-06052 Rev. *J
Page 10 of 19
CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV
Switching Waveforms
t
RC
ADDRESS
DATA OUT
t
AA
t
t
OHA
OHA
PREVIOUS DATAVALID
DATA VALID
t
ACE
CE and
LB or UB
t
HZCE
t
DOE
OE
t
HZOE
t
LZOE
DATA VALID
DATA OUT
t
LZCE
t
PU
t
PD
I
CC
CURRENT
I
SB
t
RC
ADDRESS
UB or LB
t
AA
t
OHA
t
t
HZCE
t
t
LZCE
LZCE
t
ABE
CE
HZCE
t
ACE
DATA OUT
Notes
29. R/W is HIGH for read cycles.
30. Device is continuously selected CE = V and UB or LB = V . This waveform cannot be used for semaphore reads.
IL
IL
31. OE = V .
IL
32. Address valid prior to or coincident with CE transition LOW.
33. To access RAM, CE = V , UB or LB = V , SEM = V . To access semaphore, CE = V , SEM = V .
IL
IL
IH
IH
IL
Document #: 38-06052 Rev. *J
Page 11 of 19
CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV
Switching Waveforms (continued)
t
WC
ADDRESS
OE
t
HZOE
t
AW
CE
[37]
PWE
t
t
t
HA
SA
R/W
DATAOUT
DATA IN
[40]
HZWE
t
t
LZWE
t
t
HD
SD
t
WC
ADDRESS
t
AW
CE
t
t
t
HA
SA
SCE
R/W
t
t
SD
HD
DATA IN
Notes
34. R/W or CE must be HIGH during all address transitions.
35. A write occurs during the overlap (t or t ) of a LOW CE or SEM and a LOW UB or LB.
SCE
PWE
36. t is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle.
HA
37. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t
or (t
+ t ) to enable the IO drivers to turn off and
PWE
HZWE SD
data to be placed on the bus for the required t . If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can
SD
be as short as the specified t
.
PWE
38. To access RAM, CE = V , SEM = V
.
IH
IL
39. To access upper byte, CE = V , UB = V , SEM = V .
IL
IL
IL
IL
IH
IH
To access lower byte, CE = V , LB = V , SEM = V .
40. Transition is measured ±500 mV from steady state with a 5 pF load (including scope and jig). This parameter is sampled and not 100 percent tested.
41. During this period, the IO pins are in the output state, and input signals must not be applied.
42. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high impedance state.
Document #: 38-06052 Rev. *J
Page 12 of 19
CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV
Switching Waveforms (continued)
t
t
OHA
SAA
A –A
0
VALID ADRESS
VALID ADRESS
2
t
AW
t
ACE
t
HA
SEM
t
t
SOP
SCE
t
SD
IO
0
DATA VALID
DATA
VALID
IN
OUT
t
HD
t
t
PWE
SA
R/W
OE
t
t
DOE
SWRD
t
SOP
WRITE CYCLE
READ CYCLE
A
0L
–A
2L
MATCH
R/W
L
SEM
–A
L
t
SPS
A
MATCH
0R
2R
R/W
R
SEM
R
Notes
43. CE = HIGH for the duration of the above timing (both write and read cycle).
44. IO = IO = LOW (request semaphore); CE = CE = HIGH.
0R
0L
R
L
45. Semaphores are reset (available to both ports) at cycle start.
46. If t is violated, the semaphore is definitely obtained by one side or the other, but which side gets the semaphore is unpredictable.
SPS
Document #: 38-06052 Rev. *J
Page 13 of 19
CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV
Switching Waveforms (continued)
t
WC
ADDRESS
R
MATCH
t
PWE
R/W
R
t
t
HD
SD
DATA IN
VALID
R
t
PS
ADDRESS
L
MATCH
t
BLA
t
BHA
BUSY
L
t
BDD
t
DDD
DATA
VALID
OUTL
t
WDD
Figure 13. Write Timing with Busy Input (M/S=LOW)
t
PWE
R/W
t
t
WH
WB
BUSY
Note
47. CE = CE = LOW.
L
R
Document #: 38-06052 Rev. *J
Page 14 of 19
CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV
Switching Waveforms (continued)
CELValid First
ADDRESS
L,R
ADDRESS MATCH
CE
L
t
PS
CE
R
t
t
BHC
BLC
BUSY
R
CER ValidFirst:
ADDRESS
L,R
ADDRESS MATCH
CE
R
t
PS
CE
L
L
t
t
BHC
BLC
BUSY
Left Address Valid First:
t
or t
WC
RC
ADDRESS
L
ADDRESS MATCH
ADDRESS MISMATCH
t
PS
ADDRESS
R
t
t
BHA
BLA
BUSY
R
Right AddressValid First:
t
or t
WC
RC
ADDRESS
R
ADDRESS MATCH
ADDRESS MISMATCH
t
PS
ADDRESS
L
t
t
BHA
BLA
BUSY
L
Note
48. If t is violated, the busy signal is asserted on one side or the other, but there is no guarantee to which side BUSY is asserted.
PS
Document #: 38-06052 Rev. *J
Page 15 of 19
CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV
Switching Waveforms (continued)
Figure 16. Interrupt Timing Diagram
Left Side Sets INTR :
t
WC
ADDRESS
WRITE 1FFF (OR 1/3FFF)
L
[49]
t
HA
CE
L
R/W
INT
L
R
t
INS
Right Side Clears INTR:
t
RC
READ 7FFF
(OR 1/3FFF)
ADDRESS
R
CE
R
[50]
t
INR
R/W
R
OE
R
INT
R
:
Right Side Sets INTL
t
WC
ADDRESS
R
WRITE 1FFE (OR 1/3FFE)
[49]
HA
t
CE
R
R
R/W
INT
L
INS
t
Left SideClears INTL:
t
RC
READ 7FFE
OR 1/3FFE)
ADDRESS
R
CE
L
[50]
t
INR
R/W
OE
L
L
L
INT
Notes
49. t depends on which enable pin (CE or R/W ) is deasserted first.
HA
L
L
50. t
or t
depends on which enable pin (CE or R/W ) is asserted last.
INS
INR
L
L
Document #: 38-06052 Rev. *J
Page 16 of 19
CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV
Ordering Information
4K x16 3.3V Asynchronous Dual-Port SRAM
Speed
(ns)
Package
Operating
Ordering Code
CY7C024AV-15AI
Diagram
51-85048
51-85048
51-85048
51-85048
51-85048
51-85048
51-85048
51-85048
51-85048
51-85048
Package Type
100-Pin Thin Quad Flat Pack
Range
15
Industrial
CY7C024BV-15AXI
CY7C024AV-20AC
CY7C024AV-20AXC
CY7C024AV-20AI
CY7C024AV-20AXI
CY7C024AV-25AC
CY7C024AV-25AXC
CY7C024AV-25AI
CY7C024AV-25AXI
100-Pin Pb-Free Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
20
Commercial
Industrial
100-Pin Pb-Free Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
100-Pin Pb-Free Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
25
Commercial
Industrial
100-Pin Pb-Free Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
100-Pin Pb-Free Thin Quad Flat Pack
8K x16 3.3V Asynchronous Dual-Port SRAM
Speed
(ns)
Package
Operating
Range
Ordering Code
CY7C025AV-20AC
CY7C025AV-20AXC
CY7C025AV-20AXI
CY7C025AV-25AC
CY7C025AV-25AXC
CY7C025AV-25AI
Name
Package Type
100-Pin Thin Quad Flat Pack
20
51-85048
51-85048
51-85048
51-85048
51-85048
51-85048
51-85048
Commercial
100-Pin Pb-Free Thin Quad Flat Pack
100-Pin Pb-Free Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
Industrial
25
Commercial
100-Pin Pb-Free Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
Industrial
CY7C025AV-25AXI
100-Pin Pb-Free Thin Quad Flat Pack
16K x16 3.3V Asynchronous Dual-Port SRAM
Speed
(ns)
Package
Operating
Range
Ordering Code
CY7C026AV-20AC
CY7C026AV-20AXC
CY7C026AV-20AXI
CY7C026AV-25AC
CY7C026AV-25AXC
CY7C026AV-25AI
Name
Package Type
100-Pin Thin Quad Flat Pack
20
51-85048
51-85048
51-85048
51-85048
51-85048
51-85048
51-85048
Commercial
100-Pin Pb-Free Thin Quad Flat Pack
100-Pin Pb-Free Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
Industrial
25
Commercial
100-Pin Pb-Free Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
Industrial
CY7C026AV-25AXI
100-Pin Pb-Free Thin Quad Flat Pack
4K x18 3.3V Asynchronous Dual-Port SRAM
Speed
(ns)
Package
Operating
Range
Ordering Code
CY7C0241AV-20AC
CY7C0241AV-25AC
Name
Package Type
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
20
25
51-85048
51-85048
Commercial
Commercial
8K x18 3.3V Asynchronous Dual-Port SRAM
Speed
(ns)
Package
Operating
Range
Ordering Code
CY7C0251AV-20AC
CY7C0251AV-25AC
Name
Package Type
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
20
25
51-85048
51-85048
Commercial
Commercial
Document #: 38-06052 Rev. *J
Page 17 of 19
CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV
16K x18 3.3V Asynchronous Dual-Port SRAM
Speed
(ns)
Package
Operating
Ordering Code
CY7C036AV-20AC
CY7C036AV-25AC
CY7C036AV-25AXC
CY7C036AV-25AI
Name
Package Type
100-Pin Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
100-Pin Pb-free Thin Quad Flat Pack
100-Pin Thin Quad Flat Pack
Range
Commercial
Commercial
20
25
51-85048
51-85048
51-85048
51-85048
Industrial
Package Diagram
Figure 17. 100-Pin Pb-Free Thin Plastic Quad Flat Pack (TQFP) A100
51-85048 *C
Document #: 38-06052 Rev. *J
Page 18 of 19
CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV
Document History Page
Document Title: CY7C024AV/024BV/025AV/026AV, CY7C0241AV/0251AV/036AV 3.3V 4K/8K/16K x 16/18 Dual-Port Static RAM
Document Number: 38-06052
Orig. of Submission
Rev.
ECN No.
Description of Change
Change
Date
**
110204
122302
128958
237622
241968
276451
279452
SZV
11/11/01
12/27/02
9/03/03
Change from Spec number: 38-00838 to 38-06052
Power up requirements added to Maximum Ratings Information
Added CY7C025AV-25AI to Ordering Information
*A
*B
*C
*D
*E
*F
RBI
JFU
YDT
See ECN Removed cross information from features section
See ECN Added CY7C024AV-25AI to Ordering Information
See ECN Corrected x18 for 026AV to x16
WWZ
SPN
RUY
See ECN Added Pb-free packaging information
Corrected pin A113L to A13L on CY7C026AV pin list
Added minimum VIL of 0.3V and note 16
*G
*H
373580
380476
RUY
PCX
See ECN Corrected CY7C024AC-25AXC to CY7C024AV-25AXC in Ordering Information
See ECN Added to Part Ordering information:
CY7C024AV-15AI, CY7C024AV-15AXI, CY7C024AV-20AI,
CY7C024AV-20AXI, CY7C025AV-20AXI, CY7C026AV-20AXI
*I
2543577 NXR/AESA
2623540 VKN/PYRS
07/25/08
12/17/08
Updated note number 33 on page 12 from “R/W must be HIGH during all
address transitions” to “R/W or CE must be HIGH during all address transitions”
*J
Added CY7C024BV part
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Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
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Document #: 38-06052 Rev. *J
Revised December 10, 2008
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