CY62148E MoBL®
4-Mbit (512K x 8) Static RAM
Features
Functional Description [1]
• Very high speed: 45 ns
The CY62148E is a high performance CMOS static RAM
organized as 512K words by 8 bits. This device features
advanced circuit design to provide ultra low active current.
• Voltage range: 4.5V–5.5V
• Pin compatible with CY62148B
• Ultra low standby power
®
This is ideal for providing More Battery Life™ (MoBL ) in
portable applications such as cellular telephones. The device
also has an automatic power down feature that significantly
reduces power consumption when addresses are not toggling.
Placing the device into standby mode reduces power
consumption by more than 99% when deselected (CE HIGH).
— Typical standby current: 1 µA
— Maximum standby current: 7 µA (Industrial)
• Ultra low active power
— Typical active current: 2.0 mA @ f = 1 MHz
• Easy memory expansion with CE, and OE features
• Automatic power down when deselected
• CMOS for optimum speed and power
The eight input and output pins (IO through IO ) are placed
in a high impedance state when:
0
7
• Deselected (CE HIGH)
• Outputs are disabled (OE HIGH)
• Write operation is active (CE LOW and WE LOW)
• Available in Pb-free 32-pin TSOP II and 32-pin SOIC
packages
To write to the device, take Chip Enable (CE) and Write Enable
(WE) inputs LOW. Data on the eight IO pins (IO through IO )
0
7
is then written into the location specified on the address pins
(A through A ).
0
18
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing Write Enable (WE) HIGH.
Under these conditions, the contents of the memory location
specified by the address pins appear on the IO pins.
Product Portfolio
Power Dissipation
Speed
Product
Range
V
Range (V)
Operating I (mA)
CC
CC
(ns)
Standby I
(µA)
SB2
f = 1MHz
f = f
max
[3]
[3]
Min
4.5
4.5
Typ
Max
Typ
Max Typ
Max Typ
Max
CY62148ELL TSOP II
CY62148ELL SOIC
Ind’l
5.0
5.0
5.5
5.5
45
55
2
2
2.5
2.5
15
15
20
20
1
1
7
7
Ind’l/Auto-A
Notes
1. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” at http://www.cypress.com.
2. SOIC package is available only in 55 ns speed bin.
3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = V
, T = 25°C.
CC
CC(typ)
A
Cypress Semiconductor Corporation
Document #: 38-05442 Rev. *F
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised March 28, 2007
CY62148E MoBL®
DC Input Voltage
............ –0.5V to 6.0V (V
+ 0.5V)
Maximum Ratings
CCmax
Output Current into Outputs (LOW)............................. 20 mA
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Static Discharge Voltage........................................... > 2001V
(per MIL-STD-883, Method 3015)
Storage Temperature ................................–65°C to + 150°C
Latch-up Current ......................................................>200mA
Ambient Temperature with
Power Applied............................................–55°C to + 125°C
Operating Range
Supply Voltage to Ground
Ambient
[7]
Device
Range
V
CC
Potential.................................–0.5V to 6.0V (V
+ 0.5V)
+ 0.5V)
CCmax
Temperature
DC Voltage Applied to Outputs
CY62148E Ind’l/Auto-A –40°C to +85°C 4.5V to 5.5V
in High-Z State
................–0.5V to 6.0V (V
CCmax
Electrical Characteristics (Over the Operating Range)
45 ns
55 ns
Parameter
Description
Test Conditions
= –1 mA
OH
Unit
[3]
Min Typ
Max
Min Typ
2.4
Max
V
Output HIGH
Voltage
I
2.4
V
OH
V
V
V
Output LOW Voltage I = 2.1 mA
0.4
0.4
V
V
V
OL
IH
IL
OL
Input HIGH Voltage
Input LOW voltage
V
V
= 4.5V to 5.5V
2.2
V
+ 0.5 2.2
V
+ 0.5
CC
CC
CC
CC
= 4.5V to 5.5V For TSOPII
package
–0.5
0.8
[8]
For SOIC
package
–0.5
–1
0.6
I
Input Leakage
Current
GND < V < V
CC
–1
–1
+1
+1
µA
µA
IX
I
I
I
Output Leakage
Current
GND < V < V , Output Disabled
+1
–1
+1
OZ
O
CC
V
Operating
f = f
= 1/t
V
= V
CC(max)
= 0 mA
15
2
20
15
2
20
mA
CC
CC
max
RC
CC
Supply Current
I
OUT
f = 1 MHz
2.5
2.5
CMOS levels
[9]
I
AutomaticCEPower CE > V – 0.2V
1
7
1
7
µA
SB2
CC
CC
down Current —
CMOS Inputs
V
IN
> V – 0.2V or V < 0.2V,
IN
f = 0, V = V
CC
CC(max)
Capacitance (For All Packages)
Parameter
Description
Input Capacitance
Output Capacitance
Test Conditions
Max
10
Unit
C
C
T = 25°C, f = 1 MHz,
pF
pF
IN
OUT
A
V
= V
CC
CC(typ)
10
Notes
5.
V
= –2.0V for pulse durations less than 20 ns for I < 30 mA.
IL(min)
6.
V
= V +0.75V for pulse durations less than 20 ns.
IH(max)
CC
7. Full device AC operation assumes a minimum of 100 µs ramp time from 0 to V (min) and 200 µs wait time after V stabilization.
CC
CC
8. Under DC conditions the device meets a V of 0.8V. However, in dynamic conditions Input LOW Voltage applied to the device must not be higher than 0.6V. This
IL
is applicable to SOIC package only. Refer to AN13470 for details.
9. Only chip enable (CE) must be HIGH at CMOS level to meet the I
spec. Other inputs can be left floating.
SB2
10. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05442 Rev. *F
Page 3 of 10
CY62148E MoBL®
Thermal Resistance [10]
SOIC
TSOP II
Parameter
Description
Test Conditions
Unit
Package Package
Θ
Thermal Resistance
(Junction to Ambient)
Still Air, soldered on a 3 × 4.5 inch,
two-layer printed circuit board
75
10
77
13
°C/W
JA
Θ
Thermal Resistance
(Junction to Case)
°C/W
JC
AC Test Loads and Waveforms
R1
ALL INPUT PULSES
V
CC
3.0V
OUTPUT
90%
10%
90%
10%
R2
GND
Rise Time = 1 V/ns
30 pF
Fall Time = 1 V/ns
INCLUDING
JIG AND
SCOPE
Equivalent to:
THEVENIN EQUIVALENT
R
TH
OUTPUT
V
Parameters
5.0V
1800
990
Unit
Ω
R1
R2
Ω
R
639
Ω
TH
TH
V
1.77
V
Data Retention Characteristics (Over the Operating Range)
Parameter
Description
Conditions
Min Typ
Max Unit
V
V
for Data Retention
2
V
DR
CC
I
Data Retention Current
V
V
= V , CE > V – 0.2V,
Ind’l/Auto-A
1
7
µA
CCDR
CC
DR
CC
> V – 0.2V or V < 0.2V
IN
CC
IN
t
t
Chip Deselect to Data Retention Time
Operation Recovery Time
0
ns
ns
CDR
R
t
RC
Data Retention Waveform
DATA RETENTION MODE
> 2.0V
V
V
CC(min)
V
CC(min)
VCC
CE
DR
t
t
R
CDR
Note
11. Full device operation requires linear V ramp from V to V
> 100 µs or stable at V
> 100 µs.
CC(min)
CC
DR
CC(min)
Document #: 38-05442 Rev. *F
Page 4 of 10
CY62148E MoBL®
Switching Characteristics (Over the Operating Range)
[2]
45 ns
55 ns
Parameter
Read Cycle
Description
Unit
Min
Max
Min
Max
t
t
t
t
t
t
t
t
t
t
t
Read Cycle Time
45
10
55
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RC
Address to Data Valid
45
55
AA
Data Hold from Address Change
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
45
22
55
25
CE LOW to Data Valid
OE LOW to Data Valid
5
10
0
5
10
0
OE LOW to LOW Z
18
18
45
20
20
55
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
CE LOW to Power up
CE HIGH to Power down
PD
Write Cycle
t
t
t
t
t
t
t
t
t
t
Write Cycle Time
45
35
35
0
55
40
40
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WC
CE LOW to Write End
SCE
AW
Address Setup to Write End
Address Hold from Write End
Address Setup to Write Start
HA
0
0
SA
35
25
0
40
25
0
WE Pulse Width
PWE
SD
Data Setup to Write End
Data Hold from Write End
HD
18
20
WE LOW to High-Z
HZWE
LZWE
10
10
WE HIGH to Low-Z
Notes
12. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels
of 0 to 3V, and output loading of the specified I /I as shown in the “AC Test Loads and Waveforms” on page 4.
OL OH
13. At any given temperature and voltage condition, t
is less than t
, t
is less than t
, and t
is less than t
for any given device.
HZCE
LZCE HZOE
LZOE
HZWE
LZWE
14. t
, t
, and t
transitions are measured when the outputs enter a high impedance state.
HZOE HZCE
HZWE
15. The internal write time of the memory is defined by the overlap of WE, CE = V . All signals must be ACTIVE to initiate a write and any of these signals can
IL
terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write.
Document #: 38-05442 Rev. *F
Page 5 of 10
CY62148E MoBL®
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled)
tRC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled)
ADDRESS
CE
t
RC
t
ACE
OE
t
HZOE
t
DOE
t
HZCE
t
LZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA VALID
DATA OUT
t
LZCE
t
PD
ICC
t
V
CC
PU
50%
SUPPLY
CURRENT
50%
ISB
Write Cycle No. 1 (WE Controlled, OE HIGH During Write)
t
WC
ADDRESS
t
SCE
CE
t
t
HA
AW
t
SA
t
PWE
WE
OE
t
t
SD
HD
DATA IO
NOTE
DATA VALID
t
HZOE
Notes:
16. Device is continuously selected. OE, CE = V .
IL
17. WE is HIGH for read cycles.
18. Address valid before or similar to CE transition LOW.
19. Data IO is high impedance if OE = V
.
IH
20. If CE goes HIGH simultaneously with WE HIGH, the output remains in high impedance state.
21. During this period, the IOs are in output state and input signals must not be applied.
Document #: 38-05442 Rev. *F
Page 6 of 10
CY62148E MoBL®
Switching Waveforms (continued)
Write Cycle No. 2 (CE Controlled)
t
WC
ADDRESS
CE
t
SCE
t
SA
t
t
HA
AW
t
PWE
WE
t
t
HD
SD
DATA IO
DATA VALID
Write Cycle No. 3 (WE Controlled, OE LOW)
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
t
SA
t
PWE
WE
t
t
HD
SD
NOTE
DATA VALID
DATA IO
t
t
LZWE
HZWE
Truth Table
CE
H
L
WE
OE
X
IO’s
Mode
Power
X
H
L
High Z
Deselect/Power down
Standby (I
)
SB
L
Data Out
Data In
High Z
Read
Write
Active (I
Active (I
Active (I
)
)
)
CC
CC
CC
L
X
L
H
H
Selected, Outputs Disabled
Document #: 38-05442 Rev. *F
Page 7 of 10
CY62148E MoBL®
Ordering Information
Speed
(ns)
Package
Diagram
Operating
Range
Ordering Code
Package Type
45
CY62148ELL-45ZSXI
CY62148ELL-55SXI
CY62148ELL-55SXA
51-85095 32-pin Thin Small Outline Package II (Pb-free)
51-85081 32-pin Small Outline Integrated Circuit (Pb-free)
51-85081 32-pin Small Outline Integrated Circuit (Pb-free)
Industrial
Industrial
55
55
Automotive-A
Contact your local Cypress sales representative for availability of these parts.
Package Diagrams
Figure 1. 32-pin TSOP II, 51-85095
51-85095-**
Document #: 38-05442 Rev. *F
Page 8 of 10
CY62148E MoBL®
Package Diagrams (continued)
Figure 2. 32-pin (450 MIL) Molded SOIC, 51-85081
16
1
0.546[13.868]
0.566[14.376]
0.440[11.176]
0.450[11.430]
17
32
0.793[20.142]
0.817[20.751]
0.006[0.152]
0.012[0.304]
0.101[2.565]
0.111[2.819]
0.118[2.997]
MAX.
0.004[0.102]
0.047[1.193]
0.063[1.600]
0.004[0.102]
0.050[1.270]
0.023[0.584]
0.039[0.990]
MIN.
BSC.
0.014[0.355]
0.020[0.508]
SEATING PLANE
51-85081-*B
MoBL is a registered trademark, and More Battery Life is a trademark of Cypress Semiconductor. All product and company names
mentioned in this document are the trademarks of their respective holders.
Document #: 38-05442 Rev. *F
Page 9 of 10
© Cypress Semiconductor Corporation, 2006-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for
the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended
to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY62148E MoBL®
Document History Page
®
Document Title: CY62148E MoBL , 4-Mbit (512K x 8) Static RAM
Document Number: 38-05442
Issue
Date
Orig. of
Change
REV.
ECN NO.
Description of Change
**
201580 01/08/04
249276 See ECN
AJU
SYT
New Data Sheet
*A
Changed from Advance Information to Preliminary
Moved Product Portfolio to Page 2
Added RTSOP II and Removed FBGA Package
Changed V stabilization time in footnote #7 from 100 µs to 200 µs
CC
Changed I
from 2.0 µA to 2.5 µA
CCDR
Changed typo in Data Retention Characteristics(t ) from 100 µs to t ns
R
RC
Changed t
Changed t
from 6 ns to 10 ns for both 35 ns and 45 ns Speed Bin
OHA
, t
from 12 to 15 ns for 35 ns Speed Bin and 15 to 18 ns for 45
HZOE HZWE
ns Speed Bin
Changed t
Bin
from 25 to 30 ns for 35 ns Speed Bin and 40 to 35 ns for 45 ns Speed
SCE
Changed t
Speed Bin
from 12 to18 ns for 35 ns Speed Bin and 15 to 22 ns for 45 ns
HZCE
Changed t from 15 to 18 ns for 35 ns Speed Bin and 20 to 22 ns for
SD
45 ns Speed Bin
Changed t
from 15 to 18 ns for 35 ns Speed Bin
DOE
Corrected typo in Package Name
Changed Ordering Information to include Pb-Free Packages
*B
414820 See ECN
ZSD
Changed from Preliminary to Final
Changed the address of Cypress Semiconductor Corporation on Page #1 from
“3901 North First Street” to “198 Champion Court”
Removed 35ns Speed Bin
Removed “L” version of CY62148E
Changed I (Typ) value from 1.5 mA to 2 mA at f=1 MHz
CC
Changed I (Max) value from 2 mA to 2.5 mA at f=1 MHz
CC
Changed I (Typ) value from 12 mA to 15 mA at f=f
CC
max
Removed I
Changed I
Modified footnote #4 to include current limit
spec from the Electrical characteristics table
Typ values from 0.7 µA to 1 µA and Max values from 2.5 µA to 7 µA
SB1
SB2
Removed redundant footnote on DNU pins
Changed the AC testload capacitance from 100 pF to 30 pF on page #4
Changed test load parameters R1, R2, R and V from 1838 Ω, 994 Ω,
TH
TH
645 Ω and 1.75V to 1800 Ω, 990 Ω, 639 Ω and 1.77V
Changed I from 2.5 µA to 7 µA
CCDR
Added I
typical value
CCDR
Changed t
Changed t
Changed t
Changed t
from 3 ns to 5 ns
LZOE
LZCE
HZCE
PWE
and t
from 6 ns to 10 ns
LZWE
from 22 ns to 18 ns
from 30 ns to 35 ns
Changed t from 22 ns to 25 ns
SD
Updated the ordering information table and replaced Package Name column with
Package Diagram
*C
464503 See ECN
NXR
Included Automotive Range in product offering
Updated the Ordering Information
*D
*E
485639 See ECN
833080 See ECN
VKN
VKN
Corrected the operating range to 4.5V - 5.5V on page# 3
Added footnote #8
Added V spec for SOIC package
IL
*F
890962 See ECN
VKN
Added Automotive-A part and its related information
Removed Automotive-E part and its related information
Added footnote #2 related to SOIC package
Added footnote #9 related to I
SB2
Added AC values for 55 ns Industrial-SOIC range
Updated Ordering Information table
Document #: 38-05442 Rev. *F
Page 10 of 10
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