Texas Instruments TMS320 User Manual
TMS320 SECOND-GENERATION  
DIGITAL SIGNAL PROCESSORS  
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990  
†
68-Pin GB Package  
(Top View)  
•
•
•
80-ns Instruction Cycle Time  
1
2
3
4
5
6
7
8
9 10 11  
544 Words of On-Chip Data RAM  
4K Words of On-Chip Secure Program  
EPROM (TMS320E25)  
A
B
C
D
E
F
•
4K Words of On-Chip Program ROM  
(TMS320C25)  
•
•
•
•
128K Words of Data/Program Space  
32-Bit ALU/Accumulator  
G
H
J
16 × 16-Bit Multiplier With a 32-Bit Product  
Block Moves for Data/Program  
Management  
K
L
•
Repeat Instructions for Efficient Use of  
Program Space  
†
68-Pin FN and FZ Packages  
(Top View)  
•
•
Serial Port for Direct Codec Interface  
Synchronization Input for Synchronous  
Multiprocessor Configurations  
•
Wait States for Communication to Slow  
Off-Chip Memories/Peripherals  
9
8
7
6
5
4
3
2
1
68 67 66 65 64 63 62 61  
60  
59  
V
IACK  
MSC  
10  
SS  
D7  
D6  
D5  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
58 CLKOUT1  
57 CLKOUT2  
56 XF  
•
•
•
On-Chip Timer for Control Operations  
Single 5-V Supply  
D4  
D3  
D2  
D1  
D0  
55 HOLDA  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
DX  
Packaging: 68-Pin PGA, PLCC, and  
CER-QUAD  
FSX  
X2 CLKIN  
X1  
SYNC  
INT0  
INT1  
INT2  
BR  
•
68-to-28 Pin Conversion Adapter Socket for  
EPROM Programming  
STRB  
R/W  
PS  
IS  
DS  
V
DR  
CC  
•
•
Commercial and Military Versions Available  
FSR  
NMOS Technology:  
— TMS32020 . . . . . . . . . 200-ns cycle time  
A0 26  
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43  
V
SS  
• CMOS Technology:  
— TMS320C25 . . . . . . . . 100-ns cycle time  
— TMS320E25 . . . . . . . . 100-ns cycle time  
— TMS320C25-50 . . . . . . 80-ns cycle time  
description  
This data sheet provides complete design documentation for the second-generation devices of the TMS320  
family. This facilitates the selection of the devices best suited for user applications by providing all specifications  
and special features for each TMS320 member. This data sheet is divided into four major sections: architecture,  
electrical specifications (NMOS and CMOS), timing diagrams, and mechanical data. In each of these sections,  
generic information is presented first, followed by specific device information. An index is provided for quick  
reference to specific information about a device.  
ADVANCE INFORMATION concerns new products in the  
Copyright 1991, Texas Instruments Incorporated  
sampling or preproduction phase of development.  
Characteristic data and other specifications are subject to  
change without notice.  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001  
1
TMS320 SECOND-GENERATION  
DEVICES  
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990  
description  
The TMS320 family of 16/32-bit single-chip digital signal processors combines the flexibility of a high-speed  
controller with the numerical capability of an array processor, thereby offering an inexpensive alternative to  
multichip bit-slice processors. The highly paralleled architecture and efficient instruction set provide speed and  
flexibility to produce a MOS microprocessor family that is capable of executing more than 12.5 MIPS (million  
instructions per section). The TMS320 family optimizes speed by implementing functions in hardware that other  
processors implement through microcode or software. This hardware-intensive approach provides the design  
engineer with processing power previously unavailable on a single chip.  
The TMS320 family consists of three generations of digital signal processors. The first generation contains the  
TMS32010 and its spinoffs. The second generation includes the TMS32020, TMS320C25, and TMS320E25,  
which are described in this data sheet. The TMS320C30 is a floating-point DSP device designed for even higher  
performance. Many features are common among the TMS320 processors. Specific features are added in each  
processor to provide different cost/performance tradeoffs. Software compatibility is maintained throughout the  
family to protect the user’s investment in architecture. Each processor has software and hardware tools to  
facilitate rapid design.  
introduction  
The TMS32010, the first NMOS digital signal processor in the TMS320 family, was introduced in 1983. Its  
powerful instruction set, inherent flexibility, high-speed number-crunching capabilities, and innovative  
architecture have made this high-performance, cost-effective processor the ideal solution to many  
telecommunications, computer, commercial, industrial, and military applications. Since that time, the  
TMS320C10, a low-power CMOS version of the industry-standard TMS32010, and other spinoff devices have  
been added to the first generation of the TMS320 family.  
The second generation of the TMS320 family (referred to as TMS320C2x) includes four members, the  
TMS32020, TMS320C25, TMS320C25-50, and TMS320E25. The architecture of these devices is based upon  
that of the TMS32010.  
The TMS32020, processed in NMOS technology, is source-code compatible with he TMS32010 and in many  
applications is capable of two times the throughput of the first-generation devices. Its enhanced instruction set  
(109 instructions), large on-chip data memory (544 words), large memory spaces, on-chip serial port, and  
hardware timer make the TMS32020 a powerful addition to the TMS320 family.  
TheTMS320C25isthesecondmemberoftheTMS320secondgeneration. ItisprocessedinCMOStechnology,  
is capable of an instruction cycle time of 100 ns, and is pin-for-pin and object-code compatible with the  
TMS32020. The TMS320C25’s enhanced feature set greatly increases the functionality of the device over the  
TMS32020. Enhancements included 24 additional instructions (133 total), eight auxiliary registers, an  
eight-level hardware stack, 4K words of on-chip program ROM, a bit-reversed indexed-addressing mode, and  
the low-power dissipation inherent to the CMOS process. An extended-temperature range version  
(TMS320C25GBA) is also available.  
The TMS320C25-50 is a high-speed version of the TMS320C25. It is capable of an instruction cycle time of less  
than80ns. Itisarchitecturallyidenticaltotheoriginal40-MHzversionoftheTMS320C25and, thus, ispin-for-pin  
and object-code compatible with the TMS320C25.  
The TMS320E25 is identical to the TMS320C25, with the exception that the on-chip 4K-word program ROM is  
replaced with a 4K-word on-chip program EPROM. On-chip EPROM allows realtime code development and  
modification for immediate evaluation of system performance.  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001  
3
TMS320 SECOND-GENERATION  
DEVICES  
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990  
Key Features: TMS32020  
+5 V  
GND  
•
•
•
200-ns Instruction Cycle Time  
544 Words of On-Chip Data RAM  
Interrupts  
256-Word 288-Word  
128K Words of Total Data/Program  
Memory Space  
Data (16)  
Data/Prog  
RAM  
Data  
RAM  
Multi-  
•
Wait States for Communication to Slower Off-Chip  
Memories  
Processor  
Multiplier  
Interface  
Serial  
•
•
•
•
•
•
Source Code Compatible With the TMS320C1x  
Single-Cycle Multiply/Accumulate Instructions  
Repeat Instructions  
32-BIT ALU/ACC  
Shifters  
Interface  
Address (16)  
Timer  
Global Data Memory Interface  
Block Moves for Data/Program Management  
Five Auxiliary Registers With Dedicated  
Arithmetic Unit  
•
•
•
•
On-Chip Clock Generator  
Single 5-V Supply  
•
Serial Port for Multiprocessing or Interfacing  
to Codecs, Serial Analog-to-Digital  
Converters, etc.  
NMOS Technology  
68-Pin Grid Array (PGA) Package  
Key Features: TMS320C25, TMS320C25-50, TMS320E25  
+5 V  
GND  
• 80-ns Instruction Cycle Time (TMS320C25-50)  
• 100-ns Instruction Cycle Time (TMS320C25)  
• 4K Words of On-Chip Secure Program EPROM  
(TMS320E25)  
256-Word 288-Word  
Data/Prog  
RAM  
Interrupts  
MP/MC  
Data (16)  
Data  
RAM  
• 4K Words of On-Chip Program  
ROM (TMS320C25)  
Multi-  
Processor  
4K-Words  
ROM/EPROM  
• 544 Words of On-Chip RAM  
• 128K Words of Total Program/Data  
Interface  
Multiplier  
Memory Space  
Serial  
• Wait States for Communications to  
32-Bit ALU/ACC  
Shifters  
Interface  
Slower Off-Chip Memories  
• Object-Code Compatible With the TMS32020  
Address (16)  
Timer  
• Source-Code Compatible With TMS320C1x  
• 24 Additional Instructions to Support  
Adaptive Filtering, FFTs, and  
• On-Chip Clock Generator  
• Single 5-V Supply  
Extended-Precision Arithmetic  
• Block Moves for Data/Program Management  
• Single-Cycle Multiply/Accumulate Instructions  
• Internal Security Mechanism (TMS320E25)  
• 68-to-28 Pin Conversion Adapter Socket  
• CMOS Technology  
• Eight Auxiliary Registers With Dedicated  
Arithmetic Unit  
• Bit-Reversed Indexed-Addressing Mode for  
• 68-Pin Grid Array (PGA) Package  
Radix-2 FFTS  
(TMS320C25)  
• Double-Buffered Serial Port  
• 68-Lead Plastic Leaded Chip Carrier (PLCC)  
Package (TMS320C25, TMS320C25-50)  
• 68-Lead CER-QUAD Package (TMS320E25)  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001  
4
TMS320 SECOND-GENERATION  
DEVICES  
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990  
Table 1 provides an overview of the second-generation TMS320 processors with comparisons of memory, I/O,  
cycle timing, power, package type, technology, and military support. For specific availability, contact the nearest  
TI Field Sales Office.  
Table 1. TMS320 Second-Generation Device Overview  
MEMORY  
PACKAGE  
TYPE  
CYCLE  
TIME  
(ns)  
TYP  
POWER  
(mW)  
†
I/O  
ON-CHIP  
OFF-CHIP  
DEVICE  
TIMER  
RAM ROM/EPROM PROG DATA  
SER  
YES  
YES  
YES  
YES  
PAR  
DMA  
YES  
CON  
CON  
CON  
PGA PLCC CER-QUAD  
‡
(NMOS)  
(CMOS)  
(CMOS)  
(CMOS)  
544  
544  
544  
544  
—
4K  
4K  
4K  
64K  
64K  
64K  
64K  
64K  
64K  
64K  
64K  
YES  
YES  
YES  
YES  
200  
100  
80  
1250  
500  
500  
500  
68  
68  
—
—
—
68  
68  
—
—
—
—
68  
TMS32020  
16 × 16  
16 × 16  
16 × 16  
16 × 16  
‡
TMS320C25  
§
TMS320C25-50  
§
TMS320E25  
100  
†
‡
§
SER = serial; PAR = parallel; DMA = direct memory access; CON = concurrent DMA.  
Military version available; contact nearest TI Field Sales Office for availability.  
Military version planned; contact nearest TI Field Sales Office for details.  
architecture  
The TMS320 family utilizes a modified Harvard architecture for speed and flexibility. In a strict Harvard  
architecture, program and data memory lie in two separate spaces, permitting a full overlap of instruction fetch  
and execution. The TMS320 family’s modification of the Harvard architecture allows transfers between program  
and data spaces, thereby increasing the flexibility of the device. This modification permits coefficients stored  
in program memory to be read into the RAM, eliminating the need for a separate coefficient ROM. It also makes  
available immediate instructions and subroutines based on computed values.  
Increased throughput on the TMS320C2x devices for many DSP applications is accomplished by means of  
single-cycle multiply/accumulate instructions with a data move option, up to eight auxiliary registers with a  
dedicated arithmetic unit, and faster I/O necessary for data-intensive signal processing.  
The architectural design of the TMS320C2x emphasizes overall speed, communication, and flexibility in  
processor configuration. Control signals and instructions provide floating-point support, block-memory  
transfers, communication to slower off-chip devices, and multiprocessing implementations.  
32-bit ALU/accumulator  
The 32-bit Arithmetic Logic Unit (ALU) and accumulator perform a wide range of arithmetic and logical  
instructions, the majority of which execute in a single clock cycle. The ALU executes a variety of branch  
instructions dependent on the status of the ALU or a single bit in a word. These instructions provide the following  
capabilities:  
•
•
•
Branch to an address specified by the accumulator  
Normalize fixed-point numbers contained in the accumulator  
Test a specified bit of a word in data memory  
One input to the ALU is always provided from the accumulator, and the other input may be provided from the  
Product Register (PR) of the multiplier or the input scaling shifter which has fetched data from the RAM on the  
databus. AftertheALUhasperformedthearithmeticorlogicaloperations, theresultisstoredintheaccumulator.  
The 32-bit accumulator is split into two 16-bit segments for storage in data memory. Additional shifters at the  
output of the accumulator perform shifts while the data is being transferred to the data bus for storage. The  
contents of the accumulator remain unchanged.  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001  
5
TMS320 SECOND-GENERATION  
DEVICES  
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990  
functional block diagram (TMS320C2x)  
SYNC  
IS  
DS  
Program Bus  
16  
PS  
16  
16  
16  
PFC(16)  
QIR(16)  
IR(16)  
R/W  
STRB  
READY  
BR  
16  
STO(16)  
ST1(16)  
RPTC(8)  
IFR(6)  
MUX  
16  
16  
XF  
16  
HOLD  
HOLDA  
MSC  
BIO  
MCS(16)  
PC(16)  
DR  
CLKR  
FSR  
DX  
CLKX  
FSX  
RS  
IACK  
16  
16  
16  
Address  
Stack  
16  
16  
16  
MP/MC  
(8 x 16)  
3
RSR(16)  
XSR(16)  
DRR(16)  
DXR(16)  
TIM(16)  
PRD(16)  
IMR(6)  
Program  
ROM/  
EPROM  
(4096 × 16)  
Instruction  
16  
INT(2-0)  
16  
16  
16  
A15-A0  
D15-D0  
16  
16  
16  
6
16  
16  
8
GREG(8)  
16  
16  
16  
Program Bus  
Data Bus  
16  
16  
16  
16  
16  
16  
16  
9
3
AR0(16)  
AR1(16)  
AR2(16)  
AR3(16)  
AR4(16)  
AR5(16)  
AR6(16)  
AR7(16)  
TR(16)  
7 LSB  
From IR  
MUX  
3
ARP(3)  
DP(9)  
16  
Multiplier  
Shifter(0-16)  
32  
9
3
PR(32)  
32  
16  
ARB(3)  
Shifter(-6, 0, 1, 4)  
32  
16  
16  
16  
MUX  
3
ARAU(16)  
MUX  
32  
16  
MUX  
16  
MUX  
16  
32  
ALU(32)  
32  
Block B2  
DATA/PROG  
(32 × 16)  
Data RAM  
Block B1  
(256 × 16)  
RAM (256 × 16)  
C
Block B0  
ACCH(16)  
32  
ACCL(16)  
16  
MUX  
16  
†
Shifters (0-7)  
16  
16  
16  
Data Bus  
LEGEND:  
ACCH  
ACCL  
ALU  
ARAU  
ARB  
ARP  
DP  
=
Accumulator high  
Accumulator low  
Arithmetic logic unit  
Auxiliary register arithmetic unitMCS  
Auxiliary register pointer buffer  
Auxiliary register pointer  
Data memory page pointer  
Serial port data receive registerTIM  
Serial port data transmit register  
IFR  
IMR  
IR  
=
=
=
Interrupt flag register  
Interrupt mask register  
Instruction register  
GREG  
Queue instruction register  
Product register  
Period register for timer  
ST0, ST1  
PC  
=
=
=
Program counter  
Prefetch counter  
Repeat instruction counter  
=
=
=
=
=
=
=
=
PFC  
RPTC  
=
RSR  
XSR  
AR0-AR7  
=
Microcall stack  
Global memory allocation register  
QIR  
PR  
PRD  
=
=
=
=
=
=
=
=
=
Serial port receive shift register  
Serial port transmit shift register  
Auxiliary registers  
Status registers  
Carry bit  
DRR  
DXR  
Timer  
Temporary register  
TR  
=
C
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001  
6
TMS320 SECOND-GENERATION  
DEVICES  
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990  
scaling shifter  
The TMS320C2x scaling shifter has 16-bit input connected to the data bus and a 32-bit output connected to the  
ALU. The scaling shifter produces a left shift of 0 to 16 bits on the input data, as programmed in the instruction.  
The LSBs of the output are filled with zeroes, and the MSBs may be either filled with zeroes or sign-extended,  
depending upon the status programmed into the SXM (sign-extension mode) bit of status register ST1.  
16 × 16-bit parallel multiplier  
The 16 × 16-bit hardware multiplier is capable of computing a signed or unsigned 32-bit product in a single  
machine cycle. The multiplier has the following two associated registers.  
•
•
A 16-bit Temporary Register (TR) that holds one of the operands for the multiplier, and  
A 32-bit Product Register (PR) that holds the product.  
Incorporated into the instruction set are single-cycle multiply/accumulate instructions that allow both operands  
to be processed simultaneously. The data for these operations may reside anywhere in internal or external  
memory, and can be transferred to the multiplier each cycle via the program and data buses.  
Four product shift modes are available at the Product Register (PR) output that are useful when performing  
multiply/accumulate operations, fractional arithmetic, or justifying fractional products.  
timer  
The TMS320C2x provides a memory-mapped 16-bit timer for control operations. The on-chip timer (TIM)  
register is a down counter that is continuously clocked by CLKOUT1 on the TMS320C25. The timer is clocked  
byCLKOUT1/4ontheTMS32020. Atimerinterrupt(TINT)isgeneratedeverytimethetimerdecrementstozero.  
The timer is reloaded with the value contained in the period (PRD) register within the next cycle after it reaches  
zero so that interrupts may be programmed to occur at regular intervals of PRD + 1 cycles of CLKOUT 1 on the  
TMS320C25 or 4 × PRD × CLKOUT 1 cycles on the TMS32020.  
memory control  
The TMS320C2x provides a total of 544 16-bit words of on-chip data RAM, divided into three separate blocks  
(B0, B1, and B2). Of the 544 words, 288 words (blocks B1 and B2) are always data memory, and 256 words  
(block B0) are programmable as either data or program memory. A data memory size of 544 words allows the  
TMS320C2x to handle a data array of 512 words (256 words if on-chip RAM is used for program memory), while  
still leaving 32 locations for intermediate storage. When using block B0 as program memory, instructions can  
be downloaded from external program memory into on-chip RAM and then executed.  
When using on-chip program RAM, ROM, EPROM, or high-speed external program memory, the TMS320C2x  
runs at full speed without wait states. However, the READY line can be used to interface the TMS320C2x to  
slower, less-expensive external memory. Downloading programs from slow off-chip memory to on-chip program  
RAM speeds processing while cutting system costs.  
The TMS320C2x provides three separate address spaces for program memory, data memory, and I/O. The  
on-chip memory is mapped into either the 64K-word data memory or program memory space, depending upon  
the memory configuration (see Figure 1). The CNFD (configure block B0 as data memory) and CNFP (configure  
block B0 as program memory) instructions allow dynamic configuration of the memory maps through software.  
Regardless of the configuration, the user may still execute from external program memory.  
The TMS320C2x has six registers that are mapped into the data memory space: a serial port data receive  
register, serial port data transmit register, timer register, period register, interrupt mask register, and global  
memory allocation register.  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001  
7
TMS320 SECOND-GENERATION  
DEVICES  
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990  
Program  
Program  
Data  
0(0000h)  
Interrupts  
and Reserved  
(External)  
31(001Fh)  
0(0000h)  
0(0000h)  
Interrupts  
and Reserved  
(On-Chip  
On-Chip  
Memory-Mapped  
Registers  
ROM/EPROM)  
5(0005h)  
6(0006h)  
31(001Fh)  
32(0020h)  
32(0020h)  
Page 0  
Reserved  
On-Chip  
ROM/EPROM  
95(005Fh)  
96(0060h)  
4015(0FAFh)  
4016(0FB0h)  
On-Chip  
Block B2  
127(007Fh)  
128(0080h)  
Reserved  
4095(0FFFh)  
4096(1000h)  
Pages 1-3  
Pages 4-5  
Reserved  
511(01FFh)  
512(0200h)  
External  
On-Chip  
Block B0  
767(02FFh)  
768(0300h)  
On-Chip  
Block B1  
Pages 6 -7  
External  
1023(03FFh)  
1024(0400h)  
External  
Pages 8 -511  
65,535(0FFFFh)  
65,535(0FFFFh)  
65,535(FFFFh)  
If MP/MC = 1  
If MP/MC = 0  
(Microcomputer Mode on TMS320C25)  
(Microprocessor Mode)  
(a) Memory Maps After a CNFD Instruction  
Program  
Program  
Data  
0(0000h)  
0(0000h)  
0(0000h)  
Interrupts  
and Reserved  
(On-Chip  
Interrupts  
and Reserved  
(External)  
On-Chip  
Memory-Mapped  
Registers  
ROM/EPROM)  
31(001Fh)  
32(0020h)  
5(0005h)  
6(0006h)  
31(001Fh)  
32(0020h)  
On-Chip  
ROM/EPROM  
Page 0  
Reserved  
95(005Fh)  
96(0060h)  
4015(0FAFh)  
4016(0FB0h)  
On-Chip  
Block B2  
Reserved  
4095(0FFFh)  
4096(1000h)  
127(007Fh)  
128(0080h)  
Reserved  
Pages 1-3  
Pages 4-5  
511(01FFh)  
512(0200h)  
External  
Does Not  
Exist  
767(02FFh)  
768(0300h)  
External  
On-Chip  
Block B1  
Pages 6 -7  
1023(03FFh)  
1024(0400h)  
65,279(0FEFFh)  
65,280(0FF00h)  
65,279(0FEFFh)  
65,280(0FF00h)  
External  
Pages 8 -511  
On-Chip  
Block B0  
On-Chip  
Block B0  
65,535(0FFFFh)  
65,535(0FFFFh)  
65,535(0FFFFh)  
If MP/MC = 1  
(Microprocessor Mode)  
If MP/MC = 0  
(Microcomputer Mode on TMS320C25)  
(b) Memory Maps After a CNFP Instruction  
Figure 1. Memory Maps  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001  
8
TMS320 SECOND-GENERATION  
DEVICES  
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990  
interrupts and subroutines  
The TMS320C2x has three external maskable user interrupts INT2-INT0, available for external devices that  
interrupt the processor. Internal interrupts are generated by the serial port (RINT and XINT), by the timer (TINT),  
and by the software interrupt (TRAP) instruction. Interrupts are prioritized with reset (RS) having the highest  
priority and the serial port transmit interrupt (XINT) having the lowest priority. All interrupt locations are on  
two-word boundaries so that branch instructions can be accommodated in those locations if desired.  
A built-in mechanism protects multicycle instructions from interrupts. If an interrupt occurs during a multicycle  
instruction, the interrupt is not processed until the instruction is completed. This mechanism applies to  
instructions that are repeated and to instructions that become multicycle due to the READY signal.  
external interface  
The TMS320C2x supports a wide range of system interfacing requirements. Program, data, and I/O address  
spaces provide interface to memory and I/O, thus maximizing system throughput. I/O design is simplified by  
having I/O treated the same way as memory. I/O devices are mapped into the I/O address space using the  
processor’s external address and data buses in the same manner as memory-mapped devices. Interface to  
memory and I/O devices of varying speeds is accomplished by using the READY line. When transactions are  
made with slower devices, the TMS320C2x processor waits until the other device completes its function and  
signals the processor via the READY line. Then, the TMS320C2x continues execution.  
A full-duplex serial port provides communication with serial devices, such as codecs, serial A/D converters, and  
other serial systems. The interface signals are compatible with codecs and many other serial devices with a  
minimum of external hardware. The serial port may also be used for intercommunication between processors  
in multiprocessing applications.  
Theserialporthastwomemory-mappedregisters:thedatatransmitregister(DXR)andthedatareceiveregister  
(DRR). Both registers operate in either the byte mode or 16-bit word mode, and may be accessed in the same  
manner as any other data memory location. Each register has an external clock, a framing synchronization  
pulse, and associated shift registers. One method of multiprocessing may be implemented by programming one  
devicetotransmitwhiletheothersareinthereceivemode. TheserialportontheTMS320C25isdouble-buffered  
and fully static.  
multiprocessing  
The flexibility of the TMS320C2x allows configurations to satisfy a wide range of system requirements and can  
be used as follows:  
•
•
•
•
A standalone processor  
A multiprocessor with devices in parallel  
A slave/host multiprocessor with global memory space  
A peripheral processor interfaced via processor-controlled signals to another device.  
For multiprocessing applications, the TMS320C2x has the capability of allocating global data memory space  
and communicating with that space via the BR (bus request) and READY control signals. Global memory is data  
memory shared by more than one processor. Global data memory access must be arbitrated. The 8-bit  
memory-mapped GREG (global memory allocation register) specifies part of the TMS320C2x’s data memory  
as global external memory. The contents of the register determine the size of the global memory space. If the  
current instruction addresses an operand within that space, BR is asserted to request control of the bus. The  
length of the memory cycle is controlled by the READY line.  
The TMS320C2x supports DMA (direct memory access) to its external program/data memory using the HOLD  
and HOLDA signals. Another processor can take complete control of the TMS320C2x’s external memory by  
asserting HOLD low. This causes the TMS320C2x to place its address data and control lines in a  
high-impedance state, and assert HOLDA. On the TMS320C2x, program execution from on-chip ROM may  
proceed concurrently when the device is in the hold mode.  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001  
9
TMS320 SECOND-GENERATION  
DEVICES  
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990  
instruction set  
The TMS320C2x microprocessor implements a comprehensive instruction set that supports both  
numeric-intensive signal processing operations as well as general-purpose applications, such as  
multiprocessing and high-speed control. The TMS32020 source code is upward-compatible with TMS320C25  
source code. TMS32020 object code runs directly on the TMS320C25.  
For maximum throughput, the next instruction is prefetched while the current one is being executed. Since the  
same data lines are used to communicate to external data/program or I/O space, the number of cycles may vary  
depending upon whether the next data operand fetch is from internal or external memory. Highest throughput  
is achieved by maintaining data memory on-chip and using either internal or fast external program memory.  
addressing modes  
The TMS320C2x instruction set provides three memory addressing modes: direct, indirect, and immediate  
addressing.  
Both direct and indirect addressing can be used to access data memory. In direct addressing, seven bits of the  
instruction word are concatenated with the nine bits of the data memory page pointer to form the 16-bit data  
memory address. Indirect addressing accesses data memory through the auxiliary registers. In immediate  
addressing, the data is based on a portion of the instruction word(s).  
In direct memory addressing, the instruction word contains the lower seven bits of the data memory address.  
This field is concatenated with the nine bits of the data memory page pointer to form the full 16-bit address. Thus,  
memory is paged in the direct addressing mode with a total of 512 pages, each page containing 128 words.  
Up to eight auxiliary registers (AR0-AR7) provide flexible and powerful indirect addressing (five on the  
TMS32020, eight on the TMS320C25). To select a specific auxiliary register, the Auxiliary Register Pointer  
(ARP) is loaded with a value from 0 to 7 for AR0 through AR7, respectively.  
Thereareseventypesofindirectaddressing:auto-incrementorauto-decrement, post-indexingbyeitheradding  
or subtracting the contents of AR0, single indirect addressing with no increment or decrement, and bit-reversal  
addressing (used in FFTs on the TMS320C25 only) with increment or decrement. All operations are performed  
on the current auxiliary register in the same cycle as the original instruction, following which the current auxiliary  
register and ARP may be modified.  
repeat feature  
A repeat feature, used with instructions such as multiply/accumulates, block moves, I/O transfers, and table  
read/writes, allows a single instruction to be performed up to 256 times. The repeat counter (RPTC) is loaded  
with either a data memory value (RPT instruction) or an immediate value (RPTK instruction). The value of this  
operand is one less than the number of times that the next instruction is executed. Those instructions that are  
normally multicycle are pipelined when using the repeat feature, and effectively become single-cycle  
instructions.  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001  
10  
TMS320 SECOND-GENERATION  
DEVICES  
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990  
instruction set summary  
Table 2 lists the symbols and abbreviations used in Table 3, the TMS320C25 instruction set summary. Table 3  
consists primarily of single-cycle, single-word instructions. Infrequently used branch, I/O, and CALL instructions  
are multicycle. The instruction set summary is arranged according to function and alphabetized within each  
†
functional grouping. The symbol ( ) indicates those instructions that are not included in the TMS320C1x  
‡
instruction set. The symbol ( ) indicates instructions that are not included in the TMS32020 instruction set.  
Table 2. Instruction Symbols  
SYMBOL  
DEFINITION  
4-bit field specifying a bit code  
2-bit field specifying compare mode  
Data memory address field  
B
CM  
D
FO  
I
Format status bit  
Addressing mode bit  
K
Immediate operand field  
PA  
Portaddress(PA0throughPA15arepredefinedassemblersymbols  
equal to 0 through 15, respectively.)  
2-bit field specifying P register output shift code  
3-bit operand field specifying auxiliary register  
4-bit left-shift code  
PM  
AR  
S
X
3-bit accumulator left-shift field  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001  
11  
TMS320C25  
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990  
Table 3. TMS320C25 Instruction Set Summary  
ACCUMULATOR MEMORY REFERENCE INSTRUCTIONS  
INSTRUCTION BIT CODE  
NO.  
WORDS  
MNEMONIC  
DESCRIPTION  
15 14 13 12 11 10  
9
8
7
0
I
6
5
4
3
1
2
1
0
ABS  
ADD  
Absolute value of accumulator  
Add to accumulator with shift  
Add to accumulator with carry  
Add to high accumulator  
1
1
1
1
1
1
0
0
0
1
1
0
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
1
0
1
1
D
D
S
‡
ADDC  
0
1
1
0
0
1
1
0
0
1
0
0
I
ADDH  
I
D
‡
ADDK  
ADDS  
Add to accumulator short immediate  
K
Add to low accumulator with sign  
extension suppressed  
1
1
0
0
1
1
0
0
0
0
1
1
0
0
0
1
1
0
I
I
D
D
Add to accumulator with shift specified by  
T register  
ADDT  
†
S
ADLK  
Add to accumulator long immediate with shift  
AND with accumulator  
2
1
2
1
1
1
1
0
1
1
0
1
1
1
1
1
0
1
0
0
0
0
1
0
1
0
1
0
0
0
0
I
0
0
0
0
D
0
0
0
1
0
AND  
1
1
1
1
1
1
0
0
†
†
ANDK  
CMPL  
LAC  
AND immediate with accumulator with shift  
Complement accumulator  
0
0
I
0
0
0
1
0
0
1
1
0
1
0
1
S
S
Load accumulator with shift  
D
LACK  
Load accumulator immediate short  
1
0
0
0
1
1
0
0
K
Load accumulator with shift specified by  
T register  
†
LACT  
1
0
1
0
0
I
D
†
LALK  
Load accumulator long immediate with shift  
Negate accumulator  
2
1
1
1
2
1
1
1
1
1
1
1
0
1
1
1
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
0
0
0
1
0
0
0
0
0
0
1
I
0
0
X
0
1
X
0
0
X
0
0
0
0
0
0
0
1
1
1
1
0
S
S
†
NEG  
1
1
1
1
1
1
1
1
0
0
0
1
†
NORM  
OR  
Normalize contents of accumulator  
OR with accumulator  
D
0
†
ORK  
OR immediate with accumulator with shift  
Rotate accumulator left  
0
0
0
I
0
0
0
0
1
1
0
1
1
1
1
1
0
0
0
1
0
1
‡
ROL  
1
1
1
0
1
1
1
1
0
0
0
0
‡
ROR  
Rotate accumulator right  
SACH  
SACL  
Store high accumulator with shift  
Store low-order accumulator with shift  
X
X
D
D
I
Subtract from accumulator long immediate  
with shift  
SBLK†  
2
1
1
0
1
0
0
0
0
0
0
1
1
S
S
†
SFL  
Shift accumulator left  
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
0
1
1
1
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
1
1
0
0
0
0
I
0
0
0
0
1
1
1
1
0
0
0
0
0
1
†
SFR  
Shift accumulator right  
SUB  
Subtract from accumulator with shift  
Subtract from accumulator with borrow  
Conditional subtract  
D
D
D
D
‡
SUBB  
1
0
0
1
1
1
1
1
1
1
0
0
1
1
0
1
I
SUBC  
SUBH  
I
Subtract from high accumulator  
Subtract from accumulator short immediate  
I
‡
SUBK  
K
Subtract from low accumulator with sign  
extension suppressed  
SUBS  
1
0
1
0
0
0
1
0
1
I
D
†
‡
These instructions are not included in the TMS320C1x instruction set.  
These instructions are not included in the TMS32020 instruction set.  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001  
12  
TMS320C25  
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990  
Table 3. TMS320C25 Instruction Set Summary (continued)  
ACCUMULATOR MEMORY REFERENCE INSTRUCTIONS  
INSTRUCTION BIT CODE  
NO.  
WORDS  
MNEMONIC  
DESCRIPTION  
15 14 13 12 11 10  
9
8
7
6
5
4
3
2
1
0
Subtract from accumulator with shift specified by  
T register  
†
SUBT  
1
1
2
0
0
1
1
1
1
0
0
0
0
0
1
0
1
1
1
1
0
I
D
XOR  
Exclusive-OR with accumulator  
0
0
I
D
0
Exclusive-OR immediate with accumulator with  
shift  
†
XORK  
0
0
0
0
0
0
0
1
0
1
0
0
0
S
ZAC  
Zero accumulator  
1
1
1
0
1
1
0
0
0
0
1
0
0
0
1
0
0
0
0
I
0
ZALH  
Zero low accumulator and load high accumulator  
D
Zero low accumulator and load high accumulator  
with rounding  
‡
ZALR  
1
1
0
0
1
1
1
0
1
0
1
0
0
0
1
0
1
1
I
I
D
D
Zero accumulator and load low accumulator with  
sign extension suppressed  
ZALS  
AUXILIARY REGISTERS AND DATA PAGE POINTER INSTRUCTIONS  
INSTRUCTION BIT CODE  
NO.  
WORDS  
MNEMONIC  
DESCRIPTION  
15 14 13 12 11 10  
9
8
7
6
5
4
3
2
1
0
‡
ADRK  
Add to auxiliary register short immediate  
1
1
0
1
1
1
1
1
1
0
K
Compare auxiliary register with auxiliary  
register AR0  
†
CMPR  
1
1
0
0
1
1
1
0
0
I
1
0
1
0
0
CM  
LAR  
Load auxiliary register  
1
1
1
1
1
2
1
1
1
0
1
0
0
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
0
1
1
0
1
1
1
1
0
0
0
0
1
0
0
0
1
R
D
K
1
LARK  
LARP  
LDP  
Load auxilliary register short immediate  
Load auxilliary register pointer  
Load data memory page pointer  
Load data memory page pointer immediate  
Load auxiliary register long immediate  
Modify auxiliary register  
R
1
0
0
0
1
0
1
I
0
0
0
0
0
R
0
1
0
D
LDPK  
DP  
0
†
LRLK  
MAR  
SAR  
0
I
0
0
0
R
1
1
0
1
1
D
D
Store auxiliary register  
I
R
‡
SBRK  
Subtract from auxiliary register short immediate  
1
K
†
‡
These instructions are not included in the TMS320C1x instruction set.  
These instructions are not included in the TMS32020 instruction set.  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001  
13  
TMS320C25  
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990  
Table 3. TMS320C25 Instruction Set Summary (continued)  
T REGISTER, P REGISTER, AND MULTIPLY INSTRUCTIONS  
INSTRUCTION BIT CODE  
NO.  
WORDS  
MNEMONIC  
DESCRIPTION  
15 14 13 12 11 10  
9
1
1
0
0
8
0
1
0
1
7
0
I
6
5
4
3
2
1
0
APAC  
Add P register to accumulator  
Load high P register  
1
1
1
1
1
0
0
0
1
1
0
0
0
0
1
1
0
1
1
1
1
0
1
1
1
0
1
1
0
0
1
0
1
0
1
†
LPH  
D
LT  
Load T register  
I
D
D
LTA  
Load T register and accumulate previous product  
I
Load T register, accumulate previous product,  
and move data  
LTD  
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
I
I
D
D
Load T register and store P register in  
accumulator  
†
LTP  
†
LTS  
Load T register and subtract previous product  
Multiply and accumulate  
1
2
2
0
0
0
1
1
1
0
0
0
1
1
1
1
1
1
0
1
1
1
0
0
1
1
0
I
I
I
D
D
D
†
MAC  
†
MACD  
Multiply and accumulate with data move  
Multiply (with T register, store product in  
P register)  
MPY  
1
0
0
1
1
1
1
1
0
0
0
1
0
0
I
I
D
D
‡
MPYA  
Multiply and accumulate previous product  
Multiply immediate  
1
1
1
1
1
1
1
1
1
1
1
0
1
0
1
1
1
0
0
1
0
0
0
0
0
1
1
1
1
1
1
0
1
1
1
1
0
0
0
1
1
0
1
0
MPYK  
K
MPYS‡  
MPYU‡  
Multiply and subtract previous product  
Multiply unsigned  
1
0
0
0
1
1
0
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
0
0
1
1
1
1
0
0
1
0
1
1
1
0
0
1
0
0
1
0
I
I
D
D
PAC  
Load accumulator with P register  
Subtract P register from accumulator  
Store high P register  
0
0
I
0
0
0
0
1
1
0
1
1
0
1
0
0
SPAC  
0
‡
SPH  
D
‡
SPL  
Store low P register  
I
D
†
SPM  
Set P register output shift mode  
Square and accumulate  
0
I
0
0
0
1
0
PM  
†
†
SQRA  
SQRS  
D
D
Square and subtract previous product  
I
†
‡
These instructions are not included in the TMS320C1x instruction set.  
These instructions are not included in the TMS32020 instruction set.  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001  
14  
TMS320C25  
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990  
Table 3. TMS320C25 Instruction Set Summary (continued)  
BRANCH/CALL INSTRUCTIONS  
INSTRUCTION BIT CODE  
NO.  
WORDS  
MNEMONIC  
DESCRIPTION  
15 14 13 12 11 10  
9
1
1
1
0
0
1
0
0
1
1
1
1
1
0
0
1
1
1
1
8
1
0
1
1
0
0
0
1
0
0
1
1
1
1
0
0
0
0
0
7
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
0
6
5
4
3
2
1
0
B
Branch unconditionally  
2
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
2
1
1
1
1
1
1
0
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
0
1
1
1
1
1
0
1
1
1
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
0
1
1
1
1
1
1
0
0
1
0
0
1
0
0
0
0
1
1
1
1
1
0
0
0
1
1
0
0
0
0
1
1
1
0
1
1
1
1
D
†
BACC  
BANZ  
Branch to address specified by accumulator  
Branch on auxiliary register not zero  
Branch if TC bit ≠ 0  
0
1
0
0
1
0
1
D
D
D
D
D
D
D
D
D
D
D
†
BBNZ  
†
BBZ  
Branch if TC bit = 0  
‡
BC  
Branch on carry  
BGEZ  
BGZ  
Branch if accumulator ≥ 0  
Branch if accumulator > 0  
Branch on I/O status = 0  
Branch if accumulator ≤ 0  
Branch if accumulator < 0  
Branch on no carry  
BIOZ  
BLEZ  
BLZ  
‡
BNC  
†
BNV  
BNZ  
BV  
Branch if no overflow  
Branch if accumulator ≠ 0  
Branch on overflow  
D
D
D
BZ  
Branch if accumulator = 0  
Call subroutine indirect  
Call subroutine  
CALA  
CALL  
RET  
0
0
1
1
0
0
0
0
1
1
0
1
0
0
D
Return from subroutine  
I/O AND DATA MEMORY OPERATIONS  
INSTRUCTION BIT CODE  
NO.  
WORDS  
MNEMONIC  
DESCRIPTION  
15 14 13 12 11 10  
9
8
7
6
5
4
3
2
1
0
†
BLKD  
Block move from data memory to data memory  
2
2
1
1
1
1
1
1
0
1
1
1
1
1
0
1
I
D
D
D
Block move from program memory to data  
memory  
†
BLKP  
0
0
I
DMOV Data move in data memory  
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
1
1
1
1
1
1
1
1
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
1
0
1
1
1
1
1
0
0
I
0
I
†
FORT  
IN  
Format serial port registers  
Input data from port  
0
0
0
1
1
1
FO  
PA  
D
D
OUT  
RFSM  
RTXM  
Output data to port  
I
PA  
1
‡
†
Reset serial port frame synchronization mode  
Reset serial port transmit mode  
Reset external flag  
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
I
0
0
0
0
0
0
1
1
0
1
1
0
1
0
0
1
0
0
0
0
1
0
0
1
1
0
1
1
0
1
1
0
0
1
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
†
RXF  
‡
†
SFSM  
Set serial port frame synchronization mode  
Set serial port transmit mode  
Set external flag  
STXM  
†
SXF  
TBLR  
TBLW  
Table read  
D
D
Table write  
I
†
‡
These instructions are not included in the TMS320C1x instruction set.  
These instructions are not included in the TMS32020 instruction set.  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001  
15  
TMS320C25  
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990  
Table 3. TMS320C25 Instruction Set Summary (concluded)  
CONTROL INSTRUCTIONS  
INSTRUCTION BIT CODE  
NO.  
WORDS  
MNEMONIC  
DESCRIPTION  
15 14 13 12 11 10  
9
8
7
I
6
5
4
3
D
D
0
2
1
0
†
BIT  
Test bit  
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
0
0
0
1
0
0
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
1
0
0
0
0
0
1
1
1
0
1
1
0
0
0
0
B
†
BITT  
Test bit specified by T register  
Configure block as data memory  
Configure block as program memory  
Disable interrupt  
0
1
1
1
1
1
0
0
0
1
1
0
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
1
0
1
1
1
1
1
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
I
†
CNFD  
0
0
0
0
0
I
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
0
0
0
0
1
0
1
1
0
1
†
CNFP  
DINT  
EINT  
0
0
Enable interrupt  
0
†
IDLE  
LST  
Idle until interrupt  
1
Load status register STO  
Load status register ST1  
No operation  
D
†
LST1  
NOP  
POP  
I
D
0
0
0
I
0
0
0
0
0
1
0
1
0
0
0
1
Pop top of stack to low accumulator  
Pop top of stack to data memory  
Push data memory value onto stack  
Push low accumulator onto stack  
Reset carry bit  
1
†
POPD  
D
†
PSHD  
PUSH  
I
D
1
0
1
0
0
0
0
0
0
0
1
1
0
1
1
1
0
1
0
0
0
0
0
0
1
0
0
0
0
‡
RC  
0
0
0
‡
RHM  
ROVM  
Reset hold mode  
Reset overflow mode  
Repeat instruction as specified by data  
memory value  
†
RPT  
1
1
0
1
1
1
0
0
0
0
1
1
0
0
1
1
1
1
I
D
Repeat instruction as specified by immediate  
value  
†
RPTK  
K
†
RSXM  
Reset sign-extension mode  
Reset test/control flag  
Set carry bit  
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
1
1
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
0
0
1
1
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
I
0
0
0
0
0
0
1
1
1
0
0
1
1
1
0
0
0
0
1
0
1
0
0
0
0
1
1
0
0
1
0
0
1
1
1
‡
RTC  
‡
SC  
‡
SHM  
Set hold mode  
SOVM  
SST  
Set overflow mode  
Store status register ST0  
Store status register ST1  
Set sign-extension mode  
Set test/control flag  
Software interrupt  
D
†
SST1  
I
D
0
†
SSXM  
0
0
0
0
0
0
0
1
0
0
1
1
1
0
1
1
1
1
1
1
0
‡
STC  
0
1
†
TRAP  
†
‡
These instructions are not included in the TMS320C1x instruction set.  
These instructions are not included in the TMS32020 instruction set.  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001  
16  
TMS32020  
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990  
TMS32020 PRODUCT NOTIFICATION  
Texas Instruments has identified an unusual set of circumstances that will cause the BIT (Test Bit) instruction  
on the TMS32020 to affect the contents of the accumulator; ideally, the BIT instruction should not affect the  
accumulator. This set of conditions is:  
1. The overflow mode is set (the OVM status register bit is set to one.)  
2. And, the two LSBs of the BIT instruction opcode word are zero.  
a. When direct memory addressing is used, every fourth data word is affected; all other locations are not  
affected.  
b. When indirect addressing is used, the two LSBs will be zero if a new ARP is not selected or if a new  
ARP is selected and that ARP is 0 or 4.  
3. And, adding the contents of the accumulator with the contents of the addressed data memory location,  
(bit code)  
shifted by 2  
, causes an overflow of the accumulator.  
If all of these conditions are met, the contents of the accumulator will be replaced by the positive or negative  
saturation value, depending on the polarity of the overflow.  
Various methods for avoiding this phenomenon are available:  
•
•
•
•
•
•
If the TMS32020 is not in the saturation mode when the BIT instruction is executed, the device operates  
properly and the accumulator is not affected.  
Execute the Reset Overflow Mode (ROVM) instruction immediately prior to the BIT instruction and the Set  
Overflow Mode (SOVM) instruction immediately following the BIT instruction.  
If direct memory addressing is being used during the BIT instructions, reorganize memory so that the page  
relative locations 0, 4, 8, C, 10 . . . are not used.  
If indirect addressing is being used during the Bit instruction, select a new ARP which is not AR0 or AR4.  
If necessary, follow the instruction with a LARP AR0 or LARP AR4 to restore the code.  
UsetheTestBitSpecifiedbyTRegister(BITT)instructioninsteadoftheBITinstruction. TheBITTinstruction  
operates correctly and will not affect the accumulator under any circumstances.  
Replace TMS32020 with TMS320C25 for ideal pin-to-pIn and object-code compatibility. The BIT instruction  
on the TMS320C25 executes properly and will not affect the accumulator under any circumstances.  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001  
17  
TMS320 SECOND-GENERATION  
DEVICES  
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990  
development support  
Together, Texas Instruments and its authorized third-party suppliers offer an extensive line of development  
support products to assist the user in all aspects of TMS320 second-generation-based design and  
development. These products range from development and application software to complete hardware  
developmentandevaluationsystems. Table4liststhedevelopmentsupportproductsforthesecond-generation  
TMS320 devices.  
System development may begin with the use of the simulator, Software Development System (SWDS), or  
emulator (XDS) along with an assembler/linker. These tools give the TMS320 user various means of evaluation,  
from software simulation of the second-generation TMS320s (simulator) to full-speed in-circuit emulation with  
hardware and software breakpoint trace and timing capabilities (XDS).  
Software and hardware can be developed simultaneously by using the macro assembler/linker, C compiler, and  
simulator for software development, the XDS for hardware development, and the Software Development  
System for both software development and limited hardware development.  
Many third-party vendors offer additional development support for the second-generation TMS320s, including  
assembler/linkers, simulators, high-level languages, applications software, algorithm development tools,  
application boards, software development boards, and in-circuit emulators. Refer to the TMS320 Family  
Development Support Reference Guide (SPRU011A) for further information about TMS320 development  
support products offered by both Texas Instruments and its third-party suppliers.  
Additional support for the TMS320 products consists of an extensive library or product and applications  
documentation. Three-day DSP design workshops are offered by the TI Regional Technology Centers (RTCs).  
These workshops provide insight into the architecture and the instruction set of the second-generation  
TMS320s as well as hands-on training with the TMS320 development tools. When technical questions arise  
regarding the TMS320 family, contact the Texas Instruments TMS320 Hotline at (713) 274-2320. Or, keep  
informedonthelatestTIandthird-partydevelopmentsupporttoolsbyaccessingtheDSPBulletinBoardService  
(BBS) at (713) 274-2323. The BBS serves 2400-, 1200- and 300-bps modems. Also, TMS320 application  
source code may be downloaded from the BBS.  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001  
18  
TMS320 SECOND-GENERATION  
DEVICES  
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990  
Table 4. TMS320 Second-Generation Software and Hardware Support  
SOFTWARE TOOLS  
Macro Assembler/Linker  
PART NUMBER  
IBM MS/PC-DOS  
VAX/VMS  
TMDS3242850-02  
TMDS3242250-08  
TMDS3242260-08  
TMDS3242550-08  
VAX ULTRIX  
SUN UNIX  
Simulator  
IBM MS/PC-DOS  
VAX/VMS  
TMDS3242851-02  
TMDS3242251-08  
C Compiler  
IBM MS/PC-DOS  
VAX/VMS  
TMDX3242855-02  
TMDX3242255-08  
TMDX3242265-08  
TMDX3242555-08  
VAX ULTRIX  
SUN UNIX  
Digital Filter Design Package (DFDP)  
IBM PC-DOS  
DFDP-IBM002  
DSP Software Library  
IBM MS/PC-DOS  
VAX/VMS  
TMDC3240812-12  
TMDC3204212-18  
PART NUMBER  
HARDWARE TOOLS  
Analog Interface Board 2 (AIB2)  
RTC/AIB320A-06  
Analog Interface Board Adaptor  
RTC/ADP320A-06  
EPROM Programmer Adaptor Socket  
(68 to 28-pin)  
TMDX3270120  
Software Development System (SWDS)  
XDS/22 Emulator (see Note)  
TMDX3268821  
TMDS3262221  
TMDX3282226  
XDS/22 Upgrade (TMS32020 to TMS320C2x)  
NOTE: Emulation support for the TMS320C25-50 is available from Macrochip  
Research, Inc.; refer to the TMS320 Family Development Support Reference  
Guide (SPRU011A) for the mailing address.  
IBM is a trademark of International Business Machines Corporation.  
PC-DOS is a trademark of International Business Machines Corporation.  
VAX and VMS are trademarks of Digital Equipment Corporation.  
XDS is a trademark of Texas Instruments Incorporated.  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001  
19  
TMS320 SECOND-GENERATION  
DEVICES  
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990  
documentation support  
Extensive documentation supports the second-generation TMS320 devices from product announcement  
through applications development. The types of documentation include data sheets with design specifications,  
complete user’s guides, and 750 pages of application reports published in the book, Digital Signal Processing  
Applications with the TMS320 Family (SPRA012A). An application report, Hardware Interfacing to the  
TMS320C25 (SPRA014A), is available for that device.  
A series of DSP textbooks is being published by Prentice-Hall and John Wiley & Sons to support digital signal  
processing research and education. The TMS320 newsletter, Details on Signal Processing, is published  
quarterly and distributed to update TMS320 customers on product information. The TMS320 DSP bulletin board  
service provides access to large amounts of information pertaining to the TMS320 family.  
Refer to the TMS320 Family Development Support Reference Guide (SPRU011A) for further information about  
TMS320 documentation. To receive copies of second-generation TMS320 literature, call the Customer  
Response Center at 1-800-232-3200.  
specification overview  
The electrical specifications for the TMS32020, TMS320C25, TMS320E25, and TMS320C25-50 are given in  
the following pages. Note that the electrical specifications for the TMS320E25 are identical to those for the  
TMS320C25, with the addition of EPROM-related specifications. A summary of differences between  
TMS320C25 and TMS320C25-50 specifications immediately follows the TMS320C25-50 specification.  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001  
20  
TMS32020  
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990  
absolute maximum ratings over specified temperature range (unless otherwise noted)†  
‡
Supply voltage range, V  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V  
CC  
Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V  
Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V  
Continuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 W  
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C  
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 150°C  
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and  
functionaloperation of the device at these or any other conditions beyond those indicated in the “Recommended Operating Conditions” section of  
this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
†
‡
All voltage values are with respect to V  
.
SS  
recommended operating conditions  
MIN  
NOM MAX  
UNIT  
V
V
V
Supply voltage  
Supply voltage  
4.75  
5
0
5.25  
CC  
V
SS  
All inputs except CLKIN  
CLKIN  
2
2.4  
V
+ 0.3  
+ 0.3  
0.8  
0.8  
300  
2
V
CC  
V
V
High-level input voltage  
Low-level input voltage  
IH  
V
CC  
V
All inputs except CLKIN  
CLKIN  
– 0.3  
– 0.3  
V
IL  
V
I
I
High-level output current  
Low-level output current  
µA  
mA  
°C  
OH  
OL  
T
A
Operating free-air temperature (see Notes 1 and 2)  
0
70  
NOTES: 1. Case temperature (T ) must be maintained below 90°C.  
C
2. R  
= 36°C/Watt, R = 6°C/Watt.  
θJC  
θJA  
electrical characteristics over specified free-air temperature range (unless otherwise noted)  
§
PARAMETER  
High-level output voltage  
Low-level output voltage  
Three-state current  
Input current  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
V
V
V
V
= MIN, I  
= MAX  
= MAX  
2.4  
3
OH  
CC  
OH  
= MIN, I  
V
0.3  
0.6  
20  
V
OL  
CC  
OL  
= MAX  
I
I
V
–20  
–10  
µA  
µA  
mA  
mA  
mA  
pF  
Z
CC  
V = V  
to V  
CC  
10  
I
I
SS  
= MAX, f = MAX  
T
= 0°C, V  
CC  
360  
A
x
I
Supply current  
T
A
= 25°C, V  
= MAX, f = MAX  
250  
CC  
CC  
x
T
C
= 90°C, V  
= MAX, f = MAX  
285  
15  
CC  
x
C
C
Input capacitance  
Output capacitance  
I
15  
pF  
O
§
All typical values for I  
CC  
are at V  
= 5 V, T = 25°C.  
CC  
A
This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields. These  
circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to MIL-STD-883C,  
Method 3015; however, it is advised that precautions should be taken to avoid application of any voltage higher than maximum-rated  
voltages to these high-impedance circuits. During storage or handling, the device leads should be shorted together or the device  
shouldbe placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriated logic voltagelevel, preferablyeither  
or ground. Specific guidelines for handling devices of this type are contained in the publication Guidelines for Handling  
V
CC  
Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies available from Texas Instruments.  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001  
21  
TMS32020  
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990  
CLOCK CHARACTERISTICS AND TIMING  
The TMS32020 can use either its internal oscillator or an external frequency source for a clock.  
internal clock option  
The internal oscillator is enabled by connecting a crystal across X1 and X2/CLKIN (see Figure 2). The frequency  
of CLKOUT1 is one-fourth the crystal fundamental frequency. The crystal should be fundamental  
mode, and parallel resonant, with an effective series resistance of 30 Ω, a power dissipation of 1 mW,  
and be specified at a load capacitance of 20 pF.  
†
PARAMETER  
Input clock frequency  
Serial port frequency  
TEST CONDITIONS  
MIN  
TYP  
MAX  
20.5  
2563  
UNIT  
MHz  
MHz  
pF  
f
f
T
= 0°C to 70°C  
= 0°C to 70°C  
= 0°C to 70°C  
6.7  
x
A
†
T
A
50  
xs  
C1, C2  
T
A
10  
†
Value derived from characterization data; minimum f at test = 825 kHz.  
sx  
X1  
X2/CLKIN  
Crystal  
C1  
C2  
Figure 2. Internal Clock Option  
external clock option  
An external frequency source can be used by injecting the frequency directly into X2/CLKIN with X1 left  
unconnected. The external frequency injected must conform to the specifications listed in the following table.  
switching characteristics over recommended operating conditions (see Note 3)  
PARAMETER  
CLKOUT1/CLKOUT2 cycle time  
MIN  
195  
25  
NOM  
MAX  
597  
60  
UNIT  
ns  
t
t
t
t
t
t
c(C)  
CLKIN high to CLKOUT1/CLKOUT2/STRB high/low  
CLKOUT1/CLKOUT2/STRB fall time  
ns  
d(CIH-C)  
f(C)  
10  
ns  
CLKOUT1/CLKOUT2/STRB rise time  
10  
ns  
r(C)  
CLKOUT1/CLKOUT2 low pulse duration  
2Q – 15  
2Q – 15  
Q – 10  
2Q 2Q + 15  
2Q 2Q + 15  
ns  
w(CL)  
w(CH)  
CLKOUT1/CLKOUT2 high pulse duration  
ns  
td(C1-C2)  
CLKOUT1 high to CLKOUT2 low, CLKOUT2 high to CLKOUT1 high, etc.  
Q
Q + 10  
ns  
NOTE 3: Q = 1/4t  
.
c(C)  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001  
22  
TMS32020  
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990  
timing requirements over recommended operating conditions (see Note 3)  
MIN  
NOM  
MAX  
UNIT  
ns  
t
t
t
t
t
t
t
CLKIN cycle time  
CLKIN fall time  
195  
597  
c(C)  
†
10  
10  
ns  
f(CI)  
†
CLKIN rise time  
ns  
r(CI)  
CLKIN low pulse duration, t  
= 50 ns (see Note 4)  
40  
40  
10  
15  
ns  
w(CIL)  
w(CIH)  
su(S)  
h(S)  
c(CI)  
CLKIN high pulse duration, t  
= 50 ns (see Note 4)  
ns  
c(CI)  
SYNC setup time before CLKIN low  
SYNC hold time from CLKIN low  
Q – 10  
ns  
ns  
†
Value derived from characterization data and not tested.  
NOTES: 3. Q = 1/4t  
.
c(C)  
4. CLKIN duty cycle [t  
+ t  
/ t  
must be within 40-60%.  
r(CI) w(CIH)] c(CI)  
2.15 V  
R
C
= 825 Ω  
L
L
From Output  
Under Test  
Test  
Point  
= 100 pF  
Figure 3. Test Load Circuit  
2.0 V  
V
(Min)  
(Max)  
IH  
1.88 V  
0.92 V  
V
IL  
0.80 V  
0
(a) Input  
2.4 V  
V
(Min)  
(Max)  
OH  
2.2 V  
0.8 V  
V
OL  
0.6 V  
0
(b) Output  
Figure 4. Voltage Reference Levels  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001  
23  
TMS32020  
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990  
MEMORY AND PERIPHERAL INTERFACE TIMING  
switching characteristics over recommended operating conditions (see Note 3)  
PARAMETER  
STRB from CLKOUT1 (if STRB is present)  
MIN  
TYP  
Q
MAX  
Q + 15  
15  
UNIT  
ns  
t
t
t
t
t
t
t
t
t
t
t
Q – 15  
– 15  
d(C1-S)  
d(C2-S)  
su(A)  
CLKOUT2 to STRB (if STRB is present)  
0
ns  
Address setup hold time before STRB low (see Note 5)  
Address hold time after STRB high (see Note 5)  
STRB low pulse duration (no wait states, see Note 6)  
STRB high pulse duration (between consecutive cycles, see Note 6)  
Data write setup time before STRB high (no wait states)  
Data write hold time from STRB high  
Q – 30  
Q – 15  
ns  
ns  
h(A)  
2Q  
2Q  
ns  
w(SL)  
w(SH)  
su(D)W  
h(D)W  
en(D)  
ns  
2Q – 45  
Q – 15  
ns  
Q
ns  
†
0
Data bus starts being driven after STRB low (write cycle)  
Data bus three-state after STRB high (write cycle)  
MSC valid from CLKOUT1  
ns  
†
Q
0
Q + 30  
ns  
dis(D)  
d(MSC)  
–25  
25  
ns  
†
Value derived from characterization data and not tested.  
NOTES: 3. Q = 1/4t  
.
c(C)  
5. A15-A0, PS, DS, IS, R/W, and BR timings are all included in timings referenced as “address”.  
6. Delays between CLKOUT1/CLKOUT2 edges and STRB edges track each other, resulting in t  
no wait states.  
and t  
being 2Q with  
w(SH)  
w(SL)  
timing requirements over recommended operating conditions (see Note 3)  
MIN  
NOM  
MAX  
UNIT  
ns  
†
t
t
t
t
t
t
t
t
t
Read data access time from address time (read cycle, see Notes 5 and 7)  
Data read setup time before STRB high  
Data read hold time from STRB high  
3Q – 70  
a(A)  
40  
0
ns  
su(D)R  
h(D)R  
ns  
READY valid after STRB low (no wait states)  
READY valid after CLKOUT2 high  
Q – 40  
Q – 40  
ns  
d(SL-R)  
d(C2H-R)  
h(SL-R)  
h(C2H-R)  
d(M-R)  
h(M-R)  
ns  
READY hold time after STRB low (no wait states)  
READY hold after CLKOUT2 high  
Q – 5  
Q – 5  
ns  
ns  
READY valid after MSC valid  
2Q – 50  
ns  
READY hold time after MSC valid  
0
ns  
†
Value derived from characterization data and not tested.  
NOTES: 3. Q = 1/4t  
.
c(C)  
5. A15-A0, PS, DS, IS, R/W, and BR timings are all included in timings referenced as “address”.  
7. Read data access time is defined as t = t + t – t  
.
a(A) su(A) w(SL) su(D)R  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001  
24  
TMS32020  
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990  
RS, INT, BIO, AND XF TIMING  
switching characteristics over recommended operating conditions (see Note 3 and 8)  
PARAMETER  
CLKOUT1 low to reset state entered  
MIN  
TYP MAX  
UNIT  
ns  
t
t
t
45  
d(RS)  
CLKOUT1 to IACK valid  
– 25  
0
25  
ns  
d(IACK)  
d(XF)  
XF valid before falling edge of STRB  
Q – 30  
ns  
NOTES: 3. Q = 1/4t  
.
c(C)  
8. RS, INT, and BIO are asynchronous inputs and can occur at any time during a clock cycle. However, if the specified setup time is met,  
the exact sequence shown in the timing diagrams will occur.  
timing requirements over recommended operating conditions (see Note 3 and 8)  
MIN  
50  
0
NOM MAX  
UNIT  
ns  
t
t
t
t
t
INT/BIO/RS setup before CLKOUT1 high  
INT/BIO/RS hold after CLKOUT1 high  
INT/BIO fall time  
su(IN)  
h(IN)  
f(IN)  
ns  
†
15  
ns  
INT/BIO low pulse duration  
RS low pulse duration  
t
ns  
w(IN)  
w(RS)  
c(C)  
3t  
c(C)  
ns  
†
Value derived from characterization data and not tested.  
NOTES: 3. Q = 1/4t  
.
c(C)  
8. RS, INT, and BIO are asynchronous inputs and can occur at any time during a clock cycle. However, if the specified setup time is met,  
the exact sequence shown in the timing diagrams will occur.  
HOLD TIMING  
switching characteristics over recommended operating conditions (see Note 3)  
PARAMETER  
HOLDA low after CLKOUT1 low  
MIN  
TYP MAX  
UNIT  
ns  
†
–25  
t
t
t
t
t
25  
d(C1L-AL)  
dis(AL-A)  
dis(C1L-A)  
d(HH-AH)  
en(A-C1L)  
†
15  
HOLDA low to address three-state  
ns  
†
30  
Address three-state after CLKOUT1 low (HOLD mode, see Note 9)  
HOLD high to HOLDA high  
ns  
50  
ns  
†
10  
Address driven before CLKOUT1 low (HOLD mode, see Note 9)  
ns  
†
Value derived from characterization data and not tested.  
NOTES: 3. Q = 1/4t  
.
c(C)  
9. A15-A0, PS, DS, IS, STRB, and R/W timings are all included in timings referenced as “address.”  
timing requirements over recommended operating conditions (see Note 3)  
MIN  
NOM  
MAX  
UNIT  
t
HOLD valid after CLKOUT2 high  
Q – 45  
ns  
d(C2H-H)  
NOTE 3: Q = 1/4t  
.
c(C)  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001  
25  
TMS32020  
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990  
SERIAL PORT TIMING  
switching characteristics over recommended operating conditions (see Note 3)  
PARAMETER  
DX valid after CLKX rising edge (see Note 10)  
DX valid after FSX falling edge (TXM = 0, see Note 10)  
FSX valid after CLKX rising edge (TXM = 1)  
MIN  
TYP MAX  
UNIT  
ns  
t
t
t
100  
50  
d(CH-DX)  
d(FL-DX)  
d(CH-FS)  
ns  
60  
ns  
NOTES: 3. Q = 1/4t  
.
c(C)  
10. The last occurrence of FSX falling and CLKX rising.  
timing requirements over recommended operating conditions (see Note 3)  
MIN  
NOM  
MAX  
UNIT  
†
t
t
t
t
t
t
t
t
t
Serial port clock (CLKX/CLKR) cycle time  
390  
20 000  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
c(SCK)  
f(SCK)  
r(SCK)  
w(SCK)  
w(SCK)  
su(FS)  
h(FS)  
‡
Serial port clock (CLKX/CLKR) fall time  
50  
‡
Serial port clock (CLKX/CLKR) rise time  
50  
Serial port clock (CLKX/CLKR) low pulse duration (see Note 11)  
Serial port clock (CLKX/CLKR) high pulse duration (see Note 11)  
FSX/FSR setup time before CLKX/CLKR falling edge (TXM = 0)  
FSX/FSR hold time after CLKX/CLKR falling edge (TXM = 0)  
DR setup time before CLKR falling edge  
150  
150  
20  
12 000  
12 000  
20  
20  
su(DR)  
h(DR)  
DR hold time after CLKR falling edge  
20  
†
‡
Value derived from characterization data; minimum f at test = 825 kHz.  
sx  
Value derived from characterization data and not tested.  
NOTES: 3. Q = 1/4t  
.
c(C)  
11. The duty cycle of the serial port clock must be within 40-60%.  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001  
26  
TMS320C25, TMS320E25  
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990  
†
absolute maximum ratings over specified temperature range (unless otherwise noted)  
‡
Supply voltage range, V  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V  
CC  
Input voltage range: TMS320E25 pins 24 and 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 15 V  
All other inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V  
Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V  
Continuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 W  
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C  
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 150°C  
†
‡
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and  
functionaloperation of the device at these or any other conditions beyond those indicated in the “Recommended Operating Conditions” section of  
this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
All voltage values are with respect to V  
.
SS  
recommended operating conditions  
MIN  
NOM  
MAX  
UNIT  
V
V
V
Supply voltage  
Supply voltage  
4.75  
5
0
5.25  
CC  
V
SS  
All inputs except CLKIN/CLKX/CLKR/INT (0-2)  
INT (0-2)  
2.35  
2.5  
V
CC  
V
CC  
V
CC  
+ 0.3  
+ 0.3  
+ 0.3  
0.8  
V
V
High-level input voltage  
V
IH  
CLKIN/CLKX/CLKR  
All inputs except MP/MC  
MP/MC  
3.5  
V
– 0.3  
– 0.3  
V
V
IL  
Low-level input voltage  
0.8  
V
I
I
High-level output current  
Low-level output current  
300  
2
µA  
mA  
°C  
°C  
OH  
OL  
TMS320C25, TMS320E25  
TMS320C25GBA  
0
70  
T
Operating free-air temperature  
A
– 40  
85  
electrical characteristics over specified free-air temperature range (unless otherwise noted)  
§
3
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
V
V
V
High-level output voltage  
Low-level output voltage  
Three-state current  
Input current  
V
= MIN, I  
= MAX  
= MAX  
2.4  
OH  
CC  
OH  
= MIN, I  
V
0.3  
0.6  
20  
V
OL  
CC  
OL  
= MAX  
I
I
V
–20  
–10  
µA  
µA  
Z
CC  
V = V  
to V  
CC  
10  
I
I
SS  
= MAX, f = MAX  
Normal  
110  
50  
185  
100  
mA  
Low-level input voltage  
T
A
= 0°C, V  
CC  
I
x
CC  
Idle/HOLD  
C
C
Input capacitance  
Output capacitance  
15  
pF  
pF  
I
15  
O
§
All typical values are at V  
= 5 V, T = 25°.  
CC  
A
Caution. This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic  
fields. These circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to  
MIL-STD-883C, Method 3015; however, it is advised that precautions to be taken to avoid application of any voltage higher than  
maximum rated voltages to these high-impedance circuits. During storage or handling, the device leads should be shorted together  
or the device should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriate logic voltage level,  
preferably either V or ground. Specific guidelines for handling devices of this type are contained in the publication “Guidelines for Handling  
CC  
Electrostatic-Discharge Sensitive (ESDS) Devices and Assemblies” available from Texas Instruments  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001  
27  
TMS320C25, TMS320E25  
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990  
CLOCK CHARACTERISTICS AND TIMING  
The TMS32025 can use either its internal oscillator or an external frequency source for a clock.  
internal clock option  
The internal oscillator is enabled by connecting a crystal across X1 and X2/CLKIN (see Figure 2). The frequency  
ofCLKOUT1 is one-fourth the crystal fundamental frequency. The crystal should be either fundamental  
or overtone mode, and parallel resonant, with an effective series resistance of 30 Ω, a power dissipation  
of 1 mW, and be specified at a load capacitance of 20 pF. Note that overtone crystals require an additional tuned  
LC circuit; see the application report, Hardware Interfacing to the TMS320C25 (SPRA014A).  
PARAMETER  
Input clock frequency  
Serial port frequency  
TEST CONDITIONS  
MIN  
TYP  
MAX  
40.96  
5120  
UNIT  
MHz  
MHz  
pF  
f
f
T
= 0°C to 70°C  
= 0°C to 70°C  
= 0°C to 70°C  
6.7  
x
A
†
0
T
A
xs  
C1, C2  
T
A
10  
†
The serial port was tested at a minimum frequency of 1.25 MHz. However, the serial port was fully static but will properly function down  
to f = 0 Hz.  
sx  
X1  
X2/CLKIN  
Crystal  
C1  
C2  
Figure 2. Internal Clock Option  
external clock option  
An external frequency source can be used by injecting the frequency directly into X2/CLKIN with X1 left  
unconnected. The external frequency injected must conform to the specifications listed in the following table.  
switching characteristics over recommended operating conditions (see Note 3)  
PARAMETER  
CLKOUT1/CLKOUT2 cycle time  
MIN  
97.7  
5
TYP  
MAX  
597  
30  
5
UNIT  
ns  
t
t
t
t
t
t
t
c(C)  
CLKIN high to CLKOUT1/CLKOUT2/STRB high/low  
CLKOUT1/CLKOUT2/STRB fall time  
ns  
d(CIH-C)  
f(C)  
ns  
CLKOUT1/CLKOUT2/STRB rise time  
5
ns  
r(C)  
CLKOUT1/CLKOUT2 low pulse duration  
2Q – 8  
2Q – 8  
Q – 5  
2Q 2Q + 8  
2Q 2Q + 8  
ns  
w(CL)  
w(CH)  
CLKOUT1/CLKOUT2 high pulse duration  
ns  
)
CLKOUT1 high to CLKOUT2 low, CLKOUT2 high to CLKOUT1 high, etc.  
Q
Q + 5  
ns  
d(C1-C2  
NOTE 3: Q = 1/4t  
.
c(C)  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001  
28  
TMS320C25, TMS320E25  
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990  
timing requirements over recommended operating conditions (see Note 3)  
MIN  
NOM MAX  
UNIT  
ns  
t
t
t
t
t
t
t
CLKIN cycle time  
CLKIN fall time  
24.4  
150  
c(CI)  
†
5
5
ns  
f(CI)  
†
CLKIN rise time  
ns  
r(CI)  
CLKIN low pulse duration, t  
= 50 ns (see Note 4)  
20  
20  
5
ns  
w(CIL)  
w(CIH)  
su(S)  
h(S)  
c(CI)  
CLKIN high pulse duration, t  
= 50 ns (see Note 4)  
ns  
c(CI)  
SYNC setup time before CLKIN low  
SYNC hold time from CLKIN low  
Q – 5  
ns  
8
ns  
†
Value derived from characterization data and not tested.  
NOTES: 3. Q = 1/4t  
.
c(C)  
4. CLKIN duty cycle [t  
+ t  
]/t  
must be within 40-60%.  
r(CI) w(CIH) c(CI)  
+5 V  
f
TMS320C25  
crystal  
10 kΩ  
74HC04  
4.7 kΩ  
F11  
CLKIN  
C = 20 pF  
0.1 µF  
47 pF  
74AS04  
10 kΩ  
L
f
(MHz)  
L, (µH)  
crystal,  
TMS320C25  
TMS320C25-50  
TMS320E25  
40.96  
51.20  
40.96  
1.8  
1.0  
1.8  
Figure 3. External Clock Option  
Shown above is a crystal oscillator circuit suitable for providing the input clock signal to the TMS320C25,  
TMS320E25, and TMS320C25-50. Please refer to Hardware Interfacing to the TMS320C25 (document number  
SPRA014A) for details on circuit operation.  
2.15 V  
R
C
= 825 Ω  
L
L
From Output  
Under Test  
Test  
Point  
= 100 pF  
Figure 4. Test Load Circuit  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001  
29  
TMS320C25, TMS320E25  
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990  
2.0 V  
2.4 V  
V
(Min)  
(Max)  
V
(Min)  
(Max)  
IH  
OH  
1.88 V  
0.92 V  
2.2 V  
0.8 V  
V
IL  
V
OL  
0.80 V  
0
0.6 V  
0
(a) Input  
(b) Output  
Figure 5. Voltage Reference Levels  
MEMORY AND PERIPHERAL INTERFACE TIMING  
switching characteristics over recommended operating conditions (see Note 3)  
PARAMETER  
STRB from CLKOUT1 (if STRB is present)  
MIN  
Q – 6  
TYP  
Q
MAX  
UNIT  
ns  
t
t
t
t
t
t
t
t
t
t
t
Q + 6  
6
d(C1-S)  
d(C2-S)  
su(A)  
CLKOUT2 to STRB (if STRB is present)  
– 6  
0
ns  
Address setup time before STRB low (see Note 5)  
Address hold time after STRB high (see Note 5)  
STRB low pulse duration (no wait states, see Note 6)  
STRB high pulse duration (between consecutive cycles, see Note 6)  
Data write setup time before STRB high (no wait states)  
Data write hold time from STRB high  
Q – 12  
Q – 8  
ns  
ns  
h(A)  
2Q – 5  
2Q – 5  
2Q – 20  
Q – 10  
2Q + 5  
2Q + 5  
ns  
w(SL)  
w(SH)  
su(D)W  
h(D)W  
en(D)  
ns  
ns  
Q
ns  
†
0
Data bus starts being driven after STRB low (write cycle)  
Data bus three-state after STRB high (write cycle)  
MSC valid from CLKOUT1  
ns  
†
Q
0
Q + 15  
ns  
dis(D)  
d(MSC)  
– 12  
12  
ns  
†
Value derived from characterization data and not tested.  
NOTES: 3. Q = 1/4t  
.
c(C)  
5. A15-A0, PS, DS, IS, R/W, and BR timings are all included in timings referenced as “address”.  
6. Delays between CLKOUT1/CLKOUT2 edges and STRB edges track eachother, resulting in t  
states.  
and t  
being 2Q with no wait  
w(SH)  
w(SL)  
timing requirements over recommended operating conditions (see Note 3)  
MIN  
NOM  
MAX  
UNIT  
ns  
t
t
t
t
t
t
t
t
t
Read data access time from address time (read cycle, see Notes 5 and 7)  
Data read setup time before STRB high  
Data read hold time from STRB high  
3Q – 35  
a(A)  
23  
0
ns  
su(D)R  
h(D)R  
ns  
READY valid after STRB low (no wait states)  
READY valid after CLKOUT2 high  
Q – 20  
Q – 20  
ns  
d(SL-R)  
d(C2H-R)  
h(SL-R)  
h(C2H-R)  
d(M-R)  
h(M-R)  
ns  
READY hold time after STRB low (no wait states)  
READY hold after CLKOUT2 high  
Q + 3  
Q + 3  
ns  
ns  
READY valid after MSC valid  
2Q – 25  
ns  
READY hold time after MSC valid  
0
ns  
NOTES: 3. Q = 1/4t  
.
c(C)  
5. A15-A0, PS, DS, IS, R/W, and BR timings are all included in timings referenced as “address”.  
7. Read data access time is defines as t = t + t – t  
.
a(A) su(A) w(SL) su(D)R  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001  
30  
TMS320C25, TMS320E25  
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990  
RS, INT, BIO, AND XF TIMING  
switching characteristics over recommended operating conditions (see Note 3 and 8)  
PARAMETER  
CLKOUT1 low to reset state entered  
MIN  
TYP MAX  
UNIT  
ns  
†
t
t
t
22  
12  
d(RS)  
CLKOUT1 to IACK valid  
– 6  
0
ns  
d(IACK)  
d(XF)  
XF valid before falling edge of STRB  
Q – 15  
ns  
NOTES: 3. Q = 1/4t  
.
c(C)  
8. RS, INT, and BIO are asynchronous inputs and can occur at any time during a clock cycle. However, if the specified setup time is  
met, the exact sequence shown in the timing diagrams will occur.  
timing requirements over recommended operating conditions (see Note 3 and 8)  
MIN  
32  
0
NOM MAX  
UNIT  
ns  
t
t
t
t
t
INT/BIO/RS setup before CLKOUT1 high  
INT/BIO/RS hold after CLKOUT1 high  
INT/BIO fall time  
su(IN)  
h(IN)  
f(IN)  
ns  
†
8
ns  
INT/BIO low pulse duration  
RS low pulse duration  
t
ns  
w(IN)  
w(RS)  
c(C)  
3
tc(C)  
ns  
†
Value derived from characterization data and not tested.  
NOTES: 3. Q = 1/4t  
.
c(C)  
8. RS, INT, and BIO are asynchronous inputs and can occur at any time during a clock cycle. However, if the specified setup time is  
met, the exact sequence shown in the timing diagrams will occur.  
HOLD TIMING  
switching characteristics over recommended operating conditions (see Note 3)  
PARAMETER  
HOLDA low after CLKOUT1 low  
MIN  
TYP  
MAX  
UNIT  
ns  
t
t
t
t
t
0
10  
d(C1L-AL)  
dis(AL-A)  
dis(C1L-A)  
d(HH-AH)  
en(A-C1L)  
†
0
HOLDA low to address three-state  
ns  
†
20  
Address three-state after CLKOUT1 low (HOLD mode, see Note 9)  
HOLD high to HOLDA high  
ns  
25  
ns  
†
8
Address driven before CLKOUT1 low (HOLD mode, see Note 9)  
ns  
†
Value derived from characterization data and not tested.  
NOTES: 3. Q = 1/4t  
.
c(C)  
9. A15-A0, PS, DS, IS, STRB, and R/W timings are all included in timings referenced as “address.”  
timing requirements over recommended operating conditions (see Note 3)  
MIN  
NOM  
MAX  
UNIT  
t
HOLD valid after CLKOUT2 high  
Q – 24  
ns  
d(C2H-H)  
NOTE 3: Q = 1/4t  
.
c(C)  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001  
31  
TMS320C25, TMS320E25  
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990  
SERIAL PORT TIMING  
switching characteristics over recommended operating conditions (see Note 3)  
PARAMETER  
DX valid after CLKX rising edge (see Note 10)  
DX valid after FSX falling edge (TXM = 0, see Note 10)  
FSX valid after CLKX rising edge (TXM = 1)  
MIN  
TYP MAX  
UNIT  
ns  
t
t
t
75  
40  
40  
d(CH-DX)  
d(FL-DX)  
d(CH-FS)  
ns  
ns  
NOTES: 3. Q = 1/4t  
.
c(C)  
10. The last occurrence of FSX falling and CLKX rising.  
timing requirements over recommended operating conditions (see Note 3)  
MIN  
NOM MAX  
UNIT  
ns  
†
t
t
t
t
t
t
t
t
t
Serial port clock (CLKX/CLKR) cycle time  
Serial port clock (CLKX/CLKR) fall time  
Serial port clock (CLKX/CLKR) rise time  
200  
c(SCK)  
f(SCK)  
r(SCK)  
w(SCK)  
w(SCK)  
su(FS)  
h(FS)  
‡
‡
25  
ns  
25  
ns  
Serial port clock (CLKX/CLKR) low pulse duration (see Note 11)  
Serial port clock (CLKX/CLKR) high pulse duration (see Note 11)  
FSX/FSR setup time before CLKX/CLKR falling edge (TXM = 0)  
FSX/FSR hold time after CLKX/CLKR falling edge (TXM = 0)  
DR setup time before CLKR falling edge  
80  
80  
18  
20  
10  
20  
ns  
ns  
ns  
ns  
ns  
su(DR)  
h(DR)  
DR hold time after CLKR falling edge  
ns  
†
‡
The serial port was tested at a minimum frequency of 1.25 MHz. However, the serial port was fully static but will properly function down  
to f = 0 Hz.  
sx  
Value derived from characterization data and not tested.  
NOTES: 3. Q = 1/4t  
.
c(C)  
11. The duty cycle of the serial port clock must be within 40-60%.  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001  
32  
TMS320E25  
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990  
EPROM PROGRAMMING  
†
absolute maximum ratings over specified temperature range (unless otherwise noted)  
‡
Supply voltage range, V  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.6 V to 15 V  
Input voltage range on pins 24 and 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 15 V  
PP  
†
‡
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and  
functionaloperation of the device at these or any other conditions beyond those indicated in the “Recommended Operating Conditions” section of  
this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
All voltage values are with respect to GND.  
recommended operating conditions  
MIN  
NOM MAX  
UNIT  
V
V
V
V
Programming mode supply voltage (see Note 13)  
Read mode supply voltage  
6
V
V
V
V
CC  
CC  
PP  
PP  
4.75  
12  
5
5.25  
13  
Programming mode supply voltage  
Read mode supply voltage (see Note 12)  
12.5  
V
CC  
supply current in this case would be I  
CC  
NOTES: 12. V  
can be connected to V  
CC  
directly (except in the program mode). V  
must be maintained at 12.5 V (± 0.25 V).  
+ I . During  
CC PP  
PP  
programming, V  
13. V  
CC  
PP  
must be applied before or at the same time as V  
and removed after or at the same time as V . This device must not be  
PP  
or V  
PP  
inserted into or removed from the board when V  
PP  
is applied.  
CC  
electrical characteristics over specified temperature range (unless otherwise noted)  
§
PARAMETER  
supply current  
TEST CONDITIONS  
V = V = 5.25 V  
PP  
MIN  
TYP  
MAX  
100  
50  
UNIT  
µA  
I
I
V
V
PP1  
PP  
CC  
= 13 V  
supply current (during program pulse)  
are at V = 5 V, T = 25°C.  
V
PP  
30  
mA  
PP2  
PP  
§
All typical values for I  
CC  
CC  
A
recommended timing requirements for programming, T = 25°C, V  
= 6 V, V = 12.5 V  
PP  
CC  
A
(see Notes 14 and 15)  
MIN  
NOM MAX  
UNIT  
t
t
t
t
t
t
t
t
t
t
t
t
Initial program pulse duration  
Final pulse duration  
Address setup time  
E setup time  
0.95  
1
1.05  
ms  
w(IPGM)  
w(FPGM)  
su(A)  
2.85  
78.75  
ms  
µs  
µs  
µs  
ns  
ns  
µs  
µs  
µs  
µs  
µs  
2
2
2
0
su(E)  
G setup time  
su(G)  
Output disable time from G  
Output enable time from G  
Data setup time  
130¶  
150¶  
dis(G)  
en(G)  
2
2
2
0
2
su(D)  
V
V
setup time  
setup time  
su(VPP)  
su(VCC)  
h(A)  
PP  
CC  
Address hold time  
Data hold time  
h(D)  
Value derived from characterization data and not tested.  
NOTES: 14. For all switching characteristics and timing measurements, input pulse levels are 0.4 V to 2.4 V and V  
programming.  
= 12.5 V ± 0.5 V during  
PP  
15. Common test conditions apply for t  
except during programming.  
dis(G)  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001  
33  
TMS320C25-50  
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990  
†
absolute maximum ratings over specified temperature range (unless otherwise noted)  
‡
Supply voltage range, V  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V  
CC  
Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V  
Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V  
Continuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 W  
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C  
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 150°C  
†
‡
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and  
functionaloperation of the device at these or any other conditions beyond those indicated in the “Recommended Operating Conditions” section of  
this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
All voltage values are with respect to V  
.
SS  
recommended operating conditions  
MIN  
NOM MAX  
UNIT  
V
V
V
Supply voltage  
Supply voltage  
4.75  
5
0
5.25  
CC  
V
SS  
INT0-INT2  
2.5  
3.5  
V
V
High-level input voltage  
Low-level input voltage  
CLKIN, CLKX, CLKR  
Other inputs  
MP/MC  
V
IH  
IL  
2.35  
V
0.8  
0.8  
0.8  
300  
2
V
V
CLKIN  
V
Other inputs  
V
I
I
High-level output current  
Low-level output current  
Operating free-air temperature  
µA  
mA  
°C  
OH  
OL  
T
0
70  
A
electrical characteristics over specified free-air temperature range (unless otherwise noted)  
§
TYP  
PARAMETER  
High-level output voltage  
Low-level output voltage  
High-impedance current  
Input current  
TEST CONDITIONS  
MIN  
MAX  
UNIT  
V
V
V
V
= MIN, I  
= MAX  
= MAX  
2.4  
OH  
CC  
OH  
= MIN, I  
V
0.6  
20  
V
OL  
CC  
OL  
= MAX  
I
I
V
– 20  
– 10  
µA  
µA  
Z
CC  
V = V  
to V  
CC  
10  
I
I
SS  
Normal  
Idle, HOLD  
110  
50  
185  
100  
T
A
= 0°C, V = MAX, f = MAX  
CC  
x
I
Supply current  
mA  
CC  
C
C
Input capacitance  
Output capacitance  
15  
pF  
pF  
I
15  
O
§
All typical values are at V  
= 5 V, T = 25°C.  
CC  
A
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001  
34  
TMS320C25-50  
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990  
CLOCK CHARACTERISTICS AND TIMING  
The TMS320C25-50 can use either its internal oscillator or an external frequency source for a clock.  
internal clock option  
TheinternaloscillatorisenabledbyconnectingacrystalacrossX1 andX2, CLKIN. ThefrequencyofCLKOUT1  
is one-fourth the crystal fundamental frequency. The crystal should be in either fundamental or overtone mode,  
and parallel resonant, with an effective series resistance of 30 Ω, a power dissipation of 1 mW, and be specified  
at a load capacitance of 20 pF. Note that overtone crystals require an additional tuned LC circuit.  
†
PARAMETER  
Input clock frequency  
Serial port frequency  
TEST CONDITIONS  
MIN  
6.7  
0
TYP  
MAX  
51.2  
6.4  
UNIT  
MHz  
MHz  
pF  
f
f
T
= 0°C to 70°C  
= 0°C to 70°C  
= 0°C to 70°C  
x
A
T
A
sx  
C1, C2  
T
A
10  
†
The serial port was tested at a minimum frequency of 1.25 MHz. However, the serial port was fully static but will properly function down to  
= 0 Hz.  
f
sx  
X1  
X2/CLKIN  
Crystal  
C1  
C2  
Figure 6. Internal Clock Option  
external clock option  
An external frequency source can be used by injecting the frequency directly into X2/CLK, with X1 left  
unconnected. The external frequency injected must conform to specifications listed in the following table.  
switching characteristics over recommended operating conditions (see Note 3)  
MIN  
78.13  
12  
NOM  
MAX  
597  
UNIT  
ns  
t
t
t
t
t
t
CLKOUT1, CLKOUT2 cycle time  
c(C)  
CLKIN high to CLKOUT1, CLKOUT2, STRB high, low  
CLKOUT1, CLKOUT2, STRB fall time  
27  
ns  
d(CIH-C)  
f(C)  
4
ns  
CLKOUT1, CLKOUT2, STRB rise time  
4
ns  
r(C)  
CLKOUT1, CLKOUT2, STRB low pulse duration  
CLKOUT1, CLKOUT2, STRB high pulse duration  
2Q – 7  
2Q – 3  
2Q + 3  
2Q + 7  
ns  
w(CL)  
w(CH)  
ns  
CLKOUT1 high to CLKOUT2 low,  
CLKOUT2 high to CLKOUT1 high, etc.  
t
Q – 6  
Q + 2  
ns  
d(C1-C2)  
NOTE 3: Q = 1/4 t  
c(C)  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001  
35  
TMS320C25-50  
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990  
+5 V  
f
TMS320C25  
crystal  
10 kΩ  
74HC04  
4.7 kΩ  
F11  
CLKIN  
C = 20 pF  
0.1 µF  
47 pF  
74AS04  
10 kΩ  
L
f
(MHz)  
L, (µH)  
crystal,  
TMS320C25  
TMS320C25-50  
TMS320E25  
40.96  
51.20  
40.96  
1.8  
1.0  
1.8  
Figure 7. External Clock Option  
timing requirements over recommended operating conditions (see Note 3)  
MIN  
NOM  
MAX  
UNIT  
19.5  
t
CLKIN cycle time  
150  
ns  
c(CI)  
3
†
†
t
t
t
t
t
t
CLKIN fall time  
5
ns  
ns  
ns  
ns  
ns  
ns  
f(CI)  
CLKIN rise time  
5
r(CI)  
CLKIN low pulse duration, t  
= 50 ns (see Note 4)  
20  
20  
4
w(CIL)  
w(CIH)  
su(S)  
h(S)  
c(CI)  
CLKIN high pulse duration, t  
= 50 ns (see Note 4)  
c(CI)  
SYNC setup time before CLKIN low  
SYNC hold time from CLKIN low  
Q – 4  
4
†
Value derived from characterization data and not tested.  
NOTES: 3. Q = 1/4 t  
c(C)  
4. CLKIN duty cycle [t  
+ t must be within 40-60%.  
]/t  
r(CI) w(CIH) c(CI)  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001  
36  
TMS320C25-50  
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990  
MEMORY AND PERIPHERAL INTERFACE TIMING  
switching characteristics over recommended operating conditions (see Note 3)  
PARAMETER  
MIN  
Q – 5  
TYP  
MAX  
Q + 3  
5
UNIT  
ns  
t
t
t
t
t
t
t
t
t
t
t
STRB from CLKOUT (if STRB is present)  
d(C1-S)  
d(C2-S)  
su(A)  
CLKOUT2 to STRB (if STRB is present)  
– 2  
ns  
Address setup time before STRB low (see Note 5)  
Address hold time after STRB high (see Note 5)  
STRB low pulse duration (no wait states, see Note 6)  
STRB high pulse duration (between consecutive cycles, see Note 6)  
Data write setup time before STRB high (no wait)  
Data write hold time from STRB high  
Q – 11  
Q – 4  
ns  
ns  
n(A)  
2Q – 5  
2Q – 2  
2Q – 17  
Q – 5  
2Q + 2  
ns  
w(SL)  
w(SH)  
su(D)W  
h(D)W  
en(D)  
†
2Q + 5  
ns  
ns  
ns  
†
Data bus starts being driven after STRB low (write)  
Data bus high-impedance state after STRB high, (write)  
MSC valid from CLKOUT1  
0
ns  
†
Q
Q + 15  
ns  
dis(D)  
d(MSC)  
–1  
9
ns  
†
Value derived from characterization data and not tested.  
NOTES: 3. Q = 1/4 t  
c(C)  
5. A15-A0, PS, DS, IS, R/W, and BR timings are all included in timings referenced as “address”.  
6. Delay between CLKOUT1, CLKOUT2, and STRB edges track each other, resulting in t and t  
being 2Q with no wait states.  
w(SH)  
w(SL)  
timing requirements over recommended operating conditions (see Note 3)  
MIN  
NOM  
MAX  
UNIT  
ns  
t
t
t
t
t
t
t
t
t
Read data access time from address time (see Notes 5 and 7)  
Data read setup time before STRB high  
Data read hold time from STRB high  
3Q – 30  
a(A)  
19  
0
ns  
su(D)R  
h(D)R  
ns  
READY valid after STRB low (no wait states)  
READY valid after CLKOUT2 high  
Q – 21  
Q – 21  
ns  
d(SL-R)  
d(C2H-R)  
h(SL-R)  
h(C2H-R)  
d(M-R)  
h(M-R)  
ns  
READY hold time after STRB low (no wait states)  
READY valid after CLKOUT2 high  
Q – 1  
Q – 1  
ns  
ns  
READY valid after MSC valid  
2Q – 24  
ns  
READY hold time after MSC valid  
0
ns  
NOTES: 3. Q = 1/4 t  
c(C)  
5. A15-A0, PS, DS, IS, R/W, and BR timings are all included in timings referenced as “address”.  
7. Read data access time is defined as t = t + t – t  
.
a(A) su(A) w(SL) su(D)R  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001  
37  
TMS320C25-50  
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990  
RS, INT, BIO, AND XF TIMING  
switching characteristics over recommended operating conditions (see Notes 3 and 16)  
PARAMETER  
CLKOUT1 low to reset state entered  
MIN  
TYP  
MAX  
UNIT  
ns  
†
22  
t
t
t
d(RS)  
CLKOUT1 to IACK valid  
– 5  
7
ns  
d(IACK)  
d(XF)  
XF valid before falling edge of STRB  
Q – 8  
ns  
†
Value derived from characterization data and not tested.  
NOTES: 3. Q = 1/4 t  
c(C)  
16. RS, INT, BIO are asynchronous inputs and can occur at any time during a clock cycle.  
timing requirements over recommended operating conditions (see Notes 3 and 16)  
MIN  
NOM  
MAX  
UNIT  
t
t
t
t
t
INT, BIO, RS setup before CLKOUT1 high  
INT, BIO, RS hold after CLKOUT1 high  
INT, BIO fall time  
25  
ns  
su(IN)  
h(IN)  
f(IN)  
0
ns  
ns  
ns  
ns  
†
8
INT, BIO low pulse duration  
RS low pulse duration  
t
w(IN)  
w(RS)  
c(C)  
3t  
c(C)  
†
Value derived from characterization data and not tested.  
NOTES: 3. Q = 1/4 t  
c(C)  
16. RS, INT, BIO are asynchronous inputs and can occur at any time during a clock cycle.  
HOLD TIMING  
switching characteristics over recommended operating conditions (see Note 3)  
PARAMETER  
HOLDA low after CLKOUT1 low  
MIN  
TYP  
MAX  
UNIT  
ns  
†
t
t
t
t
t
1
11  
d(CIL-AL)  
dis(AL-A)  
dis(CIL-A)  
d(HH-AH)  
en(A-CIL)  
†
HOLDA low to address high-impedance  
0
ns  
†
Address high-impedance after CLKOUT1 low (HOLD mode, see Note 17)  
HOLD high to HOLDA high  
20  
ns  
19  
ns  
†
Address driven before CLKOUT1 low (HOLD mode, see Note 17)  
8
ns  
†
Value derived from characterization data and not tested.  
NOTES: 3. Q = 1/4 t  
c(C)  
17. A15-A0, PS, DS, STRB, and R/W timings are all included in timings referenced as “address”.  
timing requirements over recommended operating conditions (see Note 3)  
MIN  
NOM  
MAX  
UNIT  
t
HOLD valid after CLKOUT2 high  
Q – 19  
ns  
d(C2H-H)  
NOTE 3: Q = 1/4 t  
c(C)  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001  
38  
TMS320C25-50  
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990  
SERIAL PORT TIMING  
switching characteristics over recommended operating conditions (see Note 3)  
PARAMETER  
DX valid after CLKX rising edge (see Note 18)  
DX valid after falling edge (TXM = 0, see Note 18)  
FSX valid after CLKX raising edge (TXM = 1)  
MIN  
TYP  
MAX  
75  
UNIT  
ns  
t
t
t
d(CH-DX)  
d(FL-DX)  
d(CH-FS)  
40  
ns  
40  
ns  
NOTES: 3. Q = 1/4 t  
c(C)  
18. The last occurrence of FSX falling and CLKX rising.  
timing requirements over recommended operating conditions (see Note 3)  
MIN  
NOM  
MAX  
UNIT  
†
t
t
t
t
t
t
t
t
Serial port clock (CLKX/CLKR) cycle time  
Serial port clock (CLKX/CLKR) fall time  
Serial port clock (CLKX/CLKR) rise time  
160  
ns  
c(SCK)  
f(SCK)  
r(SCK)  
w(SCK)  
su(FS)  
h(FS)  
‡
‡
25  
25  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Serial port clock (CLKX/CLKR) low or high pulse duration (see Note 19)  
FSX or FSR setup time before CLKX, CLKR falling edge (TXM = 0)  
FSX or FSR hold time before CLKX, CLKR falling edge (TXM = 0)  
DR setup time before CLKR falling edge  
64  
5
10  
5
su(DR)  
h(DR)  
DR hold time after CLKR falling edge  
10  
†
‡
The serial port was tested at a minimum frequency of 1.25 MHz. However, the serial port was fully static but will properly function down to  
= 0 Hz.  
f
sx  
Value derived from characterization data and not tested.  
NOTES: 3. Q = 1/4 t  
c(C)  
19. The cycle of the serial port must be within 40%-60%.  
CONTRAST SUMMARY OF ELECTRICAL SPECIFICATIONS  
The following table presents electrical parameters which differ between TMS320C25 (40 MHz, 100 ns) and  
TMS320C25-50 (50 MHz, 80 ns).  
clock characteristics and timing  
TMS320C25  
TYP  
TMS320C25-50  
MIN TYP  
PARAMETER  
UNIT  
MIN  
MAX  
MAX  
t
t
t
t
t
t
t
t
t
97.7  
597  
78.13  
12  
597  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
c(SCK)  
d(CIH-C)  
f(C)  
5
30  
5
27  
4
5
4
r(C)  
2Q – 8  
2Q – 8  
Q – 5  
5
2Q  
2Q  
Q
2Q + 8 2Q – 7  
2Q + 8 2Q – 3  
2Q + 3  
2Q + 7  
Q + 2  
Q – 4  
w(CL)  
w(CH)  
d(C1-C2)  
su(S)  
Q + 5  
Q – 5  
Q – 6  
4
4
8
h(S)  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001  
39  
TMS320C25-50  
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990  
memory and peripheral interface timing  
TMS320C25  
TMS320C25-50  
MIN TYP  
UNIT  
PARAMETER  
MIN  
Q – 6  
– 6  
TYP  
Q
MAX  
Q+6  
6
MAX  
Q + 3  
5
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Q – 5  
– 2  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
d(C1-S)  
d(C2-S)  
su(A)  
0
Q – 12  
Q – 8  
Q – 11  
Q – 4  
2Q – 5  
2Q – 2  
2Q – 17  
Q – 5  
–1  
h(A)  
2Q  
2Q  
2Q + 2  
2Q + 5  
w(SL)  
w(SH)  
2Q – 20  
Q – 10  
– 12  
su(D)W  
h(D)W  
d(MSC)  
a(A)  
Q
0
12  
9
3Q – 35  
3Q – 30  
23  
0
19  
0
su(D)R  
h(D)R  
Q – 20  
Q – 20  
Q – 21  
Q – 21  
d(SL-R)  
d(C2H-R)  
h(SL-R)  
h(C2H-R)  
d(M-R)  
h(M-R)  
Q + 3  
Q + 3  
Q – 1  
Q – 1  
2Q – 25  
2Q – 24  
0
0
RS, INT, BIO, and XF timing  
TMS320C25  
TMS320C25-50  
UNIT  
PARAMETER  
MIN  
TYP  
MAX MIN TYP MAX  
t
t
t
t
– 6  
0
12  
– 5  
Q – 8  
25  
7
ns  
ns  
ns  
ns  
d(IACK)  
Q – 15  
d(XF)  
32  
0
su(IN)  
h(IN)  
0
HOLD timing  
TMS320C25  
TYP  
TMS320C25-50  
UNIT  
PARAMETER  
MIN  
MAX  
10  
MIN  
TYP  
MAX  
11  
t
t
t
0
1
ns  
ns  
ns  
d(C1L-AL)  
d(HH-AH)  
d(C2H-H)  
25  
19  
Q – 24  
Q – 19  
serial port timing  
TMS320C25  
TYP MAX  
TMS320C25-50  
UNIT  
PARAMETER  
MIN  
MIN  
TYP MAX  
t
t
t
t
t
t
t
75  
40  
40  
70  
40  
40  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
d(CH-DX)  
d(FL-DX)  
d(CH-FS)  
su(FS)  
18  
20  
10  
20  
5
10  
5
h(FS)  
su(DR)  
h(DR)  
10  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001  
40  
TMS320 SECOND-GENERATION  
DEVICES  
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990  
TIMING DIAGRAMS  
This section contains all the timing diagrams for the TMS320 second-generation devices. Refer to the top corner  
of page for the specific device.  
Timing measurements are referenced to and from a low voltage of 0.8 voltage and a high voltage of 2 volts,  
unless otherwise noted.  
clock timing  
t
c(CI)  
t
f(CI)  
t
r(CI)  
X/2CLKIN  
SYNC  
t
w(CIH)  
t
h(S)  
su(S)  
t
w(CIL)  
t
t
su(S)  
t
c(C)  
t
w(CL)  
d(CIH-C)  
t
d(CIH-C)  
t
CLKOUT1  
STRB  
t
w(CH)  
t
t
f(C)  
r(C)  
t
d(CIH-C)  
t
d(CIH-C)  
t
c(C)  
t
w(CL)  
CLKOUT2  
t
t
t
t
r(C)  
d(C1-C2)  
d(C1-C2)  
f(C)  
t
t
w(CH)  
d(C1-C2)  
t
d(C1-C2)  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001  
41  
TMS320 SECOND-GENERATION  
DEVICES  
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990  
memory read timing  
t
d(C1-S)  
CLKOUT1  
CLKOUT2  
STRB  
t
d(C1-S)  
t
t
d(C2-S)  
d(C2-S)  
t
w(SH)  
t
t
h(A)  
su(A)  
t
w(SL)  
Valid  
A15-A0,  
BR, PS, DS  
or IS  
t
a(A)  
R/W  
READY  
D15-D0  
t
d(SL-R)  
t
su(D)R  
t
t
h(D)R  
h(SL-R)  
Data In  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001  
42  
TMS320 SECOND-GENERATION  
DEVICES  
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990  
memory write timing  
CLKOUT1  
CLKOUT2  
STRB  
t
h(A)  
t
su(A)  
A15-A0,  
BR, PS, DS  
or IS  
Valid  
R/W  
READY  
D15-D0  
t
su(D)W  
t
h(D)W  
Data Out  
t
t
en(D)  
dis(D)  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001  
43  
TMS320 SECOND-GENERATION  
DEVICES  
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990  
one wait-state memory access timing  
CLKOUT1  
CLKOUT2  
STRB  
t
h(C2H-R)  
A15-A0, BR,  
PS, DS, R/W or  
IS  
Valid  
t
h(C2H-R)  
t
d(C2H-R)  
t
d(C2H-R)  
READY  
t
t
d(M-R)  
h(M-R)  
t
t
h(M-R)  
d(M-R)  
D15-D0  
(For Read  
Operation)  
Data In  
D15-D0  
(For Write  
Operation)  
Data Out  
t
d(MSC)  
t
d(MSC)  
MSC  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001  
44  
TMS320 SECOND-GENERATION  
DEVICES  
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990  
reset timing  
CLKOUT1  
t
su(IN)  
t
d(RS)  
t
su(IN)  
t
h(IN)  
RS  
A15-A0  
D15-D0  
PS  
t
w(RS)  
Valid  
Fetch  
Location 0  
Valid  
Begin  
Program  
Execution  
STRB  
Control  
†
Signals  
IACK  
Serial Port  
‡
Control  
†
‡
Control signals are DS, IS, R/W, and XF.  
Serial port controls are DX and FSX.  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001  
45  
TMS320 SECOND-GENERATION  
DEVICES  
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990  
interrupt timing (TMS32020)  
CLKOUT1  
STRB  
t
t
su(IN)  
h(IN)  
t
w(IN)  
INT2-INT0  
A15-A0  
IACK  
t
t
d(IACK)  
f(IN)  
FETCH N  
FETCH N + 1  
FETCH I  
FETCH I + 1  
t
d(IACK)  
interrupt timing (TMS320C25)  
CLKOUT1  
t
su(IN)  
STRB  
t
h(IN)  
t
w(IN)  
INT2-INT0  
A15-A0  
IACK  
t
f(IN)  
t
d(IACK)  
FETCH N  
FETCH N + 1  
FETCH N + 2  
N + 3  
FETCH I  
t
d(IACK)  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001  
46  
TMS320 SECOND-GENERATION  
DEVICES  
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990  
serial port receive timing  
t
c(SCK)  
t
r(SCK)  
t
w(SCK)  
CLKR  
t
h(DR)  
t
f(SCK)  
t
h(FS)  
t
w(SCK)  
FSR  
t
su(FS)  
t
su(DR)  
DR  
serial port transmit timing  
t
c(SCK)  
t
t
r(SCK)  
w(SCK)  
CLKX  
t
d(CH-DX)  
t
f(SCK)  
t
w(SCK)  
t
h(FS)  
FSX  
(Input,  
TXM = 0)  
t
t
d(CH-DX)  
su(FS)  
t
d(FL-DX)  
DX  
N = 1  
N = 8,16  
t
d(CH-FS)  
t
d(CH-FS)  
FSX  
(Output,  
TXM = 1)  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001  
47  
TMS32020  
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990  
BIO timing  
CLKOUT1  
STRB  
FETCH Branch Address  
PC = N + 1  
FETCH Next Instruction  
FETCH  
A15-A0  
BIOZ  
PC = N  
PC = N + 2  
PC = N + 3  
or Branch Address  
t
su(IN)  
t
h(IN)  
BIO  
Valid  
external flag timing  
CLKOUT1  
STRB  
t
d(XF)  
FETCH  
SXF/RXF  
A15-A0  
XF  
Valid  
Valid  
Valid  
PC = N – 1  
PC = N  
PC = N + 1  
PC = N + 2  
Valid  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001  
48  
TMS320C25  
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990  
BIO timing  
CLKOUT1  
STRB  
FETCH Branch Address  
PC = N + 1  
FETCH Next Instruction  
FETCH  
BIOZ  
A15-A0  
PC = N  
PC = N + 2  
or Branch Address  
t
su(IN)  
t
h(IN)  
BIO  
Valid  
external flag timing  
CLKOUT1  
STRB  
t
d(XF)  
FETCH  
SXF/RXF  
A15-A0  
XF  
Valid  
Valid  
Valid  
PC = N  
PC = N + 1  
PC = N + 2  
PC = N + 3  
Valid  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001  
49  
TMS32020  
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990  
HOLD timing (part A)  
CLKOUT1  
CLKOUT2  
STRB  
†
t
d(C2H-H)  
HOLD  
A15-A0  
N
N + 1  
Valid  
N + 2  
PS, DS,  
or IS  
Valid  
R/W  
D15-D0  
HOLDA  
t
dis(C1L-A)  
In  
In  
t
t
dis(AL-A)  
d(C1L-AL)  
N
N + 1  
N
N/A  
Dummy  
N/A  
FETCH  
N – 1  
Dead  
EXECUTE  
†
HOLD is an asynchronous input and can occur at any time during a clock cycle. If the specified timing is met, the exact sequence shown will occur;  
otherwise, a delay of one CLKOUT2 cycle will occur.  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001  
50  
TMS32020  
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990  
HOLD timing (part B)  
CLKOUT1  
CLKOUT2  
STRB  
t
en(A-C1L)  
†
t
d(C2H-H)  
HOLD  
A15-A0  
Valid  
Valid  
PS, DS,  
or IS  
R/W  
D15-D0  
HOLDA  
In  
In  
t
d(HH-AH)  
N + 2  
N + 3  
N/A  
N /A  
N + 2  
N + 1  
N + 3  
N + 2  
FETCH  
Dead  
Dead  
EXECUTE  
†
HOLD is an asynchronous input and can occur at any time during a clock cycle. If the specified timing is met, the exact sequence shown will occur;  
otherwise, a delay of one CLKOUT2 cycle will occur.  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001  
51  
TMS320C25  
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990  
HOLD timing (part A)  
CLKOUT1  
CLKOUT2  
STRB  
†
t
d(C2H-H)  
HOLD  
A15-A0  
N
N + 1  
Valid  
N + 2  
PS, DS,  
or IS  
Valid  
R/W  
D15-D0  
HOLDA  
t
dis(C1L-A)  
In  
In  
t
t
dis(AL-A)  
d(C1L-AL)  
N
N + 1  
–
–
–
FETCH  
N – 2  
N – 1  
N
EXECUTE  
†
HOLD is an asynchronous input and can occur at any time during a clock cycle. If the specified timing is met, the exact sequence shown will occur;  
otherwise, a delay of one CLKOUT2 cycle will occur.  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001  
52  
TMS320C25  
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990  
HOLD timing (part B)  
CLKOUT1  
CLKOUT2  
STRB  
t
en(A-C1L)  
†
t
d(C2H-H)  
HOLD  
PS, DS,  
or IS  
Valid  
R/W  
D15-D0  
HOLDA  
A15-A0  
In  
t
d(HH-AH)  
N + 2  
N + 2  
–
–
–
–
–
–
N + 2  
N + 1  
FETCH  
EXECUTE  
†
HOLD is an asynchronous input and can occur at any time during a clock cycle. If the specified timing is met, the exact sequence shown will occur;  
otherwise, a delay of one CLKOUT2 cycle will occur.  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001  
53  
TMS320 SECOND-GENERATION  
DEVICES  
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990  
TYPICAL SUPPLY CURRENT CHARACTERISTICS FOR TMS320C25  
I
vs f  
and V  
I
vs f and V  
(CLKIN) CC  
CC  
(CLKIN)  
CC  
CC  
Powerdown Mode  
Normal Operating Mode  
170  
160  
150  
140  
130  
120  
110  
100  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
V
V
V
V
V
= 5.50 V  
= 5.25 V  
= 5.00 V  
= 4.75 V  
= 4.50 V  
CC  
CC  
CC  
CC  
CC  
T
= 25°C  
A
V
V
V
V
V
= 5.50 V  
= 5.25 V  
= 5.00 V  
= 4.75 V  
= 4.50 V  
CC  
CC  
CC  
CC  
CC  
80  
70  
60  
50  
40  
30  
20  
10  
4
8
12 16 20 24 28 32 36 40 44 48 52  
, MHz  
4
8
12 16 20 24 28 32 36 40 44 48 52  
, MHz  
f
f
(CLKIN)  
(CLKIN)  
TMS320C25FNL (PLCC) reflow soldering precautions  
Recent tests have identified an industry-wide problem experienced by surface mounted devices exposed to  
reflow soldering temperatures. This problem involves a package cracking phenomenon sometimes  
experienced by large (e.g., 68-lead) plastic leaded chip carrier (PLCC) packages during surface mount  
manufacturing. This phenomenon occur if the TMS320C25FNL is exposed to uncontrolled levels of humidity  
prior to reflow solder. This moisture can flash to steam during solder reflow, causing sufficient stress to crack  
the package and compromise device integrity. If the TMS320C25FNL is being socketed, no special handling  
precautions are required. In addition, once the device is soldered into the board, nospecialhandlingprecautions  
are required.  
In order to minimize moisture absorption, TI ships the TMS320C25FNL in “dry pack” shipping bags with a RH  
indicator card and moisture-absorbing desiccant. These moisture-barrier shipping bags will adequately block  
moisture transmission to allow shelf storage for 12 months from date of seal when stored at less than 60%  
relative humidity (RH) and less than 30°C. Devices may be stored outside the sealed bags indefinitely if stored  
at less than 25% RH and 30°C.  
Once the bag seal is broken, the devices should be stored at less than 60% RH and 30°C as well as reflow  
soldered within two days of removal. In the event that either of the above conditions is not met, TI recommends  
these devices be baked in a clean oven at 125°C and 10% maximum RH for 24 hours. This restores the devices  
to their “dry packed” moisture level.  
NOTE  
Shipping tubes will not withstand the 125°C baking process. Devices should be transferred to a metal tray or tube be-  
fore baking. Standard ESD precautions should be followed.  
In addition, TI recommends that the reflow process not exceed two solder cycles and the temperature not  
exceed 220°C.  
If you have any additional questions or concerns, please contact your local TI representative.  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001  
54  
TMS320 SECOND-GENERATION  
DEVICES  
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990  
MECHANICAL DATA  
68-pin GB grid array ceramic package (TMS32020, TMS320C25)  
28,448 (1.120)  
27,432 (1.080)  
Thermal Resistance Characteristics  
17,02 (0.670)  
Nom  
PARAMETER  
MAX UNIT  
Junction-to-free-air  
thermal resistance  
R
R
36  
6
°C/W  
θJA  
28,448 (1.120)  
27,432 (1.080)  
Junction-to-case  
thermal resistance  
°C/W  
θJC  
17,02  
(0.670)  
Nom  
4,953 (0.195)  
2,032 (0.080)  
1,397 (0.055)  
Max  
1,575 (0.062)  
3,302 (0.130)  
2,794 (0.110)  
Dia  
1,473 (0.058)  
0,508 (0.020)  
0,406 (0.016)  
2,54  
(0.100)  
T.P.  
2,54  
(0.100)  
T.P.  
L
K
J
H
G
F
E
D
C
B
A
1,524 (0.060)  
Nom  
4 Places  
1
2
3
4
5
6
7
8
9
10 11  
1,27  
(0.050)  
Nom  
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001  
55  
TMS320C25  
TMS320C25-50  
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990  
68-lead plastic leaded chip carrier package (TMS320C25 and TMS320C25-50)  
Seating  
Plane  
1,27 (0.050) T.P.  
(see Note B)  
0,25 (0.010) R Max  
3 Places  
24,33 (0.956)  
24,13 (0.950)  
(see Note A)  
23,62 (0.930)  
23,11 (0.910)  
(At Seating Plane)  
25,27 (0.995)  
25,02 (0.985)  
0,94 (0.037)  
R
0,69 (0.027)  
1,22 (0.048)  
1,07 (0.042)  
× 45°  
1,35 (0.053)  
× 45°  
1,19 (0.047)  
24,33 (0.956)  
24,13 (0.950)  
(see Note A)  
2,79 (0.110)  
2,41 (0.095)  
25,27 (0.995)  
25,02 (0.985)  
4,50 (0.177)  
4,24 (0.167)  
0,81 (0.032)  
1,52 (0.060)  
Min  
Thermal Resistance Characteristics  
0,66 (0.026)  
PARAMETER  
MAX UNIT  
Junction-to-free-air  
thermal resistance  
0,64 (0.025)  
Min  
R
R
46  
11  
°C/W  
θJA  
Junction-to-case  
thermal resistance  
°C/W  
θJC  
0,51 (0.020)  
0,36 (0.014)  
Lead Detail  
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES  
NOTES: A. Centerline of center pin, each side, is within 0,10 (0.004) of package centerline as determined by this dimension.  
B. Location of each pin is within 0,127 (0.005) of true position with respect to center pin on each side.  
WARNING  
When reflow soldering is required, refer to page 54 for special handling instructions.  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001  
56  
TMS320E25  
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990  
MECHANICAL DATA  
68-lead FZ CER-QUAD, ceramic leaded chip carrier package (TMS320E25 only)  
This hermetically-sealed chip carrier package consists of a ceramic base, ceramic cap, and a 68-lead frame.  
Hermetic sealing is accomplished with glass. The FZ package is intended for both socket- or surface- mounting.  
Having a Sn/Pb ratio of 60/40, the tin/lead-coated leads do not require special cleaning or processing  
when being surface-mounted.  
A
4,57 (0.180)  
3,94 (0.155)  
(see Note 2)  
3,55 (0.140)  
3,05 (0.120)  
B
1,02 (0.040) × 45°  
1,27 (0.050) Typ  
(see Note 3)  
C
A
B
(At Seating  
Plane)  
(see Note 2)  
0,81 (0.032)  
0,66 (0.026)  
0,51 (0.020)  
0,36 (0.014)  
0,64 (0.025)  
R
Max  
3 Places  
(see Note 1)  
1,016 (0.040) Min  
Ref  
Thermal Resistance Characteristics  
3,05 (0.120)  
2,29 (0.090)  
MAX UNIT  
PARAMETER  
Junction-to-free-air  
thermal resistance  
R
R
49  
8
°C/W  
θJA  
Seating Plane  
(see Note 4)  
Junction-to-case  
thermal resistance  
°C/W  
θJC  
A
B
C
JEDEC  
NO. OF  
OUTLINE  
TERMINALS  
MIN  
MAX  
MIN  
MAX  
MIN  
MAX  
12,32  
(0.485)  
12,57  
(0.465)  
10,92  
(0.430)  
11,56  
(0.455)  
10,41  
(0.410)  
10,92  
(0.430)  
MO-087AA  
MO-087AB  
–––  
28  
44  
68  
17,40  
(0.685)  
17,65  
(0.695)  
16,00  
(0.630)  
16,64  
(0.655)  
15,49  
(0.610)  
16,00  
(0.630)  
25,02  
(0.985)  
25,27  
(0.995)  
23,62  
(0.930)  
24,26  
(0.955)  
23,11  
(0.910)  
23,62  
(0.930)  
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES  
NOTES: 1. Glass is optional, and the diameter is dependent on device application.  
2. Centerline of center pin, each side, is within 0,10 (0.004) of package centerline as determined by dimension B.  
3. Location of each pin is within 0,127 (0.005) of true position with respect to center pin on each side.  
4. The lead contact points are within 0,15 (0.006) of being planar.  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001  
57  
TMS320E25  
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990  
programming the TMS320E25 EPROM cell  
The TMS320E25 includes a 4K × 16-bit EPROM, implemented from an industry-standard EPROM cell, to  
perform prototyping and early field testing and to achieve low-volume production. When used with a 4K-word  
masked-ROM TMS320C25, the TMS320E25 yields a high-volume, low-cost production as a result of more  
migration paths for data. An EPROM adapter socket (part # TMDX3270120), shown in Figure 8, is available to  
provide 68-pin to 28-pin conversion for programming the TMS320E25.  
Figure 8. EPROM Adapter Socket  
Key features of the EPROM cell include standard programming and verification. For security against copyright  
violations, the EPROM cell features an internal protection mechanism to prevent proprietary code from being  
read. The protection feature can be used to protect reading the EPROM contents. This section describes  
erasure, fast programming and verification, and EPROM protection and verification.  
fast programming and verification  
The TMS320E25 EPROM cell is programmed using the same family and device codes as the TMS27C64  
8K × 8-bit EPROM. The TMS27C64 EPROM series are ultraviolet-light erasable, electrically programmable  
read-only memories, fabricated using HVCMOS technology. The TMS27C64 is pin-compatible with existing  
28-pin ROMs and EPROMs. The TMS320E25, like the TMS27C64, operates from a single 5-V supply in the  
read mode; however, a 12.5-V supply is needed for programming. All programming signals are TTL level. For  
programming outside the system, existing EPROM programmers can be used. Locations may be programmed  
singly, in blocks, or at random. When programmed in blocks, the data is loaded into the EPROM cell one byte  
at a time, the high byte first and the low byte second.  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001  
58  
TMS320E25  
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990  
Figure 9 shows the wiring conversion to program the TMS320E25 using the 28-pin pinout of the TMS27C64.  
The pin nomenclature table provides a description of the TMS27C64 pins. The code to be programmed into the  
device should be serial mode. The TMS320E25 uses 13 address lines to address the 4K-word memory in byte  
format.  
9
8
7
6
5
4
3
2
1 68 67 66 65 64 63 62 61  
60  
10  
TMS27C64  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
59  
58  
57  
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
V
CC  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
PGM  
EPT  
A8  
A9  
A11  
G
TMS320E25  
68-Pin (FZ)  
CLKIN  
A10  
E
Q8  
Q7  
Q6  
Q5  
Q4  
E
EPT  
V
PP  
A0  
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43  
8
Pin Nomenclature (TMS320E25)  
SIGNALS  
I/O  
DEFINITION  
A12 (MSB)-A0 (LSB)  
CLIN  
I
I
On-chip EPROM programming address lines  
Clock oscillator input  
E
EPT  
I
I
EPROM chip select  
EPROM test mode select  
G
GND  
I
I
EPROM read/verify select  
Ground  
PGM  
I
EPROM write/program select  
Data lines for byte-wide programming of on-chip 8K bytes of EPROM  
Reset for initializing the device  
5-V power supply  
Q8 (MSB)-Q1 (LSB)  
RS  
I/O  
I
I
I
V
V
CC  
PP  
12.5-V power supply  
Figure 9. TMS320E25 EPROM Conversion to TMS27C64 EPROM Pinout  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001  
59  
TMS320E25  
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990  
Table 5 shows the programming levels required for programming, verifying and reading the EPROM cell. The  
paragraphs following the table describe the function of each programming level.  
Table 5. TMS320E25 Programming Mode Levels  
SIGNAL  
NAME  
TMS320E25  
PIN  
TMS27C64  
PIN  
PROGRAM  
VERIFY  
PROGRAM  
INHIBIT  
OUTPUT  
DISABLE  
PROGRAM  
READ  
†
E
22  
42  
20  
V
V
V
V
V
IL  
IL  
PULSE  
IH  
IL  
PULSE  
IL  
IH  
IH  
G
22  
V
IH  
X
V
V
PGM  
41  
27  
PULSE  
V
IH  
X
V
IH  
V
25  
1
V
V
V
V
V
V
PP  
PP  
PP  
PP  
CC  
CC  
CC  
V
CC  
61,35  
27,44,10  
52  
28  
V
V
V
CC+1  
V
CC+1  
CC+1  
CC  
V
SS  
14  
V
SS  
V
SS  
V
SS  
V
SS  
V
SS  
V
SS  
V
SS  
V
SS  
V
SS  
V
SS  
V
SS  
V
SS  
V
V
V
V
V
V
V
V
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
CLKIN  
RS  
14  
65  
14  
EPT  
24  
26  
Q1-Q8  
A12-A10  
A9-A7  
A6  
18-11  
40-38  
37,36,34  
33  
11-13,15-19  
D
Q
HI-Z  
X
Q
OUT  
HI-Z  
X
IN  
OUT  
2,23,21,  
ADDR  
ADDR  
ADDR  
ADDR  
ADDR  
ADDR  
ADDR  
ADDR  
ADDR  
ADDR  
ADDR  
ADDR  
ADDR  
ADDR  
ADDR  
ADDR  
ADDR  
ADDR  
24,25,3  
X
X
4
5
X
X
A5  
32  
X
X
A4  
31  
3
X
X
A3-A0  
30-28,26  
7-10  
X
X
†
In accordance with TMS27C64.  
LEGEND;  
V
V
= TTL high level; V = TTL low level; ADDR = byte address bit  
IH  
IL  
= 12.5 V ± 0.5 V; V  
= 5 ± 0.25 V; X = don’t care  
CC  
PP  
PULSE = low-going TTL level pulse; D = byte to be programmed at ADDR  
Q
IN  
= byte stored at ADDR; RBIT = ROM protect bit.  
OUT  
erasure  
Before programming, the device is erased by exposing the chip through the transparent lid to high-intensity  
ultraviolet light (wavelength 2537 Å). The recommended minimum exposure dose (UV-intensity ×  
2
2
exposure-time) is 15 W•s/cm . A typical 12 mW/cm , filterless UV lamp will erase the device in 21 minutes. The  
lamp should be located approximately 2.5 cm above the chip during erasure. After erasure, all bits are in the  
high state. Note that normal ambient light contains the correct wavelength for erasure. Therefore, when using  
the TMS320E25, the window should be covered with an opaque label.  
fast programming  
After erasure (all memory bits in the cell are logic one), logic zeroes are programmed into the desired locations.  
The fast programming algorithm, shown in Figure 10, is normally used to program the entire EPROM contents,  
although individual locations may be programmed separately. A programmed logic zero can be erased only by  
ultraviolet light. Data is presented in parallel (eight bits) on pins Q8-Q1. Once addresses and data are stable,  
PGM is pulsed. The programming mode is achieved when V = 12.5 V, PGM = V , V  
= 6 V, G = V , and  
PP  
IL CC  
IH  
E = V More than one TMS320E25 can be programmed when the devices are connected in parallel. Locations  
IL  
can be programmed in any order.  
Programming uses two types of programming pulses: prime and final. The length of the prime pulse is 1 ms.  
After each prime pulse, the byte being programmed is verified. If correct data is read, the final programming  
pulse is applied; if correct data is not read, an additional 1-ms prime pulse is applied up to a maximum of 15  
times. The final programming pulse is 4 ms times the number of prime programming pulses applied. This  
sequence of programming and verification is performed at V  
= 6 V, and V  
= 12.5 V. When the full fast  
CC  
PP  
programming routine is complete, all bits are verified with V  
= V = 5 V.  
CC  
PP  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001  
60  
TMS320E25  
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990  
program verify  
Programmed bits may be verified with V = 12.5 V when G = V , E = V , and PGM = V . Figure 11 shows  
PP  
IL  
IL  
IH  
the timing for the program and verify operation.  
Start  
Address = First  
Location  
V
= 6 ± 0.25 V  
CC  
V
PP  
= 12.5 V ± 0.25  
V
X = 0  
Program One  
1-ms Pulse  
Increment X  
No  
Yes  
Fail  
Verify  
One  
X = 25?  
Byte  
Pass  
Program One  
Pulse of  
3X-ms Duration  
Device  
Failed  
No  
Last  
Address?  
Increment  
Address  
Yes  
V
CC  
= V  
= 5 V ± 0.25 V  
PP  
Fail  
Compare All  
Bytes to Original  
Data  
Pass  
Device  
Passed  
Figure 10. Fast Programming Flowchart  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001  
61  
TMS320E25  
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990  
Program  
Verify  
V
V
V
V
V
V
V
V
V
V
V
V
V
V
IH  
A12-A0  
Q8-Q1  
Address Stable  
HI-Z  
Address N + 1  
IL  
/V  
IH OH  
Data In Stable  
Data Out Valid  
/V  
IL OL  
PP  
CC  
CC + 1  
CC  
IH  
V
PP  
V
CC  
E
IL  
IH  
PGM  
G
IL  
IH  
IL  
Figure 11. Fast Programming Timing  
program inhibit  
Programming may be inhibited by maintaining a high level input on the E pin or PGM pin.  
read  
The EPROM contents may be read independent of the programming cycle, provided the RBIT (ROM protect  
bit) has not been programmed. The read is accomplished by setting E to zero and pulsing G low. The contents  
of the EPROM location selected by the value on the address inputs appear on Q8-Q1.  
output disable  
DuringtheEPROMprogrammingprocess, theEPROMdataoutputsmaybedisabled, ifdesired, byestablishing  
the output disable state. This state is selected by setting the G and PGM pins high. While output disable is  
selected, Q8-Q1 are placed in the high-impedance state.  
ROM protection and verification  
This section describes the code protection feature included in the EPROM cell, which protects code against  
copyright violations. Table 6 shows the programming levels required for protecting and verifying the EPROM.  
The paragraphs following the table describe the protect and verify functions.  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001  
62  
TMS320E25  
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990  
Table 6. TMS320E25 Protect and Verify EPROM Mode Levels  
†
SIGNAL  
TMS320E25 PIN  
TMS27C64 PIN  
ROM PROTECT  
PROTECT VERIFY  
E
G
22  
42  
20  
V
V
V
V
V
IH  
IL  
22  
IH  
IL  
PGM  
41  
27  
V
IH  
IH  
V
25  
1
V
V
V
PP  
PP  
CC  
CC  
V
CC  
61,35  
10, 27, 44  
52  
28  
V
CC + 1  
V
SS  
14  
V
SS  
V
SS  
V
SS  
V
PP  
V
V
V
V
SS  
SS  
SS  
PP  
CLKIN  
RS  
14  
65  
14  
EPT  
24  
26  
Q8-Q1  
18-11  
40-38  
37, 36, 34  
33  
11-13, 15-19  
Q8 = PULSE  
Q8 = RBIT  
A12-A10  
A9-A7  
A6  
2, 23, 21,  
X
X
X
X
X
X
24, 25, 3  
4
5
V
IL  
A5  
32  
X
A4  
31  
6
V
X
X
IH  
A3-A0  
30-28, 26  
7-10  
X
†
In accordance with TMS27C64.  
LEGEND;  
V
V
= TTL high level; V = TTL low level; V  
IL  
PP  
= 5 V ± 0.25 V  
CC  
IH  
= 12.5 V ± 0.5 V; X = don’t care  
PULSE = low-going TTL level pulse; RBIT = ROM protect bit.  
EPROM protect  
The EPROM protect facility is used to completely disable reading of the EPROM contents to guarantee security  
of propietary algorithms. This facility is implemented through a unique EPROM cell called the RBIT (EPROM  
protect bit) cell. Once the contents to be protected are programmed into the EPROM, the RBIT is programmed,  
disabling access to the EPROM contents and disabling the microprocessor mode on the device. Once  
programmed, the RBIT can be cleared only by erasing the entire EPROM array with ultraviolet light, thereby  
maintaining security of the propietary algorithm. Programming the RBIT is accomplished using the EPROM  
protect cycle, which consists of setting the E, G, PGM, and A4 pins high, V and EPT to 2.5 V ± 0.5 V, and  
PP  
pulsing Q8 low. The complete sequence of operations involved in programming the RBIT is shown in the  
flowchart of Figure 12. The required setups in the figure are detailed in Table 6.  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001  
63  
TMS320E25  
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990  
Start  
X = 0  
Program One  
Pulse of 3X-ms  
Duration  
EPROM  
Protect  
Setup  
Protect  
Verify  
Setup  
Program One  
1-ms Pulse  
Device  
Failed  
Verify  
RBIT  
Device  
Passed  
X = X + 1  
Yes  
X = 25?  
No  
Protect  
Verify  
Setup  
Fail  
Verify  
RBIT  
Pass  
EPROM  
Protect  
Setup  
Figure 12. EPROM Protect Flowchart  
protect verify  
Protect verify is used following the EPROM protect to verify correct programming of the RBIT (see Figure 12).  
When using protect verify, Q8 outputs the state of the RBIT. When RBIT = 1, the EPROM is unprotected; when  
RBIT = 0, the EPROM is protected. The EPROM protect and verify timings are shown in Figure 13.  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001  
64  
TMS320E25  
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990  
Protect  
Verify  
V
V
V
V
IH  
A4  
IL  
PP  
CC  
V
PP  
V
CC + 1  
V
CC  
V
CC  
IH  
V
E
V
IL  
V
IH  
PGM  
G
V
IL  
V
IH  
V
V
V
V
V
V
V
IL  
/V  
IH OH  
Q8  
HI-Z  
HI-Z  
HI-Z  
/V  
IL OL  
PP  
SS  
IH  
EPT  
A6  
IL  
Figure 13. EPROM Protect Timing  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001  
65  
INDEX  
TMS320 SECOND-GENERATION  
DEVICES  
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001  
66  
NIL  
NIL  
NIL  
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990  
microcomputer/microprocessor mode  
accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5  
multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7  
multiprocessing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9  
adapter socket . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58  
addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . 10  
ALU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5  
architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5  
operation conditions  
TMS32020 . . . . . . . . . . . . . . . . . . . . . . . . . . 17, 21  
TMS320C25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27  
TMS320C25-50 . . . . . . . . . . . . . . . . . . . . . . . . . 34  
TMS320E25 . . . . . . . . . . . . . . . . . . . . . . . . . 27, 33  
overflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17  
BIT instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17  
block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6  
Bulletin board Service . . . . . . . . . . . . . . . . . . . . . . 18  
clock  
overview  
TMS32020 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22  
TMS320C25/E25 . . . . . . . . . . . . . . . . . . . . . 28, 29  
TMS320C25-50 . . . . . . . . . . . . . . . . . . . . . . 35, 36  
TMS320 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5  
specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20  
package types . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5  
pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2  
pin nomenclature  
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
development support . . . . . . . . . . . . . . . . . . . . 18, 19  
direct addressing . . . . . . . . . . . . . . . . . . . . . . . 10, 17  
DMA documentation support . . . . . . . . . . . . . . . . 20  
TMS32020/C25/C25-50 . . . . . . . . . . . . . . . . . . . 2  
TMS320E25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60  
EPROM protection/verification . . . . . . . . . . . . 58-65  
external interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 9  
pinouts  
TMS32020/C25/C25-50 . . . . . . . . . . . . . . . . . . . 1  
TMS320E25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60  
programming levels for EPROM . . . . . . . . . . 58-65  
flowcharts  
EPROM protect . . . . . . . . . . . . . . . . . . . . . . . . . 63  
fast . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60, 61  
repeat feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10  
reflow soldering precaution . . . . . . . . . . . . . . . . . . 54  
hotline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18  
immediate addressing . . . . . . . . . . . . . . . . . . . . . . 10  
indirect addressing . . . . . . . . . . . . . . . . . . . . . . 10, 17  
instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . 10-16  
interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9  
introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
serial port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7, 9  
shifter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7  
specification overview . . . . . . . . . . . . . . . . . . . . . . 20  
subroutines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9  
supply current characteristics . . . . . . . . . . . . . . . . 54  
switching characteristics  
key features  
TMS32020 . . . . . . . . . . . . . . . . . . . . . . . 21, 23-26  
TMS320C25/E25 . . . . . . . . . . . . . . . . . . 27, 28-33  
TMS320C25-50 . . . . . . . . . . . . . . . . . . . 34, 35-40  
TMS320 family . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
TMS32020 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4  
TMS320C25/C25-50/E25 . . . . . . . . . . . . . . . . . . 4  
timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7  
mechanical data  
timing diagrams . . . . . . . . . . . . . . . . . . 41-53, 62, 65  
TMS320 Second-Generation . . . . . . . . . . . 41-47  
TMS32020 . . . . . . . . . . . . . . . . . . . 46, 48, 50, 51  
TMS320C25/E25 . . . . . . . . . . . . . . 46, 49, 52, 53  
TMS32020 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55  
TMS320C25 . . . . . . . . . . . . . . . . . . . . . . . . . 55, 56  
TMS320C25-50 . . . . . . . . . . . . . . . . . . . . . . . . . 56  
TMS320E25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57  
memory  
TMS3220 product notification . . . . . . . . . . . . . 17  
addressing modes . . . . . . . . . . . . . . . . . . . . 10, 17  
control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7  
maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001  
67  
PACKAGE OPTION ADDENDUM  
www.ti.com  
4-May-2009  
PACKAGING INFORMATION  
Orderable Device  
Status (1)  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
Drawing  
TMS320C25FNA  
NRND  
PLCC  
FN  
68  
18 Green (RoHS & CU NIPDAU Level-3-260C-168 HR  
no Sb/Br)  
TMS320C25FNAR  
TMS320C25FNL  
NRND  
NRND  
PLCC  
PLCC  
FN  
FN  
68  
68  
TBD  
Call TI  
Call TI  
18 Green (RoHS & CU NIPDAU Level-3-260C-168 HR  
no Sb/Br)  
TMS320C25FNL33  
TMS320C25FNLR  
OBSOLETE  
NRND  
PLCC  
PLCC  
FN  
FN  
68  
68  
TBD  
Call TI  
Call TI  
250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR  
no Sb/Br)  
TMS320C25FNLW  
OBSOLETE  
PLCC  
FN  
68  
Green (RoHS & CU NIPDAU Level-3-260C-168 HR  
no Sb/Br)  
TMS320C25GBA  
TMS320C25GBL  
TMS320C25PHL  
NRND  
NRND  
NRND  
CPGA  
CPGA  
QFP  
GB  
GB  
PH  
68  
68  
80  
21  
21  
TBD  
TBD  
AU  
AU  
N / A for Pkg Type  
N / A for Pkg Type  
66 Green (RoHS & CU NIPDAU Level-4-260C-72 HR  
no Sb/Br)  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2)  
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check  
http://www.ti.com/productcontent for the latest availability information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements  
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered  
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and  
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS  
compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame  
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)  
(3)  
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder  
temperature.  
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI  
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OTHER QUALIFIED VERSIONS OF TMS320C25 :  
Military: SMJ320C25  
•
NOTE: Qualified Version Definitions:  
Military - QML certified for Military and Defense Applications  
•
Addendum-Page 1  
IMPORTANT NOTICE  
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