AUTOMOTIVE
Xilinx Automotive –
Flexible Solutions Beyond Silicon
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IMAGE PROCESSING
AND RECOGNITION
Xilinx Automotive FPGAs are being utilized as key components in the deployment of
vision-based Driver Assistance Systems:
• Superior computational performance to support pixel-level image processing
• Scalability for multiple feature bundling and customization on a single platform
• Flexibility for time-to-market and processing algorithm evolutionary enhancement
Xilinx Automotive and its alliance members offer a combination of image processing IP
solutions and design services tailored to automotive market needs:
• Productized IP cores provide fundamental image processing functionality and serve as
building blocks for customer-implemented designs
• Specialized design services leverage FPGA design experts with image processing experience
for efficient design and implementation efforts (turn-key or collaborative)
• Application-specific development boards for proof-of-concept implementation
Vision-based Automotive Applications
Forward-Looking Example: Lane Departure Warning
Rear-Looking Example: Back-up/Park Aid
DDC's Automotive VADR module provides an
FPGA-based image processing platform with the
ability to record raw roadway video data in the field
for laboratory evaluation.
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VIDEO AND GRAPHICS
Hybrid Instrument Cluster
Scalability and Flexibility
The scalability and flexibility of FPGAs can be
leveraged by the system architect in multiple ways.
For example, in driver information applications, the
increased usage of LED background lighting in today's
instrument clusters requires sophisticated control of
the individual LEDs to match the exact color and
brightness in OEM specifications.
Based on production variances of the LEDs, along with
varying numbers and arrangements inside the clusters,
achieving high production yields has become difficult
and now requires individual end-of-line programmability,
easily achievable with FPGA technology.
Easy LCD Interfacing
Deployment of hybrid instrument clusters consisting
of various numbers of traditional analog gauges,
with the addition of an LCD TFT display, poses further
challenges to the developer. Built-in support on
Spartan™-3 generation products for low-swing
differential I/O standards, such as Reduced Swing
Differential Signaling (RSDS), make external
terminating resistors obsolete by simultaneously
simplifying the physical connection between the
FPGA and the display.
Flexible Graphics Display
Controller System
Different kinds of display connections, as well as
resolutions, can easily be overcome with the highly
scalable and flexible FPGA approach, covering a
complete range of needs from simple text, to 2D
animation, to graphics-intensive 3D representations.
Automotive
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Xylon® Graphics Display Controller Solution
• Xylon Graphics Display Controller solution features a set of
configurable IP that is fully compatible with the Xilinx EDK
Platform Studio, allowing for complete systems with optional
Microblaze™ embedded processor with little, or no, VHDL
coding required
3D Graphics Accelerator
• Xylon IP cores combined with a Spartan XA FPGA scale
very efficiently, thus making it possible to size the FPGA
to a particular end-product configuration, and optimize
cost-per-function without changing platform architecture
or board design
• Graphics subsystems can be assembled with the appropriate
features that are well suited to an entire range of low- to
high-performance graphics systems, with or without video
support, all at a competitive cost
• Scaling the number of displays to two or more in a system,
such as Rear-Seat Entertainment, is now possible on a
single FPGA
Supporting a Wide Range of Applications
• Low-end graphics systems, such as message centers or HVAC
control, requiring display functions such as blend, fade, scroll,
and simple animation of graphic objects through the use of a
multilayer alpha blended LCD controller and basic 2D
acceleration
• Mid/High-end graphics systems, such as fully reconfigurable
LCD instrument clusters or Rear-Seat Entertainment systems,
requiring additional operations such as bitmap decompression,
anti-aliased scalable fonts, bitmap rotation, and bitmap
translation/scaling
• High-end graphics systems, such as navigation or advanced
user interfaces, requiring real time manipulation of 3D graphics
including texture rendering, shading, or other true 3D effects
Xylon graphics software support ranges from basic embedded
graphic libraries (i.e. Segger emWIN) to complete end-to-end
development solutions including GUI development environments
(i.e. Altia) and industry standard interfaces (i.e. OpenGL ES).
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APPLICATION
DEVELOPMENT PLATFORMS
IogiCRAFT2
The logiCRAFT2 provides designers with an evaluation and development platform targeted for multi-
display automotive infotainment systems, such as rear-seat entertainment products. Using a completely
field-configurable platform, it combines the highly popular Xilinx MicroBlaze 32-bit microprocessor core
together with a wide range of graphics and display controller IP modules from Xylon’s logicBRICKS™ IP
core family. Based on a Xilinx Spartan-3 FPGA 1.5 million system gate platform, it is capable of:
• Driving up to three different displays simultaneously, including configurable power supply voltages
for each, with different video streams on each display
• Supporting a wide variety of video input and output standards, including: LVDS, CMOS, digital and
analog RGB, COG and CVBS
• Providing complementary audio inputs and outputs, including infrared-based audio transmission for
wireless headphone utilization
• Connectivity to automotive bus systems, such as LIN, CAN and MOST® standards, as well as other
industry standards such as RS232, USB and Ethernet
IogiCRAFT3
The logiCRAFT3 is derived from the logiCRAFT2 platform utilizing a smaller form factor, ideally to fit
behind a 7“ LCD, targeting single and remote display applications in the automotive environment.
It is based on a completely field-configurable platform combining the Xilinx MicroBlaze 32-bit micro-
processor core together with the wide range of graphics and display controller IP modules from
Xylon’s logicBRICKS IP core offerings.
• The platform supports a wide variety of simultaneous video input and output standards, such as CVBS
or S-Video supporting PAL/NTSC/SECAM as well as one/two twisted pairs 1-wire LVDS based on APIX
by Inova—COG displays as well as different COG power supply requirements are also supported
• Audio input and output capabilities
• Connectivity is provided via CAN and RS232; in addition, it can be optionally extended with an Apple
iPod compatible serial interface, as well as a Bluetooth module based on Cambridge Silicon Radio
• Provisions to control a touch screen are also offered
XA1600E Board
The Automotive ECU Development Kit (HW-XA3S1600E-UNI-G) provides designers with a configurable
and expandable out-of-the-box platform, suitable for a wide range of Automotive applications. Due to
its small form factor, it can easily be placed in a standard metal housing. The board has also been
designed to be powered by a 12 volt power supply for in-vehicle prototype use.
• Powered by a completely field-configurable platform running on a Xilinx Spartan-3E FPGA, it combines
programmable logic for custom-driven IP applications as well as the popular Xilinx MicroBlaze32-bit
microprocessor core
• Features robust memory subsystem containing on-board Flash and SRAM memory
• Supports standard Automotive and System-on-Chip peripherals including all necessary physical layers
on-board the ECU, such as JTAG, 10/100 Ethernet, USB 2.0, 12-bit ADC, High- and Low-Speed CAN,
FlexRay™, LIN, K-Line, UART, SPI and over 150 user programmable I/Os
Automotive
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logiCRAFT3
logiCRAFT2
Power Supply
Video Out 3
Power Supply
LED
Touch
Screen
Voltage
Indicators
Hirose DF11
Backlight PSU
2 x Resistive
Touch Screen
Conn.
Voltage
Indicators
2 x
Dia. RGB &
Touch Screen
Board
PSU
COG PSU &
Sequencing
COG Ctrl.
COG VCOM
GAMMA PSU
Hirose DF11
Video Out 1 & 2
Board
PSU
COG PSU &
SEQUENCING
2 x Digital
RGB
Hirose DF11
Vehicle Connectivity
2 x S-Video
Video Out 1
2 x VGA DAC,
Analog RGB
MOST
FOT
MOST IDT
PLL
Dig. RGB & COG
Ctrl. Hirose DF11
CVBS
Vehicle Connectivity
2 x DVI
S-Video CVBS
2xRCA
2 x DB9
Male
2x
2 x DVI Tx
CVBS
CAN
2 x LVDS
DB9 Male
DB9 Male
CAN PHY
Encoder
PHY
Hirose DF11
LVDS
Hirose DF11
2 x DB9
Male
2x
LIN PHY
Video IN 1 & 2
CAN
PHY
1 x LVDS
Hirose DF11
DB9
Male
FlexRay
PHY
2 x Video
Decoder
Video IN 1 & 2
Video
MUX 4x2
2 x S-Video
(4xCVBS)
2x S-Video,
(4xCVBS)
4 x RCA
Video
Amplifier
and
Video
Decoder
Application Connectivity
Application Connectivity
2 x VGA ADC,
Analog
5 Pin .1”
DB9
Female
Debug App.
RS232 PHY
RGB
2 x DVI
MUX 4x2
To iPod
single row
header
Video
Decoder
2 x DVI Rx
Ethernet
PHY
RJ45
Digital RGB
Hirose FX2-60
To
Hirose
DF11
LVDS
Transceiver
Bluetooth
Module
Video CLK
PLL
Digital RGB
Hirose FX2-60
USB OTG
PHY
MiniA/B
Video CLK
PLL
Audio
2x
Firewire
Hirose
DF11
Firewire
PHY
2 x Mono Mic
Micro Jack
GPIO
Extender
8 GPIO’s
1/2 Stereo
CODEC ADC
Stereo
Audio
MUX 4x2
Audio
4 x Stereo Line
IN Micro Jack
Mono Mic
PCB Pad
Memory and Configuration
Debug App.
RS23
PHY
1/2 Stereo
CODEC DAC
DB9 Female
128MB/64-bit
DDRAM
1/2 Stereo
CODEC ADC
4x Stereo Line
IN 4x RCA and
4vx PCB Pads
2 x Stereo Line
Out Micro Jack
Stereo
Audio
Amplifier
MUX 4x2
8MB/16-bit
NOR Flash
CPLD
1/2 Stereo
CODEC DAC
2 x Stereo
Headphones
Micro Jack
Memory and Configuration
2 x IR Stereo
Audio Channels
Stereo Line
Out PCB Pad
16MB/32-bit
SDRAM
Stereo
Headphones
PCB Pad
2 x IR Stereo
Ch. Hirose DF11
User Expansion Header
BPI Config
JTAG
Switches
8MB/8-bit
NOR Flash
5 Push Buttons or 5x5
8 x LED
Key Matrix 8 DIP SW
Hirose FX2-60 Hirose FX2-60
40 FPGA IOB 40 FPGA IOB
Remote Control
RST Ctrl.
JTAG
Remote Control
RST Ctrl.
OSC 33MHz
OSC
33MHz
XA1600E
3S1600E
External
Power Input
Vehicle Connection Port
D-SUB 44 Pin Male
Vehicle Connection Port
D-SUB 44 Pin Male
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XILINX AUTOMOTIVE
Image Processing and Recognition
Xilinx and its alliance members offer solutions beyond silicon by providing IP building blocks and design
services in the areas of image processing and recognition. This allows for faster development and product
differentiation for driver assistance applications, including:
• Night Vision
• Lane Departure Warning
• Park Assist
• Back Guide Monitor
• Adaptive Cruise Control
• Drowsy Driver Detection
Courtesy of Robert Bosch GmbH
Video and Graphics
Offerings of key IP building blocks and design services allow for highly scalable
and cost-efficient implementations of infotainment and driver information
systems, including:
• Head-Unit
• Rear-Seat Entertainment
• TV Tuner
• Audio/Multimedia Systems
• Game Consoles
• Hybrid Instrument Cluster
• Heads-up Display
Application Development Platforms
Off-the-shelf, application-specific development platforms are available to provide developers a quick start,
and serve as a comprehensive hardware base to satisfy their expectations. Currently available are:
• Automotive ECU Development Kit (HW-XA3S1600E-UNI-G)
• logiCRAFT2—Infotainment Development Platform
• logiCRAFT3—Compact Multimedia Display Development Platform
• VADR—Image Processing Development Platform
Automotive
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E -- AT A GLANCE
Xilinx Technology Leadership
Xilinx leads the way in Programmable Logic Devices (PLDs), one of the fastest growing
segments of the semiconductor industry.
• Inventing and driving the technology of the Field Programmable Gate Array (FPGA)
• Offering highly scalable and flexible devices, where features and functions can be
changed “on the fly,“ or upgraded in the field
• Supplying more than 50% of the market for these devices today
• Expert design services through Xilinx and third party providers
• Full compliance and certification to ISO-9001,
ISO-14001 and ISO/TS16949
Xilinx Automotive Products
Xilinx Automotive solutions are driven by
a dedicated automotive product line,
based on:
• Pin-compatible products in various densities and packages suited for
automotive applications
• AEC-Q100 qualified products
• Production Part Approval Process (PPAP) documentation for all XA products
• A continuous improvement strategy
• Active membership in the Automotive Electronics Council (AEC) Technical
Specification Committee
• Associate membership in AUTOSAR, JASPAR, MOST Cooperation and
FlexRay Consortium
Vehicle Networking
Xilinx has designed, and is directly supporting, key automotive-specific
network interfaces. Xilinx works together with leading industry companies
to provide customers access to a comprehensive solution.
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VEHICLE NETWORKING
This super-set block diagram of an infotainment rear-seat
entertainment application shows a possible set-up based on
the combination of a host or digital signal processor (DSP)
together with an FPGA. In this example, the FPGA acts as
a companion chip to the host, providing multiple functions,
such as audio/video processing acceleration, a graphics
sub-system, and different user and vehicle networking
connections, such as CAN and MOST.
_
The following overview outlines four architectural options
Flexible MOST Architecture your design, your way
showing how various components within the Xilinx solution
for MOST, including the MOST Network Interface Controller
(NIC), can be utilized to realize efficient system architectures.
There are many possible combinations that are not constrained
by fixed or predetermined interfaces, but can be
freely defined based on the desired overall system
architecture.
1. Off-loading the host processor by utilizing
the MicroBlaze processor to run the full
MOST Network Services software stack
along with OEM-specific FBlocks and High-
Level-Protocols in conjunction with the
OS8104 (PCM IP) or OS81050 (MLB IP).
2. Utilization of available LogiCORE IP to
completely eliminate the need for an external
MOST network controller.
3. Addition of direct access to the synchronous
MOST channels to perform pre- or post-
processing of incoming or outgoing data in
FPGA hardware without the need for any
software overhead.
4. Connectivity to a wide range of different
host interfaces.
Automotive
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MOST Solution
The LogiCORE IP for the Media Oriented Systems Transport (MOST) is a complete
NIC supporting the MOST Specification revision 2.4 or later for the MOST25
network. Capabilities include:
MOST IP
Object Layer
Transfer Layer
Transmit
Media
TX
Transmit
Buffer
MCLK
FOT
Access
Control
• Compatible with SMSC 8104(A), OS8105x (INIC) and Analog Devices
MXVR transceivers
32 bit
OPB or
PLBv46
Bus
Control
Processing
Config
Registers
Bypass
MOST Ring
Receive
Media
Access
Control
• Direct interface to MOST ring via IDT PLL (IDT5V80001) for clock
generation/recovery and the fiber optic transceiver (FOT)
RCLK
RX
FOR
Receive
Buffer
• Operates in both master and slave modes
• Synchronous, asynchronous, and control channels with 4-60 bytes of
synchronous data per frame including support of up to full bandwidth
sustained transfers (24 Mbps)
Local Link
Local Link
TX
Streaming
Port
RX
Streaming
Port
• Streaming port allows synchronous data co-processing with low host
controller overhead
• Full support of error and status notification including support for ring break
diagnosis test
MOST IP Specifics
Spartan-3, Spartan-3E, Spartan-3A, Spartan-3A DSP
Supported XA Device Families
Resources Used
• Supported in CORE Generator™ software for stand alone applications and in
EDK for MicroBlaze-based ECU applications
I/O
7
LUTs
FFs
Block RAMs
6
Slices*
2930-2990
4049-4117
2535-2580
* Represent typical slice count for Spartan-3 generation devices. Results will vary on device utilization and ISE options
Working closely with Mocean Laboratories AB, and the MOST Cooperation, Xilinx
enables a portable and highly modular MOST solution where applications can
be moved between NICs without source code modification. The MOST solution
is comprised of:
Application
HLP’s (Software Download, Diagnostics, etc)
Layer 7 Application
FBlocks
MOST Network Services Layer 2 API
• Full software stack (up to MOST Specification revision 2.5) supporting Xilinx
solution for MOST
Layer 6 Presentation
Supervisor L2
(MSV2)
Network Service
L2 (NSV2)
• Versions also available supporting SMSC OS8104(A) and OS8105x (INIC)
for MicroBlaze processor
Command Interpreter (MCI)
Layer 5 Session
MOST Network Services Layer 1 API
• All services and protocols standardized in the MOST Cooperation are supported
Supervisor L1
(MSV)
Layer 4 Transport
Network
Service L1
(NSV)
• MOST Cooperation and several OEM FBlocks and High-level Protocol Modules
available including source code
Transceiver
Control Service Interface Control
(XCS) (OIC)
Optical
Layer 3 Network
Layer 2 Data Link
Layer 1 Physical
Control Message Service (CMS)
• Fully linked/structured electronic documentation
Low-Level Driver
Network Interface Controller Abstraction
• ANSI-C Source code with automated documentation generation
• Browse documentation using Service, Module, Function or Variable views
• Application examples library available as source code
MOST Network Interface Controller
Optical/electrical converters, connectors and optical fiber
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CAN Solution
The LogiCORE IP for the Controller Area Network (CAN) is a
controller compliant to ISO 11898-1, CAN 2.0A and CAN 2.0B
standards. It provides characteristics such as:
CAN IP
Object Layer
Transfer Layer
TX
TX
Priority
Logic
Transmit
Buffer
• Validated at C&S group
Bit Stream
Processor
Transmit
High
• Supports bit rates of up to 1 Mbps
32 bit
OPB or
PLBv46
Bus
Priority
Buffer
• Supports both standard (11-bit identifier) and extended
(29-bit identifier) frames
Configuration
Registers
• Transmit and receive message FIFOs with user-configurable
depths of up to 64 messages
Bit Timing
Module
CLK
RX
Receive
FIFO
Acceptance
Filtering
• Transmit prioritization through one High-Priority Transmit buffer
• Acceptance filtering (user-configurable number) of up to
4 acceptance filters
• Maskable Error and Status Interrupts
• Supported in CORE Generator software for stand alone applications
and in EDK for MicroBlaze-based ECU applications
CAN IP Specifics
Spartan-3, Spartan-3E, Spartan-3A, Spartan-3A DSP
Supported XA Device Families
Resources Used
I/O
3
LUTs
868-1056
FFs
411-593
BlockRAMs
2
Slices*
569-885
Working closely with Vector, the availability of the CAN Driver for
the Xilinx MicroBlaze 32-bit processor, enables easy access to the
full suite of Vector’s CANbedded Software solution.
* Represent typical slice count for Spartan-3 generation devices. Results will vary on device utilization and ISE options
• The CAN Driver handles the hardware-specific characteristics
of the Xilinx FPGA and provides the initialization, wakeup
detection, transmission and reception of messages with
data—and functional interface data—and functional
notification including indication and confirmation as
well as overrun and error handling
Universal
Application
Measurement
and Calibration
Protocol
Network
Management
Diagnostics
• Provision of a standardized application
Interaction
Layer
Configuration
Tool
Communication
Control
Layer
interface to the higher level software modules
as the interaction layer, transport protocol,
network management, universal measurement
Transport Protocol
and calibration protocol also available through Vector
CAN Driver
• Several diagnostics layers available in accordance with
ISO14229 (UDS) and ISO14230 (Keyword Protocol 2000)
Xilinx LogiCORE IP CAN Controller
Transceiver
• Full integration into the Vector tools chain including flash
programming, operating system, database and debug tools
CAN
Courtesy of Vector Group
Automotive
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FlexRay Solution
The LogiCORE IP for FlexRay is a controller that implements the
FlexRay communication protocol as defined in the FlexRay Protocol
Specification v2.1 Rev A. It provides functionalities such as:
FlexRay IP
Controller Host
Interface
Protocol Engine (PE)
Media
Bit
Stream
Engine
TX
Transmit
Buffer
Access
• Data rate of up to 10 Mbps
Control
TX_EN
• Single Communication Channel
Config/
Status
Clock
Sync
32 bit
OPB or
PLBv46
Bus
Register
Protocol
Operation
Control
• Scalable synchronous and asynchronous data transmission
• Configurable payload length up to a maximum of 256 bytes
Config/
Status
Register
Wakeup
& Start
• Configurable receive and transmit buffers for storage of up to
RX
Frame &
Symbol
Proc.
Bit
Stream
Decode
Receive
FIFO
128 messages each
• Frame ID, cycle counter and message ID based receive filtering
• OPB and PLB interface suitable with single and burst support
• Variable OPB and PLB interface clock
• Supported in CORE Generator software for stand alone
applications and in EDK for MicroBlaze-based ECU applications
FlexRay IP Specifics
Supported XA Device Families
Resources Used
Spartan-3, Spartan-3E, Spartan-3A, Spartan-3A DSP
LUTs FFs Block RAMs Slices*
5506-6587 3179-3386 9 to 18 4028-4789
I/O
5
* Represent typical slice count for Spartan-3 generation devices. Results will vary on device utilization and ISE options
Availability of the FlexRay Driver for the Xilinx MicroBlaze
32-bit processor enables easy access to the full suite of
Vector’s FlexRay software solution developed according to
Software
Component
Software
Component
Software
Component
Software
Component
Software
Component Component
Software
the AUTOSAR specification.
• The FlexRay Driver handles the hardware-specific
characteristics of the Xilinx FPGA and acts as an abstraction
layer to other software offerings available through Vector,
covering the signal, diagnostic and transport layer as well
as the network support and node management
AUTOSAR Runtime Environment (RTE)
XCP Protocol
Layer
Diagnostic
Communication
Manager
Development
Error Tracer
NM
Interface
Communication
Manager
AUTOSAR COM
PDU Router
XCP Transport
Layer
on FlexRay
ECU State
AUTOSAR OS
FlexRay
Network
Management
FlexRay
State
Manager
Manager
FlexRay
Transport
Protocol
• Full support of the FlexRay synchronous layer for the
driver as well as support of the FlexRay asynchronous
layer for the protocol stack and the application
Diagnostic
Event
Manager
FlexRay Interface
FlexRay Driver
Transceiver
Driver
• Full integration into the Vector tool chain including the
DaVinci Network Designer for FlexRay supporting multiple
FIBEX revisions, the development & analysis tool with
real-time support, as well as measurement and calibrations
of ECUs
Xilinx LogiCORE IP FlexRay Controller
FlexRay
Vector AUTOSAR BSW
BSW of FlexRay-Stack
XCP Communication
Module
AUTOSAR
Service Layer
AUTOSAR ECU
Abstraction Layer
AUTOSAR ECU
Microcontroller
Abstraction Layer
Courtesy of Vector Group
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XILINX AUTOMOTIVE
DEVICES
FPGAs
Spartan-IIE
Spartan-3
Spartan-3E
XA2S50E
50K
XA2S100E
100K
XA2S150E XA2S200E XA2S300E
XA3S50
50K
XA3S200 XA3S400 XA3S1000 XA3S1500 XA3S100E XA3S250E XA3S500E XA3S1200E XA3S1600E
Part Number
System Gates (1)
Slices (2)
150K
1,728
3,888
200K
2,352
5,292
300K
3,072
6,912
200K
400K 1000K 1500K
250K
2,448
5,508
500K
1200K
1600K
14,752
100K
960
768
1,200
2,700
768
1,920 3,584 7,680 13,312
4,320 8,064 17,280 29,952
3,840 7,168 15,360 26,624
4,656
8,672
Logic Resources
Logic Cells
1,728
1,728
2,160
10,476 19,512 33,192
CLB Flip-Flops
Maximum Distributed RAM (Kbits)
Block RAM Blocks
1,536
24
2,400
37
3,456
54
4,704
73
6,144
96
1,536
12
1,920
15
4,896
38
9,312
73
17,344 29,504
30
12
56
16
120
24
208
32
136
28
231
36
Memory Resources
Clock Resources
8
10
12
14
16
4
4
12
20
Total Block RAM (Kbits)
32
40
48
56
64
72
216
288
432
576
72
216
360
504
648
Digital Clock Managers
(DCMs) Spartan-3, (DLLs) Spartan-IIE
4
4
2
4
4
4
4
4
4
4
2
4
4
8
8
Maximum Single Ended I/Os
102
102
182
83
182
83
182
83
124
56
173
76
264
116
333
149
487
108
172
190
77
304
124
376
156
Maximum Differential I/O Pairs
28
28
221
40
68
LVTTL, LVCMOS33, LVCMOS25, LVCMOS18, LVCMOS15,
LVCMOS12, GTL, GTL+, HSTL15 Class I, HSTL15 Class III,
HSTL18 Class I, HSTL18 Class II, HSTL18 Class III, PCI 3.3V
32/64bit 33MHz, SSTL2 Class I, SSTL2 Class II, SSTL18
Class I, Bus LVDS, LDT (ULVDS), LVDS_ext, LVDS25 & 33,
LVPECL25, RSDS25
VCMOS15,
LVTTL, LVCMOS33, LVCMOS25, LVCMOS18, L
LVCMOS12, HSTL18 Class I, HSTL18 Class III,
LVTTL, LVCMOS25, LVCMOS18, HSTL Class I, HSTL Class III,
HSTL Class IV, PCI 3.3V 32 - 33MHz, PCI-X 3.3V, SSTL3 Class I,
SSTL3 Class II, SSTL2 Class I, SSTL2 Class II,
I/O Resources
PCI 3.3V
8 Class I,
32/64bit 33MHz, PCI-X 3.3V, SSTL2 Class I, SSTL1
Bus LVDS, LVDS25, LVPECL25, Mini-LVDS25, RSDS25
I/O Standards Supported
AGP-2x, CTT, LVDS, Bus LVDS, LVPECL25 & 33
DSP48A Slices
—
—
—
—
—
—
—
—
—
—
—
4
—
12
—
16
—
24
—
32
—
4
—
12
—
20
—
—
36
Embedded Hard
IP Resources
Dedicated Multipliers
28
Device DNA Security
Temperature Range (4)
—
—
—
—
—
—
—
—
—
—
I
—
—
—
—
—
I, Q
I, Q
I, Q
I, Q
I, Q
I, Q
I, Q
I, Q
I, Q
I, Q
I, Q
I, Q
I, Q
I, Q
Speed Grade
-6
-6
-6
-6
-6
-4
-4
-4
-4
-4
-4
-4
-4
-4
-4
Miscellaneous
Configuration
RoHS (Pb-free)
No
No
No
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
XA Released
Yes
0.6
Yes
0.9
Yes
1.1
Yes
1.4
Yes
1.9
Yes
0.4
Yes
1.0
Yes
1.7
Yes
3.2
Yes
5.2
Yes
0.6
Yes
1.4
Yes
2.3
Yes
Yes
6.0
Configuration Memory Bits (Mbits)
3.8
Package
Area
Maximum User I/Os
VQFP Packages (VQ): very thin QFP (0.5 mm lead spacing)
VQG100 16 x 16 mm
63
63
66
83
66
92
Chip Scale Packages (CP): wire-bond chip-scale BGA (0.5 mm ball spacing)
CPG132 8 x 8 mm
92
TQFP Packages (TQ): thin QFP (0.5 mm lead spacing)
TQG144 22 x 22 mm
102
102
97
108
108
PQFP Packages (PQ): wire-bond plastic QFP (0.5 mm lead spacing)
PQG208 30.6 x 30.6 mm
124
141
173
141
173
158
158
FGA Packages (FT): wire-bond fine-pitch thin BGA (1.0 mm ball spacing)
FTG256 17 x 17 mm
182
182
182
173
333
172
190
190
304
FGA Packages (FG): wire-bond fine-pitch BGA (1.0 mm ball spacing)
FGG400
FGG456
FGG484
FGG676
21 x 21 mm
23 x 23 mm
23 x 23 mm
27 x 27 mm
304
376
264
333
487
Notes: 1. System Gates include 20%-30% of CLBs used as RAMs. 2. Each slice comprises two 4-input logic function generators (LUTs), two storage elements, wide-function multiplexers, and carry logic.
Integrated in the DSP48A slices (Advanced Multiply Accumulate element). 4. Temperature Range Automotive I (Tj = -40°C to +100°C); Automotive Q (Tj = -40°C to +125°C)
Automotive
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FPGAs
Spartan-3A
Spartan-3A DSP
XA3S200A XA3S400A XA3S700A XA3S1400A XA3SD1800A XA3SD3400A
Part Number
System Gates (1)
Slices (2)
200K
1,792
4,032
3,584
28
400K
3,584
8,064
7,168
56
700K
1400K
11,264
1800K
16,640
37,440
33,280
260
3400K
23,872
53,712
47,744
373
5,888
Logic Resources
Logic Cells
13,248 25,344
11,776 22,528
Dedicated Automotive Product Line
CLB Flip-Flops
Choose from our wide range of pin-compatible AEC-Q100
qualified products in various densities and packages suited
for automotive applications.
Maximum Distributed RAM (Kbits)
Block RAM Blocks
92
20
176
32
Memory Resources
Clock Resources
16
20
84
126
Total Block RAM (Kbits)
Digital Clock Managers (DCM)
Maximum Single Ended I/Os
Maximum Differential I/O Pairs
288
4
360
4
360
8
576
8
1,512
8
2,268
8
195
90
311
142
372
165
375
165
519
227
469
213
Offering extreme flexibility and reliability, our dedicated
XA products are at the heart of innovation.
I/O Resources
LVTTL, LVCMOS33, LVCMOS25, LVCMOS18, LVCMOS15, LVCMOS12, HSTL15
Class I, HSTL15 Class III, HSTL18 Class I, HSTL18 Class II, HSTL18 Class III,
PCI 3.3V 32/64bit 33MHz, PCI-X 3.3V, SSTL3 Class I, SSTL3 Class II, SSTL2
Class I, SSTL2 Class II, SSTL18 Class I, SSTL18 Class II, Bus LVDS, LVDS25 & 33,
LVPECL25 & 33, Mini-LVDS25 & 33, RSDS25 & 33, TMDS25 & 33, PPDS25 & 33
I/O Standards Supported
DSP48A Slices
Dedicated Multipliers
Device DNA Security
Temperature Range (4)
—
16
—
20
—
20
—
32
84
126
126 (3)
Yes
I
Embedded Hard
IP Resources
84 (3)
Yes
I, Q
-4
Yes
I, Q
-4
Yes
I, Q
-4
Yes
I, Q
-4
Yes
I, Q
-4
Speed Grade
-4
Miscellaneous
Configuration
RoHS (Pb-free)
Yes
Yes
Yes
Yes
Yes
Yes
XA Released
No
1.2
No
1.9
No
2.7
No
No
No
Configuration Memory Bits (Mbits)
4.8
8.2
11.7
Package
Area
Maximum User I/Os
FGA Packages (FT): wire-bond fine-pitch thin BGA (1.0 mm ball spacing)
FTG256 17 x 17 mm
Chip Scale Packages (CS): wire-bond chip-scale BGA (0.8 mm ball spacing)
CSG484 19 x 19 mm
FGA Packages (FG): wire-bond fine-pitch BGA (1.0 mm ball spacing)
195
195
309
519
309
469
FGG400
FGG484
FGG676
21 x 21 mm
23 x 23 mm
27 x 27 mm
311
311
372
375
Notes: 1. System Gates include 20%-30% of CLBs used as RAMs.
2. Each slice comprises two 4-input logic function generators (LUTs), two storage elements,
wide-function multiplexers, and carry logic.
3. Integrated in the DSP48A slices (Advanced Multiply Accumulate element).
4. Temperature Range Automotive I (Tj = -40°C to +100°C); Automotive Q (Tj = -40°C to +125°C).
CPLDs
XA9500XL Family
CoolRunner-II Family
XA9536XL XA9572XL XA95144XL
XA2C32A
XA2C64A
XA2C128
XA2C256
XA2C384
Part Number
System Gates
Macrocells
800
36
90
3
1,600
72
3,200
144
90
750
32
56
3
1,500
64
3,000
128
56
6,000
256
56
9,000
384
56
Logic Resources
Product terms per Macrocell
Global Clocks
90
56
3
3
3
3
3
3
Clock Resources
I/O Resources
Product Term Clocks per Function Block
Maximum I/O
18
18
18
16
33
16
64
16
16
16
34
72
117
100
118
118
Input Voltage Compatible (V)
2.5/3.3/5 2.5/3.3/5 2.5/3.3/5 1.5/1.8/2.5/3.3 1.5/1.8/2.5/3.3 1.5/1.8/2.5/3.3 1.5/1.8/2.5/3.3 1.5/1.8/2.5/3.3
2.5/3.3 2.5/3.3 2.5/3.3 1.5/1.8/2.5/3.3 1.5/1.8/2.5/3.3 1.5/1.8/2.5/3.3 1.5/1.8/2.5/3.3 1.5/1.8/2.5/3.3
Output Voltage Compatible (V)
Min. pin-to-pin Logic Delay (ns)
Automotive I Speed Grades
Automotive Q Speed Grades
Temperature Grades (1)
RoHS (Pb-free)
15.5
-15
-15
I, Q
Yes
Yes
15.5
-15
-15
I, Q
Yes
Yes
15.5
-15
-15
I
5.5
-6
6.7
-7
7.0
-7
7.0
-7
9.2
-10
-11
I, Q
Yes
Yes
Speed Grades
Miscellaneous
-7
-8
-8
-8
I, Q
Yes
Yes
I, Q
Yes
Yes
I, Q
Yes
Yes
I, Q
Yes
Yes
Yes
Yes
XA Released
(2)
Package
Area
Maximum User I/Os
VQFP Packages (VQ): very thin QFP (0.5 mm lead spacing)
34
52
VQG44
VQG64
VQG100
12 x 12 mm
12 x 12 mm
16 x 16 mm
34
33
33
64
80
80
TQFP Packages (TQ): thin QFP (0.5 mm lead spacing)
TQG100
TQG144
16 x 16 mm
22 x 22 mm
72
118
118
Chip Scale Packages (CP): wire-bond chip-scale BGA (0.5 mm ball spacing)
CPG132 8 x 8 mm
Chip Scale Packages (CS): wire-bond chip-scale BGA (0.8 mm ball spacing)
CSG144 12 x 12 mm
100
117
Notes: 1. Temperature Range Automotive I (Ta = -40°C to +85°C); Automotive Q (Ta = -40°C to +105°C with Tj maximum = +125°C).
2. Area dimensions for lead-frame products are inclusive of the leads.
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