EVM IMPORTANT NOTICE
Texas Instruments (TI) provides the enclosed product(s) under the following conditions:
This evaluation kit being sold by TI is intended for use for ENGINEERING DEVELOPMENT OR EVALUATION
PURPOSES ONLY and is not considered by TI to be fit for commercial use. As such, the goods being provided
may not be complete in terms of required design-, marketing-, and/or manufacturing-related protective
considerations, including product safety measures typically found in the end product incorporating the goods.
As a prototype, this product does not fall within the scope of the European Union directive on electromagnetic
compatibility and therefore may not meet the technical requirements of the directive.
Should this evaluation kit not meet the specifications indicated in the EVM User’s Guide, the kit may be returned
within 30 days from the date of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE
WARRANTY MADE BY SELLER TO BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED,
IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY
PARTICULAR PURPOSE.
The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user
indemnifies TI from all claims arising from the handling or use of the goods. Please be aware that the products
received may not be regulatory compliant or agency certified (FCC, UL, CE, etc.). Due to the open construction
of the product, it is the user’s responsibility to take any and all appropriate precautions with regard to electrostatic
discharge.
EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE, NEITHER PARTY SHALL BE LIABLE
TO THE OTHER FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES.
TI currently deals with a variety of customers for products, and therefore our arrangement with the user is not
exclusive.
TI assumes no liability for applications assistance, customer product design, software performance, or
infringement of patents or services described herein.
Please read the EVM User’s Guide and, specifically, the EVM Warnings and Restrictions notice in the EVM
User’s Guide prior to handling the product. This notice contains important safety information about temperatures
and voltages. For further safety concerns, please contact the TI application engineer.
Persons handling the product must have electronics training and observe good laboratory practice standards.
No license is granted under any patent right or other intellectual property right of TI covering or relating to any
machine, process, or combination in which such TI products or services might be or are used.
Mailing Address:
Texas Instruments
Post Office Box 655303
Dallas, Texas 75265
Copyright 2003, Texas Instruments Incorporated
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EVM WARNINGS AND RESTRICTIONS
It is important to operate this EVM within the input voltage range of ±6 V and the output voltage
range of 0 V and 5.5 V.
Exceeding the specified input range may cause unexpected operation and/or irreversible
damage to the EVM. If there are questions concerning the input range, please contact a TI
field representative prior to connecting the input power.
Applying loads outside of the specified output range may result in unintended operation and/or
possible permanent damage to the EVM. Please consult the EVM User’s Guide prior to
connecting any load to the EVM output. If there is uncertainty as to the load specification,
please contact a TI field representative.
During normal operation, some circuit components may have case temperatures greater than
60°C. The EVM is designed to operate properly with certain components above 60°C as long
as the input and output ranges are maintained. These components include but are not limited
to linear regulators, switching transistors, pass transistors, and current sense resistors. These
types of devices can be identified using the EVM schematic located in the EVM User’s Guide.
When placing measurement probes near these devices during operation, please be aware
that these devices may be very warm to the touch.
Mailing Address:
Texas Instruments
Post Office Box 655303
Dallas, Texas 75265
Copyright 2003, Texas Instruments Incorporated
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Preface
Read This First
About This Manual
This users guide describes the characteristics, operation, and use of the
ADS8402/ADS8412 16-bit, high speed, parallel interface analog-to-digital
converter evaluation board. A complete circuit description as well as a
schematic diagram and bill of materials are included.
How to Use This Manual
This document contains the following chapters:
- Chapter 1 – EVM Overview
- Chapter 2 – Analog Interface
- Chapter 3 – Digital Interface
- Chapter 4 – Power Supply Requirements
- Chapter 5 – Using the EVM
- Chapter 6 - ADS8402/ADS8412 BOM, Layout, and Schematic
Related Documentation From Texas Instruments
To obtain a copy of any of the following TI documents, call the Texas
Instruments Literature Response Center at (800) 477-8924 or the Product
Information Center (PIC) at (972) 644-5580. When ordering, identify this
booklet by its title and literature number. Updated documents can also be
Data Sheets:
ADS8402
Literature Number:
SLAS154
ADS8412
SLAS384
REF3040
SBVS032
SN74AHC138
SN74AHC245
SN74AHC1G04
THS4503
SCLS258
SCLS230
SCLS318
SLOS352
iii
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FCC Warning
This equipment is intended for use in a laboratory test environment only. It gen-
erates, uses, and can radiate radio frequency energy and has not been tested
for compliance with the limits of computing devices pursuant to subpart J of
part 15 of FCC rules, which are designed to provide reasonable protection
against radio frequency interference. Operation of this equipment in other en-
vironments may cause interference with radio communications, in which case
the user at his own expense will be required to take whatever measures may
be required to correct this interference.
iv
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Contents
1
2
EVM Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.1
1.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
Analog Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.1
2.2
Signal Conditioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
3
4
5
Digital Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
Power Supply Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
Using the EVM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
5.1
5.2
5.3
As a Reference Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
As a Prototype Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
As a Software Test Platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
6
ADS8402/ADS8412EVM BOM, Layout, and Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
6.1
6.2
6.3
ADS8402/ADS8412EVM Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
ADS8402/ADS8412EVM Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
ADS8402/ADS8412EVM Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8
v
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Figures
1-1
5-1
5-2
5-3
5-4
Input Buffer Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
Top Layer—Layer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
Ground Plane—Layer 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
Power Plane—Layer 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6
Bottom Layer—Layer 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
Tables
1-1
1-2
2-1
2-2
2-3
2-4
3-1
3-2
5-1
Analog Input Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
Solder Short Jumper Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
Pinout for Parallel Control Connector P2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Jumper Settings for Decoder Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Data Bus Connector P3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Pinout for Converter Control Connector J3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Power Supply Test Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
Power Connector, J1, Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
ADS8402/ADS8412EVM Bill Of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
vi
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Chapter 1
EVM Overview
This chapter contains the features of the ADS8402/ADS8412.
Topic
Page
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1-1
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Features
1.1 Features
- Full-featured evaluation board for the high-speed ADS8402 (1.25 MSPS)
and the ADS8412 (2 MSPS) high speed, 16-bit, single channel, parallel
interface SAR-type analog-to-digital converters.
- Onboard signal conditioning
- Onboard reference
- Input and output digital buffer
- Onboard decoding for stacking multiple EVMs
1.2 Introduction
The ADS8402EVM and ADS8412EVM is a modular or stand alone EVM. It has
the bare minimum circuitry to showcase the device under test and plug into
prototype systems. The onboard decoding circuitry enables the user flexibility
to map the A/D to different addresses in processor memory. The power, analog
and digital control lines are on standard 0.1-in. header/socket connectors, at
the edges of the PWB, making it easy to wire into prototype systems for
evaluation. The EVM has been designed for direct evaluation of the
analog-to-digital converter performance and operating characteristics. This
EVM is compatible with the 5-6K interface board (SLAU104) from Texas
Instruments and additional third party boards.
1-2
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Chapter 2
Analog Interface
The ADS8402/ADS8412EVM analog-to-digital converter has a unipolar
differential input. A unipolar differential input is a differential signal (inverting
and noninverting input is 180 degrees out of phase) that is level shifted such
that the signals levels are always equal to or above zero volts. The
peak-to-peak amplitude on each input pin can be as large as the reference
voltage. See the respective product data sheet for more information.
Topic
Page
2.1 Signal Conditioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.2 Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2-1
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Signal Conditioning
2.1 Signal Conditioning
The ADS8402/ADS8412EVM comes installed with the unity gain buffer (U2)
wired for single-ended in to differential out configuration. The common-mode
voltage is derived from a REF3040 reference IC and is adjustable using a
potentiometer (R9). The common-mode voltage pin of the THS4503 is set to
2 V on the evaluation module. A single-ended input signal can be applied at
pin connector P1 or via SMA connectors J2 (noninverting input). The buffer
circuit can be reconfigured for a unipolar differential input by installing resistor
R6 and R8 and removing R1. The inverting leg of the differential signal should
be applied to either connector P1 pin 1 or SMA connector J4 (inverting input).
the EVM schematic.
Table 2-1.Analog Input Connector
Description
Signal Name Connector.Pin# Signal Name
Description
Inverting input
Reserved
(-)
N/A
P1.1
P1.3
P1.2
P1.4
+
Noninverting input
Reserved
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
REF+
Reserved
N/A
P1.5
P1.6
Reserved
Reserved
N/A
P1.7
P1.8
Reserved
Pin tied to ground
Pin tied to ground
Reserved
AGND
AGND
N/A
P1.9
P.10
Reserved
P1.11
P1.13
P1.15
P1.17
P1.19
P1.12
P1.14
P1.16
P1.18
P1.20
Reserved
Reserved
Pin tied to ground
Pin tied to ground
Reserved
AGND
AGND
N/A
Reserved
Reserved
External reference input
It is recommended the analog input to any SAR-type converter be buffered.
ADS8402/ADS8412EVM. This circuit consists of the THS4503, a high-speed
fully differential amplifier configured as a single-ended in to differential out,
ac (i.e., SNR, THD, SFDR, etc.) specifications listed in the ADS8402 and
ADS8412 data sheets. The 60-pF and 6800-pF capacitors in the signal path
are polypropylene type, manufactured by the WIMA Corporation.
Polypropylene capacitors cause the least distortion of the input signal.
2-2
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Reference
Figure 2-1. Input Buffer Circuit
60 pF
1 kΩ
+V
CC
0.1 µF
THS4503
1 µF
1 kΩ
25 Ω
+
V
I
(+) IN
-
+2.048 V
V
6800 pF
OCM
25 Ω
+
(-) IN
-
1 µF
1 kΩ
0.1 µF
-V
CC
1 kΩ
60 pF
2.2 Reference
The EVM allows users to select from three reference sources. The
ADS8402/ADS8412EVM provides an onboard 4.096-V reference, U3. The
EVM also has the provision for users to supply a reference voltage via
connecter P1 pin 20. The user reference voltage and onboard reference
voltages can be filtered by installing amplifier U1. Both the ADS8402 and
ADS8412 analog-to-digital converters have integrated onboard reference
buffers; therefore, it is not necessary to buffer the voltage externally. The
reference buffer circuit on the EVM is not populated with an amplifier. The EVM
comes installed with an on-chip internal reference tied directly to the reference
pin of the converter. See Chapter 6 for the schematic.
Table 2-2.Solder Short Jumper Setting
Jumper Setting
1-2 2-3
Reference
Designator
Description
SJP1
Not used on the EVM
†
SJP2
SJP3
On-chip internal reference applied to reference pin
Apply reference voltage from external source
Installed
Not Installed
Installed
N/A
†
Apply voltage to amplifier, U2, common-mode voltage pin Installed
SJP4
SJP5
Buffer onboard reference, REF3040
Buffer user reference voltage applied at P1 pin 20.
Select REF3040 for reference voltage
Select buffered reference voltage
Installed
Not installed
Installed
Not installed
Installed
Not Installed
Installed
Not Installed
†
Factory set condition
Analog Interface
2-3
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2-4
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Chapter 3
Digital Interface
The ADS8402/ADS8412 EVM is designed for easy interfacing to multiple
platforms.
Samtec
part
numbers
SSW-110-22-F-D-VS-K
and
TSM-110-01-T-DV-P provide
a
convenient dual row header/socket
1-800-SAMTEC-9 for a variety of mating connector options.
Table 3-1.Pinout for Parallel Control Connector P2
Connector.Pin
Signal
Description
P2.1
P2.3
DC_CS Daughter card board select pin
P2.5
P2.7
A0
A1
A2
Address line from processor
Address line from processor
Address line from processor
P2.9
P2.11
P2.13
P2.15
P2.17
P2.19
INTc
Set jumper W3 to select BUSY or inverted signal
to be applied to this pin.
Note: All even numbered pins of P2 are tied to DGND.
The read (RD), conversion start (CONVST), and reset (RESET) signals to the
converter can be assigned to two different addresses in memory via jumper
settings. This allows for the stacking of up to two ADS8402EVMs and/or
Note, the evaluation module does not allow the chip select (CS) line of the
converter to be assigned to different memory locations. It is therefore
suggested the CS line be grounded or wired to an appropriate signal of the
processor.
3-1
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Table 3-2.Jumper Settings for Decoder Outputs
Jumper Settings
Reference Designator
Description
1-2
2-3
†
Set A[2..0] = 0x1 to generate RD pulse
Installed
Not installed
W2
W5
Set A[2..0] = 0x2 to generate RD pulse
Not installed Installed
†
Set A[2..0] = 0x3 to generate CONVST pulse
Set A[2..0] = 0x4 to generate CONVST pulse
Set A[2..0] = 0x5 to generate RESET pulse
Set A[2..0] = 0x6 to generate RESET pulse
Installed
Not installed
Not installed Installed
†
Installed
Not installed
W4
Not installed Installed
†
Factory set condition
information.
Table 3-3.Data Bus Connector P3
Connector.Pin
P3.1
Signal
D0
Description
Buffered Data Bit 0 (LSB)
P3.3
D1
Buffered Data Bit 1
Buffered Data Bit 2
Buffered Data Bit 3
Buffered Data Bit 4
Buffered Data Bit 5
Buffered Data Bit 6
Buffered Data Bit 7
Buffered Data Bit 8
Buffered Data Bit 9
Buffered Data Bit 10
Buffered Data Bit 11
Buffered Data Bit 12
Buffered Data Bit 13
Buffered Data Bit 14
Buffered Data Bit 15
P3.5
D2
P3.7
D3
P3.9
D4
P3.11
P3.13
P3.15
P3.17
P3.19
P3.21
P3.23
P3.25
P3.27
P3.29
P3.31
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
Note: All even numbered pins of P3 are tied to DGND.
This evaluation module provides direct access to all the analog-to-digital
Table 3-4.Pinout for Converter Control Connector J3
Connector.Pin
J3.1
Signal
CS
Description
Chip select pin. Active low
Read pin. Active low
J3.3
RD
J3.5
CONVST
BYTE
RESET
BUSY
Convert start pin. Active low
J3.7
Byte mode pin. Used for 8-bit buses.
J3.9
Reset pin. Active low.
J3.11
Converter status output. High when a conversion is in progress.
Note: All even numbered pins of J3 are tied to DGND.
3-2
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Chapter 4
Power Supply Requirements
The EVM accepts four power supplies.
- A dual ±Vs dc supply for the dual supply op-amps. Recommend ±7 Vdc
supply.
- A single +5-Vdc supply for the analog section of the board (A/D +
Reference).
- A single +5-V or +3.3-Vdc supply for the digital section of the board (A/D
+ address decoder + buffers).
There are two ways to provide these voltages.
Table 4-1.Power Supply Test Points
Test Point
Signal
+BVDD
+AVCC
+VA
Description
TP14
TP11
TP12
TP13
Apply +3.3 V or +5 V. See ADC data sheet for full range.
Apply +5 Vdc.
Apply +7 Vdc. Positive supply for amplifier.
Apply –7 Vdc. Negative supply for amplifier.
-VA
2) Use the power connector J1 and derive the voltages elsewhere. The
the W1 jumper to connect +3.3VD or +5VD from connector to +BVDD.
Short between pins 1-2 to select +5VD or short between pins 2-3 to select
+3.3VD as the source for the digital buffer voltage supply (+BVDD).
Table 4-2.Power Connector, J1, Pinout
Signal
Power Connector - J1
Signal
–VA (–7V)
N/C
+VA(+7V)
+5VA
1
3
5
7
9
2
4
DGND
N/C
6
AGND
N/C
8
+3.3VD
10
+5VD
4-1
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4-2
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Chapter 5
Using the EVM
The ADS8402/ADS8412EVM serves three functions:
1) As a reference design
2) As a prototype board
3) As a software test platform
Topic
Page
5.1 As a Reference Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
5.2 As a Prototype Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
5.3 As a Software Test Platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
5-1
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As a Reference Board
5.1 As a Reference Board
As a reference design, the ADS8402/ADS8412EVM contains the essential
circuitry to showcase the analog-to-digital converter. This essential circuitry
includes the input amplifier, reference circuit, and buffers. The EVM analog
input circuit is optimized for 100-kHz sine wave. Therefore, users may need
to adjust the resistor and capacitor values of the A/D input circuit. In ac-type
applications where signal distortion is a concern, polypropylene capacitors
should be used in the signal path.
5.2 As a Prototype Board
As a prototype board, the buffer circuit consists of resistor pads for configuring
the input as either single-ended or differential input. The input circuit can be
modified to accommodate user prototype needs, whether it be evaluating
another differential amplifier or limiting noise for best performance. The
analog, power, and digital connectors can be made to plug into a standard
0.1 in. breadboard or cables made up to interface directly to an FPGA or
processor.
5.3 As a Software Test Platform
As a software test platform, connectors P1, P2, and P3, plug into the parallel
interface connectors of the 5-6K interface card. The 5-6K interface card sits
on the C5000 and C6000 digital signal processor starter kit (DSK). The
ADS8402/ADS8412EVM is then mapped into the processor’s memory space.
This card also provides an area for signal conditioning. This area can be used
to install application circuit(s) for digitization by the ADS8402/ADS8412
analog-to-digital converter. See the 5-6K interface card user’s guide
(SLAU104) for more information.
The ADS8402/ADS8412EVM provides a simple platform for interfacing to the
converter. The EVM provides standard 0.1-in. headers and sockets to wire into
prototype boards. The user only needs to provide three address lines (A2, A1,
A0) and address valid line (DC_CS) to connector P2. To choose which address
combinations generates RD, CONVST, and RESET, set jumpers as shown in
P2; therefore, it must be controlled via a general purpose pin or shorted to
ground at J3 pin 1. If address decoding is not required, the EVM provides direct
access to converter data bus via P3 and control via J3.
5-2
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Chapter 6
ADS8402/ADS8412EVM BOM, Layout, and
Schematic
This chapter contains the ADS8402/ADS8412EVM bill of materials, the
layouts, and the schematics.
Topic
Page
6.1 ADS8402/ADS8412EVM Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
6.2 ADS8402/ADS8412EVM Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
6.3 ADS8402/ADS8412EVM Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6
6-1
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ADS9393EVM Bill of Materials
6.1 ADS9393EVM Bill of Materials
materials
for
the
ADS8402/ADS8412EVM. The schematic diagram is also provided for
reference. Contact the Product Information Center or e-mail
[email protected] for questions regarding this EVM.
Table 6-1.ADS8402/ADS8412EVM Bill Of Materials
Item
No.
QTY
Value
0 Ω
Designator
Footprint
Mfg
Mfg’s Part Number
Description
1
2
R15, R21
805
Panasonic - ECG ERJ-6GEY0R00V
or Alternate
RES 0 Ω 1/8 W 5% 0805
SMD
2
2
3
24.9 Ω
100 Ω
910 Ω
1 kΩ
R12, R13
R5, R14, R25
R4
805
805
805
805
603
805
805
805
1206
TH
Panasonic - ECG ERJ-6ENF24R9V
or Alternate
RES 24.9 Ω 1/10 W 1%
0805 SMD
3
Panasonic - ECG ERJ-6ENF1000V
or Alternate
RES 100 Ω 1/10 W 1%
0805 SMD
4
1
Panasonic - ECG ERJ-6GEYJ911V
or Alternate
RES 910 Ω 1/8 W 5%
0805 SMD
5
3
R1, R7, R10
R16 - R20
R24
Panasonic - ECG ERJ-6ENF1001V
or Alternate
RES 1 kΩ 1/10 W 1%
0805 SMD
6
5
10 kΩ
10 kΩ
NI
Panasonic - ECG ERJ-3EKF1002V
or Alternate
RES 10 kΩ 1/16 W 1%
0603 SMD
7
1
Panasonic - ECG ERJ-6ENF1002V
or Alternate
RES 10 kΩ 1/10 W 1%
0805 SMD
8
6
R6, R8, R11,
R2, R3, R22
Not Installed
Not Installed
9
1
49.9 Ω
1 nF
R23
Panasonic - ECG ERJ-6ENF49R9V
or Alternate
RES 49.9 Ω 1/10 W 1%
0805 SMD
10
11
12
13
4
C3, C5, C11,
C23
Kemet or
Alternate
C1206C102J5GACTU
Capacitor 1000 pF 50-V
ceramic NPO 1206
2
68 pF
6800 pF
0.01 µF
C34, C35
WIMA
FKP2 68/100/1
68-pF polypropylene
capacitor
1
C17
TH
WIMA
FKP2 6800/100/1
6800-pF polypropylene
capacitor
10
C13, C21, C41,
C44, C46, C48,
C53, C56, C65,
C50
603
Kemet or
Alternate
C0603C103J5RACTU
Capacitor 10000 pF 50-V
ceramic X7R 0603
14
15
16
4
2
0.01 µF
0.01 µF
0.1 µF
C10, C18, C20,
C66
805
1206
603
Kemet or
Alternate
C0805C103K5RACTU
C1206C103J5RACTU
C0603C104K3RACTU
Capacitor 10000 pF 50-V
ceramic X7R 0805
C4, C26
Kemet or
Alternate
Capacitor 10000 pF 50-V
ceramic X7R 1206
15
C8, C25, C40,
C42, C43, C47,
C51, C52, C54,
C55, C57, C58,
C62, C63, C64
Kemet or
Alternate
Capacitor 0.1 µF 25-V
ceramic X7R 0603
17
7
0.1 µF
C7, C9, C15,
C22, C32, C36,
C45
805
Kemet or
Alternate
C0805C104J5RACTU
Capacitor 0.10 µF 50-V
ceramic X7R 0805
18
19
20
21
6
2
4
1
1 µF
C16, C31, C33,
C37, C59, C60
805
Kemet or
Alternate
C0805C105K4RACTU
C1206C105K3RACTU
Capacitor 1 µF 16-V
ceramic X7R 0805
1 µF
C2, C28
1206
1206
3528
Kemet or
Alternate
Capacitor 1 µF 25-V
ceramic X7R 1206
10 µF
10 µF
C1, C6, C12,
C19
Panasonic - ECG ECJ-3YB1C106M
or Alternate
Capacitor 10 µF 16-V
ceramic X5R 1206
C49
Kemet or
Alternate
T491B106K016AS
Capacitor TANT 10 µF
16 V 10% SMT
6-2
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ADS9393EVM Bill of Materials
Item
No.
QTY
Value
10 µF
Designator
Footprint
Mfg
Mfg’s Part Number
ECS-T1EC106R
Description
22
4
C14, C24, C27,
C29
6032
Panasonic -
ECG or Alternate
Capacitor 10 µF 25-V
tantalum TE SMD
23
1
22 µF
C30
805
TDK Corporation C2012X5R0J226M
Capacitor CER 22 µF
6.3 V X5R 20% 0805
24
25
3
2
NI
C38, C39, C61
RP1, RP3
805
1 Ω
CTS_742
CTS Corporation 742C163102JTR
CTS Corporation 742C163101JTR
RES array 1 Ω 16TERM
8RES SMD
26
27
28
29
1
1
4
2
100 Ω
RP2
CTS_742
RES array 100 Ω 16TRM
8RES SMD
10 kΩ
R9
BOURNS_3 Bourns
2X4W
3214W-1-103E
TRIMPOT 10 kΩ 4 mm
top ADJ SMD
L1, L2, L3
U1, U3
1206
MURATA ERIE
BLM31PG601SN1L
REF3040AIDBZT
Chip ferrite beads- 600 Ω
at 100 MHz
3-SOT-23
Texas
REF3040 50 ppm/°C,
50 µA in SOT23-3
Instruments
CMOS voltage reference
30
1
1
U2
U4
8-SOP(D)
Texas
Instruments
THS4503ID
High-speed
fully-differential amplifiers
31†
socket_48Q Texas
ADS8402IPFBT†
Not installed
ADS8402 16-bit
1.25 MSPS
FP
Instruments
32
33
1
1
OPA627AU U8
8-SOP(D)
8-SOP(D)
Not installed
Amplifier
NI
U9
Footprint for 8-pin SOIC
reference that operates
from +5V.
34
35
36
37
38
1
1
3
1
1
U10
5-SOT
(DBV)
Texas
Instruments
SN74AHC1G04DBVR
SN74AHC138PWR
SN74AHC245PWR
TSM-105-01-T-D-V-P
SSW-106-22-S-D-VS
TSM-106-01-T-D-V-P
901-144-4
Single inverter gate
U11
16-TSSOP Texas
(PW)
3-line to 8-line decoder /
demultiplexer
Instruments
U5, U6, U7
20-TSSOP Texas
(PW)
Octal bus transceiver, tri
state
Instruments
5X2X.1
6X2X.1
J1
J3
5X2X.1_SM Samtec
T_socket
0.025” SMT plug - top
side of PWB
6X2X.1_SM Samtec
T_plug_&_s
0.025” SMT socket -
bottom side of PWB
ocket
0.025” SMT plug - top
side of PWB
39
40
2
2
SMA_PCB J2, J4
_MT
SMA_JACK AMPHENOL
MaCom #5002-5003-10
/ Amphenol #901-144
10X2X.1
P1, P2
10X2X.1_S Samtec
MT_plug_&_
socket
SSW-110-22-S-D-VS
TSM-110-01-T-D-V-P
SSW-116-22-S-D-VS
TSM-116-01-T-D-V-P
0.025” SMT socket -
bottom side of PWB
0.025” SMT plug - top
side of PWB
41
1
16X2X.1_S P3
MT_plug_&
_socket
16X2X.1_S Samtec
MT_plug_&_
socket
0.025” SMT socket –
bottom side of PWB
0.025” SMT plug – top
side of PWB
42
43
1
3
SJP2
SJP3
SJP3
SJP2
SJP3
Not installed
Not installed
Not installed
Not installed
Pad 2 position jumper
Pad 3 postion jumper
SJP2, SJP4,
SJP5
44
45
1
5
SW-PB
S1
EVQ-PJ
Panasonic
Samtec
EVQ-PJU04K
Switch
3POS_JU
MPER
W1 - W5
3pos_jump
TSW-103-07-L-S
3 position jumper 0.1”
spacing
46
14
TP_.025
TP1 - TP14
test_point2
Keystone
Electronics
5000K–ND
Test point-single 0.025”
pin
Note: On ADS8412EVM, the ADS8412IPFBT is installed instead of ADS8402IPFBT.
ADS8402/ADS8412EVM BOM, Layout, and Schematic
6-3
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ADS8402/ADS8412EVM Layout
6.2 ADS8402/ADS8412EVM Layout
Figure 6-1. Top Layer—Layer 1
Figure 1.
6-4
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ADS8402/ADS8412EVM Layout
Figure 6-2. Ground Plane—Layer 2
ADS8402/ADS8412EVM BOM, Layout, and Schematic
6-5
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ADS8402/ADS8412EVM Layout
Figure 6-3. Power Plane—Layer 3
6-6
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ADS8402/ADS8412EVM Layout
Figure 6-4. Bottom Layer—Layer 4
ADS8402/ADS8412EVM BOM, Layout, and Schematic
6-7
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ADS8402/ADS8412EVM Schematic
6.3 ADS8402/ADS8412EVM Schematic
The following pages contain the schematic for the ADS8402/ADS8412EVM.
6-8
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]
. . . 5 0 [ 1 D B
S Y B U
]
. . . 5 0 [ 1 D B
S Y B U
1 5 . . 0 D ] B [
c
I N T
A 2
A 1
A 0
C S D C _
S Y B _ B U
E S R E T
E S E B T _ R
B _ B Y T E
V S N T O B _ C
S E T B _ R
B _ B Y T E
V S N T O B _ C
B _ R
B Y T E
C O N V
R D
T S
D
S
B _ R
B _ C
D
S
B _ C
C S
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DB[15...0]
+ V B D
R E S E T
B Y T E
C O N V S T
+ V B D
3 7
3 8
3 9
4 0
4 1
4 2
4 3
4 4
4 5
4 6
4 7
4 8
2 4
2 3
2 2
2 1
2 0
1 9
1 8
1 7
1 6
1 5
1 4
1 3
D B 8
D B 8
D B 9
D B 9
D B 1 0
D B 1 1
D B 1 2
D B 1 3
D B 1 4
D B 1 5
A G N D
A G N D
+ V A
D B 1 0
D B 1 1
D B 1 2
D B 1 3
D B 1 4
D B 1 5
R D
C S
+ V A
A G N D
A G N D
+ V A
R E F M
R E F M
3
1
1
3
5
1
8
4
7
1
3
3
7
6
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C
V C
G N D
1 6
8
1
3
1
3
5
3
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