Texas Instruments Power Supply 27 User Manual

ADS5525/27/45/46/47 EVM User  
Guide  
User's Guide  
November 2006  
SLWU028B  
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Contents  
1
2
Overview.................................................................................................................... 5  
1.1  
EVM Basic Functions............................................................................................ 5  
EVM Quick Start Guide ................................................................................................ 6  
2.1  
2.2  
EVM LVDS Output Mode Quick Start (Default) .............................................................. 6  
EVM CMOS Output Mode Quick Start ........................................................................ 6  
3
4
Circuit Description ...................................................................................................... 7  
3.1  
Schematic Diagram .............................................................................................. 7  
Circuit Function................................................................................................... 7  
3.2  
Expansion Options .................................................................................................... 13  
4.1  
4.2  
4.3  
Custom FPGA Code ........................................................................................... 13  
Expansion Slot .................................................................................................. 13  
Optional USB SPI Interface ................................................................................... 13  
5
Physical Description.................................................................................................. 14  
5.1  
5.2  
5.3  
PCB Layout...................................................................................................... 14  
Bill of Materials.................................................................................................. 20  
PCB Schematics................................................................................................ 25  
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Table of Contents  
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List of Figures  
1
2
3
4
5
6
7
8
9
ADS5547 SNR Performance vs Decoupling ............................................................................. 8  
THS4509 + ADS5545 EVM Performance ................................................................................ 9  
Eye Diagram of Data on Header J4...................................................................................... 11  
Top Layer.................................................................................................................... 14  
Layer 2, Ground Plane .................................................................................................... 15  
Layer 3, Power Plane #1 .................................................................................................. 16  
Layer 4, Power Plane #2 .................................................................................................. 17  
Layer 5, Ground Plane .................................................................................................... 18  
Layer 6, Bottom Layer ..................................................................................................... 19  
List of Tables  
1
2
3
4
5
DIP Switch SW1 ............................................................................................................. 7  
EVM Power Options......................................................................................................... 8  
Output Connector J4....................................................................................................... 10  
Test Points .................................................................................................................. 12  
Bill of Materials ............................................................................................................. 21  
4
List of Figures  
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User's Guide  
SLWU028BJanuary 2006Revised November 2006  
1
Overview  
This manual assists users in using the ADS5525/27/45/46/47 evaluation module (EVM) for evaluating the  
performance of the ADS5525/27/45/46/47 (ADCs). The EVM provides a powerful and robust capability in  
evaluation of the many features of the ADCs and the performance of the device der many conditions.  
1.1 EVM Basic Functions  
Analog input to the ADC is provided via external SMA connectors. The user supplies a single-ended input,  
which is converted into a differential signal. One input path uses a differential amplifier, while the other  
input is transformer-coupled.  
The EVM provides an external SMA connector for input of the ADC clock. The single-ended input is  
converted into a differential signal at the input of the device.  
Digital output from the EVM is via a 40-pin connector.  
Power connections to the EVM are via banana jack sockets. Separate sockets are provided for the ADC  
analog and digital supplies, the FPGA supply, and the differential amplifier supply.  
CAUTION  
Exceeding the maximum input voltages can damage EVM components.  
Undervoltage may cause improper operation of some or all of the EVM  
components.  
Xilinx, Spartan, WebPACK are trademarks of Xilinx, Inc.  
All other trademarks are the property of their respective owners.  
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EVM Quick Start Guide  
2
EVM Quick Start Guide  
The ADC has two basic modes of output operation, ensuring compatibility in a broad range of systems.  
Follow the steps below to get the EVM operating quickly with the ADC in either DDR LVDS output mode  
or CMOS output mode.  
Note: Follow the steps in the listed order; not doing so could result in improper operation.  
2.1 EVM LVDS Output Mode Quick Start (Default)  
1. Ensure a jumper is installed between pins 1 and 2 on JP2.  
2. Ensure DIP switch SW1, switch 2 is set to LVDS.  
3. Ensure DIP switch SW1, switch 8 is set to PARALLEL.  
4. Use a regulated power supply to provide 3.3 VDC to the ADC at J11 and J15, with the corresponding  
returns connected to J9 and J16.  
5. Use a regulated power supply to provide a 5-VDC input to J14, while connecting the return to J17.  
6. Provide a filtered, low-phase-noise, sinusoidal 1.5-Vrms, 170-MHz clock to J7.  
7. Provide a filtered, sinusoidal analog input to J3.  
8. Using a logic analyzer and Table 3 in this manual, monitor the ADC output on J4.  
2.2 EVM CMOS Output Mode Quick Start  
1. Ensure a jumper is installed between pins 2 and 3 on JP2.  
2. Ensure DIP switch SW1, switch 2 is set to CMOS.  
3. Ensure DIP switch SW1, switch 8 is set to PARALLEL.  
4. Use a regulated power supply to provide 3.3 VDC to the ADC at J11 and J15, with the corresponding  
returns connected to J9 and J16.  
5. Use a regulated power supply to provide a 5-VDC input to J14, while connecting the return to J17.  
6. Provide a low-phase-noise, sinusoidal 1.5-Vrms, 170-MHz clock to J7.  
7. Provide a filtered sinusoidal analog input to J3.  
8. Briefly depress S1, which resets the EVM.  
9. Using a logic analyzer and Table 3 in this manual, monitor the ADC output on J4.  
6
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Circuit Description  
3
Circuit Description  
3.1 Schematic Diagram  
The schematic diagram for the EVM is in Section 5.3 of this document.  
3.2 Circuit Function  
The following paragraphs describe the function of individual circuits. See the data sheet for complete  
device operating characteristics.  
3.2.1  
Configuration Options  
The EVM provides a DIP switch, SW1, to control many of the modes of operation when the EVM is  
configured for parallel-mode operation. Table 1 describes the functionality of the DIP switches.  
Note: When the device is configured for serial-mode operation (SW1, switch 8), the DIP settings  
on SW1, switch 1 through SW1, switch 7 are ignored.  
Table 1. DIP Switch SW1  
SW1 SWITCH  
NUMBER  
OFF  
ON  
DESCRIPTION  
1
2
3
4
2s complement  
LVDS  
Offset binary  
CMOS  
Determines device output format  
Determines device output mode  
Reserved  
Reserved  
Reserved  
Internal reference  
External reference When set to External Reference, ADC uses common-mode  
voltage on TP1.  
5
6
7
8
Edge = 1  
Edge = 3  
Normal  
Serial  
Edge = 2  
Edge = 4  
Power down  
Parallel  
Allows for output edge programmability  
Allows for output edge programmability  
Allows for power down  
Determines mode for register interface  
By switching SW1, switch 8 to OFF, the ADC operates in serial mode, using its programmed register  
contents. A complete register map can be found in the device datasheet. Three pins on header J6 have  
been reserved for programming the device while it operates in serial mode. To program the device  
registers using header J6, place SCLK on pin 21, SDATA on pin 23, and SEN on pin 25. A pattern  
generator can be used to generate the patterns needed for programming. Alternatively, TI provides an  
optional USB daughtercard that plugs into the expansion slot of the EVM. The USB daughtercard allows  
ADC register control via a software package loaded onto the PC.  
3.2.2  
Power  
Power is supplied to the EVM via banana jack sockets. The EVM offers the capability to supply analog  
and digital 3.3 V independently to the ADC. Table 2 offers a snapshot of the power-supply options. All  
supply connections are required for default operation, except J12, J10, J13, and J20.  
The EVM provides local decoupling for the ADC; however, the ADC features internal decoupling, and in  
many cases minimal external decoupling can be used without loss in performance. Users are encouraged  
to experiment to find the optimal amount of external decoupling required for their application. Figure 1  
shows the ADS5547 LVDS-mode performance with all of the decoupling capacitors installed and the  
performance with C4, C5, C6, C7, C8, C9, and C10 removed. By default, the EVM comes with all of the  
decoupling capacitors installed.  
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Circuit Description  
Table 2. EVM Power Options  
BANANA JACK  
NAME  
Device AGND  
AGND  
VOLTAGE  
GND  
DESCRIPTION  
J9  
J10  
J11  
J12  
GND  
Device AVDD  
3.3  
–5  
Device analog supply  
THS4509 Vs– supply  
Amplifier negative  
rail  
J13  
J14  
Amplifier positive rail  
Auxiliary power  
5
5
THS4509 Vs+ supply  
Supplies power to all peripheral circuitry including the FPGA  
and PROM. Voltages rails are created by using TI's TPS75003  
voltage regulator.  
J15  
J16  
J17  
J20  
Device DVDD  
DGND  
3.3  
Device internal digital output supply  
GND  
GND  
DGND  
If TP11, TP12, and TP13 are tied low, the TPS75003 is  
disabled. In this case, one can supply 3.3 V to pin 1, 1.2 V to  
pin 2, and 2.2 V to pin 3 of J20 while connecting the ground to  
J17.  
74  
73  
72  
71  
70  
69  
68  
1 Decoupling Cap  
Baseline-All Decoupling Caps  
9.97  
19.94  
30.13  
40.33  
50.13  
60.13  
69.59  
79.87  
89.75 100.33 130.13 170.13  
f
IN  
− Input Frequency − MHz  
G001  
Figure 1. ADS5547 SNR Performance vs Decoupling  
3.2.3  
Analog Inputs  
The EVM can be configured to provide the ADC with either transformer-coupled or differential amplifier  
inputs from a single-ended source. The inputs are provided via SMA connector J3 for transformer-coupled  
input or SMA connector J1 for differential amplifier input. To set up for one of these options, the EVM must  
be configured as follows:  
1. For a 1:1 transformer-coupled input to the ADC, a single-ended source is connected to J3. Confirm  
that SJP4 has pins 2 and 3 shorted, and that SJP5 has pins 2 and 3 shorted. The transformer used,  
the Mini-Circuits TC4-1W, forms an inherent band-pass filter with a pass band from 3 MHz to 800 MHz.  
This is the default configuration for the EVM.  
2. One can use a TI THS4509 amplifier to drive the ADC by applying an input to J1. Reconfigure SJP4  
and SJP5 such that both have pins 1 and 2 shorted. A 5-VDC supply must be connected to the board  
to provide power to U3 for this configuration.  
The THS4509 amplifier path converts a single-ended signal presented on J1 into a differential signal.  
8
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Circuit Description  
The schematics present various interface options between the amplifier and the ADC. Depending on  
the input frequencies of interest, further performance optimization can be had by designing a  
corresponding filter. In its default configuration, R43, R44, and C119 form a first-order, low-pass filter  
with a cutoff frequency of 70 MHz. Figure 2 shows the performance of the ADS5545 using the  
THS4509 path.  
10  
1
0
−10  
−20  
−30  
−40  
−50  
−60  
−70  
5
−80  
−90  
3
x
4
−100  
110  
−120  
2
−130  
−135  
0
5
10  
15  
20  
25  
30  
35  
40  
45  
50  
55  
60  
65  
70  
75  
80  
85  
f − Frequency − MHz  
G002  
Figure 2. THS4509 + ADS5545 EVM Performance  
3.2.4  
3.2.5  
Clock Input  
A single-ended, harmonically filtered, low-phase-noise, 1.5-Vrms sinusoidal input should be applied to J7.  
The frequency must not exceed the device specification. In the EVM default configuration, both SPJ1 and  
SJP2 must have pins 1 and 2 shorted.  
In the board default configuration, the transformer provides single-ended to differential conversion. The  
transformer has an impedance ratio of 4.  
Digital Outputs  
For compatibility with a broad range of logic analyzers, the EVM outputs 3.3-V parallel CMOS data on  
header J4, independent of the ADC operational mode. The Xilinx™Spartan™-3E FPGA provides the  
necessary translation, and it configures itself using one of two different logic files stored in the PROM,  
based on the EVM configuration. The CMOS data output of the FPGA is contained in data header J4 and  
is a standard 40-pin header on a 100-mil grid, which allows easy connection to a logic analyzer. The  
connector pinout is listed in Table 3. For quick setup, the eye diagram is shown in Figure 3. No setup or  
hold-time adjustments must be made to the logic analyzer if using the rising edge of the output clock to  
latch in the data.  
Note: The eye diagram shown is the output of the FPGA at 210 MSPS, not that of the ADC. For  
the ADC output timing, see the respective device data sheet.  
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Circuit Description  
Table 3. Output Connector J4  
J4 PIN  
1
ADS5525/27 DESCRIPTION  
CLK  
ADS5545/46/47 DESCRIPTION  
CLK  
2
GND  
GND  
3
NC  
NC  
4
GND  
GND  
5
Reserved  
GND  
Reserved  
GND  
6
7
Reserved  
GND  
Reserved  
GND  
8
9
NC  
Data bit 0 (LSB)  
GND  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
GND  
NC  
Data bit 1  
GND  
GND  
Data bit 0 (LSB)  
GND  
Data bit 2  
GND  
Data bit 1  
GND  
Data bit 3  
GND  
Data bit 2  
GND  
Data bit 4  
GND  
Data bit 3  
GND  
Data bit 5  
GND  
Data bit 4  
GND  
Data bit 6  
GND  
Data bit 5  
GND  
Data bit 7  
GND  
Data bit 6  
GND  
Data bit 8  
GND  
Data bit 7  
GND  
Data bit 9  
GND  
Data bit 8  
GND  
Data bit 10  
GND  
Data bit 9  
GND  
Data bit 11  
GND  
Data bit 10  
GND  
Data bit 12  
GND  
Data bit 11 (MSB)  
GND  
Data bit 13 (MSB)  
GND  
NC  
NC  
GND  
GND  
NC  
NC  
GND  
GND  
10  
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Circuit Description  
C001  
Figure 3. Eye Diagram of Data on Header J4.  
3.2.6  
Test Points  
For added EVM visibility and control, several test points are provided. Table 4 summarizes the test points  
available.  
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Circuit Description  
Table 4. Test Points  
TP  
DESCRIPTION  
TP1  
ADC common mode, input or output  
depending on the setting of SW1, switch 4  
TP3  
TP4  
TP5  
TP6  
TP7  
TP8  
TP9  
THS4509 power down  
ADC output enable  
AGND  
AGND  
AGND  
DGND  
FPGA M0 pin; determines which FPGA logic  
file to load  
TP10  
TP11  
TP12  
TP13  
ADC SCLK  
TPS75003 1.2 enable  
TPS75003 2.5 enable  
TPS75003 3.3 enable  
3.2.7  
LED Operation  
To give greater visibility into the EVM operations, two LEDs are provided, D3 and D4. On power up, D4 is  
asserted when a successful FPGA boot up is complete. For correct EVM operation, the LED should be  
asserted at all times. LED D3 is asserted when the ADC and FPGA are operating and decoding in DDR  
LVDS mode, and is not asserted when the ADC is functioning in CMOS mode. Furthermore, in either DDR  
LVDS mode or CMOS mode, LED D3 blinks when an ADC overrange condition occurs.  
CAUTION  
If LED D3 is blinking, the amplitude coming into the ADC input (J3 or J4) must  
be attenuated immediately; otherwise, damage to the ADC could occur.  
12  
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Expansion Options  
4
Expansion Options  
The EVM offers several exciting possibilities to expand the capabilities of the EVM. This allows the utmost  
flexibility when prototyping an ADC circuit under conditions that mimic the end system, without the need to  
develop a custom prototype board.  
4.1 Custom FPGA Code  
Using a standard JTAG interface on JP1, users have the ability to load custom logic onto the FPGA,  
rapidly speeding up digital development time. This allows the flexibility of prototyping and debugging an  
ADC digital interface design before developing application-specific hardware.  
To take advantage of the onboard FPGA, users can download the free Xilinx WebPACK™ from the Xilinx  
Web site. Select the XC3S250E-4FT256 as the FPGA and the XCF16PFSG48 as the PROM.  
Note: See the Xilinx Spartan-3E Web site for complete documentation of the FPGA at:  
Schematically, the FPGA is configured in BPI mode, and it samples FPGA pins M2, M1, and M0 when the  
FPGA's INIT_B is brought low. Depending of the status of M0, it boots from either the top or the bottom of  
the PROM contents. The PROM allows for the storage of two FPGA bit files. In its default condition, the  
EVM stores one file for ADC CMOS output at the beginning of the PROM address space and one file for  
ADC LVDS output at the end of the PROM address space.  
Note: When creating custom FPGA code, store any custom-developed bit files for ADC CMOS  
operation in the PROM revision 0 space, and store any custom-developed FPGA code for  
ADC LVDS operation in the PROM revision 1 space.  
4.2 Expansion Slot  
For those users who make use of a custom FPGA program on the EVM, J5 and J6 provide an  
expansion-slot capability. Users can design daughtercards or breakout boards to make use of the unused  
FPGA I/O pins which are brought out to the headers.  
Note: The EVM provides 5 V from J14 to pin 1 of both J5 and J6. This can be used to provide  
power to any designed daughtercards.  
4.3 Optional USB SPI Interface  
In most cases, users can use the ADC parallel interface mode to change the operational modes of the  
ADC. For users requiring SPI control of the ADC, TI has developed an optional USB daughter card that  
plugs into the expansion slot. With the USB daughter card, users can use a PC interface to communicate  
to the ADC three-wire SPI interface, which allows for complete control of the ADC register map. Contact  
the factory for this optional accessory.  
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Physical Description  
5
Physical Description  
This chapter describes the physical characteristics and PCB layout of the EVM.  
5.1 PCB Layout  
The EVM is constructed on a 6-layer, 0.062-inch thick PCB using FR-4 material. The individual layers are  
shown in Figure 4 through Figure 9. The layout features split analog and digital ground planes; however,  
similar performance can be had with careful layout using a single ground plane. Users can connect the  
analog and digital ground planes underneath the EVM by soldering the two exposed tinned strips together.  
K001  
Figure 4. Top Layer  
14  
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Physical Description  
K002  
Figure 5. Layer 2, Ground Plane  
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Physical Description  
K003  
Figure 6. Layer 3, Power Plane #1  
16  
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Physical Description  
K004  
Figure 7. Layer 4, Power Plane #2  
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Physical Description  
K005  
Figure 8. Layer 5, Ground Plane  
18  
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Physical Description  
K006  
Figure 9. Layer 6, Bottom Layer  
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Physical Description  
5.2 Bill of Materials  
20  
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Physical Description  
Table 5. Bill of Materials  
NOT  
INSTALLED  
VALUE  
FOOTPRINT  
QTY  
PART NUMBER  
VENDOR  
DIGI-KEY NUMBER  
REF DESIGNATOR  
CAPACITORS  
47-µF, tantalum, 20%, 10-V  
7343  
3528  
4
5
ECS-T1AD476R  
ECS-T1AX106R  
Panasonic  
Panasonic  
PCS2476CT-ND  
PCS2106CT-ND  
C65, C66, C68, C69  
10-µF, 10-V, 20%  
C70, C71, C72, C73,  
C74  
10-µF, 10-V, 20%  
100-µF, 6.3-V, 10%  
0.1-µF, 16-V, 10%  
2.2-µF, 6.3-V, 10%  
10-µF, 6.3-V, 10%  
0.01-µF, 16-V, 10%  
0.1-µF, 16-V, 10%  
3216  
6032  
805  
805  
805  
603  
603  
2
2
ECS-T1AY106R  
TPSC107K006R0150  
ECJ-2VB1C104K  
Panasonic  
AVX  
P11309CT-ND  
478-1764-2-ND  
PCC1812CT-ND  
PCC2310CT-ND  
490-1717-1-ND  
PCC1750CT-ND  
PCC1762CT-ND  
C8, C9  
C35, C60  
C115, C116  
C117  
2
Panasonic  
Panasonic  
Murata  
1
ECJ-GVB0J225K  
4
GRM21BR60J106KE19L  
ECJ-1VB1C103K  
C13, C30, C40, C41  
C57  
1
Panasonic  
Panasonic  
18  
ECJ-1VB1C104K  
C14, C15, C18, C25,  
C26, C27, C28, C32,  
C33, C34, C36, C37,  
C38, C39, C51, C55,  
C62, C113  
C52  
1.5-nF, 50-V, 10%  
10-pF, 50-V, ±0.5-pF  
1-µF, 6.3-V, 10%  
603  
603  
603  
603  
603  
603  
603  
603  
402  
3
1
C1608X7R1H152K  
ECJ-1VC1H100D  
TDX  
C31, C58, C59  
Panasonic  
Panasonic  
Panasonic  
AVX  
PCC100CVCT-ND  
PCC1915CT-ND  
PCC2395CT-ND  
478-1824-1-ND  
PCC2273CT-ND  
490-1409-1-ND  
490-3555-1-ND  
PCC1731CT-ND  
C53  
1
ECJ-1VB0J105K  
C64  
10-µF, 6.3-V, 20%  
100-µF, 4-V, 20%  
2.2-µF, 6.3-V, 10%  
18-pF, 50-V, 5%  
1
ECJ-1VB0J106M  
C63  
1
NOJC107M004RWJ  
ECJ-1VB0J225K  
C61  
13  
1
Panasonic  
Murata  
C85–C96, C114  
C119  
GRM1885C1H180JA01D  
GQM1885C2A2R0CB01D  
ECJ-0EF1C104Z  
C2, C118  
C20  
2-pF, 100-V, ±0.25-pF  
0.1-µF, 16-V, +80/–20%  
0
Murata  
14  
Panasonic  
C1, C3, C4, C5, C6,  
C7, C10, C11, C12,  
C16, C17, C19, C29,  
C44, C49  
0.22-µF, 6.3-V , ±10%  
402  
201  
17  
16  
ECJ-0EB0J224K  
Panasonic  
AVX  
PCC2269CT-ND  
478-1054-1-ND  
C42, C43, C46, C48,  
C50, C54, C67, C75,  
C76, C77, C78, C79,  
C80, C81, C82, C83,  
C84  
0.022-µF, 6.3-V, +80/–20%  
02016G223ZAT2A  
C97, C98, C99, C100,  
C101, C102, C103,  
C104, C105, C106,  
C107, C108, C109,  
C110, C111, C112  
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Physical Description  
Table 5. Bill of Materials (continued)  
NOT  
INSTALLED  
VALUE  
FOOTPRINT  
QTY  
PART NUMBER  
VENDOR  
DIGI-KEY NUMBER  
REF DESIGNATOR  
RESISTORS  
0-, 1/10-W, 5%  
603  
7
ERJ-3GEY0R00V  
Panasonic  
P0.0GCT-ND  
R5, R6, R10, R18,  
R48, R58, R82  
R54, R56  
0-, 1/10-W, 5%  
402  
603  
603  
603  
603  
603  
603  
603  
603  
603  
603  
603  
3
2
ERJ-GE0R00X  
9C06031A4R02FGHFT  
ERJ-3EKF20R0V  
ERJ-3EKF24R9V  
ERD-S1TJ4R7V  
RC0603FR-0736RL  
ERJ-3EKF49R9V  
ERA-3YEB100V  
ERJ-3EKF2000V  
ERA-V33J331V  
Panasonic  
Yageo  
P0.0JCT-ND  
311-4.02HCT-ND  
P20.0HCT-ND  
P24.9HCT-ND  
P4.7BBCT-ND  
311-36.0HRCT-ND  
P49.9HCT-ND  
P100YCT-ND  
R11, C45, C47  
R37, R38  
R79  
4.02-, 1/10-W 1%  
20-, 1/16-W, 1%  
24.9-, 1/16-W, 1%  
4.7-, 1/2-W, 5%  
36-, 1/10-W, 1%  
49.9-, 1/16-W, 1%  
100-, 1/16-W, 0.1%  
200-, 1/16-W, 1%  
330-, 1/16-W, 5%  
499-, 1/16-W, 1%  
10-k, 1/16-W, 1%  
1
Panasonic  
Panasonic  
Panasonic  
Yaego  
1
R17  
2
R44, R47  
0
R12, R13  
R34, R59  
2
Panasonic  
Panasonic  
Panasonic  
Panasonic  
Panasonic  
Panasonic  
R35, R36  
3
R31, R41, R60  
R15, R16  
2
P200HCT-ND  
R85, R86  
3
P330CHCT-ND  
P499HCT-ND  
R45, R87, R88  
R83, R84  
2
ERJ-3EKF4990V  
ERJ-3EKF1002V  
11  
P10.0KHCT-ND  
R2, R3, R4, R7, R8,  
R9, R26, R32, R33,  
R39, R40  
4.75-k, 1/16-W, 1%  
15.4-k, 1/16-W, 1%  
20-k, 1/16-W, 1%  
36.5-k, 1/16-W, 1%  
56.2-k, 1/16-W, 1%  
4.99-k, 1/16-W, 1%  
61.9-k, 1/16-W, 1%  
0.033-, 1/4-W, 5%  
348-, 1/16-W, 1%  
49.9-, 1/16-W, 1%  
78.7-, 1/16-W, 1%  
100-, 1/16-W, 1%  
20-R-pack, 5%, 0.063-W  
10-kresistor pack  
603  
2
1
3
1
1
3
2
2
2
3
2
2
2
1
ERJ-3EKF4751V  
ERJ-3EKF1542V  
ERJ-3EKF2002V  
ERJ-3EKF3652V  
ERJ-3EKF5622V  
ERJ-3EKF4991V  
ERJ-3EKF6192V  
RL1220T-R033-J  
ERJ-2RKF3480X  
ERJ-2RKF49R9X  
ERJ-2RKF78R7X  
ERJ-2RKF1000X  
742C163220JTR  
742C163103JTR  
Panasonic  
Panasonic  
Panasonic  
Panasonic  
Panasonic  
Panasonic  
Panasonic  
Susumu Co,. Ltd.  
Panasonic  
Panasonic  
Panasonic  
Panasonic  
CTS  
P4.75KHCT-ND  
P15.4KHCT-ND  
P20.0KHCT-ND  
P36.5KHCT-ND  
P56.2KHCT-ND  
P4.99KHCT-ND  
P61.9KHCT-ND  
RL12T.033JCT-ND  
P348LCT-ND  
R46, R49  
R65  
603  
603  
R30, R80, R81  
R66  
603  
603  
R1  
603  
R27, R28, R29  
R63, R64  
R61, R62  
R24, R25  
R19, R42, R43  
R20, R21  
R22, R23  
RP1, RP2  
RP3  
603  
805  
402  
402  
P49.9LCT-ND  
402  
P78.7LCT-ND  
402  
P100LCT-ND  
CTS-742_8RES  
CTS_742_8RES  
742C163220JCT-ND  
742C163103JCT-ND  
CTS  
22  
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Physical Description  
Table 5. Bill of Materials (continued)  
NOT  
INSTALLED  
VALUE  
FOOTPRINT  
QTY  
PART NUMBER  
VENDOR  
DIGI-KEY NUMBER  
REF DESIGNATOR  
FERRITE BEADS, CONNECTORS, JUMPERS, JACKS, ICs, ETC.  
Ferrite bead  
1206  
5
EXC-ML32A680U  
Panasonic  
P10437CT-ND  
FB2, FB3, FB4, FB6,  
FB7  
FB8, FB9,  
FB10  
Inductor, SMT, 15-µH, 2.6-A  
Inductor, SMT, 5-µH, 2.9-A  
0.0-, 1/8-W, 5% resistor  
Red test point  
COIL-CDRH8D43  
COIL-CDRH6D38  
805  
1
1
2
8
CDRH8D43-150  
CDRH6D38-5R0  
ERJ-6GEY0R00V  
5000k  
Sumida  
Sumida  
L1  
CDRH6D38-5R0NC-ND L2  
Panasonic  
Keystone  
P0.0ACT-ND  
5000K-ND  
L3, L4  
TP1, TP4, TP9, TP10 TP3 TP11  
Test_point2  
TP12 TP13  
Black test point  
40-pin header  
Test_point2  
4
1
2
5001k  
Keystone  
Samtec  
Samtec  
5000K-ND  
TP5 TP6 TP7 TP8  
20×2×.1  
HTSW-120-07-L-D  
MMS-120-02-T-DV  
J4  
40-pin header smt  
20X2_SMT_MMS_  
SAMTEC  
J5, J6  
Red banana jacks  
BANANA_JACK  
5
ST-351A  
Allied  
N/A  
J11, J12, J13, J14,  
J15  
Black banana jacks  
SMA connectors  
3POS_header  
BANANA_JACK  
SMA_Jack  
4
3
1
1
0
3
ST-351B  
901-144-8RFX  
HTSW-150-07-L-S  
HTSW-120-07-L-D  
93F7124  
Allied  
AMP  
N/A  
J9, J10, J16, J17  
J1, J3, J7  
JP2(1)  
ARFX1231-ND  
J8  
3pos_jumper  
6×1×.1  
Samtec  
Samtec  
Newark  
Mini-Circuits  
6-pin header  
JP1  
3-pin power connector  
Transformer  
3term_screw_con  
J20  
TC4-1W_  
TC4-1W  
T1, T2, T3  
TRANSFORMER  
Diode, Schottky, 1-A, 20-V  
Diode, Schottky, 3-A, 20-V  
Green SM_LED_1206  
DIODE-MBRM120  
DO-214AB(SMC)  
LED-1206  
1
1
2
2
MBRM120E  
SS32  
ON Semiconductor  
Vishay  
D2  
D1  
CMD15-21VGC/TR8  
SI2323DS  
Panasonic  
Vishay  
L62205CT-ND  
D3, D4  
Q1, Q2  
MOSFET, P-CH, 20-V, 4.7-A,  
3-SOT-23  
39-MΩ  
TRANS BIAS NPN, 50-V  
Switch  
SOT416  
EVQ-PJ  
1
1
1
DTC114EET1  
EVQ-PJX04M  
TDA08H0SK1  
ON Semiconductor  
Panasonic  
ITT  
DTC114EET1OS-ND  
P8050SCT-ND  
Q3  
S1  
Switch, 8-Pos, half-pitch SMT  
SWITCH_8POS_  
SMT  
CKN1365-ND  
SW1  
3-circuit jumpers  
3-circuit jumpers  
SJP3_RESISTOR  
SJP3_402  
2
2
ERJ-3GEY0R00V  
ERJ-2GE0R00X  
Panasonic  
Panasonic  
P0.0GCT-ND  
P0.0JCT-ND  
SJP4(2), SJP5(3)  
SJP1(4), SJP2(5)  
(1)  
Add jumper for JP2 between pins 1 to 2.  
(2)  
(3)  
(4)  
(5)  
Add jumper for SJP4 between pins 2 and 3 (use a 0-resistor to short pins).  
Add jumper for SJP5 between pins 2 and 3 (use a 0-resistor to short pins).  
Add jumper for SJP1 between pins 1 and 2 (use a 0-resistor to short pins).  
Add jumper for SJP2 between pins 1 and 2 (use a 0-resistor to short pins).  
SLWU028BJanuary 2006Revised November 2006  
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Physical Description  
Table 5. Bill of Materials (continued)  
NOT  
INSTALLED  
VALUE  
FOOTPRINT  
QTY  
PART NUMBER  
VENDOR  
DIGI-KEY NUMBER  
REF DESIGNATOR  
U1  
ADS5525/27, ADS5545/46/47  
48-QFN_MOD  
1
ADS5525/27,  
TI  
ADS5545/46/47  
Spartan-3E XC3S250E  
256-BGA-  
XC3S250E-4FT256CES  
Xilinx  
U2  
1mm_XILINX  
IC amp, fully-diff, wideband  
XCF16PFSG48  
16-QFN(RGT)  
48PIN_BGA_XILINX  
20-pin-QFN  
1
1
1
1
1
1
1
4
4
THS4509RGTT  
XCF16PFSG48  
TPS75003RHLR  
TPS73018DBVT  
TLV3502AIDCNT  
SN74LVC1G86DBVR  
N/A  
TI  
296-17730-1-ND  
U3  
U4  
U6  
U7  
U9  
U10  
Xilinx  
IC, pwr-mgmt, triple-supply  
IC, LDO reg, hi-PSRR, 1.8-V  
IC, comparator, R-R, hi-spd  
IC, EX-OR gate, 2-in  
2-pos shunt  
TI  
296-17835-2-ND  
296-17577-1-ND  
296-18147-2-ND  
296-9853-1-ND  
929955-06-ND  
H781-ND  
5-SOT(DBV)  
TI  
8-TSSOP(DCN)  
5-SOT(DBV)  
TI  
TI  
3M  
Shorting jumper  
4-40 × 3/8"  
Screw  
N/A  
Building Fasteners  
Keystone  
Standoff, hex (1/4 x .5")  
4-40 screw  
N/A  
1902CK-ND  
24  
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Physical Description  
5.3 PCB Schematics  
The schematics for the EVM are on the following pages.  
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U2A  
XILINX XC3S500E_FT256  
2.5V  
VCCO_0  
B5  
B12  
F7  
A14  
B14  
A13  
B13  
E11  
D11  
B11  
C11  
E10  
D10  
F8  
IO_L01N_0  
IO_L01P_0  
IO_L03N_0/VREF_0  
VCCO_0  
VCCO_0  
VCCO_0  
VCCO_0  
F10  
2
IO_L03P_0  
JP2  
IO_L04N_0  
(1-2)  
IO_L04P_0  
IO_L05N_0/VREF_0  
IO_L05P_0  
IO_L06N_0  
IO_L06P_0  
IO_L12N_0  
IO_L12P_0  
IO_L08N_0/GCLK5  
IO_L08P_0/GCLK4  
3.3V  
DRVDD  
D
C
B
A
D
C
B
A
C3  
.1uF  
C1  
C8  
+
.1uF  
E8  
F9  
E9  
10uF  
CLKOUTM  
CLKOUTP  
D12_D13P  
D12_D13M  
A9  
A10  
IO_L09N_0/GCLK7  
IO_L09P_0/GCLK6  
D10_D11P  
D10_D11M  
D8_D9P  
D8_D9M  
D6_D7P  
D6_D7M  
D4_D5P  
D4_D5M  
B8  
A8  
D8  
C8  
D7  
E7  
D6  
C6  
E6  
D5  
A4  
IP_L10N_0/GCLK9  
IP_L10P_0/GCLK8  
IO_L11N_0/GCLK11  
IO_L11P_0/GCLK10  
IO_L14N_0/VREF_0  
IO_L14P_0  
IO_L15N_0  
IO_L15P_0  
IP_L16N_0  
IP_L16P_0  
IO_L17N_0/VREF_0  
IO_L17P_0  
IO_L18N_0  
IO_L18P_0  
IO_L19N_0/HSWAP  
IO_L19P_0  
IP  
IP  
AVDD  
C7  
B7  
NC  
NC  
C9  
C4  
C5  
C6  
.1uF  
C7  
.1uF  
C10  
.1uF  
C19  
.1uF  
+
10uF  
.1uF  
.1uF  
A5  
D2_D3P  
D2_D3M  
C4  
C5  
B3  
C3  
A3  
C13  
C12  
D12  
C9  
C10  
U1-H6  
U1-H5  
(Sh 4) U1-H6  
3.3V  
(Sh 4) U1-H5  
A1  
B9  
F6  
G7  
G8  
G9  
H8  
R3  
R27  
R30  
IP_L02N_0  
IP_L02P_0  
IP_L07N_0  
IP_L07P_0  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
10K  
4.99K  
20K  
DFS  
A7  
A12  
B4  
B6  
B10  
(Sh 4)  
DFS  
IO  
IO  
IO  
IP  
IP  
1
2
3
4
5
6
7
8
9
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
DRGND  
DRVDD  
OVR  
CLKOUTM  
CLKOUTP  
DFS  
OE  
AVDD  
AGND  
CLKP  
DRGND  
DRVDD  
D0_D1P  
D0_D1M  
N/C  
N/C  
RESET  
SCLK  
SDATA  
SEN  
AVDD  
AGND  
TP10  
OVR  
D0_D1P  
D0_D1M  
(Sh 4)  
(Sh 4)  
OVR  
OE  
CLKOUTM  
CLKOUTP  
D9  
IO_VREF_0  
R10  
0
OE  
R41  
100 RESET  
SCLK  
U1-G2  
RESET (Sh 4)  
SCLK (Sh 4)  
SDATA (Sh 4)  
U1-G2 (Sh 4)  
U1  
R48  
R6  
0
R18  
0
SDATA  
3.3V  
R81  
U1-G3  
TP4  
ADS5545_48PIN-QFN  
U1-G3 (Sh 4)  
CLKP  
CLKM  
10  
11  
12  
0
(Sh 4) CLKP  
(Sh 4) CLKM  
CLKPM  
AGND  
R29  
R7  
S1  
DRVDD  
20K  
4.99K  
10K  
SW-PB  
SEN  
SEN  
(Sh 4)  
R2  
10K  
U1-H4  
U1-H3  
U1-H4 (Sh 4)  
3.3V  
U1-H3 (Sh 4)  
DRVDD  
R80  
20K  
R28  
R4  
10K  
TP1  
R5  
0
VCM  
CM  
4.99K  
R32  
(Sh 2) VCM  
DFS  
3.3V  
MODE  
(Sh 2) CM  
MODE (Sh 4)  
10K  
3.3V  
C14  
.1uF  
IREF  
C115  
.1uF  
C117  
2.2uF  
C116  
.1uF  
U9  
TLV3502  
R1  
56.2K  
R33  
10K  
1
2
3
4
8
7
6
5
+IN A  
V+  
OUT A  
OUT B  
V-  
TP9  
U10  
1
2
-IN A  
+IN B  
-IN B  
4
M0  
M0  
(Sh 4)  
INP  
R39  
10K  
(Sh 2) INP  
SN74LVC1G86  
INM  
(Sh 2) INM  
R40  
10K  
12500 TI Boulevard. Dallas, Texas 75243  
Title:  
ADS5545  
Engineer:  
J. VENABLE  
Drawn By: Y. DEWONCK  
Note 1. Part not installed  
SIZE:  
DATE:  
REV:  
11-Jul-2006  
B
FILE:  
SHEET:  
OF:  
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1
2
3
4
5
6
+VCC  
AMPLIFIER PATH:  
AC Couple (default)  
C11  
.1uF  
C12  
.1uF  
C13  
10uF  
C40  
10uF  
C45 C47 = 0.1uF  
R26 R27 = 200 Ohms  
R5 = 0 Ohms  
R24  
VCC= 5 V, VEE = GND  
348  
D
C
B
A
D
C
B
A
TP3  
DC Couple  
J1  
C45 C47 = 0 Ohms  
SMA_END  
C44  
.1uF  
R22  
100  
R26 R27 = Unpopulated  
R5 = Unpopulated  
1
AMP_P  
VCC= 4 V, VEE = -1V  
1
2
C45  
N/C  
Vin-  
R44  
4.7  
L3  
R42  
49.9  
49.9  
3
Vout+  
Vout-  
R85  
200  
0 ohm  
R20  
69.8  
R83  
499  
U3  
C2  
0 ohm  
C47  
THS4509  
20pF  
C118  
20pF  
C119  
11  
4
CM  
Vin+  
CM  
L4  
R43  
10  
20pF  
VCM  
0 ohm  
(Sh 1) VCM  
0 ohm  
R86  
200  
R47  
4.7  
C16  
.1uF  
C49  
.1uF  
R84  
499  
AMP_M  
R21  
69.8  
R23  
100  
R25  
348  
-VCC  
R19  
49.9  
C17  
.1uF  
C29  
C30  
10uF  
C41  
.1uF  
10uF  
C46  
.22uF  
Note : R12, C20, and R13 are to be un-populated  
on ADS5525/45/46 EVMs.  
AMP_M  
R12, C20, and R13 may be populated for  
future ADC boards; contact factory for details.  
R17  
24.9  
CM  
CM  
SJP4  
R37  
4.02  
2
INM  
(Sh 1)  
INM  
(2-3)  
J3  
AIN  
R12  
36  
C15  
1
4
6
T1  
3
2
1
1
2
3
T2  
6
4
.1uF  
C113  
.1uF  
C52  
.1uF  
R34  
49.9  
(Note 1)  
R15  
200  
R16  
200  
R35  
49.9  
R36  
49.9  
C20  
2pF  
(Note 1)  
TC4-1W  
TC4-1W  
AMP_P  
R13  
36  
C55  
.1uF  
C62  
.1uF  
C51  
.1uF  
SJP5  
R38  
4.02  
2
INP  
INP (Sh 1)  
(2-3)  
12500 TI Boulevard. Dallas, Texas 75243  
Title:  
ADS5545  
Engineer:  
J. VENABLE  
DOCUMENTCONTROL #  
REV:  
OF:  
B
Drawn By: Y. DEWONCK  
FILE:  
Note 1. Part not installed  
1
2
3
4
5
6
SIZE:  
DATE:  
17-Jul-2006  
SHEET:  
2
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1
2
3
4
5
6
D
C
B
A
D
C
B
A
R54  
0
1
2
(Note 1)  
J7  
CLK_INP  
C25  
.1uF  
1
6
4
T3  
1
2
3
R59  
49.9  
R60  
100  
R31  
100  
SJP2  
(Note 1)  
TC4-1W  
J8  
2
CLKP  
CLKP (Sh 1)  
CLK_INM  
(1-2)  
R56  
0
C26  
.1uF  
1
(Note 1)  
(Note 1)  
R58  
0
2
CLKM  
SJP1  
CLKM (Sh 1)  
(1-2)  
12500 TI Boulevard. Dallas, Texas 75243  
Title:  
ADS5545  
Engineer:  
Drawn By:  
FILE:  
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2
3
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5
6
5V  
U2B  
5V  
J6  
40PIN_IDC  
XILINX XC3S500E_FT256  
3.3V  
J5  
J4  
R79  
20  
CLKOUT  
RP1  
20 Ohm  
R15  
R16  
P15  
P16  
M16  
N16  
L15  
L14  
J16  
K16  
H14  
H15  
G16  
G15  
F15  
F14  
D14  
D15  
C15  
C16  
K12  
K13  
K14  
K15  
J13  
E15  
G11  
K11  
2
4
6
8
1
3
5
7
9
2
4
6
8
1
3
5
7
9
IO_L01N_1/A15  
IO_L01P_1/A16  
IO_L02N_1/A13  
IO_L02P_1/A14  
IO_L04N_1/VREF_1  
IO_L04P_1  
IO_L06N_1  
VCCO_1  
VCCO_1  
VCCO_1  
VCCO_1  
2
4
6
8
1
3
5
7
9
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
16  
15  
14  
13  
12  
11  
10  
9
ADC_D0  
ADC_D1  
ADC_D2  
ADC_D3  
ADC_D4  
ADC_D5  
ADC_D6  
ADC_D7  
ADC_D8  
ADC_D9  
ADC_D10  
ADC_D11  
ADC_D12  
ADC_D13  
ADC_D14  
ADC_D15  
M15  
U2D  
XILINX XC3S500E_FT256  
10  
10  
10  
3.3V  
12 11  
14 13  
16 15  
18 17  
20 19  
22 21  
24 23  
26 25  
28 27  
30 29  
32 31  
34 33  
36 35  
38 37  
40 39  
12 11  
14 13  
16 15  
18 17  
20 19  
22 21  
24 23  
26 25  
28 27  
30 29  
32 31  
34 33  
36 35  
38 37  
40 39  
12 11  
14 13  
16 15  
18 17  
20 19  
22 21  
24 23  
26 25  
28 27  
30 29  
32 31  
34 33  
36 35  
38 37  
40 39  
ADC_D6 R1  
ADC_D5 R2  
ADC_D4 P1  
ADC_D3 P2  
ADC_D2 N1  
ADC_D1 M1  
E2  
G6  
K6  
M2  
IO_L06P_1  
IO_L19N_3  
IO_L19P_3  
IO_L18N_3  
IO_L18P_3  
VCCO_3  
VCCO_3  
VCCO_3  
VCCO_3  
D
C
B
A
D
C
B
A
IO_L09N_1/A9/RHCLK1  
IO_L09P_1/A10/RHCLK0  
IO_L11N_1/A5/RHCLK5  
IO_L11P_1/A6/RHCLK4/IRDY1  
IO_L13N_1/A1  
IO_L13P_1/A2  
IO_L15N_1  
SW16  
SW15  
SW14  
SW13  
SW12  
SW9  
IO/HDC  
SW10  
SW11  
IO_L16N_3  
IO_L16P_3  
IO_L15N_3  
IO_L15P_3  
IO_L12N_3  
IO_L12P_3  
IO_L05N_3  
IO_L05P_3  
IO_L03N_3  
IO_L03P_3  
IO_L02N_3/VREF_3  
IO_L02P_3  
IO_L01N_3  
IO_L01P_3  
IO_L06N_3  
IO_L06P_3  
IO_L07N_3  
L5  
K5  
ADC_D0 K1  
IO_L15P_1  
J1  
E1  
D1  
E4  
E3  
C2  
C1  
B2  
B1  
G4  
G5  
G2  
G3  
H6  
H5  
H4  
H3  
IO_L18N_1/LDC0  
IO_L18P_1/HDC  
IO_L19N_1/LDC2  
IO_L19P_1/LDC1  
IO_L07N_1/A11  
IO_L07P_1/A12  
IO_L08N_1/VREF_1  
IO_L08P_1  
(Sh 5)  
IO/HDC  
RP2  
20 Ohm  
N15  
N14  
L13  
L12  
E16  
E13  
40PIN_IDC  
40PIN SMT MMS  
NC  
NC  
NC  
IO_L10N_1/A7/RHCLK3/TRDY1 NC  
J14  
IO_L10P_1/A8/RHCLK2  
IO_L12N_1/A3/RHCLK7  
IO_L12P_1/A4/RHCLK6  
IO_L14N_1/A0  
IO_L14P_1  
IO_L16N_1  
NC  
NC  
CTRL_LE  
CTRL_DATA  
CTRL_CLK  
H11  
H12  
G14  
G13  
F12  
F13  
MODE  
U1-G2  
U1-G3  
U1-H6  
U1-H5  
U1-H4  
U1-H3  
CTRL_LE  
CTRL_DATA  
CTRL_CLK  
(Sh 1) MODE  
(Sh 1) U1-G2  
(Sh 1) U1-G3  
(Sh 1) U1-H6  
(Sh 1) U1-H5  
(Sh 1) U1-H4  
(Sh 1) U1-H3  
(Sh 1) RESET  
F4  
F3  
L2  
L3  
L4  
M4  
NC  
NC  
NC  
NC  
NC  
NC  
IO_L07P_3  
IO_L08N_3/LHCLK1  
IO_L08P_3/LHCLK0  
IO_L09N_3/LHCLK3/IRDY2  
IO_L09P_3/LHCLK2  
IO_L10N_3/LHCLK5  
IO_L10P_3/LHCLK4/TRDY2  
IO_L11N_3/LHCLK7  
IO_L11P_3/LHCLK6  
IO_L13P_3  
OE  
(Sh 1)  
OE  
IO_L16P_1  
RESET  
CLKOUT J2  
J3  
B16  
E14  
G12  
H16  
J11  
IP  
IP  
IP  
IP  
IP  
IP  
IP  
OVR  
SCLK  
J4  
J5  
(Sh 1)  
OVR  
(Sh 1) SCLK  
A16  
F11  
G10  
H9  
H10  
J9  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
3.3V  
U2C  
SDATA  
SEN  
K2  
K3  
(Sh 1) SDATA  
XILINX XC3S500E_FT256  
3.3V  
L7  
L10  
R5  
(Sh 1)  
SEN  
IO_L13N_3  
J12  
M13  
M7  
T12  
T8  
D3  
LED_1206  
IP  
IP  
IO/D5  
IO/M1  
VCCO_2  
VCCO_2  
VCCO_2  
D2  
F2  
H1  
J6  
K4  
M3  
N3  
IP  
IP  
IP  
IP  
IP  
IP  
IP  
J10  
J15  
T10  
R12  
M14  
D16  
H13  
VCCO_2  
IO  
DFS  
(Sh 1)  
DFS  
IO/VREF_1  
IP/VREF_1  
P13  
R4  
H2  
H7  
J7  
IO/VREF_2  
IO/VREF_2  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
R87  
330  
R9  
T9  
J8  
IP_L11N_2/M2/GCLK1  
IP_L11P_2/RDWR_B/GCLK0  
IO/L03N_2/MOSI/CSI_B  
IO/L03P_2/DOUT/BUSY  
IO/L01N_2/INIT_B  
IO/L01P_2/CSO_B  
IP_L02N_2  
F5  
K7  
L6  
T1  
IO  
N5  
P5  
P4  
P3  
R3  
T3  
BUSY  
G1  
N2  
(Sh 5)  
(Sh 5)  
BUSY  
INIT_B  
IP/VREF_3  
IO/VREF_3  
INIT_B  
ADC_D7  
IP_L02P_2  
IO/L04N_2  
IO/L04P_2  
IO/L05N_2  
IO/L05P_2  
IO/L06N_2  
IO/L06P_2  
ADC_D8  
ADC_D9  
ADC_D10  
ADC_D13  
ADC_D12  
ADC_D11  
T5  
T4  
P7  
N7  
P10  
R10  
NC  
NC  
NC  
NC  
N6  
M6  
P6  
R6  
T7  
RP3  
10K Ohm  
IP_L08N_2/VREF_2  
R7  
N9  
P9  
P11  
R11  
N12  
P12  
R13  
T13  
L8  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
IP_L08P_2  
IO/L12N_2/D1/GCLK3  
IO/L12P_2/D2/GCLK2  
IO/L16N_2/A22  
IO/L16P_2/A23  
IO/L18N_2/A20  
IO/L18P_2/A21  
IO/L19N_2/VS1/A18  
IO/L19P_2/VS2/A19  
IO/L09N_2/D6/GCLK13  
IO/L09P_2/D7/GCLK12  
IO/L10N_2/D3/GCLK15  
IO/L10P_2/D4/GCLK14  
IO/L13N_2/DIN/D0  
IO/L13P_2/M0  
M8  
P8  
N8  
M9  
SW1  
3.3V  
M0  
L9  
16  
1
2
3
4
5
6
7
8
SW16  
SW15  
SW14  
SW13  
SW12  
SW11  
SW10  
SW9  
(Sh 1)  
M0  
ADC_D14  
ADC_D15  
M10  
N10  
N11  
M11  
R14  
P14  
K8  
K9  
K10  
L11  
R8  
IO/L15N_2  
IO/L15P_2  
IP_L17P_2  
IP_L17N_2  
GND  
GND  
GND  
GND  
GND  
GND  
15  
14  
13  
12  
11  
10  
9
CCLK  
A23  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
(Sh 5) CCLK  
IO/L20N_2/CCLK  
IO/L20P_2/VS0/A17  
T16  
(Sh 5)  
A23  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
T2  
T14  
IP  
IP  
(Sh 5)  
D7  
SWITCH_8POS_SMT  
12500 TI Boulevard. Dallas, Texas 75243  
Title:  
ADS5545  
Engineer:  
Note 1. Part not installed  
J. VENABLE  
Drawn By: Y. DEWONCK  
DOCUMENTCONTROL #  
REV:  
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3.3V  
R88  
330  
2.5V  
D4  
LED_1206  
R49  
4.75K  
2.5V  
1.8V  
U4  
D
D
C
B
A
XCF16PFSG48  
Q3  
B1  
E1  
G6  
A3  
INIT_B  
R46  
4.75K  
R45  
330  
DTC114EET1  
VCCINT  
VCCINT  
VCCINT  
OE/RESET__  
INIT_B (Sh 4)  
U2E  
B3  
B4  
C1  
CCLK  
BUSY  
XILINX XC3S500E_FT256  
1.2V  
CLK  
CE__  
BUSY  
CCLK (Sh 4)  
DONE  
T15  
D3  
D4  
BUSY (Sh 4)  
DONE  
PROG_B  
TCK  
VCCINT  
VCCINT  
VCCINT  
VCCINT  
VCCINT  
VCCINT  
VCCINT  
VCCINT  
D13  
E5  
3.3V  
C2  
PROG_B  
CLKOUT  
E12  
M5  
H6  
H5  
E5  
D5  
C5  
B5  
A5  
A6  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
A15  
A2  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
B2  
C6  
D6  
G5  
M12  
VCCO  
VCCO  
VCCO  
VCCO  
N4  
TDI  
N13  
(Sh 4)  
C14  
B15  
TDO  
2.5V  
TMS  
H2  
A6  
A11  
F1  
F16  
L1  
L16  
T6  
T11  
VCCJ  
VCCAUX  
VCCAUX  
VCCAUX  
VCCAUX  
VCCAUX  
VCCAUX  
VCCAUX  
VCCAUX  
D1  
D2  
IO/HDC  
CF__  
IO/HDC (Sh 4)  
A4  
C3  
C4  
D3  
D4  
E3  
E4  
F2  
F3  
F4  
G2  
DNC  
DNC  
DNC  
DNC  
DNC  
DNC  
DNC  
DNC  
DNC  
DNC  
DNC  
CEO__  
E2  
E6  
G1  
G3  
G4  
H3  
H4  
TMS  
TDO  
C
TDI  
A23  
REV_SEL0  
REV_SEL1  
TCK  
A23  
(Sh 4)  
A1  
A2  
B6  
F1  
F5  
F6  
H1  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
(Sh 3)  
EN_EXT_SEL__  
R11  
0
3.3V  
JP1  
6X1X.1  
B
A
12500 TI Boulevard. Dallas, Texas 75243  
Title:  
ADS5545  
Engineer:  
Note 1. Part not installed  
J. VENABLE  
DOCUMENTCONTROL #  
REV:  
OF:  
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Drawn By: Y. DEWONCK  
FILE:  
DATE:  
SIZE:  
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L1  
1.2V  
+
1
2
1
2
G
S
3
VCCO_0  
BANK 0 DECOUPLING  
CDRH8D43-150  
15uH  
D
C60  
D1  
C85  
2.2uF  
C42  
C48  
C97  
C99  
100uF  
Q1  
FET-SI2323DS  
C57  
.01uF  
C58  
C31  
.22uF  
.22uF  
.022uF  
.022uF  
SS32  
R61  
.033  
D
C
B
A
D
C
B
A
1.5nF 1.5nF  
5V  
TP11  
5V  
R8  
C27  
.1uF  
10K  
5V  
IS1  
3.3V  
BANK 1 DECOUPLING  
C64  
1uF  
C61  
100uF  
C86  
C43  
C50  
C98  
C100  
2.2uF  
.22uF  
.22uF  
.022uF  
.022uF  
20  
1
11  
IN3  
FB1  
J20  
U6  
TPS75003  
2.5V  
R82  
3
2
1
10  
FB2  
OUT3  
FB2  
0
1.2V  
3.3V  
C63  
R63  
3.3V  
BANK 2 DECOUPLING  
10uF  
61.9K  
C87  
C54  
C75  
C101  
C103  
FB3  
IS2  
CON_3TERM_SCREW  
5V  
2.2uF  
.22uF  
.22uF  
.022uF  
.022uF  
R65  
C28  
.1uF  
15.4K  
R62  
C59  
.033  
TP12  
1.5nF  
5V  
R9  
3.3V  
BANK 3 DECOUPLING  
10K  
R26  
TP13  
R66  
C88  
C67  
C76  
C102  
C104  
36.5K  
10K  
C53  
Q2  
R64  
2.2uF  
.22uF  
.22uF  
.022uF  
.022uF  
2
1
L2  
61.9K  
C35  
10pF  
S
3
3.3V  
+
D
1
2
G
CDRH6D38-5R0  
5uH  
D2  
FET-SI2323DS  
100uF  
MBRM120  
1.2V  
VCCINT DECOUPLING  
C89  
2.2uF  
C90  
C91  
C92  
C77  
C78  
C79  
C80  
C105  
C106  
C107  
C108  
2.2uF  
2.2uF  
2.2uF  
.22uF  
.22uF  
.22uF  
.22uF  
.022uF  
.022uF  
.022uF  
.022uF  
5V  
U7  
TPS73018DBV  
1.8V  
2.5V  
VCCAUX CORE DECOUPLING  
1
3
5
IN  
OUT  
C18  
.1uF  
C114  
2.2uF  
C93  
C94  
C95  
C96  
C81  
C82  
C83  
C84  
C109  
C110  
C111  
C112  
4
2.2uF  
2.2uF  
2.2uF  
2.2uF  
.22uF  
.22uF  
.22uF  
.22uF  
.022uF  
.022uF  
.022uF  
.022uF  
EN  
NR  
12500 TI Boulevard. Dallas, Texas 75243  
Title:  
Note 1. Part not installed  
ADS5545  
Engineer:  
J. VENABLE  
Drawn By:  
FILE:  
SIZE:  
DATE:  
REV:  
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Diff Amp Positive Supply (+5.0V)  
+VCC  
FB3  
J13  
C66  
+
C71  
+
C34  
.1uF  
D
C
B
A
RED  
D
C
B
A
ADC Analog Supply (+3.3V)  
AVDD  
+3.3VA-PS  
47uF  
10uF  
J10  
J12  
FB2  
J11  
BLACK  
C65  
+
C70  
C33  
.1uF  
RED  
C32  
.1uF  
+
Diff Amp Negative Supply (-5.0V)  
-VCC  
47uF  
10uF  
J9  
FB4  
BLACK  
C68  
C73  
C37  
.1uF  
RED  
+
+
47uF  
10uF  
ADC DIGITAL SUPPLY(3.3V)  
DRVDD  
TP5  
TP6  
TP7  
FPGA POWER SUPPLY(5V)  
5V  
OUTPUT_BUFFER  
FB7  
FB6  
J15  
J16  
J14  
C38  
.1uF  
C69  
+
C74  
+
C39  
.1uF  
C72  
C36  
.1uF  
RED  
RED  
+
TP8  
47uF  
10uF  
10uF  
J17  
BLACK  
BLACK  
(Note 1)  
FB8  
(Note 1)  
FB9  
(Note 1)  
FB10  
12500 TI Boulevard. Dallas, Texas 75243  
Title:  
ADS5545  
Engineer:  
Drawn By:  
FILE:  
J. VENABLE  
DOCUMENTCONTROL #  
REV:  
OF:  
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Y. DEWONCK  
Note 1. Part not installed  
DATE:  
SIZE:  
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SHEET:  
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Physical Description  
EVALUATION BOARD/KIT IMPORTANT NOTICE  
Texas Instruments (TI) provides the enclosed product(s) under the following conditions:  
This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT,  
DEMONSTRATION, OR EVALUATION PURPOSES ONLY and is not considered by TI to be a  
finished end-product fit for general consumer use. Persons handling the product(s) must have  
electronics training and observe good engineering practice standards. As such, the goods being  
provided are not intended to be complete in terms of required design-, marketing-, and/or  
manufacturing-related protective considerations, including product safety and environmental  
measures typically found in end products that incorporate such semiconductor components or  
circuit boards. This evaluation board/kit does not fall within the scope of the European Union  
directives regarding electromagnetic compatibility, restricted substances (RoHS), recycling  
(WEEE), FCC, CE or UL, and therefore may not meet the technical requirements of these  
directives or other related directives.  
Should this evaluation board/kit not meet the specifications indicated in the User’s Guide, the  
board/kit may be returned within 30 days from the date of delivery for a full refund. THE  
FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY SELLER TO BUYER  
AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY,  
INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR  
PURPOSE.  
The user assumes all responsibility and liability for proper and safe handling of the goods. Further,  
the user indemnifies TI from all claims arising from the handling or use of the goods. Due to the  
open construction of the product, it is the user’s responsibility to take any and all appropriate  
precautions with regard to electrostatic discharge.  
EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE, NEITHER PARTY  
SHALL BE LIABLE TO THE OTHER FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR  
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TI currently deals with a variety of customers for products, and therefore our arrangement with the  
user is not exclusive.  
TI assumes no liability for applications assistance, customer product design, software  
performance, or infringement of patents or services described herein.  
Please read the User’s Guide and, specifically, the Warnings and Restrictions notice in the User’s  
Guide prior to handling the product. This notice contains important safety information about  
temperatures and voltages. For additional information on TI’s environmental and/or safety  
programs, please contact the TI application engineer or visit www.ti.com/esh.  
No license is granted under any patent right or other intellectual property right of TI covering or  
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Physical Description  
FCC Warning  
This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT,  
DEMONSTRATION, OR EVALUATION PURPOSES ONLY and is not considered by TI to be a  
finished end-product fit for general consumer use. It generates, uses, and can radiate radio  
frequency energy and has not been tested for compliance with the limits of computing devices  
pursuant to part 15 of FCC rules, which are designed to provide reasonable protection against  
radio frequency interference. Operation of this equipment in other environments may cause  
interference with radio communications, in which case the user at his own expense will be  
required to take whatever measures may be required to correct this interference.  
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265  
Copyright © 2006, Texas Instruments Incorporated  
EVM WARNINGS AND RESTRICTIONS  
It is important to operate this EVM within the AVDD voltage range of –0.3 V to 3.8 V and the  
DVDD voltage range of –0.3 V to 3.8 V.  
Exceeding the specified input range may cause unexpected operation and/or irreversible damage  
to the EVM. If there are questions concerning the input range, please contact a TI field  
representative prior to connecting the input power.  
Applying loads outside of the specified output range may result in unintended operation and/or  
possible permanent damage to the EVM. Please consult the EVM User's Guide prior to  
connecting any load to the EVM output. If there is uncertainty as to the load specification, please  
contact a TI field representative.  
During normal operation, some circuit components may have case temperatures greater than  
25°C. The EVM is designed to operate properly with certain components above 50°C as long as  
the input and output ranges are maintained. These components include but are not limited to  
linear regulators, switching transistors, pass transistors, and current sense resistors. These types  
of devices can be identified using the EVM schematic located in the EVM User's Guide. When  
placing measurement probes near these devices during operation, please be aware that these  
devices may be very warm to the touch.  
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265  
Copyright © 2006, Texas Instruments Incorporated  
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Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,  
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accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent  
TI deems necessary to support this warranty. Except where mandated by government requirements, testing  
of all parameters of each product is not necessarily performed.  
TI assumes no liability for applications assistance or customer product design. Customers are responsible  
for their products and applications using TI components. To minimize the risks associated with customer  
products and applications, customers should provide adequate design and operating safeguards.  
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent  
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or process in which TI products or services are used. Information published by TI regarding third-party  
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Following are URLs where you can obtain information on other Texas Instruments products and application  
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Products  
Applications  
Audio  
Amplifiers  
dsp.ti.com  
Data Converters  
DSP  
Broadband  
Digital Control  
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interface.ti.com  
logic.ti.com  
Logic  
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Microcontrollers  
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Security  
microcontroller.ti.com  
Telephony  
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Wireless  
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Post Office Box 655303 Dallas, Texas 75265  
Copyright © 2007, Texas Instruments Incorporated  
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