Sony Network Card 486DX User Manual

AR-B1474

INDUSTRIAL GRADE

486DX/DX2/DX4 CPU CARD

User’ s Guide

Edition: 3.1

Book Number: AR-B1474-99.B01

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AR-B1474 User¡¦s Guide

Table of Contents

0. PREFACE....................................................................................................................................................... 0-3

0.1

0.2

0.3

0.4

0.5

0.6

0.7

COPYRIGHT NOTICE AND DISCLAIMER ................................................................................................................................0-3

WELCOME TO THE AR-B1474 SERIAL CPU BOARD.............................................................................................................0-3

BEFORE YOU USE THIS GUIDE...............................................................................................................................................0-3

RETURNING YOUR BOARD FOR SERVICE............................................................................................................................0-3

TECHNICAL SUPPORT AND USER COMMENTS...................................................................................................................0-3

ORGANIZATION..........................................................................................................................................................................0-4

STATIC ELECTRICITY PRECAUTIONS....................................................................................................................................0-4

1. OVERVIEW..................................................................................................................................................... 1-1

1.1

1.2

1.3

INTRODUCTION .........................................................................................................................................................................1-1

PACKING LIST ............................................................................................................................................................................1-2

FEATURES..................................................................................................................................................................................1-2

2. SYSTEM CONTROLLER ................................................................................................................................ 2-1

2.1

2.2

2.3

DMA CONTROLLER ...................................................................................................................................................................2-1

KEYBOARD CONTROLLER.........................................................................................................................................................2-1

INTERRUPT CONTROLLER ......................................................................................................................................................2-2

I/O Port Address Map..........................................................................................................................................................2-3

Real-Time Clock and Non-Volatile RAM ............................................................................................................................2-4

Timer....................................................................................................................................................................................2-4

ISA Bus Pin Assignment .....................................................................................................................................................2-5

ISA Bus Signal Description .................................................................................................................................................2-6

SERIAL PORT .............................................................................................................................................................................2-7

PARALLEL PORT........................................................................................................................................................................2-9

2.3.1

2.3.2

2.3.3

2.3.4

2.3.5

2.4

2.5

3. SETTING UP THE SYSTEM............................................................................................................................ 3-1

3.1

3.2

3.2.1

OVERVIEW..................................................................................................................................................................................3-1

SYSTEM SETTING .....................................................................................................................................................................3-2

Serial Port............................................................................................................................................................................3-2

Hard Disk (IDE) Connector (CN1).......................................................................................................................................3-3

Power Connector (J5) .........................................................................................................................................................3-3

FDD Port Connector (CN2).................................................................................................................................................3-4

Parallel Port Connector (CN3) ............................................................................................................................................3-4

PC/104 Connector...............................................................................................................................................................3-5

CPU Setting.........................................................................................................................................................................3-7

Memory Setting....................................................................................................................................................................3-9

LED Header (J1, J2 & J4) .................................................................................................................................................3-10

3.2.2

3.2.3

3.2.4

3.2.5

3.2.6

3.2.7

3.2.8

3.2.9

3.2.10

3.2.11

3.2.12

3.2.13

3.2.14

Keyboard Connector .....................................................................................................................................................3-10

External Speaker Header (J3) ......................................................................................................................................3-11

Reset Header (J7).........................................................................................................................................................3-11

Battery Setting...............................................................................................................................................................3-11

CRT Display Type Select (JP13)..................................................................................................................................3-11

4. INSTALLATION.............................................................................................................................................. 4-1

4.1

4.2

4.3

OVERVIEW..................................................................................................................................................................................4-1

UTILITY DISKETTE.....................................................................................................................................................................4-2

WRITE PROTECT FUNCTION...................................................................................................................................................4-5

Hardware Write Protect.......................................................................................................................................................4-5

Software Write Protect ........................................................................................................................................................4-5

Enable the Software Write Protect......................................................................................................................................4-5

Disable the Software Write Protect.....................................................................................................................................4-5

WATCHDOG TIMER...................................................................................................................................................................4-6

Watchdog Timer Setting......................................................................................................................................................4-6

Watchdog Timer Enabled....................................................................................................................................................4-7

Watchdog Timer Trigger......................................................................................................................................................4-7

Watchdog Timer Disabled...................................................................................................................................................4-7

4.3.1

4.3.2

4.3.3

4.3.4

4.4

4.4.1

4.4.2

4.4.3

4.4.4

5. SOLID STATE DISK ....................................................................................................................................... 5-1

5.1

5.2

5.2.1

5.2.2

5.2.3

5.2.4

5.2.5

5.3

5.3.1

5.3.2

OVERVIEW..................................................................................................................................................................................5-1

SWITCH SETTING......................................................................................................................................................................5-1

Overview..............................................................................................................................................................................5-2

I/O Port Address Select (SW1-1 & SW1-2)........................................................................................................................5-2

SSD Firmware Address Select (SW1-3 & SW1-4).............................................................................................................5-2

SSD Drive Number (SW1-5 & SW1-6) ...............................................................................................................................5-3

ROM Type Select (SW1-7 & SW1-8)..................................................................................................................................5-4

JUMPER SETTING .....................................................................................................................................................................5-5

SSD BIOS Select (JP7).......................................................................................................................................................5-5

SSD Memory Type Setting (M1 ~ M3 & JP5).....................................................................................................................5-6

0-1

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AR-B1474 User¡¦s Guide

5.4

5.4.1

5.4.2

5.4.3

5.4.4

5.4.5

5.5

5.5.1

5.5.2

ROM DISK INSTALLATION........................................................................................................................................................5-6

UV EPROM (27Cxxx)..........................................................................................................................................................5-6

Large Page 5V FLASH Disk................................................................................................................................................5-8

Small Page 5V FLASH ROM Disk......................................................................................................................................5-9

RAM Disk...........................................................................................................................................................................5-11

Combination of ROM and RAM Disk................................................................................................................................5-12

INSTALLATION D.O.C..............................................................................................................................................................5-12

Hardware Setting...............................................................................................................................................................5-12

Software Setting ................................................................................................................................................................5-13

6. BIOS CONSOLE............................................................................................................................................. 6-1

6.1

6.2

6.3

6.4

6.5

6.6

6.7

6.7.1

6.7.2

6.8

6.8.1

6.8.2

6.9

6.9.1

6.9.2

BIOS SETUP OVERVIEW ..........................................................................................................................................................6-1

STANDARD CMOS SETUP........................................................................................................................................................6-2

ADVANCED CMOS SETUP........................................................................................................................................................6-3

ADVANCED CHIPSET SETUP...................................................................................................................................................6-5

POWER MANAGEMENT............................................................................................................................................................6-6

AUTO-DETECT HARD DISKS....................................................................................................................................................6-7

PASSWORD SETTING...............................................................................................................................................................6-7

Setting Password.................................................................................................................................................................6-7

Password Checking.............................................................................................................................................................6-7

LOAD DEFAULT SETTING.........................................................................................................................................................6-7

Auto Configuration with Optimal Setting.............................................................................................................................6-7

Auto Configuration with Fail Safe Setting...........................................................................................................................6-7

BIOS EXIT....................................................................................................................................................................................6-8

Save Settings and Exit ........................................................................................................................................................6-8

Exit Without Saving .............................................................................................................................................................6-8

7. SPECIFICATIONS .......................................................................................................................................... 7-1

8. PLACEMENT & DIMENSIONS........................................................................................................................ 8-1

8.1

PLACEMENT...............................................................................................................................................................................8-1

8.2

DIMENSIONS ..............................................................................................................................................................................8-2

9. MEMORY BANKS & PROGRAMMING RS-485............................................................................................... 9-1

9.1

USING MEMORY BANK .............................................................................................................................................................9-1

9.2

PROGRAMMING RS-485 ...........................................................................................................................................................9-2

10.

10.1

10.2

SSD TYPES SUPPORTED & INDEX ..........................................................................................................10-1

SSD TYPES SUPPORTED...................................................................................................................................................10-1

INDEX ....................................................................................................................................................................................10-3

0-2

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AR-B1474 User¡¦s Guide

0.PREFACE

0.1 COPYRIGHT NOTICE AND DISCLAIMER

September 1995

Acrosser Technology makes no representations or warranties with respect to the contents hereof and specifically

disclaims any implied warranties of merchantability or fitness for any particular purpose. Furthermore, Acrosser

Technology reserves the right to revise this publication and to make changes from time to time in the contents

hereof without obligation of Acrosser Technology to notify any person of such revisions or changes.

Possession, use, or copying of the software described in this publication is authorized only pursuant to a valid

written license from Acrosser or an authorized sublicensor.

No part of this publication may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated

into any language or computer language, in any form or any means, electronic, mechanical, magnetic, optical,

chemical, manual or otherwise, without the prior written consent of Acrosser Technology.

Acrosser, IBM, INTEL, AMD, CYRIX, AMI, MS-DOS, PC-DOS, DR-DOS, X-DOS…a re registered trademarks.

All other trademarks and registered trademarks are the property of their respective holders.

This document was produced with Adobe Acrobat 3.01.

0.2 WELCOME TO THE AR-B1474 SERIAL CPU BOARD

This guide introduces the Acrosser AR-B1474 serial CPU board.

Use the information describes this card’ s functions, features, and how to start, set up and operate your AR-B1474

serial CPU board. You also could find general system information here.

0.3 BEFORE YOU USE THIS GUIDE

If you have not already installed this AR-B1474, refer to the Chapter 3, “ Setting Up the System” in this guide.

Check the packing list, make sure the accessories in the package.

AR-B1474 diskette provides the newest information about the card. Please refer to the README.DOC file of

the enclosed utility diskette. It contains the modification and hardware & software information, and adding the

description or modification of product function after manual published.

0.4 RETURNING YOUR BOARD FOR SERVICE

If your board requires servicing, contact the dealer from whom you purchased the product for service information.

If you need to ship your board to us for service, be sure it is packed in a protective carton. We recommend that

you keep the original shipping container for this purpose.

You can help assure efficient servicing of your product by following these guidelines:

Include your name, address, telephone and facsimile number where you may be reached during the day.

A description of the system configuration and/or software at the time is malfunction.

A brief description is in the symptoms.

0.5 TECHNICAL SUPPORT AND USER COMMENTS

User’ s comments are always welcome as they assist us in improving the usefulness of our products and the

understanding of our publications. They form a very important part of the input used for product enhancement

and revision.

We may use and distribute any of the information you supply in any way we believe appropriate without incurring

any obligation. You may, of course, continue to use the information you supply.

If you have suggestions for improving particular sections or if you find any errors, please indicate the manual title

and book number.

Please send your comments to Acrosser Technology Co., Ltd. or your local sales representative.

Internet electronic mail to: [email protected]

0-3

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AR-B1474 User¡¦s Guide

0.6 ORGANIZATION

This information for users covers the following topics (see the Table of Contents for a detailed listing):

Chapter 1, “ Overview” , provides an overview of the system features and packing list.

Chapter 2, “ System Controller” describes the major structure.

Chapter 3, “ Setting Up the System” , describes how to adjust the jumper, and the connectors setting.

Chapter 4, “ Installation” , describes setup procedures including information on the utility diskette.

Chapter 5, “ Solid State Disk,” describes the various type SSD’ s installation steps.

Chapter 6, “ BIOS Console” , providing the BIOS options setting.

Chapter 7, Specifications

Chapter 8, Placement & Dimensions

Chapter 9, Memory Banks & Programming RS-485

Chapter 10, SSD Types Supported & Index

0.7 STATIC ELECTRICITY PRECAUTIONS

Before removing the board from its anti-static bag, read this section about static electricity precautions.

Static electricity is a constant danger to computer systems. The charge that can build up in your body may be

more than sufficient to damage integrated circuits on any PC board. It is, therefore, important to observe basic

precautions whenever you use or handle computer components. Although areas with humid climates are much

less prone to static build-up, it is always best to safeguard against accidents may result in expensive repairs. The

following measures should generally be sufficient to protect your equipment from static discharge:

Touch a grounded metal object to discharge the static electricity in your body (or ideally, wear a grounded

wrist strap).

When unpacking and handling the board or other system component, place all materials on an antic static

surface.

Be careful not to touch the components on the board, especially the “ golden finger” connectors on the bottom

of every board.

0-4

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AR-B1474 User¡¦s Guide

1. OVERVIEW

This chapter provides an overview of your system features and capabilities. The following topics are covered:

Introduction

Packing List

Features

1.1 INTRODUCTION

The AR-B1474 is a half size industrial grade CPU card that has been designed to withstand continuous operation

in harsh environments. The total on-board memory for the AR-B1474 can be configured from 1MB to 32MB by

using all 72-pin type DRAM devices.

The 8 layers PCB CPU card is equipped with a IDE HDD interface, a floppy disk drive adapter, 1 parallel port, 2

serial ports, a watchdog timer and a solid state disk. Its dimensions are as compact as 122mm x 185mm. It’ s

highly condensed features make it an ideal cost/performance solution for high-end commercial and industrial

applications where CPU speed and mean time between failure is critical.

The AR-B1474 provides 2 bus interfaces, ISA bus and PC/104 compatible expansion bus. Based on the PC/104

expansion bus, you could easy install thousands of PC/104 module from hundreds venders around the world. You

could also directly connect the power supply to the AR-B1474 on-board power connector in stand alone

applications.

A watchdog timer, which has a software programmable time-out interval, is also provided on this CPU card. It

ensures that the system will not hang-up if a program can not execute normally.

For diskless application, the AR-B1474 provides up to 3MB of bootable ROM, FLASH, or SRAM disk space by

using 64K x 8 to 1M x 8 memory chips.

The AR-B1474 is implemented with M1429 and M1431 chipset incorporate a memory controller, parity generation

and checking, two 8237 DMA controllers, two 8259 interrupt controllers, one 8254 timer/counter, an address buffer

and a data buffer.

A super I/O chip (SMC37C669) is embedded in the AR-B1474 card. It combines functions of a floppy disk drive

adapter, a hard disk drive (IDE) adapter, two serial (with 16C550 UART) adapters and 1 parallel adapter.

The I/O port configurations can be done by setting the BIOS setup program.

As an UART, the chip supports serial to parallel conversion on data characters received from a peripheral device

or a MODEM , and parallel to serial conversion on data character received from the CPU. The UART includes a

programmable baud rate generator, complete MODEM control capability and a processor interrupt system. As a

parallel port, the SMC37C669 provides the user with a fully bi-directional parallel centronics-type printer interface.

This manual has been written to assist you in installing, configuring and running the AR-B1474 CPU card. Each

section is intended to guide you through it’ s procedures clearly and concisely, allowing you to continue to the next

chapters without any difficulty.

1-1

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1.2 PACKING LIST

The accessories are included with the system. Before you begin installing your AR-B1474 card, take a moment to

make sure that the following items have been included inside the AR-B1474 package.

The quick setup manual

1 AR-B1474 all-in-one CPU card

1 Keyboard adapter cable

1 Parallel port interface cable

1 Hard disk drive interface cable

1 Floppy disk drive interface cable

1 40-pin header for PC/104 adapter

1 64-pin header for PC/104 adapter

1 Software utility diskettes

NOTE: If there are any discrepancies, please contact your Acrosser distributor immediately.

1.3 FEATURES

The system provides a number of special features that enhance its reliability, ensure its availability, and improve its

expansion capabilities, as well as its hardware structure.

All-in-one designed 486DX/DX2/DX4 CPU card

Support 3.3V/5V CPU with voltage regulator

Support ISA bus and PC/104 bus

Support 128KB to 512KB second level cache on-board

Support up to 32MB DRAM on-board

Support shadow memory and EMS

Legal AMI BIOS

IDE hard disk drive interface

Floppy disk drive interface

Bi-direction parallel interface

2 serial ports with 16C550 UART

DS12887 or compatible RTC

Programmable watchdog timer

Up to 3MB solid state disk (SSD)

On-board build-in buzzer

8 layers PCB

1-2

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AR-B1474 User¡¦s Guide

2. SYSTEM CONTROLLER

This chapter describes the major structure of the AR-B1474 serial CPU board. The following topics are covered:

DMA Controller

Keyboard Controller

Interrupt Controller

Serial Port

Parallel Port

2.1 DMA CONTROLLER

The equivalent of two 8237A DMA controllers are implemented in the AR-B1474 card. Each controller is a four-

channel DMA device that will generate the memory addresses and control signals necessary to transfer

information directly between a peripheral device and memory. This allows high-speed information transfer with less

CPU intervention. The two DMA controllers are internally cascaded to provide four DMA channels for transfers to

8-bit peripherals (DMA1) and three channels for transfers to 16-bit peripherals (DMA2). DMA2 channel 0 provides

the cascade interconnection between the two DMA devices, thereby maintaining IBM PC/AT compatibility.

Following is the system information of DMA channels:

DMA Controller 1

Channel 0: Spare

DMA Controller 2

Channel 4: Cascade for controller 1

Channel 5: Spare

Channel 1: IBM SDLC

Channel 2: Diskette adapter

Channel 3: Spare

Channel 6: Spare

Channel 7: Spare

Table 2-1 DMA Channel Controller

2.2 KEYBOARD CONTROLLER

The 8042 processor is programmed to support the serial keyboard serial interface. The keyboard controller

receives serial data from the keyboard, checks its parity, translates scan codes, and presents it to the system as a

byte data in its output buffer. The controller can interrupt the system when data is placed in its output buffer, or

wait for the system to poll its status register to determine when data is available.

Data can be written to the keyboard by writing data to the output buffer of the keyboard controller.

Each byte of data is sent to the keyboard controller in series with an odd parity bit automatically inserted. The

keyboard controller is required to acknowledge all data transmissions. Therefore, another byte of data will not be

sent to keyboard controller until acknowledgment is received for the previous byte sent. The “ output buffer full”

interrupt may be used for both send and receive routines.

2-1

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2.3 INTERRUPT CONTROLLER

The equivalent of two 8259 Programmable Interrupt Controllers (PIC) are included on the AR-B1474 card. They

accept requests from peripherals, resolve priorities on pending interrupts in service, issue interrupt requests to the

CPU, and provide vectors which are used as acceptance indices by the CPU to determine which interrupt service

routine to execute.

Following is the system information of interrupt levels:

Description

Interrupt Level

Parity check

NMI

CTRL2

CTRL1

System timer interrupt from timer 8254

Keyboard output buffer full

IRQ 0

IRQ 1

IRQ 2

IRQ8 : Real time clock

IRQ9 : Rerouting to INT 0Ah from hardware IRQ2

IRQ10 : Spare

IRQ11 : Spare

IRQ12 : Spare

IRQ13 : Math. coprocessor

IRQ14 : Hard disk adapter

IRQ15 : Spare (Watchdog Timer)

Serial port 2

IRQ 3

IRQ 4

IRQ 5

IRQ 6

IRQ 7

Serial port 1

Parallel port 2

Floppy disk adapter

Parallel port 1

Figure 2-1 Interrupt Controller

2-2

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2.3.1 I/O Port Address Map

Hex Range

000-01F

020-021

022-023

040-04F

050-05F

060-06F

070-071

080-09F

0A0-0A1

0C0-0DF

0F0

Device

DMA controller 1

Interrupt controller 1

M1429 chipset address

Timer 1

Timer 2

8042 keyboard/controller

Real-time clock (RTC), non-maskable interrupt (NMI)

DMA page registers

Interrupt controller 2

DMA controller 2

Clear Math Co-processor

Reset Math Co-processor

Math Co-processor

Fixed disk 1

0F1

0F8-0FF

170-178

1F0-1F8

201

Fixed disk 0

Game port

208-20A

210-213

214-215

218-21A

278-27F

290-293

294-295

2E8-2EF

2F8-2FF

310-313

314-315

378-37F

380-38F

390-393

394-395

3A0-3AF

3B0-3BF

3C0-3CF

3D0-3DF

3E8-3EF

3F0-3F7

3F8-3FF

EMS register 0

SSD

Watchdog

EMS register 1

Parallel printer port 3 (LPT 3)

SSD

Watchdog

Serial port 4 (COM 4)

Serial port 2 (COM 2)

SSD

Watchdog

Parallel printer port 2 (LPT 2)

SDLC, bisynchronous 2

SSD

Watchdog

Bisynchronous 1

Monochrome display and printer port 1 (LPT 1)

EGA/VGA adapter

Color/graphics monitor adapter

Serial port 3 (COM 3)

Diskette controller

Serial port 1 (COM 1)

Table 2-2 I/O Port Address Map

2-3

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2.3.2 Real-Time Clock and Non-Volatile RAM

The AR-B1474 contains a real-time clock compartment that maintains the date and time in addition to storing

configuration information about the computer system. It contains 14 bytes of clock and control registers and 114

bytes of general purpose RAM. Because of the use of CMOS technology, it consumes very little power and can be

maintained for long period of time using an internal Lithium battery. The contents of each byte in the CMOS RAM

are listed as follows:

Address

Description

Seconds

Second alarm

Minutes

Minute alarm

Hours

Hour alarm

Day of week

Date of month

Month

Year

Status register A

Status register B

Status register C

Status register D

Diagnostic status byte

Shutdown status byte

Diskette drive type byte, drive A and B

Fixed disk type byte, drive C

Fixed disk type byte, drive D

Reserved

Equipment byte

Low base memory byte

High base memory byte

Low expansion memory byte

High expansion memory byte

Reserved

19-2D

2E-2F

2-byte CMOS checksum

Low actual expansion memory byte

High actual expansion memory byte

Date century byte

Information flags (set during power on)

Reserved for system BIOS

34-7F

Table 2-3 Real-Time Clock & Non-Volatile RAM

2.3.3 Timer

The AR-B1474 provides three programmable timers, each with a timing frequency of 1.19 MHz.

Timer 0

Timer 1

Timer 2

The output of this timer is tied to interrupt request 0. (IRQ 0)

This timer is used to trigger memory refresh cycles.

This timer provides the speaker tone.

Application programs can load different counts into this timer to generate various sound frequencies.

2-4

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AR-B1474 User¡¦s Guide

2.3.4 ISA Bus Pin Assignment

I/O Pin Signal Name Input/Output I/O Pin Signal Name Input/Output

-IOCHCK

SD7

Input

GND

RSTDRV

+5V

Ground

Output

Power

Input

Input/Output

Input

SD6

SD5

IRQ9

SD4

-5V

Power

Input

SD3

DRQ2

-12V

SD2

Power

Input

SD1

-ZWS

+12V

SD0

Power

Ground

Output

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

A26

A27

A28

A29

A30

A31

IOCHRDY

AEN

SA19

SA18

SA17

SA16

SA15

SA14

SA13

SA12

SA11

SA10

SA9

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

B21

B22

B23

B24

B25

B26

B27

B28

B29

B30

B31

GND

Output

-SMEMW

-SMEMR

-IOW

Input/Output

Output

-IOR

-DACK3

DRQ3

-DACK1

DRQ1

Input

Output

Input

-REFRESH Input/Output

BUSCLK

IRQ7

IRQ6

IRQ5

IRQ4

IRQ3

-DACK2

Output

Input

SA8

Input

SA7

Input

SA6

Input

SA5

Output

Power

Output

Ground

SA4

SA3

BALE

+5V

SA2

SA1

OSC

SA0

GND

Table 2-4 ISA Bus Pin Assignment

I/O Pin Signal Name Input/Output I/O Pin Signal Name Input/Output

SBHE

LA23

LA22

LA21

LA20

LA19

LA18

LA17

-MEMR

-MEMW

SD8

Input/Output

-MEMCS16

-IOCS16

IRQ10

Input

IRQ11

Input

IRQ12

Input

IRQ15

Input

IRQ14

Input

-DACK0

DRQ0

Output

Input

C10

C11

C12

C13

C14

C15

C16

C17

C18

D10

D11

D12

D13

D14

D15

D16

D17

D18

-DACK5

DRQ5

Output

Input

SD9

-DACK6

DRQ6

Output

Input

SD10

SD11

SD12

SD13

SD14

SD15

-DACK7

DRQ7

Output

Input

+5V

Power

Input

-MASTER

GND

Ground

Table 2-5 ISA Bus Pin Assignment

2-5

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2.3.5 ISA Bus Signal Description

Name

Description

BUSCLK [Output] The BUSCLK signal of the I/O channel is asynchronous to

the CPU clock.

RSTDRV [Output] This signal goes high during power-up, low line-voltage or

hardware reset

SA0 - SA19

The System Address lines run from bit 0 to 19. They are

The Unlatched Address line run from bit 17 to 23

System Data bit 0 to 15

[Input / Output] latched onto the falling edge of "BALE"

LA17 - LA23

[Input/Output]

SD0 - SD15

[Input/Output]

BALE [Output]

The Buffered Address Latch Enable is used to latch SA0 -

SA19 onto the falling edge. This signal is forced high

during DMA cycles

-IOCHCK [Input]

The I/O Channel Check is an active low signal which

indicates that a parity error exist on the I/O board

This signal lengthens the I/O, or memory read/write cycle,

IOCHRDY

[Input, Open and should be held low with a valid address

collector]

IRQ 3-7, 9-12, 14, 15 The Interrupt Request signal indicates I/O service request

[Input] attention. They are prioritized in the following sequence :

(Highest) IRQ 9, 10, 11, 12, 13, 15, 3, 4, 5, 6, 7 (Lowest)

-IOR

The I/O Read signal is an active low signal which instructs

[Input/Output] the I/O device to drive its data onto the data bus

-IOW [Input/Output] The I/O write signal is an active low signal which instructs

the I/O device to read data from the data bus

-SMEMW [Output] The System Memory Read is low while any of the low 1

mega bytes of memory are being used

-MEMR

The Memory Read signal is low while any memory

[Input/Output] location is being read

-SMEMW [Output] The System Memory Write is low while any of the low 1

mega bytes of memory is being written

-MEMW

The Memory Write signal is low while any memory

[Input/Output] location is being written

DRQ

0-3,

5-7 DMA Request channels 0 to 3 are for 8-bit data transfers.

[Input]

DMA Request channels

are for 16-bit data

transfers. DMA request should be held high until the

corresponding DMA has been completed. DMA request

priority is in the following sequence:(Highest) DRQ 0, 1, 2,

3, 5, 6, 7 (Lowest)

-DACK 0-3, 5-7

The DMA Acknowledges

to 3,

are the

[Output] corresponding acknowledge signals for DRQ 0 to 3 and 5

to 7

AEN [output]

The DMA Address Enable is high when the DMA

controller is driving the address bus. It is low when the

CPU is driving the address bus

-REFRESH

This signal is used to indicate a memory refresh cycle and

[Input/Output] can be driven by the microprocessor on the I/O channel

TC [Output]

Terminal Count provides a pulse when the terminal count

for any DMA channel is reached

SBHE

The System Bus High Enable indicates the high byte SD8

- SD15 on the data bus

[Input/Output]

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Name

Description

-MASTER [Input]

The MASTER is the signal from the I/O processor which

gains control as the master and should be held low for a

maximum of 15 microseconds or system memory may be

lost due to the lack of refresh

-MEMCS16

The Memory Chip Select 16 indicates that the present

[Input,

Open data transfer is

operation

1-wait state, 16-bit data memory

collector]

-IOCS16

[Input,

The I/O Chip Select 16 indicates that the present data

Open transfer is a 1-wait state, 16-bit data I/O operation

collector]

OSC [Output]

ZWS

The Oscillator is a 14.31818 MHz signal

The Zero Wait State indicates to the microprocessor that

Open the present bus cycle can be completed without inserting

additional wait cycle

[Input,

collector]

Table 2-6 ISA Bus Signal Description

2.4 SERIAL PORT

The ACEs (Asynchronous Communication Elements ACE1 to ACE2) are used to convert parallel data to a serial

format on the transmit side and convert serial data to parallel on the receiver side. The serial format, in order of

transmission and reception, is a start bit, followed by five to eight data bits, a parity bit (if programmed) and one,

one and half (five-bit format only) or two stop bits. The ACEs are capable of handling divisors of 1 to 65535, and

produce a 16x clock for driving the internal transmitter logic.

Provisions are also included to use this 16x clock to drive the receiver logic. Also included in the ACE a completed

MODEM control capability, and a processor interrupt system that may be software tailored to the computing time

required handle the communications link.

The following table is summary of each ACE accessible register

DLAB

Port Address

Receiver buffer (read)

base + 0

Transmitter holding register (write)

Interrupt enable

base + 1

base + 2

base + 3

base + 4

base + 5

base + 6

base + 7

base + 0

base + 1

Interrupt identification (read only)

Line control

MODEM control

Line status

MODEM status

Scratched register

Divisor latch (least significant byte)

Divisor latch (most significant byte)

Table 2-7 ACE Accessible Registers

(1) Receiver Buffer Register (RBR)

Bit 0-7: Received data byte (Read Only)

(2) Transmitter Holding Register (THR)

Bit 0-7: Transmitter holding data byte (Write Only)

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(3) Interrupt Enable Register (IER)

Bit 0: Enable Received Data Available Interrupt (ERBFI)

Bit 1: Enable Transmitter Holding Empty Interrupt (ETBEI)

Bit 2: Enable Receiver Line Status Interrupt (ELSI)

Bit 3: Enable MODEM Status Interrupt (EDSSI)

Bit 4: Must be 0

Bit 5: Must be 0

Bit 6: Must be 0

Bit 7: Must be 0

(4) Interrupt Identification Register (IIR)

Bit 0: “ 0” if Interrupt Pending

Bit 1: Interrupt ID Bit 0

Bit 2: Interrupt ID Bit 1

Bit 3: Must be 0

Bit 4: Must be 0

Bit 5: Must be 0

Bit 6: Must be 0

Bit 7: Must be 0

(5) Line Control Register (LCR)

Bit 0: Word Length Select Bit 0 (WLS0)

Bit 1: Word Length Select Bit 1 (WLS1)

WLS1

WLS0

Word Length

5 Bits

6 Bits

7 Bits

8 Bits

Bit 2: Number of Stop Bit (STB)

Bit 3: Parity Enable (PEN)

Bit 4: Even Parity Select (EPS)

Bit 5: Stick Parity

Bit 6: Set Break

Bit 7: Divisor Latch Access Bit (DLAB)

(6) MODEM Control Register (MCR)

Bit 0: Data Terminal Ready (DTR)

Bit 1: Request to Send (RTS)

Bit 2: Out 1 (OUT 1)

Bit 3: Out 2 (OUT 2)

Bit 4: Loop

Bit 5: Must be 0

Bit 6: Must be 0

Bit 7: Must be 0

(7) Line Status Register (LSR)

Bit 0: Data Ready (DR)

Bit 1: Overrun Error (OR)

Bit 2: Parity Error (PE)

Bit 3: Framing Error (FE)

Bit 4: Break Interrupt (BI)

Bit 5: Transmitter Holding Register Empty (THRE)

Bit 6: Transmitter Shift Register Empty (TSRE)

Bit 7: Must be 0

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(8) MODEM Status Register (MSR)

Bit 0: Delta Clear to Send (DCTS)

Bit 1: Delta Data Set Ready (DDSR)

Bit 2: Training Edge Ring Indicator (TERI)

Bit 3: Delta Receive Line Signal Detect (DSLSD)

Bit 4: Clear to Send (CTS)

Bit 5: Data Set Ready (DSR)

Bit 6: Ring Indicator (RI)

Bit 7: Received Line Signal Detect (RSLD)

(9) Divisor Latch (LS, MS)

Bit 0:

Bit 1:

Bit 2:

Bit 3:

Bit 4:

Bit 5:

Bit 6:

Bit 7:

Bit 0

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

Bit 8

Bit 9

Bit 10

Bit 11

Bit 12

Bit 13

Bit 14

Bit 15

Desired Baud Rate

Divisor Used to Generate 16x Clock

300

384

192

600

1200

1800

2400

3600

4800

9600

14400

19200

28800

38400

57600

115200

Table 2-8 Serial Port Divisor Latch

2.5 PARALLEL PORT

(1) Register Address

Port Address

base + 0

Read/Write

Write

Output data

base + 0

Read

Input data

base + 1

Read

Printer status buffer

Printer control latch

base + 2

Write

Table 2-9 Registers’ Address

(2) Printer Interface Logic

The parallel portion of the SMC37C669 makes the attachment of various devices that accept eight bits of parallel

data at standard TTL level.

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(3) Data Swapper

The system microprocessor can read the contents of the printer’ s Data Latch through the Data Swapper by reading

the Data Swapper address.

(4) Printer Status Buffer

The system microprocessor can read the printer status by reading the address of the Printer Status Buffer. The bit

definitions are described as follows:

-ERROR

SLCT

-ACK

-BUSY

Figure 2-2 Printer Status Buffer

NOTE: X presents not used.

Bit 7: This signal may become active during data entry, when the printer is off-line during printing, or when the

print head is changing position or in an error state. When Bit 7 is active, the printer is busy and can not

accept data.

Bit 6: This bit represents the current state of the printer’ s ACK signal. A 0 means the printer has received the

character and is ready to accept another. Normally, this signal will be active for approximately 5

microseconds before receiving a BUSY message stops.

Bit 5: A 1 means the printer has detected the end of the paper.

Bit 4: A 1 means the printer is selected.

Bit 3: A 0 means the printer has encountered an error condition.

(5) Printer Control Latch & Printer Control Swapper

The system microprocessor can read the contents of the printer control latch by reading the address of printer

control swapper. Bit definitions are as follows:

STROBE

AUTO FD XT

INIT

SLDC IN

IRQ ENABLE

DIR(write only)

Figure 2-3 Bit’ s Definition

NOTE: X presents not used.

Bit 5: Direction control bit. When logic 1, the output buffers in the parallel port are disabled allowing data driven

from external sources to be read; when logic 0, they work as a printer port. This bit is write only.

Bit 4: A 1 in this position allows an interrupt to occur when ACK changes from low state to high state.

Bit 3: A 1 in this bit position selects the printer.

Bit 2: A 0 starts the printer (50 microseconds pulse, minimum).

Bit 1: A 1 causes the printer to line-feed after a line is printed.

Bit 0: A 0.5 microsecond minimum highly active pulse clocks data into the printer. Valid data must be present

for a minimum of 0.5 microseconds before and after the strobe pulse.

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3. SETTING UP THE SYSTEM

This section describes pin assignments for system’ s external connectors and the jumpers setting.

Overview

System Setting

3.1 OVERVIEW

The AR-B1474 is a half size industrial grade CPU card that has been designed to withstand continuous operation

in harsh environments. The total on-board memory for the AR-B1474 can be configured from 1MB to 32MB by

using all 72-pin type DRAM devices.

CN1

CN2

CN3

J1 J2

J3 J4

JP15

JP1

LED1

LED2

JP14

JP2

SW1

JP4

JP3

JP5

SIMM1

U13

DB1

U12

JP6

JP7

JP8

U17

U18

JP9

P10

JP10

DB2

U26

U27

U20

CN6

JP11

CN4

H14

H15

C N 6

JP12

JP13

BUS1

BUS2

CN5

H16

H18

H19

Figure 3-1 AR-B1474 Placement

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3.2 SYSTEM SETTING

Jumper pins allow you to set specific system parameters. Set them by changing the pin location of jumper blocks.

(A jumper block is a small plastic-encased conductor that slips over the pins.) To change a jumper setting, remove

the jumper from its current location with your fingers or small needle-nosed pliers. Place the jumper over the two

pins designated for the desired setting. Press the jumper evenly onto the pins. Be careful not to bend the pins.

We will show the locations of the AR-B1474 jumper pins, and the factory-default setting.

CAUTION: Do not touch any electronic component unless you are safely grounded. Wear a grounded wrist strap

or touch an exposed metal part of the system unit chassis. The static discharges from your fingers can

permanently damage electronic components.

3.2.1 Serial Port

(1) RS-485 Adapter Select (JP3 & JP11)

JP3 and JP11 can be set independently. JP3 selects COM-A port and JP11 selects COM-B port.

JP3 -- COM-A

Reserved for Acrosser's

RS-485 adapter used only

RS-232C

(Factory Preset)

Figure 3-2 JP3: RS-485 Adapter Select for COM-A

JP11 -- COM-B

1 2 3

Reserved for Acrosser's

RS-485 adapter used only

1 2 3

RS-232C

(Factory Preset)

Figure 3-3 JP11: RS-485 Adapter Select —COM-B

(2) RS-232 Connector (DB1 & DB2)

There are two serial ports with EIA RS-232C interface on the AR-B1474. COM-A and COM-B use two on-board D-

type 9-pin male connectors (DB1 & DB2). If you want to configure the serial port, please refer to the BIOS

configuration.

DB1 (COM A)

DB2 (COM B)

GND 5

9-RI

-DTR 4

TXD 3

RXD 2

-DCD 1

-DTR 4

TXD 3

RXD 2

-DCD 1

8-CTS

7-RTS

6-DSR

8-CTS

7-RTS

6-DSR

Figure 3-4 DB1 & DB2: RS-232 Connector

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3.2.2 Hard Disk (IDE) Connector (CN1)

A 40-pin header type connector (CN1) is provided to interface with up to two embedded hard disk drives (IDE AT

bus). This interface, through a 40-pin cable, allows the user to connect up to two drives in a “ daisy chain” fashion.

To enable or disable the hard disk controller, please use BIOS Setup program to select. The following table

illustrates the pin assignments of the hard disk drive’ s 40-pin connector.

Figure 3-5 CN1: Hard Disk (IDE) connector

Signal

-RESET

DATA 7

DATA 6

DATA 5

DATA 4

DATA 3

DATA 2

DATA 1

DATA 0

GROUND

Not Used

-IOW

Signal

GROUND

DATA 8

DATA 9

DATA 10

DATA 11

DATA 12

DATA 13

DATA 14

DATA 15

Not used

GROUND

BALE

-IOR

Not Used

IRQ14

SA 1

SA 0

GROUND

-IOCS16

Not used

SA 2

-CS 1

GROUND

-CS 0

HD LED A

Table 3-1 HDD Pin Assignment

3.2.3 Power Connector (J5)

J5 is 8-pin power connector. Using the J5, you can connect the power supply to the on board power connector for

stand alone applications directly.

1 GND

2 +5VDC

3 +5VDC

4 GND

5 GND

6 +12VDC

7 -12VDC

8 -5VDC

Figure 3-6 J5: Power Connector

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3.2.4 FDD Port Connector (CN2)

The AR-B1474 provides a 34-pin header type connector for supporting up to two floppy disk drives.

To enable or disable the floppy disk controller, please use BIOS Setup program to select.

Figure 3-7 CN2: FDD Port connector

Signal

-DIRECTION

1-33(odd)

GROUND

-Reduce Write Current

Not used

-STEP OUTPUT PULSE

-WRITE DATA

Not used

-WRITE ENABLE

-TRACK 0

-INDEX

-MOTOR ENABLE A

-DRIVE SELECT B

-DRIVE SELECT A

-MOTOR ENABLE B

-WRITE PROTECT

-READ DATA

-SIDE 1 SELECT

-DISK CHANGE

Table 3-2 FDD Pin Assignment

3.2.5 Parallel Port Connector (CN3)

To use the parallel port, an adapter cable has been connected to the CN3 (26-pin header type) connector. This

adapter cable is included in your AR-B1474 package. The connector for the parallel port is a 25-pin D-type female

connector.

Parallel Port Connector

D-Type Connector

Figure 3-8 CN3: Parallel Port Connector

CN3 DB-25

Signal

-Strobe

CN3 DB-25

Signal

-Auto Form Feed

-Error

Data 0

Data 1

-Initialize

-Printer Select In

Ground

Data 2

Data 3

Data 4

Ground

Data 5

Ground

Data 6

Ground

Data 7

Ground

-Acknowledge

Busy

Ground

Paper Empty

Printer Select

Ground

No Connect

Table 3-3 Parallel Port Pin Assignments

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3.2.6 PC/104 Connector

(1) 64-Pin PC/104 Connector Bus A & B (CN6)

64-Pin PC/104 Connector

CN6

-IOCHCK --- A1

SD7 --- A2

--- GND

--- RSTDRV

--- +5 VDC

--- IRQ9

SD6 --- A3

SD5 --- A4

SD4 --- A5

--- -5 VDC

--- DRQ2

SD3 --- A6

SD2 --- A7

--- -12 VDC

--- -ZWS

SD1 --- A8

SD0 --- A9

--- +12 VDC

--- KEY

IOCHRDY--- A10

AEN --- A11

SA19 --- A12

SA18 --- A13

SA17 --- A14

SA16 --- A15

SA15 --- A16

SA14 --- A17

SA13 --- A18

SA12 --- A19

SA11 --- A20

SA10 --- A21

SA9 --- A22

SA8 --- A23

SA7 --- A24

SA6 --- A25

SA5 --- A26

SA4 --- A27

SA3 --- A28

SA2 --- A29

SA1 --- A30

SA0 --- A31

GND --- A32

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

B21

--- -SMEMW

--- -SMEMR

--- -IOW

--- -IOR

--- -DACK3

--- DRQ3

--- -DACK1

--- DRQ1

--- -REFRESH

--- BUSCLK

--- IRQ7

B22 --- IRQ6

B23 --- IRQ5

B24 --- IRQ4

B25 --- IRQ3

B26 --- -DACK2

B27 --- TC

B28 --- BALE

B29 --- +5 VDC

B30 --- OSC

B31 --- GND

B32 --- GND

Figure 3-9 CN6: 64-Pin PC/104 Connector Bus A & B

(2) 40-Pin PC/104 Connector Bus C & D (CN4)

40-Pin PC/104 Connector

CN4

GND --- C1

--- GND

SBHE --- C2

LA23 --- C3

LA22 --- C4

LA21 --- C5

LA20 --- C6

LA19 --- C7

LA18 --- C8

LA17 --- C9

-MEMR --- C10

-MEMW --- C11

SD8 --- C12

SD9 --- C13

SD10 --- C14

SD11 --- C15

SD12 --- C16

SD13 --- C17

SD14 --- C18

SD15 --- C19

KEY --- C20

--- -MEMCS16

--- -IOCS16

--- IRQ10

--- IRQ11

--- IRQ12

--- IRQ15

--- IRQ14

--- -DACK0

--- DRQ0

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

D20

--- -DACK5

--- DRQ5

--- -DACK6

--- DRQ6

--- -DACK7

--- DRQ7

--- +5 VDC

--- -MASTER

--- GND

Figure 3-10 CN4: 40-Pin PC/104 Connector Bus C & D

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(3) PC/104 ISA Bus Signal Description

Name

Description

BUSCLK [Output]

The BUSCLK signal of the I/O channel is asynchronous

to the CPU clock.

RSTDRV [Output]

This signal goes high during power-up, low line-voltage or

hardware reset

SA0 - SA19

The System Address lines run from bit 0 to 19. They are

[Input / Output] latched onto the falling edge of "BALE"

LA17 - LA23

[Input/Output]

SD0 - SD15

[Input/Output]

The Unlatched Address line run from bit 17 to 23

System Data bit 0 to 15

BALE [Output]

The Buffered Address Latch Enable is used to latch SA0

– SA19 onto the falling edge. This signal is forced high

during DMA cycles

-IOCHCK [Input]

The I/O Channel Check is an active low signal which

indicates that a parity error exist on the I/O board

This signal lengthens the I/O, or memory read/write cycle,

IOCHRDY

[Input, Open collector] and should be held low with a valid address

IRQ 3-7, 9-12, 14, 15 The Interrupt Request signal indicates I/O service request

[Input] attention. They are prioritized in the following sequence :

(Highest) IRQ 9, 10, 11, 12, 13, 15, 3, 4, 5, 6, 7 (Lowest)

-IOR

The I/O Read signal is an active low signal which

[Input/Output] instructs the I/O device to drive its data onto the data bus

-IOW [Input/Output]

-SMEMR [Output]

-MEMR

The I/O write signal is an active low signal which instructs

the I/O device to read data from the data bus

The System Memory Read is low while any of the low

1mega bytes of memory are being used

The Memory Read signal is low while any memory

[Input/Output] location is being read

-SMEMW [Output]

The System Memory Write is low while any of the low

1mega bytes of memory is being written

-MEMW

The Memory Write signal is low while any memory

[Input/Output] location is being written

DRQ 0-3, 5-7 [Input] DMA Request channels 0 to 3 are for 8-bit data transfers.

DMA Request channels 5 to 7 are for 16-bit data

transfers. DMA request should be held high until the

corresponding DMA has been completed. DMA request

priority is in the following sequence:(Highest) DRQ 0, 1,

2, 3, 5, 6, 7 (Lowest)

-DACK 0-3, 5-7

The DMA Acknowledges

to 3,

are the

[Output] corresponding acknowledge signals for DRQ 0 to 3 and 5

to 7

AEN [output]

The DMA Address Enable is high when the DMA

controller is driving the address bus. It is low when the

CPU is driving the address bus

-REFRESH

This signal is used to indicate a memory refresh cycle

[Input/Output] and can be driven by the microprocessor on the I/O

channel

TC [Output]

Terminal Count provides a pulse when the terminal count

for any DMA channel is reached

SBHE [Input/Output] The System Bus High Enable indicates the high byte SD8

- SD15 on the data bus

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Name

Description

-MASTER [Input]

The MASTER is the signal from the I/O processor which

gains control as the master and should be held low for a

maximum of 15 microseconds or system memory may be

lost due to the lack of refresh

-MEMCS16

The Memory Chip Select 16 indicates that the present

[Input, Open collector] data transfer is a 1-wait state, 16-bit data memory

operation

-IOCS16

The I/O Chip Select 16 indicates that the present data

[Input, Open collector] transfer is a 1-wait state, 16-bit data I/O operation

OSC [Output]

The Oscillator is a 14.31818 MHz signal

-ZWS

The Zero Wait State indicates to the microprocessor that

[Input, Open collector] the present bus cycle can be completed without inserting

additional wait cycle

Table 3-4 PC/104 ISA Bus Pin Assignment

3.2.7 CPU Setting

The AR-B1474 accepts many types of microprocessor, such as INTEL/AMD/CYRIX 486DX/DX2/DX4. All of these

CPUs include an integer processing unit, floating-point processing unit, memory-management unit, and cache.

They can give a two to ten-fold performance improvement in speed over the 386 processor, depending on the

clock speeds used and specific application. Like the 386 processor, the 486 processor includes both segment-

based and page-based memory protection schemes. Instruction processing time is reduced by on-chip instruction

pipelining. By performing fast, on-chip memory management and caching, the 486 processor relaxes requirements

for memory response for a given level of system performance.

(1) AMD DX2-80 CPU Select (JP1)

JP1

1 2 3

AMD DX2-80

Others CPU

Figure 3-11 JP1: AMD DX2-80 CPU Select

(2) CPU Voltage Select (JP2)

JP2

1 2 3

1 3 5

3.3V

1 3 5

Figure 3-12 JP2: CPU Voltage Select

(3) AMD 4X CPU (5x86) Select (JP15)

JP15

AMD CPU

Others CPU

Figure 3-13 JP15: AMD 4X CPU (5x86) Select

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(4) CPU Clock Select (JP6 & JP9)

For different type of CPUs, the clock generator and clock divisor need to be set by JP6 and JP9. The clock base is

selected by JP6, JP9 is used to select single or half clock system. We recommend that you refer the following

table for setting the CPU clock.

JP9

1 2 3

Factory Preset

Figure 3-14 JP9: CPU System Clock Multiplier Select

1-2

3-4

5-6

Definition

A B C

Table 3-5 JP6: CPU Base Clock

JP6

CPU

Base

CPU Type

JP9

Note

Clock

DX-25, DX2-50,

DX4-75

25MHz 50MHz 1X Close Open Open

DX-33, DX2-66,

DX4-100, 5X86-

133

33.3MHz 33.3MHz 1X Close Open Close

Factory

Preset

DX-40, DX2-80,

DX4-120

40MHz 40MHz 1X Close Close Open

50MHZ 50MHz 1X Close Close Close

DX-50

Table 3-6 CPU Clock Setting

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3.2.8 Memory Setting

(1) Cache RAM Size Select (JP8)

The AR-B1474 can be configured to provide a write-back or write-through cache scheme and support 128KB to

512KB cache systems. A write-back cache system may provide better performance than a write-through cache

system. The BIOS Setup program allows you to set the cache scheme either write-back or write-through, either

the internal cache selection.

The AR-B1474 needs four 32Kx8 SRAM chips to construct 128KB cache. To construct 256KB cache, four 64Kx8

SRAM chips are needed. Four 128Kx8 SRAM chips will provide 512KB cache.

JP8

128KB

256KB

512KB

(Factory Preset)

Figure 3-15 JP8: Cache RAM Size Select

(3) DRAM Configuration

There is one 32-bit memory bank on the AR-B1474 card. It can be one-side or double-side SIMM (Single-Line

Memory Modules) which is designed to accommodate 256Kx36 bit to 8Mx36 bit SIMMs. This provides the user

with up to 32MB of main memory. The 32-bit SIMM (without parity bit) also can be used on AR-B1474 card. There

are six on-board memory configurations available. Please refer to the following table for details:

SIMM1

Total Memory

1MB

256KX32(X36)

512KX32(X36)

1MX32(X36)

2MX32(X36)

4MX32(X36)

8MX32(X36)

2MB

4MB

8MB

16MB

32MB

Table 3-7 DRAM Configuration

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3.2.9 LED Header (J1, J2 & J4)

(1) External Power LED & Keyboard Lock Header (J4)

1 Power LED+

2 Not Used

3 Power LED-

4 Key-Lock+

5 Key-Lock-

Figure 3-16 J4: Power LED & Key Lock Header

(2) HDD LED Header (J1)

1 LED+

2 LED-

Figure 3-17 J1: HDD LED Header

(3) Watchdog LED Header (J2)

1 LED+

2 LED-

Figure 3-18 J2: Watchdog LED Header

3.2.10 Keyboard Connector

(1) 6-Pin Mini DIN Keyboard Connector (CN5)

CN5 is a 6-pin Mini-DIN connector. This keyboard connector is PS/2 type keyboard compatible. An PC/AT

compatible keyboard can be used by connecting the provided adapter cable CN5 and keyboard.

1 DATA

2 Not Used

3 GND

4 VCC

5 CLOCK

6 Not Used

CN5 (Front View)

Figure 3-19 CN5: Keyboard Connector

(2) AUX. Keyboard Connector (J8)

A PC/AT compatible keyboard can be used by connected the provided adapter cable between J8 and the

keyboard. The pin assignments of J8 connector are as follows:

1 CLOCK

2 DATA

3 Not Used

4 GND

5 VCC

Figure 3-20 J8: AUX. Keyboard Connector

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3.2.11 External Speaker Header (J3)

Besides the on board buzzer, you can use an external speaker by connecting J3 header directly.

1 Speaker+

2 Speaker-

3 Speaker-

4 Speaker-

Figure 3-21 J3: External Speaker Header

3.2.12 Reset Header (J7)

J7 is used to connect to an external reset switch. Shorting these two pins will reset the system.

1 Reset+

2 Reset-

1 2

Figure 3-22 J7: Reset Header

3.2.13 Battery Setting

(1) Battery Charger Select (JP4)

1 2 3

Rechargeable

Non chargeable

Factory-Default Setting

Figure 3-23 JP4: Battery Charger Select

(2) External Battery Connector (J6)

J6 allows users to connect an external 4.5 to 6 VDC battery to the AR-B1474 if the on-board battery is empty.

Only the SRAM disk will sink the battery current. If no SRAM chip will be used, no battery is needed. The battery

charger on AR-B1474 does not source charge current to the external battery which connects on J6.

1 Battery+

2 Battery-

1 2

Figure 3-24 J6: External Battery Connector

3.2.14 CRT Display Type Select (JP13)

JP13

Color Display

MONO/EGA/VGA Display

Factory-Default Setting

Figure 3-25 JP13: CRT Display Type Select

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4. INSTALLATION

This chapter describes the procedure of the installation. The following topics are covered:

Overview

Utility Diskette

Write Protect Function

Watchdog Timer

4.1 OVERVIEW

This chapter provides information for you to set up a working system based on the AR-B1474 CPU card. Please

read the details of the CPU card’ s hardware descriptions before installation carefully, especially jumpers setting,

switch setting and cable connection.

Follow steps listed below for proper installation:

Step 1 : Read the CPU card’ s hardware description in this manual.

Step 2 : Install any DRAM SIMM onto the CPU card.

Step 3:

Install the EPROMs, FLASHs ro SRAMs on the memory sockets.

Step 4 : Set jumpers and switch.

Step 5 : Make sure that the power supply connected to your passive CPU board is turned off.

Step 6 : Plug the CPU card into a free AT-bus slot or PICMG slot on the backplane and secure it in place with

a screw to the system chassis.

Step 7 : Connect all necessary cables. Make sure that the FDC, HDC, serial and parallel cables are

connected to pin 1 of the related connector.

Step 8 : Connect the hard disk/floppy disk flat cables from the CPU board to the drives. Connect a power

source to each drive.

Step 9 : Install a MDA, CGA, EGA or VGA display card in your system.

Step 10 : Plug the keyboard into the keyboard connector.

Step 11 : Turn on the power.

Step 12: Configure your system with the BIOS Setup program then re-boot your system.

Step 13: If the CPU card does not work, turn off the power and read the hardware description carefully again.

Step 14: If the CPU card still does not perform properly, return the card to your dealer for immediate service.

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4.2 UTILITY DISKETTE

To support the AR-B1474 solid state disk’ s operations, the following programs or files has been provided on the

accompanying utility diskette:

(1) PGM1474.EXE

PGM1474.EXE PGM1474.EXE is used to program the 12V FLASH EPROM after the ROM pattern files are

generated by RFG.EXE The PGM1474.EXE can also program the correctness of the ROM

pattern files onto 5V FLASH EPROM (start from MEM1) or SRAM for testing the ROM pattern

files.

To execute PGM1474.EXE, the main menu will be displayed on your screen. There are 8 options on the main

menu.

Quit to DOS

Quits and exits to the DOS.

OS Shell

Exits from PGM1474 temporarily to the DOS prompt. Type EXIT to return to PGM1474 main menu.

Load ROM File

If this option is used, the PGM1474 will prompt you for the ROM pattern file name. This option is useful if

you have not previously entered a ROM pattern file name or if you wish to use a different ROM pattern file.

The PGM1474 will check and display the ROM file name, ROM file size, (FLASH) memory capacity and the

number of ROM pattern files that will be loaded and copied onto the (FLASH) memory chips.

Verify Memory

If ROM pattern files were loaded without error, this option instructs PGM1474 to verify the contents of

(FLASH) memory chips with the current ROM pattern files.

Program Memory

If there are no mistakes in your ROM pattern file, then this menu option will erase (FLASH) memory, write

the current ROM pattern files onto (FLASH) memory and verify data that was just written to (FLASH)

memory, using the ROM pattern files.

Memory Type/Mfr.

Before you program the (FLASH) memory chips, make sure that the FLASH’ s type and manufactory match

the one shown on the main menu. Otherwise, you can use this option to select the proper type and

manufacture and instruct the program to use a right programming algorithm.

Select PGM Chips

Normally the PGM1474 will program all ROM pattern files onto the FLASH memories with the ROM pattern

files just loaded. But you can use this option to select which memory chips that you want to program and

which memory chips need to be skipped. The PGM1474 will only program the selected chips when writing

data to the FLASH memory. This is very useful when some of the memory chip were verified and

programmed previously.

Select FLASH PLSCNTs

If the 12V FLASHs have been programmed several times, please select the <Slowest> FLASH PLSCNT

mode instead of <Standard> mode. In the <Slower> or <Slowest> mode, PGM1474.EXE will retry more

times to program data onto the 12V FLASHs correctly.

The default setting is <Slowest> mode.

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(2) WD1474.EXE

WD1474.EXE

This program demonstrates how to enable and trigger the watchdog timer. It allows you to

test the <TIMES-OUT & RESET> function when the watchdog timer is enabled.

(3) WP1474.EXE

WP1474.EXE

This program demonstrates how to enable and disable software write protected function. It

also shows the current protect mode of write or read only memory.

(4) BU1474.EXE

BU1474.EXE

BU1474.EXE is used to update the SSD BIOS conveniently if the SSD BIOS need to be

revised. This program will erase the BIOS ROM and reprogram with revised BIOS.

(5) RFG.EXE

RFG.EXE

This program is used to generate ROM pattern files in a binary format. Each ROM pattern file

has the same size as the FLASH or EPROM and can be easily programmed on to the FLASH

with on-board programmer or on to EPROM with any EPROM programmer. If you have

specified a DOS drive in the *.PGF file, RFG will generate bootable ROM pattern files for the

EPROM or FLASH disk. The RFG supports the following DOS: MS-DOS, PC-DOS, DR-DOS,

and X-DOS.

NOTE: If you want to use AR-B1474 with any DOS which is not supported by RFG, please send your requirement

to Acrosser Technology Co., Ltd. or contract with your local sales representative.

The RFG.EXE provided in the utility diskette is a program that converts the files you list in the PGF and convert

them into ROM pattern file. The RFG will determine how many EPROMs are needed and generate the same

number of ROM pattern files. These ROM pattern files are named with the name assigned by the ROM_NAME in

the PGF and the extension names are *.R01, *.R02 ….etc. To generate ROM pattern files.

The ROM File Generator main menu will be displayed on the screen. There are 7 options on the main menu. They

serve the following functions:

Quit to DOS

Quits and exits to the DOS

OS Shell

Exits from the RFG temporarily to the DOS prompt. Type <EXIT> to return to the RFG main menu.

Load PFG File

If this option is used, the RFG will prompt you for the PGF file name. This option is useful if you have not

previously entered a PGF name or you wish to use a different PGF file. The RFG will check and display the

PGF filename, ROM pattern file name, EPROM capacity, DOS version and the number of ROM pattern files

that will be generated.

Type Current PGF File

This option instructs the RFG to use the DOS type command to display the contents of the current PGF file.

Generate ROM File(s)

If there is no mistake in your *.PGF file, then this menu option will generate ROM pattern files. The number

of ROM pattern file generated by the RFG will depend on the total capacity needed by your files. For

instance, if 3 files are generated, then you will need to use 3 EPROMs (The size depends upon the number

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stated in your PGF). The ROM pattern files will have the same file names, but will have different extension

names. For example:

TEST.R01, TEST.R02, TEST.R03 …etc.

Display Error in PGF File

This option displays errors that were detected in your PGF.

Help to PGF File

This option gives information on how to write a PGF file and how to generate ROM pattern files. An

example PGF is also included.

Move the reverse video bar to <Generate ROM File(s)> then press [ENTER]. The ROM pattern file is a

binary file. The file size will be the same size as the EPROM that you assigned in the PGF. For example, if

you are using 128KX8 EPROM memory chips, then the size of ROM patterns file will be 131072 bytes. For

other chips the file size will be:

64KX8 EPROM----65536 bytes

256KX8 EPROM —262144 bytes

512KX8 EPROM---524288 bytes

1MX8 EPROM -----1048576 bytes

(6) RFGDEMO.PGF

RFGDEMO.PGF This file provides a sample PROGRAM GROUP FILE which illustrates how to create ROM

pattern files correctly.

The PGF is an ASCII text file that can be created by using any text editor, word processor or DOS <COPY CON>

command. The PGF lists what files will be copied and if DOS is going to be copied. This file can have any DOS

filename, but the extension name must be *.PGF. For example, followings are valid filenames.

RFGDEMO.PGF

MYRFG.PGF

MSDOS.PGF

….

An examples of the *.PGF file is as follow.

ROM_NAME=TEST1

DOS_DRIVE=C:

; ROM pattern file name is TEST1

;The output file names will be TEST1.R01, TEST1.R02..etc.

; DOS system drive unit is drive C:

;If user does not want to copy DOS

;system files onto the ROM disk

;write as DOS_DRIVE=NONE

ROM_SIZE=128

;128 means 128KX8 (27C/29F010) EPROM size used

;256 means 512KX8 (27C/29F020) EPROM size used

;512 means 512KX8 (27C/29F040) EPROM size used

;1024 means 1MX8 (27C080) EPROM size used

The following two files are options which depend on whether the ROM disk is to be bootable or not.

CONFIG.SYS

AUTOEXEC.BAT

;Below are user’ s files

A:\USER1.COM ; File USER1.COM on root of drive A:

USER2.EXE

; File USER2.EXE on current directory & drive

C:\TTT\USER3.TXT ; File USER3.TXT on sub-directory TTT of drive C:

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4.3 WRITE PROTECT FUNCTION

The AR-B1474 provides hardware and software write protect functions for small page 5V FLASH disk and only

software write protected function for SRAM disk. This is to prevent your data on 5V FLASH or SRAM disk from

accidental deletion or overwrite. If your FLASH/SRAM disk is write protected, any write operation to the protected

FLASH/SRAM disk will get a write protect error:

Write protect error writing drive A

About, Retry, Fail?

4.3.1 Hardware Write Protect

To enable the hardware protect function for small page 5V FLASH disk, please set the SW1-5 to “ ON” and the

SW1-6 to “ OFF” , please refer to the “ Switch Setting” .

4.3.2 Software Write Protect

If you need the write protect function and sometimes you have to write or update data on your FLASH/SRAM disk,

you can use the software write protect instead of hardware write protect. The software write protect function is

enabled or disabled by writing a data to an I/O port.

4.3.3 Enable the Software Write Protect

Writes data 08h to the base port+2 address

Example 1: (in assembly language)

MOV DX, 212H

MOV AL, 08H

OUT DX, AL

; If the AR-B1474’ s base I/O address is 210H

; Enable byte = 08h

Example 2: (in BASICA language)

OUT &H212, &H08; REM If the AR-B1474’ s base I/O address is 210h

Example 3: (in Turbo C language)

outportb(0x212,0x08);/*If the AR-B1474’ s base I/O address is 210h*/

4.3.4 Disable the Software Write Protect

Writes data 0 to the base port+2 address

Example 1: (in assembly language)

MOV DX, 212H

MOV AL, 00H

OUT DX, AL

; If the AR-B1474’ s base I/O address is 210h

; Disable byte=00h

Example 2: (in BASICA language)

OUT &H212, &H00

; REM If the AR-B1474’ s base I/O address is 210h

Example 3: (in Turbo C language)

outportb(0x212,0x00); /*If the AR-B1474’ s base I/O address is 210h*/

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4.4 WATCHDOG TIMER

This section describes how to use the Watchdog Timer, disabled, enabled, and trigger.

The AR-B1474 is equipped with a programmable time-out period watchdog timer. This watchdog timer can be

enabled by your program. Once you have enabled the watchdog timer, the program should trigger it every time

before it times out. If your program fails to trigger or disable this timer before it times out because of system hang-

up, it will generate a reset signal to reset the system or generate the IRQ15 signal to tell your program that the

watchdog is times out. The time-out period can be programmed to be 6 to 42 seconds.

Enable (D6, D7)

Time Base

Time Factor (D0-D2)

Watchdog

Counter

and

Compartor

Write and Trigger

Watchdog

LED

RESET

IRQ15

Figure 4-1 Watchdog Block Diagram

4.4.1 Watchdog Timer Setting

The watchdog timer is a circuit that may be used from your program software to detect crashes or hang-ups.

Whenever the watchdog timer is enabled, the LED will blink to indicate that the timer is counting. The watchdog

timer is automatically disabled after reset.

Once you have enabled the watchdog timer, your program must trigger the watchdog timer every time before it

times-out. After you trigger the watchdog timer, it will be set to zero and start to count again. If your program fails

to trigger the watchdog timer before time-out, it will generate a reset pulse to reset the system or trigger the IRQ15

signal to tell your program that the watchdog is times out.

The factor of the watchdog timer time-out constant is approximately 6 seconds. The period for the watchdog timer

time-out period is between 1 to 7 timer factors.

If you want to reset your system when watchdog times out, the following table listed the relation of timer factors

between time-out period.

Time Factor

Time-Out Period (Seconds)

80H

81H

82H

83H

84H

85H

86H

87H

Table 4-1 Time-Out Setting

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If you want to generate IRQ15 signal to warn your program when watchdog times out, the following table listed the

relation of timer factors between time-out period.

Time Factor

0C0H

Time-Out Period (Seconds)

0C1H

0C2H

0C3H

0C4H

0C5H

0C6H

0C7H

Table 4-2 Time-Out Setting

NOTE: 1. If you program the watchdog to generate IRQ15 signal when it times out, you should initial IRQ15

interrupt vector and enable the second interrupt controller (8259 PIC) in order to enable CPU to process

this interrupt. An interrupt service routine is required too.

2. Before you initial the interrupt vector of IRQ15 and enable the PIC, please enable the watchdog timer

previously, otherwise the watchdog timer will generate an interrupt at the time watchdog timer is

enabled.

4.4.2 Watchdog Timer Enabled

To enable the watchdog timer, you have to output a byte of timer factor to the watchdog register whose address is

Base Port+4. The following is a BASICA program which demonstrates how to enable the watchdog timer and set

the time-out period at 24 seconds.

1000

1010

1020

1030

1040

1050

REM Points to command register

WD_REG% = BASE_PORT% + 4

REM Timer factor = 84H (or 0C4H)

TIMER_FACTOR% = %H84

REM Output factor to watchdog register

OUT WD_REG%, TIMER_FACTOR%

.,etc.

4.4.3 Watchdog Timer Trigger

After you enable the watchdog timer, your program must write the same factor as enabling to the watchdog register

at least once every time-out period to its previous setting. You can change the time-out period by writing another

timer factor to the watchdog register at any time, and you must trigger the watchdog before the new time-out period

in next trigger. Below is a BASICA program which demonstrates how to trigger the watchdog timer:

2000

2010

2020

2030

2040

2050

REM Points to command register

WD_REG% = BASE_PORT% + 4

REM Timer factor = 84H (or 0C4H)

TIMER_FACTOR% = &H84

REM Output factor to watchdog register

OUT WD_REG%, TIMER_FACTOR%

.,etc.

4.4.4 Watchdog Timer Disabled

To disable the watchdog timer, simply write a 00H to the watchdog register.

3000

3010

3020

3030

3040

3050

REM Points to command register

WD_REG% = BASE_PORT% + 4

REM Timer factor = 0

TIMER_FACTOR% = 0

REM Output factor to watchdog register

OUT WD_REG%, TIMER_FACTOR%

., etc.

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5.SOLID STATE DISK

The section describes the various type SSDs’ installation steps as follows. This chapter describes the procedure of

the installation. The following topics are covered:

Overview

Switch Setting

Jumper Setting

ROM Disk Installation

5.1 OVERVIEW

The AR-B1474 provides three 32-pin JEDEC DIP sockets which may be populated with up to 3MB of EPROM or

1.5MB of FLASH or 1.5MB of SRAM disk. It is ideal for diskless system, high reliability and/or high-speed access

applications, controller for industrial or line test instruments, etc.

FLASH disk function allows you to directly program the ROM disk without having to purchase any additional

programming equipment. If small page (less or equal 512 bytes per page) 5V FLASHs were used, you could

format FLASH disk and copy files onto FLASH disk just like using a normal floppy disk. You could use all of the

related DOS command (such as COPY, DEL, …etc.) to update files on the 5V FLASH disk.

The write protect function allows you to prevent your data on small page 5V FLASH or SRAM disk from accidental

deletion or overwrite.

Data retention of SRAM is ensured by an on-board Lithium battery or an external battery pack that could be

connected to the AR-B1474.

5.2 SWITCH SETTING

We will show the locations of the AR-B1474 switch, and the factory-default setting.

CAUTION: The switch setting needs to adjust with the jumpers setting, make sure the jumper settings and the

switch setting are correct.

CN1

CN2

CN3

J1 J2

J3 J4

JP15

JP1

LED1

LED2

JP14

JP2

SW1

JP3

JP4

JP5

SIMM1

U13

DB1

U12

JP6

JP7

JP8

U17

U18

P10

JP9

JP10

DB2

U26

U27

U20

CN6

JP11

CN4

H14

H15

C N 6

JP12

JP13

BUS1

BUS2

CN5

H16

H18

H19

Figure 5-1 Switch & SSD Type Jumper Location

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5.2.1 Overview

There is 1 DIP Switch located on the AR-B1474. It performs the following functions:

OFF

Figure 5-2 SW1: Switch Select

SW1-1 & SW1-2 Set the base I/O port address

SW1-3 & SW1-4 Set the starting memory address

SW1-5 & SW1-6 Set the drive number of solid state

disk

SW1-7 & SW1-8 Set the used ROM memory chips

5.2.2 I/O Port Address Select (SW1-1 & SW1-2)

SW1-1 & SW1-2 are provided to select one of the four base port addresses for the watchdog timer and the solid

state disk. The AR-B1474 occupies 6 I/O port addresses. Followings state selections of base port address.

SW1-1

OFF (*)

SW1-2

OFF

Base Port Solid State Disk Watchdog

210h

290h

310h

390h

210h-213h

290h-293h

310h-313h

390h-393h

214h-215h

294h-295h

314h-315h

394h-395h

OFF

Table 5-1 I/O Port Address Select

5.2.3 SSD Firmware Address Select (SW1-3 & SW1-4)

The AR-B1474‘ s SSD firmware occupies 16KB of memory. SW1-3 & SW1-4 are used to select the memory base

address. You must select an appropriate address so that the AR-B1474 will not conflict with memory installed on

other add-on memory cards. Additionally, be sure not to use shadow RAM area or EMM driver’ s page frame in this

area.

SW1-3

OFF (*)

SW1-4 SSD BIOS Address Bank Memory Address

OFF

C800:0 (8KB)

CC00:0 (8KB)

D000:0 (8KB)

DC00:0 (8KB)

CA00:0 (8KB)

CE00:0 (8KB)

D200:0 (8KB)

DE00:0 (8KB)

OFF

Table 5-2 SSD Firmware Address Select

If you are not going to use the solid state disk (SSD), you could use JP7 to disable the SSD BIOS. The AR-B1474

will not occupy any memory address if the SSD BIOS is disabled.

If you are going to install the EMM386.EXE driver, please use the [X] option to prevent EMM386.EXE from using

the particular range of segment address as an EMS page which is used by AR-B1474. For example, write a

statement in the CONFIG.SYS file as follow: (If the memory configuration of AR-B1474 is C800:0)

DEVICE=C:\DOS\EMM386.EXE X=C800-CFFF

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5.2.4 SSD Drive Number (SW1-5 & SW1-6)

The AR-B1474 SSD can simulate one or two disk drives. You can assign the drive letter of the AR-B1474 by

configuring SW1-5 & SW1-6.

You can make the computer to boot from SSD by copying DOS into the SSD. If your SSD does not have DOS, the

computer will boot from your hard disk or floppy disk. In this condition, the SSD BIOS of AR-B1474 will set the

drive letter of the SSD to the desired drive letter automatically.

The AR-B1474 would simulate a single disk drive when only (FLASH) EPROM or SRAM (starting from MEM1

socket) is installed. The drive numbers with respect to the switch setting when the AR-B1474 simulates single disk

drives.

SW1-5

OFF (*)

SW1-6

OFF

Occupies floppy disk number (SSD)

0 or 1 (Note 1)

0 or 2 (Note 2)

OFF

Table 5-3 SSD Drive Number

NOTE: 1. If there is no DOS on this SSD, the disk number will 1 (B:). If any DOS is found by the AR-B1474 SSD

BIOS, the disk number will be 0 (A:) But, you can change the disk number from 0 to 1 by pressing the

<ESC> key during system bootup.

2. If there is no DOS on this SSD, the disk number will be 2 (C: or D: or …). If any DOS is found by the AR-

B1474 SSD BIOS, the disk number will be 0 (A:). But, you can change the disk number from 0 to 2 by

pressing the <ESC> key during system bootup.

(1) Simulate 2 Disk Drive

When (FLASH) EPROM and SRAM are both used on the AR-B1474, or you only have installed SRAM that does

not start from MEM1 socket, the AR-B1474 will simulate two disk drives. The drive numbers respect to those

switch settings when AR-B1474 simulates two disk drives.

Occupies floppy disk number

SW1-5

SW1-6

FLASH (EPROM)

SRAM

OFF

0 or 1 (Note 1)

0 or 2 (Note 2)

OFF

Table 5-4 SSD Drive Number for Simulate 2 Disk Drive

NOTE: 1. If there is no DOS on this SSD, the disk number will be 1 (B:). If any DOS is found by the AR-B1474

SSD BIOS, the disk letter will be 0 (A:). But, you can change the disk number from 0 to 1 by pressing

the <ESC> key during system bootup.

2. If there is no DOS on this SSD, the disk number will be 2 (C: or D: or ….). If any DOS is found by the

AR-B1474 SSD BIOS, the disk number will be 0 (A:). But, you can change the disk number from 0 to 2

by pressing the <ESC> key during system bootup.

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(2) Disk Drive Name Arrangement

If any logical hard disk drives exist in your system, there will also be a different disk number depending on which

version DOS you are using.

The solid state disk drive number with there respective DOS drive designation are listed in table as follows. The

solid state disk drive number is changeable as the DOS version. The following table expresses the variety.

Floppy disk No. Logical hard disk

Condition

No Logical hard disk

1 Logical hard disk

2 Logical hard disk

3 Logical hard disk

4 Logical hard disk

A: B: C: D: --

A: B: C: D: E: --

A: B: C: D: E: F:

A: B: C: D: E: F: G: --

A: B: C: D: E: F: G: H:

Table 5-5 SSD Drive Number for DOS Version before 5.0

Floppy disk No. Logical hard disk

Condition

No Logical hard disk

1 Logical hard disk

2 Logical hard disk

3 Logical hard disk

4 Logical hard disk

A: B: C: D: --

A: B: D: E: C: --

A: B: E: F: C: D: --

A: B: F: G: C: D: E:

A: B: G: H: C: D: E: F:

Table 5-6 SSD Drive Number for DOS Version 5.0 and Newer

5.2.5 ROM Type Select (SW1-7 & SW1-8)

SW1-7 & SW1-8 are used to select the memory type of ROM disk section.

SW1-7

OFF

SW1-8

OFF

EPROM Type

UV EPROM (27Cxxx)

5V FLASH 29Fxxx (*Note)

5V FLASH (29Cxxx & 28EExxx)

12V FLASH (28Fxxx)

OFF

Table 5-7 ROM Type Select

NOTE: It is also used to perform the hardware write protection of small page 5V FLASH (29Cxxx or 28EExxx) disk.

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5.3 JUMPER SETTING

Before installing the memory into memory sockets MEM1 through MEM3, you have to configure the memory type

which will be used (ROM/RAM) on the AR-B1474. Each socket is equipped with a jumper to select the memory

type.

You can configure the AR-B1474 as a (FLASH) EPROM disk (ROM only), a SRAM disk (SRAM only) or a

combination of (FLASH) EPROM and SRAM disk.

It is not necessary to insert memory chips into all of the sockets. The number of SRAM chips required depends on

your RAM disk capacity. The number of EPROM chips required depends on the total size of files that you plan to

copy onto the ROM disk and whether or not it will be bootable.

Insert the first memory chip into MEM1 if you are going to configure it as a ROM or SRAM disk. If you use a

combination of ROM and RAM, then insert the (FLASH) EPROM chip starting with the MEM1, and insert the

SRAM chips starting from the first socket which is configured as SRAM.

M1:is used to configure the memory type of MEM1

M2:is used to configure the memory type of MEM2

M3:is used to configure the memory type of MEM3

CAUTION: When the power is turned off, please note the following precautions.

1. If your data has been stored in the SRAM disk, do not change the jumper position or data will be

lost.

2. Make sure jumpers are set properly. If you mistakenly set the jumpers for SRAM and you have

EPROM or FLASH installed, the EPROM or FLASH will drain the battery’ s power.

5.3.1 SSD BIOS Select (JP7)

JP7

Disable

(Factory preset)

Enable

Figure 5-3 JP7: SSD BIOS Select

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5.3.2 SSD Memory Type Setting (M1 ~ M3 & JP5)

JP5

1 2 3

1MX8 EPROM

(Only)

M1, M2 & M3

JP5

1 2 3

EPROM (128KX8, 256KX8 and 512KX8)

5V FLASH (64KX8, 128KX8 and 256KX8)

(Factory Preset)

M1, M2 & M3

JP5

1 2 3

5V FLASH (512KX8 Only)

M1, M2 & M3

JP5

1 2 3

SRAM

M1, M2 & M3

Figure 5-4 M1~M3 & JP5: Memory Type Setting

5.4 ROM DISK INSTALLATION

The section describes the various type SSDs’ installation steps as follows. The jumper and switch adjust as SSD’ s

different type to set.

5.4.1 UV EPROM (27Cxxx)

(2) Switch and Jumper Setting

Step 1: Use jumper block to set the memory type as ROM (FLASH).

Step 2: Select the proper I/O base port, firmware address, disk drive number and EPROM type on SW1.

Step 3: Insert programmed EPROM(s) or FLASH(s) chips into sockets starting at MEM1.

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OFF

Figure 5-5 UV EPROM (27CXXX) Switch Setting

JP5

1MX8 EPROM (Only)

M1, M2 & M3

JP5

M1, M2 & M3

EPROM (128KX8, 256KX8 and 512KX8)

Figure 5-6 UV EPROM Jumper Setting

(2) Software Programming

Use the UV EPROM, please refer to the follow steps:

Step 1: Turn on the power and boot DOS from hard disk drive or floppy disk drive.

Step 2: Making a Program Group File (*.PGF file)

Step 3: Using the RFG.EXE to generate ROM pattern files, and counting the ROM numbers as the pattern

files.

Step 4: In the DOS prompt type the command as follows.

C:\>RFG [file name of PGF]

Step 5: In the RFG.EXE main menu, choose the <Load PGF File> item, that is user editing *.PGF file.

Step 6: Choose the <Generate ROM File(s)>, the tools program will generate the ROM files, for programming

the EPROMs.

Step 7: Program the EPROMs

Using the instruments of the EPROM writer to load and write the ROM pattern files into the EPROM

chips. Make sure that the EPROMs are verified by the program without any error.

Step 8: Install EPROM chips

Be sure to place the programmed EPROMs (R01, R02 ….) into socket starting from MEM1 and ensure

that the chips are installed in the sockets in the proper orientation.

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5.4.2 Large Page 5V FLASH Disk

If you are using large page 5V FLASH as ROM disk, it is the same procedure as step 1 to step 4 of using the UV

EPROM.

(2) Switch and Jumper Setting

Step 1: Use jumper block to set the memory type as ROM (FLASH).

Step 2: Select the proper I/O base port, firmware address, disk drive number and large page 5V FLASH type

on SW1.

Step 3: Insert programmed EPROM(s) or FLASH(s) chips into sockets starting at MEM1.

OFF

Figure 5-7 5V Large FLASH (29FXXX) Switch Setting

JP5

M1, M2 & M3

5V FLASH (64KX8, 128KX8 and 256KX8)

(Factory Preset)

JP5

5V FLASH (512KX8 Only)

M1, M2 & M3

Figure 5-8 Large Page 5V FLASH Jumper Setting

(2) Software Programming

And then, you should create a PGF and generate ROM pattern files by using the RFG.EXE.

Step 1: Making a Program Group File (*.PGF file)

Step 2: Generate ROM pattern files

Step 3: Turn off your system, and then install FLASH EPROMs into the sockets.

NOTE: Place the appropriate number of FLASH EPROM chips (the numbers depends on the ROM

pattern files generated by RFG.EXE) into the socket starting from MEM1 and ensure that the

chips are installed in the sockets in the proper orientation. Line up and insert the AR-B1474

board into any free slot of your computer.

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Step 4: Turn on your system, and Program FLASH EPROMs.

NOTE: The FLASH EPROM program is built-in the AR-B1474 board. The FLASH EPROMs can be

programmed on the AR-B1474. Before programming the FLASH EPROMs, please insert at

least the same number of FLASH EPROMs, please insert at least the same number of FLASH

EPROMs, please insert at least the same number of FLASH chips as the ROM pattern files

generated.

Step 5: The PGM1474.EXE file is a program that loads and writes the ROM pattern files onto the (FLASH)

memory chips. To program the FLASH EPROM.

Step 6: In the DOS prompt type the command as follows.

C:\>PGM1474 [ROM pattern file name]

Step 7: In the main menu, choose the <Load ROM File> item, that is the ROM_NAME=[file name] in the *.PGF

file.

Step 8: Choose the <Program Memory> item, this item program will program the EPROMs.

NOTE: Move the reverse video bar to the <Program memory> option then press <ENTER>. PGM1474 will

write the ROM pattern files onto the (FLASH) memories. Ensure that data is verified by the

PGM1474 correctly.

Step 9: Reboot the system

NOTE: Reboot your computer by making a software or hardware reset.

5.4.3 Small Page 5V FLASH ROM Disk

(1) Switch and Jumper Setting

Step 1: Use jumper block to set the memory type as ROM (FLASH).

Step 2: Select the proper I/O base port, firmware address, disk drive number and EPROM type on SW1.

Step 3: Insert programmed EPROM(s) or FLASH(s) chips into sockets starting at MEM1.

OFF

Figure 5-9 5V FLASH (29CXXX & 28EEXXX) Switch Setting

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JP5

(Factory Preset)

M1, M2 & M3

5V/12V FLASH (64KX8, 128KX8 and 256KX8)

JP5

5V FLASH (512KX8 Only)

M1, M2 & M3

Figure 5-10 5V FLASH (29CXXX & 28EEXXX) Jumper Setting

(2) Using Tool Program

If small page 5V FLASH EPROMs are used, you can use the same method as step 1 to step 4 of using the UV

EPROM:

Step 1: Making a Program Group File (*.PGF file)

Step 2: Generating ROM pattern files

Step 3: Installing FLASH EPROMs

Step 4: Programming FLASH EPROMs

Step 5: Reboot system

(3) Typing DOS Command

You can use another way to format and copy files to the 5V FLASH EPROM. This method provides the

convenience of using a RAM disk. You can use the DOS <FORMAT> and <COPY> command to format and copy

files. Follow the following steps to format and copy files to the FLASH disk. it is the same procedure as step 1 to

step 4 of using the UV EPROM.

Step 1: Turn on your computer, when the screen shows the SSD BIOS menu, please hit the [F1] key during the

system boot-up, this enables you to enter the FLASH setup program. If the program does not show up,

check the switch setting of SW1.

Step 2: Use <Page-Up>, <Page-Down>, <Right>, and <Left> arrow keys to select the correct FLASH memory

type and how many memory chips are going to be used.

Step 3: Press the [F4] key to save the current settings.

Step 4: After the DOS is loaded, use the DOS [FORMAT] command to format the FLASH disk.

To format the disk and copy DOS system files to the disk.

C:\>FORMAT [ROM disk letter] /S /U

To format the disk without copying DOS system files.

C:\>FORMAT [ROM disk letter] /U

Step 5: Copy your program or files to the FLASH disk by using DOS [COPY] command.

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CAUTION: It is not recommended that the user formatted the disk and copy files to the FLASH disk very often.

Since the FLASH EPROM’ s write cycle life time is about 10,000 or 100,000 times, writing data to the

FLASH too often will reduce the life time of the FLASH EPROM chips, especially the FLASH EPROM

chip in the MEM1 socket.

5.4.4 RAM Disk

(1) Jumper Setting

Step 1: Use jumper block to set the memory type as ROM (FLASH).

Step 2: Select the proper I/O base port, firmware address, disk drive number on SW1.

Step 3: Insert programmed SRAM chips into sockets starting at MEM1.

NOTE: If you use the SRAM, please skip the SW1-7 & SW1-8 setting.

JP5

SRAM

M1, M2 & M4

Figure 5-11 SRAM Jumper Setting

(2) Software Programming

It is very easy to use the RAM disk. The RAM disk operates just like a normal floppy disk. A newly installed RAM

disk needs to be formatted before files can be copied to it. Use the DOS command [FORMAT] to format the RAM

disk.

Step 1: Use jumper block to select the memory type as SRAM refer.

Step 2: Select the proper I/O base port, firmware address and disk drive number on SW1.

Step 3: Insert SRAM chips into sockets starting from MEM1

Step 4: Turn on power and boot DOS from hard disk drive or floppy disk drive.

Step 5: Use the DOS command [FORMAT] to format the RAM disk. If you are installing SRAM for the first

time.

To format the RAM disk and copy DOS system files onto the RAM disk.

C:\>FORMAT [RAM disk letter] /S /U

To format the RAM disk without copying DOS system files into the RAM disk.

C:\>FORMAT [RAM disk letter] /U

Step 6: Use the DOS command [COPY] to copy files onto the RAM disk. For example, if you want to copy file

<EDIT.EXE> to the RAM disk from drive C: and the RAM disk is assigned as drive A:.

COPY C:EDIT.EXE A:

NOTE: In addition, you can use any other DOS command to operate the RAM disk.

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5.4.5 Combination of ROM and RAM Disk

The AR-B1474 can be configured as a combination of one ROM disk and one RAM disk. Each disk occupies a

drive unit.

Step 1: Use jumper block to select the proper ROM/RAM configuration you are going to use.

Step 2: Insert the first programmed EPROM into the socket mem1, the second into the socket MEM2, etc.

Step 3: Insert the SRAM chips starting from the first socket assigned as SRAM.

Step 4: Select the proper I/O base port, firmware address and disk drive number on SW1.

Step 5: Turn on power and boot DOS from hard disk drive or floppy disk drive.

Step 6: Use the DOS command [FORMAT] to format the RAM disk.

C:\>FORMAT [RAM disk letter] /U

Step 7: If 5V FLASH (small page) is being used for the first time.

And then use the DOS command [FORMAT] to format the FLASH disk.

Step 8: If large page 5V FLASH is being installed for the first time, please use the FLASH programming utility

PGM1474.EXE to program ROM pattern files, which have been generated by RFG.EXE onto the

FLASH chips.

NOTE: Users can only boot DOS from the ROM disk drive if the AR-B1474 is configured as a ROM and a RAM

disk. You don’ t need to copy DOS onto the RAM disk.

5.5 INSTALLATION D.O.C.

5.5.1 Hardware Setting

(1) SSD BIOS Setting (JP7)

JP7 -- SSD BIOS

Disable

Enable

Figure 5-12 JP7: SSD BIOS Setting

(2) D.O.C. Socket Select (M1)

DiskOnChip only use MEM1 socket, so user must set the M1 for adjusting the DiskOnChip’ s type.

Figure 5-13 M1: D.O.C. Socket Select

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(3) D.O.C. Setting (SW1-8)

OFF

Figure 5-14 SW1-8: D.O.C. Setting

Note: There is 1 DIP switch located on the AR-B1474. It performs the followings:

SW1-1 & SW1-2 Set the base I/O port address

SW1-3 & SW1-4 Set the starting memory address

SW1-5, SW1-6 & The function now is unavailable

SW1-7

SW1-8

Set the DiskOnChip only

5.5.2 Software Setting

We will attach the BU1474.EXE and 1474DOC.INI these two files, BU1474.EXE is the utility program, and the

1474DOC.INI is for D.O.C. BIOS. When user execute the two files for updating will show the message on the

screen as follows:

DOC Socket Service – Version 0.2

TrueFFS – BIOS – Version 3.3.5 for DiskOnChip 2000 (V1.05)

Note: If you want to use the D.O.C., and please contact technical engineer for the utility programs.

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6. BIOS CONSOLE

This chapter describes the AR-B1474 BIOS menu displays and explains how to perform common tasks needed to

get up and running, and presents detailed explanations of the elements found in each of the BIOS menus. The

following topics are covered:

BIOS Setup Overview

Standard CMOS Setup

Advanced CMOS Setup

Advanced Chipset Setup

Power Management

Auto-Detect Hard Disks

Password Setting

Load Default Setting

BIOS Exit

BIOS Update

6.1 BIOS SETUP OVERVIEW

BIOS is a program used to initialize and set up the I/O system of the computer, which includes the ISA bus and

connected devices such as the video display, diskette drive, and the keyboard.

The BIOS provides a menu-based interface to the console subsystem. The console subsystem contains special

software, called firmware that interacts directly with the hardware components and facilitates interaction between

the system hardware and the operating system.

The BIOS Default Values ensure that the system will function at its normal capability. In the worst situation the

user may have corrupted the original settings set by the manufacturer.

After the computer turned on, the BIOS will perform a diagnostics of the system and display the size of the

memory that is being tested. Press the [Del] key to enter the BIOS Setup program, and then the main menu will

show on the screen.

The BIOS Setup main menu includes some options. Use the [Up/Down] arrow key to highlight the option that you

wish to modify, and then press the [Enter] key to assure the option and configure the functions.

CAUTION: 1. AR-B1474 BIOS the factory-default setting is used to the <Auto Configuration with Optimal Settings>

Acrosser recommends using the BIOS default setting, unless you are very familiar with the setting

function, or you can contact the technical support engineer.

2. If the BIOS loss setting, the CMOS will detect the <Auto Configuration with Fail Safe Settings> to

boot the operation system, this option will reduce the performance of the system. Acrosser

recommends choosing the <Auto Configuration with Optimal Setting> in the main menu. The option

is best-case values that should optimize system performance.

3. The BIOS settings are described in detail in this section.

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6.2 STANDARD CMOS SETUP

The <Standard CMOS Setup> option allows you to record some basic system hardware configuration and set the

system clock and error handling. If the CPU board is already installed in a working system, you will not need to

select this option anymore.

Date & Time Setup

Highlight the <Date> field and then press the [Page Up] /[Page Down] or [+]/[-] keys to set the current date. Follow

the month, day and year format.

Highlight the <Time> field and then press the [Page Up] /[Page Down] or [+]/[-] keys to set the current date. Follow

the hour, minute and second format.

The user can bypass the date and time prompts by creating an AUTOEXEC.BAT file. For information on how to

create this file, please refer to the MS-DOS manual.

Floppy Setup

The <Standard CMOS Setup> option records the types of floppy disk drives installed in the system.

To enter the configuration value for a particular drive, highlight its corresponding field and then select the drive type

using the left-or right-arrow key.

Hard Disk Setup

The BIOS supports various types for user settings, The BIOS supports <Pri Master>, <Pri Slave>, <Sec Master>

and <Sec Slave> so the user can install up to two hard disks. For the master and slave jumpers, please refer to

the hard disk’ s installation descriptions and the hard disk jumper settings.

You can select <AUTO> under the <TYPE> and <MODE> fields. This will enable auto detection of your IDE drives

during bootup. This will allow you to change your hard drives (with the power off) and then power on without

having to reconfigure your hard drive type. If you use older hard disk drives which do not support this feature, then

you must configure the hard disk drive in the standard method as described above by the <USER> option.

Virus Protection

This option protects the boot sector and partition table of your hard disk against accidental modifications. Any

attempt to write to them will cause the system to halt and display a warning message. If this occurs, you can either

allow the operation to continue or use a bootable virus-free floppy disk to reboot and investigate your system. The

default setting is <Disabled>. This setting is recommended because it conflicts with new operating systems.

Installation of new operating system requires that you disable this to prevent write errors.

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6.3 ADVANCED CMOS SETUP

The <Advanced CMOS SETUP> option consists of configuration entries that allow you to improve your system

performance, or let you set up some system features according to your preference.

System BootUp Sequence

The option determines where the system looks first for an operating system.

System BootUp Num-Lock

This item is used to activate the Num Lock function upon system boot. If the setting is on, after a boot, the Num

Lock light is lit, and user can use the number key.

Floppy Drive Seek At Boot

If the <Floppy Drive Seek> item is setting Enabled, the BIOS will seek the floppy <A> drive one time upon bootup.

System BootUp CPU Speed

The option set the speed of the CPU at system boot time.

Typematic Rate (Chars/Sec)

Typematic Rate sets the rate at which characters on the screen repeat when a key is pressed and held down.

Above 1MB Memory Test

When this option is enabled, the BIOS memory test will be performed on all system memory. When this option is

disabled, the memory test will be done only for the first 1MB of system memory.

Memory Test Tick Sound

The option enables or disabled the ticking sound during the memory test.

Password Checking Option

This option enables password checking every time the computer is powered on or every time the BIOS Setup is

executed. If Always is chosen, a user password prompt appears every time the computer is turned on. If Setup is

chosen, the password prompt appears if the BIOS executed.

Hard Disk Type 47 RAM Area

Specify in this option if the top 1KB of the system programming area beginning at 639K or 0:300 in the system

BIOS area in low memory will be used to store hard disk information.

Wait for ‘ F1’ If Error

BIOS POST error messages are followed by:

Press <F1> to continue

If this option is set to Disabled, the AMIBIOS does not wait for you to press the <F1> key after an error message.

Hit ‘ DEL’ Message Display

Set this option to Disabled to prevent the message as follows:

Hit ‘DEL’ if you want to run setup

It will prevent the message from appearing on the first BIOS screen when the computer boots.

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Internal Cache Memory

This option specifies the caching algorithm used for L1 internal cache memory. The settings are:

Setting

Description

Neither L1 internal cache memory on the CPU or L2

secondary cache memory is enabled.

Use the write-back caching algorithm.

Disabled

WriteBack

WriteThru

Use the write-through caching algorithm.

Table 6-1 Internal Cache Setting

External Cache Memory

This option specifies the caching algorithm used for L2 secondary (external) cache memory. The settings are:

Setting

Description

Disabled

Neither L1 internal cache memory on the CPU or L2

secondary cache memory is enabled.

WriteBack Use the write-back caching algorithm.

WriteThru Use the write-through caching algorithm.

Table 6-2 External Cache Setting

BootSector Virus Protection

When enabled, BIOS warns the user when any program attempts to write to or format the boot sector and allows

the user to intervene.

Shadow

These options control the location of the contents of the 32KB of ROM beginning at the specified memory location.

If no adapter ROM is using the named ROM area, this area is made available to the local bus. The settings are:

SETTING

DESCRIPTION

The video ROM is not copied to RAM. The contents of

the video ROM cannot be read from or written to cache

memory.

Disabled

The contents of C000h - C7FFFh are written to the same

address in system memory (RAM) for faster execution.

The contents of the named ROM area are written to the

same address in system memory (RAM) for faster

execution, if an adapter ROM will be using the named

ROM area. Also, the contents of the RAM area can be

read from and written to cache memory.

Enabled

Cached

Table 6-3 Shadow Setting

Video ROM Shadow C000, 32K

When this option is set to Enabled, the video ROM area from C000h-C7FFh is copied (shadowed) to RAM for

faster execution.

IDE Block Mode Transfer

If your hard disk supports multi-sector transfer, you can enable this option to speed the IDE transfer rate. When

Enabled, the Read/Write and From/To operations between BIOS and hard disk will be done block by block.

IDE LBA Mode

The maximum capacity of a standard IDE disk drive without LBA mode was 528MB. The LBA mode enables IDE

drive to have more than 528MB in one disk drive.

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OnBoard FDC

This option enables the floppy drive controller on the AR-B1474.

OnBoard IDE

This option Enabled/Disabled the use of the IDE controller on the AR-B1474.

Parallel Port Address

This option is used to select the port address and the IRQ of the on-board parallel port. The addresses are 378H,

278H, 3BCH, and Disable. The IRQs are IRQ5 & IRQ7 for selecting.

Parallel Port Mode

This option is specifies the parallel port mode. The settings are Printer or Extended (Bi-direction). The system

support four mode: SPP, EPP & SPP, ECP, ECP & EPP for selecting.

Serial Port 1

This option is used to select the port address and the IRQs of the on-board serial port A. The options are 3F8H,

2F8H, 3E8H, 2E8H, and Disable. The system support IRQ3, IRQ4, IRQ5, and IRQ9 for selecting.

Serial Port 2

This option is used to select the port address and the IRQs of the on-board serial port B. The options are 3F8H,

2F8H, 3E8H, 2E8H, and Disable. The system support IRQ3, IRQ4, IRQ5, and IRQ9 for selecting.

6.4 ADVANCED CHIPSET SETUP

This option controls the configuration of the board’ s chipset. Control keys for this screen are the same as for the

previous screen.

Automatic Configuration

If selecting a certain setting for one BIOS Setup option determines the settings for one or more other BIOS Setup

options, BIOS automatically assigns the dependent settings and does not permit the end user to modify these

settings unless the setting for the parent option is changed. Invalid options are grayed and cannot be selected.

There is two department: DRAM Setting and ISA Bus Clock & Timing Setting

AR Bus Clock Select

DRAM Read Wait State

DRAM Write Wait State

CACHE Read Wait State

CACHE Write Wait State

Cycle Check Point

These options set the DRAM and Cache RAM access speed. If AUTO Config Function option is enabled, the other

options will return to the default settings.

I/O Recovery Feature

I/O Recovery Period

If I/O Recovery Feature option is enabled, the BIOS inserts a delay time between two I/O commands. The delay

time is defined in I/O Recovery Period option.

Memory Remapping

If this option is enabled, the un-shadowed RAM area will be remapped to 1MB area above.

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Parity Check

This option enables or disables parity error checking for all system RAM. This option must be Disabled if the used

DRAM SIMMs are 32-bit but not 36-bit devices.

Slow Refresh

This options sets the DRAM refresh cycle time. The settings are 15us, 30us, 60us, and 120us.

Hidden Refresh

Hidden refresh separates refreshing of AT-bus memory and local DRAM. The AT-bus controller arbitrates

between CPU accesses to the AT bus, DMA, and AT refresh, while the DRAM controller arbitrates between CPU

DRAM accesses and DRAM refresh cycle.

Ext. Cache WB/WT Feature

This option selects the type of caching algorithm of secondary cache memory. The settings are Wr-Thru or Wr-

Back.

Int. Cache WB/WT Feature

This option selects the type of caching algorithm of CPU internal cache memory. The settings are Wr-Thru or Wr-

Back.

ISA Write Cycle Insert WS

When Enabled, the wait state is added in both I/O and memory write cycle.

16-Bit ISA I/O Command WS

This option sets the wait state of 16-bit I/O cycle. The settings are 0WS, 1WS, 2WS, and 3WS.

16-Bit ISA Mem. Command WS

This option sets the wait state of 16-bit memory cycle. The settings are 0WS, 1WS, 2WS, and 3WS.

Polling Clock Select

This option sets the polling clock of IRQ and DRQ signals. The settings are CLK2, CLK2/2, CLK2/3, CLK2/4,

28.6MHz, and 14.3MHz.

6.5 POWER MANAGEMENT

This section is used to configure Power management setup for configuring power management features.

IDE Standby Mode (Min.)

This option specifies the length of time of hard disk drive inactivity that must expire before the IDE hard disk drive

is placed in IDE Standby Power Down Mode.

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6.6 AUTO-DETECT HARD DISKS

This option detects the parameters of an IDE hard disk drive, and automatically enters them into the Standard

CMOS Setup screen.

6.7 PASSWORD SETTING

This BIOS Setup has an optional password feature. The system can be configured so that all users must enter a

password every time the system boots or when BIOS Setup is executed. User can set either a Supervisor

password or a User password.

6.7.1 Setting Password

Select the appropriate password icon (Supervisor or User) from the Security section of the BIOS Setup main menu.

Enter the password and press [Enter]. The screen does not display the characters entered. After the new

password is entered, retype the new password as prompted and press [Enter].

If the password confirmation is incorrect, an error message appears. If the new password is entered without error,

press [Esc] to return to the BIOS Main Menu. The password is stored in CMOS RAM after BIOS completes. The

next time the system boots, you are prompted for the password function is present and is enabled.

6.7.2 Password Checking

The password check option is enabled in Advanced Setup by choosing either Always (the password prompt

appears every time the system is powered on) or Setup (the password prompt appears only when BIOS is run).

The password is stored in CMOS RAM. User can enter a password by typing on the keyboard. As user select

Supervisor or User. The BIOS prompts for a password, user must set the Supervisor password before user can

set the User password. Enter 1-6 character as password. The password does not appear on the screen when

typed. Make sure you write it down.

6.8 LOAD DEFAULT SETTING

In this section permit user to select a group of setting for all BIOS Setup options. Not only can you use these items

to quickly set system configuration parameters, you can choose a group of settings that have a better chance of

working when the system is having configuration related problems.

6.8.1 Auto Configuration with Optimal Setting

User can load the optimal default settings for the BIOS. The Optimal default settings are best-case values that

should optimize system performance. If CMOS RAM is corrupted, the optimal settings are loaded automatically.

Load high performance settings (Y/N) ?

6.8.2 Auto Configuration with Fail Safe Setting

User can load the Fail-Safe BIOS Setup option settings by selecting the Fail-Safe item from the Default section of

the BIOS Setup main menu.

The Fail-Safe settings provide far from optimal system performance, but are the most stable settings. Use this

option as a diagnostic aid if the system is behaving erratically.

Load failsafe settings (Y/N) ?

6-7

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6.9 BIOS EXIT

This section is used to exit the BIOS main menu in two types situation. After making your changes, you can either

save them or exit the BIOS menu and without saving the new values.

6.9.1 Save Settings and Exit

This item set in the <Standard CMOS Setup>, <Advanced CMOS Setup>, <Advanced Chipset Setup> and the new

password (if it has been changed) will be stored in the CMOS. The CMOS checksum is calculated and written into

the CMOS.

As you select this function, the following message will appear at the center of the screen to assist you to save data

to CMOS and Exit the Setup.

Save current settings and exit (Y/N) ?

6.9.2 Exit Without Saving

When you select this option, the following message will appear at the center of the screen to help to Abandon all

Data and Exit Setup.

Quit without saving (Y/N) ?

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7. SPECIFICATIONS

CPU:

25-100 MHz INTEL/AMD/CYRIX 80486DX/DX2/DX4

Bus Interface:

Chipset:

ISA (PC-AT) Bus and PC/104 Bus

ALI M1429 and M1431

RAM Memory:

Shadow RAM:

1MB to 32MB using 32-bit or 36-bit 72-pin SIMMs with access time of 70ns or less

Up to 256KB in 32 KB blocks supports system and video BIOS

Extended Memory Fully supports the LIM EMS 4.0 and 3.2 specifications

Mapping:

Co-Processor:

Supported by all CPUs

Legal AMI system BIOS

BIOS:

IDE HDD Interface: Supports up to two IDE type hard disk drives (software enable/disable)

Floppy Disk Drive: Supports up to two 5.25 (360KB & 1.2MB) or 3.5 (720KB & 1.44MB) floppy disk drives

(software enable/disable)

Parallel Port:

Serial Port:

One Centronic parallel port configurable to LPT1, LPT2, LPT3, or disable.

Two RS-232C serial port (with 16byte FIFOs, 16C550 compatible) configures as COM1,

COM2, COM3, COM4 or disable

Real-Time

DS12887 or compatible chip

Clock/Calendar:

Watchdog Timer: Programmable time-out interval from 6 to 42 seconds. The activity can be Reset System or

Generate IRQ 15 Signal

Solid State Disk:

Up to 3MB bootable solid state disk, it accepts 128Kx8 to 1Mx8 EPROM, 128Kx8 to 512Kx8

SRAM, and 64Kx8 to 512Kx8 5V FLASH

Build-in buzzer

Speaker:

DMA Channels:

Interrupt Levels:

Keyboard Port:

Bus Speed:

PCB:

7 DMA channels

15 vectored interrupt levels

PS/2 compatible 6-pin mini DIN connector, adapter cable for PC/AT is included

Programmable 1/4, 1/5, 1/6, 1/8, 1/10, or 1/12 input clock and 7.159MHz

8 layers for noise reduction

System

Landmark speed V2.0: 359MHz (INTEL 80486DX4-100)

Performance:

Power Supply:

Only +5V DC +/-% Power requirements: +5V@ 1.5A maximum

Stand Alone

Operation:

Operating

Temperature:

Storage

Provides external power connector and 4 fixed holes for stand-alone operation

0 to 60 degree C (140 degree F)

-25 to 85 degree C

Temperature:

Humidity:

0 to 95% (non-condensing)

Dimensions:

Weight:

Half size, 12.2cm x 18.5cm (4.80” x 7.29” )

280g (without CPU, DRAM SIMM, ROM and RAM chips)

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8. PLACEMENT & DIMENSIONS

8.1 PLACEMENT

CN1

CN2

CN3

J1 J2

J3 J4

JP15

JP1

LED1

LED2

JP14

JP2

SW1

JP3

JP4

JP5

SIMM1

U13

DB1

U12

JP6

JP7

JP8

U17

U18

P10

JP9

JP10

DB2

U26

U27

U20

CN6

JP11

CN4

H14

H15

C N 6

JP12

JP13

BUS1

BUS2

CN5

H16

H18

H19

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8.2 DIMENSIONS

7290

540

150

3290

2900

294

9- Æ138

6300

5500

3190

3150

540

765

200

100

1700

1900

3000

3200

525

620

Unit: mil (1 inch = 25.4 mm = 1000 mil)

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9.MEMORY BANKS & PROGRAMMING RS-485

9.1 USING MEMORY BANK

This section provides the information about how to access the memory on the AR-B1474 without using the AR-

B1474 SSD BIOS. The AR-B1474 hardware divides every 8K bytes of memory into a memory bank. To access the

data in the memory, you have to assign the chip number and the bank number. On every chip, the memory bank

number starts from zero. The last memory bank number depends on the size of the memory chip used on the AR-

B1474. For example, if you use the 256K bytes memory chip, the bank number on every chip would be in the

range of 0 to 31. The chip numbers and the bank numbers are determined by the bank select register on the AR-

B1474.

The I/O addresses of these registers are determined by SW1-1and SW1-2. The memory address of the memory

bank is located on the range selected by SW1-3 and SW1-4.

The I/O port address of the bank select register is base port+0. The following is the format of the bank select

BASE+0

CS1

CS0

Where:

CS1-CS0 : Chip select

CS1

CS0

Socket

Disable

MEM1

MEM2

MEM3

For different types of memory, K0 to K5 have different explanations. These bits are used to select the bank number

of specific memory located in CS0 and CS1.

Memory

64KB EPROM (FLASH)

128KB EPROM (FLASH)

256KB EPROM (FLASH)

512KB EPROM (FLASH)

128KB SRAM

BS2 BS1 BS0

BS3 BS2 BS1 BS0

BS4

BS4 BS5 BS3 BS2 BS1 BS0

BS3 BS2 BS1 BS0

BS5 BS4 BS3 BS2 BS1 BS0

512KB SRAM

NOTE: BS0 to BS5 are the memory bank select bits. For example, 128KB memory has sixteen 8K-byte banks, so

4 bits (BS0 to BS3) are needed, and 512KB memory needs 6 bits (BS0 to BS5), etc.

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Example 1:

Select the 10th bank of the MEM1 on the AR-B1474. The AR-B1474 is using 27C020 (256K*8), and

the base port is &H210.

100 base_port=&H210

110 OUT base_port+0,&H59

Example 2:

Select the 40th bank of MEM3 on the AR-B1474. The AR-B1474 is using 27C040 (512K*8), and the

base port is &H390.

200 base_port=&H390

210 OUT base_port+0,&HD7

9.2 PROGRAMMING RS-485

The majority communicative operation of the RS-485 is in the same of the RS-232. When the RS-485 proceeds

the transmission which needs control the TXC signal, and the installing steps are as follows:

Step 1:

Step 2:

Step 3:

Step 4:

Enable TXC

Send out data

Waiting for data empty

Disable TXC

NOTE: Please refer to the section of the “ Serial Port” in the chapter “ System Control” for the detail description of

the COM port’ s register.

(1) Initialize COM port

Step 1:

Initialize COM port in the receiver interrupt mode, and /or transmitter interrupt mode. (All of the

communication protocol buses of the RS-485 are in the same.)

Step 2:

NOTE:

Disable TXC (transmitter control), the bit 0 of the address of offset+4 just sets “ 0” .

Control the AR-B1474 CPU card’ s DTR signal to the RS-485’ s TXC communication.

(2) Send out one character (Transmit)

Step 1:

Step 2:

Step 3:

Enable TXC signal, and the bit 0 of the address of offset+4 just sets “ 1” .

Send out the data. (Write this character to the offset+0 of the current COM port address)

Wait for the buffer’ s data empty. Check transmitter holding register (THRE, bit 5 of the address of

offset+5), and transmitter shift register (TSRE, bit 6 of the address of offset+5) are all sets must be

“ 0” .

Step 4:

Disabled TXC signal, and the bit 0 of the address of offset+4 sets “ 0”

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(3) Send out one block data (Transmit – the data more than two characters)

Step 1:

Step 2:

Step 3:

Enable TXC signal, and the bit 0 of the address of offset+4 just sets “ 1” .

Send out the data. (Write all data to the offset+0 of the current COM port address)

Wait for the buffer’ s data empty. Check transmitter holding register (THRE, bit 5 of the address of

offset+5), and transmitter shift register (TSRE, bit 6 of the address of offset+5) are all sets must be

“ 0” .

Step 4:

Disabled TXC signal, and the bit 0 of the address of offset+4 sets “ 0”

(4) Receive data

The RS-485’ s operation of receiving data is in the same of the RS-232’ s.

(5) Basic Language Example

a.) Initial 86C450 UART

OPEN “ COM1:9600,m,8,1” AS #1 LEN=1

REM Reset DTR

OUT &H3FC, (INP(%H3FC) AND &HFA)

RETURN

b.) Send out one character to COM1

REM Enable transmitter by setting DTR ON

OUT &H3FC, (INP(&H3FC) OR &H01)

REM Send out one character

PRINT #1, OUTCHR$

REM Check transmitter holding register and shift register

IF ((INP(&H3FD) AND &H60) >0) THEN 60

REM Disable transmitter by resetting DTR

OUT &H3FC, (INP(&H3FC) AND &HEF)

RETURN

c.) Receive one character from COM1

REM Check COM1: receiver buffer

IF LOF(1)<256 THEN 70

REM Receiver buffer is empty

INPSTR$”

RETURN

REM Read one character from COM1: buffer

INPSTR$=INPUT$(1,#1)

RETURN

9-3

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10.SSD TYPES SUPPORTED & INDEX

10.1 SSD TYPES SUPPORTED

The following list contains SRAMs supported by the AR-B1474:

AKM

HITACHI

NEC

AKM628128

HM628128

UPD431000A

CXK581000P/M

(128Kx8, 1M bits)

SONY

HITACHI

NEC

SONY

HM628512

UPD434000

CXK584000P/M

(512Kx8, 4M bits)

The following list contains large page 5V FLASHs supported by the AR-B1474:

AMD

Am29F512

Am29F010

Am29F020

Am29F040

(64Kx8, 512K bits)

(128Kx8, 1M bits)

(256Kx8, 2M bits)

(512Kx8, 4M bits)

The following list contains small page 5V FLASHs supported by the AR-B1474:

ATMEL

SST

ATMEL

SST

WINBOND

ATMEL

SST

AT29C512

PH29EE512

AT29C010

28EE010

(64Kx8, 512K bits)

(128Kx8, 1M bits)

(256Kx8, 2M bits)

(512Kx8, 4M bits)

28EE011

PH29EE010

W29EE011

AT29C020

AT29C040

AT29C040A

PH28SF040

The following list contains EPROMs supported by the AR-B1474:

AMD

Am27C010

AT27C010

MBM27C1001

HN27C101

D27C010

M5M27C101

D27C1001

NM27C010

M27C1001

TMS27C010

TCS711000

(128Kx8, 1M bits)

ATMEL

FUJITSHU

HITACHI

INTEL

MITSHUBISHI

NEC

SGS-THOMSON

TOSHIBA

AMD

Am27C020

AT27C020

MBM27C2001

HN27C201

D27C020

M5M27C201

D27C2001

NM27C020

(256Kx8, 2M bits)

ATMEL

FUJITSU

HITACHI

INTEL

MITSHUBISHI

NEC

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SGS-THOMSON

M27C2001

TMS27C020

TCS712000

(256Kx8, 2M bits)

TOSHIBA

AMD

Am27C040

AT27C040

MBM27C4001

HN27C401

D27C040

M5M27C401

D27C4001

NM27C040

M27C4001

TMS27C040

TCS714000

(512Kx8, 4M bits)

ATMEL

FUJITSU

HITACHI

INTEL

MITSUBISHI

NEC

SGS-THOMSON

TOSHIBA

ATMEL

AT27C080

(1Mx8, 8M bits)

The following list contains 12V FLASHs supported by the AR-B1474:

AMD

INTEL

SGS-THOMSON

AMD

INTEL

SGS-THOMSON

MXIC

AMD

INTEL

SGS-THOMSON

MXIC

Am28F512

P28F512

M28F512

Am28F010

P28F010

M28F1001

MX28F1000

Am28F020

P28F020

(64Kx8, 512K bits)

(128Kx8, 1M bits)

(256Kx8, 2M bits)

M28F2001

MX28F2000

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10.2 INDEX

Name

CN1

CN2

CN3

CN4

CN5

CN6

Function

Hard disk (IDE) connector

Page

3-3

FDD port connector

3-4

Parallel port connector

40-pin PC/104 connector bus C & D

6-pin mini DIN keyboard connector

64-pin PC/104 connector bus A & B

HDD LED header

3-4

3-5

3-10

3-5

3-10

3-11

3-10

3-3

Watchdog LED header

External speaker header

External power LED & keyboard lock header

Power connector

External battery connector

Reset header

3-11

3-10

3-2

AUX. Keyboard connector

RS-232 connector for COM-A

RS-232 connector for COM-B

Switch select

DB1

DB2

SW1

SIMM1

LED1

LED2

JP1

JP2

JP3

JP4

JP5

JP6

JP7

JP8

JP9

JP11

JP13

JP15

3-2

5-2

DRAM socket

3-9

Watchdog LED

Power LED

AMD DX2-80 CPU select

CPU voltage select

3-7

3-2

3-11

5-6

3-8

5-5

3-9

3-8

3-2

3-11

3-7

5-6

RS-485 adapter select for COM-A

Battery charger select

1Mx8 EPROM select

CPU base clock select

SSD BIOS select

Cache RAM size select

CPU system clock multiplier select

RS-485 adapter select for COM-B

CRT display type select

AMD 4X CPU (5x86) select

M1,M2 &M3 Memory type setting

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