Quatech Network Card DS 102 User Guide

DS-102  
Dual Channel RS-232 Asynchronous  
Communications Adapter  
for ISA compatible machines  
INTERFACE CARDS FOR IBM PC/AT AND PS/2  
User's Manual  
QUATECH, INC.  
662 Wolf Ledges Parkway  
Akron, Ohio 44311  
TEL: (330) 434-3154  
FAX: (330) 434-1409  
BBS: (330) 434-2481  
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Table of Contents  
1
2
4
I. GENERAL INFORMATION  
II. INSTALLATION  
III. ENABLING AND ADDRESSING PORTS  
Setting the address  
4
6
8
Enabling or disabling ports  
IV. SETTING INTERRUPT LEVELS (IRQS)  
Interrupt Sharing  
9
10  
V. EXTERNAL CONNECTIONS  
14  
VI. SERIAL PORT FUNCTIONAL  
DESCRIPTION  
15  
16  
16  
18  
19  
20  
21  
22  
22  
23  
Accessing the Serial Port registers  
INTERRUPT ENABLE REGISTER  
INTERRUPT IDENTIFICATION REGISTER  
FIFO CONTROL REGISTER (16550 only)  
LINE CONTROL REGISTER  
MODEM CONTROL REGISTER  
LINE STATUS REGISTER  
MODEM STATUS REGISTER  
SCRATCHPAD REGISTER  
FIFO INTERRUPT MODE OPERATION (16550 UART  
only)  
24  
25  
27  
FIFO polled mode operation (16550 UART only)  
BAUD RATE SELECTION  
VII. SPECIFICATIONS  
28  
VIII. TROUBLESHOOTING  
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WARRANTY INFORMATION  
Quatech, Inc. warrants the DS-102 to be free of defects for  
one (1) year from the date of purchase. Quatech, Inc. will repair or  
replace any board that fails to perform under normal operating conditions  
and in accordance with the procedures outlined in this document during  
the warranty period. Any damage that results from improper installation,  
operation, or general misuse voids all warranty rights.  
Please complete the following information and retain for your  
records. Have this information available when requesting warranty  
service.  
DATE OF PURCHASE:  
MODEL NUMBER:  
DS-102  
PRODUCT DESCRIPTION: Dual Channel RS-232 Asynchronous  
Communications Adapter  
SERIAL NUMBER:  
Quatech DS-102 User's Manual  
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© 1993, Quatech, Inc.  
NOTICE  
The information contained in this document cannot be reproduced  
in any form without the written consent of Quatech, Inc. Likewise, any  
software programs that might accompany this document can be used only  
in accordance with any license agreement(s) between the purchaser and  
Quatech, Inc. Quatech, Inc. reserves the right to change this  
documentation or the product to which it refers at any time and without  
notice.  
The authors have taken due care in the preparation of this  
document and every attempt has been made to ensure its accuracy and  
completeness. In no event will Quatech, Inc. be liable for damages of any  
kind, incidental or consequential, in regard to or arising out of the  
performance or form of the materials presented in this document or any  
software programs that might accompany this document.  
Quatech, Inc. encourages feedback about this document. Please  
send any written comments to the Technical Support department at the  
address listed on the cover page of this document.  
IBM PCTM, PC-ATTM, PS/ 2™, and Micro Channel™ are trademarks of International  
Business Machines Corporation.  
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I. GENERAL INFORMATION  
The Quatech, Inc. DS-102 provides two RS-232 asynchronous serial  
communication interfaces for IBM-compatible personal computer systems  
using the ISA (Industry Standard Architecture) expansion bus.  
The DS-102's two serial ports are implemented using 16450  
Universal Asynchronous Receiver/ Transmitters (UARTs). For higher  
performance, 16550 UARTs can be installed in place of the 16450 UARTs.  
The 16550 contains a hardware buffer that reduces processing overhead.  
Software must be aware of the 16550 UART for the device's extra  
capabilities to be used, otherwise it will act as a 16450 UART. The 16550  
is suggested for multitasking environments and for applications involving  
high data rates.  
The DS-102 is highly flexible with respect to addressing and  
interrupt level use. The base I/ O address of each serial port can be  
independently set anywhere within the range of 0000 hex to 07FF hex,  
and available interrupt levels include IRQ2 through IRQ7.  
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II. INSTALLATION  
If the default address and interrupt settings are sufficient, the  
DS-102 can be quickly installed and put to use. The factory defaults are  
listed in Figure 1.  
PORT  
Serial 1  
Serial 2  
ADDRESS  
IRQ ENABLED ?  
3F8 hex (COM1)  
2F8 hex (COM2)  
4
3
YES  
YES  
Figure 1 --- Default address and IRQ settings for DS-102  
The serial port outputs on the DS-102 are CN1 and CN2, which are  
shielded D-9 connectors. Serial 1 is available on CN1 and Serial 2 is  
available on CN2.  
1. If the default settings are correct, skip to step 2, otherwise refer to  
sections III and IV of this document for detailed information on  
how to set the address and IRQ level for each port, and for how to  
disable or enable each port.  
2. Turn off the power of the computer system in which the DS-102 is  
to be installed.  
3. Remove the system cover according to the instructions provided by  
the computer manufacturer.  
4. Install the DS-102 in any vacant expansion slot. The board should  
be secured by installing the Option Retaining Bracket (ORB) screw.  
5. Replace the system cover according to the instructions provided by  
the computer manufacturer.  
6. Attach and secure the D-9 connectors to the desired equipment.  
2
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Set addresses here  
(SW1, SW2)  
(Diagram not to scale)  
16450/16550  
16450/16550  
CN1  
J7  
J1  
J2  
Serial 1  
Serial 2  
SW1  
SW2  
J4  
J3  
Serial 1  
Serial 2  
J8  
J5 Serial 1  
Serial 2  
J6  
CN2  
QUATECH INC. DS-102  
Set IRQ levels here  
(J5, J6)  
Figure 2 --- Diagram of DS-102  
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III. ENABLING AND ADDRESSING PORTS  
Setting the address  
Each serial port on the DS-102 uses 8 consecutive I/ O locations in  
the range of 0000 hex to 07FF hex. The base address of each port is set  
using a DIP switch pack on the DS-102. When setting the address  
selection switches, a switch in the "ON" position specifies that the  
corresponding address line must be a logic 0 for the port to be selected.  
Similarly, a switch in the "OFF" position forces the corresponding address  
line to be a logic 1 for the port to be selected.  
Switch SW1 selects address lines A10 through A3 for Serial 1.  
Switch SW2 serves the same purpose with respect to Serial 2. The  
remaining address lines (A2, A1 and A0) are used by the UART to select  
the register being accessed. Address lines A11 through A15 must be at  
logic 0 for a port to be selected. The serial ports may be independently  
enabled or disabled by installing or removing a jumper from jumper pack  
J4.  
Figure 3 shows how the switches on the DS-102 represent the  
address values for serial ports. This figure can be used to explain the  
examples shown in Figure 4.  
A serial port's address is a 16-bit quantity that is most often expressed  
in four hexadecimal (base 16) digits. A hex digit can hold a value from 0 to  
15 (decimal), and is made up of four binary bits given weights of eight, four,  
two, and one, hence the maximum value of 8+4+2+1 = 15.  
A common serial port address is 03F8 hex. The example below shows  
how the hex digits are broken down into binary bits.  
Binary bits  
0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0  
8 4 2 1 8 4 2 1 8 4 2 1 8 4 2 1  
0+0+0+0 0+0+2+1 8+4+2+1 8+0+0+0  
Bit weight  
Sum of bits  
Hex digits  
8
0
F
3
These address bits are set by the switches.  
All other bits are considered to be zero.  
0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0  
Figure 3 --- Examination of a serial port base address  
4
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Switch on  
bit = 0  
Switch off  
bit = 1  
Serial 1 uses SW1  
Serial 2 uses SW2  
Factory default setting for Serial 1 --- 03F8 hex (COM1)  
SW1  
ON  
1
0
2
2
3
3
1
4
8
5
4
6
2
7
1
8
8
8
F
Factory default setting for Serial 2 --- 02F8 hex (COM2)  
SW2  
ON  
1
0
2
2
2
3
0
4
8
5
4
6
2
7
1
8
8
8
F
Example: 03E8 hex (typical for COM3)  
ON  
1
0
2
2
3
3
1
4
8
5
4
6
2
7
0
8
8
8
E
Example: 02E8 hex (typical for COM4)  
ON  
1
0
2
2
2
3
0
4
8
5
4
6
2
7
0
8
8
8
E
Figure 4 --- Serial Port base I/ O address selection switches  
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The standard addresses for serial ports COM1 and COM2 are listed  
in Figure 5. Recommended addresses for serial ports COM3 and COM4  
are also listed. The switch settings for these addresses are shown in  
Figure 4.  
PORT  
COM1  
COM2  
COM3  
COM4  
TYPICAL I/ O ADDRESS  
03F8 hex  
NOTES  
Factory default for Serial 1.  
Factory default for Serial 2.  
02F8 hex  
03E8 hex  
Recommendations only. No official  
standards exist for COM3 and COM4.  
02E8 hex  
Figure 5 --- Recommended addresses for serial ports  
Enabling or disabling ports  
Each port of the DS-102 may be individually enabled or disabled.  
To enable a port, install a jumper between the appropriate pins of jumper  
pack J4. To disable a port, remove the appropriate jumper from J4. This  
is illustrated in Figure 6 below.  
The factory default configuration is both serial ports enabled.  
4
2
4
2
3
1
3
1
Serial 1 disabled  
Serial 2 disabled  
Serial 1 enabled  
Serial 2 disabled  
4
2
4
2
3
1
3
1
Serial 1 disabled  
Serial 2 enabled  
Serial 1 enabled  
Serial 2 enabled  
(factory default)  
J4  
Figure 6 --- Enabling and disabling ports  
6
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IV. SETTING INTERRUPT LEVELS (IRQS)  
The DS-102 interrupt circuitry allows each port to use any interrupt  
level in the range IRQ2 through IRQ7. The interrupt levels are selected  
using jumper packs J5 for Serial 1 and J6 for Serial 2. In Figure 7, the  
factory default settings for Serial 1 and Serial 2 are shown.  
Serial 1  
J5  
Default is IRQ 4  
Serial 2  
J6  
Default is IRQ 3  
Figure 7 --- Interrupt level (IRQ) selection  
8
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Interrupt Sharing  
An interrupt sharing circuit allows a port on the DS-102 to share an  
interrupt with the other port on the board or with another Quatech  
adapter supporting sharable interrupts. When interrupt sharing is used,  
the software must query each port attached to a given IRQ level when an  
interrupt for that IRQ is received by the computer.  
Use of this feature is beyond the capabilities of most commercial  
applications. If the software to be used with the DS-102 is not specially  
written to take advantage of interrupt sharing, then ensure that each port  
being used is connected to a different IRQ level.  
Interrupt sharing is controlled by jumper J2 as described by Figure  
8 and Figure 9. To maintain 100% ISA bus compatibility, these jumpers  
should be set to the dedicated interrupt level positions.  
CHANNEL  
Serial 1  
CONNECTION  
J2: 2-3 and 5-6  
J2: 1-2 and 4-5  
J3: 2-3 and 5-6  
J3: 1-2 and 4-5  
INTERRUPT OPERATION  
Dedicated interrupt level (default)  
Interrupt sharing enabled  
Dedicated interrupt level (default)  
Interrupt sharing enabled  
Serial 2  
Figure 8 --- Interrupt sharing modes  
Serial 1 uses J2  
Serial 2 uses J3  
4
1
5
6
4
5
6
3
3
2
2
1
Sharing enabled  
Dedicated interrupt  
(non-sharing)  
Figure 9 --- J2, J3 settings  
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V. EXTERNAL CONNECTIONS  
RS-232-C devices are classified by their function as either Data  
Terminal Equipment (DTE) or Data Communication Equipment (DCE).  
Generally, data terminal equipment is defined as the communication  
source and data communication equipment is defined as the device that  
provides a communication channel between two DTE-type devices.  
Terminal  
DTE  
Modem  
DCE  
RS-232-C  
RS-232-C  
Telephone  
line  
Terminal  
DTE  
Modem  
DCE  
Figure 10 --- Use of DTEs and DCEs in a communications link  
DTE- and DCE-type devices have complementary pinouts to allow  
terminals and modems to be connected directly using a one-to-one cable  
as shown in Figure 11. In many applications, DCEs are unnecessary, and  
in these cases a cable called a "null modem cable" or "modem eliminator  
cable" is used to directly connect two DTE-type devices. A typical null  
modem cable is also shown in Figure 11.  
(3)  
(2)  
(4)  
(5)  
(20)  
(6)  
(8)  
(22)  
(7)  
(3)  
(2)  
(4)  
(5)  
(20)  
(6)  
(8)  
(22)  
(7)  
RxD  
TxD  
RTS  
CTS  
DTR  
DSR  
DCD  
RI  
(3)  
(2)  
(4)  
(5)  
(20)  
(6)  
(8)  
(22)  
(7)  
RxD  
TxD  
RTS  
CTS  
DTR  
DSR  
DCD  
RI  
(3)  
(2)  
(4)  
(5)  
(20)  
(6)  
(8)  
(22)  
(7)  
TxD  
RxD  
CTS  
RTS  
DSR  
DTR  
DCD  
RI  
RxD  
TxD  
RTS  
CTS  
DTR  
DSR  
DCD  
RI  
GND  
GND  
GND  
GND  
Typical DTE-to-DCE cable  
Typical DTE-to-DTE null modem cable  
Figure 11 --- Cabling requirements for RS-232-C devices  
(cables using 25-pin connectors shown)  
10  
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To simplify connections to other devices, each port on the DS-102 is  
equipped with a jumper block that allows the port to be configured as  
either a DTE- or DCE-type device. This allows the DS-102 to  
communicate with either DTE- or DCE-type devices without using a null  
modem cable. J7 is used for Serial 1 and J8 is used for Serial 2. The  
DTE/ DCE selection jumper blocks are illustrated in Figure 12.  
pin 3  
RxD  
pin 7  
CTS  
pin 4  
DSR  
7
8
1
2
3
4
5
6
TxD  
pin 2  
RTS  
pin 8  
DTR  
pin 6  
J7 -- Serial 1  
J8 -- Serial 2  
These jumper blocks are used to  
connect RS-232 signals to the  
various pins of the D-9 connectors.  
9
10  
11  
12  
pin 3  
RxD  
pin 7  
CTS  
pin 4  
DSR  
pin 3  
RxD  
pin 7  
CTS  
pin 4  
DSR  
TxD  
pin 2  
RTS  
pin 8  
DTR  
pin 6  
TxD  
pin 2  
RTS  
pin 8  
DTR  
pin 6  
DTE configuration  
(factory default)  
DCE configuration  
Figure 12 --- DTE or DCE output selection  
(Jumpers J7 and J8)  
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The DS-102 connects to peripheral equipment through male D-9  
connectors. Adapters are available to convert these connectors into  
standard D-25 male connectors. The standard serial port connections are  
listed in Figure 13.  
RS-232 Signal  
Description  
DTE Connection  
DCE Connection  
D-9  
1
D-25  
8
D-9  
1
D-25  
8
Data Carrier Detect  
Receive Data  
(DCD)  
(RxD)  
(TxD)  
2
3
3
2
Transmit Data  
3
2
2
3
Data Terminal Ready (DTR)  
Signal Ground  
4
20  
7
6
6
5
5
7
Data Set Ready  
Request To Send  
Clear To Send  
Ring Indicator  
(DSR)  
(RTS)  
(CTS)  
(RI)  
6
6
4
20  
5
7
4
8
8
5
7
4
9
22  
9
22  
Figure 13 --- DS-102 connector definitions for RS-232-C  
13  
25  
12  
24  
11  
23  
10  
22  
21  
20  
5
4
3
2
1
9
8
7
6
5
4
3
2
1
9
8
7
6
19  
18  
17  
16  
15  
14  
D-9 connector  
(CN1 and CN2)  
D-25 connector  
(using adapter cable)  
Figure 14 --- DS-102 Output connectors  
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VI. SERIAL PORT FUNCTIONAL  
DESCRIPTION  
This section contains information intended for advanced users  
planning to do custom programming with the DS-102. The information  
presented here is a technical description of the interface to the 16450 or  
16550 UART.  
The 16450 UART is an improved functional equivalent of the 8250  
UART, performing serial-to-parallel conversion on received data and  
parallel-to-serial conversion on output data. Designed to be compatible  
with the 16450, the 16550 UART enters character (non-FIFO) mode on  
reset. In this mode, the 16550 appears as a 16450 to application software.  
An additional mode, FIFO mode, can be invoked through software  
to reduce CPU overhead. FIFO mode increases performance by providing  
two 16-byte hardware buffers, one for transmit and one for receive. This  
can reduce the frequency of interrupts issued to the CPU by the UART.  
Other features of the 16450 and 16550 include:  
| Programmable baud rate, character length, parity,  
and number of stop bits.  
| Automatic control of start, stop, and parity bits.  
| Independent and prioritized interrupts.  
| Transmit clock output / receive clock input.  
The DS-102's serial ports are controlled by the 16450 or 16550  
UARTs labeled U7 and U8. The serial ports will generate interrupts in  
accordance with the bits set in the interrupt enable register of the UARTs.  
In order to maintain compatibility with earlier personal computer  
systems, the user-defined output OUT2 is used as an external interrupt  
enable and must be set active for interrupts to be acknowledged. OUT2 is  
accessed through the UART's MODEM control register.  
The following pages provide a brief summary of the internal  
registers available within the 16450 and 16550 UARTs. Registers and  
functions specific to the 16550 will be indicated with boldface italic  
notations.  
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Accessing the Serial Port registers  
Figure 15 lists the address map for the 16450 and 16550 UARTs.  
Each register can be accessed by reading from or writing to the proper  
I/ O address. This I/ O address is determined by adding an offset to the  
base address set for the particular serial port. The base address is set  
using DIP switches on the DS-102 (see section III).  
Notice that two locations access different registers depending on  
whether an I/ O read or I/ O write is attempted. Address [base+0]  
accesses the receive buffer on an I/ O read, or the transmit buffer on an  
I/ O write. Address [base+2] accesses the Interrupt Identification register  
on an I/ O read or the FIFO control register (16550 only) on an I/ O write.  
Also, notice that if address [base+0] or [base+1] is used with the DLAB bit  
from the Line Control Register set to '1', the baud rate divisor latches are  
accessed.  
NOTE: All figures displaying bitmapped registers are  
formatted such that bit 7 is the high-order bit.  
UART Addressing  
Register Description  
DLAB  
I/ O Address  
Base + 0  
0
Receive buffer (read)  
Transmit holding register (write)  
0
Base + 1  
Base + 2  
Interrupt enable  
X
Interrupt identification (read) (16450 and 16550)  
FIFO control (write) (16550 only)  
X
X
X
X
X
1
Base + 3  
Base + 4  
Base + 5  
Base + 6  
Base + 7  
Base + 0  
Base + 1  
Line control  
MODEM control  
Line status  
MODEM status  
Scratchpad  
Baud rate divisor latch (LSB) *  
Baud rate divisor latch (MSB) *  
1
(X = don't care)  
* DLAB in Line Control Register must be set to access baud rate divisor latch.  
Figure 15 --- Serial port register address map for 16450/ 16550 UART  
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INTERRUPT ENABLE REGISTER  
This register is located at I/ O address [base+1]. It enables the five  
types of UART interrupts. Interrupts can be totally disabled by setting all  
of the enable bits in this register to a logic 0. Setting any bit to a logic 1  
enables that particular interrupt.  
BIT  
7
DESCRIPTION  
0 --- reserved  
0 --- reserved  
0 --- reserved  
0 --- reserved  
6
5
4
3
EDSSI --- MODEM Status Interrupt:  
When set (logic 1), enables interrupt on clear to send, data set ready,  
ring indicator, and data carrier detect.  
2
1
0
ELSI --- Receiver Line Status Interrupt:  
When set (logic 1), enables interrupt on overrun, parity, framing  
errors, and break indication.  
ETBEI --- Transmitter Holding Register Empty Interrupt:  
When set (logic 1), enables interrupt on transmitter holding register  
empty.  
ETBEI --- Received Data Available Interrupt:  
When set (logic 1), enables interrupt on received data available. For  
16550 FIFO mode, interrupts are also enabled for receive FIFO trigger  
level reached and for receive timeout.  
Figure 16 --- Interrupt Enable Register bit definitions  
INTERRUPT IDENTIFICATION REGISTER  
This read-only register is located at I/ O address [base+2]. When  
this register is read, the UART freezes all interrupts and indicates the  
highest priority interrupt. During this time, new interrupts are detected  
by the UART, but are not reported in this register until the access  
completes.  
For the 16550 only, this register can be used to indicate whether  
the FIFO mode is engaged by examining bits 6 and 7.  
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BIT  
7
DESCRIPTION  
FFE --- FIFO enable: (16550 only)  
When logic 1, indicates FIFO mode enabled. Always logic 0 for the 16450.  
6
FFE --- FIFO enable: (16550 only)  
When logic 1, indicates FIFO mode enabled. Always logic 0 for the 16450.  
5
4
3
2
1
0 --- reserved  
0 --- reserved  
Interrupt Identification:  
IID2 ---  
IID1 ---  
IID0 ---  
Indicates highest priority interrupt pending if any. See Figure 18.  
NOTE: IID2 is always a logic 0 on the 16450 or in non-FIFO mode  
on the 16550.  
0
IP --- Interrupt pending:  
When logic 0, indicates that an interrupt is pending and the contents of the  
interrupt identification register may be used to determine the interrupt  
source. See Figure 18.  
Figure 17 --- Interrupt Identification Register bit definitions  
Figure 18 gives the detail of the IIDx bits in the Interrupt  
Identification Register. These bits are examined to determine the source  
of an interrupt.  
IIDx bits IP Priority Interrupt Type  
2
1
0
don't  
care  
1
0
N/ A  
1st  
None  
0
0
1
1
0
Receiver Line Status: Indicates overrun, parity, framing errors  
or break interrupts. The interrupt is cleared by reading the line  
status register.  
1
0
0
2nd  
2nd  
Received Data Ready (16450 or 16550): Indicates receive data  
available. The interrupt is cleared by reading the receive buffer.  
In 16550 FIFO mode, indicates the receiver FIFO trigger level  
has been reached. The interrupt is reset when the FIFO drops  
below the trigger level.  
1
1
0
Character Timeout (16550 FIFO mode only): Indicates no  
characters have been removed from or input to the receiver  
FIFO for the last four character times and there is data present  
in the receiver FIFO. The interrupt is cleared by reading the  
receiver FIFO.  
0
0
0
0
1
0
0
0
3rd  
4th  
Transmitter Holding Register Empty : Indicates the transmitter  
holding register is empty. The interrupt is cleared by reading  
the interrupt identification register or writing to the transmitter  
holding register. (Indicates transmit FIFO empty for 16550.)  
MODEM Status: Indicates clear to send, data set ready, ring  
indicator, or data carrier detect have changed state. The  
interrupt is cleared by reading the MODEM status register.  
Figure 18 --- IIDx bit decoding  
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FIFO CONTROL REGISTER (16550 only)  
This register, which applies only to the 16550 UART, is a  
write-only register located at I/ O address [base+2]. It is used to enable  
the FIFO mode, clear the FIFOs, set the threshold level for the receive  
FIFO to generate interrupts, and to set the mode under which the device  
uses DMA. Note that DMA mode is NOT supported by the DS-102  
adapter.  
BIT  
7
DESCRIPTION  
Receiver FIFO Trigger Level (16550 only):  
RXT1 ---  
Determines the trigger level for the receiver FIFO interrupt  
6
RXT0 ---  
RXT1  
RXT0  
Receiver FIFO trigger level (bytes)  
0
0
1
1
0
1
0
1
1
4
8
14  
5
4
3
0 --- reserved  
0 --- reserved  
DMAM --- DMA mode select (16550 only):  
When set (logic 1), RxRDY and TxRDY change from mode 0 to mode 1 for  
DMA transfers. (DMA mode is not supported on the DS-102.)  
2
1
0
XRST --- Transmit FIFO reset (16550 only):  
When set (logic 1), all bytes in the transmitter FIFO are cleared and the  
counter is reset. The shift register is not cleared. XRST is self-clearing.  
RRST --- Receive FIFO reset (16550 only):  
When set (logic 1), all bytes in the receiver FIFO are cleared and the counter  
is reset. The shift register is not cleared. RRST is self-clearing.  
FE --- FIFO enable (16550 only):  
When set (logic 1), enables transmitter and receiver FIFOs. When cleared  
(logic 0), all bytes in both FIFOs are cleared. This bit must be set when  
other bits in the FIFO control register are written to or the bits will be  
ignored.  
Figure 19 --- 16550 FIFO Control Register bit definitions  
18  
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LINE CONTROL REGISTER  
This register is located at I/ O address [base+3]. It is used for  
specifying the format of the asynchronous serial data to be processed by  
the UART, and to set the Divisor Latch Access Bit (DLAB) allowing access  
to the baud rate divisor latches.  
BIT  
7
DESCRIPTION  
DLAB --- Divisor latch access bit:  
DLAB must be set to logic 1 to access the baud rate divisor latches. DLAB  
must be set to logic 0 to access the receiver buffer, transmitting holding  
register and interrupt enable register.  
6
5
BKCN --- Break control:  
When set (logic 1), the serial output (SOUT) is forced to the spacing state  
(logic 0).  
STKP --- Stick parity:  
Forces parity to logic 1 or  
logic 0 if parity is enabled.  
STKP EPS PEN  
PARITY  
None  
Odd  
Even  
Logic 1  
Logic 0  
x
0
0
1
1
x
0
1
0
1
0
1
1
1
1
EPS --- Even parity select:  
Selects even or odd parity if  
parity is enabled.  
4.00  
0
3
PEN --- Parity enable:  
Enables parity on  
transmission and verification  
on reception.  
2
STB --- Number of stop bits:  
Sets the number of stop bits  
transmitted.  
STB WLS1 WLS0 WORD LEN STOP BITS  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
5 bits  
6 bits  
7 bits  
8 bits  
5 bits  
6 bits  
7 bits  
8 bits  
1
1
1
1
1.5  
2
2
2
1
0
Word length select:  
Determines the  
number of bits per  
transmitted word.  
WLS1 ---  
WLS0 ---  
Figure 20 --- Line Control Register bit definitions  
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MODEM CONTROL REGISTER  
This register is located at I/ O address [base+4], and is used to  
control the interface with the modem or device used in place of a modem.  
This register allows the states of the "modem control signals" to be  
changed. These are DTR (Data Terminal Ready) and RTS (Request To  
Send). It is also possible to place the UART in a loopback mode for  
testing. Finally, the user-defined outputs OUT1 and OUT2 are controlled  
from this register.  
The DS-102 handles the OUT1 and OUT2 signals in the manner  
appropriate for maintaining compatibility with standard PC serial ports:  
| The OUT1 output is not connected.  
| The OUT2 output is used to globally enable interrupts to  
the computer. It should be active at all times if interrupts  
are being used.  
BIT  
7
DESCRIPTION  
0 --- reserved  
6
0 --- reserved  
5
0 --- reserved  
4
LOOP --- Loopback enable:  
When set (logic 1), the transmitter shift register is connected directly to the  
receiver shift register. The MODEM control inputs are internally connected  
to the MODEM control outputs and the outputs are forced to the inactive  
state. All characters transmitted are immediately received to verify  
transmit and receive data paths. Transmitter and receiver interrupts still  
operate normally. MODEM control interrupts are available but are now  
controlled through the MODEM control register.  
3
2
OUT2 ••• Output 2:  
When this bit is set (logic 1), the OUT2 output is forced active to a logic 0.  
When cleared (logic 0), the OUT2 output is forced inactive to a logic 1.  
Used for interrupt enable on the DS-102.  
OUT1 ••• Output 1:  
When this bit is set (logic 1), the OUT1 output is forced active to a logic 0.  
When cleared (logic 0), the OUT1 output is forced inactive to a logic 1.  
Not connected on the DS-102.  
1
0
RTS ••• Request to send:  
When this bit is set (logic 1), the RTS output is forced active to a logic 0.  
When cleared (logic 0), the RTS output is forced inactive to a logic 1.  
DTR -•• Data terminal ready:  
When this bit is set (logic 1), the DTR output is forced active to a logic 0.  
When cleared (logic 0), the DTR output is forced inactive to a logic 1.  
Figure 21 --- Modem Control Register bit definitions  
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LINE STATUS REGISTER  
This register is located at I/ O address [base+5]. It is used to  
provide various types of status information concerning the data transfer.  
As Figure 22 shows, the Line Status Register indicates several types of  
errors, an empty transmit buffer, a ready receive buffer, or a break on the  
receive line.  
BIT  
7
DESCRIPTION  
FFRX ••• Error in RCVR FIFO (16550 FIFO mode only):  
Always logic 0 in 16450 or 16550 non-FIFO mode.  
Indicates one or more parity errors, framing errors, or break indications in the  
receiver FIFO. FFRX is reset by reading the line status register.  
6
5
4
TEMT ••• Transmitter empty:  
Indicates the transmitter holding register or FIFO (16550) AND the transmitter  
shift register are empty and are ready to receive new data. TEMT is reset by  
writing a character to the transmitter holding register.  
THRE ••• Transmitter holding register empty:  
Indicates the transmitter holding register or FIFO (16550) is empty and it is  
ready to accept new data. THRE is reset by writing data to the transmitter  
holding register.  
BI ••• Break interrupt:  
Indicates the receive data input has been in the spacing state (logic 0) for longer  
than one full word transmission time. In 16550 FIFO mode, only one zero  
character is loaded into the FIFO and transfers are disabled until the serial data  
input goes to the mark state (logic 1) and a valid start bit is received.  
3
FE ••• Framing error:  
Indicates the received character had an invalid stop bit. The stop bit following  
the last data or parity bit was a 0 bit (spacing level).  
2
1
PE ••• Parity error:  
Indicates that the received data does not have the correct parity.  
OE ••• Overrun error:  
Indicates the receive buffer was not read before the next character was received  
and the character is destroyed. In 16550 FIFO mode, indicates the receive FIFO  
is full and another character has been shifted in. The character in the shift  
register is destroyed but is not transferred to the FIFO.  
0
DR ••• Data ready:  
Indicates data is present in the receive buffer or FIFO (16550). DR is reset by  
reading the receive buffer register or receiver FIFO.  
Figure 22 --- Line Status Register bit definitions  
Bits BI, FE, PE, and OE are the sources of receiver line status  
interrupts. The bits are reset by reading the line status register. In 16550  
FIFO mode, these bits are associated with a specific character in the FIFO  
and the exception is revealed only when that character reaches the top of  
the FIFO.  
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MODEM STATUS REGISTER  
This register is located at I/ O address [base+6]. It reports on the  
status of signals coming from the modem or equipment used in place of a  
modem. It allows the current states of "modem control signals" to be  
sensed. These signals include the DCD (Data Carrier Detect), RI (Ring  
Indicator), DSR (Data Set Ready), and CTS (Clear To Send).  
The Modem Status Register also provides change information for  
each of these signals. When a modem control signal changes state, the  
appropriate change bit is set to logic 1. The change bits (3, 2, 1, and 0) are  
reset to logic 0 whenever the Modem Status Register is read.  
A modem status interrupt is generated whenever any of bits 3, 2, 1  
or 0 is set by the UART to a logic 1.  
BIT  
7
DESCRIPTION  
DCD ••• Data carrier detect:  
Complement of the DCD input.  
6
5
4
3
RI ••• Ring indicator:  
Complement of the RI input.  
DSR ••• Data set ready:  
Complement of the DSR input.  
CTS ••• Clear to send:  
Complement of the CTS input.  
DDCD ••• Delta data carrier detect:  
Indicates the Data Carrier Detect input has changed state.  
Cleared when this register is read.  
2
TERI ••• Trailing edge ring indicator:  
Indicates the Ring Indicator input has changed from a low to a high  
state.  
Cleared when this register is read.  
1
0
DDSR ••• Delta data set ready:  
Indicates the Data Set Ready input has changed state.  
Cleared when this register is read.  
DCTS ••• Delta clear to send:  
Indicates the Clear to Send input has changed state.  
Cleared when this register is read.  
Figure 23 --- Modem Status Register bit definitions  
SCRATCHPAD REGISTER  
This register is located at I/ O address [base+7]. It is not used by  
the 16450 or 16550. It may be used by the programmer for temporary  
data storage. The Scratchpad Register is eight bits wide and can be read  
or written.  
22  
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FIFO INTERRUPT MODE OPERATION (16550 UART only)  
When the receiver FIFO and receiver interrupts are enabled:  
1. The receive data interrupt is issued when the receive FIFO reaches  
the trigger level. The interrupt is cleared as soon as the receive  
FIFO falls below the trigger level.  
2. The Interrupt Identification Register's receive data available  
indicator is set and cleared along with the receive data interrupt  
when the receive FIFO falls below the trigger level.  
3. The data ready indicator is set as soon as a character is transferred  
into the receiver FIFO and is cleared when the FIFO is empty.  
4. A FIFO timeout interrupt will occur if the receive FIFO contains at  
least one character, at least four character-times have passed since  
receipt of the last character, and the last read of the FIFO by the  
CPU was done more than four character-times ago.  
5. Timeout interrupts are cleared when a read of the receive FIFO is  
done.  
6. The receive FIFO timeout timer is reset whenever a new character  
is received into the FIFO or a read of the FIFO is done.  
When the transmit FIFO and transmit interrupts are enabled:  
1. The transmitter holding register empty interrupt occurs when the  
transmit FIFO is empty, and is cleared when a character is written  
to the FIFO or when the Interrupt Identification Register is read.  
2. Transmitter FIFO empty indications are delayed by one  
character-time less the last stop bit time when the transmitter  
holding register is empty and there have not been at least two  
bytes together in the transmit FIFO since the last time the  
transmitter holding register was empty.  
3. The first transmitter interrupt after enabling the FIFO mode will be  
immediate if that interrupt is enabled.  
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FIFO polled mode operation (16550 UART only)  
The receiver and transmitter are operated independently, which  
would allow either or both to be used in a polled mode rather than using  
interrupts to determine when the UART needs to be serviced.  
To use the UART in a polled mode, the software is responsible for  
continuously checking for the conditions that normally cause interrupts to  
occur. This would be done using the Line Status Register.  
1. The Data Ready bit will be set to logic 1 whenever there is at least  
one byte in the receive FIFO.  
2. Errors can be detected using the various error bits.  
3. The Transmitter Holding Register Empty bit can be used to  
determine when the transmit FIFO is empty.  
4. The Transmitter Empty bit indicates that the transmitter shift  
register is empty as well as the transmit FIFO being empty.  
5. Trigger levels and FIFO timeouts do not apply. Both FIFOs are  
fully capable of holding multiple characters at any time.  
24  
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BAUD RATE SELECTION  
The 16450 or 16550 UART determines the baud rate of the serial  
output using a combination of the clock input frequency and the value  
written to the divisor latches. Standard personal computer serial  
interfaces use an input clock of 1.8432 MHz. To increase versatility, the  
DS-102 uses an 18.432 MHz crystal and a frequency divider circuit to  
produce the standard clock frequency.  
Jumper block J1 is used to set the frequency input to the UART. It  
may be connected to divide the clock input by 1, 2, 5, or 10. A table of  
baud rates available using the 1.8432 MHz input is given in Figure 25.  
For compatibility with standard serial ports, J1 should be  
configured to divide by 10 as shown in Figure 24(d).  
J1  
5
2
6
3
4
1
5
2
6
3
4
1
Divide-by-1 input clock  
(A)  
Divide-by-2 input clock  
(B)  
5
6
4
5
6
4
1
1
2
2
3
3
Divide-by-5 input clock  
(C)  
Divide-by-10 input clock  
Factory default  
(D)  
Figure 24 --- Input clock frequency options  
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DESIRED BAUD  
RATE  
DIVISOR  
LATCH VALUE  
ERROR BETWEEN DESIRED AND  
ACTUAL VALUES (%)  
50  
75  
2304  
1536  
1047  
768  
384  
192  
96  
-
-
110  
0.026  
150  
-
300  
-
600  
-
1200  
1800  
2000  
2400  
3600  
4800  
7200  
9600  
19200  
38400  
56000  
-
64  
-
58  
0.69  
48  
-
32  
-
24  
-
16  
-
12  
-
6
-
-
3
2
2.86  
Figure 25 --- Divisor Latch settings for common baud rates  
using 1.8432 MHz input clock  
26  
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VII. SPECIFICATIONS  
Bus interface:  
Industry Standard Architecture (ISA)  
8-bit bus  
Serial ports  
Controller:  
16450 (16550 optional)  
Interface:  
Two male D-9 connectors  
Two male D-25 connectors  
optional using adapter cables  
Transmit drivers:  
MC1488 or compatible  
High level output voltage: +9V min, +10.5V max  
Low level output voltage: -9V min, -10.5V max  
Switching speed:  
55ns typ, 100ns max  
Receive buffers:  
MC1489 or compatible  
High level input voltage: +3V to +13V  
Low level input voltage: -3V to -13V  
Switching speed:  
120ns typ, 175ns max  
I/ O Address range:  
Interrupt levels:  
0000H - 07FFH  
IRQ2 through IRQ7  
Power requirements  
+5 volts:  
+12 volts:  
-12 volts:  
390 mA typ, 443 mA max  
38 mA typ, 46 mA max  
36 mA typ, 43 mA max  
Quatech DS-102 User's Manual  
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VIII. TROUBLESHOOTING  
Listed here are some common problems and frequent causes of  
those problems. Suggestions for corrective action are given. If the  
information here does not provide a solution, contact Quatech Customer  
Service for technical support.  
Any unauthorized repairs or modifications will void the DS-102's  
warranty.  
Computer will not boot up.  
1. Is the DS-102 properly inserted? Remove the card and try again.  
Perhaps try a different expansion slot.  
2. Is the base address correctly set? Check for address conflicts with  
other devices in the system. Set a different address if necessary.  
3. The DS-102 may be defective. Contact Quatech Customer Service  
for instructions.  
Cannot communicate with other equipment.  
1. Are the cable connections correct? Are the cables securely  
attached?  
2. Are the base address and interrupt level (IRQ) for the port correctly  
set? Check for address and IRQ conflicts with other devices in the  
system. Change the settings if necessary.  
3. Are the DTE/ DCE configuration jumpers properly set? If you are  
trying to communicate with a DTE, a null-modem cable may be  
required, or the DS-102 can be set for DCE output.  
4. If possible, use a loopback connector to test the port. This  
connector needs to connect the following sets of signals:  
TxD and RxD (pins 2 and 3)  
RTS and CTS (pins 7 and 8)  
DCD, DTR, DSR, and RI (pins 1, 4, 6, and 9)  
28  
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DS-102 Dual Channel RS-232 Asynchronous Communications Adapter  
User's Manual  
Revision 3.00 August 13, 1993  
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