NI 5412 Specifications
NI PXI/PCI-5412 14-Bit 100 MS/s Arbitrary Waveform Generator
Unless otherwise noted, the following conditions were used for each
specification:
•
•
•
Interpolation set to maximum allowed factor for a given sample rate.
Signals terminated with 50 Ω.
Low-Gain Amplifier Path set to 2 Vpk-pk, and High-Gain Amplifier
Path set to 12 Vpk-pk
.
•
Sample clock set to 100 MS/s.
Typical values are representative of an average unit operating at room
temperature. Specifications are subject to change without notice. For the
most recent NI 5412 specifications, visit ni.com/manuals.
To access all the NI 5412 documentation, including the NI Signal
Generators Getting Started Guide, which contains functional descriptions
of the NI 5412 signals, navigate to Start»Programs»National
Instruments»NI-FGEN»Documentation.
Caution Hot Surface Allow the NI 5412 to cool before removing it from the chassis to reduce
Power ...................................................................................................... 18
Software .................................................................................................. 19
Environment............................................................................................ 20
Safety, Electromagnetic Compatibility, and CE Compliance................. 22
Physical ................................................................................................... 24
Where to Go for Support......................................................................... 25
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Table 1. (Continued)
Specification
Value
Comments
Maximum Output Voltage
Maximum
Output
Voltage
Path
Load
Maximum Output Voltage (Vpk-pk
)
The Maximum
Output Voltage
of the NI 5412 is
determined by
the Amplitude
Range and the
Offset Range.
Low-
Gain
Amplifier
50 Ω
1 kΩ
Open
50 Ω
1 kΩ
Open
1.000
1.905
2.000
6.000
11.43
12.00
High-
Gain
Amplifier
Accuracy
DC Accuracy
0.2% of Amplitude 0.05% of Offset 500 µV
(within 10 °C of self-calibration temperature)
Calibrated for
high impedance
load.
0.4% of Amplitude 0.05% of Offset 1 mV
(0 °C to 55 °C)
AC Amplitude
Accuracy
1.0% of desired Amplitude 1 mV
50 kHz sine
wave.
Output Characteristics
Output
Impedance
50 Ω or 75 Ω nominal, software-selectable.
—
—
—
Output
Coupling
DC
Output Enable Software-selectable. When the Output Path is disabled, the
CH 0 Output is terminated to ground with a 1 W resistor
equal to the selected output impedance.
Maximum
Output
Overload
The CH 0 output can be connected to a 50 Ω, 12 V source
without sustaining any damage. No damage occurs if the
CH 0 output is shorted to ground indefinitely.
—
—
Waveform
Summing
The CH 0 output supports waveform summing among
similar paths—specifically, the outputs of multiple NI 5412
signal generators can be connected directly together.
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Table 1. (Continued)
Specification
Value
Comments
Frequency and Transient Response
Bandwidth
20 MHz
–3 dB
—
Digital
Interpolation
Filter
Software-selectable Finite Impulse Response (FIR) filter.
Available interpolation factors are 2, 4, or 8.
Passband
Flatness
Low-Gain and High-Gain Amplifiers Path
1.0 dB from DC to 6 MHz
—
Pulse
Response
Path
All values are
typical.
Measured with a
1 m RG-223
cable.
Low-Gain Amplifier
<20 ns
High-Gain Amplifier
Rise/Fall Time
Aberration
<20 ns
<5%
<5%
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2.0
1.6
1.2
0.8
0.4
0.0
–0.4
–0.8
–1.2
–1.6
–2.0
0
0.2
0.4
0.6
0.8
1.0
Time (µs)
Figure 1. Pulse Response, Low-Gain Amplifier Path 50 Ω Load
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Table 1. (Continued)
Specification
Value
Comments
Suggested Maximum Frequencies for Common Functions
Function Path
—
Low-Gain Amplifier
20 MHz
High-Gain Amplifier
20 MHz
Sine
Square
Ramp
5 MHz
5 MHz
1 MHz
1 MHz
Triangle
1 MHz
1 MHz
Spectral Characteristics
Spurious-Free
Dynamic
Range
(SFDR)
without
Path
Amplitude
–1 dBFS.
Measured from
DC to 50 MHz.
SFDR without
harmonics at low
amplitudes is
limited by a
–148 dBm/Hz
noise floor. All
values are
Harmonics
Low-Gain Amplifier
High-Gain Amplifier
–70 dBc
1 MHz
–70 dBc
–65 dBc
–60 dBc
10 MHz
20 MHz
–65 dBc
–60 dBc
typical.
0 ºC to 40 ºC
Total
Harmonic
Distortion
(THD)
Path
Amplitude
–1 dBFS.
Includes the 2nd
through the 6th
harmonic. All
values are
Low-Gain Amplifier
–59 dBc
High-Gain Amplifier
–51 dBc
1 MHz
10 MHz
20 MHz
typical.
–52 dBc
–40 dBc
–45 dBc
–37 dBc
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Table 1. (Continued)
Specification
Value
Comments
Spectral Characteristics (Continued)
AverageNoise
Density
Amplitude
Range
Average Noise
Density at small
amplitudes is
limited by a
–148 dBm/Hz
noise floor.
Average Noise Density
nV
dBFS/
Hz
----------
Path
Vpk-pk
2
dBm
10
Hz
dBm/Hz
–134
Low-Gain
45
–144
–145
High-
Gain
12
25.6
251
–119
Sample Clock
Table 2.
Specification
Value
1. Internal, Divide-by-N (N ≥ 1)
Comments
Sources
Refer to the
Onboard Clock
section for more
information
2. Internal, DDS-based, High-Resolution
3. External, CLK IN (SMB front panel connector)
about Internal
Clock Sources.
4. NI PXI-5412: External, PXI Star trigger
(backplane connector)
5. NI PXI-5412: External, PXI_Trig<0..7>
(backplane connector)
NI PCI-5412: External, RTSI<0..7>
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Table 2. (Continued)
Specification
Value
Comments
Sample Rate Range and Resolution
Sample Clock
—
Source
Sample Rate Range
Sample Rate Resolution
Divide-by-N
23.84 S/s to 100 MS/s
Settable to (100 MS/s) / N
(1 ≤ N ≤ 4,194,304)
High-
10 S/s to 100 MS/s
1.06 µHz
Resolution
CLK IN
200 kS/s to 105 MS/s
10 S/s to 105 MS/s
Resolution determined by
external clock source.
NI PXI-5412
PXI Star
Trigger
External Sample Clock duty
cycle tolerance 40% to 60%.
NI PXI-5412
PXI_Trig<0..7>
10 S/s to 20 MS/s
10 S/s to 20 MS/s
NI PCI-5412
RTSI<0..7>
Effective Sample Rate
Sample Rate
Interpolation
Factor
Effective Sample Effective Sample
(MS/s)
Rate
Rate =
(Interpolation
Factor)*(Sample
Rate)
10 S/s to
105 MS/s
1 (Off)
10 S/s to
105 MS/s
12.5 MS/s to
105 MS/s
2
4
8
25 MS/s to
210 MS/s
10 MS/s to
100 MS/s
40 MS/s to
400 MS/s
10 MS/s to
50 MS/s
80 MS/s to
400 MS/s
Sample Clock Delay Range and Resolution
Sample Clock
Source
Delay Adjustment
Resolution
—
Delay Adjustment Range
1 sample clock period
1 sample clock period
Divide-by-N
<10 ps
High-
Resolution
Sample Clock
Period/16,384
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Table 2. (Continued)
Specification
Value
Comments
System Phase Noise and Jitter (10 MHz Carrier)
Sample Clock
Source
System Phase Noise
Density
(dBc/Hz) Offset
1. High-
Resolution
specifications
vary with
System Output Jitter
(Integrated from
100 Hz to 100 kHz)
100 Hz 1 kHz 10 kHz
Sample Rate.
NI PXI-5412
NI PCI-5412
–100
–90
–118
–110
–120
–120
<6 ps rms
<7 ps rms
2. All values are
typical.
External
Cycle-Cycle Jitter 300 ps
Period Jitter 1 ns
—
Sample Clock
Input Jitter
Tolerance
Sample Clock Exporting
Exported
Sample Clock
Destinations
1. PFI<0..1> (SMB front panel connectors)
Exported Sample
Clocks can be
dividedbyinteger
K (1 ≤ K ≤
2. NI PXI-5412: PXI_Trig<0..6> (backplane connector)
NI PCI-5412: RTSI<0..6>
4,194,304).
Exported
—
Sample Clock
Destinations
Maximum Frequency
105 MHz
Duty Cycle
25% to 65%
—
PFI<0..1>
NI PXI-5412
20 MHz
PXI_Trig<0..6>
NI PCI-5412
20 MHz
—
RTSI<0..6>
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Onboard Clock
(Internal VCXO)
Table 3.
Specification
Value
Comments
Clock Source
Internal sample clocks can either be locked to a Reference
Clock using a phase-locked loop or be derived from the
onboard VCXO frequency reference.
—
Frequency
Accuracy
25 ppm
—
Phase-Locked Loop (PLL) Reference Clock
Table 4.
Specification
Value
Comments
Sources
1. NI PXI-5412—PXI_CLK10 (backplane connector)
The PLL
NI PCI-5412—RTSI_7 (RTSI_CLK)
Reference Clock
provides the
reference
2. CLK IN (SMB front panel connector)
frequency for the
phase-locked
loop.
Frequency
Accuracy
When using the PLL, the Frequency Accuracy of the
NI 5412 is solely dependent on the Frequency Accuracy
of the PLL Reference Clock Source.
—
Lock Time
≤ 200 ms.
—
—
Frequency
Range
5 MHz to 20 MHz in increments of 1 MHz.
Default of 10 MHz.
The PLL Reference Clock Frequency has to be accurate
to 50 ppm.
Duty Cycle
Range
40% to 60%
—
—
Exported PLL
Reference
Clock
1. PFI<0..1> (SMB front panel connectors)
2. NI PXI-5412—PXI_Trig<0..6> (backplane connector)
NI PCI-5412—RTSI<0..6>
Destinations
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CLK IN
(Sample Clock and Reference Clock Input, Front Panel Connector)
Table 5.
Specification
Connector
Value
Comments
SMB (jack)
—
—
—
Direction
Input
Destinations
1. Sample Clock
2. PLL Reference Clock
Frequency
Range
1 MHz to 105 MHz (Sample Clock destination and
sine waves)
—
200 kHz to 105 MHz (Sample Clock destination and
square waves)
5 MHz to 20 MHz (PLL Reference Clock destination)
Input Voltage
Range
Sine wave: 0.65 Vpk-pk to 2.8 Vpk-pk into 50 Ω
(0 dBm to +13 dBm)
—
Square wave: 0.2 Vpk-pk to 2.8 Vpk-pk into 50 Ω
Maximum
Input Overload
10 V
—
—
—
Input
Impedance
50 Ω
Input Coupling AC
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PFI 0 and PFI 1
(Programmable Function Interface, Front Panel Connectors)
Table 6.
Specification
Connectors
Direction
Value
Comments
Two SMB (jack)
Bi-directional
—
—
—
Frequency
Range
DC to 105 MHz
As an Input (Trigger)
Destinations
Start Trigger
—
—
Maximum
–2 V to +7 V
Input Overload
VIH
VIL
2.0 V
0.8 V
1 kΩ
Input
Impedance
As an Output (Event)
Sources
1. Sample Clock divided by integer K (1 ≤ K ≤ 4,194,304)
—
2. Sample Clock Timebase (100 MHz) divided by
integer M (2 ≤ M ≤ 4,194,304)
3. PLL Reference Clock
4. Marker
5. Exported Start Trigger (Out Start Trigger)
Output
Impedance
50 Ω
—
—
Maximum
Output
–2 V to +7 V
Overload
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Table 6. (Continued)
Specification
Value
Comments
VOH
Minimum: 2.9 V (open load), 1.4 V (50 Ω load)
Outputdriversare
+3.3 V TTL
compatible.
Measured with a
1 m cable.
VOL
Maximum: 0.2 V (open load), 0.2 V (50 Ω load)
Rise/Fall Time ≤2.0 ns
(20% to 80%)
Load of 10 pF.
Start Trigger
Table 7.
Specification
Value
Comments
Sources
1. PFI<0..1> (SMB front panel connectors)
—
2. NI PXI-5412—PXI_Trig<0..7> (backplane connector)
NI PCI-5412—RTSI<0..7>
3. NI PXI-5412—PXI Star trigger (backplane connector)
4. Software (use function call)
5. Immediate (does not wait for a trigger). Default.
Modes
1. Single
—
2. Continuous
3. Stepped
4. Burst
Edge Detection Rising
—
—
Minimum
25 ns. Refer to ts1 at NI Signal Generators Help»Devices»
NI 5412»NI <bus>-5412»Triggering»Trigger Timing.
Pulse Width
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Table 7. (Continued)
Specification
Value
Comments
Delay from
Start Trigger to
CH 0 Analog
Output
Interpolation Factor
Typical Delay
Refer to ts2 at
NI Signal
Generators
Help»Devices»
NI 5412»
NI <bus>-5412»
Triggering»
Trigger Timing.
Digital Interpolation Filter
disabled.
43 Sample Clock
Periods + 110 ns
2
4
8
57 Sample Clock
Periods + 110 ns
63 Sample Clock
Periods + 110 ns
64 Sample Clock
Periods + 110 ns
Trigger Exporting
Exported
Trigger
Destinations
A signal used as a trigger can be routed out to any
destination listed in the Destinations specification
of Table 8.
—
—
—
Exported
Trigger Delay
65 ns (typical). Refer to ts3 at NI Signal Generators Help»
Devices»NI 5412»NI <bus>-5412»Triggering»Trigger
Timing.
Exported
Trigger Pulse
Width
>150 ns. Refer to ts4 at NI Signal Generators Help»
Devices»NI 5412»NI <bus>-5412»Triggering»Trigger
Timing.
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Markers
Table 8.
Specification
Value
Comments
Destinations
1. PFI<0..1> (SMB front panel connectors)
—
2. NI PXI-5412—PXI_Trig<0..6> (backplane connector)
NI PCI-5412—RTSI<0..6>
Quantity
Quantum
One Marker per Segment.
—
—
Marker position must be placed at an integer multiple of
four samples.
Width
Skew
>150 ns. Refer to tm2 at NI Signal Generators Help»
Devices»NI 5412»NI <bus>-5412»Waveform
Generation»Marker Events.
—
With Respect to Analog
Refer to tm1 at
NI Signal
Generators
Help»Devices»
NI 5412»
NI <bus>-5412»
Waveform
Destination
PFI<0..1>
Output
2 Sample Clock Periods
2 Sample Clock Periods
NI PXI-5412
PXI_Trig<0..6>
NI PCI-5412 RTSI<0..6>
Generation»
Marker Events.
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Waveform and Instruction Memory Utilization
Table 9.
Specification
Value
Comments
Memory Usage The NI 5412 uses the Synchronization and Memory Core
(SMC) technology in which waveforms and instructions
share onboard memory. Parameters, such as number of
segments in sequence list, maximum number of waveforms
in memory, and number of samples available for waveform
storage, are flexible and user defined.
—
Onboard
Memory Size
8 MB standard:
8,388,608 bytes
32 MB option:
33,554,432 bytes 268,435,456 bytes
256 MB option:
—
Output Modes
Arbitrary Waveform mode and Arbitrary Sequence mode
—
—
Arbitrary
Waveform
Mode
In Arbitrary Waveform mode, a single waveform is selected
from the set of waveforms stored in onboard memory and
generated.
Arbitrary
Sequence
Mode
In Arbitrary Sequence mode, a sequence directs the NI 5412
to generate a set of waveforms in a specific order. Elements
of the sequence are referred to as segments. Each segment is
associated with a set of instructions. The instructions
identify which waveform is selected from the set of
waveforms in memory, how many loops (iterations) of the
waveform are generated, and at which sample in the
waveform a marker output signal is sent.
—
Minimum
WaveformSize
(Samples)
Arbitrary
Waveform Mode
Arbitrary
Sequence Mode
The Minimum
Waveform Size
is sample rate
dependent in
Arbitrary
Trigger Mode
Single
16
16
16
Continuous
96 @ >50 MS/s
32 @ ≤50 MS/s
96 @ >50 MS/s
32 @ ≤50 MS/s
512 @ >50 MS/s
256 @ ≤50 MS/s
Sequence Mode.
Stepped
Burst
32
16
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Table 9. (Continued)
Specification
Value
Comments
Loop Count
1 to 16,777,215.
—
Burst trigger: Unlimited
Quantum
Waveform size must be an integer multiple of four samples.
—
Memory Limits
8 MB Standard
32 MB Option
256 MB Option
All trigger modes
except where
noted.
Arbitrary
Waveform
Mode,
Maximum
Waveform
Memory
4,194,176
Samples
16,777,088
Samples
134,217,600
Samples
Arbitrary
Sequence
Mode,
4,194,120
Samples
16,777,008
Samples
134,217,520
Samples
Condition: One
or two segments
in a sequence.
Maximum
Waveform
Memory
Arbitrary
Sequence
Mode,
65,000
Burst trigger:
8,000
262,000
Burst trigger:
32,000
2,097,000
Burst trigger:
262,000
Condition: One
or two segments
in a sequence.
Maximum
Waveforms
Arbitrary
Sequence
Mode,
104,000
Burst trigger:
65,000
418,000
Burst trigger:
262,000
3,354,000
Burst trigger:
2,090,000
Condition:
Waveform
memory is
Maximum
Segments in a
Sequence
<4,000 samples.
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Calibration
Table 10.
Specification
Value
Comments
Self-Calibration An onboard, 24-bit ADC and precision voltage reference are
used to calibrate the DC gain and offset. The self-calibration
is initiated by the user through the software and takes
approximately 75 seconds to complete.
—
External
Calibration
The External Calibration calibrates the VCXO, voltage
reference, DC gain, and offset. Appropriate constants are
stored in nonvolatile memory.
—
Calibration
Interval
Specifications valid within 2 years of External Calibration.
—
—
Warm-up Time 15 minutes
Power
Table 11.
Overload Operation
26 W
Specification
Normal Operation
22 W
Comments
Total Power
Typical.
Overload
operation occurs
when CH 0 is
shorted to
ground.
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Software
Table 12.
Specification
Value
Comments
Driver
Software
NI-FGEN 2.3 or later version. NI-FGEN is an
IVI-compliant driver that allows you to configure, control,
and calibrate the NI 5412. NI-FGEN provides application
programming interfaces for many development
environments.
—
Application
Software
NI-FGEN provides programming interfaces for the
following application development environments:
—
•
•
•
•
•
•
LabVIEW
LabWindows™/CVI™
Measurement Studio
Microsoft Visual C++ .NET
Microsoft Visual C/C++
Microsoft Visual Basic
Soft Front
Panel/
Interactive
Configuration
The FGEN Soft Front Panel 2.3 or later supports interactive
control of the NI 5412. The FGEN Soft Front Panel is
included on the NI-FGEN driver CD.
—
Measurement & Automation Explorer (MAX) also provides
interactive configuration and test tools for the NI 5412.
MAX is also included on the NI-FGEN CD.
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Environment
NI PXI-5412 Environment
Note To ensure that the NI PXI-5412 cools effectively, follow the guidelines in the
Maintain Forced-Air Cooling Note to Users included in the NI 5412 kit. The NI PXI-5412
is intended for indoor use only.
Table 13.
Specifications
Value
Comments
Operating
0 ºC to +55 ºC in all NI PXI chassis except the following:
—
Temperature
0 ºC to +45 ºC when installed in an NI PXI-101x or
NI PXI-1000B chassis.
Meets IEC-60068-2-1 and IEC-60068-2-2.
Storage
Temperature
–25 ºC to +85 ºC. Meets IEC-60068-2-1 and
IEC-60068-2-2.
—
—
Operating
Relative
10% to 90%, noncondensing. Meets IEC-60068-2-56.
Humidity
Storage
5% to 95%, noncondensing. Meets IEC-60068-2-56.
—
Relative
Humidity
Operating
Shock
30 g, half-sine, 11 ms pulse. Meets IEC-60068-2-27. Test
profile developed in accordance with MIL-PRF-28800F.
Spectral and jitter
specifications
could degrade.
Storage Shock
50 g, half-sine, 11 ms pulse. Meets IEC-60068-2-27. Test
profile developed in accordance with MIL-PRF-28800F.
—
Operating
Vibration
5 Hz to 500 Hz, 0.31 grms. Meets IEC-60068-2-64.
Spectral and jitter
specifications
could degrade.
Storage
Vibration
5 Hz to 500 Hz, 2.46 grms. Meets IEC-60068-2-64. Test
profile exceeds requirements of MIL-PRF-28800F, Class B.
—
Altitude
2,000 m maximum (at 25 °C ambient temperature)
2
—
—
Pollution
Degree
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NI PCI-5412 Environment
Note To ensure that the NI PCI-5412 cools effectively, follow the guidelines in the
Maintain Forced-Air Cooling Note to Users included in the NI 5412 kit. Also, to maximize
airflow and extend the life of the device, leave any adjacent PCI slots empty. The
NI PCI-5412 is intended for indoor use only.
Table 14.
Specifications
Value
Comments
Operating
0 ºC to +45 ºC. Meets IEC-60068-2-1 and IEC-60068-2-2.
—
Temperature
Storage
Temperature
–25 ºC to +85 ºC. Meets IEC-60068-2-1 and
IEC-60068-2-2.
—
—
Operating
Relative
10% to 90%, noncondensing. Meets IEC-60068-2-56.
Humidity
Storage
5% to 95%, noncondensing. Meets IEC-60068-2-56.
—
Relative
Humidity
Storage
Shock
50 g, half-sine, 11 ms pulse. Meets IEC-60068-2-27. Test
profile developed in accordance with MIL-PRF-28800F.
—
—
Storage
Vibration
5 Hz to 500 Hz, 2.46 grms. Meets IEC-60068-2-64. Test
profile exceeds requirements of MIL-PRF-28800F, Class B.
Altitude
2,000 m maximum (at 25 °C ambient temperature)
2
—
—
Pollution
Degree
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Safety, Electromagnetic Compatibility, and
CE Compliance
Table 15.
Specification
Safety
Value
Comments
The NI 5412 meets the requirements of the following For UL and
standards for safety and electrical equipment for
measurement, control, and laboratory use:
other safety
certifications,
refer to the
product label or
to ni.com/
certification,
search by model
number or
•
•
•
IEC 61010-1, EN 61010-1
UL 61010-1
CAN/CSA C22.2 No. 61010-1
product line,
and click the
appropriate
link in the
Certification
column.
Emissions
Immunity
EN 55011 Class A at 10 m
FCC Part 15A above 1 GHz
—
EN 61326:1997 + A2:2001, Table 1
—
Up to 4 mVpp noise (about –44 dBm) may be present
on the output during the conducted immunity test. Use
of the product at levels below –44 dBm will result in
self-recoverable errors.
Good screening (shielding) techniques must be
employed throughout the user’s data acquisition
system.
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Table 15. (Continued)
Specification
EMC/EMI
Value
CE, C-Tick, and FCC Part 15 (Class A) Compliant
Notes:
Comments
—
1. This device is not intended for, and is restricted
from, use in residential areas.
2. For EMC compliance, operate this device with
shielded cabling.
3. When connected to other test objects, this product
may cause radio interference. If this occurs, you
may be required to take adequate measures to
reduce the interference.
This product meets the essential requirements of applicable European Directives as amended for
CE marking, as follows:
Low-Voltage
73/23/EEC
—
Directive (safety)
Electromagnetic
Compatibility
89/336/EEC
—
Directive (EMC)
Note: Refer to the Declaration of Conformity (DoC) for this product for any additional regulatory
compliance information. To obtain the DoC for this product, visit ni.com/certification,
search by model number or product line, and click the appropriate link in the Certification column.
© National Instruments Corporation
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NI 5412 Specifications
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Physical
Table 16.
Specification
Value
Comments
NI PXI-5412
NI PCI-5412
Dimensions
—
Single 3U PXI slot.
CompactPCI compatible.
34.07 × 10.67 × 2.03 cm
(13.4 × 4.20 × 0.8 inches)
2.0 × 13.0 × 21.6 cm
(0.8 × 5.1 × 8.5 inches)
Weight
340 g
(11 oz)
480 g
(17 oz)
—
—
Front Panel Connectors
Label
Function(s)
Analog Output
Connector Type
SMB (jack)
CH 0
CLK IN
Sample clock input and PLL SMB (jack)
reference clock input.
PFI 0
PFI 1
Markeroutput, triggerinput, SMB (jack)
sample clock output,
exported trigger output, and
PLL reference clock output.
Markeroutput, triggerinput, SMB (jack)
sample clock output,
exported trigger output, and
PLL reference clock output.
NI PXI-5412 Only—Front Panel LED Indicators
Label Function
For more
information, refer
to the NI Signal
Generators Help.
ACCESS LED The ACCESS LED indicates the status of the PCI bus and
the interface from the NI 5412 to the controller.
ACTIVE LED The ACTIVE LED indicates the status of the onboard
generation hardware of the NI 5412.
Included Cable
1 (NI part number 763541-01), 50 Ω, BNC Male to SMB
Plug, RG223/U, Double Shielded, 1 m cable.
—
NI 5412 Specifications
24
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Where to Go for Support
The National Instruments Web site is your complete resource for technical
support. At ni.com/support you have access to everything from
troubleshooting and application development self-help resources to email
and phone assistance from NI Application Engineers.
A Declaration of Conformity (DoC) is our claim of compliance with the
Council of the European Communities using the manufacturer’s
declaration of conformity. This system affords the user protection for
electronic compatibility (EMC) and product safety. You can obtain the DoC
for your product by visiting ni.com/certification. If your product
supports calibration, you can obtain the calibration certificate for your
product at ni.com/calibration.
National Instruments corporate headquarters is located at
11500 North Mopac Expressway, Austin, Texas, 78759-3504.
National Instruments also has offices located around the world to help
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Thailand 662 992 7519, United Kingdom 44 0 1635 523545
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National Instruments, NI, ni.com, and LabVIEW are trademarks of National Instruments Corporation.
Refer to the Terms of Use section on ni.com/legal for more information about National
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© 2004 National Instruments Corporation. All rights reserved.
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