National Instruments Network Card PCI 6023E User Manual

DAQ

PCI-6023E/6024E/6025E

User Manual

Multifunction I/O Boards for

PCI Bus Computers

PCI-6023E/6024E/6025E User Manual

October 1998 Edition

Part Number 322072A-01

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Important Information

Warranty

The PCI-6023E, PCI-6024E, and PCI-6025E boards are warranted against defects in materials and workmanship for a

period of one year from the date of shipment, as evidenced by receipts or other documentation. National Instruments will,

at its option, repair or replace equipment that proves to be defective during the warranty period. This warranty includes

parts and labor.

The media on which you receive National Instruments software are warranted not to fail to execute programming

instructions, due to defects in materials and workmanship, for a period of 90 days from date of shipment, as evidenced

by receipts or other documentation. National Instruments will, at its option, repair or replace software media that do not

execute programming instructions if National Instruments receives notice of such defects during the warranty period.

National Instruments does not warrant that the operation of the software shall be uninterrupted or error free.

A Return Material Authorization (RMA) number must be obtained from the factory and clearly marked on the outside

of the package before any equipment will be accepted for warranty work. National Instruments will pay the shipping costs

of returning to the owner parts which are covered by warranty.

National Instruments believes that the information in this manual is accurate. The document has been carefully reviewed

for technical accuracy. In the event that technical or typographical errors exist, National Instruments reserves the right to

make changes to subsequent editions of this document without prior notice to holders of this edition. The reader should

consult National Instruments if errors are suspected. In no event shall National Instruments be liable for any damages

arising out of or related to this document or the information contained in it.

E^{XCEPT AS SPECIFIED HEREIN}, N^ATIONALI^{NSTRUMENTS MAKES NO WARRANTIES}, ^{EXPRESS OR IMPLIED}, ^{AND SPECIFICALLY DISCLAIMS}

^{ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE}. C^USTOMER’^{S RIGHT TO RECOVER DAMAGES CAUSED}

^{BY FAULT OR NEGLIGENCE ON THE PART OF}N^ATIONALI^{NSTRUMENTS SHALL BE LIMITED TO THE AMOUNT THERETOFORE PAID BY THE}

^CUSTOMER. N^ATIONALI^{NSTRUMENTS WILL NOT BE LIABLE FOR DAMAGES RESULTING FROM LOSS OF DATA}, ^PROFITS, ^{USE OF PRODUCTS},

^{OR INCIDENTAL OR CONSEQUENTIAL DAMAGES}, ^{EVEN IF ADVISED OF THE POSSIBILITY THEREOF}. This limitation of the liability of

National Instruments will apply regardless of the form of action, whether in contract or tort, including negligence.

Any action against National Instruments must be brought within one year after the cause of action accrues. National

Instruments shall not be liable for any delay in performance due to causes beyond its reasonable control. The warranty

provided herein does not cover damages, defects, malfunctions, or service failures caused by owner’s failure to follow

the National Instruments installation, operation, or maintenance instructions; owner’s modification of the product;

owner’s abuse, misuse, or negligent acts; and power failure or surges, fire, flood, accident, actions of third parties,

or other events outside reasonable control.

Under the copyright laws, this publication may not be reproduced or transmitted in any form, electronic or mechanical,

including photocopying, recording, storing in an information retrieval system, or translating, in whole or in part, without

the prior written consent of National Instruments Corporation.

Trademarks

ComponentWorks^™, CVI^™, DAQ-STC^™, LabVIEW^™, Measure^™, Mite^™, NI-DAQ^™, NI-PGIA^™, RTSI^™, SCXI^™, and

VirtualBench^™are trademarks of National Instruments Corporation.

Product and company names listed are trademarks or trade names of their respective companies.

WARNING REGARDING MEDICAL AND CLINICAL USE OF NATIONAL INSTRUMENTS PRODUCTS

National Instruments products are not designed with components and testing intended to ensure a level of reliability

suitable for use in treatment and diagnosis of humans. Applications of National Instruments products involving medical

or clinical treatment can create a potential for accidental injury caused by product failure, or by errors on the part of the

user or application designer. Any use or application of National Instruments products for or involving medical or clinical

treatment must be performed by properly trained and qualified medical personnel, and all traditional medical safeguards,

equipment, and procedures that are appropriate in the particular situation to prevent serious injury or death should always

continue to be used when National Instruments products are being used. National Instruments products are NOT intended

to be a substitute for any form of established process, procedure, or equipment used to monitor or safeguard human health

and safety in medical or clinical treatment.

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Contents

About This Manual

Organization of This Manua l .........................................................................................xi

Conventions Used in This Manual.................................................................................xii

National Instruments Documentation ............................................................................xiii

Customer Communication .............................................................................................xiv

Chapter 1

Introduction

Features of the PCI-6023E, PCI-6024E, and PCI-6025 E ..............................................1-1

What You Need to Get Started ......................................................................................1-2

Unpacking...................................................................................................................... 1-2

Software Programming Choices ....................................................................................1-3

National Instruments Application Software....................................................1-3

NI-DAQ Driver Software................................................................................1-3

Optional Equipmen t .......................................................................................................1-6

Chapter 2

Installation and Configuration

Software Installation......................................................................................................2-1

Hardware Configuration ................................................................................................2-1

Hardware Installation.....................................................................................................2-2

Chapter 3

Hardware Overview

Analog Input ..................................................................................................................3-2

Input Mode ......................................................................................................3-2

Input Range .....................................................................................................3-2

Dither...............................................................................................................3-3

Multichannel Scanning Considerations...........................................................3-4

Analog Output................................................................................................................3-5

Analog Output Glitch ......................................................................................3-5

Digital I/O......................................................................................................................3-6

Timing Signal Routing...................................................................................................3-6

Programmable Function Inputs .......................................................................3-7

Board and RTSI Clocks...................................................................................3-8

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RTSI Triggers ................................................................................................. 3-8

Chapter 4

Signal Connections

I/O Connecto r ................................................................................................................ 4-1

Analog Input Signal Overvie w ...................................................................................... 4-8

Types of Signal Sources.................................................................................. 4-8

Floating Signal Sources.................................................................... 4-9

Ground-Referenced Signal Sources.................................................. 4-9

Analog Input Modes........................................................................................ 4-9

Analog Input Signal Connections.................................................................................. 4-11

Differential Connection Considerations (DIFF Input Configuration) ............ 4-13

Differential Connections for Ground-Referenced Signal Sources ... 4-14

Differential Connections for Nonreferenced or

Floating Signal Sources ................................................................. 4-15

Single-Ended Connection Considerations ...................................................... 4-17

Single-Ended Connections for Floating Signal Sources

(RSE Configuration )...................................................................... 4-18

Single-Ended Connections for Grounded Signal Sources

(NRSE Configuration )................................................................... 4-18

Common-Mode Signal Rejection Considerations........................................... 4-19

Analog Output Signal Connection s ............................................................................... 4-20

Digital I/O Signal Connections ..................................................................................... 4-21

All Boards ....................................................................................................... 4-21

PCI-6025E Only.............................................................................................. 4-22

Port C Pin Assignments................................................................................................. 4-23

Digital I/O Power-up State ............................................................................................ 4-24

Changing DIO Power-up State to Pulled Low................................................ 4-24

Timing Specifications.................................................................................................... 4-25

Mode 1 Input Timing ...................................................................................... 4-27

Mode 1 Output Timing ................................................................................... 4-28

Mode 2 Bidirectional Timing.......................................................................... 4-29

Power Connections........................................................................................................ 4-30

Timing Connections ...................................................................................................... 4-30

Programmable Function Input Connections ................................................... 4-31

DAQ Timing Connections .............................................................................. 4-32

SCANCLK Signal ............................................................................ 4-33

EXTSTROBE* Signal...................................................................... 4-33

TRIG1 Signal.................................................................................... 4-34

TRIG2 Signal.................................................................................... 4-35

STARTSCAN Signal........................................................................ 4-36

CONVERT* Signal .......................................................................... 4-38

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AIGATE Signal.................................................................................4-39

SISOURCE Signal ............................................................................4-40

Waveform Generation Timing Connections ...................................................4-40

WFTRIG Signal ................................................................................4-40

UPDATE* Signal..............................................................................4-41

UISOURCE Signal ...........................................................................4-42

General-Purpose Timing Signal Connections .................................................4-43

GPCTR0_SOURCE Signal...............................................................4-43

GPCTR0_GATE Signa l ....................................................................4-44

GPCTR0_OUT Signal ......................................................................4-45

GPCTR0_UP_DOWN Signa l ...........................................................4-45

GPCTR1_SOURCE Signal...............................................................4-46

GPCTR1_GATE Signa l ....................................................................4-46

GPCTR1_OUT Signal ......................................................................4-47

GPCTR1_UP_DOWN Signal...........................................................4-47

FREQ_OUT Signa l ...........................................................................4-49

Field Wiring Consideration s ..........................................................................................4-49

Chapter 5

Calibration

Loading Calibration Constants ......................................................................................5-1

Self-Calibration..............................................................................................................5-2

External Calibration.......................................................................................................5-2

Other Considerations .....................................................................................................5-3

Appendix A

Specifications

Appendix B

Custom Cabling and Optional Connectors

Appendix C

Common Questions

Appendix D

Customer Communication

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Contents

Glossary

Index

Figures

Figure 1-1.

The Relationship between the Programming Environment,

NI-DAQ, and Your Hardware............................................................... 1-5

PCI-6023E, PCI-6024E, and PCI-6025E Block Diagram .................... 3-1

Dither .................................................................................................... 3-4

CONVERT* Signal Routing................................................................. 3-7

RTSI Bus Signal Connectio n ................................................................ 3-9

Figure 4-1.

Figure 4-2.

Figure 4-7.

I/O Connector Pin Assignment for the PCI-6023E/PCI-6024E ........... 4-2

I/O Connector Pin Assignment for the PCI-6025E............................... 4-3

Programmable Gain Instrumentation Amplifier (PGIA) ...................... 4-10

Summary of Analog Input Connections ............................................... 4-12

Differential Input Connections for Ground-Referenced Signals .......... 4-14

Differential Input Connections for Nonreferenced Signals .................. 4-15

Single-Ended Input Connections for Nonreferenced or

Floating Signals .................................................................................... 4-18

Single-Ended Input Connections for Ground-Referenced Signals ....... 4-19

Analog Output Connections.................................................................. 4-20

Figure 4-8.

Figure 4-9.

Figure 4-10. Digital I/O Connections ........................................................................ 4-21

Figure 4-11. Digital I/O Connections Block Diagram............................................... 4-22

Figure 4-12. DIO Channel Configured for High DIO Power-up State

with External Load............................................................................... 4-24

Figure 4-13. Timing Specifications for Mode 1 Input Transfer ................................ 4-27

Figure 4-14. Timing Specifications for Mode 1 Output Transfer ............................. 4-28

Figure 4-15. Timing Specifications for Mode 2 Bidirectional Transfer.................... 4-29

Figure 4-16. Timing I/O Connections ....................................................................... 4-31

Figure 4-17. Typical Posttriggered Acquisition ........................................................ 4-32

Figure 4-18. Typical Pretriggered Acquisition.......................................................... 4-33

Figure 4-19. SCANCLK Signal Timing.................................................................... 4-33

Figure 4-20. EXTSTROBE* Signal Timing ............................................................. 4-34

Figure 4-21. TRIG1 Input Signal Timing.................................................................. 4-34

Figure 4-22. TRIG1 Output Signal Timing ............................................................... 4-35

Figure 4-23. TRIG2 Input Signal Timing.................................................................. 4-36

Figure 4-24. TRIG2 Output Signal Timing ............................................................... 4-36

Figure 4-25. STARTSCAN Input Signal Timing...................................................... 4-37

Figure 4-26. STARTSCAN Output Signal Timing ................................................... 4-37

Figure 4-27. CONVERT* Input Signal Timing ........................................................ 4-38

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Contents

Figure 4-28. CONVERT* Output Signal Timin g ......................................................4-39

Figure 4-29. SISOURCE Signal Timing....................................................................4-40

Figure 4-30. WFTRIG Input Signal Timing ..............................................................4-41

Figure 4-31. WFTRIG Output Signal Timing............................................................4-41

Figure 4-32. UPDATE* Input Signal Timing............................................................4-42

Figure 4-33. UPDATE* Output Signal Timing .........................................................4-42

Figure 4-34. UISOURCE Signal Timing...................................................................4-43

Figure 4-35. GPCTR0_SOURCE Signal Timing ......................................................4-44

Figure 4-36. GPCTR0_GATE Signal Timing in Edge-Detection Mode...................4-45

Figure 4-37. GPCTR0_OUT Signal Timin g ..............................................................4-45

Figure 4-38. GPCTR1_SOURCE Signal Timing ......................................................4-46

Figure 4-39. GPCTR1_GATE Signal Timing in Edge-Detection Mod e ...................4-47

Figure 4-40. GPCTR1_OUT Signal Timin g ..............................................................4-47

Figure 4-41. GPCTR Timing Summary.....................................................................4-48

Figure B-1.

Figure B-2.

Figure B-3.

Figure B-4.

68-Pin E Series Connector Pin Assignments ........................................B-3

68-Pin Extended Digital Input Connector Pin Assignment s .................B-4

50-Pin E Series Connector Pin Assignments ........................................B-5

50-Pin Extended Digital Input Connector Pin Assignment s .................B-6

Tables

Table 3-1.

Table 3-2.

Available Input Configuration s .............................................................3-2

Measurement Precision .........................................................................3-3

Table 4-1.

Table 4-2.

Table 4-3.

Table 4-4.

I/O Connector Signal Descriptions .......................................................4-4

I/O Signal Summary .............................................................................4-7

Port C Signal Assignments ...................................................................4-23

Signal Names Used in Timing Diagrams .............................................4-25

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About This Manual

The PCI E Series boards are high-performance multifunction analog,

digital, and timing I/O boards for PCI bus computers. Supported functions

include analog input, analog output, digital I/O, and timing I/O.

This manual describes the electrical and mechanical aspects of the

PCI-6023E, PCI-6024E, and PCI-6025E boards from the PCI E Series

product line and contains information concerning their operation and

programming.

Organization of This Manual

The PCI-6023E/6024E/6025E User Manual is organized as follows:

•

Chapter 1, Introduction , describes the boards, lists what you need to

get started, gives unpacking instructions, and describes the optional

software and equipmen t.

•

Chapter 2, Installation and Configuration, explains how to install and

configure your board.

Chapter 3, Hardware Overview, presents an overview of the hardware

functions on your board.

Chapter 4, Signal Connections, describes how to make input and

output signal connections to your board via the I/O connector.

Chapter 5, Calibration, discusses the calibration procedures for your

board.

Appendix A, Specifications, lists the specifications of the PCI-6023E,

PCI-6024E, and PCI-6025E boards.

Appendix B, Custom Cabling and Optional Connectors, describes the

various cabling and connector options.

Appendix C, Common Questions, contains a list of commonly asked

questions and their answers relating to usage and special features of

your board.

•

Appendix D, Customer Communication, contains forms you can use to

request help from National Instruments or to comment on our products

and manuals.

The Glossary contains an alphabetical list and description of terms

used in this manual, including abbreviations, acronyms, metric

prefixes, mnemonics, and symbols.

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About This Manual

•

The Index contains an alphabetical list of key terms and topics in this

manual, including the page where you can find each one.

Conventions Used in This Manual

The following conventions are used in this manual:

Angle brackets enclose the name of a key on the keyboard—for example,

<shift>. Angle brackets containing numbers separated by an ellipsis

represent a range of values associated with a bit or signal name—for

example, DBIO<3..0>.

♦

The ♦ symbol indicates that the text following it applies only to a specific

product, a specific operating system, or a specific software version.

This icon to the left of bold italicized text denotes a note, which alerts you

to important information.

This icon to the left of bold italicized text denotes a caution, which advises

you of precautions to take to avoid injury, data loss, or a system crash.

bold

Bold text denotes the names of menus, menu items, parameters, dialog

boxes, dialog box buttons or options, icons, windows, Windows 95 tabs,

or LEDs.

bold italic

Bold italic text denotes an activity objective, note, caution, or warning.

italic

Italic text denotes variables, emphasis, a cross reference, or an introduction

to a key concept. This font also denotes text from which you supply the

appropriate word or value, as in Windows 3.x.

monospace

Text in this font denotes text or characters that you should literally enter

from the keyboard, sections of code, programming examples, and syntax

examples. This font is also used for the proper names of disk drives, paths,

directories, programs, subprograms, subroutines, device names, functions,

operations, variables, filenames and extensions, and for statements and

comments taken from programs.

NI-DAQ

NI-DAQ refers to the NI-DAQ driver software for PC compatible

computers unless otherwise noted.

Refers to all PC AT series computers with PCI bus unless otherwise noted.

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About This Manual

SCXI

SCXI stands for Signal Conditioning eXtensions for Instrumentation and is

a National Instruments product line designed to perform front-end signal

conditioning for National Instruments plug-in DAQ boards.

National Instruments Documentation

The PCI-6023E/6024E/6025E User Manual is one piece of the

documentation set for your DAQ system. You could have any of several

types of manuals depending on the hardware and software in your system.

Use the manuals you have as follows:

•

Getting Started with SCXI—If you are using SCXI, this is the first

manual you should read. It gives an overview of the SCXI system and

contains the most commonly needed information for the modules,

chassis, and software.

Your SCXI hardware user manuals—If you are using SCXI, read these

manuals next for detailed information about signal connections and

module configuration. They also explain in greater detail how the

module works and contain application hints.

•

SCXI Chassis Manual—If you are using SCXI, read this manual for

maintenance information on the chassis and installation instructions.

Your DAQ hardware documentation—This documentation has

detailed information about the DAQ hardware that plugs into or is

connected to your computer. Use this documentation for hardware

installation and configuration instructions, specification information

about your DAQ hardware, and application hints.

•

Software documentation—You may have both application software

and NI-DAQ software documentation. National Instruments

application software includes ComponentWorks, LabVIEW,

LabWindows/CVI, Measure, and VirtualBench. After you set up your

hardware system, use either your application software documentation

or the NI-DAQ documentation to help you write your application. If

you have a large, complicated system, it is worthwhile to look through

the software documentation before you configure your hardware.

•

Accessory installation guides or manuals—If you are using accessory

products, read the terminal block and cable assembly installation

guides. They explain how to physically connect the relevant pieces of

the system. Consult these guides when you are making your

connections.

xiii

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About This Manual

Related Documentation

The following documents contain information you may find helpful:

•

DAQ-STC Technical Reference Manual

•

National Instruments Application Note 025, Field Wiring and Noise

Considerations for Analog Signals

•

PCI Local Bus Specification Revision 2.1

The following National Instruments manual contains detailed information

for the register-level programmer:

•

PCI E Series Register-Level Programmer Manual

This manual is available from National Instruments by request. You

should not need the register-level programmer manual if you are using

National Instruments driver or application software. Using NI-DAQ,

ComponentWorks, LabVIEW, LabWindows/CVI, Measure, or

VirtualBench software is easier than the low-level programming

described in the register-level programmer manual.

Customer Communication

National Instruments wants to receive your comments on our products

and manuals. We are interested in the applications you develop with our

products, and we want to help if you have problems with them. To make it

easy for you to contact us, this manual contains comment and configuration

forms for you to complete. These forms are in Appendix D, Customer

Communication, at the end of this manual.

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Introduction

This chapter describes the PCI-6023E, PCI-6024E, and PCI-6025E boards,

lists what you need to get started, gives unpacking instructions, and

describes the optional software and equipment.

Features of the PCI-6023E, PCI-6024E, and PCI-6025E

Thank you for buying a National Instruments PCI-6023E, PCI-6024E, or

PCI-6025E board. The PCI-6025E features 16 channels (eight differential)

of analog input, two channels of analog output, a 100-pin connector, and

32 lines of digital I/O. The PCI-6024E features 16 channels of analog

input, two channels of analog output, a 68-pin connector and eight lines of

digital I/O. The PCI-6023E is identical to the PCI-6024E, except that it

does not have analog output channels.

These boards use the National Instruments DAQ-STC system timing

controller for time-related functions. The DAQ-STC consists of three

timing groups that control analog input, analog output, and general-purpose

counter/timer functions. These groups include a total of seven 24-bit and

three 16-bit counters and a maximum timing resolution of 50 ns. The

DAQ-STC makes possible such applications as buffered pulse generation,

equivalent time sampling, and seamless changing of the sampling rate.

With other DAQ boards, you cannot easily synchronize several

measurement functions to a common trigger or timing event. These boards

have the Real-Time System Integration (RTSI) bus to solve this problem.

The RTSI bus consists of the National Instruments RTSI bus interface and

a ribbon cable to route timing and trigger signals between several functions

on as many as five DAQ boards in your computer.

These boards can interface to an SCXI system—the instrumentation front

end for plug-in DAQ boards—so that you can acquire analog signals from

thermocouples, RTDs, strain gauges, voltage sources, and current sources.

You can also acquire or generate digital signals for communication and

control.

1-1

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Chapter 1

Introduction

What You Need to Get Started

To set up and use your board, you will need the following:

❑ One of the following boards:

PCI-6023E

PCI-6024E

PCI-6025E

❑ PCI-6023E/6024E/6025E User Manual

❑ One of the following software packages and documentation:

ComponentWorks

LabVIEW for Windows

LabWindows/CVI for Windows

Measure

NI-DAQ for PC Compatibles

VirtualBench

❑ Your computer

Note

Read Chapter 2, Installation and Configuration, before installing your board.

Always install your software before installing your board.

Unpacking

Your board is shipped in an antistatic package to prevent electrostatic

damage to the board. Electrostatic discharge can damage several

components on the board. To avoid such damage in handling the board,

take the following precautions:

•

Ground yourself via a grounding strap or by holding a grounded object.

Touch the antistatic package to a metal part of your computer chassis

before removing the board from the package.

•

Remove the board from the package and inspect the board for

loose components or any other sign of damage.

Notify National Instruments if the board appears damaged in any way.

Do not install a damaged board into your computer.

Never touch the exposed pins of connectors.

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Chapter 1

Introduction

Software Programming Choices

You have several options to choose from when programming your National

Instruments DAQ and SCXI hardware. You can use National Instruments

application software, NI-DAQ, or register-level programming.

National Instruments Application Software

ComponentWorks contains tools for data acquisition and instrument

control built on NI-DAQ driver software. ComponentWorks provides

a higher-level programming interface for building virtual instruments

through standard OLE controls and DLLs. With ComponentWorks, you

can use all of the configuration tools, resource management utilities, and

interactive control utilities included with NI-DAQ.

LabVIEW features interactive graphics, a state-of-the-art user interface,

and a powerful graphical programming language. The LabVIEW Data

Acquisition VI Library, a series of VIs for using LabVIEW with National

Instruments DAQ hardware, is included with LabVIEW. The LabVIEW

Data Acquisition VI Library is functionally equivalent to NI-DAQ

software.

LabWindows/CVI features interactive graphics, state-of-the-art user

interface, and uses the ANSI standard C programming language. The

LabWindows/CVI Data Acquisition Library, a series of functions for using

LabWindows/CVI with National Instruments DAQ hardware, is included

with the NI-DAQ software kit. The LabWindows/CVI Data Acquisition

Library is functionally equivalent to the NI-DAQ software.

VirtualBench features virtual instruments that combine DAQ products,

software, and your computer to create a stand-alone instrument with the

added benefit of the processing, display, and storage capabilities of your

computer. VirtualBench instruments load and save waveform data to disk

in the same forms that can be used in popular spreadsheet programs and

word processors.

Using ComponentWorks, LabVIEW, LabWindows/CVI, or VirtualBench

software will greatly reduce the development time for your data acquisition

and control application.

NI-DAQ Driver Software

The NI-DAQ driver software is included at no charge with all National

Instruments DAQ hardware. NI-DAQ is not packaged with SCXI or

1-3

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Chapter 1

Introduction

accessory products, except for the SCXI-1200. NI-DAQ has an extensive

library of functions that you can call from your application programming

environment. These functions include routines for analog input (A/D

conversion), buffered data acquisition (high-speed A/D conversion),

analog output (D/A conversion), waveform generation (timed D/A

conversion), digital I/O, counter/timer operations, SCXI, RTSI,

self-calibration, messaging, and acquiring data to extended memory.

NI-DAQ has both high-level DAQ I/O functions for maximum ease of use

and low-level DAQ I/O functions for maximum flexibility and

performance. Examples of high-level functions are streaming data to disk

or acquiring a certain number of data points. An example of a low-level

function is writing directly to registers on the DAQ device. NI-DAQ does

not sacrifice the performance of National Instruments DAQ devices

because it lets multiple devices operate at their peak.

NI-DAQ also internally addresses many of the complex issues between the

computer and the DAQ hardware such as programming interrupts and

DMA controllers. NI-DAQ maintains a consistent software interface

among its different versions so that you can change platforms with minimal

modifications to your code. Whether you are using conventional

programming languages or National Instruments application software, your

application uses the NI-DAQ driver software, as illustrated in Figure 1-1.

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Chapter 1

Introduction

ComponentWorks,

LabVIEW,

LabWindows/CVI, or

VirtualBench

Conventional

Programming Environment

NI-DAQ

Driver Software

Personal

Computer or

Workstation

DAQ or

SCXI Hardware

Figure 1-1. The Relationship between the Programming Environment,

NI-DAQ, and Your Hardware

The final option for programming any National Instruments DAQ

hardware is to write register-level software. Writing register-level

programming software can be very time-consuming and inefficient,

and is not recommended for most users.

Even if you are an experienced register-level programmer, using NI-DAQ

or application software to program your National Instruments DAQ

hardware is easier than, and as flexible as, register-level programming,

and can save weeks of development time.

1-5

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Chapter 1

Introduction

Optional Equipment

National Instruments offers a variety of products to use with your board,

including cables, connector blocks, and other accessories, as follows:

•

Cables and cable assemblies, shielded and ribbon

Connector blocks, shielded and unshielded screw terminals

Real Time System Integration bus cables

SCXI modules and accessories for isolating, amplifying, exciting, and

multiplexing signals for relays and analog output. With SCXI you can

condition and acquire up to 3,072 channels.

•

Low channel count signal conditioning modules, boards, and

accessories, including conditioning for strain gauges and RTDs,

simultaneous sample and hold, and relays

For more specific information about these products, refer to your National

Instruments catalogue or call the office nearest you.

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Installation and Configuration

This chapter explains how to install and configure your PCI-6023E,

PCI-6024E, or PCI-6025E board.

Software Installation

Install your software before you install your board. Refer to the appropriate

release notes indicated below for specific instructions on the software

installation sequence.

If you are using NI-DAQ, refer to your NI-DAQ release notes. Find

the installation section for your operating system and follow the

instructions given there.

If you are using LabVIEW, LabWindows/CVI, or other National

Instruments application software packages, refer to the appropriate release

notes. After you have installed your application software, refer to your

NI-DAQ release notes and follow the instructions given there for your

operating system and application software package.

If you are a register-level programmer, refer to the PCI E Series

Reference Manual for software configuration information.

Hardware Configuration

Due to the National Instruments standard architecture for data acquisition

and the PCI bus specification, the PCI E Series boards are completely

software-configurable. You must perform two types of configuration on the

PCI E Series boards—bus-related and data acquisition-related

configuration.

These boards are fully compatible with the industry-standard PCI Local

Bus Specification Revision 2.1. This specification lets the PCI system

automatically set the board base memory address and interrupt channel

with no user interaction.

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Installation and Configuration

You can modify data acquisition-related configuration settings, such as

analog input range and mode, through application level software. Refer to

Chapter 3, Hardware Overview, for more information about the various

settings available for your board. These settings are changed and

configured through software after you install your board.

Hardware Installation

Note

Install your software before you install your board.

After installing your software, you are ready to install your hardware. Your

board will fit in any 5 V PCI expansion slot in your computer. However, to

achieve best noise performance, leave as much room as possible between

your board and other devices. The following are general installation

instructions. Consult your computer user manual or technical reference

manual for specific instructions and warnings.

1. Write down your board’s serial number in the

PCI-6023E/6024E/6025E Hardware and Software

Configuration Form in Appendix D, Customer Communication, of

this manual.

2. Turn off and unplug your computer.

3. Remove the top cover of your computer.

4. Remove the expansion slot cover on the back panel of the computer.

5. Insert the board into a 5 V PCI slot. Gently rock the board to ease it

into place. It may be a tight fit, but do not force the board into place.

6. Screw the mounting bracket of the board to the back panel rail of the

computer.

7. Replace the top cover of your computer.

8. Plug in and turn on your computer.

The board is installed. You are now ready to configure your software. Refer

to your software documentation for configuration instructions.

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Hardware Overview

This chapter presents an overview of the hardware functions on your board.

Figure 3-1 shows a block diagram for the PCI-6023E, PCI-6024E, and

PCI-6025E.

Calibration

EEPROM

DACs

Voltage

REF

Control

(8)

Analog

Input

Muxes

Generic

Bus

Interface

PCI

Bus

Interface

Analog Mode

Multiplexer

MINI-

MITE

ADC

FIFO

A/D

Converter

PGIA

Data

Address/Data

Calibration

Mux

Dither

Generator

Configuration

Memory

AI Control

EEPROM

IRQ

DMA

DMA/

Interrupt

Request

Trigger

Interface

Analog Input

Timing/Control

PFI / Trigger

Analog

Input

Control

EEPROM

DMA

Control Interface

Bus

Interface

Counter/

Timing I/O

DAQ-STC

Bus

Interface

DAQ - STC

DAQ-

APE

Timing

I/O

Bus

Interface

Analog Output

Timing/Control

RTSI Bus

Interface

Digital I/O

AO Control

DAC0

DAC1

Calibration DACs

RTSI Connector

NOT ON 6023E

Analog Output

DIO (24)

DIO Control

82C55A

6025E Only

Figure 3-1. PCI-6023E, PCI-6024E, and PCI-6025E Block Diagram

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Chapter 3

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Analog Input

The analog input section of each board is software configurable. The

following sections describe in detail each of the analog input settings.

Input Mode

The boards have three different input modes—nonreferenced single-ended

(NRSE) input, referenced single-ended (RSE) input, and differential

(DIFF) input. The single-ended input configurations provide up to

16 channels. The DIFF input configuration provides up to eight channels.

Input modes are programmed on a per channel basis for multimode

scanning. For example, you can configure the circuitry to scan

12 channels—four differentially-configured channels and eight

single-ended channels. Table 3-1 describes the three input configurations.

Table 3-1. Available Input Configurations

Configuration

Description

DIFF

A channel configured in DIFF mode uses two analog

input lines. One line connects to the positive input of

the board’s programmable gain instrumentation

amplifier (PGIA), and the other connects to the

negative input of the PGIA.

RSE

A channel configured in RSE mode uses one analog

input line, which connects to the positive input of the

PGIA. The negative input of the PGIA is internally

tied to analog input ground (AIGND).

NRSE

A channel configured in NRSE mode uses one

analog input line, which connects to the positive

input of the PGIA. The negative input of the PGIA

connects to analog input sense (AISENSE).

For diagrams showing the signal paths of the three configurations, refer to

the Analog Input Signal Overview section in Chapter 4, Signal

Connections.

Input Range

The PCI-6023E, PCI-6024E, and PCI-6025E boards have a bipolar input

range that changes with the programmed gain. Each channel may be

programmed with a unique gain of 0.5, 1.0, 10, or 100 to maximize the

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12-bit analog-to-digital converter (ADC) resolution. With the proper gain

setting, you can use the full resolution of the ADC to measure the input

signal. Table 3-2 shows the input range and precision according to the gain

used.

Table 3-2. Measurement Precision

Gain

0.5

Input Range

-10 to +10V

Precision ^*

4.88 mV

1.0

-5 to +5V

2.44 mV

10.0

100.0

-500 to +500 mV

-50 to +50 mV

244.14 µV

24.41 µV

*The value of 1 LSB of the 12-bit ADC; that is, the voltage increment corresponding to a

change of one count in the ADC 12-bit count.

Note: See Appendix A, Specifications, for absolute maximum ratings.

Dither

When you enable dither, you add approximately 0.5 LSBrms of white

Gaussian noise to the signal to be converted by the ADC. This addition is

useful for applications involving averaging to increase the resolution of

your board, as in calibration or spectral analysis. In such applications, noise

modulation is decreased and differential linearity is improved by the

addition of the dither. When taking DC measurements, such as when

checking the board calibration, you should enable dither and average about

1,000 points to take a single reading. This process removes the effects of

quantization and reduces measurement noise, resulting in improved

resolution. For high-speed applications not involving averaging or spectral

analysis, you may want to disable the dither to reduce noise. Your software

enables and disables the dither circuitry.

Figure 3-2 illustrates the effect of dither on signal acquisition. Figure 3-2a

shows a small (±4 LSB) sine wave acquired with dither off. The ADC

quantization is clearly visible. Figure 3-2b shows what happens when 50

such acquisitions are averaged together; quantization is still plainly visible.

In Figure 3-2c, the sine wave is acquired with dither on. There is a

considerable amount of visible noise, but averaging about 50 such

acquisitions, as shown in Figure 3-2d, eliminates both the added noise and

the effects of quantization. Dither has the effect of forcing quantization

noise to become a zero-mean random variable rather than a deterministic

function of the input signal.

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LSBs

6.0

4.0

2.0

4.0

2.0

0.0

-2.0

-4.0

-6.0

-4.0

-6.0

100

200

300

400

500

100

200

300

400

500

a. Dither disabled; no averaging

b. Dither disabled; average of 50 acquisitions

LSBs

6.0

LSBs

6.0

4.0

2.0

4.0

2.0

0.0

-2.0

-4.0

-6.0

-4.0

-6.0

100

200

300

400

500

100

200

300

400

500

c. Dither enabled; no averaging

d. Dither enabled; average of 50 acquisitions

Figure 3-2. Dither

Multichannel Scanning Considerations

The PCI-6023E, PCI-6024E, and PCI-6025E boards can scan multiple

channels at the same maximum rate as their single-channel rate; however,

pay careful attention to the settling times for each of the boards. No extra

settling time is necessary between channels as long as the gain is constant

and source impedances are low. Refer to Appendix A, Specifications, for a

complete listing of settling times for each of the boards.

When scanning among channels at various gains, the settling times may

increase. When the PGIA switches to a higher gain, the signal on the

previous channel may be well outside the new, smaller range. For instance,

suppose a 4 V signal is connected to channel 0 and a 1 mV signal is

connected to channel 1, and suppose the PGIA is programmed to apply a

gain of one to channel 0 and a gain of 100 to channel 1. When the

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Chapter 3

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multiplexer switches to channel 1 and the PGIA switches to a gain of 100,

the new full-scale range is ±50 mV.

The approximately 4 V step from 4 V to 1 mV is 4,000% of the new

full-scale range. It may take as long as 100 µs for the circuitry to settle to

1 LSB after such a large transition. In general, this extra settling time is not

needed when the PGIA is switching to a lower gain.

Settling times can also increase when scanning high-impedance signals

due to a phenomenon called charge injection, where the analog input

multiplexer injects a small amount of charge into each signal source when

that source is selected. If the impedance of the source is not low enough,

the effect of the charge—a voltage error—will not have decayed by the time

the ADC samples the signal. For this reason, keep source impedances under

1 kΩ to perform high-speed scanning.

Due to the previously described limitations of settling times resulting from

these conditions, multiple-channel scanning is not recommended unless

sampling rates are low enough or it is necessary to sample several signals

as nearly simultaneously as possible. The data is much more accurate and

channel-to-channel independent if you acquire data from each channel

independently (for example, 100 points from channel 0, then 100 points

from channel 1, then 100 points from channel 2, and so on.)

Analog Output

♦

(PCI-6025E and PCI-6024E Only)

These boards supply two channels of analog output voltage at the I/O

connector. The bipolar range is fixed at ±10 V. Data written to the

digital-to-analog converter (DAC) will be interpreted as two’s complement

format.

Analog Output Glitch

In normal operation, a DAC output will glitch whenever it is updated with

a new value. The glitch energy differs from code to code and appears as

distortion in the frequency spectrum.

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Digital I/O

The PCI-6023E, PCI-6024, and PCI-6025E boards contain eight lines of

digital I/O (DIO<0..7>) for general-purpose use. You can individually

software-configure each line for either input or output. At system startup

and reset, the digital I/O ports are all high impedance.

The hardware up/down control for general-purpose counters 0 and 1 are

connected onboard to DIO6 and DIO7, respectively. Thus, you can use

DIO6 and DIO7 to control the general-purpose counters. The up/down

control signals are input only and do not affect the operation of the DIO

lines.

♦

PCI-6025E only:

The PCI-6025E board uses an 82C55A Programmable Peripheral Interface

to provide an additional 24 lines of digital I/O that represent three 8-bit

ports: PA, PB, PC. Each port can be programmed as an input or output port.

The 82C55A has three modes of operation: simple I/O (mode 0), strobed

I/O (mode 1), and bidirectional I/O (mode 2). In modes 1 and 2, the three

ports are divided into two groups: group A and group B. Each group has

eight data bits, plus control and status bits from Port C (PC). Modes 1 and

2 use handshaking signals from the computer to synchronize data transfers.

Refer to Chapter 4, Signal Connections, for more detailed information.

Timing Signal Routing

The DAQ-STC chip provides a flexible interface for connecting timing

signals to other boards or external circuitry. Your board uses the RTSI bus

to interconnect timing signals between boards, and the Programmable

Function Input (PFI) pins on the I/O connector to connect the board to

external circuitry. These connections are designed to enable the board to

both control and be controlled by other boards and circuits.

There are a total of 13 timing signals internal to the DAQ-STC that can be

controlled by an external source. These timing signals can also be

controlled by signals generated internally to the DAQ-STC, and these

selections are fully software-configurable. Figure 3-3 shows an example of

the signal routing multiplexer controlling the CONVERT* signal.

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RTSI Trigger <0..6>

CONVERT*

PFI<0..9>

Sample Interval Counter TC

GPCTR0_OUT

Figure 3-3. CONVERT* Signal Routing

This figure shows that CONVERT* can be generated from a number of

sources, including the external signals RTSI<0..6> and PFI<0..9> and the

internal signals Sample Interval Counter TC and GPCTR0_OUT.

Many of these timing signals are also available as outputs on the RTSI pins,

as indicated in the RTSI Triggers section in this chapter, and on the PFI

pins, as indicated in Chapter 4, Signal Connections.

Programmable Function Inputs

Ten PFI pins are available on the board connector as PFI<0..9> and are

connected to the board’s internal signal routing multiplexer for each timing

signal. Software can select any one of the PFI pins as the external source

for a given timing signal. It is important to note that any of the PFI pins can

be used as an input by any of the timing signals and that multiple timing

signals can use the same PFI simultaneously. This flexible routing scheme

reduces the need to change physical connections to the I/O connector for

different applications. You can also individually enable each of the PFI

pins to output a specific internal timing signal. For example, if you need the

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UPDATE* signal as an output on the I/O connector, software can turn on

the output driver for the PFI5/UPDATE* pin.

Board and RTSI Clocks

Many board functions require a frequency timebase to generate the

necessary timing signals for controlling A/D conversions, DAC updates, or

general-purpose signals at the I/O connector.

These boards can use either its internal 20 MHz timebase or a timebase

received over the RTSI bus. In addition, if you configure the board to use

the internal timebase, you can also program the board to drive its internal

timebase over the RTSI bus to another board that is programmed to receive

this timebase signal. This clock source, whether local or from the RTSI bus,

is used directly by the board as the primary frequency source. The default

configuration at startup is to use the internal timebase without driving the

RTSI bus timebase signal. This timebase is software selectable.

RTSI Triggers

The seven RTSI trigger lines on the RTSI bus provide a very flexible

interconnection scheme for any PCI E Series board sharing the RTSI bus.

These bidirectional lines can drive any of eight timing signals onto the

RTSI bus and can receive any of these timing signals. This signal

connection scheme is shown in Figure 3-4.

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DAQ-STC

TRIG1

TRIG2

CONVERT*

UPDATE*

WFTRIG

GPCTR0_SOURCE

GPCTR0_GATE

GPCTR0_OUT

STARTSCAN

Trigger

AIGATE

SISOURCE

UISOURCE

GPCTR1_SOURCE

GPCTR1_GATE

RTSI_OSC (20 MHz)

Clock

switch

Figure 3-4. RTSI Bus Signal Connection

Refer to the Timing Connections section of Chapter 4, Signal Connections,

for a description of the signals shown in Figure 3-4.

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Signal Connections

This chapter describes how to make input and output signal connections to

your board via the I/O connector.

The I/O connector for the PCI-6023 and PCI-6024E has 68 pins that you

can connect to 68-pin accessories with the SH6868 shielded cable or the

R6868 ribbon cable. You can connect your board to 50-pin signal

accessories with the SH6850 shielded cable or R6850 ribbon cable.

The I/O connector for the PCI-6025E has 100 pins that you can connect

to 100-pin accessories with the SH100100 shielded cable. You can connect

your board to 68-pin accessories with the SH1006868 shielded cable, or to

50-pin accessories with the R1005050 ribbon cable.

I/O Connector

Figure 4-1 shows the pin assignments for the 68-pin I/O connector on the

PCI-6023 and PCI-6024E. Figure 4-2 shows the pin assignments for the

100-pin I/O connector on the PCI-6025E. Refer to Appendix B, Custom

Cabling and Optional Connectors, for pin assignments of the optional

50- and 68-pin connectors. A signal description follows the figures.

Caution

Connections that exceed any of the maximum ratings of input or output signals

on the boards can damage the board and the computer. Maximum input ratings

for each signal are given in the Protection column of Table 4-2. National

Instruments is ^NOTliable for any damages resulting from such signal connections.

4-1

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34 68

ACH1 33 67

ACH8

ACH0

AIGND

ACH9

32 66

31 65

30 64

29 63

28 62

AIGND

ACH10

ACH3

ACH2

AIGND

ACH11

AISENSE

ACH12

ACH5

AIGND

ACH4

AIGND 27 61

ACH13 26 60

ACH6

AIGND 24 58

25 59

AIGND

ACH14

ACH7

ACH15

23 57

22 56

21 55

DAC0OUT¹

DAC1OUT¹

AIGND

AOGND

DGND

DIO0

RESERVED 20 54

19 53

18 52

17 51

16 50

15 49

DIO4

DGND

DIO1

DIO5

DIO6

DGND

DIO2

DGND

+5 V 14 48

DGND 13 47

DGND 12 46

DIO7

DIO3

SCANCLK

PFI0/TRIG1

11 45

10 44

EXTSTROBE*

DGND

PFI1/TRIG2

DGND

PFI2/CONVERT*

PFI3/GPCTR1_SOURCE

PFI4/GPCTR1_GATE

GPCTR1_OUT

DGND

+5 V

DGND

PFI5/UPDATE*

PFI6/WFTRIG

DGND

PFI7/STARTSCAN

PFI8/GPCTR0_SOURCE

DGND

PFI9/GPCTR0_GATE

GPCTR0_OUT

FREQ_OUT

DGND

¹Not available on the PCI-6023E

Figure 4-1. I/O Connector Pin Assignment for the PCI-6023E/PCI-6024E

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AIGND

ACH0

PC7

GND

PC6

GND

PC5

GND

PC4

GND

PC3

GND

PC2

GND

PC1

GND

PC0

GND

PB7

GND

PB6

GND

ACH8

ACH1

ACH9

ACH2

ACH10

ACH3

ACH11

ACH4

ACH12

ACH5

ACH13

ACH6

ACH14

ACH7

ACH15

AISENSE

DAC0OUT

DAC1OUT

RESERVED

AOGND

DGND

PB5

GND

PB4

GND

PB3

GND

PB2

GND

PB1

GND

PB0

GND

PA7

DIO0

DIO4

DIO1

DIO5

DIO2

DIO6

DIO3

DIO7

DGND

+5 V

GND

PA6

SCANCLK

EXTSTROBE*

PFI0/TRIG1

GND

PA5

GND

PFI1/TRIG2

PFI2/CONVERT*

PFI3/GPCTR1_SOURCE

PFI4/GPCTR1_GATE

GPCTR1_OUT

PA4

GND

PA3

GND

PA2

GND

PA1

PFI5/UPDATE*

PFI6/WFTRIG

PFI7/STARTSCAN

PFI8/GPCTR0_SOURCE

PFI9/GPCTR0_GATE

GPCTR0_OUT

GND

PA0

GND

+5 V

GND

FREQ_OUT

50 100

Figure 4-2. I/O Connector Pin Assignment for the PCI-6025E

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Signal Connections

Table 4-1 shows the I/O connector signal descriptions for the PCI-6023E,

PCI-6024E, and PCI-6025E.

Table 4-1. I/O Connector Signal Descriptions

Signal Name

Reference

Direction

Description

AIGND

—

Analog Input Ground—These pins are the reference point

for single-ended measurements in RSE configuration and

the bias current return point for differential measurements.

All three ground references—AIGND, AOGND, and

DGND—are connected together on your board.

ACH<0..15>

AIGND

Input

Analog Input Channels 0 through 15—Each channel pair,

ACH<i, i+8> (i = 0..7), can be configured as either one

differential input or two single-ended inputs.

AISENSE

DAC0OUT¹

DAC1OUT¹

AOGND

AIGND

AOGND

—

Input

Output

—

Analog Input Sense—This pin serves as the reference node

for any of channels ACH <0..15> in NRSE configuration.

Analog Channel 0 Output—This pin supplies the voltage

output of analog output channel 0.

Analog Channel 1 Output—This pin supplies the voltage

output of analog output channel 1.

Analog Output Ground—The analog output voltages are

referenced to this node. All three ground

references—AIGND, AOGND, and DGND—are connected

together on your PCI E Series board.

DGND

—

Digital Ground—This pin supplies the reference for the

digital signals at the I/O connector as well as the +5 VDC

supply. All three ground references—AIGND, AOGND,

and DGND—are connected together on your PCI E Series

board.

DIO<0..7>

PA<0..7>²

DGND

Input or

Output

Digital I/O signals—DIO6 and 7 can control the up/down

signal of general-purpose counters 0 and 1, respectively.

Input or

Output

Port A bidirectional digital data lines for the 82C55A

programmable peripheral interface on the PCI-6025E. PA7

is the MSB. PA0 is the LSB.

PB<0..7>²

PC<0..7>²

+5 V

DGND

Input or

Output

Port B bidirectional digital data lines for the 82C55A

programmable peripheral interface on the PCI-6025E. PB7

is the MSB. PB0 is the LSB.

Input or

Output

Port C bidirectional digital data lines for the 82C55A

programmable peripheral interface on the PCI-6025E. PC7

is the MSB. PC0 is the LSB.

Output

+5 VDC Source—These pins are fused for up to 1 A of

+5 V supply. The fuse is self-resetting.

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Table 4-1. I/O Connector Signal Descriptions (Continued)

Signal Name

SCANCLK

Reference

Direction

Description

DGND

Output

Scan Clock—This pin pulses once for each A/D conversion

in scanning mode when enabled. The low-to-high edge

indicates when the input signal can be removed from the

input or switched to another signal.

EXTSTROBE*

PFI0/TRIG1

DGND

Output

Input

External Strobe—This output can be toggled under software

control to latch signals or trigger events on external devices.

PFI0/Trigger 1—As an input, this is one of the

Programmable Function Inputs (PFIs). PFI signals are

explained in the Timing Connections section later in this

chapter.

Output

As an output, this is the TRIG1 (AI Start Trigger) signal. In

posttrigger data acquisition sequences, a low-to-high

transition indicates the initiation of the acquisition

sequence. In pretrigger applications, a low-to-high

transition indicates the initiation of the pretrigger

conversions.

PFI1/TRIG2

DGND

Input

PFI1/Trigger 2—As an input, this is one of the PFIs.

Output

As an output, this is the TRIG2 (AI Stop Trigger) signal. In

pretrigger applications, a low-to-high transition indicates

the initiation of the posttrigger conversions. TRIG2 is not

used in posttrigger applications.

PFI2/CONVERT*

DGND

Input

PFI2/Convert—As an input, this is one of the PFIs.

Output

As an output, this is the CONVERT* (AI Convert) signal. A

high-to-low edge on CONVERT* indicates that an A/D

conversion is occurring.

PFI3/GPCTR1_SOURCE

PFI4/GPCTR1_GATE

GPCTR1_OUT

Input

PFI3/Counter 1 Source—As an input, this is one of the PFIs.

Output

As an output, this is the GPCTR1_SOURCE signal. This

signal reflects the actual source connected to the

general-purpose counter 1.

Input

PFI4/Counter 1 Gate—As an input, this is one of the PFIs.

Output

As an output, this is the GPCTR1_GATE signal. This signal

reflects the actual gate signal connected to the

general-purpose counter 1.

Output

Counter 1 Output—This output is from the general-purpose

counter 1 output.

4-5

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Table 4-1. I/O Connector Signal Descriptions (Continued)

Signal Name

Reference

Direction

Description

PFI5/UPDATE*

DGND

Input

PFI5/Update—As an input, this is one of the PFIs.

Output

As an output, this is the UPDATE* (AO Update) signal. A

high-to-low edge on UPDATE* indicates that the analog

output primary group is being updated for the PCI-6024 or

PCI-6025.

PFI6/WFTRIG

DGND

Input

PFI6/Waveform Trigger—As an input, this is one of the

PFIs.

Output

As an output, this is the WFTRIG (AO Start Trigger) signal.

In timed analog output sequences, a low-to-high transition

indicates the initiation of the waveform generation.

PFI7/STARTSCAN

PFI8/GPCTR0_SOURCE

PFI9/GPCTR0_GATE

Input

PFI7/Start of Scan—As an input, this is one of the PFIs.

Output

As an output, this is the STARTSCAN (AI Scan Start)

signal. This pin pulses once at the start of each analog input

scan in the interval scan. A low-to-high transition indicates

the start of the scan.

Input

PFI8/Counter 0 Source—As an input, this is one of the

PFIs.

Output

As an output, this is the GPCTR0_SOURCE signal. This

signal reflects the actual source connected to the

general-purpose counter 0.

Input

PFI9/Counter 0 Gate—As an input, this is one of the PFIs.

Output

As an output, this is the GPCTR0_GATE signal. This signal

reflects the actual gate signal connected to the

general-purpose counter 0.

GPCTR0_OUT

FREQ_OUT

DGND

Output

Counter 0 Output—This output is from the general-purpose

counter 0 output.

Frequency Output—This output is from the frequency

generator output.

^*Indicates that the signal is active low

¹Not available on the PCI-6023E

²Not available on the PCI-6023E or PCI-6024E

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Table 4-2 shows the I/O signal summary for the PCI-6023E, PCI-6024E,

and PCI-6025E.

Table 4-2. I/O Signal Summary

Signal

Type and

Direction

Impedance

Input/

Output

Protection

(Volts)

On/Off

Sink

(mA

at V)

Rise

Time

(ns)

Source

(mA at V)

Signal Name

Bias

ACH<0..15>

100 GΩ

parallel

with

42/35

40/25

—

±200 pA

100 pF

AISENSE

AIGND

100 GΩ

parallel

with

—

±200 pA

100 pF

—

DAC0OUT

(6024E and 6025E only)

0.1 Ω

Short-circuit

to ground

5 at 10

5 at -10

V/µs

DAC1OUT

(6024E and 6025E only)

0.1 Ω

Short-circuit

to ground

5 at 10

5 at -10

V/µs

—

AOGND

DGND

VCC

—

0.1 Ω

Short-circuit

to ground

1A fused

DIO<0..7>

DIO

—

+0.5

13 at (V -0.4)

24 at

0.4

1.1

50 kΩ pu

PA<0..7>

(6025E only)

2.5 at 3.7min

2.5 at

0.4

100 kΩ

PB<0..7>

(6025E only)

2.5 at

0.4

100 kΩ

PC<0..7>

(6025E only)

2.5 at

0.4

100 kΩ

SCANCLK

—

3.5 at (V -0.4) 5 at 0.4

1.5

50 kΩ pu

EXTSTROBE*

PFI0/TRIG1

—

3.5 at (V -0.4) 5 at 0.4

DIO

+0.5

3.5 at (V -0.4) 5 at 0.4

PFI1/TRIG2

+0.5

3.5 at (V -0.4) 5 at 0.4

PFI2/CONVERT*

3.5 at (V -0.4) 5 at 0.4

4-7

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Table 4-2. I/O Signal Summary (Continued)

Signal

Type and

Direction

Impedance

Input/

Output

Protection

(Volts)

On/Off

Sink

(mA

at V)

Rise

Time

(ns)

Source

(mA at V)

Signal Name

Bias

PFI3/GPCTR1_SOURCE

PFI4/GPCTR1_GATE

GPCTR1_OUT

DIO

—

+0.5

3.5 at (V -0.4) 5 at 0.4

1.5

50 kΩ pu

3.5 at (V -0.4) 5 at 0.4

—

3.5 at (V -0.4) 5 at 0.4

PFI5/UPDATE*

DIO

+0.5

3.5 at (V -0.4) 5 at 0.4

PFI6/WFTRIG

3.5 at (V -0.4) 5 at 0.4

PFI7/STARTSCAN

PFI8/GPCTR0_SOURCE

PFI9/GPCTR0_GATE

GPCTR0_OUT

3.5 at (V -0.4) 5 at 0.4

—

3.5 at (V -0.4) 5 at 0.4

FREQ_OUT

—

3.5 at (V -0.4)

5 at 0.4

AI = Analog Input

AO = Analog Output

DIO = Digital Input/Output

DO = Digital Output

pu = pullup

Note: The tolerance on the 50 kΩ pullup and pulldown resistors is very large. Actual value may range between 17 kΩ and

100 kΩ.

Analog Input Signal Overview

The analog input signals for these boards are ACH<0..15>, ASENSE, and

AIGND. Connection of these analog input signals to your board depends

on the type of input signal source and the configuration of the analog input

channels you are using. This section provides an overview of the different

types of signal sources and analog input configuration modes. More

specific signal connection information is provided in the section, Analog

Input Signal Connections.

Types of Signal Sources

When configuring the input channels and making signal connections,

you must first determine whether the signal sources are floating or

ground-referenced.

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Floating Signal Sources

A floating signal source is not connected in any way to the building ground

system but, rather, has an isolated ground-reference point. Some examples

of floating signal sources are outputs of transformers, thermocouples,

battery-powered devices, optical isolators, and isolation amplifiers. An

instrument or device that has an isolated output is a floating signal source.

You must tie the ground reference of a floating signal to your board’s

analog input ground to establish a local or onboard reference for the signal.

Otherwise, the measured input signal varies as the source floats out of the

common-mode input range.

Ground-Referenced Signal Sources

A ground-referenced signal source is connected in some way to the

building system ground and is, therefore, already connected to a common

ground point with respect to the board, assuming that the computer is

plugged into the same power system. Nonisolated outputs of instruments

and devices that plug into the building power system fall into this category.

The difference in ground potential between two instruments connected to

the same building power system is typically between 1 and 100 mV but can

be much higher if power distribution circuits are not properly connected.

If a grounded signal source is improperly measured, this difference may

appear as an error in the measurement. The connection instructions for

grounded signal sources are designed to eliminate this ground potential

difference from the measured signal.

Analog Input Modes

You can configure your board for one of three input modes: nonreferenced

single ended (NRSE), referenced single ended (RSE), and differential

(DIFF). With the different configurations, you can use the PGIA in

different ways. Figure 4-3 shows a diagram of your board’s PGIA.

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Programmable

Gain

Instrumentation

Amplifier

V_in+

PGIA

V_m

Measured

Voltage

V_in-

V_m= [V_in+- V_in-]* Gain

Figure 4-3. Programmable Gain Instrumentation Amplifier (PGIA)

In single-ended mode (RSE and NRSE), signals connected to ACH<0..15>

are routed to the positive input of the PGIA. In differential mode, signals

connected to ACH<0..7> are routed to the positive input of the PGIA, and

signals connected to ACH<8..15> are routed to the negative input of the

PGIA.

Caution

Exceeding the differential and common-mode input ranges distorts your input

signals. Exceeding the maximum input voltage rating can damage the board and

the computer. National Instruments is ^NOTliable for any damages resulting from

such signal connections. The maximum input voltage ratings are listed in the

Protection column of Table 4-2.

In NRSE mode, the AISENSE signal is connected internally to the negative

input of the PGIA when their corresponding channels are selected. In DIFF

and RSE modes, AISENSE is left unconnected.

AIGND is an analog input common signal that is routed directly to the

ground tie point on the boards. You can use this signal for a general analog

ground tie point to your board if necessary.

The PGIA applies gain and common-mode voltage rejection and presents

high input impedance to the analog input signals connected to your board.

Signals are routed to the positive and negative inputs of the PGIA through

input multiplexers on the board. The PGIA converts two input signals to a

signal that is the difference between the two input signals multiplied by the

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Chapter 4

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gain setting of the amplifier. The amplifier output voltage is referenced to

the ground for the board. Your board’s A/D converter (ADC) measures this

output voltage when it performs A/D conversions.

You must reference all signals to ground either at the source device or at

the board. If you have a floating source, you should reference the signal

to ground by using the RSE input mode or the DIFF input configuration

with bias resistors (see the Differential Connections for Nonreferenced or

Floating Signal Sources section in this chapter). If you have a grounded

source, you should not reference the signal to AIGND. You can avoid this

reference by using DIFF or NRSE input configurations.

Analog Input Signal Connections

The following sections discuss the use of single-ended and differential

measurements and recommendations for measuring both floating and

ground-referenced signal sources.

Figure 4-4 summarizes the recommended input configuration for both

types of signal sources.

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Signal Source Type

Grounded Signal Source

Floating Signal Source

(Not Connected to Building Ground)

Examples

• Plug-in instruments with

nonisolated outputs

• Ungrounded Thermocouples

• Signal conditioning with isolated outputs

• Battery devices

Input

ACH(+)

ACH (-)

Differential

(DIFF)

AIGND

See text for information on bias resistors.

NOT RECOMMENDED

ACH

Single-Ended —

Ground

Referenced

(RSE)

AIGND

Ground-loop losses, Vg, are added to

measured signal

ACH

Single-Ended —

Nonreferenced

(NRSE)

AISENSE

AIGND

See text for information on bias resistors.

Figure 4-4. Summary of Analog Input Connections

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Chapter 4

Signal Connections

Differential Connection Considerations (DIFF Input Configuration)

A differential connection is one in which the analog input signal has its own

reference signal or signal return path. These connections are available

when the selected channel is configured in DIFF input mode. The input

signal is tied to the positive input of the PGIA, and its reference signal, or

return, is tied to the negative input of the PGIA.

When you configure a channel for differential input, each signal uses two

multiplexer inputs—one for the signal and one for its reference signal.

Therefore, with a differential configuration for every channel, up to eight

analog input channels are available.

You should use differential input connections for any channel that meets

any of the following conditions:

•

The input signal is low level (less than 1 V).

The leads connecting the signal to the board are greater than

10 ft (3 m).

•

The input signal requires a separate ground-reference point or return

signal.

The signal leads travel through noisy environments.

Differential signal connections reduce picked up noise and increase

common-mode noise rejection. Differential signal connections also allow

input signals to float within the common-mode limits of the PGIA.

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Differential Connections for Ground-Referenced

Signal Sources

Figure 4-5 shows how to connect a ground-referenced signal source to a

channel on the board configured in DIFF input mode.

ACH+

Ground-

Referenced

Signal

Source

Programmable Gain

Instrumentation

V_s

Amplifier

PGIA

ACH-

Measured

Voltage

V_m

Common-

Mode

Noise and

Ground

V_cm

Potential

Input Multiplexers

AISENSE

AIGND

I/O Connector

Selected Channel in DIFF Configuration

Figure 4-5. Differential Input Connections for Ground-Referenced Signals

With this type of connection, the PGIA rejects both the common-mode

noise in the signal and the ground potential difference between the signal

source and the board ground, shown as V_cmin Figure 4-5.

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Signal Connections

Differential Connections for Nonreferenced or

Floating Signal Sources

Figure 4-6 shows how to connect a floating signal source to a channel

configured in DIFF input mode.

ACH+

Bias

resistors

(see text)

Programmable Gain

Instrumentation

Amplifier

Floating

Signal

Source

V_S

PGIA

ACH-

Measured

Voltage

V_m

Bias

Current

Return

Paths

Input Multiplexers

AISENSE

AIGND

I/O Connector

Selected Channel in DIFF Configuration

Figure 4-6. Differential Input Connections for Nonreferenced Signals

Figure 4-6 shows two bias resistors connected in parallel with the signal

leads of a floating signal source. If you do not use the resistors and the

source is truly floating, the source is not likely to remain within the

common-mode signal range of the PGIA. The PGIA will then saturate,

causing erroneous readings. You must reference the source to AIGND. The

easiest way is to connect the positive side of the signal to the positive input

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Chapter 4

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of the PGIA and connect the negative side of the signal to AIGND as well

as to the negative input of the PGIA, without any resistors at all. This

connection works well for DC-coupled sources with low source impedance

(less than 100 Ω).

However, for larger source impedances, this connection leaves the

differential signal path significantly out of balance. Noise that couples

electrostatically onto the positive line does not couple onto the negative

line because it is connected to ground. Hence, this noise appears as a

differential-mode signal instead of a common-mode signal, and the PGIA

does not reject it. In this case, instead of directly connecting the negative

line to AIGND, connect it to AIGND through a resistor that is about

100 times the equivalent source impedance. The resistor puts the signal

path nearly in balance, so that about the same amount of noise couples onto

both connections, yielding better rejection of electrostatically coupled

noise. Also, this configuration does not load down the source (other than

the very high input impedance of the PGIA).

You can fully balance the signal path by connecting another resistor of the

same value between the positive input and AIGND, as shown in Figure 4-6.

This fully balanced configuration offers slightly better noise rejection but

has the disadvantage of loading the source down with the series

combination (sum) of the two resistors. If, for example, the source

impedance is 2 kΩ and each of the two resistors is 100 kΩ, the resistors

load down the source with 200 kΩ and produce a –1% gain error.

Both inputs of the PGIA require a DC path to ground in order for the PGIA

to work. If the source is AC coupled (capacitively coupled), the PGIA needs

a resistor between the positive input and AIGND. If the source has low

impedance, choose a resistor that is large enough not to significantly load

the source but small enough not to produce significant input offset voltage

as a result of input bias current (typically 100 kΩ to 1 MΩ). In this case,

you can tie the negative input directly to AIGND. If the source has high

output impedance, you should balance the signal path as previously

described using the same value resistor on both the positive and negative

inputs; you should be aware that there is some gain error from loading down

the source.

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Single-Ended Connection Considerations

A single-ended connection is one in which the board analog input signal is

referenced to a ground that can be shared with other input signals. The input

signal is tied to the positive input of the PGIA, and the ground is tied to the

negative input of the PGIA.

When every channel is configured for single-ended input, up to 16 analog

input channels are available.

You can use single-ended input connections for any input signal that meets

the following conditions:

•

The input signal is high level (greater than 1 V).

The leads connecting the signal to the board are less than 10 ft (3 m).

The input signal can share a common reference point with other

signals.

DIFF input connections are recommended for greater signal integrity for

any input signal that does not meet the preceding conditions.

Using your software, you can configure the channels for two different types

of single-ended connections—RSE configuration and NRSE configuration.

The RSE configuration is used for floating signal sources; in this case, the

board provides the reference ground point for the external signal. The

NRSE input configuration is used for ground-referenced signal sources; in

this case, the external signal supplies its own reference ground point and the

board should not supply one.

In single-ended configurations, more electrostatic and magnetic noise

couples into the signal connections than in differential configurations. The

coupling is the result of differences in the signal path. Magnetic coupling

is proportional to the area between the two signal conductors. Electrical

coupling is a function of how much the electric field differs between the

two conductors.

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Single-Ended Connections for Floating Signal

Sources (RSE Configuration)

Figure 4-7 shows how to connect a floating signal source to a channel

configured for RSE mode.

ACH

Programmable Gain

Instrumentation Amplifier

Floating

Signal

V_s

Source

PGIA

Input Multiplexers

AISENSE

Measured

Voltage

V_m

AIGND

I/O Connector

Selected Channel in RSE Configuration

Figure 4-7. Single-Ended Input Connections for Nonreferenced or Floating Signals

Single-Ended Connections for Grounded Signal

Sources (NRSE Configuration)

To measure a grounded signal source with a single-ended configuration,

you must configure your board in the NRSE input configuration. The signal

is then connected to the positive input of the PCI E Series PGIA, and the

signal local ground reference is connected to the negative input of the

PGIA. The ground point of the signal should, therefore, be connected to the

AISENSE pin. Any potential difference between the board ground and the

signal ground appears as a common-mode signal at both the positive and

negative inputs of the PGIA, and this difference is rejected by the amplifier.

If the input circuitry of a board were referenced to ground, in this situation

as in the RSE input configuration, this difference in ground potentials

would appear as an error in the measured voltage.

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Figure 4-8 shows how to connect a grounded signal source to a channel

configured for NRSE mode.

ACH+

Ground-

Referenced

Signal

Programmable Gain

Instrumentation

V_s

Source

Amplifier

PGIA

ACH-

Measured

Voltage

V_m

Common-

Mode

Noise and

Ground

V_cm

Potential

Input Multiplexers

AISENSE

AIGND

I/O Connector

Selected Channel in DIFF Configuration

Figure 4-8. Single-Ended Input Connections for Ground-Referenced Signals

Common-Mode Signal Rejection Considerations

Figures 4-5 and 4-8 show connections for signal sources that are already

referenced to some ground point with respect to the board. In these cases,

the PGIA can reject any voltage caused by ground potential differences

between the signal source and the board. In addition, with differential input

connections, the PGIA can reject common-mode noise pickup in the leads

connecting the signal sources to the board. The PGIA can reject

common-mode signals as long as V+_inand V–_in(input signals) are both

within ±11 V of AIGND.

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Analog Output Signal Connections

♦

PCI-6024E and PCI-6025E

The analog output signals are DAC0OUT, DAC1OUT, and AOGND.

DAC0OUT and DAC1OUT are not available on the PCI-6023E.

DAC0OUT is the voltage output signal for analog output channel 0.

DAC1OUT is the voltage output signal for analog output channel 1.

AOGND is the ground reference signal for both analog output channels and

the external reference signal.

Figure 4-9 shows how to make analog output connections to your board.

DAC0OUT

Channel 0

VOUT 0

Load

AOGND

VOUT 1

DAC1OUT

Channel 1

Analog Output Channels

I/O Connector

Figure 4-9. Analog Output Connections

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Chapter 4

Signal Connections

Digital I/O Signal Connections

All Boards

All boards have digital I/O signals DIO<0..7> and DGND. DIO<0..7> are

the signals making up the DIO port, and DGND is the ground reference

signal for the DIO port. You can program all lines individually to be inputs

or outputs.

Figure 4-10 shows signal connections for three typical digital I/O

applications.

+5 V

LED

DIO<4..7>

TTL Signal

DIO<0..3>

+5 V

Switch

DGND

I/O Connector

Figure 4-10. Digital I/O Connections

Figure 4-10 shows DIO<0..3> configured for digital input and DIO<4..7>

configured for digital output. Digital input applications include receiving

TTL signals and sensing external device states such as the state of the

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Chapter 4

Signal Connections

switch shown in the figure. Digital output applications include sending

TTL signals and driving external devices such as the LED shown in the

figure.

PCI-6025E Only

The PCI-6025E board uses an 82C55A PPI to provide an additional 24

lines of digital I/O that represent three 8-bit ports: PA, PB, and PC. Each

port can be programmed as an input or output port.

Figure 4-11 depicts signal connections for three typical digital I/O

applications.

+5 V

LED

Port A

PA<3..0>

Port B

TTL Signal

PB<7..4>

+5 V

Switch

GND

I/O Connector

DIO Board

Figure 4-11. Digital I/O Connections Block Diagram

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Chapter 4

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In Figure 4-11, port A of one PPI is configured for digital output, and

port B is configured for digital input. Digital input applications include

receiving TTL signals and sensing external device states such as the state

of the switch in Figure 4-11. Digital output applications include sending

TTL signals and driving external devices such as the LED shown in

Figure 4-11.

Port C Pin Assignments

♦

PCI-6025 Only

The signals assigned to port C depend on how the 82C55A is configured.

In mode 0, or no handshaking configuration, port C is configured as two

4-bit I/O ports. In modes 1 and 2, or handshaking configuration, port C

is used for status and handshaking signals with any leftover lines available

for general-purpose I/O. Table 4-3 summarizes the port C signal

assignments for each configuration. You can also use ports A and B in

different modes; the table does not show every possible combination.

Note

Table 4-3 shows both the port C signal assignments and the terminology

correlation between different documentation sources. The 82C55A terminology

refers to the different 82C55A configurations as modes, whereas NI-DAQ,

ComponentWorks, LabWindows/CVI, and LabVIEW documentation refers to

them as handshaking and no handshaking.

Table 4-3. Port C Signal Assignments

Configuration Terminology

Signal Assignments

PCI-6023E/

6024E/6025E

User Manual

National

Instruments

Software

PC7

PC6

PC5

PC4

PC3

PC2

PC1

PC0

I/O

Mode 0

(Basic I/O)

Handshaking

I/O

IBF_A

I/O

STB_A*

I/O

INTR_A

STB_B*

ACK_B*

I/O

IBFB_B

OBF_B*

I/O

INTR_B

I/O

Mode 1

(Strobed Input)

Handshaking

OBF_A*

ACK_A*

Mode 1

(Strobed Output)

Handshaking

IBF_A

STB_A*

Mode 2

(Bidirectional

Bus)

*Indicates that the signal is active low.

Subscripts A and B denote port A or port B handshaking signals.

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Digital I/O Power-up State

♦

(PCI-6025E Only)

The PCI-6025E contains bias resistors that control the state of the digital

I/O lines PA<0..7>,PB<0..7>,PC<0..7> at power up. Each digital I/O line

is configured as an input, pulled high by a 100 kΩ bias resistor.

You can change individual lines from pulled up to pulled down by adding

your own external resistors. This section describes the procedure.

Changing DIO Power-up State to Pulled Low

Each DIO line is pulled to V_cc(approximately +5 VDC) with a 100 kΩ

resistor. To pull a specific line low, connect between that line and ground

a pull-down resistor (R_L) whose value will give you a maximum of 0.4

VDC. The DIO lines provide a maximum of 2.5 mA at 3.7 V in the high

state. Using the largest possible resistor ensures that you do not use more

current than necessary to perform the pull-down task.

However, make sure the resistor’s value is not so large that leakage current

from the DIO line along with the current from the 100 kΩ pull-up resistor

drives the voltage at the resistor above a TTL-low level of 0.4 VDC. Figure

4-12 shows the DIO configuration for high DIO power-up state.

Board

+5 V

100 kΩ

82C55

Digital I/O Line

R_L

GND

Figure 4-12. DIO Channel Configured for High DIO Power-up State with External Load

Example:

A given DIO line is pulled high at power up. To pull it low on power up with

an external resistor, follow these steps:

1. Install a load (R_L). Remember that the smaller the resistance, the

greater the current consumption and the lower the voltage.

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2. Using the following formula, calculate the largest possible load to

maintain a logic low level of 0.4 V and supply the maximum driving

current:

V = I * R_L⇒ R_L= V/I, where:

V = 0.4 V

; Voltage across R_L

I = 46 µA + 10 µA ; 4.6 V across the 100 kΩ pull-up resistor

and 10 µA maximum leakage current

Therefore:

R_L= 7.1 kΩ

; 0.4 V/56 µA

This resistor value, 7.1 kΩ, provides a maximum of 0.4 V on the DIO line

at power up. You can substitute smaller resistor values to lower the voltage

or to provide a margin for V_ccvariations and other factors. However,

smaller values will draw more current, leaving less drive current for other

circuitry connected to this line. The 7.1 kΩ resistor reduces the amount of

logic high source current by 0.4 mA with a 2.8 V output.

Timing Specifications

♦

(PCI-6025E Only)

This section lists the timing specifications for handshaking with your

PCI-6025E PC<0..7> lines. The handshaking lines STB* and IBF

synchronize input transfers. The handshaking lines OBF* and ACK*

synchronize output transfers. Table 4-4 describes signals appearing in the

handshaking diagrams.

Table 4-4. Signal Names Used in Timing Diagrams

Name

STB*

Type

Description

Input

Strobe Input—A low signal on this handshaking line loads data into

the input latch.

IBF

Output

Input Buffer Full—A high signal on this handshaking line indicates

that data has been loaded into the input latch. A low signal indicates

the board is ready for more data. This is an input acknowledge

signal.

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Table 4-4. Signal Names Used in Timing Diagrams (Continued)

Name

Type

Description

ACK*

Input

Acknowledge Input—A low signal on this handshaking line

indicates that the data written to the port has been accepted. This

signal is a response from the external device indicating that it has

received the data from your DIO board.

OBF*

INTR

Output

Output Buffer Full—A low signal on this handshaking line

indicates that data has been written to the port.

Interrupt Request—This signal becomes high when the 82C55A

requests service during a data transfer. The appropriate interrupt

enable bits must be set to generate this signal.

RD*

Internal

Read—This signal is the read signal generated from the control

lines of the computer I/O expansion bus.

WR*

DATA

Write—This signal is the write signal generated from the control

lines of the computer I/O expansion bus.

Bidirectional

Data Lines at the Specified Port—For output mode, this signal

indicates the availability of data on the data line. For input mode,

this signal indicates when the data on the data lines should be valid.

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Mode 1 Input Timing

Timing specifications for an input transfer in mode 1 are as follows:

STB *

IBF

INTR

RD *

DATA

Name

Description

Minimum

Maximum

—

100

—

STB* Pulse Width

150

STB* = 0 to IBF = 1

Data before STB* = 1

STB* = 1 to INTR = 1

Data after STB* = 1

RD* = 0 to INTR = 0

RD* = 1 to IBF = 0

—

150

—

200

150

All timing values are in nanoseconds.

Figure 4-13. Timing Specifications for Mode 1 Input Transfer

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Mode 1 Output Timing

Timing specifications for an output transfer in mode 1 are as follows:

WR*

OBF*

INTR

ACK*

DATA

Name

Description

WR* = 0 to INTR = 0

Minimum

Maximum

250

—

200

WR* = 1 to Output

—

150

WR* = 1 to OBF* = 0

ACK* = 0 to OBF* = 1

ACK* Pulse Width

—

150

100

—

150

ACK* = 1 to INTR = 1

All timing values are in nanoseconds.

Figure 4-14. Timing Specifications for Mode 1 Output Transfer

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Mode 2 Bidirectional Timing

Timing specifications for a bidirectional transfer in mode 2 are as follows:

WR *

OBF *

INTR

ACK *

STB *

T10

IBF

RD *

DATA

Name

Description

Minimum

Maximum

150

—

WR* = 1 to OBF* = 0

Data before STB* = 1

STB* Pulse Width

100

—

150

—

STB* = 0 to IBF = 1

Data after STB* = 1

ACK* = 0 to OBF* = 1

ACK* Pulse Width

ACK* = 0 to Output

ACK* = 1 to Output Float

RD* = 1 to IBF = 0

—

150

—

100

—

150

250

150

T10

—

All timing values are in nanoseconds.

Figure 4-15. Timing Specifications for Mode 2 Bidirectional Transfer

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Power Connections

Two pins on the I/0 connector supply +5 V from the computer power

supply via a self-resetting fuse. The fuse will reset automatically within a

few seconds after the overcurrent condition is removed. These pins are

referenced to DGND and can be used to power external digital circuitry.

•

Power rating

+4.65 to +5.25 VDC at 1 A

Caution

Under no circumstances should you connect these +5 V power pins directly to

analog or digital ground or to any other voltage source on the board or any other

device. Doing so can damage the board and the computer. National Instruments

is ^NOTliable for damages resulting from such a connection.

Timing Connections

Caution

Exceeding the maximum input voltage ratings, which are listed in T a ble 4-2, can

damage the board and the computer. National Instruments is ^NOTliable for any

damages resulting from such signal connections.

All external control over the timing of your board is routed through the 10

programmable function inputs labeled PFI<0..9>. These signals are

explained in detail in the section, Programmable Function Input

Connections. These PFIs are bidirectional; as outputs they are not

programmable and reflect the state of many DAQ, waveform generation,

and general-purpose timing signals. There are five other dedicated outputs

for the remainder of the timing signals. As inputs, the PFI signals are

programmable and can control any DAQ, waveform generation, and

general-purpose timing signals.

The DAQ signals are explained in the DAQ Timing Connections section

later in this chapter. The waveform generation signals are explained in the

Waveform Generation Timing Connections section later in this chapter.

The general-purpose timing signals are explained in the General-Purpose

Timing Signal Connections section in this chapter.

All digital timing connections are referenced to DGND. This reference

is demonstrated in Figure 4-16, which shows how to connect an external

TRIG1 source and an external CONVERT* source to two PCI E Series

board PFI pins.

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PFI0/TRIG1

PFI2/CONVERT*

TRIG1

Source

CONVERT*

Source

DGND

I/O Connector

Figure 4-16. Timing I/O Connections

Programmable Function Input Connections

There are a total of 13 internal timing signals that you can externally control

from the PFI pins. The source for each of these signals is

software-selectable from any of the PFIs when you want external control.

This flexible routing scheme reduces the need to change the physical

wiring to the board I/O connector for different applications requiring

alternative wiring.

You can individually enable each of the PFI pins to output a specific

internal timing signal. For example, if you need the CONVERT* signal as

an output on the I/O connector, software can turn on the output driver for

the PFI2/CONVERT* pin. Be careful not to drive a PFI signal externally

when it is configured as an output.

As an input, you can individually configure each PFI pin for edge or level

detection and for polarity selection, as well. You can use the polarity

selection for any of the 13 timing signals, but the edge or level detection

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will depend upon the particular timing signal being controlled. The

detection requirements for each timing signal are listed within the section

that discusses that individual signal.

In edge-detection mode, the minimum pulse width required is 10 ns. This

applies for both rising-edge and falling-edge polarity settings. There is no

maximum pulse-width requirement in edge-detect mode.

In level-detection mode, there are no minimum or maximum pulse-width

requirements imposed by the PFIs themselves, but there may be limits

imposed by the particular timing signal being controlled. These

requirements are listed later in this chapter.

DAQ Timing Connections

The DAQ timing signals are SCANCLK, EXTSTROBE*, TRIG1, TRIG2,

STARTSCAN, CONVERT*, AIGATE, and SISOURCE.

Posttriggered data acquisition allows you to view only data that is acquired

after a trigger event is received. A typical posttriggered DAQ sequence is

shown in Figure 4-17. Pretriggered data acquisition allows you to view data

that is acquired before the trigger of interest in addition to data acquired

after the trigger. Figure 4-18 shows a typical pretriggered DAQ sequence.

The description for each signal shown in these figures is included later in

this chapter.

TRIG1

STARTSCAN

CONVERT*

Scan Counter

Figure 4-17. Typical Posttriggered Acquisition

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TRIG1

TRIG2

Don't Care

STARTSCAN

CONVERT*

Scan Counter

Figure 4-18. Typical Pretriggered Acquisition

SCANCLK Signal

SCANCLK is an output-only signal that generates a pulse with the leading

edge occurring approximately 50 to 100 ns after an A/D conversion begins.

The polarity of this output is software-selectable but is typically configured

so that a low-to-high leading edge can clock external analog input

multiplexers indicating when the input signal has been sampled and can be

removed. This signal has a 400 to 500 ns pulse width and is

software-enabled. Figure 4-19 shows the timing for the SCANCLK signal.

CONVERT*

SCANCLK

= 50 to 100 ns

w = 400 to 500 ns

Figure 4-19. SCANCLK Signal Timing

EXTSTROBE* Signal

EXTSTROBE* is an output-only signal that generates either a single pulse

or a sequence of eight pulses in the hardware-strobe mode. An external

device can use this signal to latch signals or to trigger events. In the

single-pulse mode, software controls the level of the EXTSTROBE*

signal. A 10 µs and a 1.2 µs clock are available for generating a sequence

of eight pulses in the hardware-strobe mode. Figure 4-20 shows the timing

for the hardware-strobe mode EXTSTROBE* signal.

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= 600 ns or 5 µs

Figure 4-20. EXTSTROBE* Signal Timing

TRIG1 Signal

Any PFI pin can externally input the TRIG1 signal, which is available as

an output on the PFI0/TRIG1 pin.

Refer to Figures 4-17 and 4-18 for the relationship of TRIG1 to the DAQ

sequence.

As an input, the TRIG1 signal is configured in the edge-detection mode.

You can select any PFI pin as the source for TRIG1 and configure the

polarity selection for either rising or falling edge. The selected edge of the

TRIG1 signal starts the data acquisition sequence for both posttriggered

and pretriggered acquisitions.

As an output, the TRIG1 signal reflects the action that initiates a DAQ

sequence. This is true even if the acquisition is being externally triggered

by another PFI. The output is an active high pulse with a pulse width of 50

to 100 ns. This output is set to tri-state at startup.

Figures 4-21 and 4-22 show the input and output timing requirements for

the TRIG1 signal.

Rising-edge

polarity

Falling-edge

polarity

= 10 ns minimum

Figure 4-21. TRIG1 Input Signal Timing

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= 50-100 ns

Figure 4-22. TRIG1 Output Signal Timing

The board also uses the TRIG1 signal to initiate pretriggered DAQ

operations. In most pretriggered applications, the TRIG1 signal is

generated by a software trigger. Refer to the TRIG2 signal description for

a complete description of the use of TRIG1 and TRIG2 in a pretriggered

DAQ operation.

TRIG2 Signal

Any PFI pin can externally input the TRIG2 signal, which is available as

an output on the PFI1/TRIG2 pin. Refer to Figure 4-18 for the relationship

of TRIG2 to the DAQ sequence.

As an input, the TRIG2 signal is configured in the edge-detection mode.

You can select any PFI pin as the source for TRIG2 and configure the

polarity selection for either rising or falling edge. The selected edge of the

TRIG2 signal initiates the posttriggered phase of a pretriggered acquisition

sequence. In pretriggered mode, the TRIG1 signal initiates the data

acquisition. The scan counter indicates the minimum number of scans

before TRIG2 can be recognized. After the scan counter decrements to

zero, it is loaded with the number of posttrigger scans to acquire while the

acquisition continues. The board ignores the TRIG2 signal if it is asserted

prior to the scan counter decrementing to zero. After the selected edge of

TRIG2 is received, the board will acquire a fixed number of scans and the

acquisition will stop. This mode acquires data both before and after

receiving TRIG2.

As an output, the TRIG2 signal reflects the posttrigger in a pretriggered

acquisition sequence. This is true even if the acquisition is being externally

triggered by another PFI. The TRIG2 signal is not used in posttriggered

data acquisition. The output is an active high pulse with a pulse width of

50 to 100 ns. This output is set to tri-state at startup.

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Figures 4-23 and 4-24 show the input and output timing requirements for

the TRIG2 signal.

Rising-edge

polarity

Falling-edge

polarity

= 10 ns minimum

Figure 4-23. TRIG2 Input Signal Timing

= 50-100 ns

Figure 4-24. TRIG2 Output Signal Timing

STARTSCAN Signal

Any PFI pin can externally input the STARTSCAN signal, which is

available as an output on the PFI7/STARTSCAN pin. Refer to Figures 4-17

and 4-18 for the relationship of STARTSCAN to the DAQ sequence.

As an input, the STARTSCAN signal is configured in the edge-detection

mode. You can select any PFI pin as the source for STARTSCAN and

configure the polarity selection for either rising or falling edge. The

selected edge of the STARTSCAN signal initiates a scan. The sample

interval counter starts if you select internally triggered CONVERT*.

As an output, the STARTSCAN signal reflects the actual start pulse that

initiates a scan. This is true even if the starts are being externally triggered

by another PFI. You have two output options. The first is an active high

pulse with a pulse width of 50 to 100 ns, which indicates the start of the

scan. The second action is an active high pulse that terminates at the start

of the last conversion in the scan, which indicates a scan in progress.

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STARTSCAN will be deasserted t_offafter the last conversion in the scan is

initiated. This output is set to tri-state at startup.

Figures 4-25 and 4-26 show the input and output timing requirements for

the STARTSCAN signal.

Rising-edge

polarity

Falling-edge

polarity

= 10 ns minimum

Figure 4-25. STARTSCAN Input Signal Timing

STARTSCAN

= 50-100 ns

a. Start of Scan

Start Pulse

CONVERT*

STARTSCAN

off

= 10 ns minimum

off

b. Scan in Progress, Two Conversions per Scan

Figure 4-26. STARTSCAN Output Signal Timing

The CONVERT* pulses are masked off until the board generates the

STARTSCAN signal. If you are using internally generated conversions, the

first CONVERT* appears when the onboard sample interval counter

reaches zero. If you select an external CONVERT*, the first external pulse

after STARTSCAN generates a conversion. The STARTSCAN pulses

should be separated by at least one scan period.

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A counter on your board internally generates the STARTSCAN signal

unless you select some external source. This counter is started by the

TRIG1 signal and is stopped either by software or by the sample counter.

Scans generated by either an internal or external STARTSCAN signal are

inhibited unless they occur within a DAQ sequence. Scans occurring within

a DAQ sequence may be gated by either the hardware (AIGATE) signal or

software command register gate.

CONVERT* Signal

Any PFI pin can externally input the CONVERT* signal, which is

available as an output on the PFI2/CONVERT* pin.

Refer to Figures 4-17 and 4-18 for the relationship of CONVERT* to the

DAQ sequence.

As an input, the CONVERT* signal is configured in the edge-detection

mode. You can select any PFI pin as the source for CONVERT* and

configure the polarity selection for either rising or falling edge. The

selected edge of the CONVERT* signal initiates an A/D conversion.

The ADC switches to hold mode within 60 ns of the selected edge. This

hold-mode delay time is a function of temperature and does not vary from

one conversion to the next. CONVERT* pulses should be separated by at

least 5 µs (200 kHz sample rate)

As an output, the CONVERT* signal reflects the actual convert pulse that

is connected to the ADC. This is true even if the conversions are being

externally generated by another PFI. The output is an active low pulse with

a pulse width of 50 to 150 ns. This output is set to tri-state at startup.

Figures 4-27 and 4-28 show the input and output timing requirements for

the CONVERT* signal.

Rising-edge

polarity

Falling-edge

polarity

= 10 ns minimum

Figure 4-27. CONVERT* Input Signal Timing

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= 50-150 ns

Figure 4-28. CONVERT* Output Signal Timing

The sample interval counter on the board normally generates the

CONVERT* signal unless you select some external source. The counter is

started by the STARTSCAN signal and continues to count down and reload

itself until the scan is finished. It then reloads itself in preparation for the

next STARTSCAN pulse.

A/D conversions generated by either an internal or external CONVERT*

signal are inhibited unless they occur within a DAQ sequence. Scans

occurring within a DAQ sequence may be gated by either the hardware

(AIGATE) signal or software command register gate.

AIGATE Signal

Any PFI pin can externally input the AIGATE signal, which is not

available as an output on the I/O connector. The AIGATE signal can

mask off scans in a DAQ sequence. You can configure the PFI pin you

select as the source for the AIGATE signal in either the level-detection or

edge-detection mode. You can configure the polarity selection for the

PFI pin for either active high or active low.

In the level-detection mode if AIGATE is active, the STARTSCAN signal

is masked off and no scans can occur. In the edge-detection mode, the first

active edge disables the STARTSCAN signal, and the second active edge

enables STARTSCAN.

The AIGATE signal can neither stop a scan in progress nor continue a

previously gated-off scan; in other words, once a scan has started, AIGATE

does not gate off conversions until the beginning of the next scan and,

conversely, if conversions are being gated off, AIGATE does not gate them

back on until the beginning of the next scan.

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SISOURCE Signal

Any PFI pin can externally input the SISOURCE signal, which is not

available as an output on the I/O connector. The onboard scan interval

counter uses the SISOURCE signal as a clock to time the generation of the

STARTSCAN signal. You must configure the PFI pin you select as the

source for the SISOURCE signal in the level-detection mode. You can

configure the polarity selection for the PFI pin for either active high or

active low.

The maximum allowed frequency is 20 MHz, with a minimum pulse width

of 23 ns high or low. There is no minimum frequency limitation.

Either the 20 MHz or 100 kHz internal timebase generates the SISOURCE

signal unless you select some external source. Figure 4-29 shows the

timing requirements for the SISOURCE signal.

= 50 ns minimum

= 23 ns minimum

Figure 4-29. SISOURCE Signal Timing

Waveform Generation Timing Connections

The analog group defined for your board is controlled by WFTRIG,

UPDATE*, and UISOURCE.

WFTRIG Signal

Any PFI pin can externally input the WFTRIG signal, which is available as

an output on the PFI6/WFTRIG pin.

As an input, the WFTRIG signal is configured in the edge-detection mode.

You can select any PFI pin as the source for WFTRIG and configure the

polarity selection for either rising or falling edge. The selected edge of the

WFTRIG signal starts the waveform generation for the DACs. The update

interval (UI) counter is started if you select internally generated UPDATE*.

As an output, the WFTRIG signal reflects the trigger that initiates

waveform generation. This is true even if the waveform generation is being

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externally triggered by another PFI. The output is an active high pulse with

a pulse width of 50 to 100 ns. This output is set to tri-state at startup.

Figures 4-30 and 4-31 show the input and output timing requirements for

the WFTRIG signal.

Rising-edge

polarity

Falling-edge

polarity

= 10 ns minimum

Figure 4-30. WFTRIG Input Signal Timing

= 50-100 ns

Figure 4-31. WFTRIG Output Signal Timing

UPDATE* Signal

Any PFI pin can externally input the UPDATE* signal, which is available

as an output on the PFI5/UPDATE* pin.

As an input, the UPDATE* signal is configured in the edge-detection mode.

You can select any PFI pin as the source for UPDATE* and configure the

polarity selection for either rising or falling edge. The selected edge of the

UPDATE* signal updates the outputs of the DACs. In order to use

UPDATE*, you must set the DACs to posted-update mode.

As an output, the UPDATE* signal reflects the actual update pulse that is

connected to the DACs. This is true even if the updates are being externally

generated by another PFI. The output is an active low pulse with a pulse

width of 300 to 350 ns. This output is set to tri-state at startup.

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Figures 4-32 and 4-33 show the input and output timing requirements for

the UPDATE* signal.

Rising-edge

polarity

Falling-edge

polarity

= 10 ns minimum

Figure 4-32. UPDATE* Input Signal Timing

= 300-350 ns

Figure 4-33. UPDATE* Output Signal Timing

The DACs are updated within 100 ns of the leading edge. Separate the

UPDATE* pulses with enough time that new data can be written to the

DAC latches.

The board UI counter normally generates the UPDATE* signal unless you

select some external source. The UI counter is started by the WFTRIG

signal and can be stopped by software or the internal Buffer Counter.

D/A conversions generated by either an internal or external UPDATE*

signal do not occur when gated by the software command register gate.

UISOURCE Signal

Any PFI pin can externally input the UISOURCE signal, which is not

available as an output on the I/O connector. The UI counter uses the

UISOURCE signal as a clock to time the generation of the UPDATE*

signal. You must configure the PFI pin you select as the source for the

UISOURCE signal in the level-detection mode. You can configure the

polarity selection for the PFI pin for either active high or active low.

Figure 4-34 shows the timing requirements for the UISOURCE signal.

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= 50 ns minimum

= 23 ns minimum

Figure 4-34. UISOURCE Signal Timing

The maximum allowed frequency is 20 MHz, with a minimum pulse width

of 23 ns high or low. There is no minimum frequency limitation.

Either the 20 MHz or 100 kHz internal timebase normally generates the

UISOURCE signal unless you select some external source.

General-Purpose Timing Signal Connections

The general-purpose timing signals are GPCTR0_SOURCE,

GPCTR0_GATE, GPCTR0_OUT, GPCTR0_UP_DOWN,

GPCTR1_SOURCE, GPCTR1_GATE, GPCTR1_OUT,

GPCTR1_UP_DOWN, and FREQ_OUT.

GPCTR0_SOURCE Signal

Any PFI pin can externally input the GPCTR0_SOURCE signal, which is

available as an output on the PFI8/GPCTR0_SOURCE pin.

As an input, the GPCTR0_SOURCE signal is configured in the

edge-detection mode. You can select any PFI pin as the source for

GPCTR0_SOURCE and configure the polarity selection for either rising

or falling edge.

As an output, the GPCTR0_SOURCE signal reflects the actual clock

connected to general-purpose counter 0. This is true even if another PFI

is externally inputting the source clock. This output is set to tri-state at

startup.

Figure 4-35 shows the timing requirements for the GPCTR0_SOURCE

signal.

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= 50 ns minimum

= 23 ns minimum

Figure 4-35. GPCTR0_SOURCE Signal Timing

The maximum allowed frequency is 20 MHz, with a minimum pulse width

of 23 ns high or low. There is no minimum frequency limitation.

The 20 MHz or 100 kHz timebase normally generates the

GPCTR0_SOURCE signal unless you select some external source.

GPCTR0_GATE Signal

Any PFI pin can externally input the GPCTR0_GATE signal, which is

available as an output on the PFI9/GPCTR0_GATE pin.

As an input, the GPCTR0_GATE signal is configured in the edge-detection

mode. You can select any PFI pin as the source for GPCTR0_GATE and

configure the polarity selection for either rising or falling edge. You can use

the gate signal in a variety of different applications to perform actions such

as starting and stopping the counter, generating interrupts, saving the

counter contents, and so on.

As an output, the GPCTR0_GATE signal reflects the actual gate signal

connected to general-purpose counter 0. This is true even if the gate is

being externally generated by another PFI. This output is set to tri-state at

startup.

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Figure 4-36 shows the timing requirements for the GPCTR0_GATE signal.

Rising-edge

polarity

Falling-edge

polarity

= 10 ns minimum

Figure 4-36. GPCTR0_GATE Signal Timing in Edge-Detection Mode

GPCTR0_OUT Signal

This signal is available only as an output on the GPCTR0_OUT pin. The

GPCTR0_OUT signal reflects the terminal count (TC) of general-purpose

counter 0. You have two software-selectable output options—pulse on TC

and toggle output polarity on TC. The output polarity is software-selectable

for both options. This output is set to tri-state at startup. Figure 4-37 shows

the timing of the GPCTR0_OUT signal.

GPCTR0_SOURCE

GPCTR0_OUT

(Pulse on TC)

GPCTR0_OUT

(Toggle output on TC)

Figure 4-37. GPCTR0_OUT Signal Timing

GPCTR0_UP_DOWN Signal

This signal can be externally input on the DIO6 pin and is not available as

an output on the I/O connector. The general-purpose counter 0 will count

down when this pin is at a logic low and count up when it is at a logic high.

You can disable this input so that software can control the up-down

functionality and leave the DIO6 pin free for general use.

4-45

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Chapter 4

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GPCTR1_SOURCE Signal

Any PFI pin can externally input the GPCTR1_SOURCE signal, which is

available as an output on the PFI3/GPCTR1_SOURCE pin.

As an input, the GPCTR1_SOURCE signal is configured in the

edge-detection mode. You can select any PFI pin as the source for

GPCTR1_SOURCE and configure the polarity selection for either rising or

falling edge.

As an output, the GPCTR1_SOURCE monitors the actual clock connected

to general-purpose counter 1. This is true even if the source clock is being

externally generated by another PFI. This output is set to tri-state at startup.

Figure 4-38 shows the timing requirements for the GPCTR1_SOURCE

signal.

= 50 ns minimum

= 23 ns minimum

Figure 4-38. GPCTR1_SOURCE Signal Timing

The maximum allowed frequency is 20 MHz, with a minimum pulse width

of 23 ns high or low. There is no minimum frequency limitation.

The 20 MHz or 100 kHz timebase normally generates the

GPCTR1_SOURCE unless you select some external source.

GPCTR1_GATE Signal

Any PFI pin can externally input the GPCTR1_GATE signal, which is

available as an output on the PFI4/GPCTR1_GATE pin.

As an input, the GPCTR1_GATE signal is configured in edge-detection

mode. You can select any PFI pin as the source for GPCTR1_GATE and

configure the polarity selection for either rising or falling edge. You can use

the gate signal in a variety of different applications to perform such actions

as starting and stopping the counter, generating interrupts, saving the

counter contents, and so on.

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Chapter 4

Signal Connections

As an output, the GPCTR1_GATE signal monitors the actual gate signal

connected to general-purpose counter 1. This is true even if the gate is

being externally generated by another PFI. This output is set to tri-state at

startup.

Figure 4-39 shows the timing requirements for the GPCTR1_GATE signal.

Rising-edge

polarity

Falling-edge

polarity

= 10 ns minimum

Figure 4-39. GPCTR1_GATE Signal Timing in Edge-Detection Mode

GPCTR1_OUT Signal

This signal is available only as an output on the GPCTR1_OUT pin.

The GPCTR1_OUT signal monitors the TC board general-purpose

counter 1. You have two software-selectable output options—pulse on TC

and toggle output polarity on TC. The output polarity is software-selectable

for both options. This output is set to tri-state at startup. Figure 4-40 shows

the timing requirements for the GPCTR1_OUT signal.

GPCTR1_SOURCE

GPCTR1_OUT

(Pulse on TC)

GPCTR1_OUT

(Toggle output on TC)

Figure 4-40. GPCTR1_OUT Signal Timing

GPCTR1_UP_DOWN Signal

This signal can be externally input on the DIO7 pin and is not available as

an output on the I/O connector. General-purpose counter 1 counts down

when this pin is at a logic low and counts up at a logic high. This input can

be disabled so that software can control the up-down functionality and

4-47

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Chapter 4

Signal Connections

leave the DIO7 pin free for general use. Figure 4-41 shows the timing

requirements for the GATE and SOURCE input signals and the timing

specifications for the OUT output signals of your board.

t_sc

t_sp

SOURCE

V_IL

t_gsu

t_gh

GATE

OUT

t_gw

t_out

Source Clock Period

Source Pulse Width

Gate Setup Time

Gate Hold Time

t_sc

50 ns minimum

23 ns minimum

10 ns minimum

0 ns minimum

10 ns minimum

80 ns maximum

t_sp

t_gsu

t_gh

t_gw

t_out

Gate Pulse Width

Output Delay Time

Figure 4-41. GPCTR Timing Summary

The GATE and OUT signal transitions shown in Figure 4-41 are referenced

to the rising edge of the SOURCE signal. This timing diagram assumes that

the counters are programmed to count rising edges. The same timing

diagram, but with the source signal inverted and referenced to the falling

edge of the source signal, would apply when the counter is programmed to

count falling edges.

The GATE input timing parameters are referenced to the signal at the

SOURCE input or to one of the internally generated signals on your board.

Figure 4-41 shows the GATE signal referenced to the rising edge of a

source signal. The gate must be valid (either high or low) for at least 10 ns

before the rising or falling edge of a source signal for the gate to take effect

at that source edge, as shown by t_gsuand t_ghin Figure 4-41. The gate signal

is not required to be held after the active edge of the source signal.

If you use an internal timebase clock, the gate signal cannot be

synchronized with the clock. In this case, gates applied close to a source

edge take effect either on that source edge or on the next one. This

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Chapter 4

Signal Connections

arrangement results in an uncertainty of one source clock period with

respect to unsynchronized gating sources.

The OUT output timing parameters are referenced to the signal at the

SOURCE input or to one of the internally generated clock signals on the

boards. Figure 4-41 shows the OUT signal referenced to the rising edge of

a source signal. Any OUT signal state changes occur within 80 ns after the

rising or falling edge of the source signal.

FREQ_OUT Signal

This signal is available only as an output on the FREQ_OUT pin. The

board’s frequency generator outputs the FREQ_OUT pin. The frequency

generator is a 4-bit counter that can divide its input clock by the numbers 1

through 16. The input clock of the frequency generator is

software-selectable from the internal 10 MHz and 100 kHz timebases. The

output polarity is software-selectable. This output is set to tri-state at

startup.

Field Wiring Considerations

Environmental noise can seriously affect the accuracy of measurements

made with your board if you do not take proper care when running signal

wires between signal sources and the board. The following

recommendations apply mainly to analog input signal routing to the board,

although they also apply to signal routing in general.

Minimize noise pickup and maximize measurement accuracy by taking the

following precautions:

•

Use differential analog input connections to reject common-mode

noise.

•

Use individually shielded, twisted-pair wires to connect analog input

signals to the board. With this type of wire, the signals attached to the

CH+ and CH– inputs are twisted together and then covered with a

shield. You then connect this shield only at one point to the signal

source ground. This kind of connection is required for signals traveling

through areas with large magnetic fields or high electromagnetic

interference.

•

Route signals to the board carefully. Keep cabling away from noise

sources. The most common noise source in a PCI data acquisition

system is the video monitor. Separate the monitor from the analog

signals as much as possible.

4-49

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Signal Connections

The following recommendations apply for all signal connections to your

board:

•

Separate board signal lines from high-current or high-voltage lines.

These lines can induce currents in or voltages on the board signal lines

if they run in parallel paths at a close distance. To reduce the magnetic

coupling between lines, separate them by a reasonable distance if they

run in parallel, or run the lines at right angles to each other.

•

Do not run signal lines through conduits that also contain power lines.

Protect signal lines from magnetic fields caused by electric motors,

welding equipment, breakers, or transformers by running them through

special metal conduits.

For more information, refer to the application note, Field Wiring and Noise

Consideration for Analog Signals, available from National Instruments.

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Calibration

This chapter discusses the calibration procedures for your board. If you are

using the NI-DAQ device driver, that software includes calibration

functions for performing all of the steps in the calibration process.

Calibration refers to the process of minimizing measurement and output

voltage errors by making small circuit adjustments. For these boards, these

adjustments take the form of writing values to onboard calibration DACs

(CalDACs).

Some form of board calibration is required for all but the most forgiving

applications. If you do not calibrate your board, your signals and

measurements could have very large offset, gain, and linearity errors.

Three levels of calibration are available to you and described in this chapter.

The first level is the fastest, easiest, and least accurate, whereas the last

level is the slowest, most difficult, and most accu rate.

Loading Calibration Constants

Your board is factory calibrated before shipment at approximately 25° C to

the levels indicated in Appendix A, Specifications. The associated

calibration constants—the values that were written to the CalDACs to

achieve calibration in the factory—are stored in the onboard nonvolatile

memory (EEPROM). Because the CalDACs have no memory capability,

they do not retain calibration information when the board is unpowered.

Loading calibration constants refers to the process of loading the CalDACs

with the values stored in the EEPROM. NI-DAQ software determines

when this is necessary and does it automatically. If you are not using

NI-DAQ, you must load these values yourself.

In the EEPROM there is a user-modifiable calibration area in addition to

the permanent factory calibration area. This means that you can load the

CalDACs with values either from the original factory calibration or from a

calibration that you subsequently performed.

This method of calibration is not very accurate because it does not take into

account the fact that the board measurement and output voltage errors can

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Chapter 5

Calibration

vary with time and temperature. It is better to self-calibrate when the board

is installed in the environment in which it will be used.

Self-Calibration

Your board can measure and correct for almost all of its calibration-related

errors without any external signal connections. Your National Instruments

software provides a self-calibration method. This self-calibration process,

which generally takes less than a minute, is the preferred method of

assuring accuracy in your application. Initiate self-calibration to minimize

the effects of any offset, gain, and linearity drifts, particularly those due to

warmup.

Immediately after self-calibration, the only significant residual calibration

error could be gain error due to time or temperature drift of the onboard

voltage reference. This error is addressed by external calibration, which is

discussed in the following section. If you are interested primarily in relative

measurements, you can ignore a small amount of gain error, and

self-calibration should be sufficient.

External Calibration

Your board has an onboard calibration reference to ensure the accuracy of

self-calibration. Its specifications are listed in Appendix A, Specifications.

The reference voltage is measured at the factory and stored in the EEPROM

for subsequent self-calibrations. This voltage is stable enough for most

applications, but if you are using your board at an extreme temperature or

if the onboard reference has not been measured for a year or more, you may

wish to externally calibrate your board.

An external calibration refers to calibrating your board with a known

external reference rather than relying on the onboard reference.

Redetermining the value of the onboard reference is part of this process and

the results can be saved in the EEPROM, so you should not have to perform

an external calibration very often. You can externally calibrate your board

by calling the NI-DAQ calibration function.

To externally calibrate your board, be sure to use a very accurate external

reference. The reference should be several times more accurate than the

board itself.

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Chapter 5

Calibration

Other Considerations

The CalDACs adjust the gain error of each analog output channel by

adjusting the value of the reference voltage supplied to that channel. This

calibration mechanism is designed to work only with the internal 10 V

reference. Thus, in general, it is not possible to calibrate the analog output

gain error when using an external reference. In this case, it is advisable to

account for the nominal gain error of the analog output channel either in

software or with external hardware. See Appendix A, Specifications, for

analog output gain error information.

5-3

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Specifications

This appendix lists the specifications of PCI-6023E, PCI-6024E, and

PCI-6025E boards. These specifications are typical at 25° C unless

otherwise noted.

Analog Input

Input Characteristics

Number of channels ............................... 16 single-ended or 8 differential

(software-selectable per channel)

Type of ADC.......................................... Successive approximation

Resolution .............................................. 12 bits, 1 in 4,096

Sampling rate ........................................ 200 kS/s guaranteed

Input signal ranges ................................ Bipolar only

Board Gain

(Software-Selectable)

Range

±10 V

0.5

±5 V

100

±500 mV

±50 mV

Input coupling ........................................ DC

Max working voltage

(signal + common mode) ....................... Each input should remain within

±11 V of ground

A-1

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Appendix A

Specifications

Overvoltage protection

Powered On

± 42

Powered Off

± 35

ACH<0..15>

AISENSE

± 40

± 25

FIFO buffer size......................................512 S

Data transfers..........................................DMA, interrupts,

programmed I/O

DMA modes ...........................................Scatter-gather

(Single transfer, demand transfer)

Configuration memory size ....................512 words

Accuracy Information

♦

PCI-6025E Accuracy Information

Absolute Accuracy

Relative Accuracy

Resolution (mV)

Noise + Quantization

(mV)

Temp

Drift

Nominal Range (V)

% of Reading

Offset

Positive

Negative

24 Hours

0.0722

0.0272

0.0722

90 Days

0.0742

0.0292

0.0742

1 Year

0.0764

0.0314

0.0764

(mV)

Single Pt.

± 3.906

± 1.953

± 0.195

± 0.063

Averaged

± 0.975

± 0.488

± 0.049

± 0.006

(%/° C)

0.0010

0.0005

0.0010

Theoretical

Averaged

–10

–5

± 6.385

± 3.203

± 0.340

± 0.054

4.883

2.441

0.244

0.024

1.284

0.642

0.064

0.008

0.5

0.05

–0.5

–0.05

Note: Accuracies are valid for measurements following an internal E Series Calibration. Averaged numbers assume dithering and averaging

of 100 single-channel readings. Measurement accuracies are listed for operational temperatures within ± 1 °C of internal calibration

temperature and ± 10 °C of external or factory calibration temperature.

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Appendix A

Specifications

Transfer Characteristics

Relative accuracy ................................... ±0.5 LSB typ dithered,

±1.5 LSB max undithered

DNL ....................................................... ±0.5 LSB typ, ±1.0 LSB max

No missing codes ................................... 12 bits, guaranteed

Offset error

Pregain error after calibration......... ±12 µV max

Pregain error before calibration ...... ±28 mV max

Postgain error after calibration ....... ±0.5 mV max

Postgain error before calibration..... ±100 mV max

Gain error (relative to calibration reference)

After calibration (gain = 1) ............. ±0.02% of reading max

Before calibration ........................... ±2.75% of reading max

Gain ≠ 1 with gain error

adjusted to 0 at gain = 1................. ±0.05% of reading max

Amplifier Characteristics

Input impedance

Normal powered on ........................ 100 GΩ in parallel with 100 pF

Powered off..................................... 4 kΩ min

Overload.......................................... 4 kΩ min

Input bias current ................................... ±200 pA

Input offset current................................. ±100 pA

CMRR (DC to 60 Hz)

Gain 0.5, 1.0.................................... 85 dB

Gain 10, 100.................................... 90 dB

A-3

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Appendix A

Specifications

Dynamic Characteristics

Bandwidth

Signal

Small (–3 dB)

Bandwidth

500 kHz

Large (1% THD)

225 kHz

Settling time for full scale step...............5 µs max to ±1.0 LSB accuracy

System noise (LSBrms, not including quantization)

Gain

0.5 to 10

100

Dither Off

Dither On

0.6

0.1

0.7

0.8

Crosstalk .................................................–60 dB, DC to 100 kHz

Stability

Recommended warm-up time.................15 min.

Offset temperature coefficient

Pregain.............................................±15 µV/°C

Postgain ...........................................±240 µV/°C

Gain temperature coefficient ..................±20 ppm/°C

Analog Output

♦

(PCI-6024E and PCI-6025E only)

Output Characteristics

Number of channels................................2 voltage

Resolutio n ...............................................12 bits, 1 in 4,096

Max update rate .....................................100 kHz, system dependent

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Appendix A

Specifications

Type of DAC.......................................... Double buffered, multiplying

FIFO buffer size .................................... none

Data transfers ......................................... DMA, interrupts, programmed

I/O

DMA modes........................................... Scatter-gather

(Single transfer, demand transfer)

Accuracy Information

Absolute Accuracy

Temp

Nominal Range (V)

% of Reading

Offset

Drift

Positive

Negative

24 Hours

90 Days

1 Year

(mV)

(%/° C)

–10

0.0177

0.0197

0.0219

± 5.933

0.0005

Transfer Characteristics

Relative accuracy (INL)

After calibration.............................. ± 0.3 LSB typ, ± 0.5 LSB max

Before calibration ........................... ± 4 LSB max

DNL

After calibration.............................. ± 0.3 LSB typ, ± 1.0 LSB max

Before calibration ........................... ±3 LSB max

Monotonicity.......................................... 12 bits, guaranteed after

calibration

Offset error

After calibration.............................. ± 1.0 mV max

Before calibration ........................... ± 200 mV max

Gain error (relative to internal reference)

After calibration.............................. ± 0.01% of output max

Before calibration ........................... ± 0.75% of output max

A-5

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Appendix A

Specifications

Voltage Output

Range......................................................± 10 V

Output coupling ......................................DC

Output impedance...................................0.1 Ω max

Current drive...........................................±5 mA max

Protection................................................Short-circuit to ground

Power-on state ........................................0 V

Dynamic Characteristics

Settling time for full-scale step...............10 µs to ±0.5 LSB accuracy

Slew rate .................................................10 V/µs

Noise.......................................................200 µVrms, DC to 1 MHz

Glitch energy (at midscal transition)

Magnitude.............................................. ± 12 mV

Duration........................................... 2.0 µs

Stability

Offset temperature coefficient................± 50 µV/°C

Gain temperature coefficient ..................±25 ppm /°C

Digital I/O

Number of channels

PCI-6025E.......................................32 input/output

PCI-6023E and PCI-6024E .............8 input/output

Compatibility..........................................TTL/CMOS

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Appendix A

Specifications

DIO<0..7>

Digital logic levels

Level

Min

0 V

2 V

—

Max

0.8 V

5 V

Input low voltage

Input high voltage

Input low current (V_in= 0 V)

Input high current (V_in= 5 V)

–320 µ

—

10 µA

0.4 V

—

Output low voltage (I_OL= 24 mA)

Output high voltage (I_OH= 13 mA)

—

4.35 V

Power-on state........................................ Input (High-Z),

50 kΩ pull up to ⁺5V_DC

Data transfers ......................................... Programmed I/O

PA<0..7>,PB<0..7>,PC<0..7>

PCI-6025E only

♦

Digital logic levels

Level

Min

Max

0.8 V

5 V

Input low voltage

Input high voltage

0 V

2.2 V

—

Input low current (V_in= 0 V, 100 kΩ pull up)

Input high current (V_in= 5 V, 100 kΩ pull up)

Output low voltage (I_OL= 2.5 mA)

–75 µA

10 µA

0.4 V

—

Output high voltage (I_OH= 2.5 mA)

3.7 V

Handshaking........................................... 2-wire

Power-on state

PA<0..7>................................................ Input (High-Z),

100 kΩ pull up to ⁺5V_DC

A-7

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Appendix A

Specifications

PB<0..7>.................................................Input (High-Z),

100 kΩ pull up to ⁺5V_DC

PC<0..7>.................................................Input (High-Z),

100 kΩ pull up to ⁺5V_DC

Data transfers..........................................Interrupts, programmed I/O

Timing I/O

Number of channels................................2 up/down counter/timers, 1

frequency scaler

Resolution...............................................

Counter/timers.................................24 bits

Frequency scalers ............................4 bits

Compatibility..........................................TTL/CMOS

Base clocks available

Counter/timers.................................20 MHz, 100 kHz

Frequency scalers ............................10 MHz, 100 kHz

Base clock accuracy................................±0.01%

Max source frequency.............................20 MHz

Min source pulse duration ......................10 ns in edge-detect mode

Min gate pulse duration ..........................10 ns in edge-detect mode

Data transfers..........................................DMA, interrupts, programmed

I/O

DMA modes ...........................................Scatter-gather

(Single transfer, demand transfer)

Triggers

Digital Trigger

Compatibility..........................................TTL

Response.................................................Rising or falling edge

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Appendix A

Specifications

Pulse width............................................. 10 ns min

RTSI

Trigger lines ........................................... 7

Calibration

Interval ................................................... 1 year

Onboard calibration reference

Level ............................................... 5.000 V (±3.5 mV) (actual

value stored in EEPROM)

Temperature coefficient.................. ±5 ppm/°C max

Long-term stability ......................... ±15 ppm/ 1, 000 h

Power Requirement

Physical

+5 VDC (±5%)....................................... 0.7 A

Power available at I/O connector........... +4.65 VDC to +5.25 VDC at 1 A

Dimensions (not including

connectors)............................................. 17.5 by 10.6 cm (6.9 by 4.2 in.)

I/O connector

PCI-6023E/6024E........................... 68-pin male SCSI-II type

PCI-6025E ...................................... 100-pin female 0.05D type

Operating Environment

Ambient temperature.............................. 0° to 55° C

Relative humidity................................... 10% to 90% noncondensing

Storage Environment

Ambient temperature.............................. -20° to 70° C

Relative humidity................................... 5% to 95% noncondensing

A-9

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Custom Cabling and Optional

Connectors

This appendix describes the various cabling and connector options for the

boards.

Custom Cabling

National Instruments offers cables and accessories for you to prototype

your application or to use if you frequently change board interconnections.

If you want to develop your own cable, however, the following guidelines

may be useful:

•

For the analog input signals, shielded twisted-pair wires for each

analog input pair yield the best results, assuming that you use

differential inputs. Tie the shield for each signal pair to the ground

reference at the source.

•

You should route the analog lines separately from the digital lines.

When using a cable shield, use separate shields for the analog and

digital halves of the cable. Failure to do so results in noise coupling

into the analog signals from transient digital signals.

The following list gives recommended part numbers for connectors that

mate to the I/O connector on your board.

Mating connectors and a backshell kit for making custom 68-pin cables are

available from National Instruments (part number 776832-01)

♦

PCI-6023E and PCI-6024E

Honda 68-position, solder cup, female connector

(part number PCS-E68FS)

Honda backshell (part number PCS-E68LKPA)

B-1

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Appendix B

Custom Cabling and Optional Connectors

♦

PCI-6025E

AMP 100-position IDC male connector (part number 1-750913-9)

AMP backshell, 0.50 max O.D. cable (part number 749081-1)

AMP backshell, 0.55 max O.D. cable, (part number 749854-1)

Optional Connectors

Figure B-1 shows the pin assignments for the 68-pin E Series connector.

This connector is available when you use the SH6868 or R6868 cable

assemblies with the PCI-6023E and PCI-6024E. It is also the MIO-16

68-pin connector available when you use the SH1006868 cable assembly

with the PCI-6025E.

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Appendix B

Custom Cabling and Optional Connectors

34 68

ACH1 33 67

ACH8

ACH0

AIGND

ACH9

32 66

31 65

30 64

29 63

28 62

AIGND

ACH10

ACH3

ACH2

AIGND

ACH11

AISENSE

ACH12

ACH5

AIGND

ACH4

AIGND 27 61

ACH13 26 60

ACH6

AIGND 24 58

25 59

AIGND

ACH14

ACH7

ACH15

23 57

22 56

21 55

DAC0OUT¹

DAC1OUT¹

AIGND

AOGND

DGND

DIO0

RESERVED 20 54

19 53

18 52

17 51

16 50

15 49

DIO4

DGND

DIO1

DIO5

DIO6

DGND

DIO2

DGND

+5 V 14 48

DGND 13 47

DGND 12 46

DIO7

DIO3

SCANCLK

PFI0/TRIG1

11 45

10 44

EXTSTROBE*

DGND

PFI1/TRIG2

DGND

PFI2/CONVERT*

PFI3/GPCTR1_SOURCE

PFI4/GPCTR1_GATE

GPCTR1_OUT

DGND

+5 V

DGND

PFI5/UPDATE*

PFI6/WFTRIG

DGND

PFI7/STARTSCAN

PFI8/GPCTR0_SOURCE

DGND

PFI9/GPCTR0_GATE

GPCTR0_OUT

FREQ_OUT

DGND

¹Not available on the PCI-6023E

Figure B-1. 68-Pin E Series Connector Pin Assignments

B-3

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Appendix B

Custom Cabling and Optional Connectors

Figure B-2 shows the pin assignments for the 68-pin extended digital input

connector. This is the other 68-pin connector available when you use the

SH1006868 cable assembly with the PCI-6025E.

34 68

PC6 33 67

GND

PC7

GND

PC4

GND

PC1

GND

PB6

32 66

31 65

30 64

29 63

28 62

PC5

GND

PC3

PC2

GND

PC0 27 61

PB7 26 60

GND

PB5 24 58

25 59

GND

PB3

PB4

23 57

22 56

21 55

GND

PB2

PB1 20 54

GND

PA7

19 53

18 52

17 51

16 50

15 49

PB0

GND

PA6

GND

PA5

GND

PA4

GND

PA3 14 48

PA2 13 47

GND 12 46

GND

PA1

GND

N/C

PA0

+5 V

N/C

11 45

10 44

N/C

Figure B-2. 68-Pin Extended Digital Input Connector Pin Assignments

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Appendix B

Custom Cabling and Optional Connectors

Figure B-3 shows the pin assignments for the 50-pin E Series connector.

This connector is available when you use the SH6850 or R6850 cable

assemblies with the PCI-6023E and PCI-6024E. It is also one of the two

50-pin connectors available when you use the RI005050 cable assembly

with the PCI-6025E.

AIGND

ACH0

ACH1

AIGND

ACH8

ACH9

ACH10

ACH11

ACH12

ACH13

ACH14

ACH2

ACH3

11 12

13 14

15 16

17 18

19 20

21 22

23 24

25 26

27 28

29 30

31 32

33 34

ACH4

ACH5

ACH6

ACH7

ACH15

DAC0OUT¹

RESERVED

AISENSE

DAC1OUT¹

AOGND

DIO0

DGND

DIO4

DIO1

DIO5

DIO2

DIO6

DIO3

DIO7

DGND

+5 V

+5 V 35 36

SCANCLK

PFI0/TRIG1

PFI2/CONVERT*

PFI4/GPCTR1_GATE

PFI5/UPDATE*

PFI7/STARTSCAN

PFI9/GPCTR0_GATE

FREQ_OUT

37 38

39 40

41 42

43 44

45 46

47 48

49 50

EXTSTROBE*

PFI1/TRIG2

PFI3/GPCTR1_SOURCE

GPCTR1_OUT

PFI6/WFTRIG

PFI8/GPCTR0_SOURCE

GPCTR0_OUT

¹Not available on the PCI-6023E

Figure B-3. 50-Pin E Series Connector Pin Assignments

B-5

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Appendix B

Custom Cabling and Optional Connectors

Figure B-4 shows the pin assignments for the 50-pin extended digital input

connector. This is the other 50-pin connector available when you use the

R1005050 cable assembly with the PCI-6025E.

PC7

PC6

PC5

PC4

PC3

GND

11 12

13 14

15 16

17 18

19 20

21 22

23 24

25 26

27 28

29 30

31 32

33 34

PC2

PC1

PC0

PB7

PB6

PB5

PB4

PB3

PB2

PB1

PB0

PA7

GND

PA6 35 36

37 38

39 40

41 42

43 44

45 46

47 48

49 50

PA5

PA4

PA3

PA2

PA1

PA0

+5 V

Figure B-4. 50-Pin Extended Digital Input Connector Pin Assignments

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Common Questions

This appendix contains a list of commonly asked questions and their

answers relating to usage and special features of your board.

General Information

What is the DAQ-STC?

The DAQ-STC is the System Timing Control application-specific

integrated circuit (ASIC) designed by National Instruments and is the

backbone of the PCI E Series boards. The DAQ-STC contains seven 24-bit

counters and three 16-bit counters. The counters are divided into the

following three groups:

•

Analog input—two 24-bit, two 16-bit counters

Analog output—three 24-bit, one 16-bit counters

General-purpose counter/timer functions—two 24-bit counters

The groups can be configured independently with timing resolutions of

50 ns or 10 µs. With the DAQ-STC, you can interconnect a wide variety of

internal timing signals to other internal blocks. The interconnection scheme

is quite flexible and completely software configurable. New capabilities

such as buffered pulse generation, equivalent time sampling, and seamless

changing of the sampling rate are possible.

What does sampling rate mean to me?

It means that this is the fastest you can acquire data on your board and

still achieve accurate results. For example, these boards have a sampling

rate of 200 kS/s. This sampling rate is aggregate: one channel at 200 kS/s

or two channels at 100 kS/s per channel illustrates the relationship.

What type of 5 V protection do the boards have?

The boards have 5 V lines equipped with a self-resetting 1 A fuse.

C-1

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Appendix C

Common Questions

Installation and Configuration

How do I set the base address for a my board?

The base address of your board is assigned automatically through the PCI

bus protocol. This assignment is completely transparent to you.

What jumpers should I be aware of when configuring my PCI E Series

board?

The PCI E Series boards are jumperless and switchless.

Which National Instruments document should I read first to get

started using DAQ software?

Your NI-DAQ or application software release notes documentation is

always the best starting place.

Analog Input and Output

I’m using my board in differential analog input mode and I have

connected a differential input signal, but my readings are random and

drift rapidly. What’s wrong?

Check your ground reference connections. Your signal may be referenced

to a level that is considered floating with reference to the board ground

reference. Even if you are in differential mode, the signal must still be

referenced to the same ground level as the board reference. There are

various methods of achieving this while maintaining a high common-mode

rejection ratio (CMRR). These methods are outlined in Chapter 4, Signal

Connections.

I’m using the DACs to generate a waveform, but I discovered with a

digital oscilloscope that there are glitches on the output signal. Is this

normal?

When it switches from one voltage to another, any DAC produces glitches

due to released charges. The largest glitches occur when the most

significant bit (MSB) of the D/A code switches. You can build a lowpass

deglitching filter to remove some of these glitches, depending on the

frequency and nature of your output signal.

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Appendix C

Common Questions

Can I synchronize a one-channel analog input data acquisition with a

one-channel analog output waveform generation on my PCI E Series

board?

Yes. One way to accomplish this is to use the waveform generation timing

pulses to control the analog input data acquisition. To do this, follow steps

1 through 4 below, in addition to the usual steps for data acquisition and

waveform generation configuration.

1. Enable the PFI5 line for output, as follows:

•

If you are using NI-DAQ, call

Select_Signal(deviceNumber,ND_PFI_5,

ND_OUT_UPDATE,ND_HIGH_TO_LOW).

•

If you are using LabVIEW, invoke Route Signal VI with signal

name set to PFI5 and signal source set to AO Update.

2. Set up data acquisition timing so that the timing signal for A/D

conversion comes from PFI5, as follows:

•

If you are using NI-DAQ, call

Select_Signal(deviceNumber,ND_IN_CONVERT,

ND_PFI_5,ND_HIGH_TO_LOW).

•

If you are using LabVIEW, invoke AI Clock Config VI with clock

source code set to PFI pin, high to low, and clock source string set

to 5.

3. Initiate analog input data acquisition, which will start only when the

analog output waveform generation starts.

4. Initiate analog output waveform generation.

Timing and Digital I/O

What types of triggering can be hardware-implemented on my board?

Digital triggering is hardware-supported on every board.

Will the counter/timer applications that I wrote previously work with

the DAQ-STC?

If you are using NI-DAQ with LabVIEW, some of your applications drawn

using the CTR VIs will still run. However, there are many differences in the

counters between the PCI E Series and other boards; the counter numbers

are different, timebase selections are different, and the DAQ-STC counters

C-3

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Appendix C

Common Questions

are 24-bit counters (unlike the 16-bit counters on boards without the

DAQ-STC).

If you are using the NI-DAQ language interface or LabWindows/CVI, the

answer is no, the counter/timer applications that you wrote previously will

not work with the DAQ-STC. You must use the GPCTR functions; ICTR

and CTR functions will not work with the DAQ-STC. The GPCTR

functions have the same capabilities as the ICTR and CTR functions, plus

more, but you must rewrite the application with the GPCTR function calls.

I’m using one of the general-purpose counter/timers on my board, but

I do not see the counter/timer output on the I/O connector. What am I

doing wrong?

If you are using the NI-DAQ language interface or LabWindows/CVI, you

must configure the output line to output the signal to the I/O connector. Use

the Select_Signalcall in NI-DAQ to configure the output line. By

default, all timing I/O lines except EXTSTROBE* are tri-stated.

What are the PFIs and how do I configure these lines?

PFIs are Programmable Function Inputs. These lines serve as connections

to virtually all internal timing signals.

If you are using the NI-DAQ language interface or LabWindows/CVI, use

the Select_Signalfunction to route internal signals to the I/O connector,

route external signals to internal timing sources, or tie internal timing

signals together.

If you are using NI-DAQ with LabVIEW and you want to connect external

signal sources to the PFI lines, you can use AI Clock Config, AI Trigger

Config, AO Clock Config, AO Trigger and Gate Config, CTR Mode

Config, and CTR Pulse Config advanced level VIs to indicate which

function the connected signal will serve. Use the Route Signal VI to enable

the PFI lines to output internal signals.

Caution

If you enable a PFI line for output, do not connect any external signal source to

it; if you do, you can damage the board, the computer, and the connected

equipment.

What are the power-on states of the PFI and DIO lines on the I/O

connector?

At system power-on and reset, both the PFI and DIO lines are set to high

impedance by the hardware. This means that the board circuitry is not

actively driving the output either high or low. However, these lines

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Appendix C

Common Questions

may have pull-up or pull-down resistors connected to them as shown in

Table 4-2. These resistors weakly pull the output to either a logic high or

logic low state. For example, DIO(0) will be in the high impedance state

after power on, and Table 4-2 shows that there is a 50 kΩ pull-up resistor.

This pull-up resistor will set the DIO(0) pin to a logic high when the output

is in a high impedance state.

C-5

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Customer Communication

For your convenience, this appendix contains forms to help you gather the information necessary

to help us solve your technical problems and a form you can use to comment on the product

documentation. When you contact us, we need the information on the Technical Support Form and

the configuration form, if your manual contains one, about your system configuration to answer your

questions as quickly as possible.

National Instruments has technical assistance through electronic, fax, and telephone systems to quickly

provide the information you need. Our electronic services include a bulletin board service, an FTP site,

a fax-on-demand system, and e-mail support. If you have a hardware or software problem, first try the

electronic support systems. If the information available on these systems does not answer your

questions, we offer fax and telephone support through our technical support centers, which are staffed

by applications engineers.

Electronic Services

Bulletin Board Support

National Instruments has BBS and FTP sites dedicated for 24-hour support with a collection of files

and documents to answer most common customer questions. From these sites, you can also download

the latest instrument drivers, updates, and example programs. For recorded instructions on how to use

the bulletin board and FTP services and for BBS automated information, call 512 795 6990. You can

access these services at:

United States: 512 794 5422

Up to 14,400 baud, 8 data bits, 1 stop bit, no parity

United Kingdom: 01635 551422

Up to 9,600 baud, 8 data bits, 1 stop bit, no parity

France: 01 48 65 15 59

Up to 9,600 baud, 8 data bits, 1 stop bit, no parity

FTP Support

To access our FTP site, log on to our Internet host, ftp.natinst.com, as anonymousand use

your Internet address, such as [email protected], as your password. The support files and

documents are located in the /supportdirectories.

D-1

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Fax-on-Demand Support

Fax-on-Demand is a 24-hour information retrieval system containing a library of documents on a wide

range of technical information. You can access Fax-on-Demand from a touch-tone telephone at

512 418 1111.

E-Mail Support (Currently USA Only)

You can submit technical support questions to the applications engineering team through e-mail at the

Internet address listed below. Remember to include your name, address, and phone number so we can

contact you with solutions and suggestions.

[email protected]

Telephone and Fax Support

National Instruments has branch offices all over the world. Use the list below to find the technical

support number for your country. If there is no National Instruments office in your country, contact

the source from which you purchased your software to obtain support.

Country

Telephone

Fax

Australia

Austria

Belgium

Brazil

Canada (Ontario)

Canada (Québec)

Denmark

Finland

03 9879 5166

0662 45 79 90 0

02 757 00 20

011 288 3336

905 785 0085

514 694 8521

45 76 26 00

09 725 725 11

01 48 14 24 24

089 741 31 30

2645 3186

03 6120092

02 413091

03 5472 2970

02 596 7456

5 520 2635

03 9879 6277

0662 45 79 90 19

02 757 03 11

011 288 8528

905 785 0086

514 694 4399

45 76 26 02

09 725 725 55

01 48 14 24 14

089 714 60 35

2686 8505

France

Germany

Hong Kong

Israel

Italy

Japan

03 6120095

02 41309215

03 5472 2977

02 596 7455

5 520 3282

Korea

Mexico

Netherlands

Norway

Singapore

Spain

Sweden

Switzerland

Taiwan

0348 433466

32 84 84 00

2265886

91 640 0085

08 730 49 70

056 200 51 51

02 377 1200

01635 523545

512 795 8248

0348 430673

32 84 86 00

2265887

91 640 0533

08 730 43 70

056 200 51 55

02 737 4644

01635 523154

512 794 5678

United Kingdom

United States

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Technical Support Form

Photocopy this form and update it each time you make changes to your software or hardware, and use

the completed copy of this form as a reference for your current configuration. Completing this form

accurately before contacting National Instruments for technical support helps our applications

engineers answer your questions more efficiently.

If you are using any National Instruments hardware or software products related to this problem,

include the configuration forms from their user manuals. Include additional pages if necessary.

Name __________________________________________________________________________

Company _______________________________________________________________________

Address ________________________________________________________________________

_______________________________________________________________________________

Fax ( ___ ) ________________Phone ( ___ ) __________________________________________

Computer brand____________ Model ___________________Processor_____________________

Operating system (include version number) ____________________________________________

Clock speed ______MHz RAM _____MB

Display adapter __________________________

Mouse ___yes ___no Other adapters installed_______________________________________

Hard disk capacity _____MB Brand_________________________________________________

Instruments used _________________________________________________________________

_______________________________________________________________________________

National Instruments hardware product model _____________ Revision ____________________

Configuration ___________________________________________________________________

National Instruments software product ___________________ Version _____________________

Configuration ___________________________________________________________________

The problem is: __________________________________________________________________

_______________________________________________________________________________

List any error messages: ___________________________________________________________

_______________________________________________________________________________

The following steps reproduce the problem: ___________________________________________

_______________________________________________________________________________

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PCI-6023E/6024E/6025E Hardware and Software

Configuration Form

Record the settings and revisions of your hardware and software on the line to the right of each item.

Complete a new copy of this form each time you revise your software or hardware configuration, and

use this form as a reference for your current configuration. Completing this form accurately before

contacting National Instruments for technical support helps our applications engineers answer your

questions more efficiently.

National Instruments Products

Hardware revision _______________________________________________________________

Interrupt level of hardware _________________________________________________________

DMA channels of hardware ________________________________________________________

Base I/O address of hardware _______________________________________________________

Programming choice _____________________________________________________________

National Instruments software ______________________________________________________

Other boards in system ____________________________________________________________

Base I/O address of other boards ____________________________________________________

DMA channels of other boards _____________________________________________________

Interrupt level of other boards ______________________________________________________

Other Products

Computer make and model ________________________________________________________

Microprocessor __________________________________________________________________

Clock frequency or speed __________________________________________________________

Type of video board installed _______________________________________________________

Operating system version __________________________________________________________

Operating system mode ___________________________________________________________

Programming language ___________________________________________________________

Programming language version _____________________________________________________

Other boards in system ____________________________________________________________

Base I/O address of other boards ____________________________________________________

DMA channels of other boards _____________________________________________________

Interrupt level of other boards ______________________________________________________

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Documentation Comment Form

National Instruments encourages you to comment on the documentation supplied with our products.

This information helps us provide quality products to meet your needs.

Title:

PCI-6023E/6024E/6025E User Manual

Edition Date: October 1998

Part Number: 322072A-01

Please comment on the completeness, clarity, and organization of the manual.

_______________________________________________________________________________

If you find errors in the manual, please record the page numbers and describe the errors.

_______________________________________________________________________________

Thank you for your help.

Name _________________________________________________________________________

Title __________________________________________________________________________

Company _______________________________________________________________________

Address ________________________________________________________________________

_______________________________________________________________________________

E-Mail Address __________________________________________________________________

Phone ( ___ ) __________________________ Fax ( ___ ) _______________________________

Mail to: Technical Publications

National Instruments Corporation

Fax to: Technical Publications

National Instruments Corporation

512 794 5678

6504 Bridge Point Parkway

Austin, Texas 78730-5039

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Glossary

Prefix

Meanings

pico

Value

10^–12

10^–9

10^{– 6}

10^–3

10³

nano-

micro-

milli-

kilo-

µ-

M-

G-

mega-

giga-

10⁶

10⁹

tera-

10¹²

Numbers/Symbols

–

percent

positive of, or plus

negative of, or minus

per

degree

ohm

Ω

amperes

alternating current

AC coupled

ACH

allowing the transmission of AC signals while blocking DC signals

analog input channel signal

G-1

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Glossary

A/D

analog-to-digital

ADC

analog-to-digital converter—an electronic device, often an integrated

circuit, that converts an analog voltage to a digital number

ADC resolution

the resolution of the ADC, which is measured in bits. An ADC with 16 bits

has a higher resolution, and thus a higher degree of accuracy, than a 12-bit

ADC.

analog input

AIGATE

AIGND

AISENSE

alias

analog input gate signal

analog input ground signal

analog input sense signal

a false lower frequency component that appears in sampled data acquired

at too low a sampling rate

amplification

a type of signal conditioning that improves accuracy in the resulting

digitized signal and reduces noise

ANSI

American National Standards Institute

analog output

AOGND

ASIC

analog output ground signal

Application-Specific Integrated Circuit—a proprietary semiconductor

component designed and manufactured to perform a set of specific

functions for a specific customer

asynchronous

attenuate

(1) hardware—a property of an event that occurs at an arbitrary time,

without synchronization to a reference clock (2) software—a property of a

function that begins an operation and returns prior to the completion or

termination of the operation

to decrease the amplitude of a signal

bandwidth

the range of frequencies present in a signal, or the range of frequencies to

which a measuring device can respond

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Glossary

base address

BIOS

a memory address that serves as the starting address for programmable

registers. All other addresses are located by adding to the base address.

basic input/output system—BIOS functions are the fundamental level of

any PC or compatible computer. BIOS functions embody the basic

operations needed for successful use of the computer’s hardware resources.

bipolar

a signal range that includes both positive and negative values (for example,

–5 V to +5 V)

breakdown voltage

burst-mode

bus

the voltage high enough to cause breakdown of optical isolation,

semiconductors, or dielectric materials. See also working voltage.

a high-speed data transfer in which the address of the data is sent followed

by back-to-back data words while a physical signal is asserted

the group of conductors that interconnect individual circuitry in a computer.

Typically, a bus is the expansion vehicle to which I/O or other devices are

connected. Examples of PC buses are the ISA and PCI bus.

bus master

a type of a plug-in board or controller with the ability to read and write

devices on the computer bus

Celsius

CalDAC

calibration DAC

channel—pin or wire lead to which you apply or from which you read the

analog or digital signal. Analog signals can be single-ended or differential.

For digital signals, you group channels to form ports. Ports usually consist

of either four or eight digital channels.

channel clock

CMRR

the clock controlling the time interval between individual channel sampling

within a scan. Boards with simultaneous sampling do not have this clock.

common-mode rejection ratio—a measure of an instrument’s ability to

reject interference from a common-mode signal, usually expressed in

decibels (dB)

cold-junction

compensation

a method of compensating for inaccuracies in thermocouple circuits

G-3

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Glossary

common-mode range

common-mode signal

the input range over which a circuit can handle a common-mode signal

the mathematical average voltage, relative to the computer’s ground, of the

signals from a differential input

conversion time

the time required, in an analog input or output system, from the moment a

channel is interrogated (such as with a read instruction) to the moment that

accurate data is available

CONVERT*

counter/timer

crosstalk

convert signal

a circuit that counts external pulses or clock pulses (timing)

an unwanted signal on one channel due to an input on a different channel

counter

CTR

current drive capability

the amount of current a digital or analog output channel is capable of

sourcing or sinking while still operating within voltage range specifications

current sinking

current sourcing

the ability of a DAQ board to dissipate current for analog or digital output

signals

the ability of a DAQ board to supply current for analog or digital output

signals

D/A

digital-to-analog

DAC

digital-to-analog converter—an electronic device, often an integrated

circuit, that converts a digital number into a corresponding analog voltage

or current

DAC0OUT

DAC1OUT

DAQ

analog channel 0 output signal

analog channel 1 output signal

data acquisition—(1) collecting and measuring electrical signals from

sensors, transducers, and test probes or fixtures and inputting them to a

computer for processing; (2) collecting and measuring the same kinds of

electrical signals with A/D and/or DIO boards plugged into a computer, and

possibly generating control signals with D/A and/or DIO boards in the

same computer

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Glossary

decibel—the unit for expressing a logarithmic measure of the ratio of two

signal levels: dB=20log10 V1/V2, for signals in volts

direct current

DC coupled

DGND

allowing the transmission of both AC and DC signals

digital ground signal

DIFF

differential mode

differential input

an analog input consisting of two terminals, both of which are isolated from

computer ground, whose difference is measured

digital port

DIN

See port.

Deutsche Industrie Norme

digital input/output

DIO

dithering

DMA

the addition of Gaussian noise to an analog input signal

direct memory access—a method by which data can be transferred to/from

computer memory from/to a device or memory on the bus while the

processor does something else. DMA is the fastest method of transferring

data to/from computer memory.

DNL

differential nonlinearity—a measure in least significant bit of the

worst-case deviation of code widths from their ideal value of 1 LSB

digital output

drivers

software that controls a specific hardware device such as a DAQ board or

a GPIB interface board

EEPROM

electrically erasable programmable read-only memory—ROM that can be

erased with an electrical signal and reprogrammed

electrostatically coupled propagating a signal by means of a varying electric field

external trigger

a voltage pulse from an external source that triggers an event such as A/D

conversion

G-5

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Glossary

EXTSTROBE

external strobe signal

FIFO

first-in first-out memory buffer—the first data stored is the first data sent to

the acceptor. FIFOs are often used on DAQ devices to temporarily store

incoming or outgoing data until that data can be retrieved or output. For

example, an analog input FIFO stores the results of A/D conversions until

the data can be retrieved into system memory, a process that requires the

servicing of interrupts and often the programming of the DMA controller.

This process can take several milliseconds in some cases. During this time,

data accumulates in the FIFO for future retrieval. With a larger FIFO,

longer latencies can be tolerated. In the case of analog output, a FIFO

permits faster update rates, because the waveform data can be stored on the

FIFO ahead of time. This again reduces the effect of latencies associated

with getting the data from system memory to the DAQ device.

filtering

a type of signal conditioning that allows you to filter unwanted signals from

the signal you are trying to measure

floating signal sources

signal sources with voltage signals that are not connected to an absolute

reference or system ground. Also called nonreferenced signal sources.

Some common example of floating signal sources are batteries,

transformers, or thermocouples.

FREQ_OUT

frequency output signal

feet

gain

the factor by which a signal is amplified, sometimes expressed in decibels

a measure of deviation of the gain of an amplifier from the ideal gain

gate signal

gain accuracy

GATE

glitch

an unwanted momentary deviation from a desired signal

general purpose counter

GPCTR

GPCTR0_GATE

general purpose counter 0 gate signal

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Glossary

GPCTR0_OUT

general purpose counter 0 output signal

general purpose counter 0 clock source signal

general purpose counter 0 up down

GPCTR0_SOURCE

GPCTR0_UP_DOWN

GPCTR1_GATE

GPCTR1_OUT

general purpose counter 1 gate signal

general purpose counter 1 output signal

general purpose counter 1 clock source signal

general purpose counter 1 up down

GPCTR1_SOURCE

GPCTR1_UP_DOWN

GPIB

General Purpose Interface bus, synonymous with HP-IB. The standard bus

used for controlling electronic instruments with a computer. Also called

IEEE 488 bus because it is defined by ANSI/IEEE Standards 488-1978,

488.1-1987, and 488.2-1987.

grounded measurement See referenced single-ended measurement system.

system

hour

half-power bandwidth

the frequency range over which a circuit maintains a level of at least –3 dB

with respect to the maximum level

handshaked digital I/O

a type of digital acquisition/generation where a device or module accepts

or transfers data after a digital pulse has been received. Also called latched

digital I/O.

hex

hexadecimal

hertz—the number of events per second

in.

inches

INL

integral nonlinearity—a measure in LSB of the worst-case deviation from

the ideal A/D or D/A transfer characteristic of the analog I/O circuitry

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Glossary

input bias current

input impedance

input offset current

the current that flows into the inputs of a circuit

the resistance and capacitance between the input terminals of a circuit

the difference in the input bias currents of the two inputs of an

instrumentation amplifier

instrument driver

a set of high-level software functions that controls a specific GPIB, VXI,

or RS-232 programmable instrument or a specific plug-in DAQ board.

Instrument drivers are available in several forms, ranging from a function

callable language to a virtual instrument (VI) in LabVIEW.

instrumentation

amplifier

a circuit whose output voltage with respect to ground is proportional to the

difference between the voltages at its two high impedance inputs

interrupt

a computer signal indicating that the CPU should suspend its current task

to service a designated activity

interrupt level

the relative priority at which a device can interrupt

interval scanning

scanning method where there is a longer interval between scans than there

is between individual channels comprising a scan

I/O

input/output—the transfer of data to/from a computer system involving

communications channels, operator interface devices, and/or data

acquisition and control interfaces

I_OH

I_OL

current, output high

current, output low

interrupt request

IRQ

kilo—the standard metric prefix for 1,000, or 10³, used with units of

measure such as volts, hertz, and meters

kilo—the prefix for 1,024, or 2¹⁰, used with B in quantifying data or

computer memory

1,000 samples

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Glossary

LabVIEW

laboratory virtual instrument engineering workbench

light-emitting diode

LED

library

a file containing compiled object modules, each comprised of one of more

functions, that can be linked to other object modules that make use of these

functions. NIDAQMSC.LIB is a library that contains NI-DAQ functions.

The NI-DAQ function set is broken down into object modules so that only

the object modules that are relevant to your application are linked in, while

those object modules that are not relevant are not linked.

linearity

LSB

the adherence of device response to the equation R = KS, where

R = response, S = stimulus, and K = a constant

least significant bit

MIO

multifunction I/O

MITE

MXI Interface to Everything—a custom ASIC designed by National

Instruments that implements the PCI bus interface. The MITE supports bus

mastering for high-speed data transfers over the PCI bus.

million samples

MSB

mux

most significant bit

multiplexer—a switching device with multiple inputs that sequentially

connects each of its inputs to its output, typically at high speeds, in order to

measure several signals with a single analog input channel

normally closed, or not connected

NI-DAQ

National Instruments driver software for DAQ hardware

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Glossary

noise

an undesirable electrical signal—Noise comes from external sources such

as the AC power line, motors, generators, transformers, fluorescent lights,

soldering irons, CRT displays, computers, electrical storms, welders, radio

transmitters, and internal sources such as semiconductors, resistors, and

capacitors. Noise corrupts signals you are trying to send or receive.

nonlatched digital I/O

a type of digital acquisition/generation where LabVIEW updates the digital

lines or port states immediately or returns the digital value of an input line.

Also called immediate digital I/O or non-handshaking.

nonreferenced signal

sources

signal sources with voltage signals that are not connected to an absolute

reference or system ground. Also called floating signal sources. Some

common example of nonreferenced signal sources are batteries,

transformers, or thermocouples.

NRSE

nonreferenced single-ended mode—all measurements are made with

respect to a common (NRSE) measurement system reference, but the

voltage at this reference can vary with respect to the measurement system

ground

OUT

output pin—a counter output pin where the counter can generate various

TTL pulse waveforms

output settling time

output slew rate

the amount of time required for the analog output voltage to reach its final

value within specified limits

the maximum rate of change of analog output voltage from one level to

another

PCI

Peripheral Component Interconnect—a high-performance expansion bus

architecture originally developed by Intel to replace ISA and EISA. It is

achieving widespread acceptance as a standard for PCs and work-stations;

it offers a theoretical maximum transfer rate of 132 Mbytes/s.

peak to peak

PFI

a measure of signal amplitude; the difference between the highest and

lowest excursions of the signal

programmable function input

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PFI0/TRIG1

PFI0/trigger 1

PFI1/TRIG2

PFI1/trigger 2

PFI2/CONVERT*

PFI2/convert

PFI3/GPCTR1_

SOURCE

PFI3/general purpose counter 1 source

PFI4/GPCTR1_GATE

PFI5/UPDATE*

PFI4/general purpose counter 1 gate

PFI5/update

PFI6/WFTRIG

PFI6/waveform trigger

PFI7/STARTSCAN

PFI7/start of scan

PFI8/GPCTR0_

SOURCE

PFI8/general purpose counter 0 source

PFI9/GPCTR0_GATE

PGIA

PFI9/general purpose counter 0 gate

programmable gain instrumentation amplifier

Plug and Play devices

devices that do not require DIP switches or jumpers to configure resources

on the devices—also called switchless devices

port

(1) a communications connection on a computer or a remote controller

(2) a digital port, consisting of four or eight lines of digital input and/or

output

posttriggering

the technique used on a DAQ board to acquire a programmed number of

samples after trigger conditions are met

PPI

programmable peripheral interface

parts per million

ppm

pretriggering

the technique used on a DAQ board to keep a continuous buffer filled with

data, so that when the trigger conditions are met, the sample includes the

data leading up to the trigger condition

pts

points

pullup

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Glossary

pulse trains

multiple pulses

pulsed output

a form of counter signal generation by which a pulse is outputted when a

counter reaches a certain value

quantization error

the inherent uncertainty in digitizing an analog value due to the finite

resolution of the conversion process

RAM

random-access memory

real time

a property of an event or system in which data is processed as it is acquired

instead of being accumulated and processed at a later time

referenced signal

sources

signal sources with voltage signals that are referenced to a system ground,

such as the earth or a building ground. Also called grounded signal sources.

relative accuracy

a measure in LSB of the accuracy of an ADC. It includes all non-linearity

and quantization errors. It does not include offset and gain errors of the

circuitry feeding the ADC.

resolution

the smallest signal increment that can be detected by a measurement

system. Resolution can be expressed in bits, in proportions, or in percent of

full scale. For example, a system has 12-bit resolution, one part in 4,096

resolution, and 0.0244% of full scale.

ribbon cable

rise time

a flat cable in which the conductors are side by side

the difference in time between the 10% and 90% points of a system’s step

response

rms

root mean square—the square root of the average value of the square of the

instantaneous signal amplitude; a measure of signal amplitude

RSE

referenced single-ended mode—all measurements are made with respect

to a common reference measurement system or a ground. Also called a

grounded measurement system.

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Glossary

RTSI bus

real-time system integration bus—the National Instruments timing bus that

connects DAQ boards directly, by means of connectors on top of the boards,

for precise synchronization of functions

seconds

samples

sample counter

the clock that counts the output of the channel clock, in other words, the

number of samples taken. On boards with simultaneous sampling, this

counter counts the output of the scan clock and hence the number of scans.

scan

one or more analog or digital input samples. Typically, the number of input

samples in a scan is equal to the number of channels in the input group. For

example, one pulse from the scan clock produces one scan which acquires

one new sample from every analog input channel in the group.

scan clock

scan rate

the clock controlling the time interval between scans.

the number of scans per second. For example, a scan rate of 10 Hz means

sampling each channel 10 times per second.

SCXI

Signal Conditioning eXtensions for Instrumentation—the National

Instruments product line for conditioning low-level signals within an

external chassis near sensors so only high-level signals are sent to DAQ

boards in the noisy PC environment

single-ended—a term used to describe an analog input that is measured

with respect to a common ground

self-calibrating

a property of a DAQ board that has an extremely stable onboard reference

and calibrates its own A/D and D/A circuits without manual adjustments by

the user

sensor

a device that responds to a physical stimulus (heat, light, sound, pressure,

motion, flow, and so on), and produces a corresponding electrical signal

settling time

the amount of time required for a voltage to reach its final value within

specified limits

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Glossary

Shannon Sampling

Theorem

a law of sampling theory stating that if a continuous bandwidth-limited

signal contains no frequency components higher than half the frequency

at which it is sampled, then the original signal can be recovered without

distortion

S/H

sample-and-hold—a circuit that acquires and stores an analog voltage on a

capacitor for a short period of time

signal conditioning

SISOURCE

SNR

the manipulation of signals to prepare them for digitizing

SI counter clock signal

signal-to-noise ratio—the ratio of the overall rms signal level to the rms

noise level, expressed in decibels

software trigger

a programmed event that triggers an event such as data acquisition

software triggering

a method of triggering in which you simulate an analog trigger using

software. Also called conditional retrieval.

SOURCE

source signal

simultaneous sampling—a property of a system in which each input or

output channel is digitized or updated at the same instant

S/s

samples per second—used to express the rate at which a DAQ board

samples an analog signal

STARTSCAN

STC

start scan signal

system timing controller

switchless device

devices that do not require dip switches or jumpers to configure resources

on the devices—also called Plug and Play devices

synchronous

system noise

(1) hardware—a property of an event that is synchronized to a reference

clock (2) software—a property of a function that begins an operation and

returns only when the operation is complete

a measure of the amount of noise seen by an analog circuit or an ADC when

the analog inputs are grounded

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Glossary

terminal count—the highest value of a counter

T/H

track-and-hold—a circuit that tracks an analog voltage and holds the value

on command

THD

total harmonic distortion—the ratio of the total rms signal due to harmonic

distortion to the overall rms signal, in decibel or a percentage

THD+N

signal-to-THD plus noise—the ratio in decibels of the overall rms signal to

the rms signal of harmonic distortion plus noise introduced

throughput rate

the data, measured in bytes/s, for a given continuous operation, calculated

to include software overhead.

transducer

See sensor

transfer rate

the rate, measured in bytes/s, at which data is moved from source to

destination after software initialization and set up operations; the maximum

rate at which the hardware can operate

TRIG

trigger

TTL

trigger signal

any event that causes or starts some form of data capture

transistor-transistor logic

update interval

unipolar

UISOURCE

update

a signal range that is always positive (for example, 0 to +10 V)

update interval counter clock signal

the output equivalent of a scan. One or more analog or digital output

samples. Typically, the number of output samples in an update is equal to

the number of channels in the output group. For example, one pulse from

the update clock produces one update which sends one new sample to every

analog output channel in the group.

update rate

the number of output updates per second

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Glossary

volts

V_DC

volts direct current

virtual instrument—(1) a combination of hardware and/or software

elements, typically used with a PC, that has the functionality of a classic

stand-alone instrument (2) a LabVIEW software module (VI), which

consists of a front panel user interface and a block diagram program

V_IH

V_IL

volts, input high

volts, input low

volts in

V_in

V_m

measured voltage

volts, output high

volts, output low

reference voltage

volts, root mean square

V_OH

V_OL

V_ref

Vrms

waveform

WFTRIG

working voltage

multiple voltage readings taken at a specific sampling rate

waveform generation trigger signal

the highest voltage that should be applied to a product in normal use,

normally well under the breakdown voltage for safety margin.