LSI Computer Hardware 53C875A User Manual

TECHNICAL  
MANUAL  
LSI53C875A  
PCI to Ultra SCSI  
Controller  
Version 2.0  
D e c e m b e r 2 0 0 0  
®
S14047  
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Preface  
This book is the primary reference and technical manual for the  
LSI53C875A PCI to Ultra SCSI Controller. It contains a complete  
functional description for the product and also includes complete physical  
and electrical specifications.  
Audience  
This manual provides reference information on the LSI53C875A PCI to  
Ultra SCSI Controller. It is intended for system designers and  
programmers who are using this device to design an Ultra SCSI port for  
PCI-based personal computers, workstations, servers or embedded  
applications.  
Organization  
This document has the following chapters and appendixes:  
Chapter 1, General Description includes general information about  
the LSI53C875A.  
Chapter 2, Functional Description describes the main functional  
areas of the chip in more detail, including interfaces to the SCSI bus  
and external memory.  
Chapter 3, Signal Descriptions contains pin diagrams and signal  
descriptions.  
Chapter 4, Registers describes each bit in the operating registers,  
and is organized by register address.  
Chapter 5, SCSI SCRIPTS Instruction Set defines all of the SCSI  
SCRIPTS instructions that are supported by the LSI53C875A.  
Preface  
iii  
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Chapter 6, Electrical Specifications contains the electrical  
characteristics and AC timing diagrams.  
Appendix A, Register Summary is a register summary.  
Appendix B, External Memory Interface Diagram Examples contains  
several example interface drawings for connecting the LSI53C875A  
to external ROMs.  
Related Publications  
For background information, please contact:  
ANSI  
11 West 42nd Street  
New York, NY 10036  
(212) 642-4900  
Ask for document number X3.131-199X (SCSI-2)  
Global Engineering Documents  
15 Inverness Way East  
Englewood, CO 80112  
(800) 854-7179 or (303) 397-7956 (outside U.S.) FAX (303) 397-2740  
Ask for document number X3.131-1994 (SCSI-2); X3.253 (SCSI-3  
Parallel Interface)  
ENDL Publications  
14426 Black Walnut Court  
Saratoga, CA 95070  
(408) 867-6642  
Document names: SCSI Bench Reference, SCSI Encyclopedia,  
SCSI Tutor  
Prentice Hall  
113 Sylvan Avenue  
Englewood Cliffs, NJ 07632  
(800) 947-7700  
Ask for document number ISBN 0-13-796855-8, SCSI: Understanding  
the Small Computer System Interface  
LSI Logic World Wide Web Home Page  
www.lsilogic.com  
iv  
Preface  
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PCI Special Interest Group  
2575 N.E. Katherine  
Hillsboro, OR 97214  
(800) 433-5177; (503) 693-6232 (International); FAX (503) 693-8344  
Conventions Used in This Manual  
The word assert means to drive a signal true or active. The word  
deassert means to drive a signal false or inactive.  
Hexadecimal numbers are indicated by the prefix “0x” —for example,  
0x32CF. Binary numbers are indicated by the prefix “0b” —for example,  
0b0011.0010.1100.1111.  
Revision Record  
Revision  
Date  
Remarks  
Preliminary  
5/00  
6/00  
12/00  
Preliminary draft version of the manual.  
Preliminary version of the manual.  
Final version of the manual.  
1.0  
2.0  
Preface  
v
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vi  
Preface  
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Contents  
Chapter 1  
General Description  
1.1  
1.2  
1.3  
1.4  
1-6  
1.4.1  
1.4.2  
1.4.3  
1.4.5  
1.4.6  
1.4.7  
Integration  
Chapter 2  
Functional Description  
2.1  
2.1.1  
2.1.2  
2.1.3  
2.2  
2-21  
2-22  
2-22  
2-23  
2-23  
2.2.1  
2.2.2  
2.2.3  
2.2.4  
2.2.5  
2.2.6  
2.2.7  
2.2.8  
2.2.9  
Prefetching SCRIPTS Instructions  
Opcode Fetch Burst Capability  
Load and Store Instructions  
JTAG Boundary Scan Testing  
2.2.10 SCSI Loopback Mode  
Contents  
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2-51  
2.3  
2.4  
2.4.1  
2.4.2  
2.5  
Power Management  
2.5.2  
2.5.3  
2.5.4  
Chapter 3  
Signal Descriptions  
3.1  
3.2  
3.2.1  
3.3  
3.3.1  
3.3.2  
3.3.3  
3.3.4  
3.3.5  
3.3.6  
3.4  
3.4.1  
3.4.2  
3.4.3  
3.5  
3.6  
3.7  
3.8  
3.9  
GPIO Signals  
3-10  
3-11  
3-12  
3-13  
3-14  
ROM Flash and Memory Interface Signals  
Test Interface Signals  
Power and Ground Signals  
MAD Bus Programming  
viii  
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Chapter 4  
Chapter 5  
Registers  
4.2  
4.3  
4.4  
5.1  
5.2  
5.2.1  
5.3  
5.4  
5.5  
5.3.1  
5.3.2  
5-34  
5-37  
5.4.1  
5.4.2  
5.5.1  
5.5.2  
5.5.3  
5.5.4  
5.6  
5.7  
5.6.1  
5.6.2  
5.7.1  
5.7.2  
5.7.3  
Second Dword  
5.8  
5.8.1  
5.8.2  
Second Dword  
Chapter 6  
Electrical Specifications  
6.1  
6.2  
DC Characteristics  
6-1  
6-5  
TolerANT Technology Electrical Characteristics  
Contents  
ix  
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6.3  
6.4  
6-13  
6-35  
6-52  
6.4.1  
6.4.3  
Target Timing  
External Memory Timing  
6.5  
SCSI Timing Diagrams  
Appendix A  
Appendix B  
Index  
Customer Feedback  
Figures  
1.1  
1.2  
2.1  
2.2  
2.3  
2.4  
2.5  
2.6  
2.7  
3.1  
5.1  
6.1  
6.2  
6.3  
6.4  
6.5  
6.6  
6.7  
6.8  
Input Current as a Function of Input Voltage  
Output Current as a Function of Output Voltage  
External Clock  
6-8  
6-8  
6-9  
Reset Input  
6-10  
6-11  
Interrupt Output  
x
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6.9  
6-30  
6-32  
6-34  
6-36  
6-40  
6.21 Burst Write, 32-Bit Address and Data  
6.22 Burst Write, 64-Bit Address and 32-Bit Data  
6.23 External Memory Read  
6.25 Normal/Fast Memory (128 Kbytes) Single Byte  
6-42  
6-43  
6-44  
6.26 Normal/Fast Memory (128 Kbytes) Single Byte  
6.27 Normal/Fast Memory (128 Kbytes) Multiple Byte  
Access Read Cycle  
6.28 Normal/Fast Memory (128 Kbytes) Multiple Byte  
6-58  
6-61  
B-1  
6.38 LSI53C875A 160-Pin PQFP Mechanical Drawing  
6.39 169-Pin BGA Mechanical Drawing  
B.1  
B.2  
16 Kbyte Interface with 200 ns Memory  
64 Kbyte Interface with 150 ns Memory  
B-2  
Contents  
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B.3  
B.4  
128 Kbytes, 256 Kbytes, 512 Kbytes, or 1 Mbyte  
Tables  
2.1  
2.2  
2.3  
2.4  
2.5  
2.6  
2.7  
2.8  
3.1  
3.2  
3.3  
3.4  
3.5  
3.6  
3.7  
3.8  
3.9  
3-13  
4-2  
3.14 Power and Ground Signals  
4.1  
4.2  
4.3  
PCI Configuration Register Map  
4.4  
Example Transfer Periods and Rates for Fast SCSI-2  
and Ultra SCSI  
4-33  
4-34  
4-44  
5-3  
4.5  
4.6  
5.1  
Maximum Synchronous Offset  
SCSI Synchronous Data FIFO Word Count  
SCRIPTS Instructions  
xii  
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5.2  
5.3  
5.4  
5.5  
6.1  
6.2  
6.3  
6.4  
5-29  
SCSI Phase Comparisons  
Operating Conditions  
6-2  
Bidirectional Signals—MAD[7:0], MAS/[1:0], MCE/, MOE/,  
6.5  
6.6  
6.7  
Bidirectional Signals—GPIO0_FETCH/, GPIO1_MASTER/,  
TDI, TEST_HSC, TEST_RST, TMS, TRST/  
6-4  
6.8  
6.9  
6.13 Reset Input  
6-27  
6-29  
6-31  
6-33  
6-35  
6.14 Interrupt Output  
6.25 Burst Read, 32-Bit Address and Data  
6.26 Burst Read, 64-Bit Address and Data  
6.27 Burst Write, 32-Bit Address and Data  
6.28 Burst Write, 64-Bit Address and 32-Bit Data  
6.29 External Memory Read  
Contents  
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6-38  
6-42  
6.31 Normal/Fast Memory (128 Kbytes) Single Byte  
Access Read Cycle  
6.32 Normal/Fast Memory (128 Kbytes) Single Byte  
6-53  
6.38 Initiator Asynchronous Receive  
40.0 Mbytes (16-Bit Transfers) Quadrupled 40 MHz Clock 6-56  
6.44 160 PQFP Pin List by Location  
6.45 169 BGA Pin List by Location  
6-60  
6-62  
A-1  
A.1  
A.2  
LSI53C875A PCI Register Map  
LSI53C875A SCSI Register Map  
A-2  
xiv  
Contents  
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Chapter 1  
General Description  
Section 1.1, “New Features in the LSI53C875A”  
Section 1.2, “Benefits of Ultra SCSI”  
Section 1.3, “TolerANT® Technology”  
Section 1.4, “LSI53C875A Benefits Summary”  
The LSI53C875A PCI to Ultra SCSI Controller brings Ultra SCSI  
performance to host adapter, workstation, and general computer designs,  
making it easy to add a high-performance SCSI bus to any PCI system.  
It supports Ultra SCSI transfer rates with Single-Ended (SE) signaling for  
SCSI devices.  
The LSI53C875A has a local memory bus for local storage of the  
device’s BIOS ROM in flash memory or standard EEPROMs. The  
LSI53C875A supports programming of local flash memory for updates to  
BIOS. Chapter 6, “Electrical Specifications,” has the chip package and  
BGA specifications. Appendix B, “External Memory Interface Diagram  
Examples,” has system diagrams showing the connections of the  
LSI53C875A with an external ROM or flash memory.  
The LSI53C875A integrates a high-performance SCSI core, a 64-bit PCI  
bus master DMA core, and the LSI Logic SCSI SCRIPTS™ processor to  
meet the flexibility requirements of SCSI-3 and Ultra SCSI standards. It  
implements multithreaded I/O algorithms with a minimum of processor  
intervention, solving the protocol overhead problems of previous  
intelligent and nonintelligent adapter designs.  
Figure 1.1 illustrates a typical LSI53C875A system and Figure 1.2  
illustrates a typical LSI53C875A board application.  
LSI53C875A PCI to Ultra SCSI Controller  
1-1  
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Figure 1.1 Typical LSI53C875A System Application  
SCSI Bus  
PCI Bus  
LSI53C875A  
PCI to Wide Ultra  
SCSI Controller  
PCI Bus  
Interface  
Controller  
Fixed Disk, Optical Disk  
Printer, Tape, and Other  
Peripherals  
PCI Graphic Accelerator  
PCI Fast Ethernet  
Memory  
Controller  
Central  
Processing  
Unit  
Typical PCI  
Computer System  
Architecture  
Memory  
(CPU)  
Figure 1.2 Typical LSI53C875A Board Application  
Memory  
Address/Data  
Bus  
Memory Control  
Block  
SCSI Data,  
Parity and  
Control  
68 Pin  
SCSI  
Wide  
Flash EEPROM  
Signals  
LSI53C875A  
32 Bit PCI to  
Connector  
SCSI Controller  
GPIO[1:0]  
Serial EEPROM  
PCI Interface  
PCI Address, Data, Parity and Control Signals  
1-2  
General Description  
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1.1 New Features in the LSI53C875A  
The LSI53C875A is a drop-in replacement for the LSI53C875 PCI to  
Ultra SCSI Controller, with these additional benefits:  
Supports 32-bit PCI Interface with 64-bit addressing.  
Handles SCSI phase mismatches in SCRIPTS without interrupting  
the CPU.  
Supports JTAG boundary scanning.  
Supports PC99 Power Management.  
Automatically downloads Subsystem Vendor ID, Subsystem ID,  
and PCI power management levels D0, D1, D2, and D3.  
Improves PCI bus efficiency through improved PCI caching design.  
Transfers Load/Store data to or from 4 Kbytes of internal SCRIPTS  
RAM.  
Additional features of the LSI53C875A include:  
Hardware control of SCSI activity LED.  
32-bit ISTAT registers (Interrupt Status Zero (ISTAT0), Interrupt  
Status One (ISTAT1), Mailbox Zero (MBOX0), Mailbox One  
(MBOX1)).  
Optional 944 byte DMA FIFO supports large block transfers at Ultra  
SCSI speeds. The default FIFO size of 112 bytes is also supported.  
1.2 Benefits of Ultra SCSI  
Ultra SCSI is an extension of the SPI-2 draft standard that allows faster  
synchronous SCSI transfer rates. When enabled, Ultra SCSI performs  
20 megatransfers per second. The LSI53C875A can perform 16-bit, Ultra  
SCSI synchronous transfers as fast as 40 Mbytes/s. This advantage is  
most noticeable in heavily loaded systems or with applications with large  
block requirements, such as video on-demand and image processing.  
An advantage of Ultra SCSI is that it significantly improves SCSI  
bandwidth while preserving existing hardware and software investments.  
The primary software changes required enable the chip to perform  
New Features in the LSI53C875A  
1-3  
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synchronous negotiations for Ultra SCSI rates and to enable the clock  
quadrupler. Chapter 2, “Functional Description,” contains more  
information on Ultra SCSI design.  
®
1.3 TolerANT Technology  
The LSI53C875A features TolerANT technology, which includes active  
negation on the SCSI drivers and input signal filtering on the SCSI  
receivers. Active negation actively drives the SCSI Request,  
Acknowledge, Data, and Parity signals HIGH rather than allowing them  
to be passively pulled up by terminators. Active negation is enabled by  
setting bit 7 in the SCSI Test Three (STEST3) register.  
TolerANT receiver technology improves data integrity in unreliable  
cabling environments where other devices would be subject to data  
corruption. TolerANT receivers filter the SCSI bus signals to eliminate  
unwanted transitions, without the long signal delay associated with  
RC-type input filters. This improved driver and receiver technology helps  
eliminate double clocking of data, the single biggest reliability issue with  
SCSI operations.  
The benefits of TolerANT technology include increased immunity to noise  
when the signal is going HIGH, better performance due to balanced duty  
cycles, and improved fast SCSI transfer rates. In addition, TolerANT SCSI  
devices do not cause glitches on the SCSI bus at power-up or  
power-down, so other devices on the bus are also protected from data  
corruption. TolerANT technology is compatible with both the Alternative  
One and Alternative Two termination schemes proposed by the American  
National Standards Institute.  
1.4 LSI53C875A Benefits Summary  
This section of the chapter provides an overview of the LSI53C875A  
features and benefits. It contains these topics:  
SCSI Performance  
PCI Performance  
Integration  
1-4  
General Description  
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Ease of Use  
Flexibility  
Reliability  
Testability  
1.4.1 SCSI Performance  
To improve SCSI performance, the LSI53C875A:  
Has integrated SE transceivers.  
Bursts up to 512 bytes across the PCI bus through its 944 byte FIFO.  
Performs wide, Ultra SCSI synchronous transfers as fast as  
40 Mbytes/s.  
Can handle phase mismatches in SCRIPTS without interrupting the  
system processor, eliminating the need for CPU intervention during  
an I/O disconnect/reselect sequence.  
Achieve Ultra SCSI transfer rates with an input frequency of 20 MHz  
with the on-chip SCSI clock quadrupler.  
Includes 4 Kbytes internal RAM for SCRIPTS instruction storage.  
Has 31 levels of SCSI synchronous offset.  
Supports variable block size and scatter/gather data transfers.  
Performs sustained memory-to-memory DMA transfers to  
approximately 100 Mbytes/s.  
Minimizes SCSI I/O start latency.  
Performs complex bus sequences without interrupts, including  
restoring data pointers.  
Reduces ISR overhead through a unique interrupt status reporting  
method.  
Uses Load/Store SCRIPTS instructions which increase performance  
of data transfers to and from the chip registers without using PCI  
cycles.  
Has SCRIPTS support for 64-bit addressing.  
Supports multithreaded I/O algorithms in SCSI SCRIPTS with fast  
I/O context switching.  
LSI53C875A Benefits Summary  
1-5  
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Supports additional arithmetic capability with the Expanded Register  
Move instruction.  
1.4.2 PCI Performance  
To improve PCI performance, the LSI53C875A:  
Complies with PCI 2.2 specification.  
Supports 32-bit 33 MHz PCI interface with 64-bit addressing.  
Supports dual address cycles which can be generated for all  
SCRIPTS for > 4 Gbyte addressability.  
Bursts 2, 4, 8, 16, 32, 64, or 128 Dword transfers across the PCI bus.  
Supports 32-bit word data bursts with variable burst lengths.  
Prefetches up to 8 Dwords of SCRIPTS instructions.  
Bursts SCRIPTS opcode fetches across the PCI bus.  
Performs zero wait-state bus master data bursts faster than  
110 Mbytes/s (@ 33 MHz).  
Supports PCI Cache Line Size register.  
Supports PCI Write and Invalidate, Read Line, and Read Multiple  
commands.  
Complies with PCI Bus Power Management Specification Rev 1.1.  
1.4.3 Integration  
Features of the LSI53C875A which ease integration include:  
High-performance SCSI core.  
Integrated SE transceivers.  
Full 32-bit PCI DMA bus master.  
Integrated SCRIPTS processor.  
Memory-to-Memory Move instructions allow use as a third party PCI  
bus DMA controller.  
1.4.4 Ease of Use  
The LSI53C875A provides:  
1-6  
General Description  
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Up to one megabyte of add-in memory support for BIOS and  
SCRIPTS storage.  
Reduced SCSI development effort.  
Compiler-compatible with existing LSI53C7XX and LSI53C8XX  
family SCRIPTS.  
Direct connection to PCI and SCSI SE.  
Development tools and sample SCSI SCRIPTS available.  
Five GPIO pins.  
Maskable and pollable interrupts.  
Wide SCSI, A or P cable, and up to 15 devices supported.  
Three programmable SCSI timers: Select/Reselect,  
Handshake-to-Handshake, and General Purpose. The time-out  
period is programmable from 100 µs to greater than 25.6 seconds.  
Software for PC-based operating system support.  
Support for relative jumps.  
SCSI Selected as ID bits for responding with multiple IDs.  
1.4.5 Flexibility  
The LSI53C875A provides:  
High level programming interface (SCSI SCRIPTS).  
Ability to program local and bus flash memory.  
Selectable 112 or 944 byte DMA FIFO for backward compatibility.  
Tailored SCSI sequences execute from main system RAM or internal  
SCRIPTS RAM.  
Flexible programming interface to tune I/O performance or to adapt  
to unique SCSI devices.  
Support for changes in the logical I/O interface definition.  
Low level access to all registers and all SCSI bus signals.  
Fetch, Master, and Memory Access control pins.  
Separate SCSI and system clocks.  
LSI53C875A Benefits Summary  
1-7  
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SCSI clock quadrupler bits enable Ultra SCSI transfer rates with a 20  
or 40 MHz SCSI clock input.  
Selectable IRQ pin disable bit.  
Ability to route system clock to SCSI clock.  
Compatible with 3.3 V and 5 V PCI.  
1.4.6 Reliability  
Enhanced reliability features of the LSI53C875A include:  
2 kV ESD protection on SCSI signals.  
Protection against bus reflections due to impedance mismatches.  
Controlled bus assertion times (reduces RFI, improves reliability, and  
eases FCC certification).  
Latch-up protection greater than 150 mA.  
Voltage feed-through protection (minimum leakage current through  
SCSI pads).  
High proportion (> 25%) of device pins are power or ground.  
Power and ground isolation of I/O pads and internal chip logic.  
TolerANT technology, which provides:  
Active negation of SCSI Data, Parity, Request, and Acknowledge  
signals for improved fast SCSI transfer rates.  
Input signal filtering on SCSI receivers improves data integrity,  
even in noisy cabling environments.  
1.4.7 Testability  
The LSI53C875A provides improved testability through:  
Access to all SCSI signals through programmed I/O.  
SCSI loopback diagnostics.  
SCSI bus signal continuity checking.  
Support for single step mode operation.  
JTAG boundary scan.  
1-8  
General Description  
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Chapter 2  
Functional Description  
Section 2.2, “SCSI Functional Description”  
Section 2.3, “Parallel ROM Interface”  
Section 2.4, “Serial EEPROM Interface”  
Section 2.5, “Power Management”  
The LSI53C875A PCI to Ultra SCSI Controller is composed of the  
following modules:  
32-bit PCI Interface with 64-bit addressing  
PCI-to-Wide Ultra SCSI Controller  
ROM/Flash Memory Controller  
Serial EEPROM Controller  
Figure 2.1 illustrates the relationship between these modules.  
LSI53C875A PCI to Ultra SCSI Controller  
2-1  
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Figure 2.1 LSI53C875A Block Diagram  
PCI Bus  
32 Bit PCI Interface, PCI Configuration Register  
Wide Ultra SCSI Controller  
4 Kbyte  
SCRIPTS RAM  
8 Dword SCRIPTS  
Prefetch Buffer  
ROM/Flash  
Memory  
Control  
Serial EEPROM  
Controller and  
Autoconfiguration  
944 byte  
DMA FIFO  
SCSI SCRIPTS  
Processor  
Operating  
Registers  
SCSI FIFO and SCSI Control Block  
Local  
Memory  
Bus  
SE TolerANT  
Drivers and Receivers  
JTAG  
JTAG Bus  
Wide Ultra  
SCSI Bus  
ROM/Flash  
Memory Bus  
2-Wire Serial  
EEPROM Bus  
2.1 PCI Functional Description  
The LSI53C875A implements a PCI-to-Wide Ultra SCSI controller.  
2.1.1 PCI Addressing  
There are three physical PCI-defined address spaces:  
PCI Configuration space.  
I/O space for operating registers.  
Memory space for operating registers.  
2-2  
Functional Description  
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2.1.1.1 Configuration Space  
The host processor uses the PCI configuration space to initialize the  
LSI53C875A through a defined set of configuration space registers. The  
Configuration registers are accessible only by system BIOS during PCI  
configuration cycles. The configuration space is a contiguous  
256 X 8-bit set of addresses. Decoding C_BE[3:0]/ determines if a PCI  
cycle is intended to access the configuration register space. The IDSEL  
bus signal is a “chip select” that allows access to the configuration  
register space only. A configuration read/write cycle without IDSEL is  
ignored. The eight lower order address bits, AD[7:0], select a specific  
8-bit register. AD[10:8] are decoded as well, but they must be zero or the  
LSI53C875A does not respond. According to the PCI specification,  
AD[10:8] are reserved for multifunction devices.  
At initialization time, each PCI device is assigned a base address for I/O  
and memory accesses. In the case of the LSI53C875A, the upper 24 bits  
of the address are selected. On every access, the LSI53C875A  
compares its assigned base addresses with the value on the  
Address/Data bus during the PCI address phase. If the upper 24 bits  
match, the access is for the LSI53C875A and the low-order eight bits  
define the register being accessed. A decode of C_BE[3:0]/ determines  
which registers and what type of access is to be performed.  
I/O Space – The PCI specification defines I/O space as a contiguous  
32-bit I/O address that is shared by all system resources, including the  
LSI53C875A. Base Address Register Zero (I/O) determines which  
256-byte I/O area this device occupies.  
Memory Space – The PCI specification defines memory space as a  
contiguous 64-bit memory address that is shared by all system  
resources, including the LSI53C875A. Base Address Register One  
(MEMORY) determines which 1 Kbyte memory area this device  
occupies. Base Address Register Two (SCRIPTS RAM) determines the  
4 Kbyte memory area occupied by SCRIPTS RAM.  
2.1.2 PCI Bus Commands and Functions Supported  
Bus commands indicate to the target the type of transaction the master  
is requesting. Bus commands are encoded on the C_BE[3:0]/ lines  
during the address phase. PCI bus commands and encoding types  
appear in Table 2.1.  
PCI Functional Description  
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Table 2.1  
PCI Bus Commands and Encoding Types for the LSI53C875A  
C_BE[3:0]/ Command Type  
Supported as Master  
Supported as Slave  
0b0000  
0b0001  
0b0010  
0b0011  
0b0100  
0b0101  
0b0110  
0b0111  
0b1000  
0b1001  
0b1010  
0b1011  
0b1100  
0b1101  
0b1110  
0b1111  
Interrupt Acknowledge  
Special Cycle  
No  
No  
No  
No  
I/O Read  
Yes  
Yes  
n/a  
Yes  
I/O Write  
Yes  
Reserved  
n/a  
Reserved  
n/a  
n/a  
Memory Read  
Yes  
Yes  
n/a  
Yes  
Memory Write  
Yes  
Reserved  
n/a  
Reserved  
n/a  
n/a  
Configuration Read  
Configuration Write  
Dual Address Cycle (DAC)  
Memory Read Line  
Memory Write and Invalidate  
No  
Yes  
No  
Yes  
Yes1  
Yes  
Yes1  
Yes2  
Yes (defaults to 0b0110)  
No  
Yes (defaults to 0b0110)  
Yes (defaults to 0b0111)  
1. See the DMA Mode (DMODE) register.  
2. See the Chip Test Three (CTEST3) register.  
2.1.2.1 Interrupt Acknowledge Command  
The LSI53C875A does not respond to this command as a slave and it  
never generates this command as a master.  
2.1.2.2 Special Cycle Command  
The LSI53C875A does not respond to this command as a slave and it  
never generates this command as a master.  
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Functional Description  
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2.1.2.3 I/O Read Command  
The I/O Read command reads data from an agent mapped in I/O  
address space. All 32 address bits are decoded.  
2.1.2.4 I/O Write Command  
The I/O Write command writes data to an agent mapped in I/O address  
space. All 32 address bits are decoded.  
2.1.2.5 Reserved Command  
The LSI53C875A does not respond to this command as a slave and it  
never generates this command as a master.  
2.1.2.6 Memory Read Command  
The Memory Read command reads data from an agent mapped in the  
Memory Address Space. The target is free to do an anticipatory read for  
this command only if it can guarantee that such a read has no side  
effects.  
2.1.2.7 Memory Write Command  
The Memory Write command writes data to an agent mapped in the  
Memory Address Space. When the target returns “ready,” it assumes  
responsibility for the coherency (which includes ordering) of the subject  
data.  
2.1.2.8 Configuration Read Command  
The Configuration Read command reads the configuration space of each  
agent. An agent is selected during a configuration access when its  
IDSEL signal is asserted and AD[1:0] are 0b00.  
2.1.2.9 Configuration Write Command  
The Configuration Write command transfers data to the configuration  
space of each agent. An agent is selected when its IDSEL signal is  
asserted and AD[1:0] are 0b00.  
PCI Functional Description  
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2.1.2.10 Memory Read Multiple Command  
This command is identical to the Memory Read command except that it  
additionally indicates that the master may intend to fetch more than one  
cache line before disconnecting. The LSI53C875A supports PCI Memory  
Read Multiple functionality and issues Memory Read Multiple commands  
on the PCI bus when the Read Multiple Mode is enabled. This mode is  
enabled by setting bit 2 (ERMP) of the DMA Mode (DMODE) register. If  
cache mode is enabled, a Memory Read Multiple command is issued on  
all read cycles, except opcode fetches, when the following conditions are  
met:  
The CLSE bit (Cache Line Size Enable, bit 7, DMA Control (DCNTL)  
register) and the ERMP bit (Enable Read Multiple, bit 2, DMA Mode  
(DMODE) register) are set.  
The Cache Line Size register for each function contains a legal burst  
size value (2, 4, 8, 16, 32, or 64) and that value is less than or equal  
to the DMODE burst size.  
The transfer will cross a cache line boundary.  
When these conditions are met, the chip issues a Memory Read Multiple  
command instead of a Memory Read during all PCI read cycles.  
Burst Size Selection – The Read Multiple command reads in multiple  
cache lines of data in a single bus ownership. The number of cache lines  
to read is a multiple of the cache line size specified in Revision 2.2 of  
the PCI specification. The logic selects the largest multiple of the cache  
line size based on the amount of data to transfer, with the maximum  
allowable burst size determined from the DMA Mode (DMODE) burst size  
bits, and the Chip Test Five (CTEST5), bit 2.  
2.1.2.11 Dual Address Cycle (DAC) Command  
The LSI53C875A performs DACs when 64-bit addressing is required.  
Refer to the PCI 2.2 specification. If any of the selector registers contain  
a nonzero value, a DAC is generated. See 64-bit SCRIPTS Selectors in  
Chapter 4, “Registers,” for additional information.  
2.1.2.12 Memory Read Line Command  
This command is identical to the Memory Read command, except that it  
additionally indicates that the master intends to fetch a complete cache  
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Functional Description  
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line. This command is intended for use with bulk sequential data transfers  
where the memory system and the requesting master might gain some  
performance advantage by reading to a cache line boundary rather than  
a single memory cycle. The Read Line function in the LSI53C875A takes  
advantage of the PCI 2.2 specification regarding issuing this command.  
If the cache mode is disabled, Read Line commands are not issued.  
If the cache mode is enabled, a Read Line command is issued on all  
read cycles, except nonprefetch opcode fetches, when the following  
conditions are met:  
The CLSE (Cache Line Size Enable, bit 7, DMA Control (DCNTL)  
register) and ERL (Enable Read Line, bit 3, DMA Mode (DMODE)  
register) bits are set.  
The Cache Line Size register must contain a legal burst size value  
in Dwords (2, 4, 8, 16, 32, 64, or 128) and that value is less than or  
equal to the DMA Mode (DMODE) burst size.  
The transfer will cross a Dword boundary but not a cache line  
boundary.  
When these conditions are met, the chip issues a Read Line command  
instead of a Memory Read during all PCI read cycles. Otherwise, it  
issues a normal Memory Read command.  
Read Multiple with Read Line Enabled – When both the Read Multiple  
and Read Line modes are enabled, the Read Line command is not  
issued if the above conditions are met. Instead, a Read Multiple  
command is issued, even though the conditions for Read Line are met.  
If the Read Multiple mode is enabled and the Read Line mode is  
disabled, Read Multiple commands are issued if the Read Multiple  
conditions are met.  
PCI Functional Description  
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2.1.2.13 Memory Write and Invalidate Command  
The Memory Write and Invalidate command is identical to the Memory  
Write command, except that it additionally guarantees a minimum  
transfer of one complete cache line; that is to say, the master intends to  
write all bytes within the addressed cache line in a single PCI transaction  
unless interrupted by the target. This command requires implementation  
of the PCI Cache Line Size register at address 0x0C in PCI configuration  
space. The LSI53C875A enables Memory Write and Invalidate cycles  
when bit 0 (WRIE) in the Chip Test Three (CTEST3) register and bit 4  
(WIE) in the PCI Command register are set. When the following  
conditions are met, Memory Write and Invalidate commands are issued:  
1. The CLSE bit (Cache Line Size Enable, bit 7, DMA Control (DCNTL)  
register), WRIE bit (Write and Invalidate Enable, bit 0, Chip Test  
Three (CTEST3) register), and PCI configuration Command register,  
bit 4 are set.  
2. The Cache Line Size register contains a legal burst size value in  
Dwords (2, 4, 8, 16, 32, 64, or 128) and that value is less than or  
equal to the DMA Mode (DMODE) burst size.  
3. The chip has enough bytes in the DMA FIFO to complete at least  
one full cache line burst.  
4. The chip is aligned to a cache line boundary.  
When these conditions are met, the LSI53C875A issues a Memory Write  
and Invalidate command instead of a Memory Write command during all  
PCI write cycles.  
Multiple Cache Line Transfers – The Memory Write and Invalidate  
command can write multiple cache lines of data in a single bus  
ownership. The chip issues a burst transfer as soon as it reaches a  
cache line boundary. The size of the transfer is not automatically the  
cache line size, but rather a multiple of the cache line size specified in  
Revision 2.2 of the PCI specification. The logic selects the largest  
multiple of the cache line size based on the amount of data to transfer,  
with the maximum allowable burst size determined from the DMA Mode  
(DMODE) burst size bits, and Chip Test Five (CTEST5), bit 2. If multiple  
cache line size transfers are not desired, set the DMA Mode (DMODE)  
burst size to exactly the cache line size and the chip only issues single  
cache line transfers.  
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Functional Description  
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After each data transfer, the chip re-evaluates the burst size based on  
the amount of remaining data to transfer and again selects the highest  
possible multiple of the cache line size, and no larger than the DMA  
Mode (DMODE) burst size. The most likely scenario of this scheme is  
that the chip selects the DMA Mode (DMODE) burst size after alignment,  
and issues bursts of this size. The burst size is, in effect, throttled down  
toward the end of a long Memory Move or Block Move transfer until only  
the cache line size burst size is left. The chip finishes the transfer with  
this burst size.  
Latency – In accordance with the PCI specification, the latency timer is  
ignored when issuing a Memory Write and Invalidate command such that  
when a latency time-out occurs, the LSI53C875A continues to transfer  
up to a cache line boundary. At that point, the chip relinquishes the bus,  
and finishes the transfer at a later time using another bus ownership. If  
the chip is transferring multiple cache lines it continues to transfer until  
the next cache boundary is reached.  
PCI Target Retry – During a Memory Write and Invalidate transfer, if the  
target device issues a retry (STOP with no TRDY/, indicating that no data  
was transferred), the chip relinquishes the bus and immediately tries to  
finish the transfer on another bus ownership. The chip issues another  
Memory Write and Invalidate command on the next ownership, in  
accordance with the PCI specification.  
PCI Target Disconnect – During a Memory Write and Invalidate  
transfer, if the target device issues a disconnect the LSI53C875A  
relinquishes the bus and immediately tries to finish the transfer on  
another bus ownership. The chip does not issue another Memory Write  
and Invalidate command on the next ownership unless the address is  
aligned.  
2.1.3 PCI Cache Mode  
The LSI53C875A supports the PCI specification for an 8-bit Cache Line  
Size register located in the PCI configuration space. The Cache Line  
Size register provides the ability to sense and react to nonaligned  
addresses corresponding to cache line boundaries. In conjunction with  
the Cache Line Size register, the PCI commands Memory Read Line,  
Memory Read Multiple, and Memory Write and Invalidate are each  
PCI Functional Description  
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software enabled or disabled to allow the user full flexibility in using these  
commands.  
2.1.3.1 Enabling Cache Mode  
In order to enable the cache logic to issue PCI cache commands  
(Memory Read Line, Memory Read Multiple, and Memory Write and  
Invalidate) on any given PCI master operation the following conditions  
must be met:  
The Cache Line Size Enable bit in the DMA Control (DCNTL) register  
must be set.  
The PCI Cache Line Size register must contain a valid binary cache  
size, i.e. 2, 4, 8, 16, 32, 64, or 128 Dwords. Only these values are  
considered valid cache sizes.  
The programmed burst size (in Dwords) must be equal to or greater  
than the Cache Line Size register. The DMA Mode (DMODE) register  
bits [7:6] and Chip Test Five (CTEST5) bit 2 are the burst length bits.  
The part must be doing a PCI Master transfer. The following PCI  
Master transactions do not utilize the PCI cache logic and thus no  
PCI cache command is issued during these types of cycles: a  
nonprefetch SCRIPTS fetch, a Load/Store data transfer, or a data  
flush operation. All other types of PCI Master transactions will utilize  
the PCI cache logic.  
The above conditions must be met for the cache logic to control the type  
of PCI cache command that is issued, along with any alignment that may  
be necessary during write operations. If these conditions are not met for  
any given PCI Master transaction, a Memory Read or Memory Write is  
issued and no cache write alignment is done.  
2.1.3.2 Issuing Cache Commands  
In order to issue each type of PCI cache command, the corresponding  
enable bit must be set (2 bits in the case of Memory Write and  
Invalidate). These bits are detailed below:  
To issue Memory Read Line commands, the Read Line enable bit in  
the DMA Mode (DMODE) register must be set.  
2-10  
Functional Description  
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To issue Memory Read Multiple commands, the Read Multiple  
enable bit in the DMA Mode (DMODE) register must be set.  
To issue Memory Write and Invalidate commands, both the Write and  
Invalidate enables in the Chip Test Three (CTEST3) register and the  
PCI configuration command register must be set.  
If the corresponding cache command being issued is not enabled then  
the cache logic falls back to the next command enabled. Specifically, if  
Memory Read Multiple is not enabled and Memory Read Lines are, read  
lines are issued in place of read multiple. If no cache commands are  
enabled, cache write alignment still occurs but no cache commands are  
issued, only memory reads and memory writes.  
2.1.3.3 Memory Read Caching  
The type of Memory Read command issued depends on the starting  
location of the transfer and the number of bytes being transferred. During  
reads, no cache alignment is done (this is not required nor optimal per  
PCI 2.2 specification) and reads will always be either a programmed  
burst length in size, as set in the DMA Mode (DMODE) and Chip Test  
Three (CTEST3) registers. In the case of a transfer which is smaller than  
the burst length, all bytes for that transfer are read in one PCI burst  
transaction. If the transfer will cross a Dword boundary (A[1:0] = 0b00) a  
Memory Read Line command is issued. When the transfer will cross a  
cache boundary (depends on cache line size programmed into the PCI  
configuration register), a Memory Read Multiple command is issued. If a  
transfer will not cross a Dword or cache boundary or if cache mode is  
not enabled a Memory Read command is issued.  
2.1.3.4 Memory Write Caching  
Writes are aligned in a single burst transfer to get to a cache boundary.  
At that point, Memory Write and Invalidate commands are issued and  
continue at the burst length programmed into the DMA Mode (DMODE)  
register. Memory Write and Invalidate commands are issued as long as  
the remaining byte count is greater than the Memory Write and Invalidate  
threshold. When the byte count goes below this threshold, a single  
Memory Write burst is issued to complete the transfer. The general  
pattern for PCI writes is:  
A single Memory Write to align to a cache boundary.  
PCI Functional Description  
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Multiple Memory Write and Invalidates.  
A single data residual Memory Write to complete the transfer.  
Table 2.2 describes PCI cache mode alignment.  
Table 2.2  
PCI Cache Mode Alignment  
Host Memory  
A
00h  
B
04h  
08h  
0Ch  
10h  
14h  
18h  
1Ch  
20h  
24h  
28h  
2Ch  
30h  
34h  
38h  
3Ch  
40h  
44h  
48h  
4Ch  
50h  
54h  
58h  
5Ch  
60h  
C
D
E
F
G
H
2-12  
Functional Description  
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2.1.3.5 Examples:  
MR = Memory Read, MRL = Memory Read Line, MRM = Memory Read  
Multiple, MW = Memory Write, MWI = Memory Write and Invalidate.  
Read Example 1 –  
Burst = 4 Dwords, Cache Line Size = 4 Dwords:  
A to B:  
A to C:  
A to D:  
MRL (6 bytes)  
MRL (13 bytes)  
MRL (15 bytes)  
MR (2 bytes)  
C to D:  
C to E:  
MRM (5 bytes)  
MRM (15 bytes)  
MRM (6 bytes)  
D to F:  
A to H:  
MRL (15 bytes)  
MRL (16 bytes)  
MR (1 byte)  
MRL (15 bytes)  
MRL (16 bytes)  
MRL (16 bytes)  
MRL (16 bytes)  
MRL (16 bytes)  
MR (2 bytes)  
A to G:  
MRL (15 bytes)  
MRL (16 bytes)  
MRL (16 bytes)  
MRL (16 bytes)  
MR (3 bytes)  
Read Example 2 –  
Burst = 8 Dwords, Cache Line Size = 4 Dwords:  
A to B:  
A to C:  
A to D:  
C to D:  
MRL (6 bytes)  
MRL (13 bytes)  
MRM (17 bytes)  
MRM (5 bytes)  
PCI Functional Description  
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C to E:  
D to F:  
MRM (21 bytes)  
MRM (31 bytes)  
MR (1 byte)  
A to H:  
A to G:  
MRM (31 bytes)  
MRM (32 bytes)  
MRM (18 bytes)  
MRM (31 bytes)  
MRM (32 bytes)  
MR (3 bytes)  
Read Example 3 –  
Burst = 16 Dwords, Cache Line Size = 8 Dwords:  
A to B:  
A to C:  
A to D:  
C to D:  
C to E:  
D to F:  
A to H:  
MRL (6 bytes)  
MRL (13 bytes)  
MRL (17 bytes)  
MRL (5 bytes)  
MRM (21 bytes)  
MRM (32 bytes)  
MRM (63 bytes)  
MRL (16 bytes)  
MRM (2 bytes)  
A to G:  
2 transfers, MRM (63 bytes), MR (3 bytes)  
Write Example 1 –  
Burst = 4 Dwords, Cache Line Size = 4 Dwords:  
A to B:  
A to C:  
A to D:  
C to D:  
C to E:  
MW (6 bytes)  
MW (13 bytes)  
MW (17 bytes)  
MW (5 bytes)  
MW (3 bytes)  
MWI (16 bytes)  
MW (2 bytes)  
2-14  
Functional Description  
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D to F:  
A to H:  
MW (15 bytes)  
MWI (16 bytes)  
MW (1 byte)  
MW (15 bytes)  
MWI (16 bytes)  
MWI (16 bytes)  
MWI (16 bytes)  
MWI (16 bytes)  
MW (2 bytes)  
A to G:  
MW (15 bytes)  
MWI (16 bytes)  
MWI (16 bytes)  
MWI (16 bytes)  
MW (3 bytes)  
Write Example 2 –  
Burst = 8 Dwords, Cache Line Size = 4 Dwords:  
A to B:  
A to C:  
A to D:  
C to D:  
C to E:  
MW (6 bytes)  
MW (13 bytes)  
MW (17 bytes)  
MW (5 bytes)  
MW (3 bytes)  
MWI (16 bytes)  
MW (2 bytes)  
D to F:  
A to H:  
MW (15 bytes)  
MWI (16 bytes)  
MW (1 byte)  
MW (15 bytes)  
MWI (32 bytes)  
MWI (32 bytes)  
MW (2 bytes)  
A to G:  
MW (15 bytes)  
MWI (32 bytes)  
MWI (16 bytes)  
MW (3 bytes)  
PCI Functional Description  
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Write Example 3 –  
Burst = 16 Dwords, Cache Line Size = 8 Dwords:  
A to B:  
A to C:  
A to D:  
C to D:  
C to E:  
D to F:  
A to H:  
MW (6 bytes)  
MW (13 bytes)  
MW (17 bytes)  
MW (5 bytes)  
MW (21 bytes)  
MW (32 bytes)  
MW (15 bytes)  
MWI (64 bytes)  
MW (2 bytes)  
A to G:  
MW (15 bytes)  
MWI (32 bytes)  
MW (18 bytes)  
2.1.3.6 Memory-to-Memory Moves  
Memory-to-Memory Moves also support PCI cache commands, as  
described above, with one limitation. Memory Write and Invalidate on  
Memory-to-Memory Move writes are only supported if the source and  
destination address are quad word aligned. If the source and destination  
are not quad word aligned (that is, Source address [2:0] == Destination  
Address [2:0]), write aligning is not performed and Memory Write and  
Invalidate commands are not issued. The LSI53C875A is little endian  
only.  
2.2 SCSI Functional Description  
The LSI53C875A provides an Ultra SCSI controller that supports an  
8-bit or 16-bit bus. The controller supports Wide Ultra SCSI synchronous  
transfer rates up to 40 Mbytes/s. The SCSI core can be programmed with  
SCSI SCRIPTS, making it easy to “fine tune” the system for specific  
mass storage devices or Ultra SCSI requirements.  
The LSI53C875A offers low level register access or a high-level control  
interface. Like first generation SCSI devices, the LSI53C875A is  
2-16  
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accessed as a register-oriented device. Error recovery and/or diagnostic  
procedures use the ability to sample and/or assert any signal on the  
SCSI bus. In support of SCSI loopback diagnostics, the SCSI core may  
perform a self-selection and operate as both an initiator and a target.  
The LSI53C875A is controlled by the integrated SCRIPTS processor  
through a high-level logical interface. Commands controlling the SCSI  
core are fetched out of the main host memory or local memory. These  
commands instruct the SCSI core to Select, Reselect, Disconnect, Wait  
for a Disconnect, Transfer Information, Change Bus Phases and, in  
general, implement all aspects of the SCSI protocol. The SCRIPTS  
processor is a special high-speed processor optimized for SCSI protocol.  
2.2.1 SCRIPTS Processor  
The SCSI SCRIPTS processor allows both DMA and SCSI commands  
to be fetched from host memory or internal SCRIPTS RAM. Algorithms  
written in SCSI SCRIPTS control the actions of the SCSI and DMA  
cores. The SCRIPTS processor executes complex SCSI bus sequences  
independently of the host=CPU.  
Algorithms may be designed to tune SCSI bus performance, to adjust to  
new bus device types (such as scanners, communication gateways, etc.),  
or to incorporate changes in the SCSI-2 or SCSI-3 logical bus definitions  
without sacrificing I/O performance. SCSI SCRIPTS are hardware  
independent, so they can be used interchangeably on any host or CPU  
system bus. SCSI SCRIPTS handle conditions like Phase Mismatch.  
2.2.1.1 Phase Mismatch Handling in SCRIPTS  
The LSI53C875A can handle phase mismatches due to drive  
disconnects without needing to interrupt the processor. The primary goal  
of this logic is to completely eliminate the need for CPU intervention  
during an I/O disconnect/reselect sequence.  
Storing the appropriate information to later restart the I/O can be done  
through SCRIPTS, eliminating the need for processor intervention during  
an I/O disconnect/reselect sequence. Calculations are performed such  
that the appropriate information is available to SCRIPTS so that an I/O  
state can be properly stored for restart later.  
SCSI Functional Description  
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The Phase Mismatch Jump logic powers up disabled and must be  
enabled by setting the Phase Mismatch Jump Enable bit (ENPMJ, bit 7  
in the Chip Control 0 (CCNTL0) register).  
Utilizing the information supplied in the Phase Mismatch Jump Address  
1 (PMJAD1) and Phase Mismatch Jump Address 2 (PMJAD2) registers,  
described in Chapter 4, “Registers,” SCRIPTS handles all overhead  
involved in a disconnect/reselect sequence with a modest number of  
instructions.  
2.2.2 Internal SCRIPTS RAM  
The LSI53C875A has 4 Kbyte (1024 x 32 bits) of internal, general  
purpose RAM. The RAM is designed for SCRIPTS program storage, but  
is not limited to this type of information. When the chip fetches SCRIPTS  
instructions or Table Indirect information from the internal RAM, these  
fetches remain internal to the chip and do not use the PCI bus. Other  
types of access to the RAM by the chip, except Load/Store, use the PCI  
bus, as if they were external accesses. The SCRIPTS RAM powers up  
enabled by default.  
The RAM can be relocated by the PCI system BIOS anywhere in the  
32-bit address space. The Base Address Register Two (SCRIPTS RAM)  
in the PCI configuration space contains the base address of the internal  
RAM. To simplify loading of the SCRIPTS instructions, the base address  
of the RAM appears in the Scratch Register B (SCRATCHB) register  
when bit 3 of the Chip Test Two (CTEST2) register is set. The RAM is  
byte accessible from the PCI bus and is visible to any bus mastering  
device on the bus. External accesses to the RAM (by the CPU) follow  
the same timing sequence as a standard slave register access, except  
that the required target wait-states drop from 5 to 3.  
A complete set of development tools is available for writing custom  
drivers with SCSI SCRIPTS. For more information on the SCSI SCRIPTS  
instructions supported by the LSI53C875A, see Chapter 5, “SCSI  
SCRIPTS Instruction Set.”  
2-18  
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2.2.3 64-Bit Addressing in SCRIPTS  
The LSI53C875A has a 32-bit PCI interface which provides 64-bit  
address capability in the initiator mode.  
DACs can be generated for all SCRIPTS operations. There are six  
selector registers which hold the upper Dword of a 64-bit address. All but  
one of these is static and requires manual loading using a CPU access,  
a Load/Store instruction, or a Memory Move instruction. One of the  
selector registers is dynamic and is used during 64-bit direct block moves  
only. All selectors default to zero, meaning the LSI53C875A powers-up  
in a state where only Single Address Cycles (SACs) are generated.  
When any of the selector registers are written to a nonzero value, DACs  
are generated.  
Direct, Table Indirect and Indirect Block moves, Memory-to-Memory  
Moves, Load and Store instructions, and jumps are all instructions with  
64-bit address capability.  
Crossing the 4 Gbyte boundary on any one SCRIPTS operation is not  
permitted and software needs to take care that any given SCRIPTS  
operation will not cross the 4 Gbyte boundary.  
2.2.4 Hardware Control of SCSI Activity LED  
The LSI53C875A has the ability to control a LED through the GPIO_0  
pin to indicate that it is connected to the SCSI bus. Formerly this function  
was done by a software driver.  
When bit 5 (LED_CNTL) in the General Purpose Pin Control Zero  
(GPCNTL0) register is set and bit 6 (Fetch Enable) in the General  
Purpose Pin Control Zero (GPCNTL0) register is cleared and the  
LSI53C875A is not performing an EEPROM autodownload, then bit 3  
(CON) in the Interrupt Status Zero (ISTAT0) register is presented at the  
GPIO_0 pin.  
The CON (Connected) bit in Interrupt Status Zero (ISTAT0) is set anytime  
the LSI53C875A is connected to the SCSI bus either as an initiator or a  
target. This will happen after the LSI53C875A has successfully  
completed a selection or when it has successfully responded to a  
selection or reselection. It will also be set when the LSI53C875A wins  
arbitration in low level mode.  
SCSI Functional Description  
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2.2.5 Designing an Ultra SCSI System  
Since Ultra SCSI is based on existing SCSI standards, it can use existing  
driver programs as long as the software is able to negotiate for Ultra  
SCSI synchronous transfer rates. Additional software modifications are  
needed to take advantage of the new features in the LSI53C875A.  
For additional information on Ultra SCSI, refer to the SPI-2 working  
document which is available from the SCSI BBS referenced at the  
beginning of this manual. Chapter 6, “Electrical Specifications,” contains  
Ultra SCSI timing information. In addition to the guidelines in the draft  
standard, make the following software and hardware adjustments to  
accommodate Ultra SCSI transfers:  
Set the Ultra Enable bit to enable Ultra SCSI transfers.  
Set the TolerANT Enable bit, bit 7 in the SCSI Test Three (STEST3)  
register, whenever the Ultra Enable bit is set.  
Do not extend the SREQ/SACK filtering period with SCSI Test Two  
(STEST2) bit 1. When the Ultra Enable bit is set, the filtering period  
is fixed at 15 ns for Ultra SCSI, regardless of the value of the  
SREQ/SACK Filtering bit.  
Use the SCSI clock quadrupler.  
A 20 or 40 MHz input must be supplied if using the SCSI clock  
quadrupler for an Ultra design.  
2.2.5.1 Using the SCSI Clock Quadrupler  
The LSI53C875A can quadruple the frequency of a 20 MHz SCSI clock,  
allowing the system to perform Ultra SCSI transfers. This option is user  
selectable with bit settings in the SCSI Test One (STEST1), SCSI Test  
Three (STEST3), and SCSI Control Three (SCNTL3) registers. At  
power-on or reset, the quadrupler is disabled and powered down. Follow  
these steps to use the clock quadrupler:  
Step 1. Set the SCLK Quadrupler Enable bit (SCSI Test One  
(STEST1), bit 3).  
Step 2. Poll bit 5 of the SCSI Test Four (STEST4) register.  
The LSI53C875A sets this bit as soon as it locks in the  
quadrupled frequency. The frequency lockup takes  
approximately 100 µs.  
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Step 3. Halt the SCSI clock by setting the Halt SCSI Clock bit (SCSI  
Test Three (STEST3), bit 5).  
Step 4. Set the clock conversion factor using the SCF and CCF fields  
in the SCSI Control Three (SCNTL3) register.  
Step 5. Set the SCLK Quadrupler Select bit (SCSI Test One (STEST1),  
bit 2).  
Step 6. Clear the Halt SCSI Clock bit.  
2.2.6 Prefetching SCRIPTS Instructions  
When enabled by setting the Prefetch Enable bit (bit 5) in the DMA  
Control (DCNTL) register, the prefetch logic in the LSI53C875A fetches  
8 Dwords of instructions. The prefetch logic automatically determines the  
maximum burst size that it can perform, based on the burst length as  
determined by the values in the DMA Mode (DMODE) register. If the unit  
cannot perform bursts of at least four Dwords, it disables itself. While the  
chip is prefetching SCRIPTS instructions, it will use PCI cache  
commands Memory Read Line, and Memory Read Multiple, if PCI  
caching is enabled.  
Note:  
This feature is only useful if fetching SCRIPTS instructions  
from main memory. Due to the short access time of  
SCRIPTS RAM, prefetching is not necessary when fetching  
instructions from this memory.  
The LSI53C875A may flush the contents of the prefetch unit under  
certain conditions, listed below, to ensure that the chip always operates  
from the most current version of the SCRIPTS instruction. When one of  
these conditions apply, the contents of the prefetch unit are automatically  
flushed.  
On every Memory Move instruction. The Memory Move instruction is  
often used to place modified code directly into memory. To make  
sure that the chip executes all recent modifications, the prefetch unit  
flushes its contents and loads the modified code every time an  
instruction is issued. To avoid inadvertently flushing the prefetch unit  
contents, use the No Flush option for all Memory Move operations  
that do not modify code within the next 8 Dwords. For more  
information on this instruction refer to Chapter 5, “SCSI SCRIPTS  
Instruction Set.”  
SCSI Functional Description  
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On every Store instruction. The Store instruction may also be used  
to place modified code directly into memory. To avoid inadvertently  
flushing the prefetch unit contents use the No Flush option for all  
Store operations that do not modify code within the next 8 Dwords.  
On every write to the DMA SCRIPTS Pointer (DSP) register.  
On all Transfer Control instructions when the transfer conditions are  
met. This is necessary because the next instruction to execute is not  
the sequential next instruction in the prefetch unit.  
When the Prefetch Flush bit (DMA Control (DCNTL) register, bit 6)  
is set. The unit flushes whenever this bit is set. The bit is self-  
clearing.  
2.2.7 Opcode Fetch Burst Capability  
Setting the Burst Opcode Fetch Enable bit (bit 1) in the DMA Mode  
(DMODE) register (0x38) causes the LSI53C875A to burst in the first two  
Dwords of all instruction fetches. If the instruction is a Memory-to-  
Memory Move, the third Dword is accessed in a separate ownership. If  
the instruction is an indirect type, the additional Dword is accessed in a  
subsequent bus ownership. If the instruction is a Table Indirect Block  
Move, the chip uses two accesses to obtain the four Dwords required, in  
two bursts of two Dwords each.  
Note:  
This feature is only useful if Prefetching is disabled and  
SCRIPTS instructions are fetched from main memory. Due  
to the short SCRIPTS RAM access time, burst opcode  
fetching is not necessary when fetching instructions from  
this memory.  
2.2.8 Load and Store Instructions  
The LSI53C875A supports the Load and Store instruction type, which  
simplifies the movement of data between memory and the internal chip  
registers. It also enables the chip to transfer bytes to addresses relative  
to the Data Structure Address (DSA) register. Load and Store data  
transfers to or from the SCRIPTS RAM will remain internal to the chip  
and will not generate PCI bus cycles. While a Load/Store to or from  
SCRIPTS RAM is occurring, any external PCI slave cycles that occur are  
retried on the PCI bus. This feature can be disabled by setting the DILS  
bit in the Chip Control 0 (CCNTL0) register. For more information on the  
2-22  
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Load and Store instructions, refer to Chapter 5, “SCSI SCRIPTS  
Instruction Set.”  
2.2.9 JTAG Boundary Scan Testing  
The LSI53C875A includes support for JTAG boundary scan testing in  
accordance with the IEEE 1149.1 specification with one exception, which  
is explained in this section. This device accepts all required boundary  
scan instructions including the optional CLAMP, HIGH-Z, and IDCODE  
instructions.  
The LSI53C875A uses an 8-bit instruction register to support all  
boundary scan instructions. The data registers included in the device are  
the Boundary Data register, the IDCODE register, and the Bypass  
register. This device can handle a 10 MHz TCLK frequency for TDO and  
TDI.  
Due to design constraints, the RST/ pin (system reset) always 3-states  
the SCSI pins when it is asserted. Boundary scan logic does not control  
this action, and this is not compliant with the specification. There are two  
solutions that resolve this issue:  
1. Use the RST/ pin as a boundary scan compliance pin. When the pin  
is deasserted, the device is boundary scan compliant and when  
asserted, the device is noncompliant. To maintain compliance the  
RST/ pin must be driven HIGH.  
2. When RST/ is asserted during boundary scan testing the expected  
output on the SCSI pins must be the HIGH-Z condition, and not what  
is contained in the boundary scan data registers for the SCSI pin  
output cells.  
2.2.10 SCSI Loopback Mode  
The LSI53C875A loopback mode allows testing of both initiator and  
target functions and, in effect, lets the chip communicate with itself.  
When the Loopback Enable bit is set in the SCSI Test Two (STEST2)  
register, bit 4, the LSI53C875A allows control of all SCSI signals whether  
the chip is operating in the initiator or target mode. For more information  
on this mode of operation refer to the LSI Logic SCSI SCRIPTS  
Processor Programming Guide.  
SCSI Functional Description  
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2.2.11 Parity Options  
The LSI53C875A implements a flexible parity scheme that allows control  
of the parity sense, allows parity checking to be turned on or off, and has  
the ability to deliberately send a byte with bad parity over the SCSI bus  
to test parity error recovery procedures. Table 2.3 defines the bits that  
are involved in parity control and observation. Table 2.4 describes the  
parity control function of the Enable Parity Checking and Assert SCSI  
Even Parity bits in the SCSI Control One (SCNTL1) register, bit 2.  
Table 2.5 describes the options available when a parity error occurs.  
Figure 2.2 shows where parity checking is done in the LSI53C875A.  
2-24  
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Table 2.3  
Bit Name  
Bits Used for Parity Control and Generation  
Location Description  
SCSI Control Zero Causes the LSI53C875A to automatically assert SATN/  
Assert SATN/ on  
Parity Errors  
(SCNTL0), Bit 1  
when it detects a SCSI parity error while operating as an  
Enable Parity  
Checking  
SCSI Control Zero Enables the LSI53C875A to check for parity errors. The  
(SCNTL0), Bit 3 LSI53C875A checks for odd parity.  
Assert Even SCSI  
Parity  
SCSI Control One Determines the SCSI parity sense generated by the  
(SCNTL1), Bit 2 LSI53C875A to the SCSI bus.  
Disable Halt on  
SATN/ or a Parity  
Error (Target Mode  
Only)  
SCSI Control One Causes the LSI53C875A not to halt operations when a  
(SCNTL1), Bit 5  
parity error is detected in target mode.  
Enable Parity Error  
Interrupt  
SCSI Interrupt  
Enable Zero  
(SIEN0), Bit 0  
Determines whether the LSI53C875A generates an  
interrupt when it detects a SCSI parity error.  
Parity Error  
SCSI Interrupt  
Status Zero  
This status bit is set whenever the LSI53C875A detects a  
parity error on the SCSI bus.  
(SIST0), Bit 0  
Status of SCSI  
Parity Signal  
SCSI Status Zero This status bit represents the active HIGH current state of  
(SSTAT0), Bit 0  
SCSI SDP1 Signal  
SCSI Status Two  
(SSTAT2), Bit 0  
This bit represents the active HIGH current state of the  
SCSI SDP1 parity signal.  
Latched SCSI Parity SSTAT 2, Bit 3 and These bits reflect the SCSI odd parity signal  
SCSI Status One corresponding to the data latched into the SCSI Input  
(SSTAT1), Bit 3  
Data Latch (SIDL) register.  
Master Parity Error  
Enable  
Chip Test Four  
(CTEST4), Bit 3  
Enables parity checking during PCI master data phases.  
Master Data Parity  
Error  
DMA Status  
(DSTAT), Bit 6  
Set when the LSI53C875A, as a PCI master, detects a  
target device signaling a parity error during a data phase.  
Master Data Parity  
Error Interrupt  
Enable  
DMA Interrupt  
Enable (DIEN),  
Bit 6  
By clearing this bit, a Master Data Parity Error does not  
cause assertion of INTA/ (or INTB/), but the status bit is  
set in the DMA Status (DSTAT) register.  
SCSI Functional Description  
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Table 2.4  
SCSI Parity Control  
EPC1  
ASEP2  
Description  
0
0
Does not check for parity errors. Parity is generated when sending  
SCSI data. Asserts odd parity when sending SCSI data.  
0
1
1
1
0
1
Does not check for parity errors. Parity is generated when sending  
SCSI data. Asserts even parity when sending SCSI data.  
Checks for odd parity on SCSI data received. Parity is generated when  
sending SCSI data. Asserts odd parity when sending SCSI data.  
Checks for odd parity on SCSI data received. Parity is generated when  
sending SCSI data. Asserts even parity when sending SCSI data.  
1. EPC = Enable Parity Checking (bit 3 SCSI Control Zero (SCNTL0)).  
2. ASEP = Assert SCSI Even Parity (bit 2 SCSI Control One (SCNTL1)).  
Table 2.5  
SCSI Parity Errors and Interrupts  
DHP1  
PAR2  
Description  
0
0
Halts when a parity error occurs in the target or initiator mode and does  
NOT generate an interrupt.  
0
1
1
1
0
1
Halts when a parity error occurs in the target mode and generates an  
interrupt in the target or initiator mode.  
Does not halt in target mode when a parity error occurs until the end  
of the transfer. An interrupt is not generated.  
Does not halt in target mode when a parity error occurs until the end  
of the transfer. An interrupt is generated.  
1. DHP = Disable Halt on SATN/ or Parity Error (bit 5 SCSI Control One (SCNTL1)).  
2. PAR = Parity Error (bit 0 SCSI Interrupt Enable Zero (SIEN0)).  
2-26  
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Figure 2.2 Parity Checking/Generation  
Asynchronous  
SCSI Send  
Asynchronous  
SCSI Receive  
Synchronous  
SCSI Send  
Synchronous  
SCSI Receive  
PCI Interface**  
X
PCI Interface**  
G
PCI Interface**  
G
PCI Interface**  
X
DMA FIFO*  
(64 bits X 118)  
DMA FIFO*  
(64 bits X 118)  
DMA FIFO*  
(64 bits X 118)  
DMA FIFO*  
(64 bits X 118)  
X
SCSI FIFO**  
(8 or 16 bits x 31)  
SODL Register*  
SIDL Register*  
SODL Register*  
S
X
X
SCSI Interface**  
SCSI Interface**  
SODR Register*  
S
SCSI Interface**  
X = Check parity  
G = Generate 32-bit even PCI parity  
S = Generate 8-bit odd SCSI parity  
* = No parity protection  
** = Parity protected  
2.2.12 DMA FIFO  
The DMA FIFO is 8 bytes wide by 118 transfers deep. The DMA FIFO is  
illustrated in Figure 2.3. The default DMA FIFO size is 112 bytes to  
assure compatibility with older products in the LSI53C8XX family.  
The DMA FIFO size may be set to 944 bytes by setting the DMA FIFO  
Size bit, bit 5, in the Chip Test Five (CTEST5) register.  
SCSI Functional Description  
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Figure 2.3 DMA FIFO Sections  
8 Bytes Wide  
.
.
.
.
.
.
118  
Transfers  
Deep  
8 Bits  
8 Bits  
8 Bits  
8 Bits  
8 Bits  
8 Bits  
8 Bits  
8 Bits  
Byte Lane 7 Byte Lane 6 Byte Lane 5 Byte Lane 4 Byte Lane 3 Byte Lane 2 Byte Lane 1 Byte Lane 0  
The LSI53C875A automatically supports misaligned DMA transfers. A  
944-byte FIFO allows the LSI53C875A to support 2, 4, 8, 16, 32, 64, or  
128 Dword bursts across the PCI bus interface.  
2.2.12.1 Data Paths  
The data path through the LSI53C875A is dependent on whether data is  
being moved into or out of the chip, and whether SCSI data is being  
transferred asynchronously or synchronously.  
Figure 2.4 shows how data is moved to/from the SCSI bus in each of the  
different modes.  
2-28  
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Figure 2.4 LSI53C875A Host Interface SCSI Data Paths  
Asynchronous  
SCSI Send  
Synchronous  
SCSI Send  
Synchronous  
SCSI Receive  
Asynchronous  
SCSI Receive  
PCI Interface**  
PCI Interface**  
PCI Interface**  
PCI Interface**  
DMA FIFO*  
(8 Bytes x 118)  
DMA FIFO*  
(8 Bytes x 118)  
DMA FIFO*  
(8 Bytes x 118)  
DMA FIFO*  
(8 Bytes x 118)  
SWIDE Register  
SWIDE Register  
SCSI FIFO**  
(1 or 2 Bytes x 31)  
SODL Register*  
SIDL Register*  
SCSI Interface**  
SODL Register*  
SCSI Interface**  
SODR Register*  
SCSI Interface**  
SCSI Interface**  
* = No parity protection  
** = Parity protected  
The following steps determine if any bytes remain in the data path when  
Asynchronous SCSI Send –  
Step 1. If the DMA FIFO size is set to 112 bytes (bit 5 of the Chip Test  
Five (CTEST5) register cleared), look at the DMA FIFO  
(DFIFO) and DMA Byte Counter (DBC) registers and calculate  
if there are bytes left in the DMA FIFO. To make this calculation,  
subtract the seven least significant bits of the DBC register from  
the 7-bit value of the DFIFO register. AND the result with 0x7F  
for a byte count between zero and 112.  
If the DMA FIFO size is set to 944 bytes (bit 5 of the Chip Test  
Five (CTEST5) register is set), subtract the 10 least significant  
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bits of the DBC register from the 10-bit value of the DMA FIFO  
register and bits [7:0] of the DMA FIFO register. AND the result  
with 0x3FF for a byte count between zero and 944.  
Step 2. Read bit 5 in the SCSI Status Zero (SSTAT0) and SCSI Status  
Two (SSTAT2) registers to determine if any bytes are left in the  
SCSI Output Data Latch (SODL) register. If bit 5 is set in the  
SSTAT0 or SSTAT2 register, then the least significant byte or  
the most significant byte in the SODL register is full,  
respectively. Checking this bit also reveals bytes left in the  
SODL register from a Chained Move operation with an odd byte  
count.  
Synchronous SCSI Send –  
Step 1. If the DMA FIFO size is set to 112 bytes (bit 5 of the Chip Test  
Five (CTEST5) register cleared), look at the DFIFO and DBC  
registers and calculate if there are bytes left in the DMA FIFO.  
To make this calculation, subtract the seven least significant bits  
of the DMA Byte Counter (DBC) register from the 7-bit value of  
the DMA FIFO (DFIFO) register. AND the result with 0x7F for  
a byte count between zero and 112.  
If the DMA FIFO size is set to 944 bytes (bit 5 of the CTEST5  
register is set), subtract the 10 least significant bits of the DBC  
register from the 10-bit value of the DMA FIFO Byte Offset  
bits [7:0] of the DMA FIFO register. AND the result with 0x3FF  
for a byte count between zero and 944.  
Step 2. Read bit 5 in the SCSI Status Zero (SSTAT0) and SCSI Status  
Two (SSTAT2) registers to determine if any bytes are left in the  
SCSI Output Data Latch (SODL) register. If bit 5 is set in the  
SSTAT0 or SSTAT2 register, then the least significant byte or  
the most significant byte in the SODL register is full,  
respectively. Checking this bit also reveals bytes left in the  
SODL register from a Chained Move operation with an odd byte  
count.  
Step 3. Read bit 6 in the SCSI Status Zero (SSTAT0) and SCSI Status  
Two (SSTAT2) registers to determine if any bytes are left in the  
SODR register (a hidden buffer register which is not  
accessible). If bit 6 is set in the SSTAT0 or SSTAT2 register,  
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then the least significant byte or the most significant byte in the  
Asynchronous SCSI Receive –  
Step 1. If the DMA FIFO size is set to 112 bytes (bit 5 of the Chip Test  
Five (CTEST5) register cleared), look at the DMA FIFO  
(DFIFO) and DMA Byte Counter (DBC) registers and calculate  
if there are bytes left in the DMA FIFO. To make this calculation,  
subtract the seven least significant bits of the DBC register from  
the 7-bit value of the DFIFO register. AND the result with 0x7F  
for a byte count between zero and 88.  
If the DMA FIFO size is set to 944 bytes (bit 5 of the Chip Test  
Five (CTEST5) register is set), subtract the 10 least significant  
bits of the DMA Byte Counter (DBC) register from the 10-bit  
value of the DMA FIFO Byte Offset Counter, which consists of  
register. AND the result with 0x3FF for a byte count between  
zero and 944.  
Step 2. Read bit 7 in the SCSI Status Zero (SSTAT0) and SCSI Status  
Two (SSTAT2) registers to determine if any bytes are left in the  
SCSI Input Data Latch (SIDL) register. If bit 7 is set in the  
the most significant byte is full, respectively.  
Step 3. If any wide transfers have been performed using the Chained  
Move instruction, read the Wide SCSI Receive bit (SCSI Status  
Two (SSTAT2), bit 0) to determine whether a byte is left in the  
SCSI Wide Residue (SWIDE) register.  
Synchronous SCSI Receive –  
Step 1. If the DMA FIFO size is set to 112 bytes, subtract the seven  
least significant bits of the DMA Byte Counter (DBC) register  
from the 7-bit value of the DMA FIFO (DFIFO) register. AND  
the result with 0x7F for a byte count between zero and 112.  
If the DMA FIFO size is set to 944 bytes (bit 5 of the Chip Test  
Five (CTEST5) register is set), subtract the 10 least significant  
bits of the DBC register from the 10-bit value of the DMA FIFO  
Byte Offset Counter, which consists of bits [1:0] in the Chip Test  
Five (CTEST5) register and bits [7:0] of the DMA FIFO register.  
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AND the result with 0x3FF for a byte count between zero and  
944.  
Step 2. Read the SCSI Status One (SSTAT1) register and examine bits  
[7:4], the binary representation of the number of valid bytes in  
the SCSI FIFO, to determine if any bytes are left in the SCSI  
FIFO.  
Step 3. If any wide transfers have been performed using the Chained  
Move instruction, read the Wide SCSI Receive bit (SCSI  
Control Two (SCNTL2), bit 0) to determine whether a byte is left  
in the SCSI Wide Residue (SWIDE) register.  
2.2.13 SCSI Bus Interface  
The LSI53C875A performs SE transfers. TolerANT technology provides  
signal filtering at the inputs of SREQ/ and SACK/ to increase immunity  
to signal reflections.  
2.2.13.1 SCSI Termination  
The terminator networks provide the biasing needed to pull signals to an  
inactive voltage level. They also match the impedance seen at the end  
of the cable with the characteristic impedance of the cable. Terminators  
must be installed at the extreme ends of the SCSI chain and only at the  
ends. No system should ever have more or less than two terminators  
installed and active. SCSI host adapters should provide a means of  
accommodating terminators. The terminators should be socketed, so that  
if not needed they may be removed, or there should be a means of  
disabling them with software.  
SE cables can use a 220 pull-up to the terminator power supply  
(Term Power) line and a 330 pull-down to ground. Due to the high  
performance nature of the LSI53C875A, regulated or active termination  
is recommended. Figure 2.5 shows a Unitrode active terminator. For  
additional information, refer to the SCSI-2 Specification. TolerANT  
technology active negation can be used with either termination network.  
Note:  
If the LSI53C875A is used with an 8-bit SCSI bus, all  
16 data lines must still be terminated or pulled HIGH.  
Note:  
Active termination is required for Ultra SCSI synchronous  
transfers.  
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Figure 2.5 Regulated Termination for Ultra SCSI  
UC5601QP  
(UC5610 for Ultra SCSI)  
20  
21  
22  
23  
24  
25  
26  
27  
28  
TERML1  
2
SD0 (J1.40)  
SD1 (J1.41)  
SD2 (J1.42)  
SD3 (J1.43)  
SD4 (J1.44)  
SD5 (J1.45)  
SD6 (J1.46)  
SD7 (J1.47)  
SDP0 (J1.48)  
2.85 V  
REG_OUT  
TERML2  
TERML3  
TERML4  
TERML5  
TERML6  
TERML7  
TERML8  
TERML9  
C1  
C2  
3
4
5
6
7
8
9
10  
11  
ATN (J1.55)  
BSY (J1.57)  
ACK (J1.58)  
RST (J1.59)  
MSG (J1.60)  
SEL (J1.61)  
C/D (J1.62)  
REQ (J1.63)  
I/O (J1.64)  
TERML10  
TERML11  
TERML12  
TERML13  
TERML14  
TERML15  
TERML16  
TERML17  
TERML18  
19  
DISCONNECT  
UC5603DP  
(UC5614 for Ultra SCSI)  
10  
9
8
7
3
2
1
16  
15  
TERML1  
SD15 (J1.38)  
SD14 (J1.37)  
SD13 (J1.36)  
SD12 (J1.35)  
SD11 (J1.68)  
SD10 (J1.67)  
SD9 (J1.66)  
SD8 (J1.65)  
SDP1 (J1.39)  
14  
REG_OUT  
TERML2  
TERML3  
TERML4  
TERML5  
TERML6  
TERML7  
TERML8  
TERML9  
C3  
6
DISCONNECT  
Note:  
1. C1 - 10 µF SMT  
2. C2 - 0.1 µF SMT  
3. C3 - 2.2 µF SMT  
4. J1 - 68-pin, high density “P” connector  
2.2.14 Select/Reselect During Selection/Reselection  
In multithreaded SCSI I/O environments, it is not uncommon to be  
selected or reselected while trying to perform selection/reselection. This  
SCSI Functional Description  
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situation may occur when a SCSI controller (operating in the initiator  
mode) tries to select a target and is reselected by another. The Select  
SCRIPTS instruction has an alternate address to which the SCRIPTS will  
jump when this situation occurs. The analogous situation for target  
devices is being selected while trying to perform a reselection.  
Once a change in operating mode occurs, the initiator SCRIPTS should  
with a Set Target instruction. The Selection and Reselection Enable bits  
(SCSI Chip ID (SCID) bits 5 and 6, respectively) should both be asserted  
so that the LSI53C875A may respond as an initiator or as a target. If only  
selection is enabled, the LSI53C875A cannot be reselected as an  
initiator. There are also status and interrupt bits in the SCSI Interrupt  
Status Zero (SIST0) and SCSI Interrupt Enable Zero (SIEN0) registers,  
respectively, indicating that the LSI53C875A has been selected (bit 5)  
and reselected (bit 4).  
2.2.15 Synchronous Operation  
The LSI53C875A can transfer synchronous SCSI data in both the  
initiator and target modes. The SCSI Transfer (SXFER) register controls  
both the synchronous offset and the transfer period. It may be loaded by  
the CPU before SCRIPTS execution begins, from within SCRIPTS using  
a Table Indirect I/O instruction, or with a Read-Modify-Write instruction.  
The LSI53C875A can receive data from the SCSI bus at a synchronous  
transfer period as short as 50 ns, regardless of the transfer period used  
to send data. The LSI53C875A can receive data at one-fourth of the  
divided SCLK frequency. Depending on the SCLK frequency, the  
negotiated transfer period, and the synchronous clock divider, the  
LSI53C875A can send synchronous data at intervals as short as 50 ns  
for Ultra SCSI, 100 ns for fast SCSI and 200 ns for SCSI-1.  
2.2.15.1 Determining the Data Transfer Rate  
Synchronous data transfer rates are controlled by bits in two different  
registers of the LSI53C875A. Following is a brief description of the bits.  
Figure 2.6 illustrates the clock division factors used in each register, and  
the role of the register bits in determining the transfer rate.  
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Figure 2.6 Determining the Synchronous Transfer Rate  
SCF2  
SCF1  
SCF0  
SCF  
TP2  
TP1  
TP0  
XFERP  
Divisor  
Divisor  
0
0
0
1
0
1
1
1
0
1
1
0
0
0
1
1
1
0
1
0
0
1
0
1
1
1.5  
2
3
3
4
6
8
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
4
5
6
7
8
9
10  
11  
This point  
must not  
exceed  
160 MHz  
Divide by 4  
Receive  
Clock  
Synchronous  
Divider  
Send Clock  
(to SCSI Bus)  
This point must  
SCF  
Divider  
Clock  
Quadrupler  
SCLK  
QCLK  
not exceed 20 MHz.  
CCF  
Divider  
Asynchronous  
SCSI Logic  
CCF2  
CCF1  
CCF0  
Divisor  
QCLK (MHz)  
0
0
0
1
0
1
1
1
0
1
1
0
0
0
1
1
1
0
1
0
0
1
0
1
1
1.5  
2
3
3
4
6
8
50.1–66.00  
16.67–25.00  
25.1–37.50  
37.51–50.00  
50.01–66.00  
75.01–80.00  
120  
160  
Example 1 (using 40 MHz clock)  
SCLK = 40 MHz  
Example 2 (using 20 MHz clock)  
SCLK = 20 MHz  
QCLK (Quadrupled SCSI Clock) = 160 MHz  
SCF = 1 (/1), XFERP = 4 (/8), CCF = 7 (/8)  
QCLK (Quadrupled SCSI Clock) = 80 MHz  
SCF = 1 (/1), XFERP = 0 (/4), CCF = 5 (/4)  
Synchronous send rate = (QCLK/SCF)/XFERP =  
(160/1) /8 = 20 Mbytes/s  
Synchronous send rate = (QCLK/SCF)/XFERP =  
(80/1) /4 = 20 Mbytes/s  
1
Synchronous receive rate = (QCLK/SCF) /4 =  
(160/1) /4 = 40 Mbytes/s  
Synchronous receive rate = (QCLK/SCF) /4 =  
(80/1) /4 = 20 Mbytes/s  
2
Note:  
Synchronous send rate must not exceed 20 Mbytes/s because the  
LSI53C875A is an Ultra SCSI device.  
Although maximum synchronous receive rate is 40 Mbytes/s the  
maximum transfer rate is 20 Mbytes/s because the LSI53C875A is an  
Ultra SCSI device.  
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2.2.15.2 SCSI Control Three (SCNTL3) Register, Bits [6:4] (SCF[2:0])  
The SCF[2:0] bits select the factor by which the frequency of SCLK is  
divided before being presented to the synchronous SCSI control logic.  
The output from this divider controls the rate at which data can be  
received; this rate must not exceed 160 MHz. The receive rate of  
synchronous SCSI data is one-fourth of the SCF divider output. For  
example, if SCLK is 80 MHz and the SCF value is set to divide by one,  
then the maximum rate at which data can be received is 20 MHz  
(80/(1*4) = 20).  
2.2.15.3 SCSI Control Three (SCNTL3) Register, Bits [2:0] (CCF[2:0])  
The CCF[2:0] bits select the factor by which the frequency of SCLK is  
divided before being presented to the asynchronous SCSI core logic.  
This divider must be set according to the input clock frequency in the  
table.  
2.2.15.4 SCSI Transfer (SXFER) Register, Bits [7:5] (TP[2:0])  
The TP[2:0] divider bits determine the SCSI synchronous transfer period  
when sending synchronous SCSI data in either the initiator or target  
mode. This value further divides the output from the SCF divider.  
2.2.15.5 Ultra SCSI Synchronous Data Transfers  
Ultra SCSI is an extension of the current Fast SCSI-2 synchronous  
transfer specifications. It allows synchronous transfer periods to be  
negotiated down as low as 50 ns, which is half the 100 ns period allowed  
under Fast SCSI-2. This allows a maximum transfer rate of 40 Mbytes/s  
on a 16-bit SCSI bus. The LSI53C875A has a SCSI clock quadrupler that  
must be enabled for the chip to perform Ultra SCSI transfers with a 20  
or 40 MHz oscillator. In addition, the following bit values affect the chip’s  
ability to support Ultra SCSI synchronous transfer rates:  
Clock Conversion Factor bits, SCSI Control Three (SCNTL3) register  
bits [2:0] and Synchronous Clock Conversion Factor bits, SCNTL3  
register bits [6:4]. These fields support a value of 111 (binary),  
allowing the 160 MHz SCLK frequency to be divided by 8 for the  
asynchronous logic.  
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Ultra SCSI Enable bit, SCSI Control Three (SCNTL3) register bit 7.  
Setting this bit enables Ultra SCSI synchronous transfers in systems  
that use the internal SCSI clock quadrupler.  
TolerANT Enable bit, SCSI Test Three (STEST3) register bit 7. Active  
negation must be enabled for the LSI53C875A to perform Ultra SCSI  
transfers.  
2.2.16 Interrupt Handling  
The SCRIPTS processors in the LSI53C875A perform most functions  
independently of the host microprocessor. However, certain interrupt  
situations must be handled by the external microprocessor. This section  
explains all aspects of interrupts as they apply to the LSI53C875A.  
2.2.16.1 Polling and Hardware Interrupts  
The external microprocessor is informed of an interrupt condition by  
polling or hardware interrupts. Polling means that the microprocessor  
must continually loop and read a register until it detects a bit that is set  
indicating an interrupt. This method is the fastest, but it wastes CPU time  
that could be used for other system tasks. The preferred method of  
detecting interrupts in most systems is hardware interrupts. In this case,  
the LSI53C875A asserts the Interrupt Request (IRQ/) line that interrupts  
the microprocessor, causing the microprocessor to execute an interrupt  
2.2.16.2 Registers  
The registers in the LSI53C875A that are used for detecting or defining  
interrupts are Interrupt Status Zero (ISTAT0), Interrupt Status One  
Status Zero (SIST0), SCSI Interrupt Status One (SIST1), DMA Status  
(DSTAT), SCSI Interrupt Enable Zero (SIEN0), SCSI Interrupt Enable  
One (SIEN1), DMA Control (DCNTL), and DMA Interrupt Enable (DIEN).  
ISTAT – The ISTAT register includes the Interrupt Status Zero (ISTAT0),  
Interrupt Status One (ISTAT1), Chip Test Zero (CTEST0), and Mailbox  
One (MBOX1) registers. It is the only register that can be accessed as a  
slave during the SCRIPTS operation. Therefore, it is the register that is  
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polled when polled interrupts are used. It is also the first register that  
should be read after the IRQ/ pin is asserted in association with a  
hardware interrupt. The INTF (Interrupt-on-the-Fly) bit should be the first  
interrupt serviced. It must be written to one to be cleared. This interrupt  
must be cleared before servicing any other interrupts.  
See Register 0x14, Interrupt Status Zero (ISTAT0) register, bit 5 Signal  
process in Chapter 4, “Registers,” for additional information.  
The host (C Code) or the SCRIPTS code could potentially try to access  
the mailbox bits at the same time.  
If the SIP bit in the Interrupt Status Zero (ISTAT0) register is set, then a  
SCSI-type interrupt has occurred and the SCSI Interrupt Status Zero  
(SIST0) and SCSI Interrupt Status One (SIST1) registers should be read.  
If the DIP bit in the Interrupt Status Zero (ISTAT0) register is set, then a  
DMA-type interrupt has occurred and the DMA Status (DSTAT) register  
should be read.  
SCSI-type and DMA-type interrupts may occur simultaneously, so in  
some cases both SIP and DIP may be set.  
SIST0 and SIST1 – The SCSI Interrupt Status Zero (SIST0) and SCSI  
Interrupt Status One (SIST1) registers contain SCSI-type interrupt bits.  
Reading these registers determines which condition or conditions caused  
the SCSI-type interrupt, and clears that SCSI interrupt condition.  
If the LSI53C875A is receiving data from the SCSI bus and a fatal  
interrupt condition occurs, the chip attempts to send the contents of the  
DMA FIFO to memory before generating the interrupt.  
If the LSI53C875A is sending data to the SCSI bus and a fatal SCSI  
interrupt condition occurs, data could be left in the DMA FIFO. Because  
of this the DMA FIFO Empty (DFE) bit in DMA Status (DSTAT) should be  
checked.  
If this bit is cleared, set the CLF (Clear DMA FIFO) and CSF (Clear SCSI  
FIFO) bits before continuing. The CLF bit is bit 2 in Chip Test Three  
(CTEST3). The CSF bit is bit 1 in SCSI Test Three (STEST3).  
DSTAT – The DMA Status (DSTAT) register contains the DMA-type  
interrupt bits. Reading this register determines which condition or  
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conditions caused the DMA-type interrupt, and clears that DMA interrupt  
condition. Bit 7 in DSTAT, DFE, is purely a status bit; it will not generate  
an interrupt under any circumstances and will not be cleared when read.  
DMA interrupts flush neither the DMA nor SCSI FIFOs before generating  
the interrupt, so the DFE bit in the DMA Status (DSTAT) register should  
be checked after any DMA interrupt.  
If the DFE bit is cleared, then the FIFOs must be cleared by setting the  
CLF (Clear DMA FIFO) and CSF (Clear SCSI FIFO) bits, or flushed by  
setting the FLF (Flush DMA FIFO) bit.  
SIEN0 and SIEN1 – The SCSI Interrupt Enable Zero (SIEN0) and SCSI  
Interrupt Enable One (SIEN1) registers are the interrupt enable registers  
for the SCSI interrupts in SCSI Interrupt Status Zero (SIST0) and SCSI  
Interrupt Status One (SIST1).  
DIEN – The DMA Interrupt Enable (DIEN) register is the interrupt enable  
register for DMA interrupts in DMA Status (DSTAT).  
DCNTL – When bit 1 in the DMA Control (DCNTL) register is set, the  
IRQ/ pin is not asserted when an interrupt condition occurs. The interrupt  
is not lost or ignored, but is merely masked at the pin. Clearing this bit  
when an interrupt is pending immediately causes the IRQ/ pin to assert.  
As with any register other than ISTAT, this register cannot be accessed  
except by a SCRIPTS instruction during SCRIPTS execution.  
2.2.16.3 Fatal vs. Nonfatal Interrupts  
A fatal interrupt, as the name implies, always causes the SCRIPTS to  
stop running. All nonfatal interrupts become fatal when they are enabled  
by setting the appropriate interrupt enable bit. Interrupt masking is  
by the DIP bit in ISTAT and one or more bits in DMA Status (DSTAT)  
being set) are fatal.  
Some SCSI interrupts (indicated by the SIP bit in the Interrupt Status  
Zero (ISTAT0) and one or more bits in SCSI Interrupt Status Zero  
(SIST0) or SCSI Interrupt Status One (SIST1) being set) are nonfatal.  
When the LSI53C875A is operating in the Initiator mode, only the  
Function Complete (CMP), Selected (SEL), Reselected (RSL), General  
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Purpose Timer Expired (GEN), and Handshake-to-Handshake Timer  
Expired (HTH) interrupts are nonfatal.  
When operating in the Target mode, CMP, SEL, RSL, Target mode:  
SATN/ active (M/A), GEN, and HTH are nonfatal. Refer to the description  
for the Disable Halt on a Parity Error or SATN/ active (Target Mode Only)  
(DHP) bit in the SCSI Control One (SCNTL1) register to configure the  
chip’s behavior when the SATN/ interrupt is enabled during Target mode  
operation. The Interrupt-on-the-Fly interrupt is also nonfatal, since  
SCRIPTS can continue when it occurs.  
The reason for nonfatal interrupts is to prevent the SCRIPTS from  
stopping when an interrupt occurs that does not require service from the  
CPU. This prevents an interrupt when arbitration is complete (CMP set),  
when the LSI53C875A is selected or reselected (SEL or RSL set), when  
the initiator asserts ATN (target mode: SATN/ active), or when the  
General Purpose or Handshake-to-Handshake timers expire. These  
interrupts are not needed for events that occur during high-level  
2.2.16.4 Masking  
Masking an interrupt means disabling or ignoring that interrupt. Interrupts  
can be masked by clearing bits in the SCSI Interrupt Enable Zero  
(SIEN0) and SCSI Interrupt Enable One (SIEN1) (for SCSI interrupts)  
registers or DMA Interrupt Enable (DIEN) (for DMA interrupts) register.  
How the chip responds to masked interrupts depends on: whether polling  
or hardware interrupts are being used; whether the interrupt is fatal or  
nonfatal; and whether the chip is operating in the Initiator or Target mode.  
If a nonfatal interrupt is masked and that condition occurs, the SCRIPTS  
do not stop, the appropriate bit in the SCSI Interrupt Status Zero (SIST0)  
Interrupt Status Zero (ISTAT0) is not set, and the IRQ/ pin is not  
asserted.  
If a fatal interrupt is masked and that condition occurs, then the SCRIPTS  
still stop, the appropriate bit in the DMA Status (DSTAT), SCSI Interrupt  
Status Zero (SIST0), or SCSI Interrupt Status One (SIST1) register is  
set, and the SIP or DIP bit in the Interrupt Status Zero (ISTAT0) register  
is set, but the IRQ/ pin is not asserted.  
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Interrupts can be disabled by setting SYNC_IRQD bit 0 in the Interrupt  
Status One (ISTAT1) register. If an interrupt is already asserted and  
SYNC_IRQD is then set, the interrupt will remain asserted until serviced.  
At this point, the IRQ/ pin is blocked for future interrupts until this bit is  
cleared. When the LSI53C875A is initialized, enable all fatal interrupts if  
you are using hardware interrupts. If a fatal interrupt is disabled and that  
interrupt condition occurs, the SCRIPTS halt and the system never  
knows it unless it times out and checks the ISTAT register after a certain  
period of inactivity.  
If you are polling the ISTAT instead of using hardware interrupts, then  
masking a fatal interrupt makes no difference since the SIP and DIP bits  
in the Interrupt Status Zero (ISTAT0) inform the system of interrupts, not  
the IRQ/ pin.  
Masking an interrupt after IRQ/ is asserted does not cause deassertion  
of IRQ/.  
2.2.16.5 Stacked Interrupts  
The LSI53C875A will stack interrupts if they occur one after the other. If  
the SIP or DIP bits in the ISTAT register are set (first level), then there is  
already at least one pending interrupt, and any future interrupts are  
stacked in extra registers behind the SCSI Interrupt Status Zero (SIST0),  
SCSI Interrupt Status One (SIST1), and DMA Status (DSTAT) registers  
(second level). When two interrupts have occurred and the two levels of  
the stack are full, any further interrupts set additional bits in the extra  
registers behind SCSI Interrupt Status Zero (SIST0), SCSI Interrupt  
Status One (SIST1), and DMA Status (DSTAT). When the first level of  
interrupts are cleared, all the interrupts that came in afterward move into  
SIST0, SIST1, and DSTAT. After the first interrupt is cleared by reading  
the appropriate register, the IRQ/ pin is deasserted for a minimum of  
three CLKs; the stacked interrupts move into SIST0, SIST1, or DSTAT;  
Since a masked nonfatal interrupt does not set the SIP or DIP bits,  
interrupt stacking does not occur. A masked, nonfatal interrupt still posts  
the interrupt in SIST0, but does not assert the IRQ/ pin. Since no  
interrupt is generated, future interrupts move into SCSI Interrupt Status  
Zero (SIST0) or SCSI Interrupt Status One (SIST1) instead of being  
stacked behind another interrupt. When another condition occurs that  
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generates an interrupt, the bit corresponding to the earlier masked  
nonfatal interrupt is still set.  
A related situation to interrupt stacking is when two interrupts occur  
simultaneously. Since stacking does not occur until the SIP or DIP bits  
are set, there is a small timing window in which multiple interrupts can  
occur but are not stacked. These could be multiple SCSI interrupts (SIP  
set), multiple DMA interrupts (DIP set), or multiple SCSI and multiple  
DMA interrupts (both SIP and DIP set).  
As previously mentioned, DMA interrupts do not attempt to flush the  
FIFOs before generating the interrupt. It is important to set either the  
Clear DMA FIFO (CLF) and Clear SCSI FIFO (CSF) bits if a DMA  
interrupt occurs and the DMA FIFO Empty (DFE) bit is not set. This is  
because any future SCSI interrupts are not posted until the DMA FIFO  
is cleared of data. These ‘locked out’ SCSI interrupts are posted as soon  
as the DMA FIFO is empty.  
2.2.16.6 Halting in an Orderly Fashion  
When an interrupt occurs, the LSI53C875A attempts to halt in an orderly  
fashion.  
If the interrupt occurs in the middle of an instruction fetch, the fetch  
is completed, except in the case of a Bus Fault. Execution does not  
begin, but the DMA SCRIPTS Pointer (DSP) points to the next  
instruction since it is updated when the current instruction is fetched.  
If the DMA direction is a write to memory and a SCSI interrupt  
occurs, the LSI53C875A attempts to flush the DMA FIFO to memory  
before halting. Under any other circumstances only the current cycle  
is completed before halting, so the DFE bit in DMA Status (DSTAT)  
register should be checked to see if any data remains in the DMA  
FIFO.  
SCSI SREQ/SACK handshakes that have begun are completed  
before halting.  
The LSI53C875A attempts to clean up any outstanding synchronous  
offset before halting.  
In the case of Transfer Control Instructions, once instruction  
execution begins it continues to completion before halting.  
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If the instruction is a JUMP/CALL WHEN/IF <phase>, the DMA  
SCRIPTS Pointer (DSP) is updated to the transfer address before  
halting.  
All other instructions may halt before completion.  
2.2.16.7 Sample Interrupt Service Routine  
The following is a sample of an interrupt service routine for the  
LSI53C875A. It can be repeated during polling or should be called when  
1. Read Interrupt Status Zero (ISTAT0).  
2. If the INTF bit is set, it must be written to a one to clear this status.  
3. If only the SIP bit is set, read SCSI Interrupt Status Zero (SIST0) and  
SCSI Interrupt Status One (SIST1) to clear the SCSI interrupt  
condition and get the SCSI interrupt status. The bits in the SIST0  
and SIST1 tell which SCSI interrupts occurred and determine what  
action is required to service the interrupts.  
interrupt condition and get the DMA interrupt status. The bits in  
DSTAT tell which DMA interrupts occurred and determine what action  
is required to service the interrupts.  
5. If both the SIP and DIP bits are set, read SCSI Interrupt Status Zero  
(SIST0), SCSI Interrupt Status One (SIST1), and DMA Status  
(DSTAT) to clear the SCSI and DMA interrupt condition and get the  
interrupt status. If using 8-bit reads of the SIST0, SIST1, and DSTAT  
registers to clear interrupts, insert a 12 CLK delay between the  
consecutive reads to ensure that the interrupts clear properly. Both  
the SCSI and DMA interrupt conditions should be handled before  
leaving the interrupt service routine. It is recommended that the DMA  
interrupt is serviced before the SCSI interrupt, because a serious  
DMA interrupt condition could influence how the SCSI interrupt is  
acted upon.  
6. When using polled interrupts, go back to Step 1 before leaving the  
interrupt service routine, in case any stacked interrupts moved in  
when the first interrupt was cleared. When using hardware interrupts,  
the IRQ/ pin is asserted again if there are any stacked interrupts.  
This should cause the system to re-enter the interrupt service  
routine.  
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2.2.17 Chained Block Moves  
Since the LSI53C875A has the capability to transfer 16-bit wide SCSI  
data, a unique situation occurs when dealing with odd bytes. The  
Chained Move (CHMOV) SCRIPTS instruction along with the Wide SCSI  
Send (WSS) and Wide SCSI Receive (WSR) bits in the SCSI Control  
Two (SCNTL2) register are used to facilitate these situations. The  
Chained Block Move instruction is illustrated in Figure 2.7.  
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Figure 2.7 Block Move and Chained Block Move Instructions  
Host Memory  
SCSI Bus  
0x04  
0x03  
0x07  
0x0B  
0x02  
0x06  
0x0A  
0x01  
0x00  
0x04  
0x08  
0x03  
0x05  
0x06  
0x05  
0x09  
0x0F  
0x13  
0x0E  
0x12  
0x0D  
0x11  
0x0C  
0x10  
0x09  
0x07  
0x0B  
0x0D  
0x0A  
0x0C  
32 Bits  
16 Bits  
2.2.17.1 Wide SCSI Send Bit  
The WSS bit is set whenever the SCSI controller is sending data  
(Data-Out for initiator or Data-In for target) and the controller detects a  
partial transfer at the end of a chained Block Move SCRIPTS instruction  
(this flag is not set if a normal Block Move instruction is used). Under this  
condition, the SCSI controller does not send the low-order byte of the last  
partial memory transfer across the SCSI bus. Instead, the low-order byte  
is temporarily stored in the lower byte of the SCSI Output Data Latch  
(SODL) register and the WSS flag is set. The hardware uses the WSS  
flag to determine what behavior must occur at the start of the next data  
send transfer. When the WSS flag is set at the start of the next transfer,  
the first byte (the high-order byte) of the next data send transfer is  
“married” with the stored low-order byte in the SODL register; and the  
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two bytes are sent out across the bus, regardless of the type of Block  
Move instruction (normal or chained). The flag is automatically cleared  
when the “married” word is sent. The flag is alternately cleared through  
SCRIPTS or by the microprocessor. Also, the microprocessor or  
SCRIPTS can use this bit for error detection and recovery purposes.  
2.2.17.2 Wide SCSI Receive Bit  
The WSR bit is set whenever the SCSI controller is receiving data  
(Data-In for initiator or Data-Out for target) and the controller detects a  
partial transfer at the end of a block move or chained block move  
SCRIPTS instruction. When WSR is set, the high-order byte of the last  
SCSI bus transfer is not transferred to memory. Instead, the byte is  
temporarily stored in the SCSI Wide Residue (SWIDE) register. The  
hardware uses the WSR bit to determine what behavior must occur at  
the start of the next data receive transfer. The bit is automatically cleared  
at the start of the next data receive transfer. The bit can alternatively be  
cleared by the microprocessor or through SCRIPTS. Also, the  
microprocessor or SCRIPTS can use this bit for error detection and  
recovery purposes.  
2.2.17.3 SWIDE Register  
This register stores data for partial byte data transfers. For receive data,  
the SCSI Wide Residue (SWIDE) register holds the high-order byte of a  
partial SCSI transfer which has not yet been transferred to memory. This  
stored data may be a residue byte (and therefore ignored) or it may be  
valid data that is transferred to memory at the beginning of the next Block  
Move instruction.  
2.2.17.4 SODL Register  
For send data, the low-order byte of the SCSI Output Data Latch (SODL)  
register holds the low-order byte of a partial memory transfer which has  
not yet been transferred across the SCSI bus. This stored data is usually  
“married” with the first byte of the next data send transfer, and both bytes  
are sent across the SCSI bus at the start of the next data send block  
move command.  
2-46  
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2.2.17.5 Chained Block Move SCRIPTS Instruction  
A chained Block Move SCRIPTS instruction is primarily used to transfer  
consecutive data send or data receive blocks. Using the chained Block  
Move instruction facilitates partial receive transfers and allows correct  
partial send behavior without additional opcode overhead. Behavior of  
the chained Block Move instruction varies slightly for sending and  
receiving data.  
For receive data (Data-In for initiator or Data-Out for target), a chained  
Block Move instruction indicates that if a partial transfer occurred at the  
end of the instruction, the WSR flag is set. The high-order byte of the  
last SCSI transfer is stored in the SCSI Wide Residue (SWIDE) register  
rather than transferred to memory. The contents of the SWIDE register  
should be the first byte transferred to memory at the start of the chained  
Block Move data stream. Since the byte count always represents data  
transfers to/from memory (as opposed to the SCSI bus), the byte  
transferred out of the SCSI Wide Residue (SWIDE) register is one of the  
bytes in the byte count. If the WSR bit is cleared when a receive data  
chained Block Move instruction is executed, the data transfer occurs  
similar to that of the regular Block Move instruction. Whether the WSR  
bit is set or cleared, when a normal block move instruction is executed,  
the contents of the SCSI Wide Residue (SWIDE) register are ignored  
and the transfer takes place normally. For “N” consecutive wide data  
receive Block Move instructions, the 2nd through the Nth Block Move  
instructions should be chained block moves.  
For send data (Data-Out for initiator or Data-In for target), a chained  
Block Move instruction indicates that if a partial transfer terminates the  
chained block move instruction, the last low-order byte (the partial  
memory transfer) should be stored in the lower byte of the SCSI Output  
Data Latch (SODL) register and not sent across the SCSI bus. Without  
the chained Block Move instruction, the last low-order byte would be sent  
across the SCSI bus. The starting byte count represents data bytes  
transferred from memory but not to the SCSI bus when a partial transfer  
exists. For example, if the instruction is an Initiator chained Block Move  
Data Out of five bytes (and WSS is not previously set), five bytes are  
transferred out of memory to the SCSI controller, four bytes are  
transferred from the SCSI controller across the SCSI bus, and one byte  
is temporarily stored in the lower byte of the SCSI Output Data Latch  
(SODL) register waiting to be married with the first byte of the next Block  
Move instruction. Regardless of whether a chained Block Move or normal  
Block Move instruction is used, if the WSS bit is set at the start of a data  
SCSI Functional Description  
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send command, the first byte of the data send command is assumed to  
be the high-order byte and is “married” with the low-order byte stored in  
the lower byte of the SCSI Output Data Latch (SODL) register before the  
two bytes are sent across the SCSI bus. For “N” consecutive wide data  
send Block Move commands, the first through the (Nth – 1) Block Move  
instructions should be Chained Block Moves.  
CHMOV 5, 3 when Data_Out  
Moves five bytes from address 0x03 in the host memory to the SCSI bus.  
Bytes 0x03, 0x04, 0x05, and 0x06 are moved and byte 0x07 remains in  
the low-order byte of the SCSI Output Data Latch (SODL) register and  
is married with the first byte of the following MOVE instruction.  
MOVE 5, 9 when Data_Out  
Moves five bytes from address 0x09 in the host memory to the SCSI bus.  
2.3 Parallel ROM Interface  
The LSI53C875A supports up to one megabyte of external memory in  
binary increments from 16 Kbytes, to allow the use of expansion ROM  
for add-in PCI cards. This interface is designed for low speed operations  
such as downloading instruction code from ROM; it is not intended for  
dynamic activities such as executing instructions.  
System requirements include the LSI53C875A, two or three external  
8-bit address holding registers (HCT273 or HCT374), and the  
appropriate memory device. The 4.7 kpull-up resistors on the MAD bus  
require HC or HCT external components to be used. If in-system Flash  
ROM updates are required, a 7406 (high voltage open collector inverter),  
a MTD4P05, and several passive components are also needed. The  
memory size and speed is determined by pull-up resistors on the  
8-bit bidirectional memory bus at power-up. The LSI53C875A senses this  
bus shortly after the release of the Reset signal and configures the  
Expansion ROM Base Address register and the memory cycle state  
machines for the appropriate conditions.  
The external memory interface works with a variety of ROM sizes and  
speeds. An example set of interface drawings is in Appendix B, “External  
Memory Interface Diagram Examples.”  
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The LSI53C875A supports a variety of sizes and speeds of expansion  
ROM, using pull-down resistors on the MAD[3:0] pins. The encoding of  
pins MAD[3:1] allows the user to define how much external memory is  
available to the LSI53C875A. Table 2.6 shows the memory space  
associated with the possible values of MAD[3:1]. The MAD[3:1] pins are  
fully described in Chapter 3, “Signal Descriptions.”  
Table 2.6  
MAD[3:1]  
000  
Parallel ROM Support  
Available Memory Space  
16 Kbytes  
001  
010  
011  
100  
101  
110  
111  
32 Kbytes  
64 Kbytes  
128 Kbytes  
256 Kbytes  
512 Kbytes  
1024 Kbytes  
no external memory present  
To use one of the configurations mentioned above in a host adapter  
board design, put 4.7 kpull-up resistors on the MAD pins  
corresponding to the available memory space. For example, to connect  
to a 64 Kbyte external ROM, use a pull-up on MAD2. If the external  
memory interface is not used, MAD[3:1] should be pulled HIGH.  
Note:  
There are internal pull-downs on all of the MAD bus  
signals.  
The LSI53C875A allows the system to determine the size of the available  
external memory using the Expansion ROM Base Address register in the  
PCI configuration space. For more information on how this works, refer  
to the PCI specification or the Expansion ROM Base Address register  
description in Chapter 4, “Registers.”  
MAD0 is the slow ROM pin. When pulled up, it enables two extra clock  
cycles of data access time to allow use of slower memory devices. The  
external memory interface also supports updates to flash memory.  
Parallel ROM Interface  
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2.4 Serial EEPROM Interface  
The LSI53C875A implements an interface that allows attachment of a  
serial EEPROM device to the GPIO0 and GPIO1 pins. There are two  
modes of operation relating to the serial EEPROM and the Subsystem  
ID and Subsystem Vendor ID registers. These modes are programmable  
through the MAD7 pin which is sampled at power-up.  
2.4.1 Default Download Mode  
In this mode, MAD7 is pulled down internally, GPIO0 is the serial data  
signal (SDA) and GPIO1 is the serial clock signal (SCL). Certain data in  
the serial EEPROM is automatically loaded into chip registers at  
power-up.  
The format of the serial EEPROM data is defined in Table 2.7. If the  
download is enabled and an EEPROM is not present, or the checksum  
fails, the Subsystem ID and Subsystem Vendor ID registers read back all  
zeros. At power-up, only five bytes are loaded into the chip from locations  
0xFB through 0xFF.  
The Subsystem ID and Subsystem Vendor ID registers are read only, in  
accordance with the PCI specification, with a default value of all zeros if  
the download fails.  
2-50  
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Table 2.7  
Mode A Serial EEPROM Data Format  
Name Description  
Byte  
0xFB  
SVID(0) Subsystem Vendor ID, LSB. This byte is loaded into the least significant  
byte of the Subsystem Vendor ID register in the appropriate PCI  
configuration space at chip power-up.  
0xFC  
0xFD  
0xFE  
0xFF  
SVID(1) Subsystem Vendor ID, MSB. This byte is loaded into the most significant  
byte of the Subsystem Vendor ID register in the appropriate PCI  
configuration space at chip power-up.  
SID(0)  
Subsystem ID, LSB. This byte is loaded into the least significant byte of  
the Subsystem ID register in the appropriate PCI configuration space at  
chip power-up.  
SID(1)  
Subsystem ID, MSB. This byte is loaded into the most significant byte of  
the Subsystem ID register in the appropriate PCI configuration space at  
chip power-up.  
CKSUM Checksum. This 8-bit checksum is formed by adding, bytewise, each byte  
contained in locations 0x00–0x03 to the seed value 0x55, and then taking  
the 2s complement of the result.  
0x100–0xEOM UD  
User Data.  
2.4.2 No Download Mode  
When MAD7 is pulled up through an external resistor, the automatic  
download is disabled and no data is automatically loaded into chip  
registers at power-up. The Subsystem ID and Subsystem Vendor ID  
registers are read only, per the PCI specification, with a default value of  
0x1000 and 0x1000 respectively.  
2.5 Power Management  
The LSI53C875A complies with the PCI Bus Power Management  
Interface Specification, Revision 1.1. The PCI Function Power States D0,  
D1, D2, and D3 are defined in that specification.  
D0 is the maximum powered state, and D3 is the minimum powered  
state. Power state D3 is further categorized as D3hot or D3cold. A  
function that is powered off is said to be in the D3cold power state.  
Power Management  
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The LSI53C875A power states shown in Table 2.8 are independently  
controlled through two power state bits that are located in the PCI Power  
Management Control/Status (PMCSR) register 0x44.  
Table 2.8  
Power States  
Configuration Register 0x44  
Bits [1:0]  
Power State Function  
00  
01  
10  
11  
D0  
D1  
D2  
D3  
Maximum Power  
Disables SCSI Clock  
Coma Mode  
Minimum Power  
Although the PCI Bus Power Management Interface Specification does  
not allow power state transitions D2 to D1, D3 to D2, or D3 to D1, the  
LSI53C875A hardware places no restriction on transitions between  
power states.  
As the device transitions from one power level to a lower one, the  
attributes that occur from the higher power state level are carried over  
into the lower power state level. For example, D1 disables the SCSI CLK.  
Therefore, D2 will include this attribute as well as the attributes defined  
in the Power State D2 section. The PCI Function Power States D0, D1,  
D2, and D3 are described below. Power state actions are separate for  
each function.  
2.5.1 Power State D0  
Power state D0 is the maximum power state and is the power-up default  
state. The LSI53C875A is fully functional in this state.  
2.5.2 Power State D1  
Power state D1 is a lower power state than D0. In this state, the  
LSI53C875A core is placed in the snooze mode and the SCSI CLK is  
disabled. In the snooze mode, a SCSI reset does not generate an IRQ/  
signal. However, the SCSI CLK is still disabled.  
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2.5.3 Power State D2  
Power state D2 is a lower power state than D1. In this state the  
LSI53C875A core is placed in the coma mode. The following PCI  
Configuration Space command register enable bits are suppressed:  
I/O Space Enable  
Memory Space Enable  
Bus Mastering Enable  
SERR/Enable  
Enable Parity Error Response  
Thus, the memory and I/O spaces cannot be accessed, and the  
LSI53C875A cannot be a PCI bus master. Furthermore, all interrupts are  
disabled when in power state D2. If changed from power state D2 to  
power state D0, the previous values of the PCI command register are  
restored. Also, any pending interrupts before the function entered power  
state D2 are asserted.  
2.5.4 Power State D3  
Power state D3 is the minimum power state, which includes settings  
called D3hot and D3cold. D3hot allows the device to transition to D0  
using software. The LSI53C875A is considered to be in power state  
D3cold when power is removed from the device. D3cold can transition to  
D0 by applying VCC and resetting the device. Furthermore, the device's  
soft reset is continually asserted while in power state D3, which clears  
all pending interrupts and 3-states the SCSI bus. In addition, the device's  
PCI command register is cleared and the Clock Quadrupler is disabled,  
which results in additional power savings.  
Power Management  
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2-54  
Functional Description  
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Chapter 3  
Signal Descriptions  
This chapter presents the LSI53C875A pin configuration and signal  
definitions using tables and illustrations. This chapter contains the  
following sections:  
Section 3.1, “LSI53C875A Functional Signal Grouping”  
Section 3.6, “ROM Flash and Memory Interface Signals”  
Section 3.7, “Test Interface Signals”  
Section 3.8, “Power and Ground Signals”  
Section 3.9, “MAD Bus Programming”  
A slash (/) at the end of a signal name indicates that the active state  
occurs when the signal is at a LOW voltage. When the slash is absent,  
the signal is active at a HIGH voltage.  
LSI53C875A PCI to Ultra SCSI Controller  
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3.1 LSI53C875A Functional Signal Grouping  
Figure 3.1 presents the LSI53C875A signals by functional group.  
Figure 3.1 LSI53C875A Functional Signal Grouping  
LSI53C875A  
CLK  
System  
RST/  
SCLK  
AD[31:0]  
C_BE[3:0]/  
PAR  
Address  
and  
SD[15:0]  
SDP[1:0]  
Data  
FRAME/  
TRDY/  
IRDY/  
STOP/  
DEVSEL/  
IDSEL  
Interface  
Control  
SCD  
SIO  
SCSI  
SMSG  
SREQ  
SACK  
SBSY  
SATN  
SRST  
SSEL  
REQ/  
GNT/  
Arbitration  
PERR/  
SERR/  
Error  
Reporting  
IRQ/  
Interrupt  
GPIO0_FETCH/  
GPIO1_MASTER/  
GPIO2  
GPIO3  
GPIO4  
SCSI  
Function  
GPIO  
TEST_RST/  
TEST_HSC/  
MAC/_TESTOUT  
TCK  
Test  
Interface  
TMS  
TDI  
TDO  
TRST/  
MWE/  
MCE/  
MOE/  
MAC/_TESTOUT  
MAS0/  
MAS1/  
ROM Flash  
& Memory  
Interface  
MAD[7:0]  
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3.2 Signal Descriptions  
The Signal Descriptions are divided into PCI Bus Interface Signals, SCSI  
Bus Interface Signals, GPIO Signals, ROM Flash and Memory Interface  
Signals, Test Interface Signals, and Power and Ground Signals.  
The PCI Bus Interface Signals are subdivided into System Signals,  
Address and Data Signals, Interface Control Signals, Arbitration Signals,  
Error Reporting Signals, and Interrupt Signal.  
The SCSI Bus Interface Signals are subdivided into SCSI Bus Interface  
Signals, SCSI Signals, and SCSI Control Signals.  
Signals are assigned a type. There are five signal types:  
I
Input, a standard input only signal.  
O
Output, a standard output driver (typically a Totem Pole Output).  
Input and output (bidirectional).  
I/O  
T/S  
3-state, a bidirectional, 3-state input/output signal.  
S/T/S Sustained 3-state, an active LOW 3-state signal owned and driven by  
one and only one agent at a time.  
3.2.1 Internal Pull-ups on LSI53C875A Signals  
Several signals in the LSI53C875A have internal pull-up resistors.  
Table 3.1 describes the conditions that enable these pull-ups.  
Table 3.1  
LSI53C875A Internal Pull-ups  
Signal Name  
Pull-up Current Conditions for Pull-up  
IRQ/  
25 µA  
Pull-up enabled when the IRQ mode bit (bit 3 of DCNTL  
(0x3B)) is cleared.  
GPIO[1:0]  
25 µA  
Pull-up enabled when bits [1:0] of General Purpose Pin  
Control Zero (GPCNTL0) are not set.  
TEST_HSC/  
25 µA  
25 µA  
25 µA  
Pull-up enabled all the time.  
Pull-up enabled all the time.  
Pull-up enabled all the time.  
TEST_RST/  
TRST, TCK, TMS, TDI  
Signal Descriptions  
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3.3 PCI Bus Interface Signals  
The PCI Bus Interface Signals section contains tables describing the  
signals for the following signal groups: System Signals, Address and  
Data Signals, Interface Control Signals, Arbitration Signals, Error  
Reporting Signals, and Interrupt Signal.  
3.3.1 System Signals  
Table 3.2 describes the System signals.  
System Signals  
Name PQFP BGA Type Strength Description  
Table 3.2  
CLK  
145  
A6  
I
N/A  
Clock provides timing for all transactions on the PCI bus  
and is an input to every PCI device. All other PCI signals  
are sampled on the rising edge of CLK, and other timing  
parameters are defined with respect to this edge. Clock  
can optionally serve as the SCSI core clock, but this may  
effect fast SCSI-2 (or faster) transfer rates.  
RST/  
144  
B6  
I
N/A  
Reset forces the PCI sequencer of each device to a  
known state. All T/S and S/T/S signals are forced to a high  
impedance state, and all internal logic is reset. The RST/  
input is synchronized internally to the rising edge of CLK.  
The CLK input must be active while RST/ is active to  
properly reset the device.  
3-4  
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3.3.2 Address and Data Signals  
Table 3.3 describes Address and Data signals.  
Address and Data Signals  
Table 3.3  
Name  
PQFP  
BGA  
Type Strength Description  
AD[31:0]  
150, 151,  
153, 154,  
156, 157,  
159, 160, 3, E5, C1, D3,  
5, 6, 7, 9, E4-E1, H5,  
11–13, 28– J1, J2, H6,  
30, 32, 34– K2, J4, L1,  
36, 38, 40,  
41, 43, 44,  
46, 47, 49,  
50  
B5, C5, A4,  
B4, A3, C4,  
D4, A2, C2,  
T/S  
8 mA  
PCI  
Physical Dword Address and Data are  
multiplexed on the same PCI pins. A bus  
transaction consists of an address phase  
followed by one or more data phases.  
During the first clock of a transaction,  
AD[31:0] contain a 32-bit physical byte  
address. If the command is a DAC,  
implying a 64-bit address, a second  
address phase is required. During the  
first phase, AD[31:0] will contain the  
lower 32 bits of the address followed by  
a second phase with AD[31:0] containing  
the upper 32 bits of the address. During  
subsequent clocks, AD[31:0] contain  
data. PCI supports both read and write  
bursts. AD[7:0] define the least  
L2, M1, N1,  
M3, L3, N3,  
L4, K5, N4  
significant byte, and AD[31:24] define the  
most significant byte.  
C_BE[3:0] 1, 15, 26,  
39  
A1, F3, H3,  
K4  
T/S  
8 mA  
PCI  
Bus Command and Byte Enables are  
multiplexed on the same PCI pins.  
During the address phase of a  
transaction, C_BE[3:0]/ define the bus  
command. During the data phase,  
C_BE[3:0]/ are used as byte enables.  
The byte enables determine which byte  
lanes carry meaningful data. C_BE[0]/  
applies to byte 0, and C_BE[3]/ to byte 3.  
PAR  
25  
H1  
T/S  
8 mA  
PCI  
Parity is the even parity bit that protects  
the AD[31:0] and C_BE[3:0]/ lines.  
During the address phase, both the  
address and command bits are covered.  
During data phase, both data and byte  
enables are covered.  
PCI Bus Interface Signals  
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3.3.3 Interface Control Signals  
Table 3.4 describes the Interface Control signals.  
Interface Control Signals  
PQFP BGA Type Strength Description  
Table 3.4  
Name  
FRAME/ 16  
F2  
S/T/S 8 mA PCI Cycle Frame is driven by the current master to indicate  
the beginning and duration of an access. FRAME/ is  
asserted to indicate that a bus transaction is beginning.  
While FRAME/ is deasserted, either the transaction is  
in the final data phase or the bus is idle.  
TRDY/  
19  
G3  
S/T/S 8 mA PCI Target Ready indicates the target agent’s (selected  
device’s) ability to complete the current data phase of  
the transaction. TRDY/ is used with IRDY/. A data  
phase is completed on any clock when used with  
IRDY/. A data phase is completed on any clock when  
both TRDY/ and IRDY/ are sampled asserted. During a  
read, TRDY/ indicates that valid data is present on  
AD[31:0]. During a write, it indicates that the target is  
prepared to accept data. Wait cycles are inserted until  
both IRDY/ and TRDY/ are asserted together.  
IRDY/  
17  
F1  
S/T/S 8 mA PCI Initiator Ready indicates the initiating agent’s (bus  
master’s) ability to complete the current data phase of  
the transaction. IRDY/ is used with TRDY/. A data  
phase is completed on any clock when both IRDY/ and  
TRDY/ are sampled asserted. During a write, IRDY/  
indicates that valid data is present on AD[31:0]. During  
a read, it indicates that the master is prepared to  
accept data. Wait cycles are inserted until both IRDY/  
and TRDY/ are asserted together.  
STOP/  
22  
G4  
G2  
S/T/S 8 mA PCI Stop indicates that the selected target is requesting  
the master to stop the current transaction.  
DEVSEL/ 20  
S/T/S 8 mA PCI Device Select indicates that the driving device has  
decoded its address as the target of the current  
access. As an input, it indicates to a master whether  
any device on the bus has been selected.  
IDSEL  
2
B1  
I
N/A  
Initialization Device Select is used as a chip select in  
place of the upper 24 address lines during  
configuration read and write transactions.  
3-6  
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3.3.4 Arbitration Signals  
Table 3.5 describes Arbitration signals.  
Arbitration Signals  
Name PQFP BGA Type Strength Description  
Table 3.5  
REQ/ 148  
E6  
O
8 mA PCI Request indicates to the system arbiter that this agent  
desires use of the PCI bus. This is a point-to-point signal.  
Every master has its own REQ/ signal.  
GNT/ 147  
D6  
I
Grant indicates to the agent that access to the PCI bus  
has been granted. This is a point-to-point signal. Every  
master has its own GNT/ signal.  
3.3.5 Error Reporting Signals  
Table 3.6 describes the Error Reporting signals.  
Error Reporting Signals  
Name PQFP BGA Type Strength Description  
Table 3.6  
PERR/ 24  
H2  
E7  
S/T/ 8 mA PCI Parity Error may be pulsed active by an agent that  
S
detects a data parity error. PERR/ can be used by any  
agent to signal data corruption. However, on detection of  
a PERR/ pulse, the central resource may generate a  
nonmaskable interrupt to the host CPU, which often  
implies the system is unable to continue operation once  
error processing is complete.  
SERR/ 143  
O
8 mA PCI System Error is an open drain output used to report  
address parity errors as well as critical errors other than  
parity.  
PCI Bus Interface Signals  
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3.3.6 Interrupt Signal  
Table 3.7 describes the Interrupt signal.  
Interrupt Signal  
Name PQFP BGA Type Strength Description  
Table 3.7  
IRQ/  
52  
M5  
O
8 mA PCI Interrupt Request. This signal, when asserted LOW,  
indicates that an interrupting condition has occurred and  
that service is required from the host CPU. The output  
drive of this pin is open drain.  
1. See Register 0x4D, SCSI Test One (STEST1) in Chapter 4 for additional information on this signal.  
3.4 SCSI Bus Interface Signals  
The SCSI Bus Interface signals section contains tables describing the  
signals for the following signal groups: SCSI Bus Interface Signals, SCSI  
Signals, and SCSI Control Signals.  
3.4.1 SCSI Bus Interface Signal  
Table 3.8 describes the SCSI Bus Interface signal.  
Table 3.8  
Name PQFP BGA Type Strength Description  
SCLK 56 M6 N/A  
SCSI Bus Interface Signal  
I
SCSI Clock is used to derive all SCSI-related timings. The  
speed of this clock is determined by the application’s  
requirements. In some applications, SCLK may be sourced  
internally from the PCI bus clock (CLK). If SCLK is  
internally sourced, then the SCLK pin should be tied low.  
3-8  
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3.4.2 SCSI Signals  
Table 3.9 describes the SCSI signals.  
SCSI Signals  
PQFP  
Table 3.9  
Name  
BGA  
Type  
Strength  
Description  
SD[15:0] 113, 115–17, 85–87, 89, D13, E10, C13, D11, J9,  
102, 103, 105–108, 110, L13, K11, J10, G10, G9,  
I/O 48 mA SCSI SCSI Data.  
111  
F13, F11–9, E12, E11  
SDP[1:0] 112, 101  
F8, G13  
I/O 48 mA SCSI SCSI Parity.  
3.4.3 SCSI Control Signals  
Table 3.10 describes the SCSI Control signals.  
Table 3.10 SCSI Control Signals  
Name PQFP BGA Type Strength Description  
SCD  
SIO  
92  
90  
J12  
K13  
H11  
J11  
H13  
H9  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
48 mA SCSI phase line, command/data  
48 mA SCSI phase line, input/output.  
SMSG 95  
SREQ 91  
SACK 97  
SBSY 98  
SATN 100  
48 mA SCSI phase line, message.  
48 mA Data handshake line from target device.  
48 mA Data handshake signal from the initiator device.  
48 mA SCSI bus arbitration signal, busy.  
G12  
48 mA SCSI Attention, the initiator is requesting a message out  
phase.  
SRST 96  
SSEL 94  
H12  
H10  
I/O  
I/O  
48 mA SCSI bus reset.  
48 mA SCSI bus arbitration signal, select device.  
SCSI Bus Interface Signals  
3-9  
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3.5 GPIO Signals  
Table 3.11 describes the SCSI GPIO signals.  
Table 3.11 GPIO Signals  
Name  
PQFP BGA Type Strength Description  
GPIO0_FETCH/  
53  
N5  
I/O  
8 mA  
SCSI General Purpose I/O pin. Optionally,  
when driven LOW, indicates that the next bus  
request will be for an opcode fetch. This pin is  
programmable at power-up through the MAD7  
pin to serve as the data signal for the serial  
EEPROM interface. This signal can also be  
programmed to be driven LOW when the  
LSI53C875A is active on the SCSI bus.  
GPIO1_MASTER/ 54  
K6  
I/O  
8 mA  
SCSI General Purpose I/O pin. Optionally,  
when driven LOW, indicates that the  
LSI53C875A is bus master. This pin is  
programmable at power-up through the MAD7  
pin to serve as the clock signal for the serial  
EEPROM interface.  
GPIO2  
GPIO3  
GPIO4  
68  
70  
71  
J8  
I/O  
I/O  
I/O  
8 mA  
8 mA  
8 mA  
SCSI General Purpose I/O pin. This pin  
powers up as an input.  
M9  
L9  
SCSI General Purpose I/O pin. This pin  
powers up as an input.  
SCSI General Purpose I/O pin. GPIO4  
powers up as an output. (This pin may be used  
as the enable line for VPP, the 12 V power  
supply to the external flash memory interface.)  
3-10  
Signal Descriptions  
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3.6 ROM Flash and Memory Interface Signals  
Table 3.12 describes the ROM Flash and Memory Interface signals.  
Table 3.12 ROM Flash and Memory Interface Signals  
Name  
PQFP BGA  
Type Strength Description  
MWE/  
139  
141  
C7  
A7  
O
O
4 mA  
4 mA  
Memory Write Enable. This pin is used as a write  
enable signal to an external flash memory.  
MCE/  
MOE/  
Memory Chip Enable. This pin is used as a chip  
enable signal to an external EEPROM or flash  
memory device.  
140  
77  
B7  
O
O
O
4 mA  
Memory Output Enable. This pin is used as an  
output enable signal to an external EEPROM or  
flash memory during read operations. It is also  
used to test the connectivity of the LSI53C875A  
signals in test mode.  
MAC/_  
TESTOUT  
L10  
A8  
16 mA Memory Access Control. This pin can be  
programmed to indicate local or system memory  
accessed (non-PCI applications). It is also used to  
test the connectivity of the LSI53C875A signals in  
test mode.  
MAS0/  
MAS1/  
137  
4 mA  
Memory Address Strobe 0. This pin is used to  
latch in the least significant address byte (bits [7:0])  
of an external EEPROM or flash memory. Since  
the LSI53C875A moves addresses eight bits at a  
time, this pin connects to the clock of an external  
bank of flip-flops which are used to assemble up to  
a 20-bit address for the external memory.  
136  
B8  
O
4 mA  
Memory Address Strobe 1. This pin is used to  
latch in the most significant address byte (bits  
[15:8]) of an external EEPROM or flash memory.  
Since the LSI53C875A moves addresses eight bits  
at a time, this pin connects to the clock of an  
external bank of flip-flops which assemble up to a  
20-bit address for the external memory.  
ROM Flash and Memory Interface Signals  
3-11  
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Table 3.12 ROM Flash and Memory Interface Signals (Cont.)  
Name PQFP BGA Type Strength Description  
I/O 4 mA  
MAD[7:0] 59–62, L7, M7,  
64–67 N7, K7,  
M8, N8,  
Memory Address/Data Bus. This bus is used in  
conjunction with the memory address strobe pins  
and external address latches to assemble up to a  
20-bit address for an external EEPROM or flash  
memory. This bus will put out the least significant  
byte first and finishes with the most significant bits.  
It is also used to write data to a flash memory or  
read data into the chip from external EEPROM/  
flash memory. These pins have static pull-downs.  
L8, K8  
3.7 Test Interface Signals  
Table 3.13 describes Test Interface signals.  
Table 3.13 Test Interface Signals  
Name  
PQFP BGA Type Strength Description  
TEST_HSC/ 126  
A11  
I
N/A  
Test Halt SCSI Clock. For LSI Logic test purposes  
only. Pulled HIGH internally. This signal can also  
cause a full chip reset.  
TCK  
TMS  
130  
57  
A10  
N6  
I
I
N/A  
N/A  
Test Clock. This pin provides the clock for the JTAG  
test logic.  
Test Mode Select. The signal received at TMS is  
decoded by the TAP controller to control JTAG test  
operations. This pin has a static pull-down.  
TDI  
142  
D7  
I
N/A  
Test Data In. Serial test instructions are received by  
the JTAG test logic at this pin. This pin has a static  
pull-down.  
TEST_RST/ 127  
C10  
J6  
I
O
I
N/A  
4 mA  
N/A  
Test Reset. For test purposes only. Pulled HIGH  
internally.  
TDO  
58  
Test Data Out. This pin is the serial output for test  
instructions and data from the JTAG test logic.  
TRST/  
131  
C9  
Test Reset. This pin provides a reset for JTAG Test  
Logic. Pulled HIGH internally.  
3-12  
Signal Descriptions  
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3.8 Power and Ground Signals  
Table 3.14 describes the Power and Ground signals.  
Table 3.14 Power and Ground Signals  
Name  
PQFP  
BGA  
Type Strength Description  
VSS_I/O  
4, 10, 14, 18, A9, B11, D12,  
23, 27, 31, 37, E13, F12,  
42, 48, 69, 79, G11, J13,  
G
P
N/A  
Ground for PCI bus  
drivers/receivers, SCSI bus  
drivers/receivers, local memory  
interface drivers, and other I/O  
pins.  
88, 93, 99,  
104, 109, 114,  
123, 133, 152,  
158  
K10, K12, N9  
VDD_I/O  
8, 21, 33, 45, B10, C12, D2,  
63, 74, 84, D5, E8, G1,  
118, 128, 138, J5, J7, K1,  
N/A  
Power for PCI bus  
drivers/receivers, SCSI bus  
drivers/receivers, local memory  
interface drivers/receivers, and  
other I/O pins.  
155  
L11, M10  
VDD_CORE 51, 83, 149  
VSS_CORE 55, 80, 146  
A5, L5, L12  
C6, L6, N12  
D9  
P
G
P
N/A  
N/A  
N/A  
Power for core logic.  
Ground for core logic.  
VDDA  
VSSA  
NC  
129  
Power for analog cells (clock  
quadrupler and diffsense logic).  
132  
B9  
G
N/A  
N/A  
Ground for analog cells (clock  
quadrupler and diffsense logic).  
72, 73, 75, 76, A12, A13, B2,  
78, 81, 82, B3, B12, B13,  
N/A  
These pins have NO internal  
connection.  
119–122, 124, C3, C8, C11,  
125, 134, 135 D1, D8, D10,  
E9, F4-6, G5,  
H4, H8, J3,  
K3, K9, M2,  
M4, M11-13,  
N2, N10, N11,  
N13  
Note:  
The I/O driver pad rows and digital core have isolated power supplies as indicated by the “I/O”  
and “CORE” extensions on their respective VSS and VDD names. These power and ground pins  
should be connected directly to the primary power and ground planes of the circuit board. Bypass  
capacitors of 0.01 µF should be applied between adjacent VSS and VDD pairs wherever possible.  
Do not connect bypass capacitors between VSS and VDD pairs that cross power and ground bus  
boundaries.  
Power and Ground Signals  
3-13  
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3.9 MAD Bus Programming  
The MAD[7:0] pins, in addition to serving as the address/data bus for the  
local memory interface, also are used to program power-up options for  
the chip. A particular option is programmed allowing the internal  
pull-down current sink to pull the pin LOW at reset or by connecting a  
4.7 kresistor between the appropriate MAD[x] pin and VSS. The  
pull-down resistors require that HC or HCT external components are  
used for the memory interface. The MAD[7:0] pins are sensed by internal  
MAD[7] Serial EEPROM programmable option. When allowed to be  
pulled LOW by the internal pull-down current sink, the automatic data  
download is enabled. When pulled HIGH by an external resistor, the  
automatic data download is disabled. Please see Section 2.4, “Serial  
EEPROM Interface,” in Chapter 2 and Subsystem ID and Subsystem  
Vendor ID registers in Chapter 4 for additional information.  
MAD[6:4] Reserved and may be left floating.  
The MAD[3:1] pins are used to set the size of the external expansion  
ROM device attached. Encoding for these pins are listed in  
Table 3.15 (“0” indicates a pull-down resistor is attached, “1”  
indicates a pull-up resistor is attached).  
Table 3.15 Decode of MAD Pins  
MAD[3:1]  
Available Memory Space  
000  
001  
010  
011  
100  
101  
110  
111  
16 Kbyte  
32 Kbyte  
64 Kbyte  
128 Kbyte  
256 Kbyte  
512 Kbyte  
1024 Kbyte  
no external memory present  
3-14  
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The MAD[0] pin is the slow ROM pin. When pulled up, it enables two  
extra cycles of data access time to allow use of slower memory  
devices.  
All MAD pins have internal pull-down resistors.  
MAD Bus Programming  
3-15  
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3-16  
Signal Descriptions  
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Chapter 4  
Registers  
This chapter describes all LSI53C875A registers and is divided into the  
following sections:  
Section 4.1 “PCI Configuration Registers”  
Section 4.2 “SCSI Registers”  
Section 4.3 “64-Bit SCRIPTS Selectors”  
Section 4.4 “Phase Mismatch Jump Registers”  
In the register descriptions, the term “set” is used to refer to bits that are  
programmed to a binary one. Similarly, the term “cleared” is used to refer  
to bits that are programmed to a binary zero. Write any bits marked as  
reserved to zero; mask all information read from them. Reserved bit  
functions may change at any time. Unless otherwise indicated, all bits in  
registers are active HIGH, that is, the feature is enabled by setting the  
bit. The bottom row of every register diagram shows the default register  
values, which are enabled after the chip is powered on or reset.  
Reserved registers and bits are shaded in the register tables.  
4.1 PCI Configuration Registers  
The PCI Configuration registers are accessed by performing a  
configuration read/write to the device with its IDSEL pin asserted and the  
appropriate value in AD[10:8] during the address phase of the  
transaction. The LSI53C875A responds to a binary value of 000b.  
Table 4.1 describes the PCI configuration registers  
All PCI-compliant devices must support the Vendor ID, Device ID,  
Command, and Status registers. Support of other PCI-compliant  
registers is optional. In the LSI53C875A, registers that are not supported  
are not writable and return all zeros when read. Only those registers and  
LSI53C875A PCI to Ultra SCSI Controller  
4-1  
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bits that are currently supported by the LSI53C875A are described in this  
chapter. Reserved bits should not be accessed.  
Table 4.1  
PCI Configuration Register Map  
31  
0
Device ID  
Status  
Command  
0x00  
0x04  
0x08  
0x0C  
0x10  
0x14  
0x18  
0x20  
0x2C  
0x30  
0x34  
0x38  
0x3C  
0x40  
Class Code  
Header Type  
Revision ID (Rev ID)  
Not Supported  
Latency Timer  
Cache Line Size  
Base Address Register Zero (I/O)  
Base Address Register One (MEMORY) bits [31:0]  
Base Address Register Two (SCRIPTS RAM)  
Not Supported  
Not Supported  
Subsystem ID  
Subsystem Vendor ID  
Reserved  
Capabilities Pointer  
Reserved  
Max_Lat  
Min_Gnt  
Interrupt Pin  
Next Item Pointer  
Interrupt Line  
Capability ID  
Power Management Capabilities (PMC)  
Bridge Support Exten-  
Data  
Power Management Control/Status (PMCSR)  
0x44  
0x48  
sions (PMCSR_BSE)  
Not Supported  
Registers:0x00–0x01  
Vendor ID  
Read Only  
15  
0
VID  
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
VID  
Vendor ID  
[15:0]  
This 16-bit register identifies the manufacturer of the  
device. The Vendor ID is 0x1000.  
4-2  
Registers  
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Registers:0x02–0x03  
Device ID  
Read Only  
15  
0
DID  
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
DID  
Device ID  
[15:0]  
This 16-bit register identifies the particular device. The  
LSI53C875A Device ID is 0x0013.  
Registers:0x04–0x05  
Command  
Read/Write  
15  
x
9
x
8
SE  
0
7
R
x
6
EPER  
0
5
R
x
4
WIE  
0
3
R
x
2
1
0
R
x
EBM EMS EIS  
x
x
x
x
0
0
0
The Command register provides coarse control over a device’s ability to  
generate and respond to PCI cycles. When a zero is written to this  
register, the LSI53C875A is logically disconnected from the PCI bus for  
all accesses except configuration accesses.  
R
Reserved  
[15:9]  
8
SE  
SERR/ Enable  
This bit enables the SERR/ driver. SERR/ is disabled  
when this bit is cleared. The default value of this bit is  
zero. This bit and bit 6 must be set to report address  
parity errors.  
R
Reserved  
7
6
EPER  
Enable Parity Error Response  
This bit allows the LSI53C875A to detect parity errors on  
the PCI bus and report these errors to the system. Only  
data parity checking is enabled and disabled with this bit.  
The LSI53C875A always generates parity for the PCI  
bus.  
PCI Configuration Registers  
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R
Reserved  
5
4
WIE  
Write and Invalidate Enable  
This bit allows the LSI53C875A to generate write and  
invalidate commands on the PCI bus. The WIE bit in the  
DMA Control (DCNTL) register must also be set for the  
device to generate Write and Invalidate commands.  
R
Reserved  
3
EBM  
Enable Bus Mastering  
2
This bit controls the ability of the LSI53C875A to act as  
a master on the PCI bus. A value of zero disables this  
device from generating PCI bus master accesses. A  
value of one allows the LSI53C875A to behave as a bus  
master. The device must be a bus master in order to fetch  
SCRIPTS instructions and transfer data.  
EMS  
This bit controls the ability of the LSI53C875A to respond  
to Memory space accesses. A value of zero disables the  
device response. A value of one allows the LSI53C875A  
to respond to Memory Space accesses at the address  
range specified by Base Address Register One (MEM-  
ORY) and Base Address Register Two (SCRIPTS RAM)  
registers in the PCI configuration space.  
EIS  
Enable I/O Space  
0
This bit controls the LSI53C875A response to I/O space  
accesses. A value of zero disables the device response.  
A value of one allows the LSI53C875A to respond to I/O  
Space accesses at the address range specified by the  
Base Address Register Zero (I/O) register in the PCI  
configuration space.  
4-4  
Registers  
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Registers:0x06–0x07  
Status  
Read/Write  
15 14 13 12 11 10  
9
8
7
x
5
x
4
NC  
1
3
x
0
x
DPE SSE RMA RTA  
R
x
DT[1:0] DPR  
R
x
R
0
0
0
0
0
1
0
x
x
Reads to this register behave normally. Writes are slightly different in that  
bits can be cleared, but not set. A bit is cleared whenever the register is  
written, and the data in the corresponding bit location is a one. For  
instance, to clear bit 15 and not affect any other bits, write the value  
0x8000 to the register.  
DPE  
Detected Parity Error (from Slave)  
15  
This bit is set by the LSI53C875A whenever it detects a  
data parity error, even if data parity error handling is  
disabled.  
SSE  
Signaled System Error  
14  
This bit is set whenever the device asserts the SERR/  
signal.  
RMA  
Received Master Abort (from Master)  
A master device should set this bit whenever its  
transaction (except for Special Cycle) is terminated with  
Master Abort.  
13  
RTA  
Received Target Abort (from Master)  
A master device should set this bit whenever its  
transaction is terminated by target abort.  
12  
R
Reserved  
11  
DT[1:0]  
DEVSEL/ Timing  
[10:9]  
These bits encode the timing of DEVSEL/. These are  
encoded as:  
0b00  
0b01  
0b10  
0b11  
fast  
medium  
slow  
reserved  
PCI Configuration Registers  
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These bits are read only and should indicate the slowest  
time that a device asserts DEVSEL/ for any bus  
command except Configuration Read and Configuration  
Write. The LSI53C875A supports a value of 0b01.  
DPR  
Data Parity Error Reported  
8
This bit is set when all of the following conditions are met:  
The bus agent asserted PERR/ itself or observed  
PERR/ asserted.  
The agent setting this bit acted as the bus master for  
the operation in which the error occurred.  
The Parity Error Response bit in the Command  
register is set.  
R
Reserved  
[7:5]  
4
NC  
New Capabilities  
This bit is set to indicate a list of extended capabilities  
such as PCI Power Management. This bit is read only.  
R
Reserved  
[3:0]  
Register: 0x08  
Revision ID (Rev ID)  
Read Only  
7
0
RID  
x
x
x
x
x
x
x
x
RID  
Revision ID  
[7:0]  
This register contains the current revision level of the  
device.  
4-6  
Registers  
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Registers:0x09–0x0B  
Class Code  
Read Only  
23  
0
0
0
CC  
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CC  
Class Code  
[23:0]  
This 24-bit register is used to identify the generic function  
of the device. The upper byte of this register is a base  
class code, the middle byte is a subclass code, and the  
lower byte identifies a specific register level programming  
interface. The value of this register is 0x010000, which  
identifies a SCSI controller.  
Register: 0x0C  
Cache Line Size  
Read/Write  
7
0
CLS  
0
0
0
0
0
0
0
0
CLS  
Cache Line Size  
[7:0]  
This register specifies the system cache line size in units  
of 32-bit words. The value in this register is used by the  
device to determine whether to use Write and Invalidate  
or Write commands for performing write cycles, and  
whether to use Read, Read Line, or Read Multiple  
commands for performing read cycles as a bus master.  
Devices participating in the caching protocol use this field  
to know when to retry burst accesses at cache line  
boundaries. These devices can ignore the PCI cache  
support lines (SDONE and SB0/) when this register is  
cleared to 0. If this register is programmed to a number  
which is not a power of 2, the device will not use PCI  
performance commands to perform data transfers.  
PCI Configuration Registers  
4-7  
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Register: 0x0D  
Latency Timer  
Read/Write  
7
0
0
LT  
0
0
0
0
0
0
0
LT  
Latency Timer  
[7:0]  
The Latency Timer register specifies, in units of PCI bus  
clocks, the value of the Latency Timer for this PCI bus  
master. The LSI53C875A supports this timer. All eight  
bits are writable, allowing latency values of 0–255 PCI  
clocks. Use the following equation to calculate an  
optimum latency value for the LSI53C875A.  
Latency = 2 + (Burst Size x (typical wait states + 1))  
Values greater than optimum are also acceptable.  
Register: 0x0E  
Header Type  
Read Only  
7
0
HT  
0
0
0
0
0
0
0
0
HT  
Header Type  
[7:0]  
This register identifies the layout of bytes 0x10 through  
0x3F in configuration space and also whether or not the  
device contains multiple functions. Since the LSI53C875A  
is not a multifunction controller the value of this register  
is 0x00.  
Register: 0x0F  
Not Supported  
4-8  
Registers  
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Registers:0x10–0x13  
Base Address Register Zero (I/O)  
Read/Write  
31  
0
0
1
BAR0  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BAR0  
Base Address Register Zero - I/O  
[31:0]  
This base address register is used to map the operating  
register set into I/O space. The LSI53C875A requires  
256 bytes of I/O space for this base address register. It  
has bit zero hardwired to one. Bit 1 is reserved and  
returns a zero on all reads, and the other bits are used  
to map the device into I/O space. For detailed information  
on the operation of this register, refer to the PCI 2.2  
specification.  
Registers:0x14–0x17  
Base Address Register One (MEMORY)  
Read/Write  
31  
0
0
0
BAR1  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BAR1  
Base Address Register One  
This base address register maps SCSI operating  
registers into memory space. This device requires  
[31:0]  
1024 bytes of address space for this base register. This  
register has bits [9:0] hardwired to 0b0000000000. The  
default value of this register is 0x00000000. For detailed  
information on the operation of this register, refer to the  
PCI 2.2 specification.  
PCI Configuration Registers  
4-9  
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Registers:0x18–0x1B  
Base Address Register Two (SCRIPTS RAM)  
Read/Write  
31  
0
0
0
BAR2  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BAR2  
Base Address Register Two  
[31:0]  
This base register is used to map the SCRIPTS RAM into  
memory space. The default value of this register is  
0x00000000. The LSI53C875A points to 4096 bytes of  
address space with this register. This register has bits  
[11:0] hardwired to 0b000000000000. For detailed  
information on the operation of this register, refer to the  
PCI 2.2 specification.  
Registers:0x1C–0x27  
Not Supported  
Registers:0x28–0x2B  
Reserved  
Registers:0x2C–0x2D  
Subsystem Vendor ID  
Read Only  
15  
0
0
SVID  
If MAD[7] HIGH Default  
0
0
0
1
0
0
0
0
0
x
0
x
0
x
0
x
0
x
0
x
0
x
If MAD[7] LOW See Description Default  
x
x
x
x
x
x
x
x
x
SVID  
Subsystem Vendor ID  
[15:0]  
This 16-bit register is used to uniquely identify the vendor  
manufacturing the add-in board or subsystem where this  
PCI device resides. It provides a mechanism for an  
add-in card vendor to distinguish its cards from another  
vendor’s cards, even if the cards have the same PCI  
4-10  
Registers  
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controller installed on them (and therefore the same  
Vendor ID and Device ID).  
If the external serial EEPROM interface is enabled  
(MAD[7] LOW), this register is automatically loaded at  
power-up from the external serial EEPROM and will  
contain the value downloaded from the serial EEPROM  
or a value of 0x0000 if the download fails.  
(MAD[7] HIGH), this register returns a value of 0x1000  
(LSI Logic Vendor ID). The 16-bit value that should be  
stored in the external serial EEPROM for this register is  
the vendor’s PCI Vendor ID and must be obtained from  
the PCI Special Interest Group (SIG). Please see Section  
2.4, “Serial EEPROM Interface,” in Chapter 2 for more  
information on downloading a value for this register.  
Registers:0x2E–0x2F  
Subsystem ID  
Read Only  
15  
0
0
SID  
If MAD[7] HIGH Default  
0
0
0
1
0
0
0
0
x
0
x
0
x
0
x
0
x
0
x
0
x
0
x
If MAD[7] LOW See Description Default  
x
x
x
x
x
x
x
x
SID  
Subsystem ID  
[15:0]  
This 16-bit register is used to uniquely identify the add-in  
board or subsystem where this PCI device resides. It  
provides a mechanism for an add-in card vendor to  
distinguish its cards from one another even if the cards  
have the same PCI controller installed on them (and  
therefore the same Vendor ID and Device ID).  
If the external serial EEPROM interface is enabled  
(MAD[7] is LOW), this register is automatically loaded at  
power-up from the external serial EEPROM and will  
contain the value downloaded from the serial EEPROM  
or a value of 0x0000 if the download fails.  
If the external serial EEPROM is disabled (MAD[7] pulled  
HIGH), the register returns a value of 0x1000. The 16-bit  
PCI Configuration Registers  
4-11  
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value that should be stored in the external serial  
EEPROM is vendor specific. Please see the Section 2.4  
“Serial EEPROM Interface” in Chapter 2 for additional  
information on downloading a value for this register.  
Registers:0x30–0x33  
Expansion ROM Base Address  
Read/Write  
31  
0
0
0
ERBA[31:0]  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ERBA  
Expansion ROM Base Address  
[31:0]  
This four-byte register handles the base address and size  
information for the expansion ROM. It functions exactly  
like the Base Address Register Zero (I/O) and One  
(Memory) registers, except that the encoding of the bits  
is different. The upper 21 bits correspond to the upper  
21 bits of the expansion ROM base address.  
The expansion ROM Enable bit, bit 0, is the only bit  
defined in this register. This bit is used to control whether  
or not the device accepts accesses to its expansion  
ROM. When the bit is set, address decoding is enabled,  
and a device is used with or without an expansion ROM  
depending on the system configuration. To access the  
external memory interface, also set the Memory Space  
bit in the Command register.  
The host system detects the size of the external memory  
by first writing the Expansion ROM Base Address register  
with all ones and then reading back the register. The  
LSI53C875A responds with zeros in all don’t care  
locations. The ones in the remaining bits represent the  
binary version of the external memory size. For example,  
to indicate an external memory size of 32 Kbytes, this  
register, when written with ones and read back, returns  
ones in the upper 17 bits.  
The size of the external memory is set through MAD[3:1].  
Please see the section on MAD Bus Programming for the  
possible size encodings available.  
4-12  
Registers  
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Register: 0x34  
Capabilities Pointer  
Read Only  
7
0
0
CP  
0
1
0
0
0
0
0
CP  
Capabilities Pointer  
[7:0]  
This register indicates that the first extended capability  
register is located at offset 0x40 in the PCI Configuration.  
Registers:0x35–0x3B  
Reserved  
Register: 0x3C  
Interrupt Line  
Read/Write  
7
0
IL  
0
0
0
0
0
0
0
0
IL  
Interrupt Line  
[7:0]  
This register is used to communicate interrupt line routing  
information. POST software writes the routing information  
into this register as it configures the system. The value in  
this register tells which input of the system interrupt  
controller(s) the device’s interrupt pin is connected to.  
Values in this register are specified by system  
architecture.  
PCI Configuration Registers  
4-13  
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Register: 0x3D  
Interrupt Pin  
Read Only  
7
0
IP  
0
0
0
0
0
0
0
1
IP  
Interrupt Pin  
[7:0]  
This register indicates which interrupt pin the device  
uses. Its value is set to 0x01 for the INTA/ signal.  
Register: 0x3E  
Min_Gnt  
Read Only  
7
0
MG  
0
0
0
1
0
0
0
1
MG  
MIN_GNT  
[7:0]  
This register is used to specify the desired settings for  
latency timer values. Min_Gnt is used to specify how long  
a burst period the device needs. The value specified in  
this register is in units of 0.25 microseconds. The  
LSI53C875A sets this register to 0x11.  
Register: 0x3F  
Max_Lat  
Read Only  
7
0
ML  
0
1
0
0
0
0
0
0
ML  
MAX_LAT  
[7:0]  
This register is used to specify the desired settings for  
latency timer values. Max_Lat is used to specify how  
often the device needs to gain access to the PCI bus.  
The value specified in this register is in units of  
0.25 microseconds. The LSI53C875A sets this register to  
0x40.  
4-14  
Registers  
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Register: 0x40  
Capability ID  
Read Only  
7
0
CID  
0
0
0
0
0
0
0
1
CID  
Cap_ID  
[7:0]  
This register indicates the type of data structure currently  
being used. It is set to 0x01, indicating the Power  
Management Data Structure.  
Register: 0x41  
Next Item Pointer  
Read Only  
7
0
0
NIP  
0
0
0
0
0
0
0
NIP  
Next_Item_Ptr  
[7:0]  
Bits [7:0] contain the offset location of the next item in the  
controller’s capabilities list. The LSI53C875A has these  
bits set to zero indicating no further extended capabilities  
registers exist.  
Registers:0x42–0x43  
Power Management Capabilities (PMC)  
Read Only  
15  
0
11  
0
10  
9
8
x
6
x
5
4
3
2
0
0
0
PMES  
0
D2S D1S  
R
x
DSI APS PMEC  
VER[2:0]  
1
0
0
1
1
0
0
0
PMES  
PME_Support  
[15:11]  
Bits [15:11] define the power management states in  
which the LSI53C875A will assert the PME pin. These  
bits are all set to zero because the LSI53C875A does not  
provide a PME signal.  
PCI Configuration Registers  
4-15  
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D2S  
D1S  
D2_Support  
10  
9
The LSI53C875A sets this bit to indicate support for  
power management state D2.  
D1_Support  
The LSI53C875A sets this bit to indicate support for  
power management state D1.  
R
Reserved  
[8:6]  
5
DSI  
Device Specific Initialization  
This bit is cleared to indicate that the LSI53C875A  
requires no special initialization before the generic class  
device driver is able to use it.  
APS  
Auxiliary Power Source  
4
Because the LSI53C875A does not provide a PME  
signal, this bit is cleared, indicating that no auxiliary  
power source is required to support the PME signal in the  
D3cold power management state.  
PMEC  
PME Clock  
3
Bit 3 is cleared because the LSI53C875A does not  
provide a PME pin.  
VER[2:0]  
Version  
[2:0]  
These three bits are set to 010 to indicate that the  
LSI53C875A complies with Revision 1.1 of the PCI Power  
Management Interface Specification.  
Registers:0x44–0x45  
Power Management Control/Status (PMCSR)  
Read/Write  
15 14 13 12  
PST DSCL  
9
0
8
PEN  
0
7
x
2
x
1
0
DSLT  
0
R
PWS[1:0]  
0
0
0
0
0
x
x
x
x
0
0
PST  
PME Status  
The LSI53C875A always returns a zero for this bit,  
15  
indicating that PME signal generation is not supported  
from D3cold.  
4-16  
Registers  
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DSCL  
DSLT  
PEN  
Data_Scale  
[14:13]  
The LSI53C875A does not support the data register.  
Therefore, these two bits are always cleared.  
Data_Select  
[12:9]  
The LSI53C875A does not support the data register.  
Therefore, these four bits are always cleared.  
PME_Enable  
8
The LSI53C875A always returns a zero for this bit to  
indicate that PME assertion is disabled.  
R
Reserved  
[7:2]  
[1:0]  
PWS[1:0]  
Power State  
Bits [1:0] are used to determine the current power state  
of the LSI53C875A. They are used to place the  
LSI53C875A in a new power state. Power states are  
defined as:  
0b00  
0b01  
0b10  
0b11  
D0  
D1  
D2  
D3hot  
See Section 2.5, “Power Management,” in Chapter 2 for  
descriptions of the Power Management States.  
Register: 0x46  
Bridge Support Extensions (PMCSR_BSE)  
Read Only  
7
0
0
BSE  
0
0
0
0
0
0
0
BSE  
Bridge Support Extensions  
[7:0]  
This register indicates PCI Bridge specific functionality.  
The LSI53C875A does not support extensions and  
always returns 0x00.  
PCI Configuration Registers  
4-17  
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Register: 0x47  
Data  
Read Only  
7
0
0
DATA  
0
0
0
0
0
0
0
DATA  
Data  
[7:0]  
This register provides an optional mechanism for the  
function to report state-dependent operating data. The  
LSI53C875A does not use this register and always  
returns 0x00.  
4.2 SCSI Registers  
registers is shown in Table 4.2.  
Note:  
The only registers that the host CPU can access while the  
LSI53C875A is executing SCRIPTS are the Interrupt Status  
Zero (ISTAT0), Interrupt Status One (ISTAT1) and  
Mailbox Zero (MBOX0), Mailbox One (MBOX1) registers;  
attempts to access other registers interfere with the  
operation of the chip. However, all operating registers are  
accessible with SCRIPTS. All read data is synchronized  
and stable when presented to the PCI bus.  
4-18  
Registers  
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Table 4.2  
SCSI Register Address Map  
31  
16 15  
0
SCNTL3  
SCNTL2  
SCNTL1  
SXFER  
SOCL  
SCNTL0  
SCID  
0x00  
0x04  
GPREG0  
SBCL  
SDID  
SSID  
SFBR  
0x08  
SSTAT2  
SSTAT1  
SSTAT0  
DSTAT  
0x0C  
0x10  
DSA  
MBOX1  
MBOX0  
ISTAT1  
ISTAT0  
0x14  
CTEST3  
CTEST2  
CTEST1  
CTEST0  
0x18  
TEMP  
0x1C  
0x20  
CTEST6  
DCMD  
CTEST5  
CTEST4  
DBC  
DFIFO  
0x24  
DNAD  
DSP  
0x28  
0x2C  
0x30  
DSPS  
SCRATCH A  
0x34  
DCNTL  
SBR  
DIEN  
DMODE  
0x38  
ADDER  
0x3C  
0x40  
SIST1  
SIST0  
SIEN1  
SWIDE  
STIME1  
STEST1  
SIEN0  
SLPAR  
STIME0  
STEST0  
GPCNTL0  
RESPID1  
STEST3  
Reserved  
CCNTL1  
Reserved  
MACNTL  
RESPID0  
STEST2  
STEST4  
CCNTL0  
Reserved  
0x44  
0x48  
0x4C  
0x50  
SIDL  
SODL  
SBDL  
0x54  
0x58  
SCRATCH B  
0x5C  
0x60–0x9F  
0xA0  
0xA4  
0xA8  
0xAC  
0xB0  
0xB4  
0xB8  
0xBC  
0xC0  
0xC4  
0xC8  
0xCC  
0xD0  
0xD4  
0xD8  
0xDC  
0xE0–0xFF  
SCRATCH C–SCRATCH R  
MMRS  
MMWS  
SFS  
DRS  
SBMS  
DBMS  
DNAD64  
Reserved  
PMJAD1  
PMJAD2  
RBC  
UA  
ESA  
IA  
Reserved  
SBC  
CSBC  
Reserved  
SCSI Registers  
4-19  
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Register: 0x00  
SCSI Control Zero (SCNTL0)  
Read/Write  
7
6
5
START  
0
4
WATN  
0
3
EPC  
0
2
R
x
1
AAP  
0
0
TRG  
0
ARB[1:0]  
1
1
ARB[1:0]  
Arbitration Mode Bits 1 and 0  
[7:6]  
ARB1  
ARB0  
Arbitration Mode  
0
0
1
1
0
1
0
1
Simple arbitration  
Reserved  
Reserved  
Full arbitration, selection/reselection  
Simple Arbitration  
1. The LSI53C875A waits for a bus free condition to  
occur.  
2. It asserts SBSY/ and its SCSI ID (contained in the  
SCSI Chip ID (SCID) register) onto the SCSI bus. If  
the LSI53C875A deasserts SBSY/, deasserts its ID  
and sets the Lost Arbitration bit (bit 3) in the SCSI  
Status Zero (SSTAT0) register.  
3. After an arbitration delay, the CPU should read the  
SCSI Bus Data Lines (SBDL) register to check if a  
higher priority SCSI ID is present. If no higher priority  
ID bit is set, and the Lost Arbitration bit is not set, the  
LSI53C875A wins arbitration.  
4. Once the LSI53C875A wins arbitration, SSEL/ must be  
asserted using the SCSI Output Control Latch (SOCL)  
for a bus clear plus a bus settle delay (1.2 µs) before  
a low level selection is performed.  
4-20  
Registers  
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Full Arbitration, Selection/Reselection  
1. The LSI53C875A waits for a bus free condition.  
2. It asserts SBSY/ and its SCSI ID (the highest priority  
ID stored in the SCSI Chip ID (SCID) register) onto the  
SCSI bus.  
3. If the SSEL/ signal is asserted by another SCSI device  
or if the LSI53C875A detects a higher priority ID, the  
LSI53C875A deasserts SBSY, deasserts its ID, and  
waits until the next bus free state to try arbitration  
again.  
4. The LSI53C875A repeats arbitration until it wins  
control of the SCSI bus. When it wins, the Won  
Arbitration bit is set in the SCSI Status Zero (SSTAT0)  
5. The LSI53C875A performs selection by asserting the  
following onto the SCSI bus: SSEL/, the target’s ID  
(stored in the SCSI Destination ID (SDID) register),  
and the LSI53C875A’s ID (stored in the SCSI Chip ID  
(SCID) register).  
6. After a selection is complete, the Function Complete  
bit is set in the SCSI Interrupt Status Zero (SIST0)  
register, bit 6.  
7. If a selection time-out occurs, the Selection Time-Out  
bit is set in the SCSI Interrupt Status One (SIST1)  
register, bit 2.  
START  
Start Sequence  
5
sequence indicated by the Arbitration Mode bits. The  
Start Sequence bit is accessed directly in  
low level mode; during SCSI SCRIPTS operations, this bit  
is controlled by the SCRIPTS processor. Do not start an  
arbitration sequence if the connected (CON) bit in the  
SCSI Control One (SCNTL1) register, bit 4, indicates that  
the LSI53C875A is already connected to the SCSI bus.  
This bit is automatically cleared when the arbitration  
sequence is complete. If a sequence is aborted, check  
bit 4 in the SCNTL1 register to verify that the  
LSI53C875A is not connected to the SCSI bus.  
SCSI Registers  
4-21  
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WATN  
Select with SATN/ on a Start Sequence  
4
When this bit is set and the LSI53C875A is in the initiator  
mode, the SATN/ signal is asserted during selection of a  
SCSI target device. This is to inform the target that the  
LSI53C875A has a message to send. If a selection  
time-out occurs while attempting to select a target device,  
SATN/ is deasserted at the same time SSEL/ is  
deasserted. When this bit is cleared, the SATN/ signal is  
not asserted during selection. When executing SCSI  
SCRIPTS, this bit is controlled by the SCRIPTS  
processor, but manual setting is possible in low level  
mode.  
EPC  
Enable Parity Checking  
3
When this bit is set, the SCSI data bus is checked for odd  
parity when data is received from the SCSI bus in either  
the initiator or target mode. If a parity error is detected,  
bit 0 of the SCSI Interrupt Status Zero (SIST0) register is  
set and an interrupt may be generated.  
If the LSI53C875A is operating in the initiator mode and  
a parity error is detected, assertion of SATN/ is optional,  
but the transfer continues until the target changes phase.  
When this bit is cleared, parity errors are not reported.  
R
Reserved  
2
AAP  
Assert SATN/ on Parity Error  
1
When this bit is set, the LSI53C875A automatically  
asserts the SATN/ signal upon detection of a parity error.  
SATN/ is only asserted in the initiator mode. The SATN/  
signal is asserted before deasserting SACK/ during the  
byte transfer with the parity error. Also set the Enable  
Parity Checking bit for the LSI53C875A to assert SATN/  
in this manner. A parity error is detected on data received  
from the SCSI bus.  
If the Assert SATN/ on Parity Error bit is cleared or the  
Enable Parity Checking bit is cleared, SATN/ is not  
automatically asserted on the SCSI bus when a parity  
error is received.  
TRG  
Target Mode  
0
This bit determines the default operating mode of the  
LSI53C875A. The user must manually set the target or  
initiator mode. This is done using the SCRIPTS language  
4-22  
Registers  
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(SET TARGET or CLEAR TARGET). When this bit is set, the  
chip is a target device by default. When this bit is cleared,  
the LSI53C875A is an initiator device by default.  
Caution:  
Writing this bit while not connected may cause the loss of  
a selection or reselection due to the changing of target or  
initiator modes.  
Register: 0x01  
SCSI Control One (SCNTL1)  
Read/Write  
7
EXC  
0
6
ADB  
0
5
DHP  
0
4
CON  
0
3
RST  
0
2
AESP  
0
1
IARB  
0
0
SST  
0
EXC  
Extra Clock Cycle of Data Setup  
7
When this bit is set, an extra clock period of data setup  
is added to each SCSI data transfer. The extra data setup  
time can provide additional system design margin, though  
it affects the SCSI transfer rates. Clearing this bit disables  
the extra clock cycle of data setup time. Setting this bit  
only affects SCSI send operations.  
ADB  
Assert SCSI Data Bus  
6
When this bit is set, the LSI53C875A drives the contents  
SCSI data bus. When the LSI53C875A is an initiator, the  
SCSI I/O signal must be inactive to assert the SODL  
contents onto the SCSI bus. When the LSI53C875A is a  
target, the SCSI I/O signal must be active to assert the  
SODL contents onto the SCSI bus. The contents of the  
SCSI Output Data Latch (SODL) register can be asserted  
at any time, even before the LSI53C875A is connected to  
the SCSI bus. Clear this bit when executing SCSI  
SCRIPTS. It is normally used only for diagnostic testing  
or operation in low level mode.  
DHP  
Disable Halt on Parity Error or ATN (Target Only)  
The DHP bit is only defined for target mode. When this  
bit is cleared, the LSI53C875A halts the SCSI data  
transfer when a parity error is detected or when the  
SATN/ signal is asserted. If SATN/ or a parity error is  
received in the middle of a data transfer, the LSI53C875A  
5
SCSI Registers  
4-23  
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may transfer up to three additional bytes before halting to  
synchronize between internal core cells. During  
synchronous operation, the LSI53C875A transfers data  
until there are no outstanding synchronous offsets. If the  
LSI53C875A is receiving data, any data residing in the  
DMA FIFO is sent to memory before halting.  
When this bit is set, the LSI53C875A does not halt the  
SCSI transfer when SATN/ or a parity error is received.  
CON  
Connected  
4
This bit is automatically set any time the LSI53C875A is  
connected to the SCSI bus as an initiator or as a target.  
It is set after the LSI53C875A successfully completes  
arbitration or when it has responded to a bus initiated  
selection or reselection. This bit is also set after the chip  
wins simple arbitration when operating in low level mode.  
When this bit is cleared, the LSI53C875A is not  
connected to the SCSI bus.  
The CPU can force a connected or disconnected  
condition by setting or clearing this bit. This feature is  
used primarily during loopback mode.  
RST  
Assert SCSI RST/ Signal  
3
Setting this bit asserts the SRST/ signal. The SRST/  
output remains asserted until this bit is cleared. The  
25=µs minimum assertion time defined in the SCSI  
specification must be timed out by the controlling  
microprocessor or a SCRIPTS loop.  
AESP  
Assert Even SCSI Parity (force bad parity)  
2
When this bit is set, the LSI53C875A asserts even parity.  
It forces a SCSI parity error on each byte sent to the  
SCSI bus from the chip. If parity checking is enabled,  
then the LSI53C875A checks data received for odd parity.  
This bit is used for diagnostic testing and is cleared for  
normal operation. It is useful to generate parity errors to  
test error handling functions.  
IARB  
Immediate Arbitration  
1
Setting this bit causes the SCSI core to immediately  
begin arbitration once a Bus Free phase is detected  
following an expected SCSI disconnect. This bit is useful  
for multithreaded applications. The ARB[1:0] bits in the  
4-24  
Registers  
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SCSI Control Zero (SCNTL0) register are set for full  
arbitration and selection before setting this bit.  
Arbitration is retried until won. At that point, the  
LSI53C875A holds SBSY and SSEL asserted, and waits  
for a select or reselect sequence. The Immediate  
Arbitration bit is cleared automatically when the selection  
or reselection sequence is completed, or times out.  
An unexpected disconnect condition clears IARB with it  
attempting arbitration. See the SCSI Disconnect  
Unexpected bit (SCSI Control Two (SCNTL2), bit 7) for  
more information on expected versus unexpected  
disconnects.  
It is possible to abort an immediate arbitration sequence.  
First, set the Abort bit in the Interrupt Status Zero  
(ISTAT0) register. Then one of two things eventually  
happens:  
The Won Arbitration bit (SCSI Status Zero (SSTAT0),  
bit 2) will be set. In this case, the Immediate  
Arbitration bit needs to be cleared. This completes the  
abort sequence and disconnects the chip from the  
SCSI bus. If it is not acceptable to go to Bus Free  
phase immediately following the arbitration phase, it is  
possible to perform a low level selection instead.  
The abort completes because the LSI53C875A loses  
arbitration. This is detected by the clearing of the  
Immediate Arbitration bit. Do not use the Lost  
Arbitration bit (SCSI Status Zero (SSTAT0), bit 3) to  
detect this condition. In this case take no further  
action.  
SST  
Start SCSI Transfer  
This bit is automatically set during SCRIPTS execution  
and should not be used. It causes the SCSI core to begin  
a SCSI transfer, including SREQ/ and SACK/  
handshaking. The determination of whether the transfer  
is a send or receive is made according to the value  
written to the I/O bit in SCSI Output Control Latch  
(SOCL). This bit is self-clearing. Do not set it for low level  
operation.  
SCSI Registers  
4-25  
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Caution:  
Writing to this register while not connected may cause the  
loss of a selection/reselection by clearing the Connected  
bit.  
Register: 0x02  
SCSI Control Two (SCNTL2)  
Read/Write  
7
SDU  
0
6
CHM  
0
5
4
3
WSS  
0
2
VUE0  
0
1
VUE1  
0
0
WSR  
0
SLPMD SLPHBEN  
0
0
SDU  
SCSI Disconnect Unexpected  
7
This bit is valid in the initiator mode only. When this bit is  
set, the SCSI core is not expecting the SCSI bus to enter  
the Bus Free phase. If it does, an unexpected disconnect  
error is generated (see the Unexpected Disconnect bit in  
the SCSI Interrupt Status Zero (SIST0) register, bit 2).  
During normal SCRIPTS mode operation, this bit is set  
automatically whenever the SCSI core is reselected, or  
successfully selects another SCSI device. The SDU bit  
should be cleared with a register write (move 0x00 to  
SCNTL2) before the SCSI core expects a disconnect to  
occur, normally prior to sending an Abort, Abort Tag, Bus  
Device Reset, Clear Queue or Release Recovery  
message, or before deasserting SACK/ after receiving a  
Disconnect command or Command Complete message.  
CHM  
Chained Mode  
6
This bit determines whether or not the SCSI core is  
programmed for chained SCSI mode. This bit is  
automatically set by the Chained Block Move (CHMOV)  
SCRIPTS instruction and is automatically cleared by the  
Chained mode is primarily used to transfer consecutive  
wide data blocks. Using chained mode facilitates partial  
receive transfers and allows correct partial send behavior.  
When this bit is set and a data transfer ends on an odd  
byte boundary, the LSI53C875A stores the last byte in  
the SCSI Wide Residue (SWIDE) register during a  
receive operation, or in the SCSI Output Data Latch  
(SODL) register during a send operation. This byte is  
4-26  
Registers  
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combined with the first byte from the subsequent transfer  
so that a wide transfer is completed.  
SLPMD  
SLPAR Mode  
5
If this bit is cleared, the SCSI Longitudinal Parity (SLPAR)  
register functions as a byte-wide longitudinal parity  
register. If this bit is set, the SLPAR functions as a  
word-wide longitudinal parity function. The high or low  
byte of the SLPAR word is accessible through the SLPAR  
register. Which byte is accessible is controlled by the  
SLPHBEN bit.  
SLPHBEN  
WSS  
SLPAR High Byte Enable  
4
If this bit is cleared, the low byte of the SLPAR word is  
accessible through the SCSI Longitudinal Parity (SLPAR)  
register. If this bit is set, the high byte of the SLPAR word  
is present in the SLPAR register.  
Wide SCSI Send  
3
When read, this bit returns the value of the Wide SCSI  
Send (WSS) flag. Asserting this bit clears the WSS flag.  
This clearing function is self-clearing.  
When the WSS flag is high following a wide SCSI send  
operation, the SCSI core is holding a byte of “chain” data  
in the SCSI Output Data Latch (SODL) register. This data  
becomes the first low-order byte sent when married with  
a high-order byte during a subsequent data send transfer.  
Performing a SCSI receive operation clears this bit. Also,  
performing any nonwide transfer clears this bit.  
VUE0  
VUE1  
Vendor Unique Enhancements, Bit 0  
2
This bit is a read only value indicating whether the group  
code field in the SCSI instruction is standard or vendor  
unique. If cleared, the bit indicates standard group codes;  
if set, the bit indicates vendor unique group codes. The  
value in this bit is reloaded at the beginning of all  
asynchronous target receives.  
Vendor Unique Enhancement, Bit 1  
1
This bit is used to disable the automatic byte count reload  
during Block Move instructions in the command phase. If  
this bit is cleared, the device reloads the Block Move byte  
count if the first byte received is one of the standard  
SCSI Registers  
4-27  
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group codes. If this bit is set, the device does not reload  
the Block Move byte count, regardless of the group code.  
WSR  
Wide SCSI Receive  
0
When read, this bit returns the value of the Wide SCSI  
Receive (WSR) flag. Setting this bit clears the WSR flag.  
This clearing function is self-clearing.  
The WSR flag indicates that the SCSI core received data  
from the SCSI bus, detected a possible partial transfer at  
the end of a chained or nonchained block move  
command, and temporarily stored the high-order byte in  
the SCSI Wide Residue (SWIDE) register rather than  
passing the byte out the DMA channel. The hardware  
uses the WSR status flag to determine what behavior  
must occur at the start of the next data receive transfer.  
When the flag is set, the stored data in SWIDE may be  
“residue” data, valid data for a subsequent data transfer,  
or overrun data. The byte is read as normal data by  
starting a data receive transfer.  
Performing a SCSI send operation clears this bit. Also,  
performing any nonwide transfer clears this bit.  
Register: 0x03  
SCSI Control Three (SCNTL3)  
Read/Write  
7
USE  
0
6
0
4
0
3
EWS  
0
2
0
0
0
SCF[2:0]  
0
CCF[2:0]  
0
USE  
Ultra SCSI Enable  
7
Setting this bit enables Ultra SCSI synchronous transfers.  
The default value of this bit is 0. This bit should remain  
cleared if the LSI53C875A is not operating in Ultra SCSI  
mode.  
When this bit is set, the signal filtering period for SREQ/  
and SACK/ automatically changes to 15 ns for Ultra  
SCSI, regardless of the value of the Extend REQ/ACK  
Filtering bit in the SCSI Test Two (STEST2) register.  
Note:  
Set this bit to achieve Ultra SCSI transfer rates in legacy  
systems that use an 80 MHz clock.  
4-28  
Registers  
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SCF[2:0]  
Synchronous Clock Conversion Factor  
[6:4]  
These bits select a factor by which the frequency of  
SCLK is divided before being presented to the  
synchronous SCSI control logic. Write these to the same  
value as the Clock Conversion Factor bits below unless  
fast SCSI operation is desired. See the SCSI Transfer  
(SXFER) register description for examples of how the  
SCF bits are used to calculate synchronous transfer  
periods. See the table under the description of bits [7:5]  
of the SXFER register for the valid combinations.  
EWS  
Enable Wide SCSI  
3
When this bit is clear, all information transfer phases are  
assumed to be eight bits, transmitted on SD[7:0]/ and  
SDP0/. When this bit is asserted, data transfers are done  
16 bits at a time, with the least significant byte on  
SD[7:0]/ and SDP0/ and the most significant byte on  
SD[15:8]/, SDP1/. Command, Status, and Message  
phases are not affected by this bit.  
CCF[2:0]  
Clock Conversion Factor  
[2:0]  
These bits select a factor by which the frequency of  
SCLK is divided before being presented to the SCSI core.  
The synchronous portion of the SCSI core can be run at  
a different clock rate for fast SCSI, using the  
Synchronous Clock Conversion Factor bits. The bit  
encoding is displayed in the table below. All other  
combinations are reserved.  
SCF2 SCF1 SCF0  
CCF2 CCF1 CCF0 Frequency  
Factor  
SCSI Clock  
(MHz)  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
SCLK/3  
SCLK/1  
SCLK/1.5  
SCLK/2  
SCLK/3  
SCLK/4  
SCLK/6  
SCLK/8  
50.01–75.0  
16.67–25.0  
25.01–37.5  
37.51–50.0  
50.01–75.0  
75.01–80.00  
120  
160  
Note:  
It is important that these bits are set to the proper values  
to guarantee that the LSI53C875A meets the SCSI timings  
as defined by the ANSI specification.  
SCSI Registers  
4-29  
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Register: 0x04  
SCSI Chip ID (SCID)  
Read/Write  
7
R
x
6
RRE  
0
5
SRE  
0
4
R
x
3
0
0
0
ENC  
0
0
R
7
6
RRE  
Enable Response to Reselection  
When this bit is set, the LSI53C875A is enabled to  
respond to bus-initiated reselection at the chip ID in the  
Response ID Zero (RESPID0) and Response ID One  
(RESPID1) registers. Note that the chip does not  
automatically reconfigure itself to the initiator mode as a  
result of being reselected.  
SRE  
Enable Response to Selection  
5
When this bit is set, the LSI53C875A is able to respond  
to bus-initiated selection at the chip ID in the RESPID0  
and RESPID1 registers. Note that the chip does not  
automatically reconfigure itself to target mode as a result  
of being selected.  
R
Reserved  
4
ENC  
[3:0]  
These bits are used to store the LSI53C875A encoded  
SCSI ID. This is the ID which the chip asserts when  
arbitrating for the SCSI bus. The IDs that the  
LSI53C875A responds to when selected or reselected  
are configured in the Response ID Zero (RESPID0) and  
Response ID One (RESPID1) registers. The priority of  
the 16 possible IDs, in descending order is:  
Highest  
Lowest  
7
6
5
4
3
2
1
0
15 14 13 12 11 10  
9
8
4-30  
Registers  
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Register: 0x05  
SCSI Transfer (SXFER)  
Read/Write  
7
5
4
0
0
0
TP[2:0]  
0
MO[4:0]  
0
0
0
0
0
Note:  
When using Table Indirect I/O commands, bits [7:0] of this  
register are loaded from the I/O data structure.  
TP[2:0]  
SCSI Synchronous Transfer Period  
[7:5]  
These bits determine the SCSI synchronous transfer  
period used by the LSI53C875A when sending  
synchronous SCSI data in either the initiator or target  
mode. These bits control the programmable dividers in  
the chip.  
TP2  
TP1  
TP0  
XFERP  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
4
5
6
7
8
9
10  
11  
The synchronous transfer period the LSI53C875A should  
use when transferring SCSI data is determined in the  
following example:  
The LSI53C875A is connected to a hard disk which can  
transfer data at 10 Mbytes/s synchronously. The  
LSI53C875A’s SCLK is running at 40 MHz. The  
synchronous transfer period (SCSI Transfer (SXFER)) is  
found as follows:  
SXFERP = Period/SSCP + ExtCC  
Period = 1 ÷ Frequency = 1 ÷ 10 Mbytes/s = 100 ns  
SSCP = 1 ÷=SSCF = 1 ÷ 40 MHz = 25 ns  
SCSI Registers  
4-31  
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(This SCSI synchronous core clock is determined in  
SCNTL3 bits [6:4], ExtCC = 1 if SCNTL1 bit 7 is asserted  
and the LSI53C875A is sending data. ExtCC = 0 if the  
LSI53C875A is receiving data.)  
SXFERP = 100 ÷ 25 = 4  
Where:  
SXFERP Synchronous transfer period.  
SSCF  
ExtCC  
SCSI synchronous core period.  
SCSI synchronous core frequency.  
Extra clock cycle of data setup.  
Table 4.3 shows examples of synchronous transfer periods and rates for  
SCSI-1.  
Table 4.3  
Examples of Synchronous Transfer Periods and Rates  
for SCSI-1  
SCSI CLK ÷  
SCNTL3  
Bits [6:4]  
XFERP  
(SXFER  
Bits [7:5])  
Synch.  
Transfer  
Period (ns)  
Synch.  
Transfer Rate  
(Mbytes/s)  
CLK (MHz)  
66.67  
66.67  
50  
3
3
4
5
4
5
4
4
4
4
4
4
180  
225  
160  
200  
200  
160  
180  
160  
200  
240  
5.55  
4.44  
6.25  
5
2
50  
2
40  
2
5
37.50  
33.33  
25  
1.5  
1.5  
1
6.25  
5.55  
6.25  
5
20  
1
16.67  
1
4.17  
4-32  
Registers  
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Table 4.4 shows example transfer periods and rates for fast SCSI-2 and  
Ultra SCSI.  
Table 4.4  
Example Transfer Periods and Rates for Fast SCSI-2  
and Ultra SCSI  
SCSI CLK ÷  
SCNTL3  
Bits [6:4]  
Synch.  
Transfer  
Period (ns)  
Synch. Transfer  
Rate  
CLK (MHz)  
XFERP  
(Mbytes/s)  
1601  
1601  
80  
2
4
1
1
1
1
1
1
1
1
1
4
4
4
4
5
4
4
4
4
4
4
50  
100  
50  
20  
10  
20  
50  
80  
12.5  
10.0  
10.0  
9.375  
8.33  
6.25  
5
50  
100  
100  
106.67  
120  
160  
200  
240  
40  
37.50  
33.33  
25  
20  
16.67  
4.17  
1. Only with 40 MHz clock.  
MO[4:0]  
Max SCSI Synchronous Offset  
[4:0]  
These bits describe the maximum SCSI synchronous  
offset used by the LSI53C875A when transferring  
synchronous SCSI data in either the initiator or target  
mode. Table 4.5 describes the possible combinations and  
their relationship to the synchronous data offset used by  
the LSI53C875A. These bits determine the  
LSI53C875A’s method of transfer for Data-In and  
Data-Out phases only; all other information transfers  
occur asynchronously.  
SCSI Registers  
4-33  
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Table 4.5  
MO4  
Maximum Synchronous Offset  
MO3  
MO2  
MO1  
MO0  
Synchronous Offset  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0-Asynchronous  
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
4-34  
Registers  
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Register: 0x06  
SCSI Destination ID (SDID)  
Read/Write  
7
4
x
3
0
0
0
R
ENC  
x
x
x
0
0
R
Reserved  
[7:4]  
[3:0]  
ENC  
Encoded Destination SCSI ID  
Writing these bits set the SCSI ID of the intended initiator  
or target during SCSI reselection or selection phases,  
respectively. When executing SCRIPTS, the SCRIPTS  
processor writes the destination SCSI ID to this register.  
The SCSI ID is defined by the user in a SCRIPTS Select  
or Reselect instruction. The value written is the  
binary-encoded ID. The priority of the 16 possible IDs, in  
descending order, is:  
Highest  
Lowest  
7
6
5
4
3
2
1
0
15 14 13 12 11 10  
9
8
Register: 0x07  
General Purpose (GPREG0)  
Read/Write  
7
x
5
x
4
0
0
x
R
x
GPIO  
x
x
x
Reads to this register will always yield the same values. A write to this  
register will cause the data written to be output to the appropriate GPIO  
pin if it is set to the output mode in the General Purpose Pin Control Zero  
(GPCNTL0) register.  
R
Reserved  
[7:5]  
[4:0]  
GPIO  
General Purpose I/O  
These bits are programmed through the General Purpose  
Pin Control Zero (GPCNTL0) register as inputs, outputs,  
or to perform special functions. As an output, these pins  
can be used to enable or disable external terminators. It  
SCSI Registers  
4-35  
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is also possible to program these signals as live inputs  
and sense them through a SCRIPTS register to register  
Move Instruction. GPIO4 may be used to enable or  
disable VPP, the 12 Volt power supply to the external flash  
memory. This bit powers up with the power to external  
memory disabled. GPIO[3:0] default as inputs and GPIO4  
defaults as an output pin. When configured as inputs, an  
internal pull-down is enabled for GPIO[4:2]. For  
GPIO[1:0], internal pull-ups are enabled.  
LSI Logic software uses the GPIO[1:0] signals to access  
serial EEPROM. GPIO1 is used as a clock, with the  
GPIO0 pin serving as data.  
LSI Logic software also reserves the use of GPIO[4:2]. If  
there is a need to use GPIO[4:2] please check with LSI  
Logic for additional information.  
Register: 0x08  
SCSI First Byte Received (SFBR)  
Read/Write  
7
0
SFBR  
0
0
0
0
0
0
0
0
SFBR  
SCSI First Byte Received  
This register contains the first byte received in any  
[7:0]  
asynchronous information transfer phase. For example,  
when a LSI53C875A is operating in the initiator mode,  
this register contains the first byte received in the  
Message-In, Status phase, and Data-In phases.  
When a Block Move instruction is executed for a  
particular phase, the first byte received is stored in this  
register, even if the present phase is the same as the last  
phase. The first byte received for a particular input phase  
is not valid until after a MOVE instruction is executed.  
This register is also the accumulator for register read-  
modify-writes with the SFBR as the destination. This  
allows bit testing after an operation.  
The SFBR is not writable using the CPU, and therefore  
not by a Memory Move. However, it can be loaded using  
SCRIPTS Read/Write operations. To load the SFBR with  
4-36  
Registers  
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a byte stored in system memory, the byte must first be  
moved to an intermediate LSI53C875A register (such as  
a SCRATCH register), and then to the SFBR.  
This register also contains the state of the lower eight bits  
of the SCSI data bus during the Selection phase if the  
COM bit in the DMA Control (DCNTL) register is clear.  
If the COM bit is cleared, do not access this register  
using SCRIPTS operations, as nondeterminate  
operations may occur. This includes SCRIPTS  
Read/Write operations and conditional transfer control  
instructions that initialize the SFBR register.  
Register: 0x09  
SCSI Output Control Latch (SOCL)  
Read/Write  
7
REQ  
0
6
ACK  
0
5
BSY  
0
4
SEL  
0
3
ATN  
0
2
MSG  
0
1
C_D  
0
0
I/O  
0
REQ  
Assert SCSI REQ/ Signal  
Assert SCSI ACK/ Signal  
Assert SCSI BSY/ Signal  
Assert SCSI SEL/ Signal  
Assert SCSI ATN/ Signal  
Assert SCSI MSG/ Signal  
Assert SCSI C_D/ Signal  
Assert SCSI I_O/ Signal  
7
6
5
4
3
2
1
0
ACK  
BSY  
SEL  
ATN  
MSG  
C_D  
I/O  
This register is used primarily for diagnostic testing or programmed I/O  
operation. It is controlled by the SCRIPTS processor when executing  
SCSI SCRIPTS. SOCL is used only when transferring data using  
programmed I/O. Some bits are set (1) or cleared (0) when executing  
SCSI SCRIPTS. Do not write to the register once the LSI53C875A starts  
executing normal SCSI SCRIPTS.  
SCSI Registers  
4-37  
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Register: 0x0A  
SCSI Selector ID (SSID)  
Read Only  
7
VAL  
0
6
4
x
3
0
0
0
R
x
ENID  
x
0
0
VAL  
SCSI Valid  
7
If VAL is asserted, then the two SCSI IDs are detected  
on the bus during a bus-initiated selection or reselection,  
and the encoded destination SCSI ID bits below are valid.  
If VAL is deasserted, only one ID is present and the  
contents of the encoded destination ID are meaningless.  
R
Reserved  
[6:4]  
[3:0]  
ENID  
Encoded Destination SCSI ID  
Reading the SSID register immediately after the  
LSI53C875A is selected or reselected returns the  
binary-encoded SCSI ID of the device that performed the  
operation. These bits are invalid for targets that are  
selected under the single initiator option of the SCSI-1  
specification. This condition is detected by examining the  
VAL bit above.  
Register: 0x0B  
SCSI Bus Control Lines (SBCL)  
Read Only  
7
REQ  
x
6
ACK  
x
5
BSY  
x
4
SEL  
x
3
ATN  
x
2
MSG  
x
1
C_D  
x
0
I_O  
x
This register returns the SCSI control line status. A bit is set when the  
corresponding SCSI control line is asserted. These bits are not latched;  
they are a true representation of what is on the SCSI bus at the time the  
register is read. The resulting read data is synchronized before being  
presented to the PCI bus to prevent parity errors from being passed to  
the system. This register is used for diagnostic testing or operation in low  
level mode.  
4-38  
Registers  
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REQ  
ACK  
BSY  
SEL  
ATN  
MSG  
C_D  
I_O  
SREQ/ Status  
SACK/ Status  
SBSY/ Status  
SSEL/ Status  
SATN/ Status  
SMSG/ Status  
SC_D/ Status  
SI_O/ Status  
7
6
5
4
3
2
1
0
Register: 0x0C  
DMA Status (DSTAT)  
Read Only  
7
DFE  
1
6
MDPE  
0
5
BF  
0
4
ABRT  
0
3
SSI  
0
2
SIR  
0
1
R
x
0
IID  
0
Reading this register clears any bits that are set at the time the register  
is read, but does not necessarily clear the register in case additional  
in the Interrupt Status Zero (ISTAT0) register is also cleared. It is possible  
to mask DMA interrupt conditions individually through the DMA Interrupt  
Enable (DIEN) register.  
When performing consecutive 8-bit reads of the DSTAT, SCSI Interrupt  
Status Zero (SIST0) and SCSI Interrupt Status One (SIST1) registers (in  
any order), insert a delay equivalent to 12 CLK periods between the  
reads to ensure that the interrupts clear properly. See Chapter 2,  
“Functional Description” for more information on interrupts.  
DFE  
DMA FIFO Empty  
7
This status bit is set when the DMA FIFO is empty. It is  
possible to use it to determine if any data resides in the  
FIFO when an error occurs and an interrupt is generated.  
This bit is a pure status bit and does not cause an  
interrupt.  
SCSI Registers  
4-39  
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MDPE  
Master Data Parity Error  
6
This bit is set when the LSI53C875A as a master detects  
a data parity error, or a target device signals a parity error  
during a data phase. This bit is completely disabled by  
the Master Parity Error Enable bit (bit 3 of Chip Test Four  
(CTEST4)).  
BF  
Bus Fault  
5
This bit is set when a PCI bus fault condition is detected.  
A PCI bus fault can only occur when the LSI53C875A is  
bus master, and is defined as a cycle that ends with a  
Bad Address or Target Abort Condition.  
ABRT  
Aborted  
4
This bit is set when an abort condition occurs. An abort  
condition occurs when a software abort command is  
issued by setting bit 7 of the Interrupt Status Zero  
(ISTAT0) register.  
SSI  
SIR  
Single Step Interrupt  
3
If the Single Step Mode bit in the DMA Control (DCNTL)  
register is set, this bit is set and an interrupt is generated  
after successful execution of each SCRIPTS instruction.  
SCRIPTS Interrupt Instruction Received  
This status bit is set whenever an Interrupt instruction is  
evaluated as true.  
2
R
Reserved  
1
IID  
Illegal Instruction Detected  
0
This status bit is set any time an illegal or reserved  
instruction opcode is detected, whether the LSI53C875A  
is operating in single step mode or automatically  
executing SCSI SCRIPTS.  
Any of the following conditions during instruction  
execution also set this bit:  
The LSI53C875A is executing a Wait Disconnect  
instruction and the SCSI REQ line is asserted without  
a disconnect occurring.  
A Block Move instruction is executed with 0x000000  
loaded into the DMA Byte Counter (DBC) register,  
indicating there are zero bytes to move.  
4-40  
Registers  
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During a Transfer Control instruction, the Compare  
Data (bit 18) and Compare Phase (bit 17) bits are set  
in the DMA Byte Counter (DBC) register while the  
LSI53C875A is in target mode.  
During a Transfer Control instruction, the Carry Test  
bit (bit 21) is set and either the Compare Data (bit 18)  
or Compare Phase (bit 17) bit is set.  
A Transfer Control instruction is executed with the  
reserved bit 22 set.  
A Transfer Control instruction is executed with the  
Wait for Valid phase bit (bit 16) set while the chip is in  
target mode.  
A Load/Store instruction is issued with the  
memory address mapped to the operating registers of  
A Load/Store instruction is issued when the  
register address is not aligned with the memory  
A Load/Store instruction is issued with bit 5 in the  
DMA Command (DCMD) register cleared or bits 3 or  
2 set.  
A Load/Store instruction when the count value in the  
DMA Byte Counter (DBC) register is not set at 1 to 4.  
A Load/Store instruction attempts to cross a Dword  
boundary.  
A Memory Move instruction is executed with one of  
the reserved bits in the DMA Command (DCMD)  
register set.  
A Memory Move instruction is executed with the  
source and destination addresses not aligned.  
A 64-bit Table Indirect Block Move instruction is  
executed with a selector index value greater than  
0x16.  
If the Select with ATN/ bit 24 is set for any I/O  
instruction other than a Select instruction.  
SCSI Registers  
4-41  
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Register: 0x0D  
SCSI Status Zero (SSTAT0)  
Read Only  
7
ILF  
0
6
ORF  
0
5
OLF  
0
4
AIP  
0
3
LOA  
0
2
WOA  
0
1
RST  
0
0
SDP0  
0
ILF  
SIDL Least Significant Byte Full  
7
This bit is set when the least significant byte in the SCSI  
Input Data Latch (SIDL) register contains data. Data is  
transferred from the SCSI bus to the SCSI Input Data  
Latch register before being sent to the DMA FIFO and  
then to the host bus. The SIDL register contains SCSI  
data received asynchronously. Synchronous data  
received does not flow through this register.  
ORF  
SODR Least Significant Byte Full  
6
This bit is set when the least significant byte in the SCSI  
Output Data Register (SODR, a hidden buffer register  
which is not accessible) contains data. The SODR is  
used by the SCSI logic as a second storage register  
when sending data synchronously. It is not readable or  
determine how many bytes reside in the chip when an  
error occurs.  
OLF  
SODL Least Significant Byte Full  
5
This bit is set when the least significant byte in the SCSI  
Output Data Latch (SODL) contains data. The SODL  
register is the interface between the DMA logic and the  
SCSI bus. In synchronous mode, data is transferred from  
the host bus to the SODL register, and then to the SCSI  
Output Data Register (SODR, a hidden buffer register  
which is not accessible) before being sent to the SCSI  
bus. In asynchronous mode, data is transferred from the  
host bus to the SODL register, and then to the SCSI bus.  
The SODR buffer register is not used for asynchronous  
transfers. It is possible to use this bit to determine how  
many bytes reside in the chip when an error occurs.  
4-42  
Registers  
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AIP  
Arbitration in Progress  
4
Arbitration in Progress (AIP = 1) indicates that the  
LSI53C875A has detected a Bus Free condition, asserted  
SBSY, and asserted its SCSI ID onto the SCSI bus.  
LOA  
Lost Arbitration  
3
When set, LOA indicates that the LSI53C875A has  
detected a bus free condition, arbitrated for the SCSI bus,  
and lost arbitration due to another SCSI device asserting  
the SSEL/ signal.  
WOA  
Won Arbitration  
2
When set, WOA indicates that the LSI53C875A has  
detected a Bus Free condition, arbitrated for the SCSI  
bus and won arbitration. The arbitration mode selected in  
the SCSI Control Zero (SCNTL0) register must be full  
arbitration and selection to set this bit.  
RST  
SCSI RST/ Signal  
1
This bit reports the current status of the SCSI RST/  
signal, and the SRST signal (bit 6) in the Interrupt Status  
Zero (ISTAT0) register. This bit is not latched and may  
change as it is read.  
SDP0  
SCSI SDP0/ Parity Signal  
0
This bit represents the active HIGH current status of the  
SCSI SDP0/ parity signal. This signal is not latched and  
may change as it is read.  
Register: 0x0E  
SCSI Status One (SSTAT1)  
Read Only  
7
4
0
3
SDP0L  
2
MSG  
1
C_D  
0
I_O  
FF[3:0]  
0
0
0
FF[3:0]  
FIFO Flags  
[7:4]  
These four bits, along with SCSI Status Two (SSTAT2)  
bit 4, define the number of bytes or words that currently  
reside in the LSI53C875A’s SCSI synchronous data FIFO  
as shown in Table 4.6. These bits are not latched and  
they will change as data moves through the FIFO. The  
SCSI FIFO can hold up to 31 bytes for narrow SCSI  
SCSI Registers  
4-43  
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synchronous data transfers, or up to 31 words for wide.  
Values over 31 will not occur.  
Table 4.6  
SCSI Synchronous Data FIFO Word Count  
Bytes or Words  
in the  
FF4  
(SSTAT2 bit 4)  
FF3  
FF2  
FF1  
FF0  
SCSI FIFO  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
4-44  
Registers  
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Table 4.6  
SCSI Synchronous Data FIFO Word Count (Cont.)  
Bytes or Words  
in the  
FF4  
(SSTAT2 bit 4)  
FF3  
FF2  
FF1  
FF0  
SCSI FIFO  
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
1
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
1
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
SDP0L  
Latched SCSI Parity  
This bit reflects the SCSI parity signal (SDP0/),  
3
corresponding to the data latched in the SCSI Input Data  
Latch (SIDL). It changes when a new byte is latched into  
the least significant byte of the SIDL register. This bit is  
active HIGH, in other words, it is set when the parity  
signal is active.  
MSG  
C_D  
I_O  
SCSI MSG/ Signal  
SCSI C_D/ Signal  
2
1
0
SCSI I_O/ Signal  
These three SCSI phase status bits (MSG, C_D, and  
I_O) are latched on the asserting edge of SREQ/ when  
operating in either the initiator or target mode. These bits  
are set when the corresponding signal is active. They are  
useful when operating in the low level mode.  
SCSI Registers  
4-45  
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Register: 0x0F  
SCSI Status Two (SSTAT2)  
Read Only  
7
ILF1  
0
6
ORF1  
0
5
OLF1  
0
4
FF4  
0
3
SPL1  
x
2
R
x
1
LDSC  
1
0
SDP1  
x
ILF1  
SIDL Most Significant Byte Full  
7
This bit is set when the most significant byte in the SCSI  
Input Data Latch (SIDL) contains data. Data is transferred  
from the SCSI bus to the SCSI Input Data Latch register  
before being sent to the DMA FIFO and then to the host  
bus. The SIDL register contains SCSI data received  
asynchronously. Synchronous data received does not  
flow through this register.  
ORF1  
SODR Most Significant Byte Full  
6
This bit is set when the most significant byte in the SCSI  
Output Data register (SODR, a hidden buffer register  
which is not accessible) contains data. The SODR  
register is used by the SCSI logic as a second storage  
accessible to the user. This bit is used to determine how  
many bytes reside in the chip when an error occurs.  
OLF1  
SODL Most Significant Byte Full  
5
This bit is set when the most significant byte in the SCSI  
Output Data Latch (SODL) contains data. The SODL  
register is the interface between the DMA logic and the  
SCSI bus. In synchronous mode, data is transferred from  
the host bus to the SODL register, and then to the SCSI  
Output Data register (SODR, a hidden buffer register  
which is not accessible) before being sent to the SCSI  
bus. In asynchronous mode, data is transferred from the  
host bus to the SODL register, and then to the SCSI bus.  
The SODR buffer register is not used for asynchronous  
many bytes reside in the chip when an error occurs.  
FF4  
FIFO Flags, Bit 4  
4
This is the most significant bit in the SCSI FIFO Flags  
field, when concatenated with bits [7:4] (FF[3:0]) in SCSI  
Status One (SSTAT1). For a complete description of this  
4-46  
Registers  
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field, see the definition for SCSI Status One (SSTAT1)  
bits [7:4].  
SPL1  
Latched SCSI Parity for SD[15:8]  
3
This active HIGH bit reflects the SCSI odd parity signal  
corresponding to the data latched into the most  
significant byte in the SCSI Input Data Latch (SIDL)  
register.  
R
Reserved  
2
1
LDSC  
Last Disconnect  
This bit is used in conjunction with the Connected (CON)  
bit in SCSI Control One (SCNTL1). It allows the user to  
detect the case in which a target device disconnects, and  
then some SCSI device selects or reselects the  
LSI53C875A. If the Connected bit is asserted and the  
LDSC bit is asserted, a disconnect is indicated. This bit  
is set when the Connected bit in SCNTL1 is off. This bit  
is cleared when a Block Move instruction is executed  
while the Connected bit in SCNTL1 is on.  
SDP1  
SCSI SDP1 Signal  
0
This bit represents the active HIGH current state of the  
SCSI SDP1 parity signal. It is unlatched and may change  
as it is read.  
Registers:0x10–0x13  
Data Structure Address (DSA)  
Read/Write  
31  
0
0
0
DSA  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DSA  
Data Structure Address  
[31:0]  
This 32-bit register contains the base address used for all  
table indirect calculations. The DSA register is usually  
loaded prior to starting an I/O, but it is possible for a  
SCRIPTS Memory Move to load the DSA during the I/O.  
During any Memory-to-Memory Move operation, the  
contents of this register are preserved. The power-up  
value of this register is indeterminate.  
SCSI Registers  
4-47  
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Register: 0x14  
Interrupt Status Zero (ISTAT0)  
Read/Write  
7
ABRT  
0
6
SRST  
0
5
SIGP  
0
4
SEM  
0
3
CON  
0
2
INTF  
0
1
SIP  
0
0
DIP  
0
This register is accessible by the host CPU while a LSI53C875A is  
executing SCRIPTS (without interfering in the operation of the function).  
It is used to poll for interrupts if hardware interrupts are disabled. Read  
this register after servicing an interrupt to check for stacked interrupts.  
ABRT  
Abort Operation  
7
Setting this bit aborts the current operation under  
execution by the LSI53C875A. If this bit is set and an  
interrupt is received, clear this bit before reading the DMA  
Status (DSTAT) register to prevent further aborted  
interrupts from being generated. The sequence to abort  
any operation is:  
1. Set this bit.  
3. Read the Interrupt Status Zero (ISTAT0) and  
Interrupt Status One (ISTAT1) registers.  
4. If the SCSI Interrupt Pending bit is set, then read the  
SCSI Interrupt Status Zero (SIST0) or SCSI Interrupt  
Status One (SIST1) register to determine the cause  
of the SCSI Interrupt and go back to Step 2.  
5. If the SCSI Interrupt Pending bit is clear, and the  
DMA Interrupt Pending bit is set, then write 0x00  
value to this register.  
6. Read the DMA Status (DSTAT) register to verify the  
aborted interrupt and to see if any other interrupting  
conditions have occurred.  
SRST  
Software Reset  
6
Setting this bit resets the LSI53C875A. All operating  
registers are cleared to their respective default values  
and all SCSI signals are deasserted. Setting this bit does  
not assert the SCSI RST/ signal. This reset does not  
4-48  
Registers  
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clear the ID Mode bit or any of the PCI configuration  
registers. This bit is not self-clearing; it must be cleared  
to clear the reset condition (a hardware reset also clears  
this bit).  
SIGP  
Signal Process  
5
SIGP is a R/W bit that is writable at any time, and polled  
and reset using Chip Test Two (CTEST2). The SIGP bit  
is used in various ways to pass a flag to or from a running  
SCRIPTS instruction.  
The only SCRIPTS instruction directly affected by the  
SIGP bit is Wait for Selection/Reselection. Setting this bit  
causes that instruction to jump to the alternate address  
immediately. The instructions at the alternate jump  
address should check the status of SIGP to determine  
the cause of the jump. The SIGP bit is usable at any time  
and is not restricted to the wait for selection/reselection  
condition.  
SEM  
Semaphore  
4
The SCRIPTS processor may set this bit using a  
SCRIPTS register write instruction. An external processor  
may also set it while the LSI53C875A is executing a  
SCRIPTS operation. This bit enables the LSI53C875A to  
notify an external processor of a predefined condition  
while SCRIPTS are running. The external processor may  
also notify the LSI53C875A of a predefined condition and  
the SCRIPTS processor may take action while SCRIPTS  
are executing.  
CON  
Connected  
3
This bit is automatically set any time the LSI53C875A is  
connected to the SCSI bus as an initiator or as a target.  
It is set after successfully completing selection or when  
the LSI53C875A responds to a bus-initiated selection or  
reselection. It is also set after the LSI53C875A wins  
arbitration when operating in low level mode. When this  
bit is clear, the LSI53C875A is not connected to the SCSI  
bus.  
INTF  
Interrupt-on-the-Fly  
2
This bit is asserted by an INTFLY instruction during  
SCRIPTS execution. SCRIPTS programs do not halt  
when the interrupt occurs. This bit can be used to notify  
a service routine, running on the main processor while  
SCSI Registers  
4-49  
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the SCRIPTS processor is still executing a SCRIPTS  
program. If this bit is set when the Interrupt Status Zero  
(ISTAT0) or Interrupt Status One (ISTAT1) registers are  
read they are not automatically cleared. To clear this bit,  
write it to a one. The reset operation is self-clearing.  
Note:  
If the INTF bit is set but SIP or DIP are not set, do not  
attempt to read the other chip status registers. An  
Interrupt-on-the-Fly interrupt must be cleared before  
servicing any other interrupts indicated by SIP or DIP.  
This bit must be written to one in order to clear it after it  
has been set.  
SIP  
SCSI Interrupt Pending  
1
This status bit is set when an interrupt condition is  
detected in the SCSI portion of the LSI53C875A. The  
following conditions cause a SCSI interrupt to occur:  
A phase mismatch (initiator mode) or SATN/ becomes  
active (target mode)  
An arbitration sequence completes  
A selection or reselection time-out occurs  
The LSI53C875A is selected  
The LSI53C875A is reselected  
A SCSI gross error occurs  
An unexpected disconnect occurs  
A SCSI reset occurs  
A parity error is detected  
The handshake-to-handshake timer is expired  
The general purpose timer is expired  
To determine exactly which condition(s) caused the  
interrupt, read the SCSI Interrupt Status Zero (SIST0)  
and SCSI Interrupt Status One (SIST1) registers.  
DIP  
DMA Interrupt Pending  
0
This status bit is set when an interrupt condition is  
detected in the DMA portion of the LSI53C875A. The  
following conditions cause a DMA interrupt:  
A PCI parity error is detected  
4-50  
Registers  
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A bus fault is detected  
An abort condition is detected  
A SCRIPTS instruction is executed in single step  
mode  
A SCRIPTS interrupt instruction is executed  
An illegal instruction is detected  
To determine exactly which condition(s) caused the  
interrupt, read the DMA Status (DSTAT) register.  
Register: 0x15  
Interrupt Status One (ISTAT1)  
Read/Write  
7
3
x
2
FLSH  
0
1
SRUN  
0
0
SI  
0
R
x
x
x
x
R
Reserved  
Flushing  
[7:3]  
FLSH  
2
Reading this bit monitors if the chip is currently flushing  
data. If set, the chip is flushing data from the DMA FIFO.  
If cleared, no flushing is occurring. This bit is read only  
and writes will have no effect on the value of this bit.  
SRUN  
SCRIPTS Running  
1
This bit indicates whether or not the SCRIPTS engine is  
currently fetching and executing SCRIPTS instructions. If  
this bit is set, the SCRIPTS engine is active.  
If it is cleared, the SCRIPTS engine is not active.  
This bit is read only and writes will have no effect on the  
SI  
SYNC_IRQD  
0
Setting this bit disables the IRQ/ pin. Clearing this bit  
enables normal operation of the IRQ/ pin. The function of  
this bit is nearly identical to bit 1 of the DMA Control  
(DCNTL) (0x3B) register except that if the IRQ/ is already  
asserted and this bit is set, IRQ/ will remain asserted until  
the interrupt is serviced. At this point the IRQ/ line will be  
blocked for future interrupts until this bit is cleared. In  
SCSI Registers  
4-51  
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addition, this bit may be read and written while SCRIPTS  
are executing.  
Register: 0x16  
Mailbox Zero (MBOX0)  
Read/Write  
7
0
MBOX0  
0
0
0
0
0
0
0
0
MBOX0  
Mailbox Zero  
[7:0]  
These are general purpose bits that may be read or  
written while SCRIPTS are running. They also may be  
read or written by the SCRIPTS processor.  
Note:  
The host and the SCRIPTS processor code could  
potentially attempt to access the same mailbox byte at the  
same time. Using one mailbox register as a read only and  
the other as a write only will prevent this type of conflict.  
Register: 0x17  
Mailbox One (MBOX1)  
Read/Write  
7
0
MBOX1  
0
0
0
0
0
0
0
0
MBOX1  
Mailbox One  
[7:0]  
These are general purpose bits that may be read or  
written while SCRIPTS are running. They also may be  
read or written by the SCRIPTS processor.  
Note:  
The host and the SCRIPTS processor code could  
potentially attempt to access the same mailbox byte at the  
same time. Using one mailbox register as a read only and  
the other as a write only will prevent this type of conflict.  
4-52  
Registers  
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Register: 0x18  
Chip Test Zero (CTEST0)  
Read/Write  
7
0
FMT  
1
1
1
1
1
1
1
1
FMT  
Byte Empty in DMA FIFO  
[7:0]  
These bits identify the bottom bytes in the DMA FIFO that  
are empty. Each bit corresponds to a byte lane in the  
DMA FIFO. For example, if byte lane three is empty, then  
FMT3 will be set. Since the FMT flags indicate the status  
of bytes at the bottom of the FIFO, if all FMT bits are set,  
the DMA FIFO is empty.  
Register: 0x19  
Chip Test One (CTEST1)  
Read Only  
7
0
0
FFL  
0
0
0
0
0
0
0
FFL  
Byte Full in DMA FIFO  
[7:0]  
These status bits identify the top bytes in the DMA FIFO  
that are full. Each bit corresponds to a byte lane in the  
DMA FIFO. For example, if byte lane three is full then  
FFL3 is set. Since the FFL flags indicate the status of  
bytes at the top of the FIFO, if all FFL bits are set, the  
DMA FIFO is full.  
SCSI Registers  
4-53  
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Register: 0x1A  
Chip Test Two (CTEST2)  
Read Only (bit 3 write)  
7
DDIR  
0
6
SIGP  
0
5
CIO  
x
4
CM  
x
3
PCICIE  
0
2
TEOP  
0
1
DREQ  
0
0
DACK  
1
DDIR  
Data Transfer Direction  
7
This status bit indicates which direction data is being  
transferred. When this bit is set, the data is transferred  
from the SCSI bus to the host bus. When this bit is clear,  
the data is transferred from the host bus to the SCSI bus.  
SIGP  
Signal Process  
6
This bit is a copy of the SIGP bit in the Interrupt Status  
Zero (ISTAT0) register (bit=5). The SIGP bit is used to  
signal a running SCRIPTS instruction. When this register  
is read, the SIGP bit in the Interrupt Status Zero (ISTAT0)  
register is cleared.  
CIO  
CM  
Configured as I/O  
5
This bit is defined as the Configuration I/O Enable Status  
bit. This read only bit indicates if the chip is currently  
enabled as I/O space.  
Configured as Memory  
4
This bit is defined as the configuration memory enable  
status bit. This read only bit indicates if the chip is  
currently enabled as memory space.  
Note:  
and memory space. Also, bits 4 and 5 may be set if the chip  
is dual-mapped.  
PCICIE  
PCI Configuration Into Enable  
3
This bit controls the shadowing of the PCI Base Address  
Register One (MEMORY), PCI Base Address Register  
Two (SCRIPTS RAM), PCI Device ID, and PCI Revision  
ID into the Scratch Register A (SCRATCHA), Scratch  
Register B (SCRATCHB), and SCRIPTS Fetch Selector  
(SFS) registers.  
When it is set, the SCRATCHA register contains bits  
[31:0] of the Memory Base Address value from the PCI  
4-54  
Registers  
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Base Address Register One (MEMORY). This is the  
memory mapped operating register base address. Bits  
[9:0] will be 0. The SCRATCHB register contains bits  
[31:13] of the RAM Base Address value from the PCI  
Base Address Register Two (SCRIPTS RAM). This is the  
contain the PCI Revision ID (Rev ID) register value and  
bits [15:0] contain the PCI Device ID register value. When  
this bit is set, writes to this register have no effect.  
When this bit is cleared, the Scratch Register A  
(SCRATCHA), Scratch Register B (SCRATCHB), and  
SCRIPTS Fetch Selector (SFS) registers return to normal  
operation.  
Note:  
Bit 3 is the only writable bit in this register. All other bits are  
read only. When modifying this register, all other bits must  
be written to zero. Do not execute a read-modify-write to  
this register.  
TEOP  
SCSI True End of Process  
2
This bit indicates the status of the LSI53C875A’s TEOP  
signal. The TEOP signal acknowledges the completion of  
a transfer through the SCSI portion of the LSI53C875A.  
When this bit is set, TEOP is active. When this bit is  
clear, TEOP is inactive.  
DREQ  
DACK  
Data Request Status  
1
This bit indicates the status of the LSI53C875A’s internal  
Data Request signal (DREQ). When this bit is set, DREQ  
is active. When this bit is clear, DREQ is inactive.  
Data Acknowledge Status  
0
This bit indicates the status of the LSI53C875A’s internal  
Data Acknowledge signal (DACK/). When this bit is set,  
DACK/ is inactive. When this bit is clear, DACK/ is active.  
SCSI Registers  
4-55  
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Register: 0x1B  
Chip Test Three (CTEST3)  
Read/Write  
7
4
x
3
FLF  
0
2
CLF  
0
1
FM  
0
0
WRIE  
0
V
x
x
x
V
Chip Revision Level  
[7:4]  
These bits identify the chip revision level for software  
purposes. It should have the same value as the lower  
0x08 in the configuration space.  
FLF  
Flush DMA FIFO  
3
When this bit is set, data residing in the DMA FIFO is  
transferred to memory, starting at the address in the DMA  
Next Address 64 (DNAD64) register. The internal  
DMAWR signal, controlled by the Chip Test Five  
(CTEST5) register, determines the direction of the  
transfer. This bit is not self-clearing; clear it once the data  
is successfully transferred by the LSI53C875A.  
Note:  
Note:  
Polling of FIFO flags is allowed during flush operations.  
CLF  
Clear DMA FIFO  
2
When this bit is set, all data pointers for the DMA FIFO  
are cleared. Any data in the FIFO is lost. After the  
LSI53C875A successfully clears the appropriate FIFO  
pointers and registers, this bit automatically clears.  
This bit does not clear the data visible at the bottom of the  
FIFO.  
FM  
Fetch Pin Mode  
1
When set, this bit causes the FETCH/ pin to deassert  
during indirect and table indirect read operations.  
FETCH/ is only active during the opcode portion of an  
instruction fetch. This allows the storage of SCRIPTS in  
a PROM while data tables are stored in RAM.  
If this bit is not set, FETCH/ is asserted for all bus cycles  
during instruction fetches.  
4-56  
Registers  
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WRIE  
Write and Invalidate Enable  
0
This bit, when set, causes the issuing of Write and  
Invalidate commands on the PCI bus whenever legal.  
The Write and Invalidate Enable bit in the PCI  
Configuration Command register must also be set in  
order for the chip to generate Write and Invalidate  
commands.  
Registers:0x1C–0x1F  
Temporary (TEMP)  
Read/Write  
31  
0
0
TEMP  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TEMP  
Temporary  
[31:0]  
This 32-bit register stores the Return instruction address  
pointer from the Call instruction. The address pointer  
stored in this register is loaded into the DMA SCRIPTS  
Pointer (DSP) register when a Return instruction is  
executed. This address points to the next instruction to  
execute. Do not write to this register while the  
LSI53C875A is executing SCRIPTS.  
During any Memory-to-Memory Move operation, the  
contents of this register are preserved. The power-up  
value of this register is indeterminate.  
Register: 0x20  
DMA FIFO (DFIFO)  
Read/Write  
7
0
BO  
0
0
0
0
0
0
0
0
BO  
Byte Offset Counter  
[7:0]  
These bits, along with bits [1:0] in the Chip Test Five  
(CTEST5) register, indicate the amount of data  
transferred between the SCSI core and the DMA core. It  
is used to determine the number of bytes in the DMA  
FIFO when an interrupt occurs. These bits are unstable  
SCSI Registers  
4-57  
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while data is being transferred between the two cores.  
Once the chip has stopped transferring data, these bits  
are stable.  
The DMA FIFO (DFIFO) register counts the number of  
bytes transferred between the DMA core and the SCSI  
core. The DMA Byte Counter (DBC) register counts the  
number of bytes transferred across the host bus. The  
difference between these two counters represents the  
number of bytes remaining in the DMA FIFO.  
The following steps determine how many bytes are left in  
the DMA FIFO when an error occurs, regardless of the  
If the DFS bit (bit 5, Chip Test Five (CTEST5)) is set:  
1. Subtract the ten least significant bits of the DMA  
Byte Counter (DBC) register from the 10-bit value of  
the DFBOC. The DFBOC consists of the Chip Test  
Five (CTEST5) register, bits 1 and 0 and the DMA  
FIFO (DFIFO) register, bits [7:0].  
2. AND the result with 0x3FF for a byte count between  
If the DFS bit (bit 5, Chip Test Five (CTEST5)) is cleared:  
1. Subtract the seven least significant bits of the DMA  
Byte Counter (DBC) register from the seven bit value  
of the DFBOC which is made up of the DMA FIFO  
(DFIFO) register, bits [6:0].  
2. AND the result with 0x7F for a byte count between  
zero and 112.  
Note:  
If trying to calculate the total number of bytes in both the  
DMA FIFO and SCSI Logic, see Section 2.2.12.1 “Data  
Paths” in Chapter 2, “Functional Description.”  
4-58  
Registers  
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Register: 0x21  
Chip Test Four (CTEST4)  
Read/Write  
7
BDIS  
0
6
FBL3  
0
5
ZSD  
0
4
SRTM  
0
3
MPEE  
0
2
0
0
0
FBL[2:0]  
0
BDIS  
Burst Disable  
7
6
When set, this bit causes the LSI53C875A to perform  
back-to-back cycles for all transfers. When this bit is  
cleared, back-to-back transfers for opcode fetches and  
burst transfers for data moves are performed.  
FBL3  
ZSD  
FIFO Byte Control  
This bit is used with FBL[2:0]. See Bits [2:0] description  
in this register.  
SCSI Data High Impedance  
5
Setting this bit causes the LSI53C875A to place the SCSI  
data bus SD[15:0] and the parity lines SDP[1:0] in a high  
impedance state. In order to transfer data on the SCSI  
SRTM  
Shadow Register Test Mode  
4
Setting this bit allows access to the shadow registers  
used by Memory-to-Memory Move operations. When this  
bit is set, register accesses to the Temporary (TEMP) and  
Data Structure Address (DSA) registers are directed to  
the shadow copies STEMP (Shadow TEMP) and SDSA  
(Shadow DSA). The registers are shadowed to prevent  
them from being overwritten during a Memory-to-Memory  
Move operation. The DSA and TEMP registers contain  
the base address used for table indirect calculations, and  
the address pointer for a call or return instruction,  
respectively. This bit is intended for manufacturing  
diagnostics only and should not be set during normal  
operations.  
MPEE  
Master Parity Error Enable  
3
Setting this bit enables parity checking during master  
data phases. A parity error during a bus master read is  
detected by the LSI53C875A. A parity error during a bus  
master write is detected by the target, and the  
SCSI Registers  
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LSI53C875A is informed of the error by the PERR/ pin  
being asserted by the target. When this bit is cleared, the  
LSI53C875A does not interrupt if a master parity error  
occurs. This bit is cleared at power-up.  
FBL[2:0]  
FIFO Byte Control  
[2:0]  
DMA FIFO  
Byte Lane  
FBL3  
FBL2  
FBL1  
FBL0  
0
1
1
1
1
1
1
1
1
x
0
0
0
0
1
1
1
1
x
0
0
1
1
0
0
1
1
x
0
1
0
1
0
1
0
1
Disabled  
0
1
2
3
4
5
6
7
(CTEST6) register to the appropriate byte lane of the  
64-bit DMA FIFO. If the FBL3 bit is set, then FBL2  
through FBL0 determine which of eight byte lanes can be  
read or written. When cleared, the byte lane read or  
written is determined by the current contents of the DMA  
Next Address (DNAD) and DMA Byte Counter (DBC)  
registers. Each of the eight bytes that make up the 64-bit  
DMA FIFO is accessed by writing these bits to the proper  
value. For normal operation, FBL3 must equal zero.  
Register: 0x22  
Chip Test Five (CTEST5)  
Read/Write  
7
ADCK  
0
6
BBCK  
0
5
DFS  
0
4
MASR  
0
3
DDIR  
0
2
BL2  
0
1
0
0
0
BO[9:8]  
ADCK  
Clock Address Incrementor  
7
Setting this bit increments the address pointer contained  
in the DMA Next Address (DNAD) register. The DNAD  
register is incremented based on the DNAD contents and  
4-60  
Registers  
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BBCK  
DFS  
Clock Byte Counter  
6
Setting this bit decrements the byte count contained in  
the 24-bit DBC register. It is decremented based on the  
DMA Byte Counter (DBC) contents and the current DMA  
Next Address (DNAD) value. This bit automatically clears  
itself after decrementing the DBC register.  
DMA FIFO Size  
5
This bit controls the size of the DMA FIFO. When clear,  
the DMA FIFO appears as only 112 bytes deep. When  
set, the DMA FIFO size increases to 944 bytes. Using an  
112-byte FIFO allows software written for other  
LSI53C8XX family chips to properly calculate the number  
of bytes residing in the chip after a target disconnect. The  
default value of this bit is zero.  
MASR  
DDIR  
Master Control for Set or Reset Pulses  
4
This bit controls the operation of bit 3. When this bit is  
set, bit 3 asserts the corresponding signals. When this bit  
is cleared, bit 3 deasserts the corresponding signals. Do  
not change this bit and bit 3 in the same write cycle.  
DMA Direction  
3
Setting this bit either asserts or deasserts the internal  
DMA Write (DMAWR) direction signal depending on the  
current status of the MASR bit in this register. Asserting  
the internal DMA write signal indicates that data is  
transferred from the SCSI bus to the host bus.  
Deasserting the internal DMA write signal transfers data  
from the host bus to the SCSI bus.  
BL2  
Burst Length Bit 2  
2
This bit works with bits 6 and 7 (BL[1:0]) in the DMA  
Mode (DMODE), 0x38 register to determine the burst  
length. For complete definitions of this field, refer to the  
descriptions of DMODE bits 6 and 7. This bit is disabled  
if a 112-byte FIFO is selected by clearing the DMA FIFO  
size bit.  
SCSI Registers  
4-61  
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BO[9:8]  
DMA FIFO Byte Offset Counter, Bits [9:8]  
[1:0]  
These are the upper two bits of the DFBOC. The DFBOC  
consists of these bits, and the DMA FIFO (DFIFO)  
register, bits [7:0].  
Register: 0x23  
Chip Test Six (CTEST6)  
Read/Write  
7
0
DF  
0
0
0
0
0
0
0
0
DF  
DMA FIFO  
[7:0]  
Writing to this register writes data to the appropriate byte  
lane of the DMA FIFO as determined by the FBL bits in  
the Chip Test Four (CTEST4) register. Reading this  
register unloads data from the appropriate byte lane of  
the DMA FIFO as determined by the FBL bits in the  
CTEST4 register. Data written to the FIFO is loaded into  
the top of the FIFO. Data read out of the FIFO is taken  
from the bottom. To prevent DMA data from being  
corrupted, this register should not be accessed before  
starting or restarting SCRIPTS operation. Write this  
register only when testing the DMA FIFO using the  
CTEST4 register. Writing to this register while the test  
mode is not enabled produces unexpected results.  
Registers:0x24–0x26  
DMA Byte Counter (DBC)  
Read/Write  
23  
x
0
x
DBC  
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
DBC  
DMA Byte Counter  
[23:0]  
This 24-bit register determines the number of bytes  
transferred in a Block Move instruction. While sending  
data to the SCSI bus, the counter is decremented as data  
is moved into the DMA FIFO from memory. While  
receiving data from the SCSI bus, the counter is  
decremented as data is written to memory from the  
4-62  
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LSI53C875A. The DBC counter is decremented each  
time data is transferred on the PCI bus. It is decremented  
by an amount equal to the number of bytes that are  
transferred.  
The maximum number of bytes that can be transferred in  
any one Block Move command is 16,777,215 bytes. The  
maximum value that can be loaded into the DMA Byte  
Counter (DBC) register is 0xFFFFFF. If the instruction is  
a Block Move and a value of 0x000000 is loaded into the  
DBC register, an illegal instruction interrupt occurs if the  
LSI53C875A is not in target mode, Command phase.  
The DBC register is also used to hold the least significant  
24 bits of the first Dword of a SCRIPTS fetch, and to hold  
the offset value during table indirect I/O SCRIPTS. For a  
complete description see Chapter 5, “SCSI SCRIPTS  
Instruction Set”. The power-up value of this register is  
indeterminate.  
See Section 5.3.1, “First Dword,” for register detail.  
Register: 0x27  
DMA Command (DCMD)  
Read/Write  
7
0
x
DCMD  
0
1
x
x
x
x
x
DCMD  
DMA Command  
This 8-bit register determines the instruction for the  
[7:0]  
LSI53C875A to execute. This register has a different  
format for each instruction.  
See Section 5.3.1, “First Dword,” for register detail.  
SCSI Registers  
4-63  
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Registers:0x28–0x2B  
DMA Next Address (DNAD)  
Read/Write  
31  
0
0
0
DNAD  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DNAD  
DMA Next Address  
[31:0]  
This 32-bit register contains the general purpose address  
pointer. At the start of some SCRIPTS operations, its  
value is copied from the DMA SCRIPTS Pointer Save  
(DSPS) register. Its value may not be valid except in  
certain abort conditions. The default value of this register  
is zero.  
Registers:0x2C–0x2F  
DMA SCRIPTS Pointer (DSP)  
Read/Write  
31  
0
0
0
DSP  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DSP  
DMA SCRIPTS Pointer  
[31:0]  
To execute SCSI SCRIPTS, the address of the first  
SCRIPTS instruction must be written to this register. In  
normal SCRIPTS operation, once the starting address of  
the SCRIPT is written to this register, SCRIPTS are  
automatically fetched and executed until an interrupt  
condition occurs.  
In single step mode, there is a single step interrupt after  
each instruction is executed. The DMA SCRIPTS Pointer  
(DSP) register does not need to be written with the next  
(DCNTL) register) must be set each time the step  
interrupt occurs to fetch and execute the next SCRIPTS  
command. When writing this register eight bits at a time,  
writing the upper eight bits begins execution of SCSI=  
SCRIPTS. The default value of this register is zero.  
See Section 5.4.2, “Second Dword,” for register detail.  
4-64  
Registers  
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Registers:0x30–0x33  
DMA SCRIPTS Pointer Save (DSPS)  
Read/Write  
31  
x
0
x
DSPS  
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
DSPS  
DMA SCRIPTS Pointer Save  
[31:0]  
This register contains the second Dword of a SCRIPTS  
instruction. It is overwritten each time a SCRIPTS  
instruction is fetched. When a SCRIPTS interrupt  
instruction is executed, this register holds the interrupt  
vector. The power-up value of this register is  
indeterminate.  
Registers:0x34–0x37  
Scratch Register A (SCRATCHA)  
Read/Write  
31  
x
0
x
SCRATCHA  
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
SCRATCHA Scratch Register A  
[31:0]  
This is a general purpose, user-definable scratch pad  
register. Apart from CPU access, only Register  
Read/Write and Memory Moves into the SCRATCH  
register alter its contents. The power-up value of this  
A special mode of this register is enabled by setting the  
PCI Configuration Into Enable bit in the Chip Test Two  
(CTEST2) register. If this bit is set, the SCRATCH A  
register returns bits [31:10] of the Memory Mapped  
Operating register PCI base address (Base Address Reg-  
ister One (MEMORY)) in bits [31:10] of the Scratch Reg-  
ister A (SCRATCHA) when read. Bits [9:0] of SCRATCH  
A will always return zero in this mode. Writes to the  
SCRATCH A register are unaffected. Clearing the PCI  
Configuration Into Enable bit causes the SCRATCH A  
register to return to normal operation.  
SCSI Registers  
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Register: 0x38  
DMA Mode (DMODE)  
Read/Write  
7
6
5
SIOM  
0
4
DIOM  
0
3
ERL  
0
2
ERMP  
0
1
BOF  
0
0
MAN  
0
BL[1:0]  
0
0
BL[1:0]  
Burst Length  
[7:6]  
These bits control the maximum number of Dwords  
transferred per bus ownership, regardless of whether the  
transfers are back-to-back, burst, or a combination of  
both. The LSI53C875A asserts the Bus Request (REQ/)  
output when the DMA FIFO can accommodate a transfer  
of at least one burst threshold of data. Bus Request  
(REQ/) is also asserted during start-of-transfer and  
end-of-transfer cleanup and alignment, even if less than  
a full burst of transfers is performed. The LSI53C875A  
inserts a “fairness delay” of four CLKs between burst  
transfers (as set in BL[2:0]) during normal operation. The  
fairness delay is not inserted during PCI retry cycles. This  
gives the CPU and other bus master devices the  
opportunity to access the PCI bus between bursts.  
The LSI53C875A will only support burst thresholds of up  
to 16 Dwords in the small FIFO mode. Setting the burst  
threshold to higher than 16 Dwords in the small FIFO  
mode will yield unexpected results in burst lengths. The  
big FIFO mode is activated by setting bit 5 of the Chip  
Test Five (CTEST5) register. In the big FIFO mode, the  
LSI53C875A will support burst thresholds of up to  
128 Dwords.  
4-66  
Registers  
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BL2  
(CTEST5 bit 2)  
Burst Length  
Transfers  
BL1  
BL0  
Dwords  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
2
4
8
4
8
16  
16  
321  
641  
32  
64  
1281  
1281  
Reserved  
64  
Reserved  
1. The 944-byte FIFO must be enabled for these burst sizes.  
SIOM  
Source I/O Memory Enable  
5
This bit is defined as an I/O Memory Enable bit for the  
source address of a Memory Move or Block Move  
Command. If this bit is set, then the source address is in  
I/O space; and if cleared, then the source address is in  
memory space.  
This function is useful for register-to-memory operations  
using the Memory Move instruction when the  
LSI53C875A is I/O mapped. Bits 4 and 5 of the Chip Test  
Two (CTEST2) register are used to determine the  
configuration status of the LSI53C875A.  
DIOM  
Destination I/O Memory Enable  
4
This bit is defined as an I/O Memory Enable bit for the  
destination address of a Memory Move or Block Move  
Command. If this bit is set, then the destination address  
is in I/O space; and if cleared, then the destination  
address is in memory space.  
This function is useful for memory-to-register operations  
using the Memory Move instruction when the  
LSI53C875A is I/O mapped. Bits 4 and 5 of the Chip Test  
Two (CTEST2) register are used to determine the  
configuration status of the LSI53C875A.  
ERL  
Enable Read Line  
3
This bit enables a PCI Read Line command. If this bit is  
set and the chip is about to execute a read cycle other  
than an opcode fetch, then the command is 0b1110.  
SCSI Registers  
4-67  
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ERMP  
BOF  
Enable Read Multiple  
2
1
If this bit is set and cache mode is enabled, a Read  
Multiple command is used on all read cycles when it is  
legal.  
Burst Opcode Fetch Enable  
Setting this bit causes the LSI53C875A to fetch  
instructions in burst mode. Specifically, the chip bursts in  
the first two Dwords of all instructions using a single bus  
ownership. If the instruction is a Memory-to-Memory  
Move type, the third Dword is accessed in a subsequent  
bus ownership. If the instruction is an indirect type, the  
additional Dword is accessed in a subsequent bus  
ownership. If the instruction is a table indirect block move  
type, the chip accesses the remaining two Dwords in a  
subsequent bus ownership, thereby fetching the four  
Dwords required in two bursts of two Dwords each. If  
prefetch is enabled, this bit has no effect. This bit also  
has no effect on fetches out of SCRIPTS RAM.  
MAN  
Manual Start Mode  
0
Setting this bit prevents the LSI53C875A from  
automatically fetching and executing SCSI SCRIPTS  
when the DMA SCRIPTS Pointer (DSP) register is  
written. When this bit is set, the Start DMA bit in the DMA  
Control (DCNTL) register must be set to begin SCRIPTS  
execution. Clearing this bit causes the LSI53C875A to  
automatically begin fetching and executing SCSI  
SCRIPTS when the DSP register is written. This bit  
normally is not used for SCSI SCRIPTS operations.  
4-68  
Registers  
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Register: 0x39  
DMA Interrupt Enable (DIEN)  
Read/Write  
7
R
x
6
MDPE  
0
5
BF  
0
4
ABRT  
0
3
SSI  
0
2
SIR  
0
1
R
x
0
IID  
0
R
Reserved  
7
6
5
4
3
1
0
MDPE  
BF  
Master Data Parity Error  
Bus Fault  
ABRT  
SSI  
SIR  
R
Aborted  
Single Step Interrupt  
SCRIPTS Interrupt Instruction Received  
Reserved  
IID  
Illegal Instruction Detected  
This register contains the interrupt mask bits corresponding to the  
interrupting conditions described in the DMA Status (DSTAT) register. An  
interrupt is masked by clearing the appropriate mask bit. Masking an  
interrupt prevents IRQ/ from being asserted for the corresponding  
interrupt, but the status bit is still set in the DSTAT register. Masking an  
interrupt does not prevent setting the Interrupt Status Zero (ISTAT0) DIP.  
All DMA interrupts are considered fatal, therefore SCRIPTS stops  
running when this condition occurs, whether or not the interrupt is  
masked. Setting a mask bit enables the assertion of IRQ/ for the  
corresponding interrupt. (A masked nonfatal interrupt does not prevent  
unmasked or fatal interrupts from getting through; interrupt stacking  
begins when either the Interrupt Status Zero (ISTAT0) SIP or DIP bit is  
set.)  
The IRQ/ output is latched. Once asserted, it will remain asserted until  
the interrupt is cleared by reading the appropriate status register.  
Masking an interrupt after the IRQ/ output is asserted does not cause  
deassertion of IRQ/.  
SCSI Registers  
4-69  
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For more information on interrupts, see Chapter 2, “Functional  
Description”.  
Register: 0x3A  
Scratch Byte Register (SBR)  
Read/Write  
7
0
0
SBR  
0
0
0
0
0
0
0
SBR  
Scratch Byte Register  
This is a general purpose register. Apart from CPU  
[7:0]  
access, only register Read/Write and Memory Moves into  
this register alter its contents. The default value of this  
register is zero. This register is called the DMA Watchdog  
Timer on previous LSI53C8XX family products.  
Register: 0x3B  
DMA Control (DCNTL)  
Read/Write  
7
CLSE  
0
6
0
5
0
4
0
3
IRQM  
0
2
STD  
0
1
IRQD  
0
0
COM  
0
CLSE  
Cache Line Size Enable  
Setting this bit enables the LSI53C875A to sense and  
7
react to cache line boundaries set up by the DMA Mode  
(DMODE) or PCI Cache Line Size register, whichever  
contains the smaller value. Clearing this bit disables the  
cache line size logic and the LSI53C875A monitors the  
cache line size using the DMODE register.  
PFF  
Prefetch Flush  
6
Setting this bit causes the prefetch unit to flush its  
contents. The bit clears after the flush is complete.  
PFEN  
Prefetch Enable  
5
Setting this bit enables an 8-Dword SCRIPTS instruction  
prefetch unit. The prefetch unit, when enabled, will fetch  
8 Dwords of instructions and instruction operands in  
bursts of 4 or 8 Dwords. Prefetching instructions allows  
4-70  
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the LSI53C875A to make more efficient use of the  
system PCI bus, thus improving overall system  
performance. The unit will flush whenever the PFF bit is  
set, as well as on all transfer control instructions when  
the transfer conditions are met, on every write to the  
DMA SCRIPTS Pointer (DSP), on every regular MMOV  
instruction, and when any interrupt is generated. The unit  
automatically determines the maximum burst size that it  
is capable of performing based on the burst length as  
determined by the values in the DMA Mode (DMODE)  
register. If the burst threshold is set to 8 Dwords the  
prefetch unit will fetch instructions in two bursts of  
4 Dwords. If the burst threshold is set to 16 Dwords or  
greater the prefetch unit will fetch instructions in one burst  
of 8 Dwords. Burst thresholds of less than 8 Dwords will  
cause the prefetch unit to be disabled. PCI Cache  
commands (Read Line and Read Multiple) will be issued  
appropriately if PCI caching is enabled. Prefetching from  
SCRIPTS RAM is not supported and is unnecessary due  
to the speed of the fetches. When fetching from  
SCRIPTS RAM the setting of this bit will have no effect  
on the fetch mechanism from SCRIPTS RAM.  
SSM  
Single Step Mode  
4
Setting this bit causes the LSI53C875A to stop after  
executing each SCRIPTS instruction, and generate a  
continues fetching and executing instructions until an  
interrupt condition occurs. For normal SCSI SCRIPTS  
operation, keep this bit clear. To restart the LSI53C875A  
after it generates a SCRIPTS Step interrupt, read the  
Interrupt Status Zero (ISTAT0), Interrupt Status One  
(ISTAT1) and DMA Status (DSTAT) registers to recognize  
and clear the interrupt. Then set the START DMA bit in  
this register.  
IRQM  
IRQ Mode  
3
When set, this bit enables a totem pole driver for the IRQ/  
pin. When cleared, this bit enables an open drain driver  
for the IRQ/ pin with an internal weak pull-up. The bit  
should remain cleared to retain full PCI compliance.  
SCSI Registers  
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STD  
2
The LSI53C875A fetches a SCSI SCRIPTS instruction  
from the address contained in the DMA SCRIPTS Pointer  
(DSP) register when this bit is set. This bit is required if  
the LSI53C875A is in one of the following modes:  
Manual start mode – Bit 0 in the DMA Mode  
(DMODE) register is set  
Single step mode – Bit 4 in the DMA Control (DCNTL)  
register is set  
When the LSI53C875A is executing SCRIPTS in manual  
start mode, the Start DMA bit must be set to start  
instruction fetches, but need not be set again until an  
interrupt occurs. When the LSI53C875A is in single step  
IRQD  
IRQ Disable  
1
Setting this bit disables the IRQ pin. Clearing the bit  
enables normal operation. As with any other register  
other than Interrupt Status Zero (ISTAT0) and Interrupt  
Status One (ISTAT1), this register cannot be accessed  
except by a SCRIPTS instruction during SCRIPTS  
execution. For more information on the use of this bit in  
interrupt handling, see Chapter 2, “Functional  
COM  
LSI53C700 Compatibility  
0
When the COM bit is cleared, the LSI53C875A behaves  
in a manner compatible with the LSI53C700;  
selection/reselection IDs are stored in both the SCSI  
Selector ID (SSID) and SCSI First Byte Received (SFBR)  
registers. This bit is not affected by a software reset.  
If the COM bit is cleared, do not access this register  
using SCRIPTS operation as nondeterminate operations  
may occur. (This includes SCRIPTS Read/Write  
operations and conditional transfer control instructions  
that initialize the SFBR register.)  
When the COM bit is set, the ID is stored only in the  
SSID register, protecting the SFBR from being  
overwritten if a selection/reselection occurs during a DMA  
register-to-register operation.  
4-72  
Registers  
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Registers:0x3C–0x3F  
Adder Sum Output (ADDER)  
Read Only  
31  
0
0
0
ADDER  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ADDER  
Adder Sum Output  
[31:0]  
This register contains the output of the internal adder,  
and is used primarily for test purposes. The power-up  
value for this register is indeterminate. It is used to  
determine if the correct memory address was calculated  
for a relative jump SCRIPTS instruction.  
Register: 0x40  
SCSI Interrupt Enable Zero (SIEN0)  
Read/Write  
7
M/A  
0
6
CMP  
0
5
SEL  
0
4
RSL  
0
3
SGE  
0
2
UDC  
0
1
RST  
0
PAR  
0
This register contains the interrupt mask bits corresponding to the  
interrupting conditions described in the SCSI Interrupt Status Zero  
(SIST0) register. An interrupt is masked by clearing the appropriate mask  
bit. For more information on interrupts, see Chapter 2, “Functional  
Description.”  
M/A  
SCSI Phase Mismatch - Initiator Mode;  
SCSI ATN Condition - Target Mode  
7
In the initiator mode, this bit is set when the SCSI phase  
not match the expected phase in the SCSI Output Control  
Latch (SOCL) register. This expected phase is  
automatically written by SCSI SCRIPTS. In target mode,  
this bit is set when the initiator asserts SATN/. See the  
Disable Halt on Parity Error or SATN/ Condition bit in the  
SCSI Control One (SCNTL1) register for more  
information on when this status is actually raised.  
SCSI Registers  
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CMP  
SEL  
Function Complete  
completed.  
6
5
Selected  
Indicates the LSI53C875A is selected by a SCSI initiator  
device. Set the Enable Response to Selection bit in the  
SCSI Chip ID (SCID) register for this to occur.  
RSL  
SGE  
Reselected  
4
Indicates the LSI53C875A is reselected by a SCSI target  
device. Set the Enable Response to Reselection bit in the  
SCSI Chip ID (SCID) register for this to occur.  
SCSI Gross Error  
3
The following conditions are considered SCSI Gross  
Errors:  
Data underflow – reading the SCSI FIFO when no  
data is present.  
Data overflow – writing to the SCSI FIFO while it is  
full.  
Offset underflow – receiving a SACK/ pulse in target  
mode before the corresponding SREQ/ is sent.  
Offset overflow – receiving an SREQ/ pulse in the  
initiator mode, and exceeding the maximum offset  
(defined by the MO[3:0] bits in the SCSI Transfer  
(SXFER) register).  
A phase change in the initiator mode, with an  
outstanding SREQ/SACK/ offset.  
Residual data in SCSI FIFO – starting a transfer other  
than synchronous data receive with data left in the  
SCSI synchronous receive FIFO.  
UDC  
Unexpected Disconnect  
2
This condition only occurs in the initiator mode. It  
happens when the target to which the LSI53C875A is  
connected disconnects from the SCSI bus unexpectedly.  
See the SCSI Disconnect Unexpected bit in the SCSI  
Control Two (SCNTL2) register for more information on  
expected versus unexpected disconnects. Any  
disconnect in low level mode causes this condition.  
4-74  
Registers  
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RST  
PAR  
SCSI Reset Condition  
Indicates assertion of the SRST/ signal by the  
LSI53C875A or any other SCSI device. This condition is  
edge-triggered, so multiple interrupts cannot occur  
1
SCSI Parity Error  
0
Indicates detection by the LSI53C875A of a parity error  
while receiving or sending SCSI data. See the Disable  
Halt on Parity Error or SATN/ Condition bits in the SCSI  
Control One (SCNTL1) register for more information on  
when this condition is actually raised.  
Register: 0x41  
SCSI Interrupt Enable One (SIEN1)  
Read/Write  
7
3
x
STO  
0
GEN  
0
HTH  
0
R
x
x
x
x
This register contains the interrupt mask bits corresponding to the  
interrupting conditions described in the SCSI Interrupt Status One  
(SIST1) register. An interrupt is masked by clearing the appropriate mask  
bit. For more information on interrupts, refer to Chapter 2, “Functional  
Description.”  
R
[7:3]  
2
STO  
Selection or Reselection Time-out  
The SCSI device which the LSI53C875A is attempting to  
select or reselect does not respond within the  
programmed time-out period. See the description of the  
SCSI Timer Zero (STIME0) register bits [3:0] for more  
information on the time-out timer.  
GEN  
General Purpose Timer Expired  
1
The general purpose timer is expired. The time measured  
is the time between enabling and disabling of the timer.  
See the description of the SCSI Timer One (STIME1)  
register, bits [3:0], for more information on the general  
purpose timer.  
SCSI Registers  
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HTH  
Handshake-to-Handshake Timer Expired  
0
The handshake-to-handshake timer is expired. The time  
measured is the SCSI Request-to-Request (target) or  
Acknowledge-to-Acknowledge (initiator) period. See the  
description of the SCSI Timer Zero (STIME0) register,  
bits [7:4], for more information on the handshake-  
to-handshake timer.  
Register: 0x42  
SCSI Interrupt Status Zero (SIST0)  
Read Only  
7
M/A  
0
6
CMP  
0
5
SEL  
0
4
RSL  
0
3
SGE  
0
2
UDC  
0
1
RST  
0
0
PAR  
0
Reading the SIST0 register returns the status of the various interrupt  
conditions, whether they are enabled in the SCSI Interrupt Enable Zero  
(SIEN0) register or not. Each bit set indicates occurrence of the  
corresponding condition. Reading the SIST0 clears the interrupt status.  
Reading this register clears any bits that are set at the time the register  
interrupts may be pending (the LSI53C875A stacks interrupts). SCSI  
interrupt conditions are individually masked through the SCSI Interrupt  
Enable Zero (SIEN0) register.  
When performing consecutive 8-bit reads of the DMA Status (DSTAT),  
SCSI Interrupt Status Zero (SIST0), and SCSI Interrupt Status One  
(SIST1) registers (in any order), insert a delay equivalent to 12 CLK  
periods between the reads to ensure the interrupts clear properly. Also,  
if reading the registers when both the Interrupt Status Zero (ISTAT0) SIP  
and DIP bits may not be set, read the SIST0 and SIST1 registers before  
the DSTAT register to avoid missing a SCSI interrupt. For more  
information on interrupts, refer to Chapter 2, “Functional Description.”  
M/A  
Initiator Mode: Phase Mismatch; Target Mode:  
SATN/ Active  
7
In the initiator mode, this bit is set if the SCSI phase  
asserted by the target does not match the instruction.  
The phase is sampled when SREQ/ is asserted by the  
4-76  
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target. In target mode, this bit is set when the SATN/  
signal is asserted by the initiator.  
CMP  
SEL  
Function Complete  
This bit is set when an arbitration only or full arbitration  
sequence is completed.  
6
5
Selected  
This bit is set when the LSI53C875A is selected by  
another SCSI device. The Enable Response to Selection  
bit must be set in the SCSI Chip ID (SCID) register (and  
the Response ID Zero (RESPID0) and Response ID One  
(RESPID1) register must hold the chip’s ID) for the  
RSL  
SGE  
Reselected  
4
This bit is set when the LSI53C875A is reselected by  
another SCSI device. The Enable Response to  
Reselection bit must be set in the SCID register (and the  
Response ID Zero (RESPID0) and Response ID One  
(RESPID1) registers must hold the chip’s ID) for the  
LSI53C875A to respond to reselection attempts.  
SCSI Gross Error  
3
This bit is set when the LSI53C875A encounters a SCSI  
Gross Error Condition. The following conditions can result  
in a SCSI Gross Error Condition:  
Data Underflow – reading the SCSI FIFO when no  
data is present.  
Data Overflow – writing too many bytes to the SCSI  
FIFO, or the synchronous offset causes overwriting  
the SCSI FIFO.  
target mode and a SACK/ pulse is received when the  
outstanding offset is zero.  
Offset Overflow – the other SCSI device sends a  
SREQ/ or SACK/ pulse with data which exceeds the  
maximum synchronous offset defined by the SCSI  
Transfer (SXFER) register.  
A phase change occurs with an outstanding  
synchronous offset when the LSI53C875A is  
operating as an initiator.  
SCSI Registers  
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Residual data in the synchronous data FIFO – a  
transfer other than synchronous data receive is  
started with data left in the synchronous data FIFO.  
UDC  
Unexpected Disconnect  
2
This bit is set when the LSI53C875A is operating in the  
initiator mode and the target device unexpectedly  
disconnects from the SCSI bus. This bit is only valid  
when the LSI53C875A operates in the initiator mode.  
When the LSI53C875A operates in low level mode, any  
disconnect causes an interrupt, even a valid SCSI  
disconnect. This bit is also set if a selection time-out  
occurs (it may occur before, at the same time, or stacked  
after the STO interrupt, since this is not considered an  
RST  
SCSI RST/ Received  
1
This bit is set when the LSI53C875A detects an active  
SRST/ signal, whether the reset is generated external to  
the chip or caused by the Assert RST bit in the SCSI  
Control One (SCNTL1) register. This SCSI reset  
detection logic is edge-sensitive, so that multiple  
interrupts are not generated for a single assertion of the  
SRST/ signal.  
PAR  
Parity Error  
0
This bit is set when the LSI53C875A detects a parity  
error while receiving SCSI data. The Enable Parity  
Checking bit (bit 3 in the SCSI Control Zero (SCNTL0)  
register) must be set for this bit to become active. The  
LSI53C875A always generates parity when sending SCSI  
data.  
Register: 0x43  
SCSI Interrupt Status One (SIST1)  
Read Only  
7
3
x
2
STO  
0
1
GEN  
0
HTH  
0
R
x
x
x
x
Reading the SIST1 register returns the status of the various interrupt  
conditions, whether they are enabled in the SCSI Interrupt Enable One  
4-78  
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(SIEN1) register or not. Each bit that is set indicates an occurrence of  
the corresponding condition.  
Reading the SIST1 clears the interrupt condition.  
R
[7:3]  
2
STO  
Selection or Reselection Time-out  
The SCSI device which the LSI53C875A is attempting to  
select or reselect does not respond within the  
programmed time-out period. See the description of the  
SCSI Timer Zero (STIME0) register, bits [3:0], for more  
GEN  
HTH  
General Purpose Timer Expired  
1
This bit is set when the general purpose timer expires.  
The time measured is the time between enabling and  
disabling of the timer. See the description of the SCSI  
Timer One (STIME1) register, bits [3:0], for more  
information on the general purpose timer.  
Handshake-to-Handshake Timer Expired  
0
This bit is set when the handshake-to-handshake timer  
expires. The time measured is the SCSI Request to  
Request (target) or Acknowledge-to-Acknowledge  
(initiator) period. See the description of the SCSI Timer  
Zero (STIME0) register, bits [7:4], for more information on  
the handshake-to-handshake timer.  
Register: 0x44  
SCSI Longitudinal Parity (SLPAR)  
Read/Write  
7
0
x
SLPAR  
x
x
x
x
x
x
x
SLPAR  
SCSI Longitudinal Parity  
This register performs a bytewise longitudinal parity  
[7:0]  
check on all SCSI data received or sent through the SCSI  
core. If one of the bytes received or sent (usually the last)  
is the set of correct even parity bits, SLPAR should go to  
zero (assuming it started at zero). As an example,  
suppose that the following three data bytes and one  
SCSI Registers  
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check byte are received from the SCSI bus (all signals  
are shown active HIGH):  
Data Bytes  
Running SLPAR  
00000000  
1. 11001100 11001100 (XOR of word 1)  
2. 01010101 10011001 (XOR of word 1 and 2)  
3. 00001111 10010110 (XOR of word 1, 2 and 3) Even Parity  
4. 10010110 00000000  
A one in any bit position of the final SLPAR value would  
indicate a transmission error.  
The SLPAR register is also used to generate the check  
bytes for SCSI send operations. If the SLPAR register  
contains all zeros prior to sending a block move, it  
contains the appropriate check byte at the end of the  
block move. This byte must then be sent across the SCSI  
bus.  
Note:  
Writing any value to this register clears it to zero.  
The longitudinal parity checks are meant to provide an  
added measure of SCSI data integrity and are entirely  
optional. This register does not latch SCSI  
selection/reselection IDs under any circumstances. The  
default value of this register is zero.  
The longitudinal parity function normally operates as a  
byte function. During 16-bit transfers, the high and low  
bytes are XORed together and then XORed into the  
current longitudinal parity value. By setting the SLPMD bit  
in the SCSI Control Two (SCNTL2) register, the  
longitudinal parity function is made to operate as a  
of the SCSI bus is XORed with the high byte of the  
current longitudinal parity value, and the low byte of the  
SCSI bus is XORed with the low byte of the current  
longitudinal parity value. In this mode, the 16-bit  
longitudinal parity value is accessed a byte at a time  
through the SCSI Longitudinal Parity (SLPAR) register.  
4-80  
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Which byte is accessed is controlled by the SLPHBEN bit  
in the SCSI Control Two (SCNTL2) register.  
Register: 0x45  
SCSI Wide Residue (SWIDE)  
Read/Write  
7
0
x
SWIDE  
x
x
x
x
x
x
x
SWIDE  
SCSI Wide Residue  
[7:0]  
After a wide SCSI data receive operation, this register  
contains a residual data byte if the last byte received was  
never sent across the DMA bus. It represents either the  
first data byte of a subsequent data transfer, or it is a  
residue byte which should be cleared when an Ignore  
Wide Residue message is received. It may also be an  
overrun data byte. The power-up value of this register is  
indeterminate.  
Register: 0x46  
Memory Access Control (MACNTL)  
Read/Write  
7
1
4
1
3
DWR  
0
2
DRD  
0
1
PSCPT  
0
0
SCPTS  
0
TYP  
1
1
TYP  
Chip Type  
[7:4]  
These bits identify the chip type for software purposes.  
Note:  
These bits no longer identify an 8XX device. These bits  
have been set to 0xF to indicate that the device should be  
uniquely identified by setting the PCI Configuration Enable  
bit in the Chip Test Two (CTEST2) register and using the  
PCI Revision ID and PCI Device ID which will be shadowed  
in the SCRIPTS Fetch Selector (SFS) register. Any devices  
that contain the value 0xF in this register should use this  
mechanism to uniquely identify the device.  
SCSI Registers  
4-81  
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DWR  
Data Write  
3
This bit is used to define if a data write is considered to  
be a local memory access.  
DRD  
Data Read  
2
This bit is used to define if a data read is considered to  
be a local memory access.  
PSCPT  
Pointer SCRIPTS  
1
This bit is used to define if a pointer to a SCRIPTS  
indirect or table indirect fetch is considered to be a local  
memory access.  
SCPTS  
SCRIPTS  
0
This bit is used to define if a SCRIPTS fetch is  
considered to be a local memory access.  
Register: 0x47  
General Purpose Pin Control Zero (GPCNTL0)  
Read/Write  
7
ME  
0
6
FE  
0
5
LEDC  
0
4
0
2
1
1
1
0
1
GPIO  
1
GPIO  
This register is used to determine if the pins controlled by the General  
Purpose (GPREG0) register are inputs or outputs. Bits [4:0] in GPCNTL0  
correspond to bits [4:0] in the GPREG0 register. When the bits are  
enabled as inputs, internal pull-downs are enabled for GPIO[4:2] and  
internal pull-ups are enabled for GPIO[1:0].  
The data written to each bit of the GPREG0 register is output to the  
appropriate GPIO pin if it is set to the output mode in the GPCNTL0  
register.  
ME  
Master Enable  
7
The internal bus master signal is presented on GPIO1 if  
this bit is set, regardless of the state of bit 1 (GPIO1).  
FE  
Fetch Enable  
6
The internal opcode fetch signal is presented on GPIO0  
if this bit is set, regardless of the state of bit 0 (GPIO0).  
4-82  
Registers  
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LEDC  
LED_CNTL  
5
The internal connected signal (bit 3 of the Interrupt Status  
Zero (ISTAT0) register) will be presented on GPIO0 if this  
bit is set and bit 6 of GPCNTL0 is cleared and the chip  
is not in progress of performing an EEPROM  
autodownload regardless of the state of bit 0 (GPIO0).  
This provides a hardware solution to driving a SCSI  
activity LED in many implementations of LSI Logic SCSI  
chips.  
GPIO  
GPIO  
GPIO Enable  
[4:2]  
General purpose control, corresponding to bits [4:2] in  
the GPREG0 register and pins GPIO[4:2]. GPIO4 powers  
up as a general purpose output, and GPIO[3:2] power-up  
as general purpose inputs.  
GPIO Enable  
[1:0]  
These bits power-up set, causing the GPIO1 and GPIO0  
pins to become inputs. Clearing these bits causes  
GPIO[1:0] to become outputs.  
Register: 0x48  
SCSI Timer Zero (STIME0)  
Read/Write  
7
4
0
3
0
0
HTH[3:0]  
SEL[3:0]  
0
0
0
0
0
0
HTH[3:0]  
[7:4]  
These bits select the handshake-to-handshake time-out  
period, the maximum time between SCSI handshakes  
(SREQ/ to SREQ/ in target mode, or SACK/ to SACK/ in  
initiator mode). When this timing is exceeded, an interrupt  
One (SIST1) register is set. The following table contains  
time-out periods for the Handshake-to-Handshake Timer,  
the Selection/Reselection Timer (bits [3:0]), and the  
General Purpose Timer (SCSI Timer One (STIME1) bits  
[3:0]). For a more detailed explanation of interrupts, refer  
to Chapter 2, “Functional Description.”  
SCSI Registers  
4-83  
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HTH [3:0]  
SEL [3:0]  
GEN [3:0]  
Minimum Time-out  
(80 MHz Clock) With  
Minimum Time-out  
(80 MHz Clock) With  
Scale Factor Bit Set  
Scale Factor Bit Cleared1  
0000  
0001  
0010  
0011  
0100  
0101  
0110  
0111  
1000  
1001  
1010  
1011  
1100  
1101  
1110  
1111  
Disabled  
100 µs  
Disabled  
1.6 ms  
3.2 ms  
6.4 ms  
12.8 ms  
25.6 ms  
51.2 ms  
102.4 ms  
204.8 ms  
409.6 ms  
819.2 ms  
1.6 s  
200 µs  
400 µs  
800 µs  
1.6 ms  
3.2 ms  
6.4 ms  
12.8 ms  
25.6 ms  
51.2 ms  
102.4 ms  
204.8 ms  
409.6 ms  
819.2 ms  
1.6 + s  
6.4 s  
12.8 s  
25.6 s  
1. These values are correct if the CCF bits in the SCSI Control Three (SCNTL3)  
register are set according to the valid combinations in the bit description.  
SEL[3:0]  
[3:0]  
These bits select the SCSI selection/reselection time-out  
period. When this timing (plus the 200 µs selection abort  
time) is exceeded, the STO bit in the SCSI Interrupt  
Status One (SIST1) register is set. For a more detailed  
explanation of interrupts, refer to Chapter 2, “Functional  
Description.”  
4-84  
Registers  
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Register: 0x49  
SCSI Timer One (STIME1)  
Read/Write  
7
R
x
6
HTHBA  
0
5
GENSF  
0
4
HTHSF  
0
3
0
0
0
GEN[3:0]  
0
0
R
Reserved  
7
6
HTHBA  
Handshake-to-Handshake Timer Bus Activity  
Enable  
Setting this bit causes this timer to begin testing for SCSI  
REQ/, ACK/ activity as soon as SBSY/ is asserted,  
regardless of the agents participating in the transfer.  
GENSF  
HTHSF  
General Purpose Timer Scale Factor  
Setting this bit causes this timer to shift by a factor of 16.  
Refer to the SCSI Timer Zero (STIME0) register  
description for details.  
5
Handshake-to-Handshake Timer Scale Factor  
Setting this bit causes this timer to shift by a factor of 16.  
Refer to the SCSI Timer Zero (STIME0) register  
description for details.  
4
GEN[3:0]  
[3:0]  
These bits select the period of the general purpose timer.  
The time measured is the time between enabling and  
disabling of the timer. When this timing is exceeded, the  
GEN bit in the SCSI Interrupt Status One (SIST1) register  
is set. Refer to the table under SCSI Timer Zero  
(STIME0), bits [3:0], for the available time-out periods.  
Note:  
To reset a timer before it expires and obtain repeatable  
delays, the time value must be written to zero first, and then  
written back to the desired value. This is also required  
when changing from one time value to another.  
SCSI Registers  
4-85  
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Register: 0x4A  
Response ID Zero (RESPID0)  
Read/Write  
7
0
RESPID0  
x
x
x
x
x
x
x
x
RESPIO0  
Response ID Zero  
[7:0]  
RESPID0 and Response ID One (RESPID1) contain the  
selection or reselection IDs. In other words, these two  
8-bit registers contain the ID that the chip responds to on  
the SCSI bus. Each bit represents one possible ID with  
the most significant bit of RESPID1 representing ID 15  
and the least significant bit of RESPID0 representing  
ID 0. The SCSI Chip ID (SCID) register still contains the  
chip ID used during arbitration. The chip can respond to  
more than one ID because more than one bit can be set  
in the RESPID1 and RESPID0 registers. However, the  
chip can arbitrate with only one ID value in the SCID  
register.  
Register: 0x4B  
Response ID One (RESPID1)  
Read/Write  
7
0
RESPID1  
x
x
x
x
x
x
x
x
RESPID1  
Response ID One  
[7:0]  
Response ID Zero (RESPID0) and RESPID1 contain the  
selection or reselection IDs. In other words, these two  
8-bit registers contain the ID that the chip responds to on  
the SCSI bus. Each bit represents one possible ID with  
the most significant bit of RESPID1 representing ID 15  
and the least significant bit of RESPID0 representing  
ID 0. The SCSI Chip ID (SCID) register still contains the  
chip ID used during arbitration. The chip can respond to  
more than one ID because more than one bit can be set  
in the RESPID1 and RESPID0 registers. However, the  
4-86  
Registers  
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chip can arbitrate with only one ID value in the SCID  
register.  
Register: 0x4C  
SCSI Test Zero (STEST0)  
Read Only  
7
4
x
3
SLT  
2
ART  
x
1
SOZ  
0
SOM  
SSAID  
x
x
x
SSAID  
SCSI Selected As ID  
[7:4]  
These bits contain the encoded value of the SCSI ID that  
the LSI53C875A is selected during a SCSI selection  
phase. These bits work in conjunction with the Response  
ID Zero (RESPID0) and Response ID One (RESPID1)  
registers, which contain the allowable IDs that the  
LSI53C875A can respond to. During a SCSI selection  
phase, when a valid ID is put on the bus, and the  
LSI53C875A responds to that ID, the ID that the chip was  
selected as will be written into the SSAID[3:0] bits.  
SLT  
Selection Response Logic Test  
3
This bit is set when the LSI53C875A is ready to be  
selected or reselected. This does not take into account  
the bus settle delay of 400 ns. This bit is used for  
functional test and fault purposes.  
ART  
Arbitration Priority Encoder Test  
2
This bit is always set when the LSI53C875A exhibits the  
highest priority ID asserted on the SCSI bus during  
arbitration. It is primarily used for chip level testing, but it  
may be used during low level mode operation to  
determine if the LSI53C875A won arbitration.  
SOZ  
SCSI Synchronous Offset Zero  
1
This bit indicates that the current synchronous SREQ/,  
SACK/ offset is zero. This bit is not latched and may  
change at any time. It is used in low level synchronous  
SCSI operations. When this bit is set, the LSI53C875A  
functioning as an initiator, is waiting for the target to  
request data transfers. If the LSI53C875A is a target,  
then the initiator has sent the offset number of  
acknowledges.  
SCSI Registers  
4-87  
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SOM  
SCSI Synchronous Offset Maximum  
0
This bit indicates that the current synchronous SREQ/,  
SACK/ offset is the maximum specified by bits [3:0] in the  
SCSI Transfer (SXFER) register. This bit is not latched  
and may change at any time. It is used in low level  
synchronous SCSI operations. When this bit is set, the  
LSI53C875A, as a target, is waiting for the initiator to  
acknowledge the data transfers. If the LSI53C875A is an  
initiator, then the target has sent the offset number of  
requests.  
Register: 0x4D  
SCSI Test One (STEST1)  
Read/Write  
7
SCLK  
0
6
ISO  
0
5
x
4
x
3
QEN  
0
2
QSEL  
0
1
x
0
x
R
R
SCLK  
SCSI Clock  
7
When set, this bit disables the external SCLK (SCSI  
Clock) pin, and the chip uses the PCI clock as the  
internal SCSI clock. When set, it will also select the PCI  
clock as the internal SCSI clock if the internal clock  
quadrupler is enabled and selected.  
ISO  
SCSI Isolation Mode  
6
This bit allows the LSI53C875A to put the SCSI  
bidirectional and input pins into a low power mode when  
the SCSI bus is not in use. When this bit is set, the SCSI  
bus inputs are logically isolated from the SCSI bus.  
R
Reserved  
[5:4]  
3
QEN  
SCLK Quadrupler Enable  
This bit, when set, powers up the internal clock  
quadrupler circuit, which quadruples the SCLK. A 40  
MHz clock is quadrupled to an internal 160 MHz SCSI  
clock, as required for Ultra SCSI operation. The output  
from a 20 MHz SCLK is 80 MHz. When cleared, this bit  
powers down the internal quadrupler circuit.  
4-88  
Registers  
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QSEL  
SCLK Quadrupler Select  
2
This bit, when set, selects the output of the internal clock  
quadrupler for use as the internal SCSI clock. When  
cleared, this bit selects the clock presented on SCLK for  
use as the internal SCSI clock.  
R
Reserved  
[1:0]  
Register: 0x4E  
SCSI Test Two (STEST2)  
Read/Write  
7
SCE  
0
6
ROF  
0
5
R
0
4
SLB  
0
3
SZM  
0
2
AWS  
0
1
EXT  
0
0
LOW  
0
SCE  
SCSI Control Enable  
Setting this bit allows assertion of all SCSI control and  
7
data lines through the SCSI Output Control Latch (SOCL)  
and SCSI Output Data Latch (SODL) registers regardless  
of whether the LSI53C875A is configured as a target or  
initiator.  
Note:  
Do not set this bit during normal operation, since it could  
cause contention on the SCSI bus. It is included for  
diagnostic purposes only.  
ROF  
Reset SCSI Offset  
6
Setting this bit clears any outstanding synchronous  
SREQ/SACK offset. Set this bit if a SCSI gross error  
condition occurs and to clear the offset when a  
synchronous transfer does not complete successfully.  
The bit automatically clears itself after resetting the  
synchronous offset.  
R
Reserved  
This bit must be cleared.  
5
4
SLB  
SCSI Loopback Mode  
Setting this bit allows the LSI53C875A to perform SCSI  
loopback diagnostics. That is, it enables the SCSI core to  
simultaneously perform as both the initiator and the  
target.  
SCSI Registers  
4-89  
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SZM  
AWS  
SCSI High Impedance Mode  
3
2
Setting this bit places all the open drain 48 mA SCSI  
drivers into a high impedance state. This is to allow  
internal loopback mode operation without affecting the  
SCSI bus.  
Always Wide SCSI  
When this bit is set, all SCSI information transfers are  
done in 16-bit wide mode. This includes data, message,  
command, status and reserved phases. Normally,  
deassert this bit since 16-bit wide message, command,  
and status phases are not supported by the SCSI  
specifications.  
EXT  
Extend SREQ/SACK/ Filtering  
1
LSI Logic TolerANT SCSI receiver technology includes a  
special digital filter on the SREQ/ and SACK/ pins which  
causes the disregarding of glitches on deasserting  
edges. Setting this bit increases the filtering period from  
30 ns to 60 ns on the deasserting edge of the SREQ/ and  
SACK/ signals.  
Note:  
Never set this bit during fast SCSI (greater than 5 Mbyte  
transfers per second) operations, because a valid assertion  
could be treated as a glitch.  
LOW  
SCSI Low level Mode  
0
Setting this bit places the LSI53C875A in the low level  
mode. In this mode, no DMA operations occur, and no  
SCRIPTS execute. Arbitration and selection may be  
performed by setting the start sequence bit as described  
in the SCSI Control Zero (SCNTL0) register. SCSI bus  
SCSI signals. Clearing this bit allows instructions to be  
executed in SCSI SCRIPTS mode.  
Note:  
It is not necessary to set this bit for access to the SCSI  
bit-level registers SCSI Output Data Latch (SODL), SCSI  
Bus Control Lines (SBCL), and input registers.  
4-90  
Registers  
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Register: 0x4F  
SCSI Test Three (STEST3)  
Read/Write  
7
TE  
0
6
STR  
0
5
HSC  
0
4
DSI  
0
3
S16  
x
2
TTM  
0
1
CSF  
0
0
STW  
0
TE  
TolerANT Enable  
7
Setting this bit enables the active negation portion of  
LSI Logic TolerANT technology. Active negation causes  
the SCSI Request, Acknowledge, Data, and Parity  
signals to be actively deasserted, instead of relying on  
external pull-ups, when the LSI53C875A is driving these  
signals. Active deassertion of these signals occurs only  
phase. When operating in a differential environment or at  
fast SCSI timings, TolerANT Active negation should be  
enabled to improve setup and deassertion times. Active  
negation is disabled after reset or when this bit is cleared.  
For more information on LSI Logic TolerANT technology,  
see Chapter 1, “General Description.”  
Note:  
Set this bit if the Enable Ultra SCSI bit in SCSI Control  
Three (SCNTL3) is set.  
STR  
SCSI FIFO Test Read  
6
Setting this bit places the SCSI core into a test mode in  
which the SCSI FIFO is easily read. Reading the least  
significant byte of the SCSI Output Data Latch (SODL)  
register causes the FIFO to unload. The functions are  
summarized in the table below.  
Register  
Name  
Register  
Operation  
FIFO  
Function  
FIFO Bits  
SODL  
SODL0  
SODL1  
Read  
Read  
Read  
[15:0]  
[7:0]  
Unload  
Unload  
None  
[15:8]  
HSC  
Halt SCSI Clock  
5
Asserting this bit causes the internal divided SCSI clock  
to come to a stop in a glitchless manner. This bit is used  
SCSI Registers  
4-91  
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for test purposes or to lower IDD during a power-down  
mode.  
DSI  
Disable Single Initiator Response  
4
If this bit is set, the LSI53C875A ignores all bus-initiated  
selection attempts that employ the single initiator option  
from SCSI-1. In order to select the LSI53C875A while this  
bit is set, the LSI53C875A’s SCSI ID and the initiator’s  
SCSI ID must both be asserted. Assert this bit in  
SCSI-2 systems so that a single bit error on the SCSI bus  
is not interpreted as a single initiator response.  
S16  
16-Bit System  
3
If this bit is set, all devices in the SCSI system  
implementation are assumed to be 16-bit. This causes  
the LSI53C875A to always check the parity bit for SCSI  
IDs [15:8] during bus-initiated selection or reselection,  
assuming parity checking has been enabled. If an 8-bit  
SCSI device attempts to select the LSI53C875A while  
this bit is set, the LSI53C875A will ignore the selection  
attempt. This is because the parity bit for IDs [15:8] will  
not be driven. See the description of the Enable Parity  
Checking bit in the SCSI Control Zero (SCNTL0) register  
for more information.  
TTM  
Timer Test Mode  
2
Asserting this bit facilitates testing of the selection  
time-out, general purpose, and handshake-to-handshake  
timers by greatly reducing all three time-out periods.  
Setting this bit starts all three timers and if the respective  
bits in the SCSI Interrupt Enable One (SIEN1) register  
are asserted, the LSI53C875A generates interrupts at  
time-out. This bit is intended for internal manufacturing  
CSF  
Clear SCSI FIFO  
Setting this bit causes the “full flags” for the SCSI FIFO  
to be cleared. This empties the FIFO. This bit is  
self-clearing. In addition to the SCSI FIFO pointers, the  
SCSI Input Data Latch (SIDL), SCSI Output Data Latch  
(SODL), and (SODR, a hidden buffer register which is not  
accessible) full bits in the SCSI Status Zero (SSTAT0)  
and SCSI Status Two (SSTAT2) are cleared.  
4-92  
Registers  
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STW  
SCSI FIFO Test Write  
0
Setting this bit places the SCSI core into a test mode in  
which the FIFO is easily read or written. While this bit is  
set, writes to the least significant byte of the SCSI Output  
Data Latch (SODL) register cause the entire word  
contained in the SODL to be loaded into the FIFO. These  
functions are summarized in the table below.  
Register  
Name  
Register  
Operation  
FIFO  
Function  
FIFO Bits  
SODL  
SODL0  
SODL1  
Write  
Write  
Write  
[15:0]  
[7:0]  
Load  
Load  
None  
[15:8]  
Registers:0x50–0x51  
SCSI Input Data Latch (SIDL)  
Read Only  
15  
0
SIDL  
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
SIDL  
SCSI Input Data Latch  
[15:0]  
This register is used primarily for diagnostic testing,  
programmed I/O operation, or error recovery. Data  
register. Data can be written to the SCSI Output Data  
Latch (SODL) register and then read back into the  
LSI53C875A by reading this register to allow loopback  
testing. When receiving SCSI data, the data flows into  
this register and out to the host FIFO. This register differs  
from the SCSI Bus Data Lines (SBDL) register; SIDL  
contains latched data and the SBDL always contains  
exactly what is currently on the SCSI data bus. Reading  
this register causes the SCSI parity bit to be checked,  
and causes a parity error interrupt if the data is not valid.  
The power-up values are indeterminate.  
SCSI Registers  
4-93  
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Register: 0x52  
SCSI Test Four (STEST4)  
Read Only  
7
6
5
LOCK  
0
4
x
0
x
R
R
x
x
x
x
x
R
Reserved  
[7:6]  
5
LOCK  
This bit is used when enabling the SCSI clock quadrupler,  
which allows the LSI53C875A to transfer data at Ultra  
SCSI rates. Poll this bit for a 1 to determine that the clock  
quadrupler has locked. For more information on enabling  
the clock quadrupler, refer to the descriptions of SCSI  
Test One (STEST1), bits 2 and 3.  
R
Reserved  
[4:0]  
Register: 0x53  
Reserved  
Registers:0x54–0x55  
SCSI Output Data Latch (SODL)  
Read/Write  
15  
0
SODL  
x
x
x
x
x
x
x
x
x
x
x
SODL  
SCSI Output Data Latch  
[15:0]  
This register is used primarily for diagnostic testing or  
programmed I/O operation. Data written to this register is  
asserted onto the SCSI data bus by setting the Assert  
Data Bus bit in the SCSI Control One (SCNTL1) register.  
This register is used to send data using programmed I/O.  
Data flows through this register when sending data in any  
mode. It is also used to write to the synchronous data  
FIFO when testing the chip. The power-up value of this  
register is indeterminate.  
4-94  
Registers  
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Register: 0x56  
Chip Control 0 (CCNTL0)  
Read/Write  
7
6
5
4
DISFC  
0
3
x
2
x
1
DILS  
0
0
R
x
ENPMJ PMJCTL ENNDJ  
R
0
0
0
ENPMJ  
Enable Phase Mismatch Jump  
Upon setting this bit, any phase mismatches do not  
7
interrupt but force a jump to an alternate location to  
handle the phase mismatch. Prior to actually taking the  
jump, the appropriate remaining byte counts and  
addresses will be calculated such that they can be easily  
stored to the appropriate memory location with SCRIPTS  
Store instruction.  
In the case of a SCSI send, any data in the part will be  
automatically cleared after being accounted for. In the  
case of a SCSI receive, all data will be flushed out of the  
part and accounted for prior to taking the jump. This  
feature does not cover, however, the byte that may  
appear in SCSI Wide Residue (SWIDE). This byte must  
be flushed manually.  
This bit also enables the flushing mechanism to flush  
data during a Data-In phase mismatch in a more efficient  
PMJCTL  
Jump Control  
6
This bit controls which decision mechanism is used when  
jumping on phase mismatch. When this bit is cleared the  
LSI53C875A will use Phase Mismatch Jump Address 1  
(PMJAD1) when the WSR bit is cleared and  
Phase Mismatch Jump Address 2 (PMJAD2) when the  
WSR bit is set. When this bit is set the LSI53C875A will  
use jump address one (PMJAD1) on data out (data out,  
command, message out) transfers and jump address two  
(PMJAD2) on data in (data in, status, message in)  
transfers. Note that the phase referred to here is the  
phase encoded in the block move SCRIPTS instruction,  
not the phase on the SCSI bus that caused the phase  
mismatch.  
SCSI Registers  
4-95  
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ENNDJ  
Enable Jump on Nondata Phase Mismatches  
5
This bit controls whether or not a jump is taken during a  
nondata phase mismatch (i.e. message in, message out,  
status, or command). When this bit is clear, jumps will  
only be taken on Data-In or Data-Out phases and a  
phase mismatch interrupt will be generated for all other  
phases. When this bit is set, jumps will be taken  
regardless of the phase in the block move. Note that the  
phase referred to here is the phase encoded in the block  
move SCRIPTS instruction, not the phase on the SCSI  
DISFC  
Disable Auto FIFO Clear  
4
This bit controls whether or not the FIFO is automatically  
cleared during a Data-Out phase mismatch. When set,  
data in the DMA FIFO as well as data in the SCSI Output  
Data Latch (SODL) and SODR, a hidden buffer register  
which is not accessible, will not be cleared after  
calculations on them are complete. When cleared, the  
DMA FIFO and SODL and SODR will automatically be  
cleared. This bit also disables the enhanced flushing  
mechanism.  
R
Reserved  
[3:2]  
DILS  
Disable Internal Load and Store  
1
This bit controls whether or not Load and Store data  
transfers in which the source/destination is located in  
SCRIPTS RAM generate external PCI cycles.  
If cleared, Load and Store data transfers of this type will  
NOT generate PCI cycles, but will stay internal to the  
chip.  
If set, Load and Store data transfers of this type will  
generate PCI cycles.  
R
Reserved  
0
4-96  
Registers  
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Register: 0x57  
Chip Control 1 (CCNTL1)  
Read/Write  
7
ZMODE  
0
6
4
3
DDAC  
0
2
1
0
R
x
64TIMOD EN64TIBMV EN64DBMV  
x
x
0
0
0
ZMODE  
High Impedance Mode  
7
Setting this bit causes the LSI53C875A to place all output  
and bidirectional pins except MAC/_TESTOUT, into a  
high impedance state. Also, setting this bit causes all I/O  
pins to become inputs, and all pull-ups and pull-downs to  
be disabled. When this bit is set, the MAC/_TESTOUT  
pin becomes the output pin for the connectivity test of the  
LSI53C875A signals in the “AND-tree” test mode. In  
order to read data out of the LSI53C875A, this bit must  
be cleared. This bit is intended for board-level testing  
only. Do not set this bit during normal system operation.  
R
Reserved  
[6:4]  
DDAC  
Disable Dual Address Cycle  
3
When this bit is set, all 64-bit addressing as a master will  
be disabled. No dual address cycles will be generated by  
the LSI53C875A.  
When this bit is cleared, the LSI53C875A will generate  
dual address cycles based on the master operation being  
performed and the value of its associated selector  
register.  
64TIMOD  
64-Bit Table Indirect Indexing Mode  
2
When this bit is cleared, bits [24:28] of the first table entry  
Dword will select one of 22 possible selectors to be used  
in a BMOV operation. When this bit is set, bits [24:31] of  
the first table entry Dword will be copied directly into  
DNAD64 to provide 40-bit addressing capability. This bit  
will only function if the EN64TIBMV bit is set.  
Index Mode 0 (64TIMOD clear) table entry format:  
[31:29]  
[28:24]  
[23:0]  
Reserved  
Sel Index  
Byte Count  
Source/Destination Address [31:0]  
SCSI Registers  
4-97  
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Index Mode 1 (64TIMOD set) table entry format:  
[31:24]  
[23:0]  
Src/Dest Addr [39:32]  
Byte Count  
Source/Destination Address [31:0]  
EN64TIBMV Enable 64-Bit Table Indirect BMOV  
Setting this bit enables 64-bit addressing for Table  
1
Indirect BMOVs using the upper byte (bit [24:31]) of the  
first Dword of the table entry. When this bit is cleared  
table indirect BMOVs will use the Static Block Move  
the data address.  
EN64DBMV Enable 64-Bit Direct BMOV  
0
Setting this bit enables the 64-bit version of a direct  
BMOV. When this bit is cleared direct BMOVs will use the  
Static Block Move Selector (SBMS) register to obtain the  
upper 32 bits of the data address.  
Registers:0x58–0x59  
SCSI Bus Data Lines (SBDL)  
Read Only  
15  
0
SBDL  
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
SBDL  
SCSI Bus Data Lines  
[15:0]  
This register contains the SCSI data bus status. Even  
though the SCSI data bus is active low, these bits are  
active high. The signal status is not latched and is a true  
time the register is read. This register is used when  
receiving data using programmed I/O. This register can  
also be used for diagnostic testing or in low level mode.  
The power-up value of this register is indeterminate.  
If the chip is in the wide mode (SCSI Control Three  
(SCNTL3), bit 3 and SCSI Test Two (STEST2), bit 2 are  
set) and SBDL is read, both byte lanes are checked for  
parity regardless of phase. When in a nondata phase,  
this will cause a parity error interrupt to be generated  
because the upper byte lane parity is invalid.  
4-98  
Registers  
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Register: 0x5A–0x5B  
Reserved  
Registers:0x5C–0x5F  
Scratch Register B (SCRATCHB)  
Read/Write  
31  
x
0
x
SCRATCHB  
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
SCRATCHB Scratch Register B  
[31:0]  
This is a general purpose user definable scratch pad  
register. Apart from CPU access, only register  
Read/Write and Memory Moves directed at the  
SCRATCH register will alter its contents. The power-up  
values are indeterminate. A special mode of this register  
can be enabled by setting the PCI Configuration Into  
Enable bit in the Chip Test Two (CTEST2) register. If this  
bit is set, the SCRATCH B register returns bits [31:12] of  
the SCRIPTS RAM PCI Base Address Register Two  
(SCRIPTS RAM) in bits [31:12] of the SCRATCH B  
register when read. When read, bits [11:0] of SCRATCH  
B will always return zeros in this mode. Writes to the  
SCRATCH B register are unaffected. Resetting the PCI  
Configuration Into Enable bit causes the SCRATCH B  
register to return to normal operation.  
Registers:0x60–0x9F  
Scratch Registers C–R (SCRATCHC–SCRATCHR)  
Read/Write  
These are general purpose user definable scratch pad registers. Apart  
from CPU access, only register read/write, memory moves and Load and  
Stores directed at a SCRATCH register will alter its contents. The  
power-up values are indeterminate.  
4.3 64-Bit SCRIPTS Selectors  
The following registers are used to hold the upper 32-bit addresses for  
various SCRIPTS operations. When a particular type of SCRIPTS  
64-Bit SCRIPTS Selectors  
4-99  
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operation is performed, one of the six selector registers below will be  
used to generate a 64-bit address.  
If the selector for a particular device operation is zero, then a standard  
32-bit address cycle will be generated. If the selector value is nonzero,  
then a DAC will be issued and the 64-bit address will be presented in  
two address phases.  
All selectors default to 0 (zero) with the exception of the 16 SCRATCH  
registers, these power-up in an indeterminate state and should be  
initialized before they are used.  
All selectors can be read/written using the Load and Store SCRIPTS  
instruction, Memory-to-Memory Move, Read/Write SCRIPTS instruction,  
or CPU with SCRIPTS not running.  
Note:  
Crossing of selector boundaries in one memory operation  
is not supported.  
Registers:0xA0–0xA3  
Memory Move Read Selector (MMRS)  
Read/Write  
31  
0
0
0
MMRS  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MMRS  
Memory Move Read Selector (MMRS)  
Supplies the upper Dword of a 64-bit address during data  
read operations for Memory-to-Memory Moves and  
absolute address LOAD operations.  
A special mode of this register can be enabled by setting  
the PCI Configuration Enable bit in the Chip Test Two  
(CTEST2) register. Because the LSI53C875A supports  
only a 32-bit memory mapped PCI base address, the  
MMRS register is always read as 0x00000000 when in  
the special mode.  
Writes to the MMRS register are unaffected. Clearing the  
PCI Configuration Into Enable bit causes the MMRS  
register to return to normal operation.  
4-100  
Registers  
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Registers:0xA4–0xA7  
Memory Move Write Selector (MMWS)  
Read/Write  
31  
0
0
0
MMWS  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MMWS  
[31:0]  
Supplies the upper Dword of a 64-bit address during data  
write operations during Memory-to-Memory Moves and  
absolute address STORE operations.  
A special mode of this register can be enabled by setting  
the PCI Configuration Into Enable bit in the Chip Test Two  
(CTEST2) register. Because the LSI53C875A supports  
only a 32-bit SCRIPTS RAM PCI base address, the  
MMWS register is always read as 0x00000000 when in  
the special mode.  
Writes to the MMWS register are unaffected. Clearing the  
PCI Configuration Enable bit causes the MMWS register  
to return to normal operation.  
Registers:0xA8–0xAB  
SCRIPTS Fetch Selector (SFS)  
Read/Write  
31  
0
0
0
SFS  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SFS  
SCRIPTS Fetch Selector  
Supplies the upper Dword of a 64-bit address during  
SCRIPTS fetches and Indirect fetches (excluding Table  
Indirect fetches). This register can be loaded  
automatically using a 64-bit jump instruction.  
A special mode of this register can be enabled by setting  
the PCI Configuration Into Enable bit in the Chip Test Two  
(CTEST2) register. If this bit is set, bits [23:16] of the SFS  
register return the PCI Revision ID (Rev ID) register value  
and bits [15:0] return the PCI Device ID register value  
when read.  
64-Bit SCRIPTS Selectors  
4-101  
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Writes to the SFS register are unaffected. Clearing the  
PCI Configuration Into Enable bit causes the SFS register  
to return to normal operation.  
Registers:0xAC–0xAF  
DSA Relative Selector (DRS)  
Read/Write  
31  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DRS  
DSA Relative Selector  
[31:0]  
Supplies the upper Dword of a 64-bit address during  
table indirect fetches and Load and Store Data Structure  
Address (DSA) relative operations.  
Registers:0xB0–0xB3  
Static Block Move Selector (SBMS)  
Read/Write  
31  
0
0
0
SBMS  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SBMS  
Static Block Move Selector  
[31:0]  
Supplies the upper Dword of a 64-bit address during  
block move operations, reads or writes. This register is  
static and will not be changed when a 64-bit direct BMOV  
is used.  
4-102  
Registers  
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Registers:0xB4–0xB7  
Dynamic Block Move Selector (DBMS)  
Read/Write  
31  
0
0
0
DBMS  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DBMS  
Dynamic Block Move Selector  
[31:0]  
Supplies the upper Dword of a 64-bit address during  
block move operations, reads or writes. This register is  
used only during 64-bit direct BMOV instructions and will  
be reloaded with the upper 32-bit data address upon  
execution of a 64-bit direct BMOVs.  
Registers:0xB8–0xBB  
DMA Next Address 64 (DNAD64)  
Read/Write  
31  
0
0
0
DNAD64  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DNAD64  
DMA Next Address 64  
[31:0]  
This register holds the current selector being used in a  
given host transaction. The appropriate selector is copied  
to this register prior to beginning a host transaction.  
Registers:0xBC–0xBF  
Reserved  
4.4 Phase Mismatch Jump Registers  
Eight 32-bit registers contain the byte count and addressing information  
required to update the direct, indirect, or table indirect BMOV instructions  
with new byte counts and addresses. The eight register descriptions  
follow.  
All registers can be read/written using the Load and Store SCRIPTS  
instructions, Memory-to-Memory Moves, read/write SCRIPTS  
instructions, or the CPU with SCRIPTS not running.  
Phase Mismatch Jump Registers  
4-103  
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Registers:0xC0–0xC3  
Phase Mismatch Jump Address 1 (PMJAD1)  
Read/Write  
31  
0
0
0
PMJAD1  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PMJAD1  
Phase Mismatch Jump Address 1  
[31:0]  
This register contains the 32-bit address that will be  
jumped to upon a phase mismatch. Depending upon the  
state of the PMJCTL bit in register Chip Control 0  
(CCNTL0) this address will either be used during an  
outbound (data out, command, message out) phase  
mismatch  
(PMJCTL = 0) or when the WSR bit is cleared  
(PMJCTL = 1). It should be loaded with an address of a  
SCRIPTS routine that will handle the updating of memory  
data structures of the BMOV that was executing when the  
phase mismatch occurred.  
Registers:0xC4–0xC7  
Phase Mismatch Jump Address 2 (PMJAD2)  
Read/Write  
31  
0
0
0
PMJAD2  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PMJAD2  
Phase Mismatch Jump Address 2  
[31:0]  
This register contains the 32-bit address that will be  
jumped to upon a phase mismatch. Depending upon the  
state of the PMJCTL bit in register Chip Control 0  
(CCNTL0) this address will either be used during an  
inbound (data in, status, message in) phase mismatch  
(PMJCTL = 0) or when the WSR bit is set (PMJCTL = 1).  
It should be loaded with an address of a SCRIPTS  
routine that will handle the updating of memory data  
structures of the BMOV that was executing when the  
phase mismatch occurred.  
4-104  
Registers  
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Registers:0xC8–0xCB  
Remaining Byte Count (RBC)  
Read/Write  
31  
0
0
0
RBC  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RBC  
Remaining Byte Count (RBC)  
[31:0]  
This register contains the byte count that remains for the  
BMOV that was executing when the phase mismatch  
occurred. In the case of direct or indirect BMOV  
instructions, the upper byte of this register will also  
contain the opcode of the BMOV that was executing. In  
the case of a table indirect BMOV instruction, the upper  
byte will contain the upper byte of the table indirect entry  
that was fetched.  
In the case of a SCSI data receive, this byte count will  
reflect all data received from the SCSI bus, including any  
byte in SCSI Wide Residue (SWIDE). There will be no  
data remaining in the part that must be flushed to  
memory with the exception of a possible byte in the  
SWIDE register. That byte must be flushed to memory  
manually in SCRIPTS.  
In the case of a SCSI data send, this byte count will  
reflect all data sent out onto the SCSI bus. Any data left  
in the part from the phase mismatch will be ignored and  
automatically cleared from the FIFOs.  
Registers:0xCC–0xCF  
Updated Address (UA)  
Read/Write  
31  
0
0
0
UA  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
UA  
Updated Address  
[31:0]  
This register will contain the updated data address for the  
BMOV that was executing when the phase mismatch  
occurred.  
Phase Mismatch Jump Registers  
4-105  
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In the case of a SCSI data receive, if there is a byte in  
the SCSI Wide Residue (SWIDE) register then this  
address will point to the location where that byte must be  
stored. The SWIDE byte must be manually written to  
memory and this address must be incremented prior to  
updating any scatter/gather entry.  
In the case of a SCSI data receive, if there is not a byte  
in the SWIDE register then this address will be the next  
location that should be written to when this I/O restarts.  
No manual flushing will be necessary.  
In the case of a SCSI data send, all data sent to the SCSI  
bus will be accounted for and any data left in the part will  
be ignored and will be automatically cleared from the  
FIFOs.  
Registers:0xD0–0xD3  
Entry Storage Address (ESA)  
Read/Write  
31  
0
0
0
ESA  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
This register's value depends on the type of BMOV being executed. The  
three types of BMOVs are listed below.  
ESA  
Entry Storage Address  
[31:0]  
This register's value depends on the type of BMOV being  
executed. The three types of BMOVs are listed below.  
Direct BMOV:  
In the case of a direct BMOV, this register will contain  
the address the BMOV was fetched from when the  
phase mismatch occurred.  
Indirect BMOV:  
In the case of an indirect BMOV, this register will  
contain the address the BMOV was fetched from when  
the phase mismatch occurred.  
Table Indirect BMOV: In the case of a table indirect BMOV, this register will  
contain the address of the table indirect entry being  
used when the phase mismatch occurred.  
4-106  
Registers  
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Registers:0xD4–0xD7  
Instruction Address (IA)  
Read/Write  
31  
0
0
0
IA  
0
0
0
0
0
0
0
0
0
0
0
0
0
IA  
Instruction Address  
[31:0]  
This register always contains the address of the BMOV  
instruction that was executing when the phase mismatch  
occurred. This value will always match the value in the  
Entry Storage Address (ESA) except in the case of a  
table indirect BMOV in which case the ESA will have the  
address of the table indirect entry and this register will  
point to the address of the BMOV instruction.  
Registers:0xD8–0xDA  
SCSI Byte Count (SBC)  
Read Only  
23  
0
0
SBC  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SBC  
SCSI Byte Count  
[23:0]  
This register contains the count of the number of bytes  
transferred to or from the SCSI bus during any given  
BMOV. This value is used in calculating the information  
placed into the Remaining Byte Count (RBC) and  
Updated Address (UA) register and should not need to be  
used in normal operations. There are two conditions in  
which this byte count will not match the number of bytes  
transferred exactly. If a BMOV is executed to transfer an  
odd number of bytes across a wide bus then the byte  
count at the end of the BMOV will be greater than the  
number of bytes sent by one. This will also happen in an  
odd byte count wide receive case. Also, in the case of a  
wide send in which there is a chain byte from a previous  
transfer, the count will not reflect the chain byte sent  
across the bus during that BMOV. The reason for this is  
due to the fact that to determine the correct address to  
start fetching data from after a phase mismatch this byte  
Phase Mismatch Jump Registers  
4-107  
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cannot be counted for this BMOV as it was actually part  
of the byte count for the previous BMOV.  
Register: 0xDB  
Reserved  
Registers:0xDC–0xDF  
Cumulative SCSI Byte Count (CSBC)  
Read/Write  
31  
0
0
0
CSBC  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CSBC  
Cumulative SCSI Byte Count  
actual number of bytes that have been transferred across  
the SCSI bus during data phases, i.e. it will not count  
bytes sent in command, status, message in or message  
out phases. It will count bytes as long as the phase  
mismatch enable (ENPMJ) bit in the Chip Control 0  
(CCNTL0) register is set. Unlike the SCSI Byte Count  
(SBC) this count will not be cleared on each BMOV  
instruction but will continue to count across multiple  
BMOV instructions. This register can be loaded with any  
arbitrary start value.  
Registers:0xE0–0xFF  
Reserved  
4-108  
Registers  
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Chapter 5  
SCSI SCRIPTS  
Instruction Set  
The LSI53C875A contains a SCSI SCRIPTS processor that permits both  
DMA and SCSI commands to be fetched from host memory or internal  
SCRIPTS RAM. Algorithms written in SCSI SCRIPTS control the actions  
SCSI bus sequences independently of the host CPU. This chapter  
describes the SCSI SCRIPTS Instruction Set used to write these  
algorithms. The following sections describe the benefits and use of SCSI  
SCRIPTS Instructions.  
Section 5.5, “Read/Write Instructions”  
Section 5.6, “Transfer Control Instructions”  
Section 5.7, “Memory Move Instructions”  
Section 5.8, “Load and Store Instructions”  
After power-up and initialization, the LSI53C875A can be operated in the  
low level register interface mode or in the high level SCSI SCRIPTS  
mode.  
5.1 Low Level Register Interface Mode  
With the low level register interface mode, the user has access to the  
DMA control logic and the SCSI bus control logic. An external processor  
has access to the SCSI bus signals and the low level DMA signals, which  
allows creation of complicated board level test algorithms. The low level  
interface is useful for backward compatibility with SCSI devices that  
LSI53C875A PCI to Ultra SCSI Controller  
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require certain unique timings or bus sequences to operate properly.  
Another feature allowed at the low level is loopback testing. In loopback  
mode, the SCSI core can be directed to talk to the DMA core to test  
internal data paths all the way out to the chip’s pins.  
5.2 High Level SCSI SCRIPTS Mode  
To operate in the SCSI SCRIPTS mode, the LSI53C875A requires only  
a SCRIPTS start address. The start address must be at a Dword (four  
byte) boundary. This aligns subsequent SCRIPTS at a Dword boundary  
since all SCRIPTS are 8 or 12 bytes long. Instructions are fetched until  
an interrupt instruction is encountered, or until an unexpected event  
(such as a hardware error) causes an interrupt to the external processor.  
Once an interrupt is generated, the LSI53C875A halts all operations until  
the interrupt is serviced. Then, the start address of the next SCRIPTS  
instruction may be written to the DMA SCRIPTS Pointer (DSP) register  
to restart the automatic fetching and execution of instructions.  
The SCSI SCRIPTS mode of execution allows the LSI53C875A to make  
decisions based on the status of the SCSI bus, which offloads the  
microprocessor from servicing the numerous interrupts inherent in I/O  
operations.  
Given the rich set of SCSI oriented features included in the instruction  
set, and the ability to re-enter the SCSI algorithm at any point, this high  
level interface is all that is required for both normal and exception  
conditions. Switching to low level mode for error recovery should never  
be required.  
The following types of SCRIPTS instructions are implemented in the  
LSI53C875A, as shown in Table 5.1:  
5-2  
SCSI SCRIPTS Instruction Set  
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Table 5.1  
SCRIPTS Instructions  
Description  
Instruction  
Block Move  
Block Move instruction moves data between the SCSI  
bus and memory.  
I/O or Read/Write  
Transfer Control  
Memory Move  
I/O or Read/Write instructions cause the LSI53C875A to  
trigger common SCSI hardware sequences, or to move  
registers.  
Transfer Control instruction allows SCRIPTS instructions  
to make decisions based on real time SCSI bus  
conditions.  
Memory Move instruction causes the LSI53C875A to  
execute block moves between different parts of main  
memory.  
Load and Store  
Load and Store instructions provide a more efficient way  
to move data to/from memory from/to an internal register  
in the chip without using the Memory Move instruction.  
Each instruction consists of two or three 32-bit words. The first 32-bit  
word is always loaded into the DMA Command (DCMD) and DMA Byte  
Counter (DBC) registers, the second into the DMA SCRIPTS Pointer  
Save (DSPS) register. The third word, used only by Memory Move  
instructions, is loaded into the Temporary (TEMP) shadow register. In an  
indirect I/O or Move instruction, the first two 32-bit opcode fetches is  
followed by one or two more 32-bit fetch cycles.  
5.2.1 Sample Operation  
This sample operation describes execution of a SCRIPTS instruction for  
a Block Move instruction.  
The host CPU, through programmed I/O, gives the DMA SCRIPTS  
Pointer (DSP) register (in the Operating register file) the starting  
address in main memory that points to a SCSI SCRIPTS program  
for execution.  
Loading the DMA SCRIPTS Pointer (DSP) register causes the  
LSI53C875A to fetch its first instruction at the address just loaded.  
This is from main memory or the internal RAM, depending on the  
address.  
High Level SCSI SCRIPTS Mode  
5-3  
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The LSI53C875A typically fetches two Dwords (64 bits) and decodes  
the high order byte of the first longword as a SCRIPTS instruction. If  
the instruction is a Block Move, the lower three bytes of the first  
longword are stored and interpreted as the number of bytes to be  
moved. The second longword is stored and interpreted as the 32-bit  
beginning address in main memory to which the move is directed.  
For a SCSI send operation, the LSI53C875A waits until there is  
enough space in the DMA FIFO to transfer a programmable size  
block of data. For a SCSI receive operation, it waits until enough data  
is collected in the DMA FIFO for transfer to memory. At this point,  
the LSI53C875A requests use of the PCI bus again to transfer the  
data.  
When the LSI53C875A is granted the PCI bus, it executes (as a bus  
master) a burst transfer (programmable size) of data, decrement the  
internally stored remaining byte count, increment the address  
pointer, and then release the PCI bus. The LSI53C875A stays off the  
PCI bus until the FIFO can again hold (for a write) or has collected  
(for a read) enough data to repeat the process.  
The process repeats until the internally stored byte count has reached  
zero. The LSI53C875A releases the PCI bus and then performs another  
SCRIPTS instruction fetch cycle, using the incremented stored address  
maintained in the DMA SCRIPTS Pointer (DSP) register. Execution of  
SCRIPTS instructions continues until an error condition occurs or an  
interrupt SCRIPTS instruction is received. At this point, the LSI53C875A  
interrupts the host CPU and waits for further servicing by the host  
system. It can execute independent Block Move instructions specifying  
new byte counts and starting locations in main memory. In this manner,  
the LSI53C875A performs scatter/gather operations on data without  
requiring help from the host program, generating a host interrupt, or  
requiring an external DMA controller to be programmed. An overview of  
this process is presented in Figure 5.1.  
5-4  
SCSI SCRIPTS Instruction Set  
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Figure 5.1 SCRIPTS Overview  
System Processor  
Write DSA  
System Memory  
SCSI Initiator Write Example  
S
Y
S
T
Write  
DSP  
× Select ATN 0, alt_addr  
× Move from identify_msg_buf,  
when MSG_OUT  
× Move from data_buf when DATA_OUT  
× Move from stat_in_buf, when STATUS  
× Move SCNTL2 & 7F to SCNTL2  
× Clear ACK  
E
M
Fetch  
P
C
I
SCRIPTS  
× Wail disconnect alt2  
LSI53C875A  
SCSI Bus  
× Int 10  
For details,  
see block  
Table  
B
U
S
diagram in  
byte count  
address  
Chapter 2  
byte count  
address  
byte count  
address  
Data  
byte count  
address  
Data Structure  
Message Buffer  
Command Buffer  
Data Buffer  
Status Buffer  
High Level SCSI SCRIPTS Mode  
5-5  
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5.3 Block Move Instruction  
Performing a Block Move instruction, bit 5, Source I/O - Memory Enable  
(SIOM) and bit 4, Destination I/O - Memory Enable (DIOM) in the DMA  
Mode (DMODE) register determines whether the source/destination  
address resides in memory or I/O space. When data is being moved onto  
the SCSI bus, SIOM controls whether that data comes from I/O or  
memory space. When data is being moved off of the SCSI bus, DIOM  
controls whether that data goes to I/O or memory space.  
5.3.1 First Dword  
31 30 29 28 27 26  
24 23  
0
x
DMA Command (DCMD) Register  
IT[1:0] IA TIA OPC SCSIP[2:0]  
DMA Byte Counter (DBC) Register  
Transfer Counter [23:0]  
0
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
IT[1:0]  
IA  
Instruction Type - Block Move  
The IT bit configuration (00) defines a Block Move  
Instruction Type.  
[31:30]  
Indirect Addressing  
29  
This bit determines if addressing is direct or indirect.  
If IA bit is (0), use destination field as an address (direct  
addressing). If IA bit is (1), use destination field as a  
pointer to an address (indirect addressing).  
When this bit is zero, user data is moved to or from the  
32-bit data start address for the Block Move instruction.  
The value is loaded into the chip’s address register and  
incremented as data is transferred. The address of the  
data to move is in the second Dword of this instruction.  
When this bit is one, the 32-bit user data start address  
for the Block Move is the address of a pointer to the  
actual data buffer address. The value at the 32-bit start  
address is loaded into the chip’s DMA Next Address  
(DNAD) register using a third longword fetch (4-byte  
transfer across the host computer bus).  
5-6  
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Direct Addressing  
The byte count and absolute address are:  
Command  
Byte Count  
Address of Data  
Indirect Addressing  
Use the fetched byte count, but fetch the data address  
from the address in the instruction.  
Command  
Byte Count  
Address of Pointer to Data  
Once the data pointer address is loaded, it is executed  
as when the chip operates in the direct mode. This  
indirect feature allows a table of data buffer addresses to  
be specified. Using the SCSI SCRIPTS assembler, the  
table offset is placed in the script at compile time. Then  
at the actual data transfer time, the offsets are added to  
the base address of the data address table by the  
external processor. The logical I/O driver builds a  
structure of addresses for an I/O rather than treating each  
address individually. This feature makes it possible to  
locate SCSI SCRIPTS in a PROM.  
Note:  
Do not use indirect and table indirect addressing  
simultaneously; use only one addressing method at a time.  
TIA  
Table Indirect  
28  
32-Bit Addressing  
When this bit is set, the 24-bit signed value in the start  
from the value in the Data Structure Address (DSA)  
register. Both the transfer count and the source/  
destination address are fetched from this location.  
Use the signed integer offset in bits [23:0] of the second  
four bytes of the instruction, added to the value in the  
Data Structure Address (DSA) register, to fetch first the  
byte count and then the data address. The signed value  
is combined with the data structure base address to  
generate the physical address used to fetch values from  
Block Move Instruction  
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the data structure. Sign extended values of all ones for  
negative values are allowed, but bits [31:24] are ignored.  
Command  
Not Used  
Table Offset  
Note:  
Do not use indirect and table indirect addressing  
simultaneously; use only one addressing method at a time.  
Prior to the start of an I/O, the Data Structure Address  
(DSA) register should be loaded with the base address of  
the I/O data structure. The address may be any address  
on a longword boundary.  
After a Table Indirect opcode is fetched, the DSA is  
added to the 24-bit signed offset value from the opcode  
to generate the address of the required data; both  
positive and negative offsets are allowed. A subsequent  
fetch from that address brings the data values into the  
chip.  
For a MOVE instruction, the 24-bit byte count is fetched  
from system memory. Then the 32-bit physical address is  
brought into the LSI53C875A. Execution of the move  
begins at this point.  
SCRIPTS can directly execute operating system I/O data  
structures, saving time at the beginning of an I/O  
operation. The I/O data structure can begin on any  
longword boundary and may cross system segment  
boundaries.  
There are two restrictions on the placement of pointer  
data in system memory:  
The eight bytes of data in the MOVE instruction must  
be contiguous, as shown below, and  
Indirect data fetches are not available during  
execution of a Memory-to-Memory DMA operation.  
00  
Byte Count  
Physical Data Address  
5-8  
SCSI SCRIPTS Instruction Set  
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OPC  
OpCode  
27  
This 1-bit OpCode field defines the type of Block Move  
(MOVE) Instruction to be preformed in Target and Initiator  
mode.  
Target Mode  
In Target mode, the OpCode bit defines the following  
operations:  
OPC  
Instruction Defined  
0
1
MOVE/MOVE64  
CHMOV/CHMOV64  
These instructions perform the following steps:  
1. The LSI53C875A verifies that it is connected to the SCSI  
bus as a Target before executing this instruction.  
2. The LSI53C875A asserts the SCSI phase signals (SMSG/,  
SC_D/, and SI_O/) as defined by the Phase Field bits in the  
instruction.  
3. If the instruction is for the command phase, the  
LSI53C875A receives the first command byte and decodes  
If the SCSI Group Code is either Group 0, Group 1,  
Group 2, or Group 5, and if the Vendor Unique  
Enhancement 1 (VUE1) bit (SCNTL2 bit 1) is clear, then  
the LSI53C875A overwrites the DMA Byte Counter  
(DBC) register with the length of the Command  
Descriptor Block: 6, 10, or 12 bytes.  
If the Vendor Unique Enhancement 1 (VUE1) bit  
(SCNTL2 bit 1) is set, the LSI53C875A receives the  
number of bytes in the byte count regardless of the  
If the Vendor Unique Enhancement 1 bit is clear and  
group code is vendor unique, the LSI53C875A receives  
the number of bytes in the count.  
If any other Group Code is received, the DMA Byte  
Counter (DBC) register is not modified and the  
LSI53C875A requests the number of bytes specified in  
the DMA Byte Counter (DBC) register. If the DBC  
Block Move Instruction  
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register contains 0x000000, an illegal instruction  
interrupt is generated.  
4. The LSI53C875A transfers the number of bytes specified in  
the DBC register starting at the address specified in the  
DMA Next Address (DNAD) register. If the OpCode bit is  
set and a data transfer ends on an odd byte boundary, the  
LSI53C875A stores the last byte in the SCSI Wide Residue  
(SWIDE) register during a receive operation. This byte is  
combined with the first byte from the subsequent transfer  
5. If the SATN/ signal is asserted by the Initiator or a parity  
error occurred during the transfer, the transfer can  
optionally be halted and an interrupt generated. The  
Disable Halt on Parity Error or ATN bit in the SCSI Control  
One (SCNTL1) register controls whether the LSI53C875A  
halts on these conditions immediately, or waits until  
completion of the current Move.  
Initiator Mode  
In Target mode, the OpCode bit defines the following  
operations:  
OPC  
Instruction Defined  
0
1
CHMOV  
MOVE  
These instructions perform the following steps:  
1. The LSI53C875A verifies that it is connected to the SCSI  
bus as an Initiator before executing this instruction.  
2. The LSI53C875A waits for an unserviced phase to occur.  
An unserviced phase is any phase (with SREQ/ asserted)  
for which the LSI53C875A has not yet transferred data by  
responding with a SACK/.  
3. The LSI53C875A compares the SCSI phase bits in the  
DMA Command (DCMD) register with the latched SCSI  
phase lines stored in the SCSI Status One (SSTAT1)  
5-10  
SCSI SCRIPTS Instruction Set  
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register. These phase lines are latched when SREQ/ is  
asserted.  
4. If the SCSI phase bits match the value stored in the SCSI  
transfers the number of bytes specified in the DMA Byte  
Counter (DBC) register starting at the address pointed to  
by the DMA Next Address (DNAD) register. If the OpCode  
bit is cleared and a data transfer ends on an odd byte  
boundary, the LSI53C875A stores the last byte in the SCSI  
Wide Residue (SWIDE) register during a receive operation,  
send operation. This byte is combined with the first byte  
from the subsequent transfer so that a wide transfer can  
complete.  
5. If the SCSI phase bits do not match the value stored in the  
SCSI Status One (SSTAT1) register, the LSI53C875A  
generates a phase mismatch interrupt and the instruction is  
not executed.  
6. During a Message-Out phase, after the LSI53C875A has  
performed a select with Attention (or SATN/ is manually  
asserted with a Set ATN instruction), the LSI53C875A  
deasserts SATN/ during the final SREQ/SACK/ handshake.  
7. When the LSI53C875A is performing a block move for  
Message-In phase, it does not deassert the SACK/ signal  
for the last SREQ/SACK/ handshake. Clear the SACK/  
SCSIP[2:0]  
SCSI Phase  
[26:24]  
This 3-bit field defines the SCSI information transfer  
phase. When the LSI53C875A operates in Initiator mode,  
these bits are compared with the latched SCSI phase bits  
in the SCSI Status One (SSTAT1) register. When the  
LSI53C875A operates in Target mode, it asserts the  
phase defined in this field. Table 5.2 describes the  
possible combinations and the corresponding SCSI  
phase.  
Block Move Instruction  
5-11  
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Table 5.2  
SCSI Information Transfer Phase  
MSG C_D I_O  
SCSI Phase  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Data-Out  
Data-In  
Command  
Status  
Reserved  
Reserved  
Message-Out  
Message-In  
TC[23:0]  
Transfer Counter  
This 24-bit field specifies the number of data bytes to be  
moved between the LSI53C875A and system memory.  
The field is stored in the DMA Byte Counter (DBC)  
register. When the LSI53C875A transfers data to/from  
memory, the DBC register is decremented by the number  
of bytes transferred. In addition, the DMA Next Address  
(DNAD) register is incremented by the number of bytes  
transferred. This process is repeated until the DBC  
register is decremented to zero. At this time, the  
LSI53C875A fetches the next instruction.  
If bit 28 is set, indicating table indirect addressing, this  
field is not used. The byte count is instead fetched from  
a table pointed to by the Data Structure Address (DSA)  
register.  
5-12  
SCSI SCRIPTS Instruction Set  
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5.3.2 Second Dword  
31  
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Start Address  
[31:0]  
This 32-bit field specifies the starting address of the data  
to move to/from memory. This field is copied to the DMA  
Next Address (DNAD) register. When the LSI53C875A  
transfers data to or from memory, the DNAD register is  
incremented by the number of bytes transferred.  
When bit 29 is set, indicating indirect addressing, this  
address is a pointer to an address in memory that points  
to the data location. When bit 28 is set, indicating table  
indirect addressing, the value in this field is an offset into  
a table pointed to by the Data Structure Address (DSA).  
The table entry contains byte count and address  
information.  
5.4 I/O Instruction  
I/O Instructions perform the following SCSI operations in Target and  
Initiator mode. These I/O operations are chosen with the opcode bits in  
the DMA Command (DCMD) register.  
OPC2  
OPC1  
OPC0  
Target Mode  
Initiator Mode  
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
Reselect  
Disconnect  
Wait Select  
Set  
Select  
Wait Disconnect  
Wait Reselect  
Set  
Clear  
Clear  
This section describes these I/O operations.  
I/O Instruction  
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5.4.1 First Dword  
31 30 29  
27 26 25 24 23  
20 19  
16 15  
11 10  
9
8
7
6
5
0
4
0
3
2
0
0
0
DMA Command (DCMD)  
Register  
DMA Byte Counter (DBC) Register  
IT[1:0] OPC[2:0] RA TI Sel  
R
ENDID[3:0]  
R
0
CC TM  
R
ACK  
x
R
ATN  
x
R
0
0
1
x
x
x
x
x
x
0
0
0
0
x
x
x
x
0
0
0
0
x
x
0
0
IT[1:0]  
Instruction Type - I/O Instruction  
[31:30]  
The IT bit configuration (01) defines an I/O Instruction  
Type.  
OPC[2:0]  
[29:27]  
The OpCode bit configurations define the I/O operation  
performed but the OpCode bit meanings change in Target  
mode compared to Initiator mode. OpCode bit  
configurations (101, 110, and 111) are considered  
Read/Write instructions, and are described in Section  
5.5, “Read/Write Instructions.” This section describes  
Target mode operations.  
Target Mode  
OPC2 OPC1 OPC0  
Instruction Defined  
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
Reselect  
Disconnect  
Wait Select  
Set  
Clear  
Reselect Instruction  
The LSI53C875A arbitrates for the SCSI bus by asserting  
the SCSI ID stored in the SCSI Chip ID (SCID) register.  
If it loses arbitration, it tries again during the next  
available arbitration cycle without reporting any lost  
arbitration status.  
If the LSI53C875A wins arbitration, it attempts to reselect  
the SCSI device whose ID is defined in the destination ID  
field of the instruction. Once the LSI53C875A wins  
arbitration, it fetches the next instruction from the address  
pointed to by the DMA SCRIPTS Pointer (DSP) register.  
5-14  
SCSI SCRIPTS Instruction Set  
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This way the SCRIPTS can move on to the next  
instruction before the reselection completes. It continues  
executing SCRIPTS until a SCRIPT that requires a  
response from the Initiator is encountered.  
If the LSI53C875A is selected or reselected before  
winning arbitration, it fetches the next instruction from the  
address pointed to by the 32-bit jump address field stored  
in the DMA Next Address (DNAD) register. Manually set  
the LSI53C875A to Initiator mode if it is reselected, or to  
Target mode if it is selected.  
Disconnect Instruction  
deasserting all SCSI signal outputs.  
Wait Select Instruction  
If the LSI53C875A is selected, it fetches the next  
instruction from the address pointed to by the DMA  
SCRIPTS Pointer (DSP) register.  
If reselected, the LSI53C875A fetches the next instruction  
from the address pointed to by the 32-bit jump address  
field stored in the DMA Next Address (DNAD) register.  
Manually set the LSI53C875A to Initiator mode when it is  
reselected.  
If the CPU sets the SIGP bit in the Interrupt Status Zero  
(ISTAT0) register, the LSI53C875A aborts the Wait Select  
instruction and fetches the next instruction from the  
address pointed to by the 32-bit jump address field stored  
in the DMA Next Address (DNAD) register.  
Set Instruction  
When the SACK/ or SATN/ bits are set, the  
corresponding bits in the SCSI Output Control Latch  
(SOCL) register are set. Do not set SACK/ or SATN/  
except for testing purposes. When the target bit is set,  
the corresponding bit in the SCSI Control Zero (SCNTL0)  
register is also set. When the carry bit is set, the  
corresponding bit in the Arithmetic Logic Unit (ALU) is  
set.  
Note:  
None of the signals are set on the SCSI bus in Target  
mode.  
Clear Instruction  
I/O Instruction  
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When the SACK/ or SATN/ bits are cleared, the  
corresponding bits are cleared in the  
SCSI Output Control Latch (SOCL) register. Do not set  
SACK/ or SATN/ except for testing purposes. When the  
target bit is cleared, the corresponding bit in the SCSI  
Control Zero (SCNTL0) register is cleared. When the  
carry bit is cleared, the corresponding bit in the ALU is  
cleared.  
Note:  
None of the signals are cleared on the SCSI bus in the  
Target mode.  
Initiator Mode  
OPC2 OPC1 OPC0 Instruction Defined  
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
Select  
Wait Disconnect  
Wait Reselect  
Set  
Clear  
Select Instruction  
The LSI53C875A arbitrates for the SCSI bus by asserting  
the SCSI ID stored in the SCSI Chip ID (SCID) register.  
If it loses arbitration, it tries again during the next  
available arbitration cycle without reporting any lost  
arbitration status.  
If the LSI53C875A wins arbitration, it attempts to select  
the SCSI device whose ID is defined in the destination ID  
field of the instruction. Once the LSI53C875A wins  
arbitration, it fetches the next instruction from the address  
pointed to by the DMA SCRIPTS Pointer (DSP) register.  
This way the SCRIPTS can move to the next instruction  
before the selection completes. It continues executing  
SCRIPTS until a SCRIPT that requires a response from  
the Target is encountered.  
If the LSI53C875A is selected or reselected before  
winning arbitration, it fetches the next instruction from the  
address pointed to by the 32-bit jump address field stored  
in the DMA Next Address (DNAD) register. Manually set  
5-16  
SCSI SCRIPTS Instruction Set  
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the LSI53C875A to Initiator mode if it is reselected, or to  
Target mode if it is selected.  
If the Select with SATN/ field is set, the SATN/ signal is  
asserted during the selection phase.  
Wait Disconnect Instruction  
The LSI53C875A waits for the Target to perform a “legal”  
disconnect from the SCSI bus. A “legal” disconnect  
occurs when SBSY/ and SSEL/ are inactive for a  
minimum of one Bus Free delay (400 ns), after the  
LSI53C875A receives a Disconnect Message or a  
Wait Reselect Instruction  
If the LSI53C875A is selected before being reselected, it  
by the 32-bit jump address field stored in the DMA Next  
Address (DNAD) register. Manually set the LSI53C875A  
to Target mode when it is selected.  
If the LSI53C875A is reselected, it fetches the next  
instruction from the address pointed to by the DMA  
SCRIPTS Pointer (DSP) register.  
If the CPU sets the SIGP bit in the Interrupt Status Zero  
(ISTAT0) register, the LSI53C875A aborts the Wait  
Reselect instruction and fetches the next instruction from  
the address pointed to by the 32-bit jump address field  
stored in the DMA Next Address (DNAD) register.  
Set Instruction  
When the SACK/ or SATN/ bits are set, the  
corresponding bits in the SCSI Output Control Latch  
(SOCL) register are set. When the target bit is set, the  
corresponding bit in the SCSI Control Zero (SCNTL0)  
register is also set. When the carry bit is set, the  
corresponding bit in the ALU is set.  
Clear Instruction  
When the SACK/ or SATN/ bits are cleared, the  
corresponding bits are cleared in the SCSI Output Con-  
trol Latch (SOCL) register. When the target bit is cleared,  
the corresponding bit in the SCSI Control Zero (SCNTL0)  
register is cleared. When the carry bit is cleared, the  
corresponding bit in the ALU is cleared.  
I/O Instruction  
5-17  
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RA  
Relative Addressing Mode  
26  
When this bit is set, the 24-bit signed value in the DMA  
Next Address (DNAD) register is used as a relative  
displacement from the current DMA SCRIPTS Pointer  
(DSP) address. Use this bit only in conjunction with the  
Select, Reselect, Wait Select, and Wait Reselect  
instructions. The Select and Reselect instructions can  
transfer address.  
TI  
Table Indirect Mode  
25  
When this bit is set, the 24-bit signed value in the DMA  
Byte Counter (DBC) register is added to the value in the  
Data Structure Address (DSA) register, and used as an  
offset relative to the value in the Data Structure Address  
(DSA) register. The SCSI Control Three (SCNTL3) value,  
SCSI ID, synchronous offset and synchronous period are  
loaded from this address. Prior to the start of an I/O, load  
the Data Structure Address (DSA) with the base address  
of the I/O data structure. Any address on a Dword  
boundary is allowed. After a Table Indirect opcode is  
fetched, the Data Structure Address (DSA) is added to  
the 24-bit signed offset value from the opcode to  
generate the address of the required data. Both positive  
and negative offsets are allowed. A subsequent fetch  
from that address brings the data values into the chip.  
SCRIPTS can directly execute operating system I/O data  
structures, saving time at the beginning of an I/O  
operation. The I/O data structure can begin on any Dword  
boundary and may cross system segment boundaries.  
There are two restrictions on the placement of data in  
system memory:  
above or below the base address.  
An I/O command structure must have all four bytes  
contiguous in system memory, as shown below. The  
offset/period bits are ordered as in the SCSI Transfer  
(SXFER) register. The configuration bits are ordered  
as in the SCSI Control Three (SCNTL3) register.  
Config  
ID  
Offset/period  
00  
5-18  
SCSI SCRIPTS Instruction Set  
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Use this bit only in conjunction with the Select, Reselect,  
Wait Select, and Wait Reselect instructions. Use bits 25  
and 26 individually or in=combination to produce the  
following conditions:  
Bit 25  
Bit 26  
Direct  
0
0
1
1
0
1
0
1
Table Indirect  
Relative  
Table Relative  
Direct  
Uses the device ID and physical address in the  
instruction.  
Command  
ID  
Not Used  
Not Used  
Absolute Alternate Address  
Table Indirect  
Uses the physical jump address, but fetches data using  
the table indirect method.  
Command  
Table Offset  
Absolute Alternate Address  
Relative  
Uses the device ID in the instruction, but treats the  
alternate address as a relative jump.  
Command  
ID  
Not Used  
Not Used  
Absolute Jump Offset  
I/O Instruction  
5-19  
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Table Relative  
Treats the alternate jump address as a relative jump and  
fetches the device ID, synchronous offset, and  
synchronous period indirectly. The value in bits [23:0] of  
the first four bytes of the SCRIPTS instruction is added  
to the data structure base address to form the fetch  
address.  
Command  
Table Offset  
Absolute Jump Offset  
Sel  
Select with ATN/  
24  
This bit specifies whether SATN/ is asserted during the  
selection phase when the LSI53C875A is executing a  
Select instruction. When operating in Initiator mode, set  
this bit for the Select instruction. If this bit is set on any  
other I/O instruction, an illegal instruction interrupt is  
generated.  
R
Reserved  
[23:20]  
ENDID[3:0]  
Encoded SCSI Destination ID  
[19:16]  
This 4-bit field specifies the destination SCSI ID for an I/O  
instruction.  
R
Reserved  
[15:11]  
CC  
Set/Clear Carry  
10  
This bit is used in conjunction with a Set or Clear  
instruction to set or clear the Carry bit. Setting this bit  
with a Set instruction asserts the Carry bit in the ALU.  
Clearing this bit with a Clear instruction deasserts the  
Carry bit in the ALU.  
TM  
Set/Clear Target Mode  
9
This bit is used in conjunction with a Set or Clear  
instruction to set or clear Target mode. Setting this bit  
with a Set instruction configures the LSI53C875A as a  
Target device (this sets bit 0 of the SCSI Control Zero  
(SCNTL0) register). Clearing this bit with a Clear  
instruction configures the LSI53C875A as an Initiator  
device (this clears bit 0 of the SCNTL0 register).  
5-20  
SCSI SCRIPTS Instruction Set  
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R
Reserved  
[8:7]  
6
ACK  
R
Set/Clear SACK/  
Reserved  
[5:4]  
3
ATN  
Set/Clear SATN/  
These two bits are used in conjunction with a Set or Clear  
instruction to assert or deassert the corresponding SCSI  
control signal. Bit 6 controls the SCSI SACK/ signal. Bit 3  
controls the SCSI SATN/ signal.  
The Set instruction is used to assert SACK/ and/or SATN/  
on the SCSI bus. The Clear instruction is used to  
deassert SACK/ and/or SATN/ on the SCSI bus. The  
corresponding bit in the SCSI Output Control Latch  
(SOCL) register is set or cleared depending on the  
instruction used.  
Since SACK/ and SATN/ are Initiator signals, they are not  
asserted on the SCSI bus unless the LSI53C875A is  
operating as an Initiator or the SCSI Loopback Enable bit  
is set in the SCSI Test Two (STEST2) register.  
The Set/Clear SCSI ACK/, ATN/ instruction is used after  
message phase Block Move operations to give the  
Initiator the opportunity to assert attention before  
acknowledging the last message byte. For example, if the  
Initiator wishes to reject a message, it issues an Assert  
SCSI ATN instruction before a Clear SCSI ACK  
instruction.  
R
[2:0]  
5.4.2 Second Dword  
31  
0
DMA SCRIPTS Pointer Save (DSPS) Register  
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
SA  
Start Address  
[31:0]  
This 32-bit field contains the memory address to fetch the  
next instruction if the selection or reselection fails.  
I/O Instruction  
5-21  
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If relative or table relative addressing is used, this value  
is a 24-bit signed offset relative to the current DMA  
SCRIPTS Pointer (DSP) register value.  
5.5 Read/Write Instructions  
The Read/Write instruction supports addition, subtraction, and  
comparison of two separate values within the chip. It performs the  
desired operation on the specified register and the SCSI First Byte  
Received (SFBR) register, then stores the result back to the specified  
register or the SFBR. If the COM bit DMA Control (DCNTL bit 0) is  
5.5.1 First Dword  
31 30 29  
27 26  
24 23 22  
16 15  
DMA Byte Counter (DBC) Register  
ImmD A7 Reserved - Must be 0  
8
7
6
0
DMA Command (DCMD)  
Register  
IT[1:0] OPC[2:0] O[2:0] D8  
A[6:0]  
x
0
1
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
0
0
0
0
0
0
IT[1:0]  
Instruction Type - Read/Write Instruction  
[31:30]  
The configuration of the IT bits, the OpCode bits and the  
Operator bits define the Read/Write Instruction Type. The  
configuration of all these bits determine which instruction  
is currently selected.  
OPC[2:0]  
O[2:0]  
D8  
OpCode  
[29:27]  
The combinations of these bits determine if the  
instruction is a Read/Write or an I/O instruction. OpCodes  
0b000 through 0b100 are considered I/O instructions.  
Operator  
[26:24]  
These bits are used in conjunction with the opcode bits  
to determine which instruction is currently selected. Refer  
to Table 5.1 for field definitions.  
Use data8/SFBR  
23  
When this bit is set, SFBR is used instead of the data8  
value during a Read-Modify-Write instruction (see  
Table 5.1). This allows the user to add two register  
values.  
5-22  
SCSI SCRIPTS Instruction Set  
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A[6:0]  
Register Address - A[6:0]  
[22:16]  
It is possible to change register values from SCRIPTS in  
read-modify-write cycles or move to/from SFBR cycles.  
A[6:0] selects an 8-bit source/destination register within  
the LSI53C875A.  
ImmD  
A7  
Immediate Data  
This 8-bit value is used as a second operand in logical  
and arithmetic functions.  
[15:8]  
Upper Register Address Line [A7]  
7
This bit is used to access registers 0x80–0xFF.  
R
[6:0]  
5.5.2 Second Dword  
31  
0
DMA SCRIPTS Pointer Save (DSPS) Register  
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Destination Address  
[31:0]  
This field contains the 32-bit destination address where  
the data is to move.  
5.5.3 Read-Modify-Write Cycles  
During these cycles the register is read, the selected operation is  
performed, and the result is written back to the source register.  
The Add operation is used to increment or decrement register values (or  
memory values if used in conjunction with a Memory-to-Register Move  
operation) for use as loop counters.  
Subtraction is not available when SFBR is used instead of data8 in the  
instruction syntax. To subtract one value from another when using SFBR,  
first XOR the value to subtract (subtrahend) with 0xFF, and add 1 to the  
resulting value. This creates the 2’s complement of the subtrahend. The  
two values are then added to obtain the difference.  
Read/Write Instructions  
5-23  
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5.5.4 Move To/From SFBR Cycles  
All operations are read-modify-writes. However, two registers are  
involved, one of which is always the SFBR. Table 5.3 shows the possible  
read-modify-write operations. The possible functions of this instruction  
are:  
Write one byte (value contained within the SCRIPTS instruction) into  
any chip register.  
Move to/from the SFBR from/to any other register.  
Alter the value of a register with AND, OR, ADD, XOR, SHIFT LEFT,  
or SHIFT RIGHT operators.  
After moving values to the SFBR, the compare and jump, call, or  
similar instructions are used to check the value.  
A Move-to-SFBR followed by a Move-from-SFBR is used to perform  
a register-to-register move.  
Table 5.3  
Read/Write Instructions  
OpCode 111  
Operator Read-Modify-Write  
OpCode 110  
Move to SFBR  
OpCode 101  
Move from SFBR  
000  
Move data into register.  
Syntax: “Move data8 to  
RegA”  
Move data into SCSI First  
Byte Received (SFBR)  
register. Syntax: “Move  
data8 to SFBR”  
Move data into register.  
Syntax: “Move data8 to  
RegA”  
0011  
Shift register one bit to the Shift register one bit to the  
left and place the result in left and place the result in  
the same register. Syntax: the SCSI First Byte  
Shift the SFBR register one  
bit to the left and place the  
result in the register. Syntax:  
“Move SFBR SHL RegA”  
“Move RegA SHL RegA”  
Received (SFBR) register.  
Syntax: “Move RegA SHL  
SFBR”  
010  
011  
OR data with register and OR data with register and  
place the result in the same place the result in the SCSI place the result in the  
OR data with SFBR and  
register. Syntax: “Move  
RegA | data8 to RegA”  
First Byte Received (SFBR) register. Syntax: “Move  
register. Syntax: “Move  
RegA | data8 to SFBR”  
SFBR | data8 to RegA”  
XOR data with register and XOR data with register and XOR data with SFBR and  
place the result in the same place the result in the SCSI place the result in the  
register. Syntax: “Move  
RegA XOR data8 to RegA” register. Syntax: “Move  
RegA XOR data8 to SFBR”  
First Byte Received (SFBR) register. Syntax: “Move  
SFBR XOR data8 to RegA”  
5-24  
SCSI SCRIPTS Instruction Set  
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Table 5.3  
Read/Write Instructions (Cont.)  
OpCode 111  
Operator Read-Modify-Write  
OpCode 110  
Move to SFBR  
OpCode 101  
Move from SFBR  
100  
AND data with register and AND data with register and AND data with SFBR and  
place the result in the same place the result in the SCSI place the result in the  
register. Syntax: “Move  
RegA & data8 to RegA”  
First Byte Received (SFBR) register. Syntax: “Move  
register. Syntax: “Move  
RegA & data8 to SFBR”  
SFBR & data8 to RegA”  
1011  
Shift register one bit to the Shift register one bit to the  
right and place the result in right and place the result in bit to the right and place the  
Shift the SFBR register one  
the same register. Syntax: the SCSI First Byte  
“Move RegA SHR RegA” Received (SFBR) register.  
result in the register. Syntax:  
“Move SFBR SHR RegA”  
Syntax: “Move RegA SHR  
SFBR”  
110  
111  
Add data to register without Add data to register without Add data to SFBR without  
carry and place the result  
in the same register.  
Syntax: “Move RegA +  
data8 to RegA”  
carry and place the result in carry and place the result in  
the SCSI First Byte  
Syntax: “Move RegA + data8  
to SFBR”  
the register. Syntax: “Move  
SFBR + data8 to RegA”  
Add data to register with  
carry and place the result  
in the same register.  
Add data to register with  
carry and place the result in and place the result in the  
the SCSI First Byte  
Add data to SFBR with carry  
register. Syntax: “Move  
Syntax: “Move RegA +  
Received (SFBR) register.  
SFBR + data8 to RegA with  
data8 to RegA with carry” Syntax: “Move RegA + data8 carry”  
to SFBR with carry”  
1. Data is shifted through the Carry bit and the Carry bit is shifted into the data byte.  
Miscellaneous Notes:  
• Substitute the desired register name or address for “RegA” in the syntax examples.  
• data8 indicates eight bits of data.  
• Use SFBR instead of data8 to add two register values.  
5.6 Transfer Control Instructions  
This section describes the Transfer Control Instructions. The  
configuration of the OpCode bits define which Transfer Control Instruction  
to perform.  
Transfer Control Instructions  
5-25  
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5.6.1 First Dword  
31 30 29  
27 26  
24 23 22 21 20 19 18 17 16 15  
8
7
x
0
x
DMA Command (DCMD)  
Register  
DMA Byte Counter (DBC) Register  
DCM-Data Compare  
DCV-Data Compare  
Value  
IT[1:0] OPC[2:0] SCSIP[2:0] RA R CT IF JMP CD CP WVP  
Mask  
1
0
x
x
x
x
x
x
x
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
IT[1:0]  
Instruction Type - Transfer Control  
Instruction  
[31:30]  
The IT bit configuration (10) defines the Transfer Control  
Instruction Type.  
OPC[2:0]  
OpCode  
[29:27]  
This 3-bit field specifies the type of Transfer Control  
Instruction to execute. All Transfer Control Instructions  
can be conditional. They can be dependent on a  
true/false comparison of the ALU Carry bit or a  
comparison of the SCSI information transfer phase with  
the Phase field, and/or a comparison of the First Byte  
Received with the Data Compare field. Each instruction  
can operate in Initiator or Target mode. Transfer Control  
Instructions are shown in Table 5.4.  
Table 5.4  
OPC2  
Transfer Control Instructions  
OPC1 OPC0 Instruction Defined  
0
0
0
0
1
0
0
1
1
X
0
1
0
1
X
Jump  
Call  
Return  
Interrupt  
Reserved  
Jump Instruction  
The LSI53C875A can do a true/false comparison of the  
ALU carry bit, or compare the phase and/or data as  
defined by the Phase Compare, Data Compare and  
True/False bit fields.  
If the comparisons are true, then it loads the DMA  
SCRIPTS Pointer (DSP) register with the contents of the  
5-26  
SCSI SCRIPTS Instruction Set  
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DMA SCRIPTS Pointer Save (DSPS) register. The DSP  
register now contains the address of the next instruction.  
If the comparisons are false, the LSI53C875A fetches the  
next instruction from the address pointed to by the DMA  
SCRIPTS Pointer (DSP) register, leaving the instruction  
pointer unchanged.  
Call Instruction  
ALU carry bit, or compare the phase and/or data as  
defined by the Phase Compare, Data Compare, and  
True/False bit fields.  
If the comparisons are true, it loads the DMA SCRIPTS  
Pointer (DSP) register with the contents of the DMA  
SCRIPTS Pointer Save (DSPS) register and that address  
value becomes the address of the next instruction.  
When the LSI53C875A executes a Call instruction, the  
instruction pointer contained in the DSP register is stored  
in the Temporar y (TEMP) register. Since the TEMP  
register is not a stack and can only hold one Dword,  
nested call instructions are not allowed.  
If the comparisons are false, the LSI53C875A fetches the  
next instruction from the address pointed to by the DSP  
register and the instruction pointer is not modified.  
Return Instruction  
ALU carry bit, or compare the phase and/or data as  
defined by the Phase Compare, Data Compare, and  
True/False bit fields.  
If the comparisons are true, it loads the DMA SCRIPTS  
Pointer (DSP) register with the contents of the DMA  
SCRIPTS Pointer Save (DSPS) register. That address  
value becomes the address of the next instruction.  
When a Return instruction is executed, the value stored  
in the Temporary (TEMP) register is returned to the DSP  
register. The LSI53C875A does not check to see whether  
the Call instruction has already been executed. It does  
not generate an interrupt if a Return instruction is  
executed without previously executing a Call instruction.  
Transfer Control Instructions  
5-27  
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If the comparisons are false, the LSI53C875A fetches the  
next instruction from the address pointed to by the DSP  
register and the instruction pointer is not modified.  
Interrupt Instruction  
The LSI53C875A can do a true/false comparison of the  
ALU carry bit, or compare the phase and/or data as  
True/False bit fields.  
If the comparisons are true, the LSI53C875A generates  
an interrupt by asserting the IRQ/ signal.  
The 32-bit address field stored in the DMA SCRIPTS  
Pointer Save (DSPS) register can contain a unique  
interrupt service vector. When servicing the interrupt, this  
unique status code allows the Interrupt Service Routine  
to quickly identify the point at which the interrupt  
occurred.  
The LSI53C875A halts and the DMA SCRIPTS Pointer  
(DSP) register must be written to before starting any  
further operation.  
Interrupt-on-the-Fly Instruction  
The LSI53C875A can do a true/false comparison of the  
ALU carry bit or compare the phase and/or data as  
defined by the Phase Compare, Data Compare, and  
True/False bit fields. If the comparisons are true, and the  
Interrupt-on-the-Fly bit (Interrupt Status One (ISTAT1)  
bit 2) is set, the LSI53C875A asserts the Interrupt-on-the-  
Fly bit.  
SCSIP[2:0]  
SCSI Phase  
[26:24]  
This 3-bit field corresponds to the three SCSI bus phase  
signals that are compared with the phase lines latched  
when SREQ/ is asserted. Comparisons can be performed  
to determine the SCSI phase actually being driven on the  
SCSI bus. Table 5.5 describes the possible combinations  
and their corresponding SCSI phase. These bits are only  
valid when the LSI53C875A is operating in Initiator mode.  
Clear these bits when the LSI53C875A is operating in  
Target mode.  
5-28  
SCSI SCRIPTS Instruction Set  
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Table 5.5  
MSG  
SCSI Phase Comparisons  
C/D I/O SCSI Phase  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Data-Out  
Data-In  
Command  
Status  
Reserved  
Reserved  
Message-Out  
Message-In  
RA  
Relative Addressing Mode  
23  
When this bit is set, the 24-bit signed value in the DMA  
SCRIPTS Pointer Save (DSPS) register is used as a  
relative offset from the current DMA SCRIPTS Pointer  
(DSP) address (which is pointing to the next instruction,  
not the one currently executing). The relative mode does  
not apply to Return and Interrupt SCRIPTS.  
Jump/Call an Absolute Address  
Start execution at the new absolute address.  
Command  
Condition Codes  
Absolute Alternate Address  
Jump/Call a Relative Address  
Start execution at the current address plus (or minus) the  
relative offset.  
Command  
Don’t Care  
Condition Codes  
Alternate Jump Offset  
The SCRIPTS program counter is a 32-bit value pointing  
to the SCRIPTS currently under execution by the  
LSI53C875A. The next address is formed by adding the  
32-bit program counter to the 24-bit signed value of the  
last 24 bits of the Jump or Call instruction. Because it is  
Transfer Control Instructions  
5-29  
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signed (2’s complement), the jump can be forward or  
backward.  
A relative transfer can be to any address within a  
16 Mbyte segment. The program counter is combined  
with the 24-bit signed offset (using addition or  
subtraction) to form the new execution address.  
SCRIPTS programs may contain a mixture of direct  
jumps and relative jumps to provide maximum versatility  
when writing SCRIPTS. For example, major sections of  
code can be accessed with far calls using the 32-bit  
physical address, then local labels can be called using  
relative transfers. If a SCRIPT is written using only  
relative transfers it does not require any run time  
alteration of physical addresses, and can be stored in and  
executed from a PROM.  
R
Reserved  
22  
CT  
Carry Test  
21  
When this bit is set, decisions based on the ALU carry bit  
can be made. True/False comparisons are legal, but Data  
Compare and Phase Compare are illegal.  
IF  
Interrupt-on-the-Fly  
20  
When this bit is set, the interrupt instruction does not halt  
the SCRIPTS processor. Once the interrupt occurs, the  
Interrupt-on-the-Fly bit (Interrupt Status One (ISTAT1)  
bit 2) is asserted.  
JMP  
Jump If True/False  
19  
This bit determines whether the LSI53C875A branches  
when a comparison is true or when a comparison is false.  
This bit applies to phase compares, data compares, and  
carry tests. If both the Phase Compare and Data  
Compare bits are set, then both compares must be true  
to branch on a true condition. Both compares must be  
false to branch on a false condition.  
5-30  
SCSI SCRIPTS Instruction Set  
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Result of  
Bit 19  
Compare Action  
0
0
1
False  
True  
Jump Taken  
No Jump  
True  
No Jump  
Jump Taken  
CD  
Compare Data  
18  
When this bit is set, the first byte received from the SCSI  
data bus (contained in the SCSI First Byte Received  
(SFBR) register) is compared with the Data to be  
Compared Field in the Transfer Control instruction. The  
Wait for Valid Phase bit controls when this compare  
occurs. The Jump if True/False bit determines the  
condition (true or false) to branch on.  
CP  
Compare Phase  
17  
When the LSI53C875A is in Initiator mode, this bit  
controls phase compare operations. When this bit is set,  
the SCSI phase signals (latched by SREQ/) are  
compared to the Phase Field in the Transfer Control  
instruction. If they match, the comparison is true. The  
Wait for Valid Phase bit controls when the compare  
occurs. When the LSI53C875A is operating in Target  
mode and this bit is set it tests for an active SCSI SATN/  
signal.  
WVP  
DCM  
Wait for Valid Phase  
16  
If the Wait for Valid Phase bit is set, the LSI53C875A  
waits for a previously unserviced phase before comparing  
the SCSI phase and data.  
If the Wait for Valid Phase bit is cleared, the LSI53C875A  
Data Compare Mask  
[15:8]  
The Data Compare Mask allows a SCRIPT to test certain  
bits within a data byte. During the data compare, if any  
mask bits are set, the corresponding bit in the SCSI First  
Byte Received (SFBR) data byte is ignored. For instance,  
a mask of 0b01111111 and data compare value of  
0b1XXXXXXX allows the SCRIPTS processor to  
determine whether or not the high order bit is set while  
ignoring the remaining bits.  
Transfer Control Instructions  
5-31  
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DCV  
Data Compare Value  
[7:0]  
This 8-bit field is the data compared against the register.  
These bits are used in conjunction with the Data  
Compare Mask Field to test for a particular data value.  
5.6.2 Second Dword  
31  
0
DMA SCRIPTS Pointer Save (DSPS) Register  
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Jump Address  
This 32-bit field contains the address of the next  
[31:0]  
instruction to fetch when a jump is taken. Once the  
LSI53C875A fetches the instruction from the address  
pointed to by these 32 bits, this address is incremented  
by 4, loaded into the DMA SCRIPTS Pointer (DSP)  
register and becomes the current instruction pointer.  
5.7 Memory Move Instructions  
For Memory Move instructions, bits 5 and 4 (SIOM and DIOM) in the  
DMA Mode (DMODE) register determine whether the source or  
destination addresses reside in memory or I/O space. By setting these  
bits appropriately, data may be moved within memory space, within I/O  
space, or between the two address spaces.  
The Memory Move instruction is used to copy the specified number of  
bytes from the source address to the destination address.  
Allowing the LSI53C875A to perform memory moves frees the system  
processor for other tasks and moves data at higher speeds than available  
from current DMA controllers. Up to 16 Mbytes may be transferred with  
one instruction. There are two restrictions:  
Both the source and destination addresses must start with the same  
address alignment A[1:0]. If the source and destination are not  
aligned, then an illegal instruction interrupt occurs. For the PCI  
Cache Line Size register setting to take effect, the source and  
destination must be the same distance from a cache line boundary.  
5-32  
SCSI SCRIPTS Instruction Set  
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the source address, put into the DMA FIFO and then written out to  
the destination address. The move continues until the byte count  
decrements to zero, then another SCRIPTS is fetched from system  
memory.  
The DMA SCRIPTS Pointer Save (DSPS) and Data Structure Address  
(DSA) registers are additional holding registers used during the Memory  
Move. However, the contents of the Data Structure Address (DSA)  
register are preserved.  
5.7.1 First Dword  
31  
29 28  
25 24 23  
0
x
DMA Command (DCMD) Register  
DMA Byte Counter (DBC) Register  
Transfer Counter (TC) [23:0]  
IT[2:0]  
1
R
NF  
x
1
0
0
0
0
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
IT[2:0]  
Instruction Type - Memory Move  
[31:29]  
The IT bit configuration (110) defines a Memory Move  
Instruction Type.  
R
Reserved  
[28:25]  
These bits are reserved and must be zero. If any of these  
bits are set, an illegal instruction interrupt occurs.  
NF  
No Flush  
24  
When this bit is set, the LSI53C875A performs a Memory  
Move without flushing the prefetch unit. When this bit is  
cleared, the Memory Move instruction automatically  
flushes the prefetch unit. Use the No Flush option if the  
source and destination are not within four instructions of  
the current Memory Move instruction.  
Note:  
This bit has no effect unless the Prefetch Enable bit in the  
DMA Control (DCNTL) register is set. For information on  
SCRIPTS instruction prefetching, see Chapter 2.  
TC[23:0]  
Transfer Counter  
[23:0]  
The number of bytes to transfer is stored in the lower  
24 bits of the first instruction word.  
Memory Move Instructions  
5-33  
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5.7.2 Read/Write System Memory from SCRIPTS  
By using the Memory Move instruction, single or multiple register values  
are transferred to or from system memory.  
Because the LSI53C875A responds to addresses as defined in the Base  
Address Register Zero (I/O) or Base Address Register One (MEMORY)  
registers, it can be accessed during a Memory Move operation if the  
source or destination address decodes to within the chip’s register space.  
If this occurs, the register indicated by the lower seven bits of the address  
is taken as the data source or destination. In this way, register values are  
saved to system memory and later restored, and SCRIPTS can make  
decisions based on data values in system memory.  
The SFBR is not writable using the CPU, and therefore not by a Memory  
Move. However, it can be loaded using SCRIPTS Read/Write operations.  
To load the SFBR with a byte stored in system memory, first move the  
byte to an intermediate LSI53C875A register (for example, a SCRATCH  
register), and then to the SFBR.  
The same address alignment restrictions apply to register access  
operations as to normal memory-to-memory transfers.  
5.7.3 Second Dword  
-
31  
x
0
x
DMA SCRIPTS Pointer Save (DSPS) Register  
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
DSPS Register  
[31:0]  
These bits contain the source address of the Memory  
Move.  
5-34  
SCSI SCRIPTS Instruction Set  
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5.7.4 Third Dword  
31  
0
x
Temporary (TEMP) Register  
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
TEMP Register  
[31:0]  
These bits contain the destination address for the  
Memory Move.  
5.8 Load and Store Instructions  
The Load and Store instructions provide a more efficient way to move  
data from/to memory to/from an internal register in the chip without using  
the normal memory move instruction.  
The Load and Store instructions are represented by two Dword opcodes.  
The first Dword contains the DMA Command (DCMD) and DMA Byte  
Counter (DBC) register values. The second Dword contains the DMA  
SCRIPTS Pointer Save (DSPS) value. This is either the actual memory  
location of where to Load and Store, or the offset from the Data Structure  
Address (DSA), depending on the value of bit 28 (DSA Relative).  
A maximum of 4 bytes may be moved with these instructions. The  
register address and memory address must have the same byte  
alignment, and the count set such that it does not cross Dword  
boundaries. The memory address may not map back to the chip,  
excluding RAM and ROM. If it does, a PCI read/write cycle occurs (the  
data does not actually transfer to/from the chip), and the chip issues an  
interrupt (Illegal Instruction Detected) immediately following.  
Bit A1 Bit A0  
Number of Bytes Allowed to Load and Store  
0
0
1
1
0
1
0
1
One, two, three or four  
One, two, or three  
One or two  
One  
Load and Store Instructions  
5-35  
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The SIOM and DIOM bits in the DMA Mode (DMODE) register determine  
whether the destination or source address of the instruction is in Memory  
space or I/O space, as illustrated in the following table. The Load and  
Store utilizes the PCI commands for I/O read and I/O write to access the  
I/O space.  
Bit  
Source  
Destination  
SIOM (Load)  
Memory  
Register  
Register  
Memory  
5.8.1 First Dword  
31  
29 28 27 26 25 24 23 22  
16 15  
3
0
2
x
0
x
DMA Command (DCMD)  
Register  
DMA Byte Counter (DBC) Register  
R
IT[2:0] DSA  
R
NF LS R  
RA[6:0]  
BC  
x
1
1
1
x
0
0
x
x
0
x
x
x
x
x
x
x
0
0
0
0
0
0
0
0
0
0
0
0
IT[2:0]  
DSA  
These bits should be 0b111, indicating the Load and  
Store instruction.  
[31:29]  
DSA Relative  
Pointer Save (DSPS) is the actual 32-bit memory address  
used to perform the Load and Store to/from. When this  
bit is set, the chip determines the memory address to  
perform the Load and Store to/from by adding the 24-bit  
signed offset value in the DMA SCRIPTS Pointer Save  
(DSPS) to the Data Structure Address (DSA).  
R
Reserved  
[27:26]  
NF  
No Flush (Store instruction only)  
25  
When this bit is set, the LSI53C875A performs a Store  
without flushing the prefetch unit. When this bit is cleared,  
the Store instruction automatically flushes the prefetch  
unit. Use No Flush if the source and destination are not  
within four instructions of the current Store instruction.  
This bit has no effect on the Load instruction.  
5-36  
SCSI SCRIPTS Instruction Set  
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Note:  
This bit has no effect unless the Prefetch Enable bit in the  
DMA Control (DCNTL) register is set.  
LS  
R
Load and Store  
When this bit is set, the instruction is a Load. When  
cleared, it is a Store.  
24  
Reserved  
23  
RA[6:0]  
Register Address  
[22:16]  
A[6:0] selects the register to Load and Store to/from  
within the LSI53C875A.  
R
Reserved  
[15:3]  
[2:0]  
BC  
Byte Count  
This value is the number of bytes to Load and Store.  
5.8.2 Second Dword  
31  
0
x
DMA SCRIPTS Pointer Save (DSPS) Register - Memory I/O Address/DSA Offset  
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Memory I/O Address / DSA Offset  
[31:0]  
This is the actual memory location of where to Load and  
Store, or the offset from the Data Structure Address  
(DSA) register value.  
Load and Store Instructions  
5-37  
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5-38  
SCSI SCRIPTS Instruction Set  
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Chapter 6  
Electrical  
Specifications  
This section specifies the LSI53C875A electrical and mechanical  
Section 6.2, TolerANT Technology Electrical Characteristics”  
Section 6.3, “AC Characteristics”  
Section 6.4, “PCI and External Memory Interface Timing Diagrams”  
Section 6.5, “SCSI Timing Diagrams”  
Section 6.6, “Package Diagrams”  
6.1 DC Characteristics  
This section of the manual describes the LSI53C875A DC  
characteristics. Table 6.1 through Table 6.10 give current and voltage  
specifications.  
LSI53C875A PCI to Ultra SCSI Controller  
6-1  
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Table 6.1  
Symbol  
Absolute Maximum Stress Ratings1  
Parameter  
Min  
Max  
Unit  
Test Conditions  
TSTG  
VDD  
VIN  
Storage temperature  
Supply voltage  
55  
0.5  
150  
4.5  
5.55  
°C  
V
Input voltage  
VSS 0.3  
±=150  
V
SCSI 5 V TolerANT pads  
2
ILP  
Latch-up current  
Electrostatic discharge  
mA  
V
ESD  
2 K  
MIL-STD 883C,  
Method 3015.7  
1. Stresses beyond those listed above may cause permanent damage to the device. These are stress  
ratings only; functional operation of the device at these or any other conditions beyond those  
indicated in the Operating Conditions section of the manual is not implied.  
2. 2 V < VPIN < 8 V.  
Table 6.2  
Symbol Parameter  
Operating Conditions1  
Min  
Max  
Unit  
Test Conditions  
VDD  
IDD  
Supply voltage  
2.97  
3.63  
V
±10%  
Supply current (dynamic)  
Supply current (static)  
200 mA  
1 mA  
mA  
mA  
TA  
Operating free air  
0
70  
°C  
θJA  
Thermal resistance  
(junction to ambient air)  
25.1  
34.7  
°C/W  
160 PQFP  
169 PBGA  
1. Conditions that exceed the operating limits may cause the device to function incorrectly.  
Table 6.3  
Symbol  
Input Capacitance  
Parameter  
Min  
Max  
Unit  
Test Conditions  
CI  
Input capacitance of input pads  
Input capacitance of I/O pads  
7
pF  
pF  
CIO  
15  
6-2  
Electrical Specifications  
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Table 6.4  
Symbol  
Bidirectional Signals—MAD[7:0], MAS/[1:0], MCE/, MOE/, MWE/  
Parameter  
Min  
Max  
Unit  
Test Conditions  
VIH  
VIL  
Input high voltage  
Input low voltage  
Output high voltage  
Output low voltage  
3-state leakage  
2.0  
VSS 0.5  
2.4  
5.25  
0.8  
V
V
4 mA  
4 mA  
VOH  
VOL  
IOZ  
VDD  
0.4  
V
VSS  
V
10  
10  
µA  
µA  
IPULL  
Pull-down current  
12.5  
+50  
Table 6.5  
Symbol  
Bidirectional Signals—GPIO0_FETCH/, GPIO1_MASTER/, GPIO[2:4]  
Parameter  
Min  
Max  
Unit  
Test Conditions  
VIH  
VIL  
Input high voltage  
Input low voltage  
Output high voltage  
Output low voltage  
3-state leakage  
2.0  
VSS 0.5  
2.4  
5.25  
0.8  
V
V
8 mA  
8 mA  
VOH  
VOL  
IOZ  
VDD  
0.4  
V
VSS  
V
10  
10  
µA  
µA  
IPULL  
Pull-down current  
12.5  
+50  
DC Characteristics  
6-3  
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Table 6.6  
Bidirectional Signals—AD[31:0], C_BE[3:0]/, FRAME/, IRDY/, TRDY/,  
DEVSEL/, STOP/, PERR/, PAR  
Symbol Parameter  
Min  
Max  
Unit  
Test Conditions  
VIH  
VIL  
Input high voltage  
0.5 VDD  
VSS  
5.25  
0.3 VDD  
VDD  
V
V
Input low voltage  
Output high voltage  
Output low voltage  
3-state leakage  
16 mA  
16 mA  
VOH  
VOL  
IOZ  
0.9 VDD  
VSS  
V
0.1 VDD  
10  
V
10  
µA  
µA  
IPULL  
Pull-down current  
25  
Table 6.7  
Input Signals—CLK, GNT/, IDSEL, RST/, SCLK, TCK, TDI, TEST_HSC,  
TEST_RST, TMS, TRST/  
Symbol Parameter  
Min  
Max  
Unit  
Test Conditions  
VIH  
VIL  
Input high voltage  
0.5 VDD  
VSS  
5.25  
0.3 VDD  
10  
V
V
Input low voltage  
Input leakage  
IIN  
10  
µA  
µA  
IPULL  
Pull-up current - only on  
TCK, TDI, TEST_HSC,  
TEST_RST, TMS, TRST/  
50  
12.5  
Table 6.8  
Symbol  
Output Signal—TDO  
Parameter  
Min  
Max  
Unit  
Test Conditions  
VOH  
VOL  
IOZ  
Output high voltage  
Output low voltage  
3-state leakage  
2.4  
VSS  
10  
VDD  
0.4  
10  
V
V
4 mA  
4 mA  
µA  
6-4  
Electrical Specifications  
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Table 6.9  
Symbol  
Output Signals—IRQ/, MAC/_TESTOUT, REQ/  
Parameter  
Min  
Max  
Unit  
Test Conditions  
VOH  
VOL  
IOZ  
Output high voltage  
Output low voltage  
3-state leakage  
0.9 VDD  
VSS  
VDD  
0.1 VDD  
10  
V
V
16 mA  
16 mA  
10  
µA  
µA  
IPULL  
Pull-down current - only  
on IRQ/  
50  
12.5  
Table 6.10 Output Signal—SERR/  
Symbol Parameter  
Min  
Max  
Unit  
Test Conditions  
VOL  
IOZ  
Output low voltage  
3-state leakage  
VSS  
0.1 VDD  
10  
V
16 mA  
10  
µA  
6.2 TolerANT Technology Electrical Characteristics  
The LSI53C875A features TolerANT technology, which includes active  
negation on the SCSI drivers and input signal filtering on the SCSI  
receivers. Active negation actively drives the SCSI Request,  
Acknowledge, Data, and Parity signals HIGH rather than allowing them  
to be passively pulled up by terminators. Table 6.11 provides electrical  
characteristics for SE SCSI signals. Figure 6.1 through Figure 6.5  
provide reference information for testing SCSI signals.  
TolerANT Technology Electrical Characteristics  
6-5  
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Table 6.11 TolerANT Technology Electrical Characteristics for SE SCSI Signals  
Symbol Parameter  
Min1  
Max  
Unit  
Test Conditions  
2
VOH  
VOL  
VIH  
VIL  
Output high voltage  
2.0  
VSS  
2.0  
VDD +0.3  
0.5  
V
V
IOH = 7 mA  
Output low voltage  
IOL = 48 mA  
Input high voltage  
VDD +0.3  
0.8  
V
Input low voltage  
VSS 0.3  
0.66  
1.0  
V
Referenced to VSS  
VIK  
Input clamp voltage  
Threshold, HIGH to LOW  
Threshold, LOW to HIGH  
0.77  
1.2  
V
VDD = 4.75; II = 20 mA  
VTH  
VTL  
V
1.4  
1.6  
V
V
TH–VTL Hysteresis  
300  
500  
mV  
mA  
mA  
mA  
2
IOH  
Output high current  
2.5  
24  
VOH = 2.5 V  
VOL = 0.5 V  
IOL  
Output low current  
100  
200  
2
IOSH  
Short-circuit output high current  
625  
Output driving low, pin  
shorted to VDD supply3  
IOSL  
ILH  
Short-circuit output low current  
Input high leakage  
95  
20  
mA  
µA  
µA  
Output driving high, pin  
shorted to VSS supply  
0.5 < VDD < 5.25  
VPIN = 2.7 V  
ILL  
Input low leakage  
20  
0.5 < VDD < 5.25  
VPIN = 0.5 V  
RI  
Input resistance  
20  
15  
MΩ  
pF  
SCSI pins  
PQFP  
CP  
Capacitance per pin  
Rise time, 10% to 90%  
Fall time, 90% to 10%  
2
tR  
4.0  
4.0  
0.15  
0.15  
2
18.5  
18.5  
0.50  
0.50  
ns  
Figure 6.1  
Figure 6.1  
Figure 6.1  
Figure 6.1  
MIL-STD-883C; 3015-7  
tF  
ns  
dVH/dt Slew rate, LOW to HIGH  
dVL/dt Slew rate, HIGH to LOW  
V/ns  
V/ns  
KV  
mA  
ns  
ESD  
Electrostatic discharge  
Latch-up  
100  
20  
Filter delay  
30  
Figure 6.2  
Figure 6.2  
Figure 6.2  
Ultra filter delay  
Extended filter delay  
10  
15  
ns  
40  
60  
ns  
1. These values are guaranteed by periodic characterization; they are not 100% tested on every  
device.  
2. Active negation outputs only: Data, Parity, SREQ/, SACK/.  
3. Single pin only; irreversible damage may occur if sustained for one second.  
6-6  
Electrical Specifications  
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Figure 6.1 Rise and Fall Time Test Condition  
47  
20 pF  
+
2.5 V  
Figure 6.2 SCSI Input Filtering  
t1  
REQ/ or SACK/ Input  
VTH  
Note: t is the input filtering period.  
1
Figure 6.3 Hysteresis of SCSI Receivers  
1.1  
1.3  
1
0
1.5  
1.7  
Input Voltage (Volts)  
TolerANT Technology Electrical Characteristics  
6-7  
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Figure 6.4 Input Current as a Function of Input Voltage  
+40  
+20  
14.4 V  
8.2 V  
0
0.7 V  
HIGH-Z  
OUTPUT  
20  
ACTIVE  
40  
4  
0
4
8
12  
16  
Input Voltage (Volts)  
Figure 6.5 Output Current as a Function of Output Voltage  
0
100  
80  
200  
400  
600  
800  
60  
40  
20  
0
0
1
2
3
4
5
0
1
2
3
4
5
Output Voltage (Volts)  
Output Voltage (Volts)  
6-8  
Electrical Specifications  
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6.3 AC Characteristics  
The AC characteristics described in this section apply over the entire  
range of operating conditions (refer to the DC Characteristics section).  
Chip timings are based on simulation at worst case voltage, temperature,  
and processing. Timing was developed with a load capacitance of 50 pF.  
Table 6.12 and Figure 6.6 provide external clock timing data.  
Table 6.12 External Clock1  
Symbol  
Parameter  
Min  
Max  
Unit  
t1  
Bus clock cycle time  
SCSI clock cycle time (SCLK)2  
CLK LOW time3  
30  
25  
10  
6
DC  
60  
ns  
ns  
t2  
t3  
t4  
ns  
SCLK LOW time3  
CLK HIGH time3  
33  
ns  
12  
10  
1
ns  
SCLK HIGH time3  
CLK slew rate  
33  
ns  
V/ns  
V/ns  
SCLK slew rate  
1
1. Timings are for an external 40 MHz clock.  
2. This parameter must be met to ensure SCSI timings are within specification.  
3. Duty cycle not to exceed 60/40.  
Figure 6.6 External Clock  
t
1
t
3
CLK, SCLK 1.4 V  
t
2
t
4
AC Characteristics  
6-9  
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Table 6.13 and Figure 6.7 provide Reset Input timing data.  
Table 6.13 Reset Input  
Symbol  
Parameter  
Min  
Max  
Unit  
t1  
t2  
t3  
Reset pulse width  
10  
0
tCLK  
ns  
Reset deasserted setup to CLK HIGH  
MAD setup time to CLK HIGH  
(for configuring the MAD bus only)  
20  
ns  
t4  
MAD hold time from CLK HIGH  
(for configuring the MAD bus only)  
20  
ns  
Figure 6.7 Reset Input  
CLK  
t
t
1
2
RST/  
t
t
4
3
1
Valid Data  
MAD  
Note:  
1. When enabled.  
Table 6.14 and Figure 6.8 provide Interrupt Output timing data.  
Table 6.14 Interrupt Output  
Symbol  
Parameter  
Min  
Max  
Unit  
t1  
t2  
t3  
CLK HIGH to IRQ/ LOW  
CLK HIGH to IRQ/ HIGH  
IRQ/ deassertion time  
2
2
3
11  
11  
ns  
ns  
CLK  
6-10  
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Figure 6.8 Interrupt Output  
t
t
t
1
2
3
IRQ/  
CLK  
6.4 PCI and External Memory Interface Timing Diagrams  
Figure 6.9 through Figure 6.32 represent signal activity when the  
LSI53C875A accesses the PCI bus. This section includes timing  
diagrams for access to three groups of memory configurations. The first  
group applies to Target Timing. The second group applies to Initiator  
Timing. The third group applies to External Memory Timing.  
Note:  
Multiple byte accesses to the external memory bus  
increase the read or write cycle by 11 clocks for each  
additional byte.  
Target Timing  
32-Bit Operating Register/SCRIPTS RAM Read  
Initiator Timing  
Nonburst Opcode Fetch, 32-Bit Address and Data  
Burst Opcode Fetch, 32-Bit Address and Data  
Back-to-Back Read, 32-Bit Address and Data  
Back-to-Back Write, 32-Bit Address and Data  
PCI and External Memory Interface Timing Diagrams  
6-11  
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Burst Read, 64-Bit Address and Data  
Burst Write, 32-Bit Address and Data  
Burst Write, 64-Bit Address and 32-Bit Data  
External Memory Timing  
External Memory Read  
External Memory Write  
Normal/Fast Memory (128 Kbytes) Single Byte Access Read  
Cycle  
Normal/Fast Memory (128 Kbytes) Single Byte Access Write  
Cycle  
Nornal/Fast Memory (128 Kbytes) Multiple Byte Access Read  
Cycle  
Normal/Fast Memory (128 Kbytes) Multiple Byte Access Write  
Cycle  
Slow Memory (128 Kbytes) Read Cycle  
Slow Memory (128 Kbytes) Write Cycle  
64 Kbytes ROM Read Cycle  
64 Kbyte ROM Write Cycle  
6-12  
Electrical Specifications  
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6.4.1 Target Timing  
The tables and figures in this section describe target timings.  
Table 6.15 PCI Configuration Register Read  
Symbol  
Parameter  
Min  
Max  
Unit  
t1  
t2  
t3  
Shared signal input setup time  
Shared signal input hold time  
CLK to shared signal output valid  
7
0
ns  
ns  
ns  
11  
Figure 6.9 PCI Configuration Register Read  
CLK  
(Driven by System)  
t
1
FRAME/  
(Driven by System)  
t
2
t
t
3
1
AD  
(Driven by Master-Addr;  
LSI53C875A-Data)  
Addr  
In  
Data Out  
t
t
2
2
t
1
C_BE/  
CMD  
Byte Enable  
(Driven by Master  
)
t3  
t
t
1
2
PAR  
(Driven by Master-Addr;  
LSI53C875A-Data)  
In  
Out  
t
t
2
2
IRDY/  
(Driven by Master)  
t
1
TRDY/  
(Driven by LSI53C875A)  
t
3
STOP/  
(Driven by LSI53C875A)  
DEVSEL/  
(Driven by LSI53C875A)  
t
t
1
3
IDSEL  
(Driven by Master)  
t
2
PCI and External Memory Interface Timing Diagrams  
6-13  
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Table 6.16 PCI Configuration Register Write  
Symbol  
Parameter  
Min  
Max  
Unit  
t1  
t2  
t3  
Shared signal input setup time  
Shared signal input hold time  
CLK to shared signal output valid  
7
0
ns  
ns  
ns  
11  
Figure 6.10 PCI Configuration Register Write  
CLK  
(Driven by System)  
t
1
FRAME/  
(Driven by Master)  
t
t
2
2
t
t
1
1
Addr  
In  
AD  
Data In  
(Driven by Master)  
t
t
2
2
t
1
C_BE/  
(Driven by Master)  
CMD  
Byte Enable  
t
2
t
1
PAR  
(Driven by Master)  
t
2
t
2
t
1
IRDY/  
(Driven by Master)  
TRDY/  
(Driven by LSI53C875A)  
t
3
STOP/  
(Driven by LSI53C875A)  
DEVSEL/  
(Driven by LSI53C875A)  
t
3
t
1
IDSEL  
(Driven by Master)  
t
2
6-14  
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Table 6.17 32-Bit Operating Register/SCRIPTS RAM Read  
Symbol  
Parameter  
Min  
Max  
Unit  
t1  
t2  
t3  
Shared signal input setup time  
Shared signal input hold time  
CLK to shared signal output valid  
7
0
ns  
ns  
ns  
11  
Figure 6.11 32-Bit Operating Register/SCRIPTS RAM Read  
CLK  
(Driven by System)  
t
1
t
2
FRAME/  
(Driven by Master)  
t
3
AD  
(Driven by Master-Addr;  
LSI53C875A-Data)  
Data  
Out  
Addr  
In  
t
2
t
1
C_BE/  
(Driven by Master)  
CMD  
Byte Enable  
t
t
2
2
t
t
1
3
PAR  
(Driven by Master-Addr;  
LSI53C875A-Data)  
In  
t
Out  
t
2
t
2
1
IRDY/  
(Driven by Master)  
t
3
TRDY/  
(Driven by LSI53C875A)  
STOP/  
(Driven by LSI53C875A)  
DEVSEL/  
(Driven by LSI53C875A)  
t
3
PCI and External Memory Interface Timing Diagrams  
6-15  
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Table 6.18 64-Bit Address Operating Register/SCRIPTS RAM Read  
Symbol  
Parameter  
Min  
Max  
Unit  
t1  
t2  
t3  
Shared signal input setup time  
Shared signal input hold time  
CLK to shared signal output valid  
7
0
ns  
ns  
ns  
11  
Figure 6.12 64-Bit Address Operating Register/SCRIPTS RAM Read  
CLK  
(Driven by System)  
t1  
FRAME/  
(Driven by Master)  
t2  
t1  
t3  
AD[31:0]  
(Driven by Master-Addr;  
LSI53C875A-Data)  
Addr  
Lo  
Addr  
Hi  
Data  
Out  
t2  
t1  
t1  
C_BE[3:0]  
(Driven by Master)  
Dual  
Addr CMD  
Bus  
Byte Enable  
t2  
t1  
In  
t3  
Out  
PAR  
(Driven by Master-Addr;  
LSI53C875A-Data)  
In  
t2  
t2  
t1  
IRDY/  
(Driven by Master)  
t3  
TRDY/  
(Driven by LSI53C875A)  
t3  
STOP/  
(Driven by LSI53C875A)  
t3  
DEVSEL/  
(Driven by LSI53C875A)  
6-16  
Electrical Specifications  
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Table 6.19 32-Bit Operating Register/SCRIPTS RAM Write  
Symbol  
Parameter  
Min  
Max  
Unit  
t1  
t2  
t3  
Shared signal input setup time  
Shared signal input hold time  
CLK to shared signal output valid  
7
0
ns  
ns  
ns  
11  
Figure 6.13 32-Bit Operating Register/SCRIPTS RAM Write  
CLK  
(Driven by System)  
t1  
t2  
FRAME/  
(Driven by Master)  
t1  
t2  
t1  
AD  
Addr  
In  
(Driven by Master)  
t2  
t1  
C_BE/  
(Driven by Master)  
CMD  
t2  
t2  
t1  
t1  
PAR  
In  
In  
(Driven by Master)  
t2  
t2  
t2  
IRDY/  
(Driven by Master)  
t1  
t3  
TRDY/  
(Driven by LSI53C875A)  
STOP/  
(Driven by LSI53C875A)  
t3  
DEVSEL/  
(Driven by LSI53C875A)  
PCI and External Memory Interface Timing Diagrams  
6-17  
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Table 6.20 64-Bit Address Operating Register/SCRIPTS RAM Write  
Symbol  
Parameter  
Min  
Max  
Unit  
t1  
t2  
t3  
Shared signal input setup time  
Shared signal input hold time  
CLK to shared signal output valid  
7
0
ns  
ns  
ns  
11  
Figure 6.14 64-Bit Address Operating Register/SCRIPTS RAM Write  
CLK  
(Driven by System)  
t
t
1
2
FRAME/  
(Driven by Master)  
t
t
1
t
1
2
AD  
Addr Addr  
Data In  
(Driven by Master)  
Lo  
Hi  
t
t
2
t
t
1
1
C_BE/  
(Driven by Master)  
Dual  
Addr CMD  
Bus  
Byte Enable  
t
t
2
2
2
t
t
1
1
PAR  
In  
In  
In  
(Driven by Master)  
t
2
t
t
2
1
IRDY/  
(Driven by Master)  
t
2
t
3
TRDY/  
(Driven by LSI53C875A)  
STOP/  
(Driven by LSI53C875A)  
t
3
DEVSEL/  
(Driven by LSI53C875A)  
6-18  
Electrical Specifications  
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6.4.2 Initiator Timing  
The tables and figures in this section describe LSI53C875A initiator  
timings.  
Table 6.21 Nonburst Opcode Fetch, 32-Bit Address and Data  
Symbol  
Parameter  
Min  
Max  
Unit  
t1  
t2  
t3  
t4  
t5  
t6  
t7  
t8  
t9  
t10  
Shared signal input setup time  
Shared signal input hold time  
7
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
CLK to shared signal output valid  
Side signal input setup time  
2
11  
10  
0
Side signal input hold time  
CLK to side signal output valid  
CLK HIGH to GPIO0_FETCH/ LOW  
CLK HIGH to GPIO0_FETCH/ HIGH  
CLK HIGh to GPIO1_MASTER/ LOW  
CLK HIGH to GPIO1_MASTER/ HIGH  
2
12  
20  
20  
20  
20  
PCI and External Memory Interface Timing Diagrams  
6-19  
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Figure 6.15 Nonburst Opcode Fetch, 32-Bit Address and Data  
CLK  
(Driven by System)  
t
t
8
7
GPIO0_FETCH/  
(Driven by LSI53C875A)  
t
t
9
10  
GPIO1_MASTER/  
(Driven by LSI53C875A)  
t
6
REQ/  
(Driven by LSI53C875A)  
t
4
GNT/  
(Driven by Arbiter)  
t
5
FRAME/  
(Driven by LSI53C875A)  
t
3
t
1
Data  
In  
AD  
(Driven by LSI53C875A-  
Addr; Target-Data)  
Addr  
Out  
Addr  
Out  
Data  
In  
t
t
2
3
C_BE/  
(Driven by LSI53C875A)  
BE  
CMD  
CMD  
BE  
t
3
t
t
1
3
PAR  
(Driven by LSI53C875A-  
Addr/ Target-Data)  
t
t
2
3
IRDY/  
(Driven by LSI53C875A)  
t
3
t
1
TRDY/  
(Driven by Target)  
t
2
STOP/  
(Driven by Target)  
t
2
t
1
DEVSEL/  
(Driven by Target)  
6-20  
Electrical Specifications  
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Table 6.22 Burst Opcode Fetch, 32-Bit Address and Data  
Symbol  
Parameter  
Min  
Max  
Unit  
t1  
t2  
t3  
t4  
t5  
t6  
t7  
t8  
t9  
t10  
Shared signal input setup time  
Shared signal input hold time  
7
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
CLK to shared signal output valid  
Side signal input setup time  
2
11  
10  
0
Side signal input hold time  
CLK to side signal output valid  
CLK HIGH to GPIO0_FETCH/ LOW  
CLK HIGH to GPIO0_FETCH/ HIGH  
CLK HIGH to GPIO1_MASTER/ LOW  
CLK HIGH to GPIO1_MASTER/ HIGH  
2
12  
20  
20  
20  
20  
PCI and External Memory Interface Timing Diagrams  
6-21  
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Figure 6.16 Burst Opcode Fetch, 32-Bit Address and Data  
CLK  
(Driven by System)  
t
t
8
7
GPIO0_FETCH/  
(Driven by LSI53C875A)  
t
t
10  
9
GPIO1_MASTER/  
(Driven by LSI53C875A)  
t
6
REQ/  
(Driven by LSI53C875A)  
t
4
GNT/  
(Driven by Arbiter)  
t
5
FRAME/  
(Driven by LSI53C875A)  
t
Data Data  
In In  
3
t
3
AD  
(Driven by LSI53C875A-  
Addr; Target-Data)  
Addr  
Out  
t
1
t
3
t
2
C_BE/  
(Driven by LSI53C875A)  
CMD  
t
BE  
t
3
t
1
3
PAR  
(Driven by LSI53C875A-  
Addr/ Target-Data)  
Out  
In  
In  
t
t
2
3
IRDY/  
(Driven by LSI53C875A)  
t
3
t
1
TRDY/  
(Driven by Target)  
t
2
STOP/  
(Driven by Target)  
t
1
t
2
DEVSEL/  
(Driven by Target)  
6-22  
Electrical Specifications  
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Table 6.23 Back-to-Back Read, 32-Bit Address and Data  
Symbol  
Parameter  
Min  
Max  
Unit  
t1  
t2  
Shared signal input setup time  
Shared signal input hold time  
CLK to shared signal output valid  
Side signal input setup time  
7
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
t3  
2
11  
t4  
10  
0
t5  
Side signal input hold time  
t6  
CLK to side signal output valid  
CLK HIGH to GPIO1_MASTER/ LOW  
CLK HIGH to GPIO1_MASTER/ HIGH  
2
12  
20  
20  
t9  
t10  
PCI and External Memory Interface Timing Diagrams  
6-23  
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Figure 6.17 Back-to-Back Read, 32-Bit Address and Data  
CLK  
(Driven by System)  
GPIO0_FETCH/  
(Driven by LSI53C875A)  
t
t
10  
9
GPIO1_MASTER/  
(Driven by LSI53C875A)  
REQ/  
(Driven by LSI53C875A)  
t
6
t
5
GNT/  
(Driven by Arbiter)  
t
4
t
3
FRAME/  
(Driven by LSI53C875A)  
t
t
1
3
Data In  
Data In  
AD  
(Driven by LSI53C875A-  
Addr; Target-Data)  
Addr  
Out  
Addr  
Out  
t
t
3
2
C_BE/  
(Driven by LSI53C875A)  
CMD  
BE  
CMD  
BE  
t
t
3
1
PAR  
(Driven by LSI53C875A-  
Addr; Target-Data)  
In  
Out  
Out  
In  
t
t
3
2
IRDY/  
(Driven by LSI53C875A)  
t
1
TRDY/  
(Driven by Target)  
t
2
STOP/  
(Driven by Target)  
t
1
DEVSEL/  
(Driven by Target)  
t
2
6-24  
Electrical Specifications  
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Table 6.24 Back-to-Back Write, 32-Bit Address and Data  
Symbol  
Parameter  
Min  
Max  
Unit  
t1  
t2  
Shared signal input setup time  
Shared signal input hold time  
CLK to shared signal output valid  
Side signal input setup time  
7
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
t3  
2
11  
t4  
10  
0
t5  
Side signal input hold time  
t6  
CLK to side signal output valid  
CLK HIGH to GPIO1_MASTER/ LOW  
CLK HIGH to GPIO1_MASTER/ HIGH  
2
12  
20  
20  
t9  
t10  
PCI and External Memory Interface Timing Diagrams  
6-25  
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Figure 6.18 Back-to-Back Write, 32-Bit Address and Data  
CLK  
(Driven by System)  
GPIO0_FETCH/  
(Driven by LSI53C875A)  
t
t
10  
9
GPIO1_MASTER/  
(Driven by LSI53C875A)  
t
6
REQ/  
(Driven by LSI53C875A)  
t
4
GNT/  
(Driven by Arbiter)  
t
5
3
t
FRAME/  
(Driven by LSI53C875A)  
t
t
3
3
AD  
(Driven by LSI53C875A-  
Addr; Target-Data)  
Addr  
Out  
Addr Data  
Out Out  
Data  
Out  
t
t
3
3
C_BE/  
(Driven by LSI53C875A)  
CMD BE  
CMD BE  
t
t
3
3
PAR  
(Driven by LSI53C875A-  
Addr; Target-Data)  
t
3
IRDY/  
(Driven by LSI53C875A)  
t
1
TRDY/  
(Driven by Target)  
t
2
STOP/  
(Driven by Target)  
t
t
2
1
DEVSEL/  
(Driven by Target)  
6-26  
Electrical Specifications  
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Table 6.25 Burst Read, 32-Bit Address and Data  
Symbol  
Parameter  
Min  
Max  
Unit  
t1  
t2  
t3  
Shared signal input setup time  
Shared signal input hold time  
CLK to shared signal output valid  
7
0
2
ns  
ns  
ns  
11  
PCI and External Memory Interface Timing Diagrams  
6-27  
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Figure 6.19 Burst Read, 32-Bit Address and Data  
CLK  
GPIO0_FETCH/  
(Driven by LSI53C875A)  
GPIO1_MASTER/  
(Driven by LSI53C875A)  
REQ/  
(Driven by LSI53C875A)  
GNT/  
(Driven by Arbiter)  
FRAME/  
(Driven by LSI53C875A)  
Data In  
AD  
Addr  
Out  
(Driven by LSI53C875A-  
Addr; Target-Data)  
t
3
C_BE/  
(Driven by LSI53C875A)  
CMD  
BE  
PAR  
(Driven by LSI53C875A-  
Addr; Target-Data)  
Out  
In  
In  
IRDY/  
(Driven by LSI53C875A)  
t
1
TRDY/  
(Driven by Target)  
t
2
STOP/  
(Driven by Target)  
t
2
DEVSEL/  
(Driven by Target)  
6-28  
Electrical Specifications  
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Table 6.26 Burst Read, 64-Bit Address and Data  
Symbol  
Parameter  
Min  
Max  
Unit  
t1  
t2  
Shared signal input setup time  
Shared signal input hold time  
7
0
2
ns  
ns  
ns  
ns  
t3  
CLK to shared signal output valid  
CLK HIGH to GPIO1_MASTER/HIGH  
11  
20  
t10  
PCI and External Memory Interface Timing Diagrams  
6-29  
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Figure 6.20 Burst Read, 64-Bit Address and Data  
CLK  
GPIO0_FETCH/  
(Driven by LSI53C875A)  
t
10  
GPIO1_MASTER/  
(Driven by LSI53C875A)  
REQ/  
(Driven by LSI53C875A)  
GNT/  
(Driven by Arbiter)  
FRAME/  
(Driven by LSI53C875A)  
Data In  
AD[31:0]  
(Addr driven by LSI53C875A-  
Data driven by Target)  
Addr  
Out Hi  
Addr  
Out Lo  
t
3
C_BE[3:0]/  
(Driven by LSI53C875A)  
Dual  
Addr  
Bus  
CMD  
BE  
t
2
PAR  
(Addr drvn by LSI53C875A;  
Data drvn by Target)  
In  
Out  
In  
In  
t
1
IRDY/  
(Driven by LSI53C875A)  
t
1
TRDY/  
(Driven by Target)  
t
2
STOP/  
(Driven by Target)  
t
2
DEVSEL/  
(Driven by Target)  
6-30  
Electrical Specifications  
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Table 6.27 Burst Write, 32-Bit Address and Data  
Symbol  
Parameter  
Min  
Max  
Unit  
t1  
t2  
Shared signal input setup time  
Shared signal input hold time  
7
0
2
ns  
ns  
ns  
ns  
t3  
CLK to shared signal output valid  
CLK HIGH to GPIO1_MASTER/ HIGH  
11  
20  
t10  
PCI and External Memory Interface Timing Diagrams  
6-31  
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Figure 6.21 Burst Write, 32-Bit Address and Data  
CLK  
(Driven by System)  
GPIO0_FETCH/  
(Driven by LSI53C875A)  
t
10  
GPIO1_MASTER/  
(Driven by LSI53C875A)  
REQ/  
(Driven by LSI53C875A)  
GNT/  
(Driven by Arbiter)  
FRAME/  
(Driven by LSI53C875A)  
AD  
Addr  
Out  
Data  
Out  
Data  
Out  
(Driven by LSI53C875A)  
C_BE/  
(Driven by LSI53C875A)  
CMD  
BE  
t
3
PAR  
(Driven by LSI53C875A)  
IRDY/  
(Driven by LSI53C875A)  
t
1
TRDY/  
(Driven by Target)  
t
2
STOP/  
(Driven by Target)  
t
1
DEVSEL/  
(Driven by Target)  
t
2
6-32  
Electrical Specifications  
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Table 6.28 Burst Write, 64-Bit Address and 32-Bit Data  
Symbol  
Parameter  
Min  
Max  
Unit  
t1  
t2  
Shared signal input setup time  
Shared signal input hold time  
7
0
2
ns  
ns  
ns  
ns  
t3  
CLK to shared signal output valid  
CLK HIGH to GPIO1_MASTER/ HIGH  
11  
20  
t10  
PCI and External Memory Interface Timing Diagrams  
6-33  
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Figure 6.22 Burst Write, 64-Bit Address and 32-Bit Data  
CLK  
(Driven by System)  
GPIO0_FETCH/  
(Driven by LSI53C875A)  
t
10  
GPIO1_MASTER/  
(Driven by LSI53C875A)  
REQ/  
(Driven by LSI53C875A)  
GNT/  
(Driven by Arbiter)  
FRAME/  
(Driven by LSI53C875A)  
AD[31:0]  
(Driven by LSI53C875A)  
Addr  
Out Hi  
Data  
Out  
Data  
Out  
Addr  
Out Lo  
C_BE[3:0]/  
(Driven by LSI53C875A)  
Dual  
Addr  
Bus  
CMD  
BE  
BE  
PAR  
(Driven by LSI53C875A)  
t
3
IRDY/  
(Driven by LSI53C875A)  
t
1
TRDY/  
(Driven by Target)  
t
2
STOP/  
(Driven by Target)  
t
2
DEVSEL/  
(Driven by Target)  
t
1
6-34  
Electrical Specifications  
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6.4.3 External Memory Timing  
The tables and figures in this section describe LSI53C875A external  
timings. The External Memory Write timings start on page 6-40.  
Table 6.29 External Memory Read  
Symbol  
Parameter  
Min  
Max  
Unit  
t1  
Shared signal input setup time  
Shared signal input hold time  
CLK to shared signal output valid  
Address setup to MAS/ HIGH  
Address hold from MAS/ HIGH  
MAS/ pulse width  
7
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
t2  
t3  
11  
t11  
t12  
t13  
t14  
t15  
t16  
t17  
t19  
25  
15  
25  
150  
205  
100  
0
MCE/ LOW to data clocked in  
Address valid to data clocked in  
MOE/ LOW to data clocked in  
Data hold from address, MOE/, MCE/ change  
Data setup to CLK HIGH  
5
PCI and External Memory Interface Timing Diagrams  
6-35  
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Figure 6.23 External Memory Read  
1
2
3
4
5
6
7
8
9
CLK  
(Driven by System)  
t1  
FRAME/  
(Driven by Master)  
t2  
t1  
AD  
(Driven by Master-Addr;  
LSI53C875A-Data)  
Addr  
In  
t2  
t1  
C_BE[3:0]/  
(Driven by Master)  
CMD  
t2  
Byte Enable  
t1  
PAR  
(Driven by Master-Addr;  
LSI53C875A-Data)  
In  
t2  
t1  
IRDY/  
(Driven by Master)  
TRDY/  
(Driven by LSI53C875A)  
STOP/  
(Driven by LSI53C875A)  
DEVSEL/  
(Driven by LSI53C875A)  
t3  
MAD  
(Addr driven by LSI53C875A;  
Data driven by Memory)  
Upper  
Address  
Middle  
Address  
Lower  
Address  
t11  
t12  
MAS1/  
(Driven by LSI53C875A)  
t13  
MAS0/  
(Driven by LSI53C875A)  
MCE/  
(Driven by LSI53C875A)  
MOE/  
(Driven by LSI53C875A)  
MWE/  
(Driven by LSI53C875A)  
6-36  
Electrical Specifications  
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Figure 6.23 External Memory Read (Cont.)  
9
10  
11 12  
13  
14  
15  
16  
17 18 19 20  
21  
CLK  
(Driven by System)  
FRAME/  
(Driven by Master)  
t3  
AD  
(Driven by Master-Addr;  
LSI53C875A-Data)  
Data  
Out  
C_BE[3:0]/  
(Driven by Master)  
Byte Enable  
t2  
t3  
PAR  
(Driven by Master-Addr;  
LSI53C875A-Data)  
Out  
t2  
IRDY/  
(Driven by Master)  
t3  
TRDY/  
(Driven by LSI53C875A)  
t3  
STOP/  
(Driven by LSI53C875A)  
DEVSEL/  
(Driven by LSI53C875A)  
t19  
t17  
MAD  
(Addr driven by LSI53C875A;  
Data driven by Memory)  
Data  
In  
Lower  
Address  
MAS1/  
(Driven by LSI53C875A)  
t15  
MAS0/  
(Driven by LSI53C875A)  
t14  
MCE/  
(Driven by LSI53C875A)  
t16  
MOE/  
(Driven by LSI53C875A)  
MWE/  
(Driven by LSI53C875A)  
PCI and External Memory Interface Timing Diagrams  
6-37  
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Table 6.30 External Memory Write  
Symbol  
Parameter  
Min  
Max  
Unit  
t1  
Shared signal input setup time  
Shared signal input hold time  
CLK to shared signal output valid  
Address setup to MAS/ HIGH  
Address hold from MAS/ HIGH  
MAS/ pulse width  
7
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
t2  
t3  
11  
t11  
t12  
t13  
t20  
t21  
t22  
t23  
t24  
t25  
t26  
25  
15  
25  
30  
20  
100  
60  
120  
25  
25  
Data setup to MWE/ LOW  
Data hold from MWE/ HIGH  
MWE/ pulse width  
Address setup to MWE/ LOW  
MCE/ LOW to MWE/ HIGH  
MCE/ LOW to MWE/ LOW  
MWE/ HIGH to MCE/ HIGH  
6-38  
Electrical Specifications  
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The External Memory Write timings start on page 6-40.  
PCI and External Memory Interface Timing Diagrams  
6-39  
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Figure 6.24 External Memory Write  
1
2
3
4
5
6
7
8
9
CLK  
(Driven by System)  
t1  
t2  
FRAME/  
(Driven by Master)  
t1  
t1  
AD  
(Driven by Master-Addr;  
LSI53C875A-Data)  
Addr  
In  
t2  
t1  
C_BE[3:0]/  
(Driven by Master)  
CMD  
t2  
Byte Enable  
t1  
PAR  
(Driven by Master-Addr;  
LSI53C875A-Data)  
In  
t2  
t1  
IRDY/  
(Driven by Master)  
TRDY/  
(Driven by LSI53C875A)  
STOP/  
(Driven by LSI53C875A)  
DEVSEL/  
(Driven by LSI53C875A)  
t3  
MAD  
(Addr driven by LSI53C875A;  
Data driven by Memory)  
Higher  
Address  
Middle  
Address  
Lower  
Address  
t11  
t12  
MAS1/  
(Driven by LSI53C875A)  
t13  
MAS0/  
(Driven by LSI53C875A)  
MCE/  
(Driven by LSI53C875A)  
MOE/  
(Driven by LSI53C875A)  
MWE/  
(Driven by LSI53C875A)  
6-40  
Electrical Specifications  
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Figure 6.24 External Memory Write (Cont.)  
9
10 11  
12  
13  
14  
15  
16 17  
18  
19 20 21  
CLK  
(Driven by System)  
FRAME/  
(Driven by Master)  
t2  
AD  
(Driven by Master-Addr;  
LSI53C875A-Data)  
Data In  
C_BE[3:0]/  
(Driven by Master)  
Byte Enable  
t2  
t1  
In  
PAR  
(Driven by Master-Addr;  
LSI53C875A-Data)  
t2  
t2  
IRDY/  
(Driven by Master)  
t3  
TRDY/  
(Driven by LSI53C875A)  
t3  
STOP/  
(Driven by LSI53C875A)  
DEVSEL/  
(Driven by LSI53C875A)  
MAD  
(Addr driven by LSI53C875A;  
Data driven by Memory)  
Lower  
Address  
Data Out  
MAS1/  
(Driven by LSI53C875A)  
MAS0/  
(Driven by LSI53C875A)  
t24  
MCE/  
(Driven by LSI53C875A)  
t25  
MOE/  
(Driven by LSI53C875A)  
t26  
t20  
t21  
MWE/  
(Driven by LSI53C875A)  
t22  
t23  
PCI and External Memory Interface Timing Diagrams  
6-41  
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Table 6.31 Normal/Fast Memory (=128 Kbytes) Single Byte Access Read Cycle  
Symbol  
Parameter  
Min  
Max  
Unit  
t11  
t12  
t13  
t14  
t15  
t16  
t17  
t18  
t19  
Address setup to MAS/ HIGH  
Address hold from MAS/ HIGH  
MAS/ pulse width  
25  
15  
25  
150  
205  
100  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
MCE/ LOW to data clocked in  
Address valid to data clocked in  
MOE/ LOW to data clocked in  
Data hold from address, MOE/, MCE/ change  
Address out from MOE/, MCE/ HIGH  
Data setup to CLK HIGH  
50  
5
Figure 6.25 Normal/Fast Memory (=128 Kbytes) Single Byte Access Read Cycle  
CLK  
t
19  
MAD  
(Addr driven by LSI53C875A;  
Data driven by memory)  
Higher  
Address  
3.  
1.  
2.  
t
t
11  
12  
t
17  
MAS1/  
(Driven by LSI53C875A)  
t
15  
t
13  
MAS0/  
(Driven by LSI53C875A)  
t
14  
MCE/  
(Driven by LSI53C875A)  
t
t
16  
18  
MOE/  
(Driven by LSI53C875A)  
MWE/  
(Driven by LSI53C875A)  
1. Middle Address  
2. Lower Address 3. Valid Read Data  
6-42  
Electrical Specifications  
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Table 6.32 Normal/Fast Memory (=128 Kbytes) Single Byte Access Write Cycle  
Symbol  
Parameter  
Min  
Max  
Unit  
t11  
t12  
t13  
t20  
t21  
t22  
t23  
t24  
t25  
t26  
Address setup to MAS/ HIGH  
Address hold from MAS/ HIGH  
MAS/ pulse width  
25  
15  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
25  
Data setup to MWE/ LOW  
Data hold from MWE/ HIGH  
MWE/ pulse width  
30  
20  
100  
60  
Address setup to MWE/ LOW  
MCE/ LOW to MWE/ HIGH  
MCE/ LOW to MWE/ LOW  
MWE/ HIGH to MCE/ HIGH  
120  
25  
25  
Figure 6.26 Normal/Fast Memory (=128 Kbytes) Single Byte Access Write Cycle  
CLK  
MAD  
Higher  
Valid Write Data  
1.  
2.  
(Driven by LSI53C875A)  
Address  
t
11  
t
12  
MAS1/  
(Driven by LSI53C875A)  
t
23  
t
13  
MAS0/  
(Driven by LSI53C875A)  
t
24  
MCE/  
(Driven by LSI53C875A)  
t
26  
t
25  
MOE/  
t
21  
(Driven by LSI53C875A)  
t
20  
t
22  
MWE/  
(Driven by LSI53C875A)  
1. Middle Address  
2. Lower Address  
PCI and External Memory Interface Timing Diagrams  
6-43  
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Figure 6.27 Normal/Fast Memory (=128 Kbytes) Multiple Byte Access Read Cycle  
0
2
4
6
8
10  
12  
14  
16 17  
CLK  
(Driven by System)  
FRAME/  
(Driven by Master)  
Addr In  
CMD  
AD  
(Driven by LSI53C875A-  
Master-Addr; Data)  
C_BE[3:0]/  
(Driven by Master)  
Byte Enable  
PAR  
(Driven by LSI53C875A-  
Master-Addr; Data)  
In  
IRDY/  
(Driven by Master)  
TRDY/  
(Driven by LSI53C875A)  
STOP/  
(Driven by LSI53C875A)  
DEVSEL/  
(Driven by LSI53C875A)  
MAD  
(Addr Driven by LSI53C875A;  
Data driven by Memory)  
Upper  
Address  
Middle  
Address Address  
Lower  
MAS1/  
(Driven by LSI53C875A)  
MAS0/  
(Driven by LSI53C875A)  
MCE/  
(Driven by LSI53C875A)  
MOE/  
(Driven by LSI53C875A)  
MWE/  
(Driven by LSI53C875A)  
6-44  
Electrical Specifications  
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Figure 6.27 Normal/Fast Memory (=128 Kbytes) Multiple Byte Access Read Cycle  
(Cont.)  
15 16  
18  
20  
22  
24  
26  
28  
30  
32  
CLK  
(Driven by System)  
FRAME/  
(Driven by Master)  
Data In  
AD  
(Driven by LSI53C875A-  
Master-Addr; Data)  
C_BE[3:0]/  
(Driven by Master)  
Byte Enable  
PAR  
(Driven by LSI53C875A-  
Master-Addr; Data)  
Out  
IRDY/  
(Driven by Master)  
TRDY/  
(Driven by LSI53C875A)  
STOP/  
(Driven by LSI53C875A)  
DEVSEL/  
(Driven by LSI53C875A)  
Data In  
Data In  
MAD  
(Addr Driven by LSI53C875A;  
Data driven by Memory)  
Lower  
Address  
MAS1/  
(Driven by LSI53C875A)  
MAS0/  
(Driven by LSI53C875A)  
MCE/  
(Driven by LSI53C875A)  
MOE/  
(Driven by LSI53C875A)  
MWE/  
(Driven by LSI53C875A)  
PCI and External Memory Interface Timing Diagrams  
6-45  
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Figure 6.28 Normal/Fast Memory (=128 Kbytes) Multiple Byte Access Write Cycle  
0
2
4
6
8
10  
12  
14  
CLK  
(Driven by System)  
FRAME/  
(Driven by Master)  
Addr In  
CMD  
AD  
(Driven by Master-Addr;  
LSI53C875A-Data)  
Data In  
C_BE[3:0]/  
(Driven by Master)  
Byte Enable  
PAR  
(Driven by Master-Addr;  
LSI53C875A-Data)  
In  
IRDY/  
(Driven by Master)  
TRDY/  
(Driven by LSI53C875A)  
STOP/  
(Driven by LSI53C875A)  
DEVSEL/  
(Driven by LSI53C875A)  
Upper  
Address  
Middle  
Address Address  
Lower  
MAD  
(Driven by LSI53C875A)  
MAS1/  
(Driven by LSI53C875A)  
MAS0/  
(Driven by LSI53C875A)  
MCE/  
(Driven by LSI53C875A)  
MOE/  
(Driven by LSI53C875A)  
MWE/  
(Driven by LSI53C875A)  
6-46  
Electrical Specifications  
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Figure 6.28 Normal/Fast Memory (=128 Kbytes) Multiple Byte Access Write Cycle  
(Cont.)  
15 16  
18  
20  
22  
24  
26  
28  
30  
32  
CLK  
(Driven by System)  
FRAME/  
(Driven by Master)  
AD  
(Driven by Master-Addr;  
LSI53C875A-Data)  
Data In  
C_BE[3:0]/  
(Driven by Master)  
Byte Enable  
PAR  
(Driven by Master-Addr;  
LSI53C875A-Data)  
In  
IRDY/  
(Driven by Master)  
TRDY/  
(Driven by LSI53C875A)  
STOP/  
(Driven by LSI53C875A)  
DEVSEL/  
(Driven by LSI53C875A)  
Lower  
Address  
MAD  
Data Out  
Data Out  
(Driven by LSI53C875A;  
MAS1/  
(Driven by LSI53C875A)  
MAS0/  
(Driven by LSI53C875A)  
MCE/  
(Driven by LSI53C875A)  
MOE/  
(Driven by LSI53C875A)  
MWE/  
(Driven by LSI53C875A)  
PCI and External Memory Interface Timing Diagrams  
6-47  
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Table 6.33 Slow Memory (=128 Kbytes) Read Cycle  
Symbol  
Parameter  
Min  
Max  
Unit  
t11  
t12  
t13  
t14  
t15  
t16  
t17  
t18  
t19  
Address setup to MAS/ HIGH  
Address hold from MAS/ HIGH  
MAS/ pulse width  
25  
15  
25  
150  
205  
100  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
MCE/ LOW to data clocked in  
Address valid to data clocked in  
MOE/ LOW to data clocked in  
Data hold from address, MOE/, MCE/ change  
Address out from MOE/, MCE/ HIGH  
Data setup to CLK HIGH  
50  
5
Figure 6.29 Slow Memory (=128 Kbytes) Read Cycle  
CLK  
Valid Read Data  
t
17  
MAD  
Higher  
Address  
Middle  
Address Address  
Lower  
(Address driven by LSI53C875A;  
Data driven by Memory)  
t
t
12  
19  
t
11  
MAS1/  
(Driven by LSI53C875A)  
t
15  
t
13  
MAS0/  
(Driven by LSI53C875A)  
t
14  
MCE/  
(Driven by LSI53C875A)  
t
t
18  
16  
MOE/  
(Driven by LSI53C875A)  
MWE/  
(Driven by LSI53C875A)  
6-48  
Electrical Specifications  
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Table 6.34 Slow Memory (128 Kbytes) Write Cycle  
Symbol  
Parameter  
Min  
Max  
Unit  
t11  
t12  
t13  
t20  
t21  
t22  
t23  
t24  
t25  
t26  
Address setup to MAS/ HIGH  
Address hold from MAS/ HIGH  
MAS/ pulse width  
25  
15  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
25  
Data setup to MWE/ LOW  
Data hold from MWE/ HIGH  
MWE/ pulse width  
30  
20  
100  
60  
Address setup to MWE/ LOW  
MCE/ LOW to MWE/ HIGH  
MCE/ LOW to MWE/ LOW  
MWE/ HIGH to MCE/ HIGH  
120  
25  
25  
Figure 6.30 Slow Memory (=128 Kbytes) Write Cycle  
CLK  
MAD  
Higher  
Address  
Middle  
Address Address  
Lower  
Valid Write Data  
(Driven by LSI53C875A)  
t
12  
t
11  
MAS1/  
(Driven by LSI53C875A)  
t
13  
MAS0/  
(Driven by LSI53C875A)  
t
24  
MCE/  
(Driven by LSI53C875A)  
t
t
25  
26  
MOE/  
(Driven by LSI53C875A)  
t
21  
t
t
22  
20  
MWE/  
(Driven by LSI53C875A)  
t
23  
PCI and External Memory Interface Timing Diagrams  
6-49  
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Table 6.35 =64 Kbytes ROM Read Cycle  
Symbol  
Parameter  
Min  
Max  
Unit  
t11  
t12  
t13  
t14  
t15  
t16  
t17  
t18  
t19  
Address setup to MAS/ HIGH  
Address hold from MAS/ HIGH  
MAS/ pulse width  
25  
15  
25  
150  
205  
100  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
MCE/ LOW to data clocked in  
Address valid to data clocked in  
MOE/ LOW to data clocked in  
Data hold from address, MOE/, MCE/ change  
Address out from MOE/, MCE/ HIGH  
Data setup to CLK HIGH  
50  
5
Figure 6.31 64 Kbytes ROM Read Cycle  
CLK  
t
17  
MAD  
Valid  
Read  
Data  
Higher  
Address  
Lower  
Address  
(Address driven by LSI53C875A;  
Data driven by Memory)  
t
12  
t
19  
t
11  
MAS1/  
(Driven by LSI53C875A)  
t
15  
t
13  
MAS0/  
(Driven by LSI53C875A)  
t
t
14  
18  
MCE/  
(Driven by LSI53C875A)  
t
16  
MOE/  
(Driven by LSI53C875A)  
MWE/  
(Driven by LSI53C875A)  
6-50  
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Table 6.36 =64 Kbyte ROM Write Cycle  
Symbol  
Parameter  
Min  
Max  
Unit  
t11  
t12  
t13  
t20  
t21  
t22  
t23  
t24  
t25  
t26  
Address setup to MAS/ HIGH  
Address hold from MAS/ HIGH  
MAS/ pulse width  
25  
15  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
25  
Data setup to MWE/ LOW  
Data hold from MWE/ HIGH  
MWE/ pulse width  
30  
20  
100  
60  
Address setup to MWE/ LOW  
MCE/ LOW to MWE/ HIGH  
MCE/ LOW to MWE/ LOW  
MWE/ HIGH to MCE/ HIGH  
120  
25  
25  
Figure 6.32 64 Kbyte ROM Write Cycle  
CLK  
MAD  
Higher  
Address  
Lower  
Address  
Valid Write Data  
(Driven by LSI53C875A)  
t
12  
t
11  
MAS1/  
(Driven by LSI53C875A)  
t
13  
MAS0/  
(Driven by LSI53C875A)  
t
24  
MCE/  
(Driven by LSI53C875A)  
t
t
26  
t
25  
MOE/  
(Driven by LSI53C875A)  
t
21  
20  
MWE/  
(Driven by LSI53C875A)  
t
t
22  
23  
PCI and External Memory Interface Timing Diagrams  
6-51  
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6.5 SCSI Timing Diagrams  
The tables and diagrams in this section describe the LSI53C875A SCSI  
timings.  
Table 6.37 Initiator Asynchronous Send  
Symbol  
Parameter  
Min  
Max  
Unit  
t1  
t2  
t3  
t4  
SACK/ asserted from SREQ/ asserted  
SACK/ deasserted from SREQ/ deasserted  
Data setup to SACK/ asserted  
5
5
ns  
ns  
ns  
ns  
55  
0
Data hold from SREQ/ deasserted  
Figure 6.33 Initiator Asynchronous Send  
SREQ/  
n + 1  
t
t
1
2
n + 1  
SACK/  
n
t
t
3
4
SD[15:0]/  
SDP[1:0]/  
Valid n  
Valid n + 1  
6-52  
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Table 6.38 Initiator Asynchronous Receive  
Symbol  
Parameter  
Min  
Max  
Unit  
t1  
t2  
t3  
t4  
SACK/ asserted from SREQ/ asserted  
SACK/ deasserted from SREQ/ deasserted  
Data setup to SREQ/ asserted  
5
5
0
0
ns  
ns  
ns  
ns  
Data hold from SACK/ asserted  
Figure 6.34 Initiator Asynchronous Receive  
SREQ/  
SACK/  
n
n + 1  
t
t
2
1
n
n + 1  
t
t
4
3
SD[15:0]/,  
SDP[1:0]/  
Valid n  
Valid n + 1  
SCSI Timing Diagrams  
6-53  
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Table 6.39 Target Asynchronous Send  
Symbol  
Parameter  
Min  
Max  
Unit  
t1  
t2  
t3  
t4  
SREQ/ deasserted from SACK/ asserted  
SREQ/ asserted from SACK/ deasserted  
Data setup to SREQ/ asserted  
5
5
ns  
ns  
ns  
ns  
55  
0
Data hold from SACK/ asserted  
Figure 6.35 Target Asynchronous Send  
SREQ/  
SACK/  
n
n + 1  
t
t
2
1
n
n + 1  
t
t
4
3
SD[15:0]/,  
SDP[1:0]/  
Valid n  
Valid n + 1  
6-54  
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Table 6.40 Target Asynchronous Receive  
Symbol  
Parameter  
Min  
Max  
Unit  
t1  
t2  
t3  
t4  
SREQ/ deasserted from SACK/ asserted  
SREQ/ asserted from SACK/ deasserted  
Data setup to SACK/ asserted  
5
5
0
0
ns  
ns  
ns  
ns  
Data hold from SREQ/ deasserted  
Figure 6.36 Target Asynchronous Receive  
SREQ/  
SACK/  
n
n + 1  
t
t
2
1
n
n + 1  
t
t
4
3
SD[15:0]/,  
SDP[1:0]/  
Valid n  
Valid n + 1  
Table 6.41 SCSI-1 Transfers (5.0 Mbytes)  
Symbol  
Parameter  
Min  
Max  
Unit  
t1  
t2  
t1  
t2  
t3  
t4  
t5  
t6  
Send SREQ/ or SACK/ assertion pulse width  
Send SREQ/ or SACK/ deassertion pulse width  
Receive SREQ/ or SACK/ assertion pulse width  
80  
80  
70  
70  
24  
54  
14  
24  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Receive SREQ/ or SACK/ deassertion pulse width  
Send data setup to SREQ/ or SACK/ asserted  
Send data hold from SREQ/ or SACK/ asserted  
Receive data setup to SREQ/ or SACK/ asserted  
Receive data hold from SREQ/ or SACK/ asserted  
SCSI Timing Diagrams  
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Table 6.42 SCSI-2 Fast Transfers 10.0 Mbytes (8-Bit Transfers) or 20.0 Mbytes  
(16-Bit Transfers) 40 MHz Clock  
Symbol  
Parameter  
Min  
Max  
Unit  
t1  
t2  
t1  
t2  
t3  
t4  
t5  
t6  
Send SREQ/ or SACK/ assertion pulse width  
Send SREQ/ or SACK/ deassertion pulse width  
Receive SREQ/ or SACK/ assertion pulse width  
Receive SREQ/ or SACK/ deassertion pulse width  
Send data setup to SREQ/ or SACK/ asserted  
Send data hold from SREQ/ or SACK/ asserted  
Receive data setup to SREQ/ or SACK/ asserted  
Receive data hold from SREQ/ or SACK/ asserted  
30  
30  
22  
22  
24  
34  
14  
24  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Table 6.43 Ultra SCSI Transfers 20.0 Mbytes (8-Bit Transfers) or  
40.0 Mbytes (16-Bit Transfers) Quadrupled 40 MHz Clock1, 2  
Symbol  
Parameter  
Min  
Max  
Unit  
t1  
t2  
t1  
t2  
t3  
t4  
t5  
t6  
Send SREQ/ or SACK/ assertion pulse width  
Send SREQ/ or SACK/ deassertion pulse width  
Receive SREQ/ or SACK/ assertion pulse width  
Receive SREQ/ or SACK/ deassertion pulse width  
Send data setup to SREQ/ or SACK/ asserted  
Send data hold from SREQ/ or SACK/ asserted  
Receive data setup to SREQ/ or SACK/ asserted  
Receive data hold from SREQ/ or SACK/ asserted  
15  
15  
11  
11  
17  
6
ns  
ns  
ns  
ns  
ns  
ns  
ns  
11  
1. Transfer period bits (bits [6:4] in the SCSI Transfer (SXFER) register) are set to zero and the Extra  
Clock Cycle of Data Setup bit (bit 7 in SCSI Control One (SCNTL1)) is set.  
2. During Ultra SCSI transfers, the value of the Extend REQ/ACK Filtering bit (SCSI Test Two  
(STEST2), bit 1) has no effect.  
6-56  
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Figure 6.37 Initiator and Target Synchronous Transfer  
t
t
2
1
SREQ/  
or SACK/  
n
n + 1  
t
t
4
3
Send Data  
SD[15:0]/, SDP[1:0]/  
Valid n  
Valid n + 1  
Valid n + 1  
t
5
t
6
Receive Data  
SD[15:0]/,  
Valid n  
SDP[1:0]/  
SCSI Timing Diagrams  
6-57  
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6.6 Package Diagrams  
This section of the manual has a package drawing and pinout for both  
the PQFP and BGA.  
Figure 6.38 LSI53C875A 160-Pin PQFP Mechanical Drawing  
Important:  
This drawing may not be the latest version. For board layout and manufacturing, obtain the  
most recent engineering drawings from your LSI Logic marketing representative by  
requesting the outline drawing for package code P3.  
6-58  
Electrical Specifications  
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Figure 6.38 160-pin PQFP (P3) Mechanical Drawing (Sheet 2 of 2)  
Important:  
This drawing may not be the latest version. For board layout and manufacturing, obtain the  
most recent engineering drawings from your LSI Logic marketing representative by  
requesting the outline drawing for package code P3.  
Package Diagrams  
6-59  
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Table 6.44 160 PQFP Pin List by Location  
Signal  
Pin  
Signal  
Pin  
41  
Signal  
Pin  
Signal  
Pin  
C_BE[3]/  
IDSEL  
PCI_AD[23]  
VSSIO  
PCI_AD[22]  
PCI_AD[21]  
PCI_AD[20]  
VDDIO  
PCI_AD[19]  
VSSIO  
PCI_AD[18]  
PCI_AD[17]  
PCI_AD[16]  
VSSIO  
1
2
PCI_AD[6]  
VSSIO  
NC  
NC  
81  
82  
NC  
NC  
121  
122  
123  
124  
125  
126  
127  
128  
129  
130  
131  
132  
133  
134  
135  
136  
137  
138  
139  
140  
141  
142  
143  
144  
145  
146  
147  
148  
149  
150  
151  
152  
153  
154  
155  
156  
157  
158  
159  
160  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
76  
3
PCI_AD[5]  
PCI_AD[4]  
VDDIO  
PCI_AD[3]  
PCI_AD[2]  
VSSIO  
VDDCORE  
VDDSCSI  
SD[11]/  
SD[10]/  
SD[9]/  
VSSIO  
SD[8]/  
IO/  
83  
VSSIO  
NC  
4
84  
5
85  
NC  
6
86  
TEST_HSC/  
TEST_RST/  
VDDIO  
VDDA  
7
87  
8
88  
9
PCI_AD[1]  
PCI_AD[0]  
VDDCORE  
IRQ/  
GPIO[0]  
GPIO[1]  
VSSCORE  
SCLK  
TMS/  
TDO/  
MAD[7]  
MAD[6]  
MAD[5]  
MAD[4]  
VDDIO  
MAD[3]  
MAD[2]  
MAD[1]  
MAD[0]  
GPIO[2]  
VSSIO  
89  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
90  
TCK  
REQ/  
CD/  
VSSSIO  
SEL/  
MSG/  
RST/  
ACK/  
BSY/  
VSSIO  
ATN/  
91  
TRST/  
92  
VSSA  
93  
VSSIO  
NC  
94  
C_BEN[2]  
FRAME/  
IRDY/  
95  
NC  
96  
MASN[1]/  
MASN[0]/  
VDDIO  
MEW/  
97  
VSSIO  
TRDY/  
98  
99  
DEVSEL/  
VDDIO  
100  
101  
102  
103  
104  
105  
106  
107  
108  
109  
110  
111  
112  
113  
114  
115  
116  
117  
118  
119  
120  
MOE/  
SDP[0]/  
SD[7]/  
SD[6]/  
VSSIO  
SD[5]/  
SD[4]/  
SD[3]/  
SD[2]/  
VSSIO  
SD[1]/  
SD[0]/  
SDP[1]/  
SD[15]/  
VSSIO  
SD[14]/  
SD[13]/  
SD[12]/  
VDDIO  
NC  
MCE/  
STOP/  
TDI  
VSSIO  
SERR/  
RST/  
PERR/  
PAR  
CLK  
C_BEN[1]/  
VSSIO  
VSSCORE  
GNT/  
PCI_AD[15]  
PCI_AD[14]  
PCI_AD[13]  
VSSIO  
REQ/  
VDDCORE  
PCI_AD[31]  
PCI_AD[30]  
VSSIO  
PCI_AD[29]  
PCI_AD[28]  
VDDIO  
PCI_AD[27]  
PCI_AD[26]  
VSSIO  
PCI_AD[25]  
PCI_AD[24]  
GPIO[3]  
GPIO[4]  
NC1  
PCI_AD[12]  
VDDIO  
PCI_AD[11]  
PCI_AD[10]  
PCI_AD[9]  
VSSIO  
PCI_AD[8]  
C_BEN[0]/  
PCI_AD[7]  
NC  
VDDIO  
NC  
NC  
MACN_TESTOUT 77  
NC  
VSSIO  
VSSCORE  
78  
79  
80  
NC  
1. NC pins are not connected.  
6-60  
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Figure 6.39 169-Pin BGA Mechanical Drawing  
Important:  
This drawing may not be the latest version. For board layout and manufacturing, obtain the  
most recent engineering drawings from your LSI Logic marketing representative by  
requesting the outline drawing for package code GV.  
Package Diagrams  
6-61  
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Table 6.45 169 BGA Pin List by Location  
Signal  
Pin  
Signal  
Pin  
Signal  
Pin  
Signal  
Pin  
C_BE[3]/  
PCI_AD[24]  
PCI_AD[27]  
PCI_AD[29]  
VDDCORE  
CLK  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
A9  
A10  
A11  
A12  
A13  
B1  
B2  
B3  
B4  
B5  
B6  
B7  
PCI_AD[20]D3  
PCI_AD[25]  
VDDIO  
GNT/  
TDI  
NC  
SD[6]G9  
SD[7]  
VSSIO  
ATN/  
SDP[0]  
PAR  
PERR/  
C_BE[1]/  
NC  
PCI_AD[15]  
PCI_AD[12]  
NC  
VSSIO  
SIO  
K12  
D4  
D5  
D6  
D7  
D8  
G10  
G11  
G12  
G13  
H1  
H2  
H3  
H4  
H5  
H6  
H8  
H9  
H10  
H11  
H12  
H13  
J1  
K13  
PCI_AD[9]  
PCI_AD[8]  
PCI_AD[4]  
PCI_AD[2]  
VDDCORE  
VSSCORE  
MAD[7]  
MAD[1]  
GPIO[4]  
MAC_TESTOUT/ L10  
VDDIO  
VDDCORE  
SD[10]  
PCI_AD[7]  
NC  
PCI_AD[5]  
NC  
L1  
L2  
L3  
L4  
L5  
L6  
L7  
L8  
L9  
MCE/  
VDDA  
NC  
D9  
MAS[0]/  
VSSIO  
TCK  
D10  
D11  
D12  
D13  
E1  
E2  
E3  
E4  
E5  
E6  
E7  
SD[12]  
VSSIO  
SD[15]  
PCI_AD[16]  
PCI_AD[17]  
PCI_AD[18]  
PCI_AD[19]  
PCI_AD[22]  
REQ/  
TEST_HSC/  
NC1  
NC  
IDSEL  
NC  
NC  
PCI_AD[28]  
PCI_AD[31]  
RST/  
SBSY  
SSEL  
SMSG  
SRST  
L11  
L12  
L13  
M1  
M2  
M3  
SACK  
SERR/  
VDDIO  
NC  
PCI_AD[14]  
PCI_AD[13]  
NC  
E8  
E9  
J2  
J3  
M4  
M5  
MOE/  
IRQ/  
MAS[1]/  
VSSA  
VDDIO  
VSSIO  
NC  
B8  
B9  
SD[14]  
SD[0]  
SD[1]  
VSSIO  
IRDY/  
FRAME/  
C_BE[2]/  
NC  
NC  
NC  
SDP[1]  
SD[2]  
SD[3]  
SD[4]  
VSSIO  
SD[5]  
VDDIO  
DEVSEL/  
TRDY/  
STOP/  
NC  
E10  
E11  
E12  
E13  
F1  
F2  
F3  
F4  
F5  
F6  
F8  
PCI_AD[10]  
VDDIO  
TDO  
VDDIO  
GPIO[2]  
SD[11]  
SD[8]  
J4  
J5  
J6  
J7  
J8  
J9  
J10  
J11  
J12  
J13  
K1  
K2  
K3  
K4  
K5  
K6  
K7  
K8  
K9  
SCLK  
M6  
M7  
M8  
M9  
M10  
M11  
M12  
M13  
N1  
N2  
N3  
N4  
N5  
N6  
N7  
N8  
N9  
N10  
N11  
N12  
N13  
MAD[6]  
MAD[3]  
GPIO[3]  
VDDIO  
NC  
NC  
NC  
PCI_AD[6]  
NC  
PCI_AD[3]  
PCI_AD[0]  
GPIO[0]  
TMS  
MAD[5]  
MAD[2]  
VSSIO  
NC  
B10  
B11  
B12  
B13  
C1  
C2  
C3  
C4  
C5  
C6  
C7  
C8  
C9  
C10  
C11  
C12  
C13  
D1  
NC  
PCI_AD[21]  
PCI_AD[23]  
NC  
PCI_AD[26]  
PCI_AD[30]  
VSSCORE  
MWE/  
NC  
TRST/  
TEST_RST/  
NC  
SREQ  
SCD  
VSSIO  
VDDIO  
PCI_AD[11]  
NC  
C_BE[0]/  
PCI_AD[1]  
GPIO[1]  
MAD[4]  
MAD[0]  
NC  
F9  
F10  
F11  
F12  
F13  
G1  
G2  
G3  
G4  
G5  
VDDIO  
SD[13]  
NC  
NC  
VSSCORE  
NC  
VSSIO  
SD[9]  
K10  
K11  
VDDPCI1  
D2  
1. NC pins are not connected.  
6-62  
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Appendix A  
Register Summary  
Table A.1  
LSI53C875A PCI Register Map  
Register Name  
Address  
Read/Write Page  
Base Address Register One (MEMORY)  
Base Address Register Two (SCRIPTS RAM)  
Base Address Register Zero (I/O)  
Bridge Support Extensions (PMCSR_BSE)  
Cache Line Size  
0x14–0x17  
0x18–0x1B  
0x10–0x13  
0x46  
Read/Write 4-9  
Read/Write 4-9  
Read/Write 4-3  
Read Only 4-18  
Read/Write 4-8  
Read Only 4-14  
Read Only 4-14  
Read Only 4-15  
0x0C  
Capabilities Pointer  
Capability ID  
0x34  
0x40  
Class Code  
0x09–0x0B  
0x04–0x05  
0x47  
Command  
Data  
Device ID  
0x02–0x03  
0x30–0x33  
0x0E  
Expansion ROM Base Address  
Header Type  
Interrupt Line  
0x3C  
Interrupt Pin  
0x3D  
Latency Timer  
0x0D  
Max_Lat  
0x3F  
Min_Gnt  
0x3E  
Next Item Pointer  
0x41  
LSI53C875A PCI to Ultra SCSI Controller  
A-1  
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Table A.1  
LSI53C875A PCI Register Map (Cont.)  
Register Name  
Address  
Read/Write Page  
0x42–0x43  
0x44–0x45  
0x28–0x2B  
0x35–0x3B  
0x08  
Power Management Control/Status (PMCSR)  
Reserved  
Reserved  
Revision ID (Rev ID)  
Status  
Read/Write 4-5  
Read Only 4-11  
Read Only 4-10  
Read Only 4-2  
0x06–0x07  
0x2E–0x2F  
0x2C–0x2D  
0x00–0x01  
Subsystem ID  
Subsystem Vendor ID  
Vendor ID  
Table A.2  
LSI53C875A SCSI Register Map  
Register Name  
Address  
Read/Write  
Page  
Chip Control 0 (CCNTL0)  
Chip Control 1 (CCNTL1)  
Chip Test Five (CTEST5)  
Chip Test Four (CTEST4)  
Chip Test One (CTEST1)  
Chip Test Six (CTEST6)  
0x3C–0x3F  
0x56  
Read Only  
Read/Write  
Read/Write  
Read/Write  
Read/Write  
Read Only  
Read/Write  
4-73  
4-95  
4-97  
4-60  
4-53  
4-62  
4-56  
0x57  
0x22  
0x21  
0x19  
0x23  
Chip Test Three (CTEST3)  
Chip Test Two (CTEST2)  
Chip Test Zero (CTEST0)  
Cumulative SCSI Byte Count (CSBC)  
Data Structure Address (DSA)  
DMA Byte Counter (DBC)  
0x1B  
0x1A  
0x18  
Read/Write  
Read/Write  
Read/Write  
Read/Write  
4-53  
4-108  
4-47  
4-62  
0xDC–0xDF  
0x10–0x13  
0x24–0x26  
A-2  
Register Summary  
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Table A.2  
LSI53C875A SCSI Register Map (Cont.)  
Register Name  
Address  
Read/Write  
Page  
DMA Command (DCMD)  
0x27  
Read/Write  
Read/Write  
Read/Write  
Read/Write  
Read/Write  
Read/Write  
Read/Write  
Read/Write  
Read Only  
Read/Write  
Read/Write  
Read/Write  
Read/Write  
Read/Write  
Read/Write  
Read/Write  
Read/Write  
Read/Write  
Read/Write  
Read/Write  
Read/Write  
Read/Write  
Read/Write  
Read/Write  
4-63  
DMA Control (DCNTL)  
0x3B  
4-70  
DMA FIFO (DFIFO)  
0x20  
4-57  
DMA Mode (DMODE)  
0x39  
4-69  
0x38  
4-66  
0x28–0x2B  
0xB8–0xBB  
0x2C–0x2F  
0x30–0x33  
0x0C  
4-64  
4-103  
4-64  
DMA Status (DSTAT)  
4-65  
4-39  
DSA Relative Selector (DRS)  
General Purpose (GPREG0)  
General Purpose Pin Control Zero (GPCNTL0)  
Instruction Address (IA)  
0xB4–0xB7  
0xD0–0xD3  
0x07  
4-101  
4-103  
4-106  
4-35  
0x47  
4-82  
4-107  
4-51  
0xD4–0xD7  
0x15  
Interrupt Status One (ISTAT1)  
Interrupt Status Zero (ISTAT0)  
Mailbox One (MBOX1)  
0x14  
4-48  
0x17  
4-52  
Mailbox Zero (MBOX0)  
4-52  
4-81  
4-100  
4-100  
4-104  
4-104  
Memory Move Read Selector (MMRS)  
Memory Move Write Selector (MMWS)  
Phase Mismatch Jump Address 1 (PMJAD1)  
Phase Mismatch Jump Address 2 (PMJAD2)  
0xA0–0xA3  
0xA4–0xA7  
0xC0–0xC3  
0xC4–0xC7  
Register Summary  
A-3  
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Table A.2  
LSI53C875A SCSI Register Map (Cont.)  
Register Name  
Address  
Read/Write  
Page  
Remaining Byte Count (RBC)  
Reserved  
0xC8–0xCB  
0x53  
Read/Write  
4-105  
4-94  
4-99  
4-103  
4-108  
4-108  
4-86  
4-86  
4-70  
4-65  
4-99  
4-99  
4-101  
4-38  
4-98  
4-107  
4-30  
4-23  
4-28  
4-26  
4-20  
4-35  
4-36  
4-93  
4-75  
Reserved  
0x5A–0x5B  
0xBC–0xBF  
0xDB  
Reserved  
Reserved  
Reserved  
0xE0–0xFF  
0x4B  
Response ID One (RESPID1)  
Response ID Zero (RESPID0)  
Scratch Byte Register (SBR)  
Read/Write  
Read/Write  
Read/Write  
Read/Write  
Read/Write  
Read/Write  
Read Only  
Read Only  
Read Only  
Read/Write  
Read/Write  
Read/Write  
Read/Write  
Read/Write  
Read/Write  
Read/Write  
Read Only  
Read/Write  
0x3A  
0x34–0x37  
0x5C–0x5F  
Scratch Registers C–R (SCRATCHC–SCRATCHR) 0x60–0x9F  
SCSI Byte Count (SBC)  
0xA8–0xAB  
0x0B  
0x58–0x59  
0xD8–0xDA  
0x04  
SCSI Chip ID (SCID)  
SCSI Control One (SCNTL1)  
SCSI Control Three (SCNTL3)  
SCSI Control Two (SCNTL2)  
SCSI Control Zero (SCNTL0)  
SCSI Destination ID (SDID)  
SCSI First Byte Received (SFBR)  
SCSI Input Data Latch (SIDL)  
SCSI Interrupt Enable One (SIEN1)  
0x01  
0x03  
0x02  
0x00  
0x06  
0x08  
0x50–0x51  
0x41  
A-4  
Register Summary  
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Table A.2  
LSI53C875A SCSI Register Map (Cont.)  
Register Name  
Address  
Read/Write  
Page  
SCSI Selector ID (SSID)  
0x40  
Read/Write  
Read Only  
Read Only  
Read/Write  
Read/Write  
Read/Write  
Read Only  
Read Only  
Read Only  
Read Only  
Read Only  
Read/Write  
Read/Write  
Read/Write  
Read Only  
Read/Write  
Read/Write  
Read/Write  
Read/Write  
Read/Write  
Read/Write  
4-73  
4-78  
4-76  
4-79  
4-37  
4-94  
4-38  
4-43  
4-46  
4-42  
4-94  
4-88  
4-91  
4-89  
4-87  
4-85  
4-83  
4-31  
4-81  
4-102  
4-57  
4-105  
0x43  
0x42  
0x44  
0x09  
0x54–0x55  
0x0A  
SCSI Status One (SSTAT1)  
SCSI Status Two (SSTAT2)  
SCSI Status Zero (SSTAT0)  
SCSI Test Four (STEST4)  
SCSI Test One (STEST1)  
0x0E  
0x0F  
0x0D  
0x52  
0x4D  
SCSI Test Three (STEST3)  
SCSI Test Two (STEST2)  
0x4F  
0x4E  
SCSI Test Zero (STEST0)  
SCSI Timer One (STIME1)  
SCSI Timer Zero (STIME0)  
SCSI Transfer (SXFER)  
0x4C  
0x49  
0x48  
0x05  
SCSI Wide Residue (SWIDE)  
Static Block Move Selector (SBMS)  
Temporary (TEMP)  
0x45  
0xB0–0xB3  
0x1C–0x1F  
0xCC–0xCF  
Updated Address (UA)  
Register Summary  
A-5  
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A-6  
Register Summary  
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Appendix B  
External Memory  
Interface Diagram  
Examples  
Appendix B has example external memory interface diagrams.  
Figure B.1 16 Kbyte Interface with 200 ns Memory  
MOE/  
MCE/  
OE  
CE  
D[7:0]  
MAD[7:0]  
Bus  
A[7:0]  
V
DD  
A[13:8]  
MAD0  
4.7 K  
D0  
27C128  
8
Q0  
LSI53C875A  
HCT374  
D7  
CK  
Q7  
QE  
MAS0/  
MAS1/  
D0  
HCT374  
Q0  
6
D5  
CK  
Q5  
QE  
Note: MAD[3:1] pulled LOW internally. MAD bus sense logic enabled for 16 Kbyte of slow memory (200 ns  
devices @ 33 MHz).  
LSI53C875A PCI to Ultra SCSI Controller  
B-1  
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Figure B.2 64 Kbyte Interface with 150 ns Memory  
Optional - for Flash Memory only, not  
required for EEPROMS.  
VPP  
+ 12 V  
VPP  
GPIO4  
Control  
MWE/  
WE  
OE  
CE  
MOE/  
MCE/  
D[7:0]  
A[7:0]  
MAD[7:0]  
Bus  
V
DD  
27C512-15/  
28F512-15/  
A[15:8]  
MAD2 4.7 K  
Socket  
LSI53C875A  
D0  
HCT374  
Q0  
8
MAS0/  
MAS1/  
D7  
CK  
Q7  
QE  
D0  
HCT374  
Q0  
6
D7  
CK  
Q7  
QE  
Note: MAD 3, 1, 0 pulled LOW internally. MAD bus sense logic enabled for 64 Kbyte of fast memory (150 ns  
devices @ 33 MHz).  
B-2  
External Memory Interface Diagram Examples  
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Figure B.3 128 Kbytes, 256 Kbytes, 512 Kbytes, or 1 Mbyte Interface with 150 ns  
Memory  
Optional - for Flash Memory only, not  
required for EEPROMS.  
VPP  
+ 12 V  
VPP  
GPIO4  
Control  
MWE/  
MOE/  
WE  
OE  
CE  
MCE/  
D[7:0]  
MAD[7:0]  
Bus  
A[7:0]  
V
DD  
27C020-15/  
28F020-15/  
Socket  
A[15:8]  
MAD3 4.7 K  
A[19:16]  
LSI53C875A  
8
D0  
HCT374  
Q0  
MAS0/  
MAS1/  
D7  
CK  
Q7  
QE  
D0  
HCT374  
Q0  
6
D7  
CK  
Q7  
QE  
MAD[3:0]  
Bus  
D0  
HCT377  
D3  
CK  
Q0  
Q3  
4
E
Note: MAD[2:0] pulled LOW internally. MAD bus sense logic enabled for 128, 256, 512 Kbytes, or 1 Mbyte of fast  
memory (150 ns devices @ 33 MHz). The HCT374s may be replaced with HCT377s.  
External Memory Interface Diagram Examples  
B-3  
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Figure B.4 512 Kbyte Interface with 150 ns Memory  
Optional - for Flash Memory only, not  
required for EEPROMS.  
27C010-15/28F010-15 Sockets  
VPP  
+ 12 V  
VPP  
GPIO4  
Control  
MWE/  
WE  
WE  
WE  
WE  
MOE/  
OE  
OE  
OE  
OE  
D[7:0]  
D[7:0]  
D[7:0]  
D[7:0]  
D[7:0]  
MAD[7:0]  
Bus  
A[7:0]  
V
DD  
A0  
.
.
A0  
.
.
A0  
.
.
A0  
.
.
MAD3  
MAD1  
4.7 K  
4.7 K  
A[15:8]  
.
.
.
.
MAD3  
4.7 K  
LSI53C875A  
D0  
Q0  
8
HCT374  
D7  
CK  
Q7  
QE  
MAS0/  
A16  
CE  
A16  
CE  
A16  
CE  
A16  
CE  
D0  
Q0  
8
HCT374  
D7  
CK  
Q7  
QE  
MAS1/  
MCE/  
MAD[2:0]  
Bus  
Q0  
Q2  
D0  
D2  
3
Y0  
Y1  
Y2  
Y3  
HCT377  
A
B
CK  
E
GB  
HCT139  
Note: MAD2 pulled LOW internally. MAD bus sense logic enabled for 512 Kbytes of slow memory (150 ns  
devices, additional time required for HCT139 @ 33 MHz). The HCT374s may be replaced with HCT377s.  
B-4  
External Memory Interface Diagram Examples  
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Index  
Symbols  
(64TIMOD) 4-97  
(A7) 5-23  
(AAP) 4-22  
(ABRT) 4-40, 4-48  
(ACK) 4-37, 4-39  
(ADB) 4-23  
(ADCK) 4-60  
(ADDER) 4-73  
(AESP) 4-24  
(AIP) 4-43  
(APS) 4-16  
(ARB[1:0]) 4-20  
(ART) 4-87  
(ATN) 4-37, 4-39  
(AWS) 4-90  
(BAR0) 4-9  
(DDIR) 4-54, 4-61  
(BAR1) 4-9  
(BAR2) 4-10  
(BBCK) 4-61  
(BDIS) 4-59  
(BF) 4-40, 4-69  
(BL[1:0]) 4-66  
(BL2) 4-61  
(BO) 4-57  
(BO[9:8]) 4-62  
(BOF) 4-68  
(BSE) 4-17  
(BSY) 4-37, 4-39  
(C_D) 4-37, 4-39, 4-45  
(CC) 4-7  
(CCF[2:0]) 4-29  
(CCNTL0) 4-95  
(CCNTL1) 4-97  
(CHM) 4-26  
(CID) 4-15  
(CIO) 4-54  
(CLF) 4-56  
(CLS) 4-7  
(CLSE) 4-70  
(CM) 4-54  
(EIS) 4-4  
(EMS) 4-4  
(CMP) 4-74, 4-77  
(COM) 4-72  
(EN64DBMV) 4-98  
(EN64TIBMV) 4-98  
(ENC) 4-30, 4-35  
(ENID) 4-38  
(ENNDJ) 4-96  
(ENPMJ) 4-95  
(EPC) 4-22  
(CON) 4-24, 4-49  
(CP) 4-13  
(CSBC) 4-108  
(CSF) 4-92  
(CTEST0) 4-53  
(CTEST1) 4-53  
(CTEST2) 4-54  
(EPER) 4-3  
LSI53C875A PCI to Ultra SCSI Controller  
IX-1  
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(ERBA) 4-12  
(ERL) 4-67  
(MSG) 4-37, 4-39, 4-45  
(ERMP) 4-68  
(ESA) 4-106  
(EWS) 4-29  
(EXC) 4-23  
(EXT) 4-90  
(FBL3) 4-59  
(FE) 4-82  
(FF[3:0]) 4-43  
(FF4) 4-46  
(FFL) 4-53  
(FLF) 4-56  
(FLSH) 4-51  
(FM) 4-56  
(FMT) 4-53  
(GEN) 4-75, 4-79  
(GEN[3:0]) 4-85  
(GENSF) 4-85  
(GPCNTL0) 4-82  
(GPIO) 4-35  
(GPIO[1:0]) 4-83  
(GPIO[4:2]) 4-83  
(GPREG0) 4-35  
(HSC) 4-91  
(HT) 4-8  
(HTH) 4-76, 4-79  
(HTH[3:0]) 4-83  
(HTHBA) 4-85  
(HTHSF) 4-85  
(I/O) 4-9, 4-37, 4-45  
(I_O) 4-39  
(IA) 4-107  
(IARB) 4-24  
(IID) 4-40, 4-69  
(IL) 4-13  
(RST) 4-24, 4-43, 4-75, 4-78  
(ILF) 4-42  
(ILF1) 4-46  
(INTF) 4-49  
(IP) 4-14  
(IRQD) 4-72  
(IRQM) 4-71  
(ISO) 4-88  
(ISTAT0) 4-48  
(ISTAT1) 4-51  
(LDSC) 4-47  
(LEDC) 4-83  
(LOA) 4-43  
(LOCK) 4-94  
(LOW) 4-90  
(LT) 4-8  
(SCRIPTS RAM) 4-10  
(M/A) 4-73  
(MACNTL) 4-81  
(MAN) 4-68  
(MASR) 4-61  
(MBOX0) 4-52  
(MBOX1) 4-52  
(MDPE) 4-40, 4-69  
(ME) 4-82  
(SDP0L) 4-45  
(SDP1) 4-47  
(MEMORY) 4-9  
(MG) 4-14  
(SDU) 4-26  
(SE) 4-3  
(ML) 4-14  
(SEL) 4-37, 4-39, 4-74, 4-77  
(SEL[3:0]) 4-84  
(SEM) 4-49  
(SFBR) 4-36  
(SFS) 4-101  
(MMRS) 4-100  
(MMWS) 4-101  
(MO[4:0]) 4-33  
(MPEE) 4-59  
IX-2  
Index  
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(SGE) 4-74, 4-77  
(SI) 4-51  
(SID) 4-11  
(SIEN0) 4-73  
(SIEN1) 4-75  
(SIGP) 4-49, 4-54  
(SIOM) 4-67  
(SIP) 4-50  
(SIR) 4-40  
(SIST0) 4-76  
(SIST1) 4-78  
(SLB) 4-89  
(SLPAR) 4-79  
(SLPHBEN) 4-27  
(SLPMD) 4-27  
(SLT) 4-87  
(SOCL) 4-37  
(SODL) 4-94  
(SOM) 4-88  
(SOZ) 4-87  
16-bit system (S16) 4-92  
addressing in SCRIPTS 2-19  
SCRIPT selectors 4-99  
table indirect indexing mode (64TIMOD) 4-97  
(SPL1) 4-47  
(SRE) 4-30  
abort operation (ABRT) 4-48  
aborted (ABRT) 4-40, 4-69  
absolute maximum stress ratings 6-2  
AC characteristics 6-9  
adder sum output (ADDER) 4-73  
address/data bus 2-3  
always wide SCSI (AWS) 4-90  
in progress (AIP) 4-43  
mode bits 1 and 0 (ARB[1:0]) 4-20  
priority encoder test (ART) 4-87  
(SRST) 4-48  
(SRTM) 4-59  
(SRUN) 4-51  
(SSAID) 4-87  
(SSE) 4-5  
(SSI) 4-40, 4-69  
(SSID) 4-38  
(SSM) 4-71  
(SST) 4-25  
(SSTAT0) 4-42  
(SSTAT1) 4-43  
(SSTAT2) 4-46  
(START) 4-21  
(STD) 4-72  
(STEST0) 4-87  
(STEST1) 4-88  
(STEST2) 4-89  
(STEST3) 4-91  
(STEST4) 4-94  
(STIME0) 4-83  
(STIME1) 4-85  
(STO) 4-75, 4-79  
(STR) 4-91  
even SCSI parity (force bad parity) (AESP) 4-24  
SATN/ on parity error (AAP) 4-22  
ACK/ signal (ACK) 4-37  
ATN/ signal (ATN) 4-37  
BSY/ signal (BSY) 4-37  
C_D/ signal (C_D) 4-37  
data bus (ADB) 4-23  
I_O/ signal (I/O) 4-37  
MSG/ signal (MSG) 4-37  
REQ/ signal (REQ) 4-37  
RST/ signal (RST) 4-24  
SEL/ signal (SEL) 4-37  
asynchronous SCSI  
(STW) 4-93  
(SWIDE) 4-81  
(SXFER) 4-31  
(SZM) 4-90  
(TE) 4-91  
(TEMP) 4-57  
(TEOP) 4-55  
(TP[2:0]) 4-31  
(TRG) 4-22  
(TTM) 4-92  
(TYP) 4-81  
(UA) 4-105  
(UDC) 4-74, 4-78  
(USE) 4-28  
(V) 4-56  
(VAL) 4-38  
(VER[2:0]) 4-16  
(VID) 4-2  
(VUE0) 4-27  
(VUE1) 4-27  
(WATN) 4-22  
base address register  
one (BAR1) 2-3, 4-9  
two (BAR2) 4-10  
zero - I/O (BAR0) 4-9  
bidirectional 3-3  
signals 6-3  
BIOS 2-3  
bits used for parity control and generation 2-25  
block move 2-9  
instruction 5-6  
bridge support extensions (BSE) 4-17  
burst  
disable (BDIS) 4-59  
Index  
IX-3  
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burst (Cont.)  
length (BL[1:0]) 4-66  
as I/O (CIO) 4-54  
as memory (CM) 4-54  
length bit 2 (BL2) 4-61  
opcode fetch enable (BOF) 4-68  
size selection 2-6  
CTEST4 2-25  
bus  
cumulative SCSI byte count (CSBC) 4-108  
cycle frame 3-6  
command and byte enables 3-5  
fault (BF) 4-40, 4-69  
byte  
count 5-37  
D1_Support (D1S) 4-16  
D2_Support (D2S) 4-16  
empty in DMA FIFO (FMT) 4-53  
full in DMA FIFO (FFL) 4-53  
offset counter (BO) 4-57  
(DATA) 4-18  
acknowledge status (DACK) 4-55  
compare mask 5-31  
compare value 5-32  
C
cache line size 2-7, 2-9  
(CLS) 4-7  
enable (CLSE) 4-70  
register 2-6  
structure address (DSA) 4-47  
transfer direction (DDIR) 4-54  
data write (DWR) 4-82  
data_scale (DSCL) 4-17  
data_select (DSLT) 4-17  
decode of MAD pins 3-14  
default download mode 2-50  
cache mode, see PCI cache mode 2-9  
call instruction 5-27  
Cap_ID (CID) 4-15  
capabilities pointer (CP) 4-13  
carry test 5-30  
chained block moves 2-44  
SCRIPTS instruction 2-47  
SODL register 2-46  
SWIDE register 2-46  
wide SCSI receive bit 2-46  
wide SCSI send bit 2-45  
chained mode (CHM) 4-26  
change bus phases 2-17  
chip  
address 5-23  
ID (DID) 4-3  
specific initialization (DSI) 4-16  
control 0 (CCNTL0) 4-95  
control 1 (CCNTL1) 4-97  
revision level (V) 4-56  
test five (CTEST5) 4-60  
test one (CTEST1) 4-53  
test six (CTEST6) 4-62  
test three (CTEST3) 4-56  
test two (CTEST2) 4-54  
test zero (CTEST0) 4-53  
type (TYP) 4-81  
timing (DT[1:0]) 4-5  
DIEN 2-25, 2-39, 2-40  
DIP 2-38, 2-41, 2-42, 2-43  
CHMOV 2-44  
class code (CC) 4-7  
clear DMA FIFO 2-42, 4-56  
clear instruction 5-15, 5-17  
clear SCSI FIFO (CSF) 4-92  
CLF 2-42  
auto FIFO clear (DISFC) 4-96  
dual address cycle (DDAC) 4-97  
halt on parity error or ATN (target only) (DHP) 4-23  
single initiator response (DSI) 4-92  
disconnect 2-17  
CLK 3-4  
clock 3-4  
address incrementor (ADCK) 4-60  
byte counter (BBCK) 4-61  
conversion factor (CCF[2:0]) 4-29  
quadrupler 2-20  
disconnect instruction 5-15  
byte counter (DBC) 4-62  
command (DCMD) 4-63  
control (DCNTL) 4-70  
direction (DDIR) 4-61  
FIFO 2-8, 2-27, 2-38  
(DF) 4-62  
CLSE 2-6, 2-7  
CMP 2-39  
compare  
data 5-31  
phase 5-31  
configuration  
read command 2-5  
space 2-3  
write command 2-5  
configured  
(DFIFO) 4-57  
byte offset counter, bits [9:8] (BO[9:8]) 4-62  
empty (DFE) 4-39  
size (DFS) 4-61  
interrupt 2-39, 2-40, 2-42  
enable (DIEN) 4-69  
IX-4  
Index  
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DMA  
interrupt (Cont.)  
pending (DIP) 4-50  
mode (DMODE) 4-66  
SCRIPTS  
pointer (DSP) 4-64  
pointer save (DSPS) 4-65  
status (DSTAT) 4-39  
enable (FE) 4-82  
pin mode (FM) 4-56  
byte control (FBL[2:0]) 4-60  
byte control (FBL3) 4-59  
flags (FF[3:0]) 4-43  
DMA next  
address (DNAD) 4-64  
address 64 (DNAD64) 4-103  
DMODE 2-6  
register 2-22  
DSA  
relative 5-36  
relative selector (DRS) 4-102  
DSPS register 5-34  
DSTAT 2-38, 2-42, 2-43  
dual address cycles  
flags, bit 4 (FF4) 4-46  
first dword 5-6, 5-14, 5-22, 5-26, 5-36  
flush DMA FIFO (FLF) 4-56  
flushing (FLSH) 4-51  
FRAME/ 3-6  
frequency lock (LOCK) 4-94  
full arbitration, selection/reselection 4-21  
function complete 2-39  
(CMP) 4-74, 4-77  
command 2-6  
dynamic block move selector (DBMS) 4-103  
E
(GPREG0) 4-35  
I/O pin 0 3-10  
I/O pin 1 3-10  
I/O pin 2 3-10  
I/O pin 3 3-10  
I/O pin 4 3-10  
enable  
64-bit  
direct BMOV (EN64DBMV) 4-98  
table indirect BMOV (EN64TIBMV) 4-98  
bus mastering (EBM) 4-4  
I/O space (EIS) 4-4  
timer expired (GEN) 4-75, 4-79  
GPIO enable, bits [1:0] (GPIO[1:0]) 4-83  
GPIO enable, bits [4:2] (GPIO[4:2]) 4-83  
GPIO0_ FETCH/ 3-10  
GPIO1_ MASTER/ 3-10  
jump on nondata phase mismatches (ENNDJ) 4-96  
memory space (EMS) 4-4  
parity  
checking 2-24  
checking (EPC) 4-22  
error response (EPER) 4-3  
phase mismatch jump (ENPMJ) 4-95  
read  
line (ERL) 4-67  
multiple (ERMP) 4-68  
response to  
reselection (RRE) 4-30  
selection (SRE) 4-30  
wide SCSI (EWS) 4-29  
enabling cache mode 2-10  
encoded  
chip SCSI ID (ENC) 4-30  
destination SCSI ID  
halt SCSI clock (HSC) 4-91  
(ENC) 4-35  
(ENID) 4-38  
handshake-to-handshake timer  
bus activity enable (HTHBA) 4-85  
expired (HTH) 4-76, 4-79  
SCSI destination ID 5-20  
entry storage address (ESA) 4-106  
error reporting signals 3-7  
even parity 2-24  
expansion ROM base  
address (ERBA) 4-12  
address register 2-49  
extend SREQ/SACK filtering (EXT) 4-90  
external  
period (HTH[3:0]) 4-83  
hardware control of SCSI activity LED 2-19  
hardware interrupts 2-37  
header type (HT) 4-8  
high impedance mode (SZM) 4-90  
high impedance mode (ZMODE) 4-97  
clock 6-9  
memory interface 2-49  
configuration 2-49  
I
I/O 3-3  
slow memory 2-49  
instructions 5-13  
read command 2-5  
space 2-2, 2-3  
write command 2-5  
external memory interface  
multiple byte accesses 6-11  
extra clock cycle of data setup (EXC) 4-23  
Index  
IX-5  
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IDSEL 2-3, 3-6  
control (PMJCTL) 4-95  
if true/false 5-30  
signal 2-5  
illegal instruction detected (IID) 4-40, 4-69  
immediate  
arbitration (IARB) 4-24  
data 5-23  
indirect addressing 5-6  
initialization device select 3-6  
initiator  
last disconnect (LDSC) 4-47  
latched SCSI parity  
(SDP0L) 4-45  
for SD[15:8] (SPL1) 4-47  
mode 5-16  
phase mismatch 4-76  
ready 3-6  
timer (LT) 4-8  
input 3-3  
capacitance 6-2  
instruction  
LED_CNTL (LEDC) 4-83  
load and store instructions 2-22, 5-37  
prefetch unit and store instructions 2-22  
loopback enable 2-23  
LSI53C700 compatibility (COM) 4-72  
LSI53C875A  
address (IA) 4-107  
block move 5-6  
prefetch unit flushing 2-21  
type 5-36  
block move 5-6  
new features 1-3  
I/O instruction 5-14  
memory move 5-33  
read/write instruction 5-22  
transfer control instruction 5-26  
internal  
SCRIPTS RAM 2-18  
internal RAM  
see also SCRIPTS  
RAM 2-18  
interrupt  
MAC/_TESTOUT 3-11  
bus programming 3-14  
MAD[7:0] 3-12, 3-14  
mailbox one (MBOX1) 4-52  
mailbox zero (MBOX0) 4-52  
manual start mode (MAN) 4-68  
acknowledge command 2-4  
handling 2-37  
instruction 5-28  
line (IL) 4-13  
on-the-fly 5-30  
on-the-fly (INTF) 4-49  
on-the-fly instruction 5-28  
output 6-10  
pin (IP) 4-14  
request 2-37, 3-8  
signals 3-8  
control for set or reset pulses (MASR) 4-61  
data parity error (MDPE) 4-40, 4-69  
enable (ME) 4-82  
status one (ISTAT1) 4-51  
status zero (ISTAT0) 4-48  
interrupts 2-39  
parity error enable (MPEE) 4-59  
max SCSI synchronous offset (MO[4:0]) 4-33  
Max_Lat (ML) 4-14  
maximum stress ratings 6-2  
fatal vs. nonfatal interrupts 2-39  
halting 2-42  
IRQ disable bit 2-39  
masking 2-40  
sample interrupt service routine 2-43  
stacked interrupts 2-41  
IRDY/ 3-6  
memory  
access control 3-11  
(MACNTL) 4-81  
address strobe 0 3-11  
address strobe 1 3-11  
address/data bus 3-12  
chip enable 3-11  
IRQ  
disable (IRQD) 4-72  
mode (IRQM) 4-71  
IRQ/ 2-37, 3-8  
pin 2-40, 2-43  
issuing cache commands 2-10  
ISTAT 2-37, 2-43  
I/O address/DSA offset 5-37  
move instructions 2-21, 5-32  
no flush option 2-21  
move read selector (MMRS) 4-100  
move write selector (MMWS) 4-101  
output enable 3-11  
read 2-10, 2-11  
read caching 2-11  
read command 2-5  
read line 2-10, 2-11  
J
JTAG boundary scan testing 2-23  
jump  
address 5-32  
call a relative address 5-29  
call an absolute address 5-29  
IX-6  
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memory (Cont.)  
target disconnect 2-9  
target retry 2-9  
read line command 2-6  
read multiple 2-10, 2-11  
read multiple command 2-6  
space 2-2, 2-3  
to memory 2-16  
to memory moves 2-16  
write 2-10, 2-11  
write and invalidate 2-10  
write and invalidate command 2-8  
write caching 2-11  
write command 2-5  
write enable 3-11  
handling in SCRIPTS 2-17  
jump address 1 (PMJAD1) 4-104  
jump registers 4-103  
physical dword address and data 3-5  
PME  
clock (PMEC) 4-16  
enable (PEN) 4-17  
status (PST) 4-16  
Min_Gnt (MG) 4-14  
MOE/ 3-11  
move to/from SFBR cycles 5-24  
multiple cache line transfers 2-8  
MWE/ 3-11  
support (PMES) 4-15  
pointer SCRIPTS (PSCPT) 4-82  
management 2-51  
state (PWS[1:0]) 4-17  
state D0 2-52  
N
state D1 2-52  
state D2 2-53  
state D3 2-53  
new capabilities (NC) 4-6  
new features in the LSI53C875A 1-3  
Next_Item_Ptr (NIP) 4-15  
no connections 3-13  
no download mode 2-51  
no flush 5-33  
enable (PFEN) 4-70  
flush (PFF) 4-70  
store instruction only 5-36  
not supported 4-8, 4-10  
SCRIPTS instructions 2-21  
pull-ups, internal, conditions 3-3  
O
opcode 5-9, 5-14, 5-22, 5-26  
fetch burst capability 2-22  
operating conditions 6-2  
operator 5-22  
see also SCRIPTS  
RAM 2-18  
function 2-7  
modify-write cycles 5-23  
multiple 2-7  
P
PAR 3-5  
multiple with read line enabled 2-7  
write instructions 5-22  
write system memory from SCRIPTS 5-34  
instructions 5-22, 5-24  
system memory from SCRIPTS 5-34  
parallel ROM interface 2-48  
parallel ROM support 2-49  
parity 2-26, 3-5  
error 3-7  
(PAR) 4-78  
options 2-24  
PCI  
addressing 2-2  
and external memory interface timing diagrams 6-11  
bus commands and encoding types 2-4  
bus commands and functions supported 2-3  
cache line size register 2-8  
cache mode 2-9  
address 5-37  
address - A[6:0] 5-23  
commands 2-3  
REQ/ 3-7  
request 3-7  
reselect 2-17  
configuration into enable (PCICIE) 4-54  
configuration register read 6-13  
configuration registers 4-1  
configuration space 2-2  
functional description 2-2  
I/O space 2-3  
during reselection 2-33  
instruction 5-14  
interface signals 3-4  
reselected (RSL) 4-74, 4-77  
reserved 4-3, 4-4, 4-5, 4-6, 4-10, 4-13, 4-16, 4-17, 4-22, 4-30,  
4-35, 4-38, 4-40, 4-51, 4-69, 4-75, 4-79, 4-85, 4-88, 4-94,  
4-96, 4-97, 4-99, 4-103, 4-108  
command 2-5  
master transaction 2-10  
master transfer 2-10  
memory space 2-3  
performance 1-6  
Index  
IX-7  
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reset 3-4  
input 6-10  
I_O/ signal (I/O) 4-45  
input data latch (SIDL) 4-93  
instructions  
SCSI offset (ROF) 4-89  
response ID one (RESPID1) 4-86  
response ID zero (RESPID0) 4-86  
return instruction 5-27  
revision ID (RID) 4-6  
ROM  
flash and memory interface signals 3-11  
pin 2-49  
RST/ 3-4  
block move 5-6  
I/O 5-13  
read/write 5-22  
interface signals 3-8  
interrupt enable one (SIEN1) 4-75  
interrupt enable zero (SIEN0) 4-73  
interrupt pending (SIP) 4-50  
interrupt status one (SIST1) 4-78  
interrupt status zero (SIST0) 4-76  
isolation mode (ISO) 4-88  
longitudinal parity (SLPAR) 4-79  
loopback mode 2-23  
loopback mode (SLB) 4-89  
low level mode (LOW) 4-90  
MSG/ signal (MSG) 4-45  
output control latch (SOCL) 4-37  
output data latch (SODL) 4-94  
parity control 2-26  
S
SACK 2-42  
SACK/ status (ACK) 4-39  
SACs 2-19  
SATN/ status (ATN) 4-39  
SBSY/ status (BSY) 4-39  
SC_D/ status (C_D) 4-39  
SCLK 3-8  
(SCLK) 4-88  
parity error (PAR) 4-75  
performance 1-5  
phase 5-11, 5-28  
quadrupler enable (QEN) 4-88  
quadrupler select (QSEL) 4-89  
SCNTL0 2-25  
phase mismatch - initiator mode 4-73  
reset condition (RST) 4-75  
RST/ received (RST) 4-78  
RST/ signal (RST) 4-43  
SCRIPTS operation 5-2  
sample instruction 5-3  
SDP0/ parity signal (SDP0) 4-43  
SDP1 signal (SDP1) 4-47  
selected as ID (SSAID) 4-87  
selector ID (SSID) 4-38  
serial EEPROM access 2-50  
status one (SSTAT1) 4-43  
status two (SSTAT2) 4-46  
status zero (SSTAT0) 4-42  
synchronous offset maximum (SOM) 4-88  
synchronous offset zero (SOZ) 4-87  
synchronous transfer period (TP[2:0]) 4-31  
termination 2-32  
test four (STEST4) 4-94  
test one (STEST1) 4-88  
test three (STEST3) 4-91  
test two (STEST2) 4-89  
test zero (STEST0) 4-87  
timer one (STIME1) 4-85  
timer zero (STIME0) 4-83  
TolerANT technology 1-4  
transfer (SXFER) 4-31  
SCNTL1 2-24, 2-25  
SCNTL3 2-36  
scratch  
byte register (SBR) 4-70  
register A (SCRATCHA) 4-65  
register B (SCRATCHB) 4-99  
registers C–R (SCRATCHC–SCRATCHR) 4-99  
script fetch selector (SFS) 4-101  
SCRIPTS  
(SCPTS) 4-82  
instruction 2-46  
interrupt instruction received (SIR) 4-40, 4-69  
processor 2-17  
internal RAM for instruction storage 2-18  
performance 2-17  
RAM 2-3, 2-18  
running (SRUN) 4-51  
SCSI  
ATN condition - target mode (M/A) 4-73  
bus control lines (SBCL) 4-38  
bus data lines (SBDL) 4-98  
bus interface 2-32  
byte count (SBC) 4-107  
C_D/ signal (C_D) 4-45  
chip ID (SCID) 4-30  
clock 3-8  
control enable (SCE) 4-89  
control one (SCNTL1) 4-23  
control three (SCNTL3) 4-28  
control two (SCNTL2) 4-26  
control zero (SCNTL0) 4-20  
data high impedance (ZSD) 4-59  
destination ID (SDID) 4-35  
disconnect unexpected (SDU) 4-26  
encoded destination ID 5-20  
FIFO test read (STR) 4-91  
FIFO test write (STW) 4-93  
first byte received (SFBR) 4-36  
functional description 2-16  
GPIO signals 3-10  
true end of process (TEOP) 4-55  
valid (VAL) 4-38  
wide residue (SWIDE) 4-81  
SCSI-2  
fast transfers  
10.0 Mbytes (8-bit transfers)  
40 MHz clock 6-56  
20.0 Mbytes (16-bit transfers)  
40 MHz clock 6-56  
SCTRL signals 3-9  
SD[15:0] 3-9  
second dword 5-13, 5-21, 5-23, 5-32, 5-34, 5-37  
gross error (SGE) 4-74, 4-77  
IX-8  
Index  
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SEL 2-39  
select 2-17  
store 2-22  
instruction 5-16  
with ATN/ 5-20  
subsystem ID 2-51  
with SATN/ on a start sequence (WATN) 4-22  
selected (SEL) 4-74, 4-77  
selection or reselection time-out (STO) 4-75, 4-79  
selection response logic test (SLT) 4-87  
selection time-out (SEL[3:0]) 4-84  
semaphore (SEM) 4-49  
serial EEPROM  
subsystem ID (SID) 4-11  
subsystem vendor ID 2-51  
subsystem vendor ID (SVID) 4-10  
SWIDE register 2-46, 2-47  
SYNC_IRQD (SI) 4-51  
interface 2-50  
SERR/ 3-7  
data transfer rates 2-34  
operation 2-34  
SCSI receive 2-31  
SERR/ enable (SE) 4-3  
set instruction 5-15, 5-17  
set/clear  
SCSI send 2-30  
carry 5-20  
SACK/ 5-21  
system signals 3-4  
shadow register test mode (SRTM) 4-59  
SI_O/ status (I_O) 4-39  
SID 2-51  
SIDL  
mode 5-18  
least significant byte full (ILF) 4-42  
most significant byte full (ILF1) 4-46  
SIEN0 2-39  
SIEN1 2-39  
mode 5-9, 5-14  
SATN/ active (M/A) 4-76  
mode (TRG) 4-22  
signal process (SIGP) 4-49, 4-54  
signaled system error (SSE) 4-5  
simple arbitration 4-20  
single  
address cycles 2-19  
TDO 3-12  
ended SCSI signals 6-6  
step interrupt (SSI) 4-40, 4-69  
step mode (SSM) 4-71  
SIP 2-38, 2-41, 2-42  
SIST0 2-25, 2-38, 2-41, 2-43  
SIST1 2-38, 2-41, 2-43  
slow ROM pin 3-15  
SLPAR high byte enable (SLPHBEN) 4-27  
SLPAR mode (SLPMD) 4-27  
SMSG/ status (MSG) 4-39  
SODL  
least significant byte full (OLF) 4-42  
most significant byte full (OLF1) 4-46  
register 2-45, 2-46, 2-47  
SODR  
least significant byte full (ORF) 4-42  
most significant byte full (ORF1) 4-46  
software reset (SRST) 4-48  
source I/O memory enable (SIOM) 4-67  
special cycle command 2-4  
SREQ 2-42  
SREQ/ status (REQ) 4-39  
SSEL/ status (SEL) 4-39  
SSTAT0 2-25  
TEMP register 5-35  
temporary (TEMP) 4-57  
test interface signals 3-12  
TEST_HSC/ 3-12  
TEST_RST/ 3-12  
timer test mode (TTM) 4-92  
TolerANT 1-4, 6-5  
enable (TE) 4-91  
technology 1-4  
benefits 1-4  
electrical characteristics 6-5  
totem pole output 3-3  
control 2-22  
control instructions 5-25  
and SCRIPTS instruction prefetching 2-22  
counter 5-12, 5-33  
information 2-17  
synchronous 2-34  
SSTAT1 2-25  
stacked interrupts 2-41  
start  
address 5-13, 5-21  
U
DMA operation (STD) 4-72  
SCSI transfer (SST) 4-25  
sequence (START) 4-21  
static block move selector (SBMS) 4-102  
STEST2 register 2-23  
STOP command 2-9  
Ultra SCSI 1-3  
benefits 1-3  
clock conversion factor bits 4-29  
designing an Ultra SCSI system 2-20  
enable (USE) 4-28  
stop signal 3-6  
Index  
IX-9  
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Ultra SCSI (Cont.)  
single-ended transfers  
20.0 Mbytes (16-bit transfers)  
quadrupled 40 MHz clock 6-56  
20.0 Mbytes (8-bit transfers)  
40 MHz clock 6-56  
synchronous data transfers 2-36  
unexpected disconnect (UDC) 4-74, 4-78  
updated address (UA) 4-105  
upper register address line (A7) 5-23  
use data8/SFBR 5-22  
V
VDD 3-13  
-A 3-13  
-core 3-13  
vendor  
ID (VID) 4-2  
unique enhancement, bit 1 (VUE1) 4-27  
unique enhancements, bit 0 (VUE0) 4-27  
version (VER[2:0]) 4-16  
VSS 3-13  
-A 3-13  
-core 3-13  
W
wait  
disconnect instruction 5-17  
for a disconnect 2-17  
for valid phase 5-31  
reselect instruction 5-17  
select instruction 5-15  
wide SCSI  
chained block moves 2-44  
receive (WSR) 4-28  
receive bit 2-46  
send (WSS) 4-27  
send bit 2-45  
won arbitration (WOA) 4-43  
write  
read instructions 5-22  
read system memory from SCRIPTS 5-34  
write and invalidate  
enable (WIE) 4-4  
enable (WRIE) 4-57  
WSR bit 2-46  
WSS flag 2-45  
IX-10  
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I. E.  
W. E. Tel: 856.439.9110  
W. E. Tel: 256.830.1119  
Tel: 303.457.9953  
Tel: 480.736.7000  
Tel: 602.267.9551  
Tel: 800.528.4040  
Florida  
Altamonte Springs  
Missouri  
W. E. Tel: 630.620.0969  
St. Louis  
Tel: 913.663.7900  
B. M.  
I. E.  
Tel: 407.682.1199  
Tel: 407.834.6310  
Tempe  
I. E.  
Tucson  
A. E.  
Tel: 913.492.0408  
A. E.  
I. E.  
Tel: 314.291.5350  
Tel: 314.872.2182  
Tel: 480.829.1800  
Tel: 520.742.0515  
Boca Raton  
Kentucky  
W. E.  
Central/Northern/ Western  
A. E.  
I. E.  
Tel: 561.997.2540  
Tel: 937.436.9953  
Montana  
Bonita Springs  
A. E.  
Tel: 800.526.1741  
B. M.  
Tel: 941.498.6011  
Arkansas  
Tel: 800.984.9503  
Tel: 800.767.0329  
Tel: 800.829.0146  
W. E. Tel: 801.974.9953  
Clearwater  
W. E.  
Tel: 972.235.9953  
I. E.  
Tel: 727.524.8850  
Nebraska  
Fort Lauderdale  
California  
Agoura Hills  
A. E.  
Tel: 800.332.4375  
A. E.  
Tel: 954.484.5482  
Louisiana  
W. E.  
North/South  
A. E.  
W. E. Tel: 303.457.9953  
W. E. Tel: 800.568.9953  
Miami  
B. M.  
Tel: 818.865.0266  
Tel: 713.854.9953  
Granite Bay  
Nevada  
Las Vegas  
B. M.  
Tel: 305.477.6406  
B. M.  
Irvine  
A. E.  
B. M.  
I. E.  
Tel: 916.523.7047  
Tel: 800.231.0253  
Tel: 800.231.5775  
Orlando  
A. E.  
A. E.  
Tel: 800.528.8471  
Tel: 407.657.3300  
Tel: 949.789.4100  
Tel: 949.470.2900  
Tel: 949.727.3291  
Tel: 800.626.9953  
W. E. Tel: 702.765.7117  
W. E. Tel: 407.740.7450  
Tampa  
W. E. Tel: 800.395.9953  
St. Petersburg  
Maine  
A. E.  
W. E.  
New Hampshire  
Tel: 800.272.9255  
Tel: 781.271.9953  
A. E.  
Tel: 800.272.9255  
W. E.  
W. E. Tel: 781.271.9953  
Los Angeles  
A. E.  
Tel: 727.507.5000  
Maryland  
Baltimore  
A. E.  
W. E.  
Columbia  
A. E.  
W. E.  
Tel: 818.594.0404  
Tel: 800.288.9953  
New Jersey  
North/South  
Georgia  
Atlanta  
A. E.  
Tel: 410.720.3400  
Tel: 800.863.9953  
Sacramento  
A. E.  
Tel: 201.515.1641  
Tel: 609.222.6400  
A. E.  
W. E.  
Tel: 916.632.4500  
Tel: 800.627.9953  
Tel: 770.623.4400  
Tel: 770.980.4922  
B. M.  
Mt. Laurel  
B. M.  
I. E.  
Tel: 800.673.7461  
Tel: 410.381.3131  
San Diego  
W. E. Tel: 800.876.9953  
Duluth  
I. E.  
Tel: 856.222.9566  
A. E.  
B. M.  
I. E.  
Tel: 858.385.7500  
Pine Brook  
Tel: 858.597.3010  
Tel: 800.677.6011  
Tel: 800.829.9953  
I. E.  
Tel: 678.584.0812  
Tel: 800.851.2282  
Tel: 801.365.3800  
Massachusetts  
Boston  
A. E.  
W. E.  
Burlington  
I. E.  
Marlborough  
B. M.  
Woburn  
B. M.  
B. M.  
Tel: 973.244.9668  
W. E. Tel: 800.862.9953  
Parsippany  
W. E.  
Hawaii  
A. E.  
Tel: 978.532.9808  
Tel: 800.444.9953  
San Jose  
I. E.  
Tel: 973.299.4425  
A. E.  
B. M.  
I. E.  
Tel: 408.435.3500  
Tel: 408.436.0881  
Tel: 408.952.7000  
Wayne  
W. E. Tel: 973.237.9010  
Idaho  
A. E.  
Tel: 781.270.9400  
W. E. Tel: 801.974.9953  
Santa Clara  
New Mexico  
W. E. Tel: 480.804.7000  
Albuquerque  
Tel: 800.673.7459  
W. E.  
Tel: 800.866.9953  
Woodland Hills  
Tel: 800.552.4305  
A. E.  
Tel: 818.594.0404  
A. E.  
Tel: 505.293.5119  
Westlake Village  
I. E.  
Tel: 818.707.2101  
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U.S. Distributors  
by State  
(Continued)  
New York  
South Carolina  
Washington  
Hauppauge  
A. E.  
Tel: 919.872.0712  
Kirkland  
I. E.  
Tel: 516.761.0960  
W. E. Tel: 919.469.1502  
I. E.  
Tel: 425.820.8100  
Long Island  
Maple Valley  
South Dakota  
A. E.  
W. E.  
Tel: 516.434.7400  
Tel: 800.861.9953  
B. M.  
Seattle  
A. E.  
Tel: 206.223.0080  
A. E.  
Tel: 800.829.0116  
W. E. Tel: 612.853.2280  
Rochester  
Tel: 425.882.7000  
Tel: 800.248.9953  
A. E.  
I. E.  
W. E.  
Tel: 716.475.9130  
Tel: 716.242.7790  
Tel: 800.319.9953  
W. E.  
Tennessee  
W. E. Tel: 256.830.1119  
East/West  
West Virginia  
A. E.  
Tel: 800.638.5988  
Smithtown  
A. E.  
Tel: 800.241.8182  
Tel: 800.633.2918  
B. M.  
Tel: 800.543.2008  
Wisconsin  
Milwaukee  
Syracuse  
A. E.  
Tel: 315.449.4927  
Texas  
Arlington  
B. M.  
A. E.  
W. E.  
Tel: 414.513.1500  
Tel: 800.867.9953  
North Carolina  
Raleigh  
Tel: 817.417.5993  
Wauwatosa  
Austin  
A. E.  
B. M.  
I. E.  
Tel: 414.258.5338  
A. E.  
I. E.  
W. E.  
Tel: 919.859.9159  
Tel: 919.873.9922  
Tel: 800.560.9953  
Tel: 512.219.3700  
Tel: 512.258.0725  
Tel: 512.719.3090  
Wyoming  
I. E.  
A. E.  
W. E.  
Tel: 800.332.9326  
Tel: 801.974.9953  
W. E. Tel: 800.365.9953  
Dallas  
North Dakota  
A. E.  
W. E.  
Tel: 800.829.0116  
Tel: 612.853.2280  
A. E.  
B. M.  
Tel: 214.553.4300  
Tel: 972.783.4191  
Ohio  
Cleveland  
W. E. Tel: 800.955.9953  
El Paso  
A. E.  
W. E.  
Dayton  
A. E.  
I. E.  
Tel: 216.498.1100  
Tel: 800.763.9953  
A. E.  
Houston  
A. E.  
Tel: 800.526.9238  
Tel: 713.781.6100  
Tel: 713.917.0663  
Tel: 614.888.3313  
Tel: 937.253.7501  
Tel: 800.575.9953  
B. M.  
W. E. Tel: 800.888.9953  
Richardson  
W. E.  
Strongsville  
I. E.  
Tel: 972.783.0800  
B. M.  
Tel: 440.238.0404  
Rio Grande Valley  
Valley View  
A. E.  
Tel: 210.412.2047  
I. E.  
Tel: 216.520.4333  
Stafford  
I. E.  
Tel: 281.277.8200  
Oklahoma  
W. E.  
Tulsa  
A. E.  
I. E.  
Tel: 972.235.9953  
Utah  
Centerville  
B. M.  
Murray  
I. E.  
Salt Lake City  
A. E.  
W. E. Tel: 800.477.9953  
Tel: 918.459.6000  
Tel: 918.665.4664  
Tel: 801.295.3900  
Tel: 801.288.9001  
Oregon  
Beaverton  
B. M.  
I. E.  
Tel: 801.365.3800  
Tel: 503.524.1075  
Tel: 503.644.3300  
Portland  
A. E.  
W. E.  
Vermont  
Tel: 503.526.6200  
Tel: 800.879.9953  
A. E.  
Tel: 800.272.9255  
W. E. Tel: 716.334.5970  
Pennsylvania  
Virginia  
Mercer  
A. E.  
Tel: 800.638.5988  
I. E.  
Philadelphia  
Tel: 412.662.2707  
W. E. Tel: 301.604.8488  
Haymarket  
A. E.  
B. M.  
W. E.  
Tel: 800.526.4812  
Tel: 877.351.2355  
Tel: 800.871.9953  
B. M.  
Springfield  
B. M. Tel: 703.644.9045  
Tel: 703.754.3399  
Pittsburgh  
A. E.  
W. E.  
Tel: 412.281.4150  
Tel: 440.248.9996  
Rhode Island  
A. E.  
W. E.  
800.272.9255  
Tel: 781.271.9953  
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Direct Sales  
Representatives by State  
(Component and HAB)  
E. A.  
E. L.  
GRP  
I. S.  
ION  
R. A.  
Earle Associates  
Electrodyne - UT  
Group 2000  
Infinity Sales, Inc.  
ION Associates, Inc.  
Rathsburg Associ-  
ates, Inc.  
Texas  
Austin  
ION  
Arlington  
ION  
Tel: 512.794.9006  
Tel: 817.695.8000  
Tel: 281.376.2000  
Houston  
ION  
SGY  
Synergy Associates,  
Inc.  
Utah  
Salt Lake City  
Arizona  
Tempe  
E. A.  
E. L.  
Tel: 801.264.8050  
Wisconsin  
Muskego  
Tel: 480.921.3305  
R. A.  
Saukville  
R. A.  
Tel: 414.679.8250  
California  
Calabasas  
Tel: 414.268.1152  
I. S.  
Irvine  
I. S.  
Tel: 818.880.6480  
Tel: 714.833.0300  
San Diego  
E. A.  
Tel: 619.278.5441  
Illinois  
Elmhurst  
R. A.  
Tel: 630.516.8400  
Indiana  
Cicero  
R. A.  
Ligonier  
R. A.  
Tel: 317.984.8608  
Tel: 219.894.3184  
Tel: 317.838.0360  
Plainfield  
R. A.  
Massachusetts  
Burlington  
SGY  
Tel: 781.238.0870  
Michigan  
Byron Center  
R. A.  
Tel: 616.554.1460  
Good Rich  
R. A.  
Novi  
R. A.  
Tel: 810.636.6060  
Tel: 810.615.4000  
North Carolina  
Cary  
GRP  
Tel: 919.481.1530  
Ohio  
Columbus  
R. A.  
Tel: 614.457.2242  
Dayton  
R. A.  
Tel: 513.291.4001  
Independence  
R. A.  
Tel: 216.447.8825  
Pennsylvania  
Somerset  
R. A.  
Tel: 814.445.6976  
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Sales Offices and Design  
Resource Centers  
LSI Logic Corporation  
Fort Collins  
New Jersey  
Red Bank  
125 Half Mile Road  
Suite 200  
Red Bank, NJ 07701  
Tel: 732.933.2656  
Fax: 732.933.2643  
Canada  
Ontario  
Ottawa  
260 Hearst Way  
Suite 400  
2001 Danfield Court  
Fort Collins, CO 80525  
Tel: 970.223.5100  
Corporate Headquarters  
1551 McCarthy Blvd  
Milpitas CA 95035  
Tel: 408.433.8000  
Fax: 970.206.5549  
TKealn:a6ta1,3O.5N9K22.1L236H31  
Fax: 408.433.8989  
NORTH AMERICA  
California  
Irvine  
18301 Von Karman Ave  
Suite 900  
Florida  
Boca Raton  
2255 Glades Road  
Suite 324A  
Boca Raton, FL 33431  
Tel: 561.989.3236  
Fax: 561.989.3237  
Fax: 613.592.3253  
Cherry Hill - Mint Technology  
215 Longstone Drive  
Cherry Hill, NJ 08003  
Tel: 856.489.5530  
Fax: 856.489.5531  
INTERNATIONAL  
France  
Paris  
LSI Logic S.A.  
Immeuble Europa  
53 bis Avenue de l'Europe  
B.P. 139  
ITreviln:e9,4C9A.890296.142600  
Georgia  
Alpharetta  
2475 North Winds Parkway  
Suite 200  
Alpharetta, GA 30004  
Tel: 770.753.6146  
Fax: 770.753.6147  
New York  
Fairport  
550 Willowbrook Office Park  
Fairport, NY 14450  
Tel: 716.218.0020  
Fax: 716.218.9010  
Fax: 949.809.4444  
Pleasanton Design Center  
5050 Hopyard Road, 3rd Floor  
Suite 300  
Pleasanton, CA 94588  
Tel: 925.730.8800  
78148 Velizy-Villacoublay  
CTeeld:e3x3, .P1a.r3is4.63.13.13  
North Carolina  
Raleigh  
Phase II  
4601 Six Forks Road  
Suite 528  
Raleigh, NC 27609  
Tel: 919.785.4520  
Fax: 919.783.8909  
Fax: 33.1.34.63.13.19  
Fax: 925.730.8700  
Illinois  
Oakbrook Terrace  
Two Mid American Plaza  
Suite 800  
Oakbrook Terrace, IL 60181  
Tel: 630.954.2234  
Germany  
Munich  
LSI Logic GmbH  
Orleansstrasse 4  
San Diego  
7585 Ronson Road  
Suite 100  
San Diego, CA 92111  
Tel: 858.467.6981  
8T1e6l:6499M.8u9ni.c4h.58.33.0  
Fax: 630.954.2235  
Fax: 858.496.0548  
Fax: 49.89.4.58.33.108  
Kentucky  
Oregon  
Silicon Valley  
1551 McCarthy Blvd  
Sales Office  
Bowling Green  
Beaverton  
15455 NW Greenbrier Parkway  
Suite 235  
Beaverton, OR 97006  
Tel: 503.645.0589  
Stuttgart  
1262 Chestnut Street  
Bowling Green, KY 42101  
Tel: 270.793.0010  
Mittlerer Pfad 4  
DTe-7l:044999.7S1t1ut.t1g3ar.9t 6.90  
M/S C-500  
TMeillp:it4a0s,8C.4A3935.8030500  
Fax: 270.793.0040  
Fax: 49.711.86.61.428  
Fax: 503.645.6612  
Fax: 408.954.3353  
Design Center  
Maryland  
Bethesda  
6903 Rockledge Drive  
Suite 230  
Bethesda, MD 20817  
Tel: 301.897.5800  
Fax: 301.897.8389  
Italy  
Milan  
Texas  
Austin  
M/S C-410  
Tel: 408.433.8000  
Fax: 408.433.7695  
LSI Logic S.P.A.  
Centro Direzionale Colleoni Palazzo  
Orione Ingresso 1  
9020 Capital of TX Highway North  
Building 1  
Suite 150  
Austin, TX 78759  
Tel: 512.388.7294  
2T0e0l:4319A.g0r3a9te.6B8ri7a3n7za1, Milano  
Wireless Design Center  
11452 El Camino Real  
Suite 210  
San Diego, CA 92130  
Tel: 858.350.5560  
Fax: 39.039.6057867  
Fax: 512.388.4171  
Massachusetts  
Waltham  
200 West Street  
Japan  
Tokyo  
LSI Logic K.K.  
Rivage-Shinagawa Bldg. 14F  
4-1-8 Kounan  
Plano  
Fax: 858.350.0171  
500 North Central Expressway  
Suite 440  
TWeall:th7a8m1,.8M9A00.02145810  
Colorado  
Boulder  
4940 Pearl East Circle  
Suite 201  
PTelaln: o9,7T2X.2745407.54000  
Fax: 781.890.6158  
MTeinl:a8to1-k.3u,.5T4ok6y3o.718082-10075  
Fax: 972.244.5001  
Burlington - Mint Technology  
77 South Bedford Street  
Burlington, MA 01803  
Tel: 781.685.3800  
Fax: 781.685.3801  
Fax: 81.3.5463.7820  
TBeolu:ld3e0r,3C.4O4780.3380010  
Houston  
20405 State Highway 249  
Suite 450  
Houston, TX 77070  
Tel: 281.379.7800  
Fax: 303.541.0641  
Osaka  
Crystal Tower 14F  
1-2-27 Shiromi  
Colorado Springs  
Minnesota  
Minneapolis  
8300 Norman Center Drive  
Suite 730  
TCehlu:o8-k1u.6, O.9s4a7k.a5524801-6014  
4420 Arrowswest Drive  
Colorado Springs, CO 80907  
Tel: 719.533.7000  
Fax: 281.379.7818  
Fax: 81.6.947.5287  
Fax: 719.533.7020  
MTeinl:n6ea1p2o.l9is2,1M.8N35050437  
Fax: 612.921.8399  
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Sales Offices and Design  
Resource Centers  
(Continued)  
Korea  
Seoul  
LSI Logic Corporation of  
Korea Ltd  
10th Fl., Haesung 1 Bldg.  
942, Daechi-dong,  
Kangnam-ku, Seoul, 135-283  
Tel: 82.2.528.3400  
Fax: 82.2.528.2250  
The Netherlands  
Eindhoven  
LSI Logic Europe Ltd  
World Trade Center Eindhoven  
Building ‘Rijder’  
Bogert 26  
5612 LZ Eindhoven  
Tel: 31.40.265.3580  
Fax: 31.40.296.2109  
Singapore  
Singapore  
LSI Logic Pte Ltd  
7 Temasek Boulevard  
#28-02 Suntec Tower One  
Singapore 038987  
Tel: 65.334.9061  
Fax: 65.334.4749  
Sweden  
Stockholm  
LSI Logic AB  
Finlandsgatan 14  
1T6e4l:7446K.8is.4ta44.15.00  
Fax: 46.8.750.66.47  
Taiwan  
Taipei  
LSI Logic Asia, Inc.  
Taiwan Branch  
10/F 156 Min Sheng E. Road  
Section 3  
Taipei, Taiwan R.O.C.  
Tel: 886.2.2718.7828  
Fax: 886.2.2718.8869  
United Kingdom  
Bracknell  
LSI Logic Europe Ltd  
Greenwood House  
London Road  
TBeral:ck4n4e.l1l,3B4e4rk.4sh2i6re5R4G412 2UB  
Fax: 44.1344.481039  
Sales Offices with  
Design Resource Centers  
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International Distributors  
Australia  
Hong Kong  
Yokohama-City  
United Kingdom  
New South Wales  
Reptechnic Pty Ltd  
3/36 Bydown Street  
Hong Kong  
AVT Industrial Ltd  
Unit 608 Tower 1  
Cheung Sha Wan Plaza  
833 Cheung Sha Wan Road  
Kowloon, Hong Kong  
Tel: 852.2428.0008  
Innotech  
2-15-10 Shin Yokohama  
Kohoku-ku  
Yokohama-City, 222-8580  
Tel: 81.45.474.9037  
Maidenhead  
Azzurri Technology Ltd  
16 Grove Park Business Estate  
Waltham Road  
White Waltham  
Maidenhead, Berkshire SL6 3LW  
TNeelu:tr6a1l 2B.a9y9, N53S.W98240489  
Fax: 81.45.474.9065  
Fax: 612.9953.9683  
Tel: 44.1628.826826  
Fax: 852.2401.2105  
Fax: 44.1628.829730  
Milton Keynes  
Ingram Micro (UK) Ltd  
Garamonde Drive  
Wymbush  
Milton Keynes  
Buckinghamshire MK8 8DF  
Tel: 44.1908.260422  
Macnica Corporation  
Hakusan High-Tech Park  
1-22-2 Hadusan, Midori-Ku,  
Yokohama-City, 226-8505  
Tel: 81.45.939.6140  
Belgium  
Acal nv/sa  
Lozenberg 4  
1932 Zaventem  
Tel: 32.2.7205983  
Fax: 32.2.7251014  
Serial System (HK) Ltd  
2301 Nanyang Plaza  
57 Hung To Road, Kwun Tong  
Kowloon, Hong Kong  
Tel: 852.2995.7538  
Fax: 852.2950.0386  
Fax: 81.45.939.6141  
The Netherlands  
Eindhoven  
Acal Nederland b.v.  
Beatrix de Rijkweg 8  
5657 EG Eindhoven  
Tel: 31.40.2.502602  
Fax: 31.40.2.510255  
China  
Beijing  
LSI Logic International  
Services Inc.  
Beijing Representative  
Office  
India  
Bangalore  
Spike Technologies India  
Private Ltd  
951, Vijayalakshmi Complex,  
2nd Floor, 24th Main,  
J P Nagar II Phase,  
Swindon  
EBV Elektronik  
12 Interface Business Park  
Bincknoll Lane  
Wootton Bassett,  
Swindon, Wiltshire SN4 8SY  
Tel: 44.1793.849933  
Fax: 44.1793.859555  
Room 708  
Canway Building  
66 Nan Li Shi Lu  
Xicheng District  
Beijing 100045, China  
Tel: 86.10.6804.2534 to 38  
Fax: 86.10.6804.2521  
Switzerland  
Brugg  
LSI Logic Sulzer AG  
Mattenstrasse 6a  
CH 2555 Brugg  
Tel: 41.32.3743232  
Fax: 41.32.3743233  
TBealn:g9a1lo.r8e0, .I6nd6i4a.5565030078  
Fax: 91.80.664.9748  
Sales Offices with  
Israel  
Tel Aviv  
Eastronics Ltd  
11 Rozanis Street  
P.O. Box 39300  
Tel Aviv 61392  
Tel: 972.3.6458777  
Fax: 972.3.6458666  
Design Resource Centers  
France  
Rungis Cedex  
Azzurri Technology France  
22 Rue Saarinen  
Sillic 274  
94578 Rungis Cedex  
Tel: 33.1.41806310  
Fax: 33.1.41730340  
Taiwan  
Taipei  
Avnet-Mercuries  
Corporation, Ltd  
14F, No. 145,  
Sec. 2, Chien Kuo N. Road  
Taipei, Taiwan, R.O.C.  
Tel: 886.2.2516.7303  
Japan  
Tokyo  
Daito Electron  
Sogo Kojimachi No.3 Bldg  
1-6 Kojimachi  
Chiyoda-ku, Tokyo 102-8730  
Tel: 81.3.3264.0326  
Fax: 81.3.3261.3984  
Germany  
Haar  
EBV Elektronik  
Hans-Pinsel Str. 4  
D-85540 Haar  
Tel: 49.89.4600980  
Fax: 49.89.46009840  
Fax: 886.2.2505.7391  
Lumax International  
Corporation, Ltd  
7th Fl., 52, Sec. 3  
Nan-Kang Road  
Taipei, Taiwan, R.O.C.  
Global Electronics  
Corporation  
Nichibei Time24 Bldg. 35 Tansu-cho  
Shinjuku-ku, Tokyo 162-0833  
Tel: 81.3.3260.1411  
Fax: 81.3.3260.7100  
Technical Center  
Munich  
Tel: 886.2.2788.3656  
Fax: 886.2.2788.3568  
Avnet Emg GmbH  
Stahlgruberring 12  
81829 Munich  
Tel: 49.89.45110102  
Fax: 49.89.42.27.75  
Prospect Technology  
Corporation, Ltd  
4Fl., No. 34, Chu Luen Street  
Taipei, Taiwan, R.O.C.  
Tel: 886.2.2721.9533  
Tel: 81.471.43.8200  
Wuennenberg-Haaren  
Peacock AG  
Fax: 886.2.2773.3756  
Marubeni Solutions  
1-26-20 Higashi  
Shibuya-ku, Tokyo 150-0001  
Tel: 81.3.5778.8662  
Fax: 81.3.5778.8669  
Graf-Zepplin-Str 14  
D-33181 Wuennenberg-Haaren  
Tel: 49.2957.79.1692  
Fax: 49.2957.79.9341  
Wintech Microeletronics  
Co., Ltd  
7F., No. 34, Sec. 3, Pateh Road  
Taipei, Taiwan, R.O.C.  
Tel: 886.2.2579.5858  
Shinki Electronics  
Myuru Daikanyama 3F  
3-7-3 Ebisu Minami  
Fax: 886.2.2570.3123  
Shibuya-ku, Tokyo 150-0022  
Tel: 81.3.3760.3110  
Fax: 81.3.3760.3101  
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