Intel Computer Hardware 80302 User Manual

Intel 80303 and 80302 I/O

Processors

Specification Update

May 6, 2003

Notice: The Intel 80303 and Intel 80302 I/O Processors processor may contain design defects

or errors known as errata. Characterized errata that may cause the product’s behavior to deviate

from pubished specifications are documented in this specification update.

Order Number: 273355-010

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Contents

Revision Histor y ......................................................................................... 5

Preface....................................................................................................... 7

Summary T a ble of Changes....................................................................... 8

Identification Information.......................................................................... 14

Errata ....................................................................................................... 16

Specification Changes ............................................................................. 23

Specification Clarification s ....................................................................... 25

Documentation Changes ......................................................................... 28

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This Page Intentionally Left Blank

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Revision History

Date

Version

Description

Added Errata 2.

05/01/03

010

Revised Specification Clarifications 4, 7 and 8.

Reworded Specification Clarification 4.

Added Specification Clarifications 7 and 8.

08/27/02

11/15/01

08/22/01

009

008

007

Added Specification Clarifications 5 and 6.

Added Document Changes 32 and 33.

Added Specification Clarification 4.

Added Document Changes 30 and 31.

Added Document Changes 25 through 29.

04/24/01

04/02/01

006

005

Revised Device ID Registers “A-2” Revision ID Registers data.

Added Note to Device ID Registers.

Added Specification Clarification 3.

Added Errata 1.

Added Specification Change 1.

03/22/01

004

Added Specification Clarifications 1 and 2.

Added Document Changes 13 through 24.

Updated Die Details Table and Device ID Registers for A-2 step.

02/23/01

08/2000

003

002

Die Details and Device ID Registers tables, corrected stepping A-0 to A-1.

Updated Die Details Table.

Revised Device ID Registers Table.

Added Document Changes 1 through 12.

This is the new Specification Update document. It contains all identified errata published

prior to this date.

06/2000

001

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Preface

This document is an update to the specifications contained in the Affected Documents/Related

Documents table below. This document is a compilation of device and documentation errata,

specification clarifications and changes. It is intended for hardware system manufacturers and

software developers of applications, operating systems, or tools.

Information types defined in Nomenclature are consolidated into the specification update and are

no longer published in other documents.

This document may also contain information that was not previously published.

Affected Documents/Related Documents

Title

Intel^®80303 I/O Processor Developer’s Manual

Intel^®80303 I/O Processor Data Sheet

Order #

273353

273358

273308

Intel^®80303 I/O Processor Design Guide

Nomenclature

Errata are design defects or errors. These may cause the Intel 80303 and Intel 80302 I/O

Processors behavior to deviate from published specifications. Hardware and software designed to

be used with any given stepping must assume that all errata documented for that stepping are

present on all devices.

Specification Changes are modifications to the current published specifications. These changes

will be incorporated in any new release of the specification.

Specification Clarifications describe a specification in greater detail or further highlight a

specification’s impact to a complex design situation. These clarifications will be incorporated in

any new release of the specification.

Documentation Changes include typos, errors, or omissions from the current published

specifications. These will be incorporated in any new release of the specification.

Note: Errata remain in the specification update throughout the product’s lifecycle, or until a particular

stepping is no longer commercially available. Under these circumstances, errata removed from the

specification update are archived and available upon request. Specification changes, specification

clarifications and documentation changes are removed from the specification update when the

appropriate changes are made to the appropriate product specification or user documentation

(datasheets, manuals, etc.).

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Summary Table of Changes

The following table indicates the errata, specification changes, specification clarifications, or

documentation changes which apply to the Intel 80303 and Intel 80302 I/O Processors product.

Intel may fix some of the errata in a future stepping of the component, and account for the other

outstanding issues through documentation or specification changes as noted. This table uses the

following notations:

Codes Used in Summary Table

Stepping

Errata exists in the stepping indicated. Specification Change or

Clarification that applies to this stepping.

(No mark)

or (Blank box):

This erratum is fixed in listed stepping or specification change does not

apply to listed stepping.

Page

(Page):

Page location of item in this document.

Status

Doc:

Document change or update will be implemented.

This erratum is intended to be fixed in a future step of the component.

This erratum has been previously fixed.

Fix:

Fixed:

NoFix:

Eval:

There are no plans to fix this erratum.

Plans to fix this erratum are under evaluation.

Row

Change bar to left of table row indicates this erratum is either new or

modified from the previous version of the document.

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Summary Table of Changes

Errata

Steppings

No.

Page

Status

Errata

A-0

A-1

A-2

Single-bit and Multi-bit Error Reporting Cannot Be

Individually Enabled by ECC Control Register

NoFix

Instruction Sequence Can Scoreboard a Register

Indefinitely

Specification Changes

Steppings

No.

Page

Status

Specification Changes

A-2

#-#

Doc

Summary of the Intel® 80302 I/O Processor

Specification Clarifications

Steppings

No.

Page

Status

Specification Clarifications

A-0

A-1

A-2

Doc

ECC is Always Enabled

32-bit SDRAM is Not Supported

Non-Battery Backup Systems

POCCDR and SOCCDR Functionality

‘Bus Hold’ Devices on the RAD Bus

SREQ64# Functionality

PCI Local Bus Specification, Revision 2.3 Compliancy

DMA and AAU End of Chain Functionality

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Summary Table of Changes

Documentation Changes

No. Document Revision

Page

Status

Documentation Changes

Title Page revision number

272353-001

Doc

Figure 9-3 on pg 9-9 did not print correctly

Figure 13-22 on pg 13-40 did not print correctly

Figure 13-18, pg 13-35

Figure 15-2 on pg 15-3 did not print correctly

Incorrect Vendor ID in ATU register

Section 23.2 on pg 23-2 has incorrect text

T a ble 24-4 on pg 24-8 is incorrect

Figure 25-1 on pg 25-1 has incorrect data

Section 25.1.3 on page 25-2

Figure 25-2 on pg 25-2 did not print correctly

T a ble 25-2 on page 25-3 did not print completely

Section 1.2.2 on page 1-2 has incorrect data

Figure 12-2 on page 12-10 has incorrect data

Section 19.1 on page 19-1 has incorrect data

T a ble 14-46 on page 14-109 has missing data

Section 13.2.4.3 on page 13-30 has incorrect data

Figure 15-3 on page 15-7 has missing text

Section 15.7.39 on page 15-100 has incorrect data

T a ble 8-17 on page 8-38 has incorrect data

Section 11.2.8 on page 11-5 has incorrect data

Section 13.2.3.1 on page 13-13 has incorrect data

T a ble 13-4 on page 13-9 has incorrect data

T a ble 8-15 on page 8-36 needs clarification

T a ble 13-13 on page 13-30 has incorrect data

Section 13.2.4.3, First Paragraph after T a ble 13-13 has

Incorrect Data

272353-001

Doc

Section 13.2.4.3, First Paragraph after “Current” Figure

13-16. H-Matrix has Incorrect Data

272353-001

Doc

Section 11.3.1.5 FAIL# Code

Section 13.5 Reset Conditions has Incorrect Data

Section 13.2.4.2, First Sentence has Incorrect Data

Section 13.6.2, Second Sentence has Incorrect Data

Section 4.5.2 on page 50 is only correct for A-0 and A-1

steppings

272358-007

272353-001

Doc

Section 17.5.1 on page 17-12 is only correct for A-0 and

A-1 steppings

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Identification Information

Markings

Topside Markings

GC80303

SSSSSS

MALAY

FFFFFFFF-[{SN}]

INTEL

Intel 80303 I/O Processor

Die Details

Intel^®

QDF/

Spec

Number

i960^®Core

Processor

Speed

Voltage

(V)

Part Number

Stepping

Notes

(MHz)

GC80303

A-0

A-1

Q176

Q196

3.3

100

Samples - limited testing

Production

GC80303

Q189

SL4Q4

Production - Yield

GC80303

GC80302

A-2

SL57T

Q229

3.3

100

improvement only, no

functionality changes.

Samples - limited testing,

66 MHz internal bus and

SDRAM memory interface.

Production - 66 MHz internal

bus and SDRAM memory

interface.

SL5HS

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Identification Information

Device ID Registers

Address

Translation Unit

Revision ID

(ATURID - 0x1208)

Processor

Device ID

PCI-to-PCI

Bridge Unit

Revision ID

Intel^®i960^®Core Processor

Device ID

(DEVICEID - 0xFF00 8710)

Device and

Stepping

(PDIDR - 0x1710) (RIDR - 0x1008)

80303 A-0

80303 A-1

80303 A-2

80302 A-2

08879013

18879013

18878013

0x00

0x01

0x00

0x01

00823013

NOTE: There are no functionality differences between the A-1 and A-2 steppings of the 80303. Therefore, the

Device IDs are the same.

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Errata

Single-bit and Multi-bit Error Reporting Cannot Be Individually Enabled by

ECC Control Register

Problem:

The ECC Control Register ECCR is described as having the ability to select multi-bit error and/or

single-bit error reporting (see Table 13-24 on page 13-31 of the Intel 80303 I/O Processor

Developer’s Manual). However, the algorithm does not allow individual enabling; that is, the

reporting is either on or off for both multi-bit and single bit error reporting.

Implication:

The error reporting selection (enabled or disabled) will apply to both multi-bit and single-bit errors.

Workaround: There is no current workaround. If either the ECCR.0 bit or the ECCR.1 bit is selected for

reporting, then both multi-bit and single-bit error reporting are enabled. If neither bit is selected for

reporting, then both multi-bit and single-bit error reporting are disabled.

Status:

NoFix. See the T a ble “Summary Table of Changes” on page 7.

Instruction Sequence Can Scoreboard a Register Indefinitely

Problem:

accessing registers for which there is an outstanding operation (see section 3.2.3 in the Intel

80303 I/O Processor Developer’s Manual).

An instruction sequence that coincides with some specific instruction cache conditions can

scoreboard a local or global register indefinitely. When this happens, processing can stall at the

next access to that register, awaiting a scoreboard release that does not come. In that case, external

bus accesses cease.

A hardware reset is the only way to release the scoreboard.

The following three conditions are required to scoreboard a register:

1. Execution of the following three-instruction sequence:

a. emul

b. ld, ldos, ldis, ldob, or ldib

c. mulo or muli

Only two-word, MEMB format load instructions that execute in two clock cycles cause the

failure. Table 1 lists all the versions of these instructions that can produce this failure. Any

version can be used for each instruction and still produce the failure as long as the sequential

order is maintained.

2. The emul must appear at address 0xXXXXXXX8.

3. Instruction caching must be enabled. The emul instruction must be fetched from external

memory along with the first word of the load instruction. Also, the second word of the load

and the multiply instruction must already reside in cache. To accomplish this, the code must

have run once in order to load the instructions into cache followed by code which causes the

invalidation of the cache line containing the emul instruction. At this point, re-execution of the

code sets up the failure condition.

Once the failure condition occurs, the processor will continue code execution until an instruction

using the scoreboarded register is encountered, then indefinite processor stall will occur.

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Errata

Nominally, the emul multiplies two 32-bit operands to produce a long ordinal (64-bit) result stored

in two adjacent registers. When the errata occurs, the low-order register receives the correct value,

but the high-order register becomes scoreboarded indefinitely. The scoreboarded register is always

odd-numbered (i.e., g1, g3, g5, ..., r7, r9, r11, ...) since the emul instruction always directs the

high-order result to the odd-numbered register of the destination pair.

In some cases, the result of the mulo or muli instruction is corrupted, too, but such has never been

observed apart from the scoreboard failure. Once the scoreboard failure has occurred, subsequent

mulo or muli instructions that are separated by load instructions can also produce faulty results in

some cases. The details of this secondary behavior has not been studied as thoroughly as the

primary scoreboarding issue.

When the scoreboard stalls the processor, higher-level processes, such as higher-priority interrupts

and faults, can run as normal unless they access the scoreboarded register and also stall.

Not all 80303 processors have been observed to exhibit this errata.

Table 1.

Instruction Versions that Can Produce a Scoreboard Failure in this Sequence

Instruction

Data Type

Addressing Mode

Format

1. Extended

Multiply

All

n/a

emul reg/lit, reg/lit, reg

2. Load

ld exp, reg

ld exp(reg), reg

ld exp[reg*scale], reg

ldos exp, reg

ldos exp(reg), reg

ldos exp[reg*scale], reg

•

Absolute

Displacement

•

Word - ld

Ordinal short - ldos

Integer short - ldis

Ordinal byte - ldob

Integer byte - ldib

ldis exp, reg

Displacement

ldis exp(reg), reg

ldis exp[reg*scale], reg

Index with

Displacement

ldob exp, reg

ldob exp(reg), reg

ldob exp[reg*scale], reg

ldib exp, reg

ldib exp(reg), reg

ldib exp[reg*scale], reg

3. Multiply

•

Ordinal

Integer

mulo reg/lit, reg/lit, reg

muli reg/lit, reg/lit, reg

n/a

Implication:

Systems containing this instruction sequence may exhibit sporadic and unrepeatable stall failures

depending on where these instructions appear in the executable memory image and the runtime

dynamics as they affect the Icache.

Workaround: Avoid this sequence of instructions in systems that employ the instruction cache.

Status:

NoFix. Refer to Summary Table of Changes to determine the affected stepping(s).

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Specification Changes

Summary of the Intel® 80302 I/O Processor

Problem:

The Intel® 80302 I/O processor is based on the A-2 stepping of the Intel® 80303 I/O processor.

The 80302 I/O processor is identical to the 80303 I/O processor, except the SDRAM and internal

bus run at 66 MHz. For applications that use the I C unit, the I C clock is generated from the

internal bus clock, so the ICCR (I C Clock Count Register) needs to be properly adjusted.

The Device ID Register (DIDR; 1002H), in the Bridge configuration header, is 0308H for the

80302 I/O processor.

The ATU Device ID Register (ATUDID; 1202H), in the ATU configuration header, is 5308H for

the 80302 I/O processor.

The 80303 I/O processor manual, datasheet and design guide should be used when designing with

the 80302 I/O processor.

Status:

The 80302 I/O processor will be introduced with the A-2 stepping.

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Specification Clarifications

ECC is Always Enabled

Problem:

ECC is always enabled, therefore do not design an Intel® 80303 I/O processor based product

without ECC implemented, this causes severe system errors. On the Intel® 80960RM/RN I/O

processors, ECCR.3 can be cleared to disable ECC, but with the 80303 I/O processor, ECCR.3 is

reserved.

32-bit SDRAM is Not Supported

Problem:

The memory controller on the 80303 I/O processor supports between 32 and 512 Mbytes of 64-bit

SDRAM, but 32-bit SDRAM is not supported. On the 80960RM/RN I/O processors, 32-bit

memory was selected by the 32BITMEM_EN# pin (multiplexed on RAD[2]), and by reading a '0'

from SDCR.2, this would indicate a 32-bit data bus width. But, for the 80303 I/O processor the

32BITMEM_EN# pin does not exist and SDCR.2 is reserved.

Non-Battery Backup Systems

Problem:

Applications that do not support battery back-up should follow these recommendations:

1. Pull the PWRDELAY pin low through a 1.5K pulldown. Pulling it low has the effect of

keeping the power fail state machine in reset, therefore not allowing the power fail sequence to

ever occur.

2. Pull the CKE pins high on the SDRAMs, and leave the SCKE signals on the 80303 as 'no

connects'. This keeps the SDRAM from entering a pseudo, self-refresh mode which can cause

a lock-up condition on the SDRAM device.

POCCDR and SOCCDR Functionality

Problem:

The Primary Outbound Configuration Cycle Data Register (POCCDR) and Secondary Outbound

Configuration Cycle Data Register (SOCCDR) are used to initiate configuration cycles to PCI

target devices. On page 15-57, Table 15-26 in the Intel 80303 I/O Processor Developer’s Manual,

these registers are stated as “Not Available in PCI Configuration Space”.

To clarify, when these registers are either read or written via PCI during a scan of configuration space,

an unwanted configuration cycle is initiated by the 80303 to the address held in the Primary

Outbound Configuration Cycle Address Register (POCCAR) or Secondary Outbound Configuration

Cycle Address Register (SOCCAR) based on a read or write to POCCDR or SOCCDR respectively.

An invalid address causes the 80303 to signal a master abort. Only the first 64 bytes in the ATU

Configuration Header is read during configuration. Any thing above 64 bytes up to 256 bytes is

defined as device-specific and not accessed by a master. This does not have to rule out access by any

master, only a master which does not have knowledge of the device-specific registers.

‘Bus Hold’ Devices on the RAD Bus

Problem:

There are six user mode configuration pins (RST_MODE#, ONCE#, STEST, RETRY, SPMEM#

and 32BITPCI_EN#) and three test mode configuration pins (on RAD8, 7 and 0) that are

multiplexed on the RAD[8:0] signals. All these signals have internal pull-ups, so there is no need

for external pull-ups. But, if the application requires an active low signal, then an external

pull-down needs to be added. The configuration signals are latched on the rising edge of P_RST#.

Devices with a ‘bus hold’ feature (i.e., CPLD) connected to the RAD bus may pull the RAD[8:0]

signals low at the rising edge of P_RST#, causing the 80303 to enter an undesired mode. 80303

designs that use ‘bus hold’ devices should either turn off the ‘bus hold’ feature or verify that proper

signal levels are being maintained at the rising edge of P_RST#.

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Specification Clarifications

SREQ64# Functionality

Problem:

There is an SREQ64# functionality difference between the A-1 and A-2 steppings of the 80303 I/O

processors. (This functionality is also on the 80302 since it is based on the A-2 stepping.) During

the power up sequence, the S_REQ64# signal is sampled by PCI devices on the secondary PCI bus

to determine 64-bit or 32-bit PCI operation. On the A-1 stepping, S_REQ64# is deasserted one

P_CLK after the deassertion of S_RST# (as stated in the Developer's Manual and Datasheet). On

the A-2 stepping, SREQ64# is deasserted approximately 600ps after the deassertion of S_RST#.

The PCI Local Bus Specification, Revision 2.2 has a setup and hold specification for REQ64# with

respect to RST#. Even though the Intel Datasheets and Developer's Manuals state that,

“S_REQ64# is deasserted one P_CLK after the deassertion of S_RST#”, the PCI Local Bus

Specification, Revision 2.2 states that the RST# to REQ64# hold time is 0-50ns. Since the RST# to

REQ64# hold time can be zero, compliant devices should be sampling REQ64# during the

REQ64# to RST# setup time which is a minimum of 10 clock cycles. (see pages 128 and 135,

table 4-6 and figure 4-11 of the PCI Local Bus Specification, Revision 2.2)

The implication of this change is that some 64-bit PCI devices on the secondary PCI bus only

works in 32-bit PCI mode. This could be due to using a non-PCI compliant device or because of

trace delays between the S_RST# and S_REQ64# signals. Verify proper functionality on 80303

A-2 designs. The processor stepping identification is listed page 10. Also see Documentation

Changes #32 and 33 for corrections to the datasheet and manual.

PCI Local Bus Specification, Revision 2.3 Compliancy

Problem:

The Intel 80303 I/O processor (80303) was designed to be compliant with the PCI Local Bus

Specification, Revision 2.2. (This functionality is also on the 80302 since it is based on the A-2

stepping.). Since the release of the 80303, the PCI Special Interest Group has released a new

specification revision, PCI Local Bus Specification, Revision 2.3. There are no plans to step the

80303 to make it compliant with the PCI Local Bus Specification, Revision 2.3.

DMA and AAU End of Chain Functionality

Problem:

There is a case where a race condition occurs between the End of Chain (EOC), Channel Active

(CA) and resume bit, which causes a bogus EOC. The Intel 80303 I/O processor (80303) (this

functionality is also on the 80302 since it is based on the A-2 stepping.) asserts the EOC bit when

the NDAR is zero, even when the chain resume bit is set. When the resume bit is set, the CA bit is

cleared for one cycle and then set again, modifying the CA and EOC at the same time.

Consider the case when a chain has been added to the list after the last descriptor is read by the

DMA. In this case, the resume bit gets set by software. The EOC occurs because the NDAR was

zero when read and the CA bit is momentarily cleared. The DMA processes the resume and sets the

CA bit again. It remains active until it again reaches an NDAR of 0.

One way to handle this condition, is for the software to track the last descriptor believed to be in

memory. To compare the NDAR and DAR in the DMA descriptor MMR space, to see when they

are 0, and are the last expected DAR. In this situation, the DMA is already idle and the CA bit is

clear. When not, ignore the EOC interrupt. A bogus EOC is detected when NDAR is not 0 and

resume is set.

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Documentation Changes

Title Page revision number

Issue:

Manual indicates Revision 0.5.

Implication:

This type of revision numbering is not used with published documents. Refer to the Document

Number 272353-001. The extension -001 is the correct revision number for this document.

Workaround: Ignore revision number 0.5.

Affected Docs: Intel 80303 I/O Processor Developer’s Manual.

Figure 9-3 on pg 9-9 did not print correctly

Problem:

Figure 9-3 on pg 9-9 did not print correctly.

Workaround: Replace Figure 9-3 with the following:

Intel 80960

Local Bus Address

Was

NFP-96 NFP-(n+1)*32

Fault Data

NFP-88 NFP-24-n*32

NFP-84

NFP-20-n*32

NFP-76 NFP-12-n*32

FSUBTYPE (N)

FTYPE (N)

NFP-72

NFP-68

NFP-8-n*32

NFP-4-n*32

Address of Faulting Instruction (n)

NFP-64 NFP-64

Resumption Information

NFP-52

NFP-48

NFP-44

Override Fault Data

Fault Data

NFP-32

NFP-20

NFP-16

OTYPE

OSUBTYPE

Process Controls

NFP-12

Arithmetic Controls

FTYPE (1)

FSUBTYPE (1)

NFP-8

NFP-4

Address of Faulting Instruction (1)

Note: "NFP" means New Frame Pointer

Reserved

A6406-01

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Documentation Changes

Figure 13-22 on pg 13-40 did not print correctly

Figure 13-22 on pg 13-40 did not print correctly.

Problem:

Workaround: Replace Figure 13-22 with the following:

out

SCKE

PULLCKE = 1

PULLCKE = 0

P_RST#

A6814-01

Affected Docs: Intel 80303 I/O Processor Developer’s Manual.

Figure 13-18, pg 13-35

Problem:

Replace Figure 13-18 with the following:

I_CLK

SDQ(71:0)

DQ(71:0)

P_CLK

DCLKout

DCLKin

CLK(3:0)

SDRAM

DIMM0

SDRAM

DIMM1

A4662-02

Affected Docs: Intel 80303 I/O Processor Developer’s Manual.

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Documentation Changes

Figure 15-2 on pg 15-3 did not print correctly

Problem:

Figure 15-2 on pg 15-3 did not print correctly.

Workaround: Replace Figure 15-2 with the following:

Primary ATU

P_ORQ 16 Bytes

P_OWQ 16 Bytes

P_OTQ

P_IWQAD

P_IWQ 256 Bytes

P_IRQ 256 Bytes

P_ITQ1

P_ITQ2

P_IDWQ

8 Bytes

PCI-to-PCI

Bridge

Secondary ATU

S_ORQ 16 Bytes

S_OWQ 16 Bytes

S_OTQ

S_IWQAD

S_IWQ 256 Bytes

S_IRQ 256 Bytes

S_ITQ1

S_ITQ2

A6490-01

Affected Docs: Intel 80303 I/O Processor Developer’s Manual.

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Documentation Changes

Incorrect Vendor ID in ATU register

The value for the Vendor ID register (ATUVID) is incorrect.

Problem:

Workaround: Replace Table 15-28 on page 15-60 with the following table:

IOP

Attributes

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

PCI

Attributes

ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro

Intel^®i960^®Core Local Bus Address

1200H

PCI Configuration Address Offset

00H - 01H

Attribute Legend:

RV = Reserved

PR = Preserved

RS = Read/Set

RW = Read/Write

RC = Read Clear

RO = Read Only

NA = Not Accessible

Bit

Default

Description

ATU Vendor ID - This is a 16-bit value assigned to Intel. This register, combined with the DID, uniquely

identify the PCI device. Access type is Read/Write to allow the 80303 I/O processor to configure the

existing application software.

15:00

8086H

Affected Docs: Intel 80303 I/O Processor Developer’s Manual.

Section 23.2 on pg 23-2 has incorrect text

Problem:

The text and register descriptions in section 23.2 are incorrect.

Workaround: Replace Section 23.2 Register Definitions with the following:

All three GPIO registers are visible as 80303 I/O processor memory mapped registers and can be

accessed through the internal memory bus. Each is a 8-bit register and is memory-mapped in the

80303 processor memory space. The memory-mapped addresses of the GPIO control registers are

found in Appendix C, “Peripheral Memory-Mapped Registers.”

There are four control and status registers for the PCI And Peripheral Interrupt Controller:

• GPIO Output Enable Register

• GPIO Input Data Register

• GPIO Output Data Register

Affected Docs: Intel 80303 I/O Processor Developer’s Manual.

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Table 24-4 on pg 24-8 is incorrect

Problem:

Table 24-4 on pg 24-8 is incorrect.

Workaround: Replace Table 24-4 with the following table:

Table 24-4. Intel® 80303 I/O Processor Boundary Scan Register Bit Order (Sheet 1 of 10)

Cell Type

Name

scl,

Function Safe bit Control Signal

Disable Value

Disable Result

(CBSC_1,

(BC_1,

bidir,

Z)," &

control,

bidir,

1)," &

(CBSC_1,

(BC_1,

sda,

Z)," &

control,

1)," &

(BC_1,

rale,

output3, X,

111,

Z)," &

(BC_1,

roez,

rad(15),

(CBSC_1,

(BC_1,

bidir,

control,

0)," &

(BC_1,

rcez(1),

output3, X,

Z)," &

(BC_1,

control,

0)," &

"10

"11

"12

"13

"14

"15

"16

"17

"18

"19

"20

"21

"22

"23

"24

"25

"26

"27

"28

"29

"30

"31

"32

"33

"34

"35

"36

"37

"38

"39

"40

"41

(BC_1,

rcez(0),

output3, X,

11,

(BC_1,

control,

bidir,

0)," &

(CBSC_1,

(BC_1,

rad(6),

rwez,

rad(9),

rad(10),

28,

111,

18,

16,

Z)," &

output3, X,

(CBSC_1,

(BC_1,

bidir,

control,

bidir,

0)," &

(CBSC_1,

(BC_1,

rad(11),

18,

20,

22,

Z)," &

control,

bidir,

0)," &

(CBSC_1,

(BC_1,

rad(13),

control,

bidir,

0)," &

(CBSC_1,

(BC_1,

rad(12),

control,

bidir,

0)," &

(CBSC_1,

(BC_1,

rad(8),

rad(14),

28,

25,

Z)," &

bidir,

control,

bidir,

0)," &

(CBSC_1,

(BC_1,

rad(2),

rad(1),

28,

Z)," &

bidir,

control,

bidir,

1)," &

(CBSC_1,

(BC_1,

rad(16),

30,

Z)," &

control,

bidir,

0)," &

(CBSC_1,

(BC_4,

rad(0),

rad(5),

rad(4),

rad(3),

nc1,

28,

Z)," &

bidir,

input,

bidir,

X)," &

(CBSC_1,

(BC_1,

rad(7),

GPIO(0),

28,

38,

Z)," &

bidir,

control,

bidir,

1)," &

(CBSC_1,

(BC_1,

GPIO(1),

40,

42,

Z)," &

control,

bidir,

1)," &

(CBSC_1,

GPIO(2),

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Table 24-4. Intel® 80303 I/O Processor Boundary Scan Register Bit Order (Sheet 2 of 10)

Cell Type

Name

Function Safe bit Control Signal

control, 1)," &

output3, X,

Disable Value

Disable Result

"42

"43

"44

"45

"46

"47

"48

"49

"50

"51

"52

"53

"54

"55

"56

"57

"58

"59

"60

"61

"62

"63

"64

"65

"66

"67

"68

"69

"70

"71

"72

"73

"74

"75

"76

"77

"78

"79

"80

"81

"82

"83

"84

"85

"86

"87

"88

(BC_1,

(CBSC_1,

(BC_1,

(CBSC_1,

(BC_1,

(CBSC_1,

(BC_1,

(CBSC_1,

(BC_1,

(CBSC_1,

(BC_1,

(BC_4,

(BC_1,

(BC_4,

(BC_1,

(BC_4,

(BC_1,

(BC_4,

(BC_1,

i_rstz,

GPIO(3),

111,

45,

Z)," &

bidir,

control,

bidir,

1)," &

GPIO(4),

47,

49,

51,

53,

Z)," &

control,

bidir,

1)," &

GPIO(5),

control,

bidir,

1)," &

GPIO(6),

control,

bidir,

1)," &

GPIO(7),

control,

input,

1)," &

X)," &

irqz(0),

irqz(1),

irqz(2),

irqz(3),

irqz(4),

irqz(5),

nc2,

output3, X,

65,

Z)," &

lcdinitz,

logic1,

failz,

input,

X)," &

output3, X,

X)," &

110,

nmiz,

input,

control,

input,

1)," &

X)," &

nc3,

nc4,

nc5,

nc6,

nc7,

nc8,

nc9,

nc10,

nc11,

nc12,

nc20,

nc13,

nc15,

nc14,

nc16,

pwrdelay, input,

nc17,

nc19,

nc18,

output3, X,

65,

85,

Z)," &

control,

1)," &

dclk(3),

dclk(2),

dclk(1),

output3, X,

111,

Z)," &

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Table 24-4. Intel® 80303 I/O Processor Boundary Scan Register Bit Order (Sheet 3 of 10)

Cell Type

Name

Function Safe bit Control Signal

Disable Value

Disable Result

"89

"90

"91

"92

"93

"94

"95

"96

"97

"98

"99

(BC_1,

dclk(0),

dclkout,

dq(35),

dq(0),

output3, X,

111,

95,

Z)," &

(BC_1,

(CBSC_1,

(BC_1,

bidir,

control,

bidir,

control,

bidir,

control,

bidir,

control,

bidir,

93,

0)," &

(CBSC_1,

(BC_1,

dq(32),

95,

Z)," &

0)," &

(CBSC_1,

dq(2),

dq(36),

dq(33),

dq(1),

dq(34),

dq(37),

dq(4),

dq(39),

dq(41),

dq(38),

dq(3),

dq(43),

93,

95,

93,

95,

93,

95,

93,

108,

Z)," &

"100 (CBSC_1,

"101 (CBSC_1,

"102 (CBSC_1,

"103 (CBSC_1,

"104 (CBSC_1,

"105 (CBSC_1,

"106 (CBSC_1,

"107 (CBSC_1,

"108 (BC_1,

0)," &

"109 (CBSC_1,

"110 (BC_1,

dq(40),

95,

Z)," &

1)," &

"111 (BC_1,

"112 (CBSC_1,

"113 (CBSC_1,

"114 (CBSC_1,

"115 (CBSC_1,

"116 (CBSC_1,

"117 (CBSC_1,

"118 (CBSC_1,

"119 (CBSC_1,

"120 (CBSC_1,

"121 (CBSC_1,

"122 (CBSC_1,

"123 (CBSC_1,

"124 (CBSC_1,

"125 (CBSC_1,

"126 (CBSC_1,

"127 (CBSC_1,

"128 (CBSC_1,

"129 (CBSC_1,

"130 (BC_1,

dq(5),

dq(6),

dq(8),

dq(42),

dq(7),

dq(45),

dq(44),

dq(9),

dq(47),

dq(12),

dq(10),

dq(11),

dq(46),

dq(14),

dq(13),

scb(5),

dq(15),

scb(4),

sdqm(4),

scasz,

scb(0),

swez,

scb(1),

sdqm(0),

202,

204,

202,

204,

202,

204,

202,

204,

202,

200,

202,

200,

205,

200,

205,

200,

205,

Z)," &

output3, X,

"131 (BC_1,

"132 (CBSC_1,

"133 (BC_1,

bidir,

output3, X,

bidir, X,

output3, X,

"134 (CBSC_1,

"135 (BC_1,

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Table 24-4. Intel® 80303 I/O Processor Boundary Scan Register Bit Order (Sheet 4 of 10)

Cell Type

Name

Function Safe bit Control Signal

Disable Value

Disable Result

"136 (BC_1,

"137 (BC_1,

"138 (BC_1,

"139 (BC_1,

"140 (BC_1,

"141 (BC_1,

"142 (BC_1,

"143 (BC_1,

"144 (BC_1,

"145 (BC_1,

"146 (BC_1,

"147 (BC_1,

"148 (BC_1,

"149 (BC_1,

"150 (BC_1,

"151 (BC_1,

"152 (BC_1,

"153 (BC_1,

"154 (BC_1,

"155 (BC_4,

"156 (BC_1,

"157 (BC_1,

"158 (BC_1,

"159 (BC_1,

"160 (BC_1,

"161 (CBSC_1,

"162 (CBSC_1,

"163 (BC_1,

"164 (BC_1,

"165 (CBSC_1,

"166 (CBSC_1,

"167 (CBSC_1,

"168 (CBSC_1,

"169 (CBSC_1,

"170 (CBSC_1,

"171 (CBSC_1,

"172 (CBSC_1,

"173 (CBSC_1,

"174 (CBSC_1,

"175 (CBSC_1,

"176 (CBSC_1,

"177 (BC_1,

"178 (CBSC_1,

"179 (CBSC_1,

"180 (CBSC_1,

"181 (CBSC_1,

"182 (CBSC_1,

scez(1),

sdqm(5),

sdqm(1),

scez(0),

sa(0),

output3, X,

205,

Z)," &

srasz,

sa(1),

sa(2),

sa(4),

sa(3),

sa(5),

sa(6),

sa(8),

sa(7),

sa(9),

sba(0),

sa(11),

sa(10),

sba(1),

dclkin,

input,

X)," &

sa(12),

sdqm(2),

sdqm(3),

scke(0),

sdqm(6),

scb(2),

scb(3),

sdqm(7),

sa(13),

scb(6),

dq(16),

dq(17),

scb(7),

dq(48),

dq(18),

dq(49),

dq(19),

dq(50),

dq(20),

dq(51),

dq(21),

scke(1),

dq(22),

dq(52),

dq(23),

dq(53),

dq(24),

output3, X,

205,

200,

205,

200,

201,

200,

204,

201,

204,

201,

204,

201,

204,

201,

205,

201,

204,

201,

204,

201,

Z)," &

bidir,

output3, X,

bidir,

output3, X,

bidir,

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Table 24-4. Intel® 80303 I/O Processor Boundary Scan Register Bit Order (Sheet 5 of 10)

Cell Type

Name

Function Safe bit Control Signal

Disable Value

Disable Result

"183 (CBSC_1,

"184 (CBSC_1,

"185 (CBSC_1,

"186 (CBSC_1,

"187 (CBSC_1,

"188 (CBSC_1,

"189 (CBSC_1,

"190 (CBSC_1,

"191 (CBSC_1,

"192 (CBSC_1,

"193 (CBSC_1,

"194 (CBSC_1,

"195 (CBSC_1,

"196 (CBSC_1,

"197 (CBSC_1,

"198 (CBSC_1,

"199 (CBSC_1,

"200 (BC_1,

dq(54),

dq(55),

dq(25),

dq(26),

dq(56),

dq(27),

dq(57),

dq(28),

dq(59),

dq(58),

dq(30),

dq(29),

dq(60),

dq(61),

dq(31),

dq(62),

dq(63),

bidir,

204,

201,

204,

201,

204,

201,

204,

201,

204,

201,

204,

Z)," &

bidir,

control,

0)," &

1)," &

"201 (BC_1,

"202 (BC_1,

"203 (BC_1,

"204 (BC_1,

"205 (BC_1,

"206 (CBSC_1,

"207 (CBSC_1,

"208 (CBSC_1,

"209 (CBSC_1,

"210 (CBSC_1,

"211 (CBSC_1,

"212 (CBSC_1,

"213 (CBSC_1,

"214 (CBSC_1,

"215 (CBSC_1,

"216 (CBSC_1,

"217 (CBSC_1,

"218 (CBSC_1,

"219 (CBSC_1,

"220 (CBSC_1,

"221 (CBSC_1,

"222 (CBSC_1,

"223 (CBSC_1,

"224 (CBSC_1,

"225 (CBSC_1,

"226 (CBSC_1,

"227 (CBSC_1,

"228 (CBSC_1,

"229 (CBSC_1,

s_ad(38), bidir,

s_ad(34), bidir,

s_ad(42), bidir,

s_ad(36), bidir,

s_ad(33), bidir,

s_ad(32), bidir,

s_ad(40), bidir,

s_ad(37), bidir,

s_ad(46), bidir,

s_ad(35), bidir,

s_ad(44), bidir,

s_ad(39), bidir,

s_ad(41), bidir,

s_ad(50), bidir,

s_ad(48), bidir,

s_ad(45), bidir,

s_ad(47), bidir,

s_ad(54), bidir,

s_ad(43), bidir,

s_ad(49), bidir,

s_ad(52), bidir,

s_ad(53), bidir,

s_ad(51), bidir,

s_ad(58), bidir,

325,

324,

323,

Z)," &

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Table 24-4. Intel® 80303 I/O Processor Boundary Scan Register Bit Order (Sheet 6 of 10)

Cell Type

Name

Function Safe bit Control Signal

Disable Value

Disable Result

"230 (CBSC_1,

"231 (CBSC_1,

"232 (CBSC_1,

"233 (CBSC_1,

"234 (CBSC_1,

"235 (CBSC_1,

"236 (CBSC_1,

"237 (CBSC_1,

"238 (CBSC_1,

"239 (BC_1,

s_ad(56), bidir,

s_ad(57), bidir,

s_ad(55), bidir,

s_ad(60), bidir,

s_ad(59), bidir,

s_ad(62), bidir,

s_ad(61), bidir,

s_cbez(5), bidir,

322,

331,

239,

Z)," &

s_par64,

bidir,

control,

0)," &

"240 (CBSC_1,

"241 (CBSC_1,

"242 (BC_1,

s_cbez(4), bidir,

s_req64z, bidir,

331,

242,

Z)," &

control,

0)," &

"243 (CBSC_1,

"244 (CBSC_1,

"245 (CBSC_1,

"246 (BC_1,

s_ad(63), bidir,

s_cbez(7), bidir,

s_ack64z, bidir,

322,

331,

246,

Z)," &

control,

0)," &

"247 (CBSC_1,

"248 (CBSC_1,

"249 (CBSC_1,

"250 (CBSC_1,

"251 (CBSC_1,

"252 (CBSC_1,

"253 (CBSC_1,

"254 (CBSC_1,

"255 (CBSC_1,

"256 (CBSC_1,

"257 (CBSC_1,

"258 (CBSC_1,

"259 (BC_4,

s_ad(0),

s_ad(2),

bidir,

329,

331,

328,

329,

330,

329,

328,

Z)," &

s_cbez(6), bidir,

s_ad(8),

s_ad(3),

s_ad(4),

s_ad(7),

s_ad(1),

bidir,

s_cbez(0), bidir,

s_ad(5),

s_ad(6),

bidir,

s_ad(10), bidir,

s_m66en, input,

s_ad(12), bidir,

s_ad(11), bidir,

X)," &

"260 (CBSC_1,

"261 (CBSC_1,

"262 (CBSC_1,

"263 (CBSC_1,

"264 (CBSC_1,

"265 (BC_1,

328,

329,

328,

265,

Z)," &

s_ad(9),

bidir,

s_ad(14), bidir,

s_serrz,

bidir,

control,

0)," &

"266 (CBSC_1,

"267 (CBSC_1,

"268 (CBSC_1,

"269 (CBSC_1,

"270 (BC_1,

s_ad(15), bidir,

s_cbez(1), bidir,

s_ad(13), bidir,

328,

330,

328,

270,

Z)," &

s_par,

bidir,

control,

bidir,

0)," &

"271 (CBSC_1,

"272 (CBSC_1,

"273 (BC_1,

s_stopz,

s_perrz,

280,

273,

Z)," &

bidir,

control,

bidir,

0)," &

"274 (CBSC_1,

"275 (BC_1,

s_lockz,

275,

280,

Z)," &

control,

bidir,

0)," &

"276 (CBSC_1,

s_trdyz,

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Table 24-4. Intel® 80303 I/O Processor Boundary Scan Register Bit Order (Sheet 7 of 10)

Cell Type

Name

Function Safe bit Control Signal

Disable Value

Disable Result

"277 (CBSC_1,

"278 (BC_1,

"279 (CBSC_1,

"280 (BC_1,

"281 (CBSC_1,

"282 (BC_1,

"283 (CBSC_1,

"284 (CBSC_1,

"285 (CBSC_1,

"286 (CBSC_1,

"287 (CBSC_1,

"288 (CBSC_1,

"289 (CBSC_1,

"290 (CBSC_1,

"291 (CBSC_1,

"292 (CBSC_1,

"293 (CBSC_1,

"294 (CBSC_1,

"295 (CBSC_1,

"296 (CBSC_1,

"297 (CBSC_1,

"298 (CBSC_1,

"299 (CBSC_1,

"300 (CBSC_1,

"301 (BC_1,

"302 (BC_1,

"303 (BC_4,

"304 (BC_1,

"305 (BC_1,

"306 (BC_1,

"307 (BC_1,

"308 (BC_1,

"309 (BC_1,

"310 (BC_1,

"311 (BC_1,

"312 (BC_4,

"313 (BC_4,

"314 (BC_4,

"315 (BC_4,

"316 (BC_1,

"317 (BC_1,

"318 (BC_4,

"319 (BC_1,

"320 (BC_4,

"321 (BC_1,

"322 (BC_1,

"323 (BC_1,

s_framez, bidir,

278,

280,

282,

Z)," &

control,

0)," &

s_devselz, bidir,

Z)," &

control,

0)," &

s_irdyz,

bidir,

control,

0)," &

s_ad(16), bidir,

s_ad(18), bidir,

s_cbez(2), bidir,

s_ad(17), bidir,

s_ad(20), bidir,

s_ad(21), bidir,

s_ad(19), bidir,

s_ad(24), bidir,

s_ad(22), bidir,

s_ad(26), bidir,

s_ad(23), bidir,

s_cbez(3), bidir,

s_ad(28), bidir,

s_ad(25), bidir,

s_ad(30), bidir,

s_ad(27), bidir,

s_ad(29), bidir,

s_ad(31), bidir,

327,

330,

327,

326,

330,

326,

333,

321,

Z)," &

s_rstz,

s_holdaz, output3, X,

s_holdz, input, X)," &

s_gntz(0), output3, X,

output3, X,

321,

333,

332,

Z)," &

s_clk(0),

s_clk(1),

s_clk(2),

s_clk(3),

s_clk(4),

s_clk(5),

r_clkout,

r_clkin,

output3, X,

input,

X)," &

s_reqz(0), input,

s_reqz(1), input,

s_reqz(2), input,

X)," &

s_gntz(1), output3, X,

s_gntz(2), output3, X,

321,

Z)," &

s_reqz(3), input,

X)," &

s_gntz(3), output3, X,

321,

Z)," &

s_reqz(4), input,

X)," &

control,

0)," &

control,

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Table 24-4. Intel® 80303 I/O Processor Boundary Scan Register Bit Order (Sheet 8 of 10)

Cell Type

Name

Function Safe bit Control Signal

Disable Value

Disable Result

"324 (BC_1,

"325 (BC_1,

"326 (BC_1,

"327 (BC_1,

"328 (BC_1,

"329 (BC_1,

"330 (BC_1,

"331 (BC_1,

"332 (BC_1,

"333 (BC_1,

"334 (BC_1,

"335 (BC_4,

"336 (BC_1,

"337 (BC_1,

"338 (BC_1,

"339 (BC_1,

"340 (BC_4,

"341 (CBSC_1,

"342 (BC_4,

"343 (BC_1,

"344 (BC_1,

"345 (CBSC_1,

"346 (BC_1,

"347 (BC_1,

"348 (BC_1,

"349 (BC_1,

"350 (CBSC_1,

"351 (BC_1,

"352 (BC_1,

"353 (CBSC_1,

"354 (CBSC_1,

"355 (CBSC_1,

"356 (BC_4,

"357 (CBSC_1,

"358 (CBSC_1,

"359 (CBSC_1,

"360 (CBSC_1,

"361 (CBSC_1,

"362 (CBSC_1,

"363 (CBSC_1,

"364 (CBSC_1,

"365 (CBSC_1,

"366 (CBSC_1,

"367 (CBSC_1,

"368 (CBSC_1,

"369 (BC_1,

"370 (CBSC_1,

control,

0)," &

1)," &

s_gntz(4), output3, X,

337,

339,

Z)," &

s_reqz(5), input,

X)," &

s_gntz(5), output3, X,

control,

0)," &

p_intz(1), output3, X,

control,

input,

0)," &

X)," &

p_gntz,

p_ad(28), bidir,

p_rstz, input,

455,

344,

Z)," &

X)," &

p_intz(3), output3, X,

control,

0)," &

p_ad(30), bidir,

455,

347,

Z)," &

p_intz(2), output3, X,

*, control, 0)," &

p_intz(0), output3, X,

349,

Z)," &

control,

0)," &

p_ad(31), bidir,

455,

352,

Z)," &

p_reqz,

output3, X,

control,

0)," &

p_ad(26), bidir,

p_ad(29), bidir,

p_ad(22), bidir,

455,

454,

Z)," &

p_idsel,

input,

X)," &

p_ad(25), bidir,

p_ad(24), bidir,

p_ad(27), bidir,

p_ad(20), bidir,

p_ad(23), bidir,

p_cbez(3), bidir,

p_ad(21), bidir,

p_ad(18), bidir,

p_ad(19), bidir,

p_ad(16), bidir,

p_ad(17), bidir,

p_framez, bidir,

455,

454,

453,

454,

369,

Z)," &

control,

0)," &

p_cbez(2), bidir,

453,

Z)," &

Intel 80303 and 80302 I/O Processors Specification Update

Download from Www.Somanuals.com. All Manuals Search And Download.

Documentation Changes

Table 24-4. Intel® 80303 I/O Processor Boundary Scan Register Bit Order (Sheet 9 of 10)

Cell Type

Name

Function Safe bit Control Signal

Disable Value

Disable Result

"371 (CBSC_1,

"372 (CBSC_1,

"373 (BC_1,

p_stopz,

p_trdyz,

bidir,

373,

Z)," &

bidir,

control,

0)," &

p_devselz

"374 (CBSC_1,

bidir,

373,

376,

Z)," &

"375 (CBSC_1,

"376 (BC_1,

p_irdyz,

bidir,

control,

0)," &

"377 (CBSC_1,

"378 (CBSC_1,

"379 (BC_1,

p_ad(15), bidir,

452,

379,

Z)," &

p_par,

bidir,

control,

bidir,

0)," &

"380 (CBSC_1,

"381 (BC_1,

p_perrz,

381,

Z)," &

control,

input,

0)," &

X)," &

"382 (BC_4,

p_lockz,

"383 (CBSC_1,

"384 (CBSC_1,

"385 (CBSC_1,

"386 (CBSC_1,

"387 (BC_1,

p_ad(11), bidir,

p_ad(13), bidir,

p_cbez(1), bidir,

452,

453,

387,

Z)," &

p_serrz,

bidir,

control,

0)," &

"388 (CBSC_1,

"389 (CBSC_1,

"390 (CBSC_1,

"391 (CBSC_1,

"392 (CBSC_1,

"393 (BC_4,

p_cbez(0), bidir,

p_ad(9), bidir,

453,

452,

Z)," &

p_ad(12), bidir,

p_ad(14), bidir,

p_ad(10), bidir,

p_m66en, input,

X)," &

"394 (CBSC_1,

"395 (CBSC_1,

"396 (CBSC_1,

"397 (CBSC_1,

"398 (BC_4,

p_ad(6),

p_ad(4),

p_ad(8),

p_ad(7),

p_clk,

bidir,

input,

bidir,

452,

451,

Z)," &

X)," &

"399 (CBSC_1,

"400 (CBSC_1,

"401 (CBSC_1,

"402 (CBSC_1,

"403 (CBSC_1,

"404 (BC_1,

p_ad(2),

p_ad(5),

p_ad(3),

p_ad(0),

451,

404,

Z)," &

p_req64z, bidir,

control,

bidir,

0)," &

"405 (CBSC_1,

"406 (CBSC_1,

"407 (BC_1,

p_ad(1),

451,

407,

Z)," &

p_ack64z, bidir,

control,

0)," &

"408 (CBSC_1,

"409 (CBSC_1,

"410 (CBSC_1,

"411 (CBSC_1,

"412 (BC_1,

p_cbez(7), bidir,

p_cbez(5), bidir,

p_cbez(6), bidir,

450,

412,

Z)," &

p_par64,

bidir,

control,

0)," &

"413 (CBSC_1,

"414 (CBSC_1,

"415 (CBSC_1,

"416 (CBSC_1,

p_cbez(4), bidir,

p_ad(62), bidir,

p_ad(63), bidir,

p_ad(60), bidir,

450,

449,

Z)," &

Intel 80303 and 80302 I/O Processors Specification Update

Download from Www.Somanuals.com. All Manuals Search And Download.

Documentation Changes

Table 24-4. Intel® 80303 I/O Processor Boundary Scan Register Bit Order (Sheet 10 of 10)

Cell Type

Name

Function Safe bit Control Signal

Disable Value

Disable Result

"417 (CBSC_1,

"418 (CBSC_1,

"419 (CBSC_1,

"420 (CBSC_1,

"421 (CBSC_1,

"422 (CBSC_1,

"423 (CBSC_1,

"424 (CBSC_1,

"425 (CBSC_1,

"426 (CBSC_1,

"427 (CBSC_1,

"428 (CBSC_1,

"429 (CBSC_1,

"430 (CBSC_1,

"431 (CBSC_1,

"432 (CBSC_1,

"433 (CBSC_1,

"434 (CBSC_1,

"435 (CBSC_1,

"436 (CBSC_1,

"437 (CBSC_1,

"438 (CBSC_1,

"439 (CBSC_1,

"440 (CBSC_1,

"441 (CBSC_1,

"442 (CBSC_1,

"443 (CBSC_1,

"444 (CBSC_1,

"445 (CBSC_1,

"446 (BC_1,

p_ad(59), bidir,

p_ad(61), bidir,

p_ad(57), bidir,

p_ad(58), bidir,

p_ad(56), bidir,

p_ad(55), bidir,

p_ad(53), bidir,

p_ad(52), bidir,

p_ad(54), bidir,

p_ad(51), bidir,

p_ad(49), bidir,

p_ad(50), bidir,

p_ad(48), bidir,

p_ad(46), bidir,

p_ad(47), bidir,

p_ad(44), bidir,

p_ad(45), bidir,

p_ad(43), bidir,

p_ad(41), bidir,

p_ad(42), bidir,

p_ad(38), bidir,

p_ad(37), bidir,

p_ad(40), bidir,

p_ad(34), bidir,

p_ad(39), bidir,

p_ad(35), bidir,

p_ad(33), bidir,

p_ad(32), bidir,

p_ad(36), bidir,

449,

448,

447,

446,

Z)," &

control,

0)," &

0)" ;

"447 (BC_1,

control,

"448 (BC_1,

"449 (BC_1,

"450 (BC_1,

"451 (BC_1,

"452 (BC_1,

"453 (BC_1,

"454 (BC_1,

"455 (BC_1,

Affected Docs: Intel 80303 I/O Processor Developer’s Manual.

Intel 80303 and 80302 I/O Processors Specification Update

Download from Www.Somanuals.com. All Manuals Search And Download.

Documentation Changes

Figure 25-1 on pg 25-1 has incorrect data

The Internal bus in diagram shows 66 MHz bus speed. The actual bus speed is 100 MHz

Problem:

Workaround: Replace Figure 25-1 with the following:

Figure 25-1. Intel® 80303 I/O Processor Clocking Regions Diagram

Clock Region 3

Clock Region 2

Intel^®i960^®JN CPU 100 MHz

16K I-Cache

Memory

Controller

I²C

Unit

Application

Accelerator

4K D-Cache

Bus Interface Unit

800 MBs Internal Bus (100MHz/64-bit)

Primary

Secondary

Address

Translation

Unit

2 Channel

DMA

Controller

I²0

Messaging

Unit

1 Channel

DMA

Controller

Performance

Monitoring

Unit

Address

Translation

Unit

S_CLKOUT

[5:0]

R_CLKOUT

R_CLKIN

P_CLK

PCI - to - PCI

Bridge

Secondary PCI Bus

Secondary

Primary PCI Bus

6 Reg/Gnt Pairs

PCI Arbiter

Clock Region 1

Clock Region 4

A8053-01

Affected Docs: Intel 80303 I/O Processor Developer’s Manual

10.

Section 25.1.3 on page 25-2

Problem:

The third sentence of the first paragraph is incorrect. It states the maximum bus speed of the region

is 66 MHz. It is actually 100 MHz.

Workaround: Change the third sentence to the following:

“It supports clock frequencies up to a maximum of 100 MHz.”

Affected Docs: Intel 80303 I/O Processor Developer’s Manual

Intel 80303 and 80302 I/O Processors Specification Update

Download from Www.Somanuals.com. All Manuals Search And Download.

Documentation Changes

11.

Figure 25-2 on pg 25-2 did not print correctly

Figure 25-2 on pg 25-2 did not print correctly.

Problem:

Workaround: Replace Figure 25-2 with the following:

I_CLK

SDQ(71:0)

DQ(71:0)

P_CLK

DCLKout

DCLKin

CLK(3:0)

SDRAM

DIMM0

SDRAM

DIMM1

A4662-02

Affected Docs: Intel 80303 I/O Processor Developer’s Manual.

12.

Table 25-2 on page 25-3 did not print completely

Problem:

Table 25-2 on page 25-3 did not print completely

Workaround: Replace Table 25-2 with the following:

Input Clock

Region/Clock

Buffered/PLL P_M66EN

S_M66EN

Region 1: 1x P_CLK

Region 2: 3x P_CLK

Region 3: 3x P_CLK

Region 4: 1x P_CLK

Region 1: 1x P_CLK

Region 2: 3/2x P_CLK

Region 3: 3/2x P_CLK

Region 4: 1x P_CLK

Region 1: 1x P_CLK

Region 2: 3/2x P_CLK

Region 3: 3/2x P_CLK

Region 4: 1/2x P_CLK

Buffered

PLL

P_CLK = 33 MHz

PLL

Buffered

PLL

P_CLK = 66 MHz

PLL

Buffered

PLL

Buffered

NOTE: Combination of P_M66EN=0 and S_M66EN=1 is not supported by the Intel^®80303 I/O processor.

When P_M66EN=0, the 80303 I/O processor forces S_M66EN=0 ensuring the unsupported condition

never occurs.

Affected Docs: Intel 80303 I/O Processor Developer’s Manual

Intel 80303 and 80302 I/O Processors Specification Update

Download from Www.Somanuals.com. All Manuals Search And Download.

Documentation Changes

13.

Section 1.2.2 on page 1-2 has incorrect data

Problem:

The second sentence of the first paragraph is incorrect. It states the Internal Bus operates at

66 MHz. It is actually 100 MHz.

Workaround: Change the second sentence to the following:

“The Internal Bus operates at 100 MHz and is 64 bits wide.”

Affected Docs: Intel 80303 I/O Processor Developer’s Manual

14.

Figure 12-2 on page 12-10 has incorrect data

Problem:

The Internal bus in diagram shows 66 MHz bus speed. The actual bus speed is 100 MHz

Workaround: Replace Figure 12-2 with the following:

Figure 12-2. Core Processor/BIU Interface Block Diagram

100 MHz

Intel i960

Core Processor

100 MHz Intel i960 Processor Local Bus

Bus Interface

Unit

100 MHz Internal Bus (IB)

A6414-02

Affected Docs: Intel 80303 I/O Processor Developer’s Manual

15.

Section 19.1 on page 19-1 has incorrect data

Problem:

The last bullet incorrectly states, '64-bit/66MHz PCI and 80303 I/O processor internal bus

interface.' The internal bus on the 80303 I/O processor is 100 MHz.

Workaround: Change the last bullet to the following: '64-bit/66MHz PCI and 64-bit/100 MHz internal bus

interface.'

Affected Docs: Intel 80303 I/O Processor Developer’s Manual

16.

Table 14-46 on page 14-109 has missing data

Problem:

Table 14-46 is missing the bit description for bit 12. Add the following:

Bit

Default

Description

Varies with

inverse of the

Special Downstream Window Enable - When set, a special downstream

external state of memory window which includes the addresses FEC0_0000h through

RAD[2]/SPME FECF_FFFFh is opened. This window provides support for an alternate address

M# at Primary

mechanism to a Hot-Plug Controller.

PCI bus reset

Workaround: When clear, the Special Downstream Memory window is closed.

Affected Docs: Intel 80303 I/O Processor Developer’s Manual

Intel 80303 and 80302 I/O Processors Specification Update

Download from Www.Somanuals.com. All Manuals Search And Download.

Documentation Changes

17.

Section 13.2.4.3 on page 13-30 has incorrect data

Problem:

The first sentence incorrectly states, 'If enabled'. ECC is always enabled on the 80303 I/O

processor, it is not optional.

Workaround: Remove 'If enabled'.

Affected Docs: Intel 80303 I/O Processor Developer’s Manual

18.

Figure 15-3 on page 15-7 has missing text

Problem:

The figure shows 'se_Register + Value of Limit_Register'. It should be 'Base_Register + Value of

Limit_Register'.

Workaround: Replace Figure 15-3 with the following:

Affected Docs: Intel 80303 I/O Processor Developer’s Manual

19.

Section 15.7.39 on page 15-100 has incorrect data

Problem:

The last paragraph is incorrect. It states, 'Note that bits 4:0, bits 12:11, bit 9 and bit 7 can result in

an NMI# interrupt driven to the i960 core processor.' Bit 12 is a reserved bit, so it should be

removed from this sentence.

Workaround: Change the last paragraph to the following: 'Note that bits 4:0, 11, 9 and 7 can result in an NMI#

interrupt driven to the i960 core processor.'

Affected Docs: Intel 80303 I/O Processor Developer’s Manual

Intel 80303 and 80302 I/O Processors Specification Update

Download from Www.Somanuals.com. All Manuals Search And Download.

Documentation Changes

20.

Table 8-17 on page 8-38 has incorrect data

The bit locations for External Interrupt 5 are incorrectly shown as bits '9:4'. It should be '7:4'.

Problem:

Workaround: Replace Table 8-17 with the following:

IOP

Attributes

rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

PCI

Attributes

na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na

Intel^®i960^®Core internal bus address

FF00 8524H

Attribute Legend:

RV = Reserved

PR = Preserved

RS = Read/Set

RW = Read/Write

RC = Read Clear

RO = Read Only

NA= Not Accessible

IMAP1

Bit

Default

Description

31:16

15:12

11:8

7:4

Reserved (initialize to 0)

External Interrupt 7 Field - IMAP1.x7

Default

Value loaded

from image External Interrupt 6 Field - IMAP1.x6

in Control

External Interrupt 5 Field - IMAP1.x5

Table

3:0

External Interrupt 4 Field - IMAP1.x4

Affected Docs: Intel 80303 I/O Processor Developer’s Manual

21.

Section 11.2.8 on page 11-5 has incorrect data

Problem:

The last sentence in the third paragraph states, 'Specifications for a cold and warm reset can be

found in the 80960RM I/O Processor Data Sheet and the 80960RN I/O Processor Data Sheet.'

This sentence should be removed, it does not pertain to the 80303 I/O processor.

Workaround: Change text to the following: 'The 80303 I/O processor complies with the PCI Local Bus

Specification, Revision 2.2. Reset parameters are defined in this specification.'

Affected Docs: Intel 80303 I/O Processor Developer’s Manual

22.

Section 13.2.3.1 on page 13-13 has incorrect data

Problem:

The first sentence states, 'The MCU supports an ECC only memory subsystem ranging from 32 to

528 Mbytes.' It should be 512 Mbytes, not 528 Mbytes.

Workaround: Change this sentence to the following: 'The MCU supports an ECC only memory subsystem

ranging from 32 to 512 Mbytes.'

Affected Docs: Intel 80303 I/O Processor Developer’s Manual

23.

Table 13-4 on page 13-9 has incorrect data

Problem:

Table 13-4 lists incorrect wait states for the flash bus.

Workaround: Replace Table 13-4 with the following:

Flash Speed

Address-to-Data Wait States

Recovery Wait States

<= 55 ns

<= 115 ns

<= 175 ns

Affected Docs: Intel 80303 I/O Processor Developer’s Manual

Intel 80303 and 80302 I/O Processors Specification Update

Download from Www.Somanuals.com. All Manuals Search And Download.

Documentation Changes

24.

Table 8-15 on page 8-36 needs clarification

ICON.10, Global Interrupt Enable bit, does not state what bit value enables interrupts.

Problem:

Workaround: Add this sentence to the bit description, 'A '0' will globally enable interrupts, and a '1' globally

disables interrupts.'

Affected Docs: Intel 80303 I/O Processor Developer’s Manual

25.

Table 13-13 on page 13-30 has incorrect data

Problem:

Syndrome Decoding Error Types and Symptoms are incorrectly stated.

Workaround: Replace Table 13-13 with the following and, add the adjacent paragraph with “new” Figure 13-16:

Table 13-13. Syndrome Decoding

Error Type

None

Symptom

The syndrome is 0000 0000.

Single-Bit

Multi-Bit

Use the H-Matrix in Figure 13-17 to determine which bit the MCU will invert to fix the error.

If the Syndrome does not match an 8-bit value in the H-matrix, the error is uncorrectable

Figure 13-16 shows how the data flows through the ECC hardware for a read transaction.

Figure 13-16. ECC Read Data Flow

Main

ECC

Memory

MCU

Calculate ECC

with G-matrix

Calculate Syndrome by

Comparing ECC w/Check Bits

Data Corrector

(single-bit error)

H-matrix

Look-up Table

Error Type/Location

Data to Internal Bus

A8160-01

Affected Docs: Intel 80303 I/O Processor Developer’s Manual

Intel 80303 and 80302 I/O Processors Specification Update

Download from Www.Somanuals.com. All Manuals Search And Download.

Documentation Changes

26.

Section 13.2.4.3, First Paragraph after Table 13-13 has Incorrect Data

Problem:

First sentence incorrectly states error types for corrected Table 13-13:

...If decoding the syndrome indicates a double-bit or nibble error...

Should read as follows:

...”When” decoding the syndrome indicates a “multi”-bit error...

Affected Docs: Intel 80303 I/O Processor Developer’s Manual

27.

Section 13.2.4.3, First Paragraph after “Current” Figure 13-16. H-Matrix has

Incorrect Data

Problem:

First sentence incorrectly states error types for corrected Table 13-13:

...If error reporting is enabled in the ECCR and the MCU detects a nibble, single-bit, or double-bit

error...

Should read as follows:

...”When” error reporting is enabled in the ECCR and the MCU detects a single-bit or “multi”-bit

error...

Affected Docs: Intel 80303 I/O Processor Developer’s Manual

28.

Section 11.3.1.5 FAIL# Code

Problem:

The verbiage in this section is residual from the Intel i960 I/O Processor Developer’s Manual,

where the internal bus was accessible from the outside. The internal bus is not accessible from the

outside for i960 RM/RN I/O processor. Since the customer cannot “see” the internal bus, whatever

is on it is not useful and is only confusing. Therefore, this section has been removed.

Affected Docs: Intel 80303 I/O Processor Developer’s Manual

29.

Section 13.5 Reset Conditions has Incorrect Data

Problem:

The last sentence in the first paragraph incorrectly states:

Reads issued prior to a write to the same address results in an ECC error (if enabled) and is not

recommended.

This should state:

Reads issued prior to a write to the same address results in an ECC error and are not recommended.

30.

Section 13.2.4.2, First Sentence has Incorrect Data

Problem:

On page 13-28, the first sentence reads: “If the internal bus master writes less than the data bus

width programmed in the SDCR, then the MCU translates the write transaction into a

read-modify-write transaction.” Please remove “programmed in the SDCR” from the sentence.

Affected Docs: Intel 80303 I/O Processor Developer’s Manual

31.

Section 13.6.2, Second Sentence has Incorrect Data

On page 13-46, the second sentence reads: “The SDCR specifies the drive strength for the MCU

pins, the bus width, and power failure handling.” Please “remove, the bus width, and power failure

handling” from the sentence. It should read “The SDCR specifies the drive strength for the MCU

pins.”

Affected Docs: Intel® 80303 I/O Processor Developer’s Manual

Intel 80303 and 80302 I/O Processors Specification Update

Download from Www.Somanuals.com. All Manuals Search And Download.

Documentation Changes

32.

Section 4.5.2 on page 50 is only correct for A-0 and A-1 steppings

Problem:

The second sentence in Note 7 states, ‘S_REQ64# is deasserted one P_CLK after the deassertion of

S_RST#’. This statement is not correct for the A-2 stepping of the 80303 and 80302 I/O

processors.

Workaround: This statement is only correct for the A-0 and A-1 steppings of the 80303. See Specification

Clarification #6 for A-2 stepping functionality.

Affected Docs: Intel 80303 I/O Processor Datasheet

33.

Section 17.5.1 on page 17-12 is only correct for A-0 and A-1 steppings

Problem:

The last sentence states, ‘S_REQ64# remains valid for one clock (P_CLK) after S_RST#

deasserts’. This statement is not correct for the A-2 stepping of the 80303 and 80302 I/O

processors.

Workaround: This statement is only correct for the A-0 and A-1 steppings of the 80303. See Specification

Clarification #6 for A-2 stepping functionality.

Affected Docs: Intel 80303 I/O Processor Developer’s Manual

Intel 80303 and 80302 I/O Processors Specification Update

Download from Www.Somanuals.com. All Manuals Search And Download.

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