DSP56366 24-Bit Digital Signal
Processor
User Manual
Document Number: DSP56366UM
Rev. 4
08/2006
Download from Www.Somanuals.com. All Manuals Search And Download.
Contents
DSP56366 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
DSP56300 Core Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
DSP56366 Audio Processor Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
DSP56300 Core Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
Data ALU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
Data ALU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
Multiplier-Accumulator (MAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
Address Generation Unit (AGU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
Program Control Unit (PCU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
Internal Buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
Direct Memory Access (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
PLL-based Clock Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
JTAG TAP and OnCE Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
On-Chip Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
Off-Chip Memory Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
Peripheral Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
Host Interface (HDI08) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
General Purpose Input/Output (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
Triple Timer (TEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
Enhanced Serial Audio Interface (ESAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10
Enhanced Serial Audio Interface 1 (ESAI_1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10
Serial Host Interface (SHI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10
Digital Audio Transmitter (DAX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10
Signal/Connection Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-1
Signal Groupings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Clock and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
External Memory Expansion Port (Port A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
External Address Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
External Data Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
External Bus Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
Interrupt and Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
PARALLEL HOST INTERFACE (HDI08) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
Serial Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
Enhanced Serial Audio Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
2.10 Enhanced Serial Audio Interface_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
2.11 SPDIF Transmitter Digital Audio Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21
2.12 Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22
2.13 JTAG/OnCE Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22
Memory Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-1
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Data and Program Memory Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
Reserved Memory Spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
Program ROM Area Reserved for Motorola Use . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
Bootstrap ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
Dynamic Memory Configuration Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
External Memory Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
Internal I/O Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
Core Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
Operating Mode Register (OMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
Asynchronous Bus Arbitration Enable (ABE) - Bit 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
Address Attribute Priority Disable (APD) - Bit 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
Address Tracing Enable (ATE) - Bit 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
Patch Enable (PEN) - Bit 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
Interrupt Priority Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
DMA Request Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12
PLL Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13
PLL Multiplication Factor (MF0-MF11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13
PLL Pre-Divider Factor (PD0-PD3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13
Crystal Range Bit (XTLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13
XTAL Disable Bit (XTLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13
Device Identification (ID) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13
JTAG Identification (ID) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13
JTAG Boundary Scan Register (BSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14
General Purpose Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
Port B Signals and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
Port C Signals and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
Port D Signals and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
Port E Signals and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
Timer/Event Counter Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
Host Interface (HDI08) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
HDI08 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
Interface - DSP side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
Interface - Host Side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
HDI08 Host Port Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3
HDI08 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
HDI08 – DSP-Side Programmer’s Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
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Host Receive Data Register (HORX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6
Host Transmit Data Register (HOTX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6
Host Control Register (HCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7
HCR Host Receive Interrupt Enable (HRIE) Bit 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7
HCR Host Transmit Interrupt Enable (HTIE) Bit 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7
HCR Host Command Interrupt Enable (HCIE) Bit 2 . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7
HCR Host Flags 2,3 (HF2,HF3) Bits 3-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8
HCR Reserved Bits 8-15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10
Host Status Register (HSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10
HSR Host Receive Data Full (HRDF) Bit 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10
HSR Host Transmit Data Empty (HTDE) Bit 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10
HSR Host Command Pending (HCP) Bit 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10
HSR Host Flags 0,1 (HF0,HF1) Bits 3-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11
HSR Reserved Bits 5-6, 8-15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11
HSR DMA Status (DMA) Bit 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11
Host Base Address Register (HBAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11
HBAR Base Address (BA[10:3]) Bits 0-7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11
HBAR Reserved Bits 8-15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12
Host Port Control Register (HPCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12
HPCR Host GPIO Port Enable (HGEN) Bit 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12
HPCR Host Address Line 8 Enable (HA8EN) Bit 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13
HPCR Host Address Line 9 Enable (HA9EN) Bit 2 . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13
HPCR Host Chip Select Enable (HCSEN) Bit 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13
HPCR Host Request Enable (HREN) Bit 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13
HPCR Host Acknowledge Enable (HAEN) Bit 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13
HPCR Host Enable (HEN) Bit 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13
HPCR Reserved Bit 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13
HPCR Host Request Open Drain (HROD) Bit 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14
HPCR Host Data Strobe Polarity (HDSP) Bit 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14
HPCR Host Address Strobe Polarity (HASP) Bit 10 . . . . . . . . . . . . . . . . . . . . . . . . . 6-14
HPCR Host Multiplexed bus (HMUX) Bit 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14
HPCR Host Dual Data Strobe (HDDS) Bit 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14
HPCR Host Chip Select Polarity (HCSP) Bit 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15
HPCR Host Request Polarity (HRP) Bit 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15
HPCR Host Acknowledge Polarity (HAP) Bit 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15
Data direction register (HDDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15
Host Data Register (HDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16
DSP-Side Registers After Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16
Host Interface DSP Core Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-17
HDI08 – External Host Programmer’s Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18
Interface Control Register (ICR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-19
ICR Receive Request Enable (RREQ) Bit 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-20
ICR Transmit Request Enable (TREQ) Bit 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-20
ICR Double Host Request (HDRQ) Bit 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21
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ICR Host Flag 0 (HF0) Bit 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21
ICR Host Flag 1 (HF1) Bit 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21
ICR Host Little Endian (HLEND) Bit 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22
ICR Initialize Bit (INIT) Bit 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-23
Command Vector Register (CVR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-23
CVR Host Vector (HV[6:0]) Bits 0–6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-23
CVR Host Command Bit (HC) Bit 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-24
Interface Status Register (ISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-24
ISR Receive Data Register Full (RXDF) Bit 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-24
ISR Transmit Data Register Empty (TXDE) Bit 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-24
ISR Transmitter Ready (TRDY) Bit 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-25
ISR Host Flag 2 (HF2) Bit 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-25
ISR Host Flag 3 (HF3) Bit 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-25
ISR Reserved Bits 5-6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-25
ISR Host Request (HREQ) Bit 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-25
Interrupt Vector Register (IVR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-26
Receive Byte Registers (RXH:RXM:RXL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-26
Transmit Byte Registers (TXH:TXM:TXL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-26
Host Side Registers After Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-27
General Purpose INPUT/OUTPUT (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-27
Servicing The Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-28
HDI08 Host Processor Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-28
Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-28
Servicing Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-29
Serial Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
Serial Host Interface Internal Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
SHI Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
Serial Host Interface Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3
SHI Input/Output Shift Register (IOSR)—Host Side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5
SHI Host Transmit Data Register (HTX)—DSP Side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6
SHI Host Receive Data FIFO (HRX)—DSP Side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6
SHI Slave Address Register (HSAR)—DSP Side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6
HSAR Reserved Bits—Bits 19, 17–0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7
2
SHI Clock Control Register (HCKR)—DSP Side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7
HCKR Prescaler Rate Select (HRS)—Bit 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9
HCKR Reserved Bits—Bits 23–14, 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9
HCKR Filter Mode (HFM[1:0]) — Bits 13–12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9
SHI Control/Status Register (HCSR)—DSP Side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10
HCSR Host Enable (HEN)—Bit 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10
SHI Individual Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11
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2
HCSR I C/SPI Selection (HI2C)—Bit 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11
HCSR I C Clock Freeze (HCKFR)—Bit 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11
2
HCSR FIFO-Enable Control (HFIFO)—Bit 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-12
HCSR Master Mode (HMST)—Bit 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-12
HCSR Idle (HIDLE)—Bit 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13
HCSR Bus-Error Interrupt Enable (HBIE)—Bit 10 . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13
HCSR Transmit-Interrupt Enable (HTIE)—Bit 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13
HCSR Host Transmit Data Empty (HTDE)—Bit 15 . . . . . . . . . . . . . . . . . . . . . . . . . . 7-15
HCSR Reserved Bits—Bits 23, 18 and 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-15
Host Receive FIFO Not Empty (HRNE)—Bit 17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-15
Host Receive FIFO Full (HRFF)—Bit 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-15
Host Receive Overrun Error (HROE)—Bit 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-15
Host Bus Error (HBER)—Bit 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-16
HCSR Host Busy (HBUSY)—Bit 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-16
Characteristics Of The SPI Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-16
Characteristics Of The I C Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-16
2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-17
I C Data Transfer Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-18
2
SHI Programming Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-19
SPI Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-19
SPI Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-20
2
I C Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-21
2
Receive Data in I C Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-21
2
Transmit Data In I C Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-22
2
I C Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-23
2
Receive Data in I C Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-24
2
Transmit Data In I C Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-24
SHI Operation During DSP Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-25
8..1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
ESAI Data and Control Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3
Serial Transmit 0 Data Pin (SDO0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3
Serial Transmit 1 Data Pin (SDO1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3
Serial Transmit 2/Receive 3 Data Pin (SDO2/SDI3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3
Serial Transmit 3/Receive 2 Data Pin (SDO3/SDI2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4
Serial Transmit 4/Receive 1 Data Pin (SDO4/SDI1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4
Serial Transmit 5/Receive 0 Data Pin (SDO5/SDI0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4
Receiver Serial Clock (SCKR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V4
Transmitter Serial Clock (SCKT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5
Frame Sync for Receiver (FSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6
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Frame Sync for Transmitter (FST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7
High Frequency Clock for Transmitter (HCKT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7
High Frequency Clock for Receiver (HCKR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7
ESAI Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7
ESAI Transmitter Clock Control Register (TCCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8
TCCR Transmit Prescaler Range (TPSR) - Bit 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9
TCCR Transmit Clock Polarity (TCKP) - Bit 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-12
TCCR Transmit Frame Sync Polarity (TFSP) - Bit 19 . . . . . . . . . . . . . . . . . . . . . . . . 8-12
ESAI Transmit Control Register (TCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-12
TCR ESAI Transmit 0 Enable (TE0) - Bit 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-13
TCR ESAI Transmit 1 Enable (TE1) - Bit 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-13
TCR ESAI Transmit 2 Enable (TE2) - Bit 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-14
TCR ESAI Transmit 3 Enable (TE3) - Bit 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-14
TCR ESAI Transmit 4 Enable (TE4) - Bit 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-14
TCR ESAI Transmit 5 Enable (TE5) - Bit 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-15
TCR Transmit Shift Direction (TSHFD) - Bit 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-15
TCR Transmit Word Alignment Control (TWA) - Bit 7 . . . . . . . . . . . . . . . . . . . . . . . 8-15
TCR Transmit Frame Sync Length (TFSL) - Bit 15 . . . . . . . . . . . . . . . . . . . . . . . . . . 8-19
TCR Transmit Zero Padding Control (PADC) - Bit 17 . . . . . . . . . . . . . . . . . . . . . . . . 8-21
TCR Reserved Bit - Bits 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-21
TCR Transmit Section Personal Reset (TPR) - Bit 19 . . . . . . . . . . . . . . . . . . . . . . . . 8-21
TCR Transmit Exception Interrupt Enable (TEIE) - Bit 20 . . . . . . . . . . . . . . . . . . . . 8-21
TCR Transmit Interrupt Enable (TIE) - Bit 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-22
TCR Transmit Last Slot Interrupt Enable (TLIE) - Bit 23 . . . . . . . . . . . . . . . . . . . . . 8-22
ESAI Receive Clock Control Register (RCCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-22
RCCR Receiver Prescaler Range (RPSR) - Bit 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-23
RCCR Receiver Clock Polarity (RCKP) - Bit 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-24
RCCR Receiver Frame Sync Polarity (RFSP) - Bit 19 . . . . . . . . . . . . . . . . . . . . . . . . 8-24
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ESAI Receive Control Register (RCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-26
RCR ESAI Receiver 0 Enable (RE0) - Bit 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-27
RCR ESAI Receiver 1 Enable (RE1) - Bit 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-27
RCR ESAI Receiver 2 Enable (RE2) - Bit 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-27
RCR ESAI Receiver 3 Enable (RE3) - Bit 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-27
RCR Reserved Bits - Bits 4-5, 17-18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-27
RCR Receiver Shift Direction (RSHFD) - Bit 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-27
RCR Receiver Word Alignment Control (RWA) - Bit 7 . . . . . . . . . . . . . . . . . . . . . . . 8-28
RCR Receiver Frame Sync Length (RFSL) - Bit 15 . . . . . . . . . . . . . . . . . . . . . . . . . . 8-30
RCR Receiver Section Personal Reset (RPR) - Bit 19 . . . . . . . . . . . . . . . . . . . . . . . . 8-30
RCR Receive Exception Interrupt Enable (REIE) - Bit 20 . . . . . . . . . . . . . . . . . . . . . 8-31
RCR Receive Interrupt Enable (RIE) - Bit 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-31
RCR Receive Last Slot Interrupt Enable (RLIE) - Bit 23 . . . . . . . . . . . . . . . . . . . . . . 8-31
ESAI Common Control Register (SAICR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-31
SAICR Serial Output Flag 0 (OF0) - Bit 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-32
SAICR Serial Output Flag 1 (OF1) - Bit 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-32
SAICR Serial Output Flag 2 (OF2) - Bit 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-32
SAICR Reserved Bits - Bits 3-5, 9-23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-32
SAICR Synchronous Mode Selection (SYN) - Bit 6 . . . . . . . . . . . . . . . . . . . . . . . . . . 8-32
SAICR Transmit External Buffer Enable (TEBE) - Bit 7 . . . . . . . . . . . . . . . . . . . . . . 8-33
SAICR Alignment Control (ALC) - Bit 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-33
ESAI Status Register (SAISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-34
SAISR Serial Input Flag 0 (IF0) - Bit 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-35
SAISR Serial Input Flag 1 (IF1) - Bit 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-35
SAISR Serial Input Flag 2 (IF2) - Bit 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-35
SAISR Reserved Bits - Bits 3-5, 11-12, 18-23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-35
SAISR Receive Frame Sync Flag (RFS) - Bit 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-35
SAISR Receiver Overrun Error Flag (ROE) - Bit 7 . . . . . . . . . . . . . . . . . . . . . . . . . . 8-36
SAISR Receive Data Register Full (RDF) - Bit 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-36
SAISR Receive Even-Data Register Full (REDF) - Bit 9 . . . . . . . . . . . . . . . . . . . . . . 8-36
SAISR Transmit Frame Sync Flag (TFS) - Bit 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-36
SAISR Transmit Underrun Error Flag (TUE) - Bit 14 . . . . . . . . . . . . . . . . . . . . . . . . 8-37
SAISR Transmit Data Register Empty (TDE) - Bit 15 . . . . . . . . . . . . . . . . . . . . . . . . 8-37
ESAI Receive Shift Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-40
ESAI Receive Data Registers (RX3, RX2, RX1, RX0) . . . . . . . . . . . . . . . . . . . . . . . . . . 8-40
ESAI Transmit Shift Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-40
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ESAI Time Slot Register (TSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-40
Transmit Slot Mask Registers (TSMA, TSMB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-40
Receive Slot Mask Registers (RSMA, RSMB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-42
Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-43
ESAI After Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-43
ESAI Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-43
ESAI Interrupt Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-44
Operating Modes – Normal, Network, and On-Demand . . . . . . . . . . . . . . . . . . . . . . . . . . 8-45
Normal/Network/On-Demand Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-45
Synchronous/Asynchronous Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-45
Frame Sync Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-46
Shift Direction Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-46
Serial I/O Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-46
GPIO - Pins and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-47
Port C Control Register (PCRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-47
Port C Direction Register (PRRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-47
Port C Data register (PDRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-48
ESAI Initialization Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-49
Initializing the ESAI Using Individual Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-49
Initializing Just the ESAI Transmitter Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-49
Initializing Just the ESAI Receiver Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-50
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
ESAI_1 Data and Control Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3
Serial Transmit 0 Data Pin (SDO0_1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3
Serial Transmit 1 Data Pin (SDO1_1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3
Serial Transmit 2/Receive 3 Data Pin (SDO2_1/SDI3_1) . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3
Serial Transmit 3/Receive 2 Data Pin (SDO3_1/SDI2_1) . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3
Serial Transmit 4/Receive 1 Data Pin (SDO4_1/SDI1_1) . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3
Serial Transmit 5/Receive 0 Data Pin (SDO5_1/SDI0_1) . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4
Receiver Serial Clock (SCKR_1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4
Transmitter Serial Clock (SCKT_1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4
Frame Sync for Receiver (FSR_1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4
Frame Sync for Transmitter (FST_1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4
ESAI_1 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4
ESAI_1 Multiplex Control Register (EMUXR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5
ESAI_1 Transmitter Clock Control Register (TCCR_1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5
TCCR_1 Tx High Freq. Clock Polarity (THCKP) - Bit 20 . . . . . . . . . . . . . . . . . . . . . . 9-6
ESAI_1 Transmit Control Register (TCR_1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8
ESAI_1 Receive Clock Control Register (RCCR_1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9
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ESAI_1 Receive Control Register (RCR_1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10
ESAI_1 Common Control Register (SAICR_1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10
ESAI_1 Status Register (SAISR_1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10
ESAI_1 Receive Shift Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-11
ESAI_1 Receive Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-11
ESAI_1 Transmit Shift Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-11
ESAI_1 Transmit Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-11
ESAI_1 Time Slot Register (TSR_1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12
Transmit Slot Mask Registers (TSMA_1, TSMB_1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12
Receive Slot Mask Registers (RSMA_1, RSMB_1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12
Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-13
ESAI_1 After Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-13
GPIO - Pins and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-13
Port E Control Register (PCRE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-13
Port E Direction Register (PRRE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-14
Port E Data register (PDRE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-14
Digital Audio Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-1
10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1
10.2 DAX Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2
10.3 DAX Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2
10.4 DAX Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3
10.5 DAX Internal Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4
DAX Audio Data Register (XADR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5
DAX Audio Data Buffers (XADBUFA / XADBUFB) . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5
DAX Audio Data Shift Register (XADSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5
DAX Non-Audio Data Register (XNADR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5
DAX Channel A Validity (XVA)—Bit 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5
DAX Channel A User Data (XUA)—Bit 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6
DAX Channel A Channel Status (XCA)—Bit 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6
DAX Channel B Validity (XVB)—Bit 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6
DAX Channel B User Data (XUB)—Bit 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6
DAX Channel B Channel Status (XCB)—Bit 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6
XNADR Reserved Bits—Bits 0-9, 16–23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6
DAX Non-Audio Data Buffer (XNADBUF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6
DAX Control Register (XCTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6
Underrun Error Interrupt Enable (XUIE)—Bit 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7
Block Transferred Interrupt Enable (XBIE)—Bit 2 . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7
DAX Clock Input Select (XCS[1:0])—Bits 3–4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7
DAX Start Block (XSB)—Bit 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7
XCTR Reserved Bits—Bits 6-23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7
DAX Status Register (XSTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7
DAX Audio Data Register Empty (XADE)—Bit 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-8
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DAX Transmit Underrun Error Flag (XAUR)—Bit 1 . . . . . . . . . . . . . . . . . . . . . . . . . 10-8
DAX Block Transfer Flag (XBLK)—Bit 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-8
XSTR Reserved Bits—Bits 3–23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-8
DAX Parity Generator (PRTYG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9
DAX Biphase Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9
10.5.10 DAX Preamble Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9
10.5.11 DAX Clock Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9
10.5.12 DAX State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10
10.6 DAX Programming Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10
Initiating A Transmit Session . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10
Audio Data Register Empty Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10
Block Transferred Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11
DAX operation with DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11
DAX Operation During Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-12
10.7 GPIO (PORT D) - Pins and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-12
Port D Control Register (PCRD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-12
Port D Direction Register (PRRD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-13
Port D Data Register (PDRD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-14
Timer/ Event Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-1
11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
11.2 Timer/Event Counter Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
Timer/Event Counter Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
Individual Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2
11.3 Timer/Event Counter Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3
Prescaler Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5
Timer Prescaler Load Register (TPLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5
TPLR Prescaler Preload Value PL[20:0] Bits 20–0 . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5
TPLR Prescaler Source PS[1:0] Bits 22-21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5
TPLR Reserved Bit 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6
Timer Prescaler Count Register (TPCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6
TPCR Prescaler Counter Value PC[20:0] Bits 20–0 . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6
TPCR Reserved Bits 23–21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6
Timer Control/Status Register (TCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6
TCSR Timer Enable (TE) Bit 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6
TCSR Timer Overflow Interrupt Enable (TOIE) Bit 1 . . . . . . . . . . . . . . . . . . . . . . . . 11-7
TCSR Timer Compare Interrupt Enable (TCIE) Bit 2 . . . . . . . . . . . . . . . . . . . . . . . . 11-7
TCSR Timer Control (TC[3:0]) Bits 4–7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7
TCSR Inverter (INV) Bit 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9
TCSR Timer Reload Mode (TRM) Bit 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-10
TCSR Direction (DIR) Bit 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-10
TCSR Data Input (DI) Bit 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-10
TCSR Data Output (DO) Bit 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-10
TCSR Prescaler Clock Enable (PCE) Bit 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-11
TCSR Timer Overflow Flag (TOF) Bit 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-11
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TCSR Timer Compare Flag (TCF) Bit 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-11
TCSR Reserved Bits (Bits 3, 10, 14, 16-19, 22, 23) . . . . . . . . . . . . . . . . . . . . . . . . . 11-11
Timer Load Register (TLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-12
Timer Compare Register (TCPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-12
Timer Count Register (TCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-12
11.4 Timer Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-12
Timer Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-13
Timer GPIO (Mode 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-13
Timer Pulse (Mode 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-14
Timer Toggle (Mode 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-14
Timer Event Counter (Mode 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-15
Signal Measurement Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-16
Measurement Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-16
Measurement Input Width (Mode 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-16
Measurement Input Period (Mode 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-17
Measurement Capture (Mode 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-17
Pulse Width Modulation (PWM, Mode 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-18
Watchdog Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-19
Watchdog Pulse (Mode 9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-19
Watchdog Toggle (Mode 10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-20
Reserved Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-20
Special Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-20
Timer Behavior during Wait . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-20
Timer Behavior during Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-21
DMA Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-21
Appendix A Bootstrap ROM Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1
A.1 DSP56366 Bootstrap Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1
Appendix B Equates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1
Appendix C JTAG BSDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-1
Appendix D Programmer’s Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1
Peripheral Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1
Interrupt Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1
Interrupt Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1
Programming Sheets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1
Internal I/O Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1
Interrupt Vector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-8
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Interrupt Source Priorities (within an IPL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-10
Host Interface—Quick Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-12
Programming Sheets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-15
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List of Figures
DSP56366 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
Signals Identified by Functional Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Figure 3-10 Memory Maps for MSW=(X,X), CE=1, MS=0, SC=1 . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
Figure 3-11 Memory Maps for MSW=(0,0), CE=0, MS=1, SC=1 . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
Figure 3-12 Memory Maps for MSW=(0,1), CE=0, MS=1, SC=1 . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
Figure 3-13 Memory Maps for MSW=(1,0), CE=0, MS=1, SC=1 . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
Figure 3-14 Memory Maps for MSW=(0,0), CE=1, MS=1, SC=1 . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
Figure 3-15 Memory Maps for MSW=(0,1), CE=1, MS=1, SC=1 . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
Figure 3-16 Memory Maps for MSW=(1,0), CE=1, MS=1, SC=1 . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
Interrupt Priority Register P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
Interrupt Priority Register C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
HDI08 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
Host Control Register (HCR) (X:$FFFFC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7
Host Status Register (HSR) (X:FFFFC3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10
Host Base Address Register (HBAR) (X:$FFFFC5) . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11
Self Chip Select logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12
Host Port Control Register (HPCR) (X:$FFFFC4) . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12
Single strobe bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14
Dual strobes bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15
Host Data Direction Register (HDDR) (X:$FFFFC8) . . . . . . . . . . . . . . . . . . . . . . . . . 6-16
Figure 6-10 Host Data Register (HDR) (X:$FFFFC9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16
Figure 6-11 HSR-HCR Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18
Figure 6-12 Interface Control Register (ICR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-20
Figure 6-13 Command Vector Register (CVR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-23
Figure 6-14 Interface Status Register (ISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-24
Figure 6-15 Interrupt Vector Register (IVR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-26
Figure 6-16 HDI08 Host Request Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-29
Serial Host Interface Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
SHI Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3
SHI Programming Model—Host Side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3
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SHI Programming Model—DSP Side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4
SHI I/O Shift Register (IOSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6
SPI Data-To-Clock Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8
2
I C Bit Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-17
2
I C Start and Stop Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-17
2
Acknowledgment on the I C Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-18
2
Figure 7-10 I C Bus Protocol For Host Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-18
Figure 7-11 I C Bus Protocol For Host Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-19
2
ESAI Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
TCCR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8
ESAI Clock Generator Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9
TCR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-13
Normal and Network Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-17
Frame Length Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-20
RCCR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-22
RCR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-26
Figure 8-10 SAICR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-32
Figure 8-11 SAICR SYN Bit Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-34
Figure 8-12 SAISR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-35
Figure 8-13 ESAI Data Path Programming Model ([R/T]SHFD=0) . . . . . . . . . . . . . . . . . . . . . . . 8-38
Figure 8-14 ESAI Data Path Programming Model ([R/T]SHFD=1) . . . . . . . . . . . . . . . . . . . . . . . 8-39
Figure 8-15 TSMA Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-41
Figure 8-16 TSMB Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-41
Figure 8-17 RSMA Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-42
Figure 8-18 RSMB Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-42
Figure 8-19 PCRC Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-48
Figure 8-20 PRRC Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-48
Figure 8-21 PDRC Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-49
ESAI_1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2
EMUXR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5
TCCR_1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6
ESAI_1 Clock Generator Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7
TCR_1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8
RCCR_1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9
RCR_1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10
SAICR_1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10
Figure 9-10 SAISR_1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-11
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Figure 9-11 TSMA_1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12
Figure 9-12 TSMB_1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12
Figure 9-13 RSMA_1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-13
Figure 9-14 RSMB_1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-13
Figure 9-15 PCRE Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-14
Figure 9-16 PRRE Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-14
Figure 9-17 PDRE Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-15
Figure 10-1 Digital Audio Transmitter (DAX) Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2
Figure 10-2 DAX Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4
Figure 10-3 DAX Relative Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-8
Figure 10-4 Preamble sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9
Figure 10-5 Clock Multiplexer Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10
Figure 10-6 Examples of data organization in memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-12
Figure 10-7 Port D Direction Register (PRRD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-13
Figure 10-8 Port D Data Register (PDRD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-14
Figure 11-1 Timer/Event Counter Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2
Figure 11-2 Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3
Figure 11-3 Timer Module Programmer’s Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4
Figure 11-4 Timer Prescaler Load Register (TPLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5
Figure 11-5 Time Prescaler Count Register (TPCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6
Operating Mode Register (OMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-17
Interrupt Priority Register–Core (IPR–C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-18
Interrupt Priority Register – Peripherals (IPR–P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-19
Phase Lock Loop Control Register (PCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-20
Host Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-22
Host Interrupt Control and Interrupt Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-24
Figure D-10 Host Interrupt Vector and Command Vector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-25
Figure D-11 Host Receive and Transmit Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-26
Figure D-12 SHI Slave Address and Clock Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-27
Figure D-13 SHI Transmit and Receive Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-28
Figure D-14 SHI Host Control/Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-29
Figure D-15 ESAI Transmit Clock Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-30
Figure D-16 ESAI Transmit Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-31
Figure D-17 ESAI Receive Clock Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-32
Figure D-18 ESAI Receive Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-33
Figure D-19 ESAI Common Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-34
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Figure D-20 ESAI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-35
Figure D-21 ESAI_1 Multiplex Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-36
Figure D-22 ESAI_1 Transmit Clock Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-37
Figure D-23 ESAI_1 Transmit Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-38
Figure D-24 ESAI_1 Receive Clock Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-39
Figure D-25 ESAI_1 Receive Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-40
Figure D-26 ESAI_1 Common Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-41
Figure D-27 ESAI_1 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-42
Figure D-28 DAX Non-Audio Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-43
Figure D-29 DAX Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-44
Figure D-30 Timer Prescaler Load and Prescaler Count Registers (TPLR, TPCR) . . . . . . . . . . . . D-45
Figure D-31 Timer Control/Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-46
Figure D-32 Timer Load, Compare and Count Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-47
Figure D-33 GPIO Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-48
Figure D-34 GPIO Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-49
Figure D-35 GPIO Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-50
Figure D-36 GPIO Port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-51
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List of Tables
DSP56364 Functional Signal Groupings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Power Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Grounds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Clock and PLL Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
External Address Bus Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
External Data Bus Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
External Bus Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
Interrupt and Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
Serial Host Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
Enhanced Serial Audio Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
Enhanced Serial Audio Interface_1 Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
Digital Audio Interface (DAX) Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21
Timer Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22
JTAG/OnCE Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22
Internal Memory Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
On-chip RAM Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
On-chip ROM Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
Internal I/O Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
Operating Mode Register (OMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
DSP56366 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
DSP56366 Mode Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
Interrupt Priority Level Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
Interrupt Sources Priorities Within an IPL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
DSP56366 Interrupt Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10
DMA Request Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12
Identification Register Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13
JTAG Identification Register Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14
DSP56366 BSR Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14
HDI08 Signal Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3
Strobe Signals Support signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
Host request support signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
HDI08 IRQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8
HDM[2:0] Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8
HDR and HDDR Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16
DSP-Side Registers after Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-17
HDI08 Host Side Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-19
HDRQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21
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Table 7-3
Host Mode Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22
INIT Command Effect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-23
Host Request Status (HREQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-25
Host Side Registers After Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-27
SHI Interrupt Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5
SHI Internal Interrupt Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5
SHI Noise Reduction Filter Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10
SHI Data Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11
HREQ Function In SHI Slave Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-12
HCSR Receive Interrupt Enable Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-14
Receiver Clock Sources (asynchronous mode only) . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5
Transmitter Clock Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6
Transmitter High Frequency Clock Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-11
Transmit Network Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-16
ESAI Transmit Slot and Word Length Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18
Receiver High Frequency Clock Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-24
SCKR Pin Definition Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-25
FSR Pin Definition Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-25
HCKR Pin Definition Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-26
ESAI Receive Network Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-28
ESAI Receive Slot and Word Length Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-29
PCRC and PRRC Bits Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-48
EMUXR ESA/ESAI_1 Pin Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5
Transmitter Clock Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6
Receiver Clock Sources (asynchronous mode only) . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9
PCRE and PRRE Bits Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-14
DAX Interrupt Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4
DAX Interrupt Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4
Clock Source Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7
Preamble Bit Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9
Examples of DMA configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11
DAX Port GPIO Control Register Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-13
Prescaler Source Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6
Timer Control Bits for Timer 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8
Timer Control Bits for Timers 1 and 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8
Inverter (INV) Bit Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9
Internal I/O Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-2
DSP56366 Interrupt Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-8
Interrupt Sources Priorities Within an IPL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-10
HDI08 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-12
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Preface
This manual describes the DSP56366 24-bit digital signal processor (DSP), its memory, operating modes,
and peripheral modules. The DSP56366 is a member of the DSP56300 family of programmable CMOS
DSPs. Changes in core functionality specific to the DSP56366 are also described in this manual.
The DSP56366 is targeted to applications that require digital audio compression and decompression,
sound field processing, acoustic equalization, and other digital audio algorithms.
This manual is intended to be used with the following publications:
•
The DSP56300 Family Manual (DSP56300FM), which describes the CPU, core programming models,
and instruction set details.
•
The DSP56366 Technical Data Sheet (DSP56366), which provides electrical specifications, timing,
pinout, and packaging descriptions of the DSP56366.
These documents, as well as Freescale’s DSP development tools, can be obtained through a local Freescale
Semiconductor Sales Office or authorized distributor.
To receive the latest information on this DSP, access the Freescale DSP home page at the address given on
the back cover of this document.
This manual contains the following sections and appendices.
SECTION 1—DSP56366 OVERVIEW
•
Provides a brief description of the DSP56366, including a features list and block diagram. Lists
related documentation needed to use this chip and describes the organization of this manual.
SECTION 2—SIGNAL/CONNECTION DESCRIPTIONS
•
Describes the signals on the DSP56366 pins and how these signals are grouped into interfaces.
SECTION 3—MEMORY CONFIGURATION
•
Describes the DSP56366 memory spaces, RAM and ROM configuration, memory configurations
and their bit settings, and memory maps.
SECTION 4—CORE CONFIGURATION
•
Describes the registers used to configure the DSP56300 core when programming the DSP56366,
in particular the interrupt vector locations and the operation of the interrupt priority registers.
Explains the operating modes and how they affect the processor’s program and data memories.
SECTION 5—GENERAL PURPOSE INPUT/OUTPUT (GPIO)
•
Describes the DSP56366 GPIO capability and the programming model for the GPIO signals
(operation, registers, and control).
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SECTION 6— HOST INTERFACE (HDI08)
•
Describes the HDI08 parallel host interface.
SECTION 7—SERIAL HOST INTERFACE (SHI)
•
Describes the serial input/output interface providing a path for communication and
program/coefficient data transfers between the DSP and an external host processor. The SHI can
also communicate with other serial peripheral devices.
SECTION 8—ENHANCED SERIAL AUDIO INTERFACE (ESAI)
•
Describes one of the full-duplex serial port for serial communication with a variety of serial
devices.
SECTION 9—ENHANCED SERIAL AUDIO INTERFACE 1 (ESAI_1)
•
Describes the second full-duplex serial port for serial communication with a variety of serial
devices.
SECTION 10—DIGITAL AUDIO TRANSMITTER (DAX)
•
Describes the full-duplex serial port for serial communication with a variety of serial devices.
SECTION 11—TRIPLE TIMER MODULE (TEC)
APPENDIX A—BOOTSTRAP PROGRAM
•
Lists the bootstrap code used for the DSP56366.
APPENDIX B—EQUATES
•
Lists equates for the DSP56366.
APPENDIX C—JTAG/BSDL LISTING
•
Provides the BSDL listing for the DSP56366.
APPENDIX D—PROGRAMMING REFERENCE
•
Lists peripheral addresses, interrupt addresses, and interrupt priorities for the DSP56366. Contains
programming sheets listing the contents of the major DSP56366 registers for programmer
reference.
Manual Conventions
The following conventions are used in this manual:
•
•
Bits within registers are always listed from most significant bit (MSB) to least significant bit
(LSB).
When several related bits are discussed, they are referenced as AA[n:m], where n>m. For purposes
of description, the bits are presented as if they are contiguous within a register. However, this is not
always the case. Refer to the programming model diagrams or to the programmer’s sheets to see
the exact location of bits within a register.
•
When a bit is described as “set”, its value is 1. When a bit is described as “cleared”, its value is 0.
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•
The word “assert” means that a high true (active high) signal is pulled high to V or that a low
CC
true (active low) signal is pulled low to ground. The word “deassert” means that a high true signal
is pulled low to ground or that a low true signal is pulled high to V
.
CC
High True/Low True Signal Conventions
Signal/Symbol
Logic State
True
Signal State
Asserted
Voltage
1
2
PIN
Ground
3
PIN
PIN
PIN
False
Deasserted
Asserted
V
CC
True
V
CC
False
Deasserted
Ground
1
2
PIN is a generic term for any pin on the chip.
Ground is an acceptable low voltage level. See the appropriate data sheet for the range of
acceptable low voltage levels (typically a TTL logic low).
3
V
is an acceptable high voltage level. See the appropriate data sheet for the range of acceptable
CC
high voltage levels (typically a TTL logic high).
•
Pins or signals that are asserted low (made active when pulled to ground)
— In text, have an overbar (e.g., RESET is asserted low).
— In code examples, have a tilde in front of their names. In example below, line 3 refers to the
SS0 pin (shown as ~SS0).
•
•
Sets of pins or signals are indicated by the first and last pins or signals in the set (e.g., HA1–HA8).
Code examples are displayed in a monospaced font, as shown below:
Example Sample Code Listing
BFSET
#$0007,X:PCC Configure:
line 1
line 2
line 3
; MISO0, MOSI0, SCK0 for SPI master
; ~SS0 as PC3 for GPIO
•
•
Hex values are indicated with a dollar sign ($) preceding the hex value, as follows: $FFFFFF is the
X memory address for the core interrupt priority register (IPR-C).
The word “reset” is used in four different contexts in this manual:
— the reset signal, written as “RESET,”
— the reset instruction, written as “RESET,”
— the reset operating state, written as “Reset,” and
— the reset function, written as “reset.”
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NOTES
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1 DSP56366 Overview
1.1
Introduction
This manual describes the DSP56366 24-bit digital signal processor (DSP), its memory, operating modes,
and peripheral modules. The DSP56366 is a member of the DSP56300 family of programmable CMOS
DSPs. The DSP56366 is targeted to applications that require digital audio compression/decompression,
sound field processing, acoustic equalization and other digital audio algorithms. Changes in core
functionality specific to the DSP56366 are also described in this manual. See Figure 1-1 for the block
diagram of the DSP56366.
4
8
2
16
5
1
6
MEMORY EXPANSION AREA
X MEMORY
RAM
13K X 24
ROM
Y MEMORY
RAM
7K X 24
ROM
PROGRAM
RAM
DAX
HOST
INTER-
FACE
SHI
INTER-
FACE
ESAI
INTER-
FACE
TRIPLE
TIMER
(SPDIF Tx.)
INTER-FAC
E
/INSTR.
CACHE
3K x 24
PROGRAM
ROM
32K x 24
8K x 24
ESAI_1
40K x 24
Bootstrap
PERIPHERAL
EXPANSION AREA
ADDRESS
GENERATION
UNIT
YAB
EXTERNAL
ADDRESS
BUS
18
XAB
PAB
DAB
ADDRESS
SIX CHANNELS
DMA UNIT
SWITCH
24-BIT
DSP56300
Core
DRAM &
SRAM BUS
INTERFACE
&
10
CONTROL
I - CACHE
DDB
YDB
XDB
PDB
GDB
EXTERNAL
DATA BUS
SWITCH
24
INTERNAL
DATA
BUS
DATA
POWER
MNGMNT
PLL
DATA ALU
->
PROGRAM
INTERRUPT
CONTROLLER
PROGRAM
DECODE
CONTROLLE
PROGRAM
ADDRESS
GENERATOR
+
24X24 56 56-BIT MAC
4
JTAG
TWO 56-BIT ACCUMULATORS
BARREL SHIFTER
CLOCK
GENERATO
OnCE™
24 BITS BUS
EXTAL
MODA/IRQA
MODB/IRQB
MODC/IRQC
MODD/IRQD
RESET
PINIT/NMI
Figure 1-1 DSP56366 Block Diagram
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
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DSP56300 Core Description
1.2
DSP56300 Core Description
The DSP56366 uses the DSP56300 core, a high-performance, single clock cycle per instruction engine that
provides up to twice the performance of Freescale's popular DSP56000 core family while retaining code
compatibility with it.
The DSP56300 core family offers a new level of performance in speed and power, provided by its rich
instruction set and low power dissipation, thus enabling a new generation of wireless, telecommunications,
and multimedia products. For a description of the DSP56300 core, see Section 1.4, "DSP56300 Core
Functional Blocks". Significant architectural enhancements to the DSP56300 core family include a barrel
shifter, 24-bit addressing, an instruction cache, and direct memory access (DMA).
The DSP56300 core family members contain the DSP56300 core and additional modules. The modules
are chosen from a library of standard predesigned elements such as memories and peripherals. New
modules may be added to the library to meet customer specifications. A standard interface between the
DSP56300 core and the on-chip memory and peripherals supports a wide variety of memory and
Core features are described fully in the DSP56300 Family Manual. Pinout, memory, and peripheral
features are described in this manual.
•
DSP56300 modular chassis
— 120 Million Instructions Per Second (MIPS) with an 120 MHz clock at 3.3V.
— Object Code Compatible with the 56K core.
— Data ALU with a 24 × 24 bit multiplier-accumulator and a 56-bit barrel shifter. 16-bit
arithmetic support.
— Program Control with position independent code support and instruction cache support.
— Six-channel DMA controller.
— PLL based clocking with a wide range of frequency multiplications (1 to 4096), predivider
i
factors (1 to 16) and power saving clock divider (2 : i=0 to 7). Reduces clock noise.
— Internal address tracing support and OnCE™ for Hardware/Software debugging.
— JTAG port.
— Very low-power CMOS design, fully static design with operating frequencies down to DC.
— STOP and WAIT low-power standby modes.
•
On-chip Memory Configuration
— 7K × 24 Bit Y-Data RAM and 8K × 24 Bit Y-Data ROM.
— 13K × 24 Bit X-Data RAM and 32K × 24 Bit X-Data ROM.
— 40K × 24 Bit Program ROM.
— 3K × 24 Bit Program RAM and 192 × 24 Bit Bootstrap ROM. 1K of Program RAM may be
used as Instruction Cache or for Program ROM patching.
— 2K × 24 Bit from Y Data RAM and 5K × 24 Bit from X Data RAM can be switched to Program
RAM resulting in up to 10K × 24 Bit of Program RAM.
•
Off-chip memory expansion
— External Memory Expansion Port.
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DSP56366 Audio Processor Architecture
— Off-chip expansion up to two 16M × 24-bit word of Data memory.
— Off-chip expansion up to 16M × 24-bit word of Program memory.
— Simultaneous glueless interface to SRAM and DRAM.
Peripheral modules
•
2
— Serial Audio Interface (ESAI): up to 4 receivers and up to 6 transmitters, master or slave. I S,
Sony, AC97, network and other programmable protocols.
— Serial Audio Interface I (ESAI_1): up to 4 receivers and up to 6 transmitters, master or slave.
2
I S, Sony, AC97, network and other programmable protocols
The ESAI_1 shares four of the data pins with ESAI, and ESAI_1 does NOT support HCKR and
HCKT (high frequency clocks)
2
— Serial Host Interface (SHI): SPI and I C protocols, multi master capability, 10-word receive
FIFO, support for 8, 16 and 24-bit words.
— Byte-wide parallel Host Interface (HDI08) with DMA support.
— Triple Timer module (TEC).
— Digital Audio Transmitter (DAX): 1 serial transmitter capable of supporting the SPDIF,
IEC958, CP-340 and AES/EBU digital audio formats.
— Pins of unused peripherals (except SHI) may be programmed as GPIO lines.
144-pin plastic TQFP package.
•
1.3
DSP56366 Audio Processor Architecture
This section defines the DSP56366 audio processor architecture. The audio processor is composed of the
following units:
•
The DSP56300 core is composed of the Data ALU, Address Generation Unit, Program Controller,
Instruction-Cache Controller, DMA Controller, PLL-based clock oscillator, Memory Module
Interface, Peripheral Module Interface and the On-Chip Emulator (OnCE). The DSP56300 core is
described in the document DSP56300 24-Bit Digital Signal Processor Family Manual, Freescale
publication DSP56300FM.
•
•
Memory modules.
Peripheral modules. The peripheral modules are defined in the following sections.
Memory sizes in the block diagram are defaults. Memory may be differently partitioned, according to the
1.4
DSP56300 Core Functional Blocks
The DSP56300 core provides the following functional blocks:
•
•
•
•
•
Data arithmetic logic unit (Data ALU)
Address generation unit (AGU)
Program control unit (PCU)
Bus interface unit (BIU)
DMA controller (with six channels)
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DSP56300 Core Functional Blocks
•
•
•
•
•
Instruction cache controller
PLL-based clock oscillator
OnCE module
JTAG TAP
Memory
In addition, the DSP56366 provides a set of on-chip peripherals, described in Section 1.5, "Peripheral
1.4.1
Data ALU
The Data ALU performs all the arithmetic and logical operations on data operands in the DSP56300 core.
The components of the Data ALU are as follows:
•
•
Fully pipelined 24-bit × 24-bit parallel multiplier-accumulator (MAC)
Bit field unit, comprising a 56-bit parallel barrel shifter (fast shift and normalization; bit stream
generation and parsing)
•
•
•
•
Conditional ALU instructions
24-bit or 16-bit arithmetic support under software control
Four 24-bit input general purpose registers: X1, X0, Y1, and Y0
Six Data ALU registers (A2, A1, A0, B2, B1, and B0) that are concatenated into two general
purpose, 56-bit accumulators (A and B), accumulator shifters
•
Two data bus shifter/limiter circuits
1.4.1.1
Data ALU Registers
The Data ALU registers can be read or written over the X memory data bus (XDB) and the Y memory data
bus (YDB) as 24- or 48-bit operands (or as 16- or 32-bit operands in 16-bit arithmetic mode). The source
operands for the Data ALU, which can be 24, 48, or 56 bits (16, 32, or 40 bits in 16-bit arithmetic mode),
always originate from Data ALU registers. The results of all Data ALU operations are stored in an
accumulator.
All the Data ALU operations are performed in two clock cycles in pipeline fashion so that a new
instruction can be initiated in every clock, yielding an effective execution rate of one instruction per clock
cycle. The destination of every arithmetic operation can be used as a source operand for the immediately
following arithmetic operation without a time penalty (i.e., without a pipeline stall).
1.4.1.2
Multiplier-Accumulator (MAC)
The MAC unit comprises the main arithmetic processing unit of the DSP56300 core and performs all of
the calculations on data operands. In the case of arithmetic instructions, the unit accepts as many as three
input operands and outputs one 56-bit result of the following form- Extension:Most Significant
Product:Least Significant Product (EXT:MSP:LSP).
The multiplier executes 24-bit × 24-bit, parallel, fractional multiplies, between two’s-complement signed,
unsigned, or mixed operands. The 48-bit product is right-justified and added to the 56-bit contents of either
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DSP56300 Core Functional Blocks
the A or B accumulator. A 56-bit result can be stored as a 24-bit operand. The LSP can either be truncated
or rounded into the MSP. Rounding is performed if specified.
1.4.2
Address Generation Unit (AGU)
The AGU performs the effective address calculations using integer arithmetic necessary to address data
operands in memory and contains the registers used to generate the addresses. It implements four types of
arithmetic: linear, modulo, multiple wrap-around modulo, and reverse-carry. The AGU operates in parallel
with other chip resources to minimize address-generation overhead.
The AGU is divided into two halves, each with its own Address ALU. Each Address ALU has four sets of
register triplets, and each register triplet is composed of an address register, an offset register, and a
modifier register. The two Address ALUs are identical. Each contains a 24-bit full adder (called an offset
adder).
A second full adder (called a modulo adder) adds the summed result of the first full adder to a modulo
value that is stored in its respective modifier register. A third full adder (called a reverse-carry adder) is
also provided.
The offset adder and the reverse-carry adder are in parallel and share common inputs. The only difference
between them is that the carry propagates in opposite directions. Test logic determines which of the three
summed results of the full adders is output.
Each Address ALU can update one address register from its respective address register file during one
instruction cycle. The contents of the associated modifier register specifies the type of arithmetic to be used
in the address register update calculation. The modifier value is decoded in the Address ALU.
1.4.3
Program Control Unit (PCU)
The PCU performs instruction prefetch, instruction decoding, hardware DO loop control, and exception
processing. The PCU implements a seven-stage pipeline and controls the different processing states of the
DSP56300 core. The PCU consists of the following three hardware blocks:
•
•
•
Program decode controller (PDC)
Program address generator (PAG)
Program interrupt controller (PIC)
The PDC decodes the 24-bit instruction loaded into the instruction latch and generates all signals necessary
for pipeline control. The PAG contains all the hardware needed for program address generation, system
stack, and loop control. The PIC arbitrates among all interrupt requests (internal interrupts, as well as the
five external requests: IRQA, IRQB, IRQC, IRQD, and NMI), and generates the appropriate interrupt
vector address.
PCU features include the following:
•
•
•
•
Position independent code support
Addressing modes optimized for DSP applications (including immediate offsets)
On-chip instruction cache controller
On-chip memory-expandable hardware stack
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DSP56300 Core Functional Blocks
•
•
Nested hardware DO loops
Fast auto-return interrupts
The PCU implements its functions using the following registers:
•
•
•
•
•
•
•
•
•
PC—program counter register
SR—Status register
LA—loop address register
LC—loop counter register
VBA—vector base address register
SZ—stack size register
SP—stack pointer
OMR—operating mode register
SC—stack counter register
The PCU also includes a hardware system stack (SS).
1.4.4
Internal Buses
To provide data exchange between blocks, the following buses are implemented:
•
•
•
•
•
Peripheral input/output expansion bus (PIO_EB) to peripherals
Program memory expansion bus (PM_EB) to program memory
X memory expansion bus (XM_EB) to X memory
Y memory expansion bus (YM_EB) to Y memory
Global data bus (GDB) between registers in the DMA, AGU, OnCE, PLL, BIU, and PCU as well
as the memory-mapped registers in the peripherals
•
•
•
•
•
•
•
•
DMA data bus (DDB) for carrying DMA data between memories and/or peripherals
DMA address bus (DAB) for carrying DMA addresses to memories and peripherals
Program Data Bus (PDB) for carrying program data throughout the core
X memory Data Bus (XDB) for carrying X data throughout the core
Y memory Data Bus (YDB) for carrying Y data throughout the core
Program address bus (PAB) for carrying program memory addresses throughout the core
X memory address bus (XAB) for carrying X memory addresses throughout the core
Y memory address bus (YAB) for carrying Y memory addresses throughout the core
1.4.5
Direct Memory Access (DMA)
The DMA block has the following features:
•
•
Six DMA channels supporting internal and external accesses
One-, two-, and three-dimensional transfers (including circular buffering)
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DSP56300 Core Functional Blocks
•
•
End-of-block-transfer interrupts
Triggering from interrupt lines and all peripherals
1.4.6
PLL-based Clock Oscillator
The clock generator in the DSP56300 core is composed of two main blocks: the PLL, which performs
clock input division, frequency multiplication, and skew elimination; and the clock generator (CLKGEN),
which performs low-power division and clock pulse generation. PLL-based clocking:
•
•
•
Allows change of low-power divide factor (DF) without loss of lock
Provides output clock with skew elimination
Provides a wide range of frequency multiplications (1 to 4096), predivider factors (1 to 16), and a
i
power-saving clock divider (2 : i = 0 to 7) to reduce clock noise
The PLL allows the processor to operate at a high internal clock frequency using a low frequency clock
input. This feature offers two immediate benefits:
•
A lower frequency clock input reduces the overall electromagnetic interference generated by a
system.
•
The ability to oscillate at different frequencies reduces costs by eliminating the need to add
additional oscillators to a system.
1.4.7
JTAG TAP and OnCE Module
The DSP56300 core provides a dedicated user-accessible TAP fully compatible with the IEEE 1149.1
Standard Test Access Port and Boundary Scan Architecture. Problems associated with testing high-density
circuit boards led to developing this standard under the sponsorship of the Test Technology Committee of
IEEE and JTAG. The DSP56300 core implementation supports circuit-board test strategies based on this
standard.
The test logic includes a TAP consisting of four dedicated signals, a 16-state controller, and three test data
registers. A boundary scan register links all device signals into a single shift register. The test logic,
implemented utilizing static logic design, is independent of the device system logic. More information on
the JTAG port is provided in DSP56300 Family Manual, JTAG Port.
The OnCE module provides a nonintrusive means of interacting with the DSP56300 core and its
peripherals so a user can examine registers, memory, or on-chip peripherals. This facilitates hardware and
software development on the DSP56300 core processor. OnCE module functions are provided through the
JTAG TAP signals. More information on the OnCE module is provided in DSP56300 Family Manual,
On-Chip Emulation Module.
1.4.8
On-Chip Memory
The memory space of the DSP56300 core is partitioned into program memory space,
X data memory space, and Y data memory space. The data memory space is divided into X and Y data
memory in order to work with the two Address ALUs and to feed two operands simultaneously to the Data
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Peripheral Overview
ALU. Memory space includes internal RAM and ROM and can be expanded off-chip under software
control.
There is an instruction cache, made using program RAM. The patch mode (which uses instruction cache
space) is used to patch program ROM. The memory switch mode is used to increase the size of program
RAM as needed (switch from X data RAM and/or Y data RAM).
There are on-chip ROMs for program memory (40K × 24-bit), bootstrap memory (192 words × 24-bit), X
ROM (32K × 24-bit), and Y ROM(8K × 24-bit).
1.4.9
Off-Chip Memory Expansion
Memory can be expanded off-chip as follows:
•
Data memory can be expanded to two 16 M × 24-bit word memory spaces in 24-bit address mode
(64K in 16-bit address mode).
•
Program memory can be expanded to one 16 M × 24-bit word memory space in 24-bit address
mode (64K in 16-bit address mode).
Other features of external memory expansion include the following:
•
•
•
•
External memory expansion port
Chip-select logic glueless interface to static random access memory (SRAM)
On-chip dynamic RAM (DRAM) controller for glueless interface to DRAM
Eighteen external address lines
1.5
Peripheral Overview
The DSP56366 is designed to perform a wide variety of fixed-point digital signal processing functions. In
addition to the core features previously discussed, the DSP56366 provides the following peripherals:
•
•
•
•
•
•
8-bit parallel host interface (HDI08, with DMA support) to external hosts
As many as 37 user-configurable general purpose input/output (GPIO) signals
Timer/event counter (TEC) module, containing three independent timers
Memory switch mode in on-chip memory
Four external interrupt/mode control lines and one external non-maskable interrupt line
Enhanced serial audio interface (ESAI) with up to four receivers and up to six transmitters, master
2
or slave, using the I S, Sony, AC97, network, and other programmable protocols
•
•
A second enhanced serial audio interface (ESAI_1) with 6 dedicated pins.
2
Serial host interface (SHI) using SPI and I C protocols, with multi-master capability, 10-word
receive FIFO, and support for 8-, 16-, and 24-bit words
•
Digital audio transmitter (DAX): a serial transmitter capable of supporting the SPDIF, IEC958,
CP-340, and AES/EBU digital audio formats
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Peripheral Overview
1.5.1
Host Interface (HDI08)
The host interface (HDI08) is a byte-wide, full-duplex, double-buffered, parallel port that can be connected
directly to the data bus of a host processor. The HDI08 supports a variety of buses and provides glueless
connection with a number of industry-standard DSPs, microcomputers, microprocessors, and DMA
hardware.
The DSP core treats the HDI08 as a memory-mapped peripheral, using either standard polled or interrupt
programming techniques. Separate transmit and receive data registers are double-buffered to allow the
DSP and host processor to efficiently transfer data at high speed. Memory mapping allows DSP core
communication with the HDI08 registers to be accomplished using standard instructions and addressing
modes.
Since the host bus may operate asynchronously with the DSP core clock, the HDI08 registers are divided
into 2 banks. The “host side” bank is accessible to the external host, and the “DSP side” bank is accessible
to the DSP core.
The HDI08 supports the following three classes of interfaces:
•
•
•
Host processor/MCU connection
DMA controller
GPIO port
Host port pins not in use may be configured as GPIO pins. The host interface provides up to 16 GPIO pins.
These pins can be programmed to function as either GPIO or host interface.
For more information on the HDI08, see Section 6, Host Interface (HDI08).
1.5.2
General Purpose Input/Output (GPIO)
The GPIO port consists of as many as 37 programmable signals, all of which are also used by the
peripherals (HDI08, ESAI, ESAI_1, DAX, and TEC). There are no dedicated GPIO signals. The signals
are configured as GPIO after hardware reset. Register programming techniques for all GPIO functionality
among these interfaces are very similar.
1.5.3
Triple Timer (TEC)
This section describes a peripheral module composed of a common 21-bit prescaler and three independent
and identical general purpose 24-bit timer/event counters, each one having its own register set.
Each timer can use internal or external clocking and can interrupt the DSP after a specified number of
events (clocks). Timer 0 can signal an external device after counting internal events. Each timer can also
be used to trigger DMA transfers after a specified number of events (clocks) occurred. One timer (Timer
0) connects to the external world through one bidirectional pin TIO0. When TIO0 is configured as input,
the timer functions as an external event counter or can measure external pulse width/signal period. When
TIO0 is used as output the timer is functioning as either a timer, a watchdog or a Pulse Width Modulator.
When the TIO0 pin is not used by the timer it can be used as a General Purpose Input/Output Pin. Refer
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Peripheral Overview
1.5.4
Enhanced Serial Audio Interface (ESAI)
The ESAI provides a full-duplex serial port for serial communication with a variety of serial devices
including one or more industry-standard codecs, other DSPs, microprocessors, and peripherals that
implement the Freescale SPI serial protocol. The ESAI consists of independent transmitter and receiver
sections, each with its own clock generator. It is a superset of the DSP56300 family ESSI peripheral and
of the DSP56000 family SAI peripheral. For more information on the ESAI, refer to Section 8, "Enhanced
1.5.5
Enhanced Serial Audio Interface 1 (ESAI_1)
The ESAI_1 is a second ESAI interface with just 6 dedicated pins instead of the 12 pins of the full ESAI.
Four data pins are shared with the ESAI, while the two high frequency clock pins are not available. Other
than the available pins, ESAI_1 is functionally identical to ESAI. For more information on the ESAI_1,
1.5.6
Serial Host Interface (SHI)
The SHI is a serial input/output interface providing a path for communication and program/coefficient data
transfers between the DSP and an external host processor. The SHI can also communicate with other serial
peripheral devices. The SHI can interface directly to either of two well-known and widely used
synchronous serial buses: the Freescale serial peripheral interface (SPI) bus and the Philips
2
2
inter-integrated-circuit control (I C) bus. The SHI supports either the SPI or I C bus protocol, as required,
from a slave or a single-master device. To minimize DSP overhead, the SHI supports single-, double-, and
triple-byte data transfers. The SHI has a 10-word receive FIFO that permits receiving up to 30 bytes before
generating a receive interrupt, reducing the overhead for data reception. For more information on the SHI,
1.5.7
Digital Audio Transmitter (DAX)
The DAX is a serial audio interface module that outputs digital audio data in the AES/EBU, CP-340 and
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2 Signal/Connection Descriptions
2.1
Signal Groupings
The input and output signals of the DSP56364 are organized into functional groups, which are listed in
The DSP56364 is operated from a 3.3 V supply; however, some of the inputs can tolerate 5 V. A special
notice for this feature is added to the signal descriptions of those inputs.
Table 2-1 DSP56364 Functional Signal Groupings
Number of
Signals
Detailed
Description
Functional Group
Power (V
)
20
18
3
CC
Ground (GND)
Clock and PLL
Address bus
Data bus
18
24
10
5
1
Port A
Port B
Bus control
Interrupt and mode control
HDI08
2
3
16
5
SHI
ESAI
Port C
12
6
4
ESAI_1
Port E
5
Digital audio transmitter (DAX)
Timer
Port D
2
1
JTAG/OnCE Port
4
1
2
3
4
5
Port A is the external memory interface port, including the external address bus, data bus, and control signals.
Port B signals are the GPIO port signals which are multiplexed with the HDI08 signals.
Port C signals are the GPIO port signals which are multiplexed with the ESAI signals.
Port E signals are the GPIO port signals which are multiplexed with the ESAI_1 signals.
Port D signals are the GPIO port signals which are multiplexed with the DAX signals.
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Signal Groupings
OnCE‰
ON-CHIP EMULATION/
PORT A ADDRESS BUS
JTAG PORT
TDI
DSP56366
A0-A17
VCCA (3)
TCK
TDO
TMS
GNDA (4)
PORT A DATA BUS
PARALLEL HOST PORT (HDI08)
D0-D23
VCCD (4)
HAD(7:0) [PB0-PB7]
HAS/HA0 [PB8]
Port B
GNDD (4)
HA8/HA1 [PB9]
PORT A BUS CONTROL
HA9/HA2 [PB10]
HRW/HRD [PB11]
HDS/HWR [PB12]
HCS/HA10 [PB13]
HOREQ/HTRQ [PB14]
AA0-AA2/RAS0-RAS2
CAS
RD
WR
TA
HACK/HRRQ [PB15]
VCCH
BR
GNDH
BG
BB
SERIAL AUDIO INTERFACE (ESAI)
SCKT[PC3]
VCCC (2)
GNDC (2)
FST [PC4]
Port C
HCKT [PC5]
INTERRUPT AND
MODE CONTROL
SCKR [PC0]
FSR [PC1]
MODA/IRQA
MODB/IRQB
MODC/IRQC
MODD/IRQD
RESET
HCKR [PC2]
SDO0 [PC11] / SDO0_1[PE11]
SDO1 [PC10] / SDO1_1[PE10]
SDO2/SDI3[PC9] / SDO2_1/SDI3_1[PE9]
SDO3/SDI2[PC8] / SDO3_1/SDI2_1[PE8]
SDO4/SDI1 [PC7]
PLL AND CLOCK
SDO5/SDI0 [PC6]
EXTAL
PINIT/NMI
PCAP
SERIAL AUDIO INTERFACE(ESAI_1)
SCKT_1[PE3]
FS T_1[PE4]
VCCP
GNDP
Port E
SCKR_1[PE0]
FSR_1[PE1]
QUIET POWER
VCCQH (3)
SDO4_1/SDI1_1[PE7]
SDO5_1/SDI0_1[PE6]
VCCS (2)
VCCQL (4)
GNDQ (4)
GNDS (2)
SPDIF TRANSMITTER (DAX)
Port D
SERIAL HOST INTERFACE (SHI)
MOSI/HA0
ADO [PD1]
ACI [PD0]
SS/HA2
MISO/SDA
TIMER 0
TIO0 [TIO0]
SCK/SCL
HREQ
Figure 2-1 Signals Identified by Functional Group
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Power
2.2
Power
Table 2-2 Power Inputs
Description
Power Name
V
PLL Power — V
is V dedicated for PLL use. The voltage should be well-regulated and the input
CCP
CCP CC
should be provided with an extremely low impedance path to the V power rail. There is one V
CC
CCP
input.
V
(4)
(3)
(3)
(4)
(2)
Quiet Core (Low) Power — V
must be tied externally to all other chip power inputs. The user must provide adequate external
decoupling capacitors. There are four V inputs.
is an isolated power for the internal processing logic. This input
CCQL
CCQL
CCQL
V
Quiet External (High) Power — V
is a quiet power source for I/O lines. This input must be tied
CCQH
CCQH
externally to all other chip power inputs. The user must provide adequate decoupling capacitors. There
are three V inputs.
CCQH
V
Address Bus Power — V
is an isolated power for sections of the address bus I/O drivers. This input
CCA
CCD
CCC
CCA
must be tied externally to all other chip power inputs. The user must provide adequate external
decoupling capacitors. There are three V inputs.
CCA
V
Data Bus Power — V
is an isolated power for sections of the data bus I/O drivers. This input must
CCD
be tied externally to all other chip power inputs. The user must provide adequate external decoupling
capacitors. There are four V inputs.
CCD
V
Bus Control Power — V
is an isolated power for the bus control I/O drivers. This input must be tied
CCC
externally to all other chip power inputs. The user must provide adequate external decoupling
capacitors. There are two V inputs.
CCC
V
Host Power — V
is an isolated power for the HDI08 I/O drivers. This input must be tied externally
CCH
CCH
to all other chip power inputs. The user must provide adequate external decoupling capacitors. There
is one V input.
CCH
V
(2)
SHI, ESAI, ESAI_1, DAX and Timer Power — V
is an isolated power for the SHI, ESAI, ESAI_1,
CCS
CCS
DAX and Timer. This input must be tied externally to all other chip power inputs. The user must provide
adequate external decoupling capacitors. There are two V inputs.
CCS
2.3
Ground
Table 2-3 Grounds
Description
PLL Ground — GND is a ground dedicated for PLL use. The connection should be provided with an
Ground Name
GND
P
P
extremely low-impedance path to ground. V
should be bypassed to GND by a 0.47 µF capacitor
CCP
P
located as close as possible to the chip package. There is one GND connection.
P
GND (4)
Quiet Ground — GND is an isolated ground for the internal processing logic. This connection must
Q
Q
be tied externally to all other chip ground connections. The user must provide adequate external
decoupling capacitors. There are four GND connections.
Q
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Clock and PLL
Ground Name
Table 2-3 Grounds (continued)
Description
GND (4)
Address Bus Ground — GND is an isolated ground for sections of the address bus I/O drivers. This
A
A
connection must be tied externally to all other chip ground connections. The user must provide
adequate external decoupling capacitors. There are four GND connections.
A
GND (4)
Data Bus Ground — GND is an isolated ground for sections of the data bus I/O drivers. This
D
D
connection must be tied externally to all other chip ground connections. The user must provide
adequate external decoupling capacitors. There are four GND connections.
D
GND (2)
Bus Control Ground — GND is an isolated ground for the bus control I/O drivers. This connection
C
C
must be tied externally to all other chip ground connections. The user must provide adequate external
decoupling capacitors. There are two GND connections.
C
GND
Host Ground — GND is an isolated ground for the HD08 I/O drivers. This connection must be tied
H
h
externally to all other chip ground connections. The user must provide adequate external decoupling
capacitors. There is one GND connection.
H
GND (2)
SHI, ESAI, ESAI_1, DAX and Timer Ground — GND is an isolated ground for the SHI, ESAI, ESAI_1,
S
S
DAX and Timer. This connection must be tied externally to all other chip ground connections. The user
must provide adequate external decoupling capacitors. There are two GND connections.
S
2.4
Clock and PLL
Table 2-4 Clock and PLL Signals
Signal
Name
State during
Type
Signal Description
Reset
EXTAL
Input
Input
External Clock Input — An external clock source must be connected to EXTAL
in order to supply the clock to the internal clock generator and PLL.
This input cannot tolerate 5 V.
PCAP
Input
Input
Input
Input
PLL Capacitor — PCAP is an input connecting an off-chip capacitor to the PLL
filter. Connect one capacitor terminal to PCAP and the other terminal to V
.
CCP
If the PLL is not used, PCAP may be tied to V , GND, or left floating.
CC
PINIT/NMI
PLL Initial/Nonmaskable Interrupt — During assertion of RESET, the value of
PINIT/NMI is written into the PLL Enable (PEN) bit of the PLL control register,
determining whether the PLL is enabled or disabled. After RESET de assertion
and during normal instruction processing, the PINIT/NMI Schmitt-trigger input
is a negative-edge-triggered nonmaskable interrupt (NMI) request internally
synchronized to internal system clock.
This input cannot tolerate 5 V.
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External Memory Expansion Port (Port A)
2.5
External Memory Expansion Port (Port A)
When the DSP56364 enters a low-power standby mode (stop or wait), it releases bus mastership and
tri-states the relevant port A signals: A0 – A17, D0 – D23, AA0/RAS0 – AA2/RAS2, RD, WR, BB, CAS.
2.5.1
External Address Bus
Table 2-5 External Address Bus Signals
State during
Reset
Signal Name
A0–A17
Type
Signal Description
Output
Tri-stated
Address Bus — When the DSP is the bus master, A0 – A17 are active-high
outputs that specify the address for external program and data memory
accesses. Otherwise, the signals are tri-stated. To minimize power dissipation,
A0 – A17 do not change state when external memory spaces are not being
accessed.
2.5.2
External Data Bus
Table 2-6 External Data Bus Signals
State during Reset Signal Description
Tri-stated
Signal Name
Type
D0–D23
Input/Output
Data Bus — When the DSP is the bus master,
D0 – D23 are active-high, bidirectional input/outputs that provide the
bidirectional data bus for external program and data memory
accesses. Otherwise,
D0 – D23 are tri-stated.
2.5.3
External Bus Control
Table 2-7 External Bus Control Signals
State during
Reset
Signal Name
Type
Signal Description
AA0–AA2/RAS0
Output
Tri-stated
Tri-stated
Tri-stated
Address Attribute or Row Address Strobe — When defined as AA, these
signals can be used as chip selects or additional address lines. When defined
as RAS, these signals can be used as RAS for DRAM interface. These
signals are tri-statable outputs with programmable polarity.
– RAS2
CAS
RD
Output
Output
Column Address Strobe — When the DSP is the bus master, CAS is an
active-low output used by DRAM to strobe the column address. Otherwise, if
the bus mastership enable (BME) bit in the DRAM control register is cleared,
the signal is tri-stated.
Read Enable — When the DSP is the bus master, RD is an active-low output
that is asserted to read external memory on the data bus (D0-D23).
Otherwise, RD is tri-stated.
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External Memory Expansion Port (Port A)
Table 2-7 External Bus Control Signals (continued)
State during
Reset
Signal Name
Type
Signal Description
WR
Output
Tri-stated
Write Enable — When the DSP is the bus master, WR is an active-low output
that is asserted to write external memory on the data bus (D0-D23).
Otherwise, WR is tri-stated.
TA
Input
Ignored Input Transfer Acknowledge — If the DSP is the bus master and there is no
external bus activity, or the DSP is not the bus master, the TA input is ignored.
The TA input is a data transfer acknowledge (DTACK) function that can extend
an external bus cycle indefinitely. Any number of wait states (1, 2. . .infinity)
may be added to the wait states inserted by the BCR by keeping TA
deasserted. In typical operation, TA is deasserted at the start of a bus cycle,
is asserted to enable completion of the bus cycle, and is deasserted before
the next bus cycle. The current bus cycle completes one clock period after TA
is asserted synchronous to the internal system clock. The number of wait
states is determined by the TA input or by the bus control register (BCR),
whichever is longer. The BCR can be used to set the minimum number of wait
states in external bus cycles.
In order to use the TA functionality, the BCR must be programmed to at least
one wait state. A zero wait state access cannot be extended by TA
deassertion, otherwise improper operation may result. TA can operate
synchronously or asynchronously, depending on the setting of the TAS bit in
the operating mode register (OMR).
TA functionality may not be used while performing DRAM type accesses,
otherwise improper operation may result.
BR
Output
Output
Bus Request — BR is an active-low output, never tri-stated. BR is asserted
(deasserted) when the DSP requests bus mastership. BR is deasserted when the DSP no
longer needs the bus. BR may be asserted or deasserted independent of
whether the DSP56364 is a bus master or a bus slave. Bus “parking” allows
BR to be deasserted even though the DSP56364 is the bus master. (See the
description of bus “parking” in the BB signal description.) The bus request
hold (BRH) bit in the BCR allows BR to be asserted under software control
even though the DSP does not need the bus. BR is typically sent to an
external bus arbitrator that controls the priority, parking, and tenure of each
master on the same external bus. BR is only affected by DSP requests for the
external bus, never for the internal bus. During hardware reset, BR is
deasserted and the arbitration is reset to the bus slave state.
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Interrupt and Mode Control
Table 2-7 External Bus Control Signals (continued)
State during
Signal Description
Reset
Signal Name
Type
BG
Input
Ignored Input Bus Grant — BG is an active-low input. BG is asserted by an external bus
arbitration circuit when the DSP56364 becomes the next bus master. When
BG is asserted, the DSP56364 must wait until BB is deasserted before taking
bus mastership. When BG is deasserted, bus mastership is typically given up
at the end of the current bus cycle. This may occur in the middle of an
instruction that requires more than one external bus cycle for execution.
For proper BG operation, the asynchronous bus arbitration enable bit (ABE)
in the OMR register must be set.
BB
Input/
Output
Input
Bus Busy — BB is a bidirectional active-low input/output. BB indicates that
the bus is active. Only after BB is deasserted can the pending bus master
become the bus master (and then assert the signal again). The bus master
may keep BB asserted after ceasing bus activity regardless of whether BR is
asserted or deasserted. This is called “bus parking” and allows the current
bus master to reuse the bus without rearbitration until another device requires
the bus. The deassertion of BB is done by an “active pull-up” method (i.e., BB
is driven high and then released and held high by an external pull-up resistor).
For proper BB operation, the asynchronous bus arbitration enable bit (ABE)
in the OMR register must be set.
BB requires an external pull-up resistor.
2.6
Interrupt and Mode Control
The interrupt and mode control signals select the chip’s operating mode as it comes out of hardware reset.
After RESET is deasserted, these inputs are hardware interrupt request lines.
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Interrupt and Mode Control
Table 2-8 Interrupt and Mode Control
State during
Signal Name
Type
Signal Description
Reset
MODA/IRQA
Input
Input
Mode Select A/External Interrupt Request A — MODA/IRQA is an active-low
Schmitt-trigger input, internally synchronized to the DSP clock. MODA/IRQA
selects the initial chip operating mode during hardware reset and becomes a
level-sensitive or negative-edge-triggered, maskable interrupt request input
during normal instruction processing. MODA, MODB, MODC, and MODD select
one of 16 initial chip operating modes, latched into the OMR when the RESET
signal is deasserted. If the processor is in the stop standby state and the
MODA/IRQA pin is pulled to GND, the processor will exit the stop state.
This input is 5 V tolerant.
MODB/IRQB
MODC/IRQC
MODD/IRQD
RESET
Input
Input
Input
Input
Input
Input
Input
Input
Mode Select B/External Interrupt Request B — MODB/IRQB is an active-low
Schmitt-trigger input, internally synchronized to the DSP clock. MODB/IRQB
selects the initial chip operating mode during hardware reset and becomes a
level-sensitive or negative-edge-triggered, maskable interrupt request input
during normal instruction processing. MODA, MODB, MODC, and MODD select
one of 16 initial chip operating modes, latched into OMR when the RESET
signal is deasserted.
This input is 5 V tolerant.
Mode Select C/External Interrupt Request C — MODC/IRQC is an active-low
Schmitt-trigger input, internally synchronized to the DSP clock. MODC/IRQC
selects the initial chip operating mode during hardware reset and becomes a
level-sensitive or negative-edge-triggered, maskable interrupt request input
during normal instruction processing. MODA, MODB, MODC, and MODD select
one of 16 initial chip operating modes, latched into OMR when the RESET
signal is deasserted.
This input is 5 V tolerant.
Mode Select D/External Interrupt Request D — MODD/IRQD is an active-low
Schmitt-trigger input, internally synchronized to the DSP clock. MODD/IRQD
selects the initial chip operating mode during hardware reset and becomes a
level-sensitive or negative-edge-triggered, maskable interrupt request input
during normal instruction processing. MODA, MODB, MODC, and MODD select
one of 16 initial chip operating modes, latched into OMR when the RESET
signal is deasserted.
This input is 5 V tolerant.
Reset — RESET is an active-low, Schmitt-trigger input. When asserted, the
chip is placed in the Reset state and the internal phase generator is reset. The
Schmitt-trigger input allows a slowly rising input (such as a capacitor charging)
to reset the chip reliably. When the RESET signal is deasserted, the initial chip
operating mode is latched from the MODA, MODB, MODC, and MODD inputs.
The RESET signal must be asserted during power up. A stable EXTAL signal
must be supplied while RESET is being asserted.
This input is 5 V tolerant.
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PARALLEL HOST INTERFACE (HDI08)
2.7
PARALLEL HOST INTERFACE (HDI08)
The HDI08 provides a fast, 8-bit, parallel data port that may be connected directly to the host bus. The
HDI08 supports a variety of standard buses and can be directly connected to a number of industry standard
microcomputers, microprocessors, DSPs, and DMA hardware.
Table 2-9 Host Interface
State during
Signal Name
Type
Signal Description
Reset
H0 – H7
Input/
output
Host Data — When HDI08 is programmed to interface a nonmultiplexed
host bus and the HI function is selected, these signals are lines 0 – 7 of the
bidirectional, tri-state data bus.
HAD0 – HAD7
PB0 – PB7
Input/
output
Host Address/Data — When HDI08 is programmed to interface a
multiplexed host bus and the HI function is selected, these signals are lines
0 – 7 of the address/data bidirectional, multiplexed, tri-state bus.
Input, output, or
disconnected
GPIO
Port B 0–7 — When the HDI08 is configured as GPIO, these signals are
disconnected individually programmable as input, output, or internally disconnected.
The default state after reset for these signals is GPIO disconnected.
These inputs are 5 V tolerant.
HA0
Input
Input
GPIO
Host Address Input 0 — When the HDI08 is programmed to interface a
disconnected nonmultiplexed host bus and the HI function is selected, this signal is line 0
of the host address input bus.
HAS/HAS
Host Address Strobe — When HDI08 is programmed to interface a
multiplexed host bus and the HI function is selected, this signal is the host
address strobe (HAS) Schmitt-trigger input. The polarity of the address
strobe is programmable, but is configured active-low (HAS) following reset.
PB8
Input, output, or
disconnected
Port B 8 — When the HDI08 is configured as GPIO, this signal is individually
programmed as input, output, or internally disconnected.
The default state after reset for this signal is GPIO disconnected.
This input is 5 V tolerant.
HA1
HA8
PB9
Input
Input
GPIO
Host Address Input 1 — When the HDI08 is programmed to interface a
disconnected nonmultiplexed host bus and the HI function is selected, this signal is line 1
of the host address (HA1) input bus.
Host Address 8 — When HDI08 is programmed to interface a multiplexed
host bus and the HI function is selected, this signal is line 8 of the host
address (HA8) input bus.
Input, output, or
disconnected
Port B 9 — When the HDI08 is configured as GPIO, this signal is individually
programmed as input, output, or internally disconnected.
The default state after reset for this signal is GPIO disconnected.
This input is 5 V tolerant.
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PARALLEL HOST INTERFACE (HDI08)
Table 2-9 Host Interface (continued)
State during
Signal Name
Type
Signal Description
Reset
HA2
Input
GPIO
Host Address Input 2 — When the HDI08 is programmed to interface a
disconnected non-multiplexed host bus and the HI function is selected, this signal is line 2
of the host address (HA2) input bus.
HA9
Input
Host Address 9 — When HDI08 is programmed to interface a multiplexed
host bus and the HI function is selected, this signal is line 9 of the host
address (HA9) input bus.
PB10
Input, Output, or
Disconnected
Port B 10 — When the HDI08 is configured as GPIO, this signal is
individually programmed as input, output, or internally disconnected.
The default state after reset for this signal is GPIO disconnected.
This input is 5 V tolerant.
HRW
Input
Input
GPIO
Host Read/Write — When HDI08 is programmed to interface a
disconnected single-data-strobe host bus and the HI function is selected, this signal is the
Host Read/Write (HRW) input.
HRD/
HRD
Host Read Data — When HDI08 is programmed to interface a
double-data-strobe host bus and the HI function is selected, this signal is the
host read data strobe (HRD) Schmitt-trigger input. The polarity of the data
strobe is programmable, but is configured as active-low (HRD) after reset.
PB11
Input, Output, or
Disconnected
Port B 11 — When the HDI08 is configured as GPIO, this signal is
individually programmed as input, output, or internally disconnected.
The default state after reset for this signal is GPIO disconnected.
This input is 5 V tolerant.
HDS/
HDS
Input
Input
GPIO
Host Data Strobe — When HDI08 is programmed to interface a
disconnected single-data-strobe host bus and the HI function is selected, this signal is the
host data strobe (HDS) Schmitt-trigger input. The polarity of the data strobe
is programmable, but is configured as active-low (HDS) following reset.
HWR/
HWR
Host Write Data — When HDI08 is programmed to interface a
double-data-strobe host bus and the HI function is selected, this signal is the
host write data strobe (HWR) Schmitt-trigger input. The polarity of the data
strobe is programmable, but is configured as active-low (HWR) following
reset.
PB12
Input, output, or
disconnected
Port B 12 — When the HDI08 is configured as GPIO, this signal is
individually programmed as input, output, or internally disconnected.
The default state after reset for this signal is GPIO disconnected.
This input is 5 V tolerant.
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PARALLEL HOST INTERFACE (HDI08)
Table 2-9 Host Interface (continued)
State during
Signal Name
Type
Signal Description
Reset
HCS
Input
GPIO
Host Chip Select — When HDI08 is programmed to interface a
disconnected nonmultiplexed host bus and the HI function is selected, this signal is the
host chip select (HCS) input. The polarity of the chip select is
programmable, but is configured active-low (HCS) after reset.
HA10
PB13
Input
Host Address 10 — When HDI08 is programmed to interface a multiplexed
host bus and the HI function is selected, this signal is line 10 of the host
address (HA10) input bus.
Input, output, or
disconnected
Port B 13 — When the HDI08 is configured as GPIO, this signal is
individually programmed as input, output, or internally disconnected.
The default state after reset for this signal is GPIO disconnected.
This input is 5 V tolerant.
HOREQ/HOR
EQ
Output
Output
GPIO
Host Request — When HDI08 is programmed to interface a single host
disconnected request host bus and the HI function is selected, this signal is the host
request (HOREQ) output. The polarity of the host request is programmable,
but is configured as active-low (HOREQ) following reset. The host request
may be programmed as a driven or open-drain output.
HTRQ/
HTRQ
Transmit Host Request — When HDI08 is programmed to interface a
double host request host bus and the HI function is selected, this signal is
the transmit host request (HTRQ) output. The polarity of the host request is
programmable, but is configured as active-low (HTRQ) following reset. The
host request may be programmed as a driven or open-drain output.
PB14
Input, output, or
disconnected
Port B 14 — When the HDI08 is configured as GPIO, this signal is
individually programmed as input, output, or internally disconnected.
The default state after reset for this signal is GPIO disconnected.
This input is 5 V tolerant.
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Serial Host Interface
Signal Name
Table 2-9 Host Interface (continued)
State during
Type
Signal Description
Reset
HACK/
HACK
Input
GPIO
Host Acknowledge — When HDI08 is programmed to interface a single
disconnected host request host bus and the HI function is selected, this signal is the host
acknowledge (HACK) Schmitt-trigger input. The polarity of the host
acknowledge is programmable, but is configured as active-low (HACK) after
reset.
HRRQ/
HRRQ
Output
Receive Host Request — When HDI08 is programmed to interface a
double host request host bus and the HI function is selected, this signal is
the receive host request (HRRQ) output. The polarity of the host request is
programmable, but is configured as active-low (HRRQ) after reset. The host
request may be programmed as a driven or open-drain output.
PB15
Input, output, or
disconnected
Port B 15 — When the HDI08 is configured as GPIO, this signal is
individually programmed as input, output, or internally disconnected.
The default state after reset for this signal is GPIO disconnected.
This input is 5 V tolerant.
2.8
Serial Host Interface
2
The SHI has five I/O signals that can be configured to allow the SHI to operate in either SPI or I C mode.
Table 2-10 Serial Host Interface Signals
Signal
Name
State during
Reset
Signal Type
Signal Description
SCK
Input or output
Tri-stated
SPI Serial Clock — The SCK signal is an output when the SPI is configured as
a master and a Schmitt-trigger input when the SPI is configured as a slave.
When the SPI is configured as a master, the SCK signal is derived from the
internal SHI clock generator. When the SPI is configured as a slave, the SCK
signal is an input, and the clock signal from the external master synchronizes
the data transfer. The SCK signal is ignored by the SPI if it is defined as a slave
and the slave select (SS) signal is not asserted. In both the master and slave
SPI devices, data is shifted on one edge of the SCK signal and is sampled on
the opposite edge where data is stable. Edge polarity is determined by the SPI
transfer protocol.
2
2
2
SCL
Input or output
I C Serial Clock — SCL carries the clock for I C bus transactions in the I C
mode. SCL is a Schmitt-trigger input when configured as a slave and an
open-drain output when configured as a master. SCL should be connected to
V
through a pull-up resistor.
CC
This signal is tri-stated during hardware, software, and individual reset. Thus,
there is no need for an external pull-up in this state.
This input is 5 V tolerant.
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Serial Host Interface
Table 2-10 Serial Host Interface Signals (continued)
Signal
Name
State during
Signal Description
Reset
Signal Type
MISO
Input or output
Tri-stated
SPI Master-In-Slave-Out — When the SPI is configured as a master, MISO is
the master data input line. The MISO signal is used in conjunction with the
MOSI signal for transmitting and receiving serial data. This signal is a
Schmitt-trigger input when configured for the SPI Master mode, an output when
configured for the SPI Slave mode, and tri-stated if configured for the SPI Slave
mode when SS is deasserted. An external pull-up resistor is not required for SPI
operation.
2
2
SDA
Input or
open-drain
output
I C Data and Acknowledge — In I C mode, SDA is a Schmitt-trigger input
when receiving and an open-drain output when transmitting. SDA should be
connected to V through a pull-up resistor. SDA carries the data for I C
2
CC
transactions. The data in SDA must be stable during the high period of SCL.
The data in SDA is only allowed to change when SCL is low. When the bus is
free, SDA is high. The SDA line is only allowed to change during the time SCL
is high in the case of start and stop events. A high-to-low transition of the SDA
line while SCL is high is a unique situation, and is defined as the start event. A
low-to-high transition of SDA while SCL is high is a unique situation defined as
the stop event.
This signal is tri-stated during hardware, software, and individual reset. Thus,
there is no need for an external pull-up in this state.
This input is 5 V tolerant.
MOSI
HA0
Input or output
Tri-stated
SPI Master-Out-Slave-In — When the SPI is configured as a master, MOSI is
the master data output line. The MOSI signal is used in conjunction with the
MISO signal for transmitting and receiving serial data. MOSI is the slave data
input line when the SPI is configured as a slave. This signal is a Schmitt-trigger
input when configured for the SPI Slave mode.
2
Input
I C Slave Address 0 — This signal uses a Schmitt-trigger input when
2
2
configured for the I C mode. When configured for I C slave mode, the HA0
signal is used to form the slave device address. HA0 is ignored when configured
2
for the I C master mode.
This signal is tri-stated during hardware, software, and individual reset. Thus,
there is no need for an external pull-up in this state.
This input is 5 V tolerant.
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Serial Host Interface
Signal
Table 2-10 Serial Host Interface Signals (continued)
State during
Signal Description
Reset
Signal Type
Name
SS
Input
Tri-stated
SPI Slave Select — This signal is an active low Schmitt-trigger input when
configured for the SPI mode. When configured for the SPI Slave mode, this
signal is used to enable the SPI slave for transfer. When configured for the SPI
master mode, this signal should be kept deasserted (pulled high). If it is
asserted while configured as SPI master, a bus error condition is flagged. If SS
is deasserted, the SHI ignores SCK clocks and keeps the MISO output signal
in the high-impedance state.
2
HA2
Input
I C Slave Address 2 — This signal uses a Schmitt-trigger input when
2
2
configured for the I C mode. When configured for the I C Slave mode, the HA2
2
signal is used to form the slave device address. HA2 is ignored in the I C master
mode.
This signal is tri-stated during hardware, software, and individual reset. Thus,
there is no need for an external pull-up in this state.
This input is 5 V tolerant.
HREQ Input or Output
Tri-stated
Host Request — This signal is an active low Schmitt-trigger input when
configured for the master mode but an active low output when configured for the
slave mode.
When configured for the slave mode, HREQ is asserted to indicate that the SHI
is ready for the next data word transfer and deasserted at the first clock pulse
of the new data word transfer. When configured for the master mode, HREQ is
an input. When asserted by the external slave device, it will trigger the start of
the data word transfer by the master. After finishing the data word transfer, the
master will await the next assertion of HREQ to proceed to the next transfer.
This signal is tri-stated during hardware, software, personal reset, or when the
HREQ1–HREQ0 bits in the HCSR are cleared. There is no need for external
pull-up in this state.
This input is 5 V tolerant.
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Enhanced Serial Audio Interface
2.9
Enhanced Serial Audio Interface
Table 2-11 Enhanced Serial Audio Interface Signals
State during
Reset
Signal Name
Signal Type
Signal Description
HCKR
Input or output
GPIO
High Frequency Clock for Receiver — When programmed as an
disconnected input, this signal provides a high frequency clock source for the ESAI
receiver as an alternate to the DSP core clock. When programmed as
an output, this signal can serve as a high-frequency sample clock (e.g.,
for external digital to analog converters [DACs]) or as an additional
system clock.
PC2
HCKT
PC5
Input, output, or
disconnected
Port C 2 — When the ESAI is configured as GPIO, this signal is
individually programmable as input, output, or internally disconnected.
The default state after reset is GPIO disconnected.
This input is 5 V tolerant.
Input or output
GPIO
High Frequency Clock for Transmitter — When programmed as an
disconnected input, this signal provides a high frequency clock source for the ESAI
transmitter as an alternate to the DSP core clock. When programmed as
an output, this signal can serve as a high frequency sample clock (e.g.,
for external DACs) or as an additional system clock.
Input, output, or
disconnected
Port C 5 — When the ESAI is configured as GPIO, this signal is
individually programmable as input, output, or internally disconnected.
The default state after reset is GPIO disconnected.
This input is 5 V tolerant.
FSR
Input or output
GPIO
Frame Sync for Receiver — This is the receiver frame sync
disconnected input/output signal. In the asynchronous mode (SYN=0), the FSR pin
operates as the frame sync input or output used by all the enabled
receivers. In the synchronous mode (SYN=1), it operates as either the
serial flag 1 pin (TEBE=0), or as the transmitter external buffer enable
control (TEBE=1, RFSD=1).
When this pin is configured as serial flag pin, its direction is determined
by the RFSD bit in the RCCR register. When configured as the output
flag OF1, this pin will reflect the value of the OF1 bit in the SAICR
register, and the data in the OF1 bit will show up at the pin synchronized
to the frame sync in normal mode or the slot in network mode. When
configured as the input flag IF1, the data value at the pin will be stored
in the IF1 bit in the SAISR register, synchronized by the frame sync in
normal mode or the slot in network mode.
PC1
Input, output, or
disconnected
Port C 1 — When the ESAI is configured as GPIO, this signal is
individually programmable as input, output, or internally disconnected.
The default state after reset is GPIO disconnected.
This input is 5 V tolerant.
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Enhanced Serial Audio Interface
Table 2-11 Enhanced Serial Audio Interface Signals (continued)
State during
Reset
Signal Name
Signal Type
Signal Description
FST
Input or output
GPIO
Frame Sync for Transmitter — This is the transmitter frame sync
disconnected input/output signal. For synchronous mode, this signal is the frame sync
for both transmitters and receivers. For asynchronous mode, FST is the
frame sync for the transmitters only. The direction is determined by the
transmitter frame sync direction (TFSD) bit in the ESAI transmit clock
control register (TCCR).
PC4
Input, output, or
disconnected
Port C 4 — When the ESAI is configured as GPIO, this signal is
individually programmable as input, output, or internally disconnected.
The default state after reset is GPIO disconnected.
This input is 5 V tolerant.
SCKR
Input or output
GPIO
Receiver Serial Clock — SCKR provides the receiver serial bit clock for
disconnected the ESAI. The SCKR operates as a clock input or output used by all the
enabled receivers in the asynchronous mode (SYN=0), or as serial flag
0 pin in the synchronous mode (SYN=1).
When this pin is configured as serial flag pin, its direction is determined
by the RCKD bit in the RCCR register. When configured as the output
flag OF0, this pin will reflect the value of the OF0 bit in the SAICR
register, and the data in the OF0 bit will show up at the pin synchronized
to the frame sync in normal mode or the slot in network mode. When
configured as the input flag IF0, the data value at the pin will be stored
in the IF0 bit in the SAISR register, synchronized by the frame sync in
normal mode or the slot in network mode.
PC0
Input, output, or
disconnected
Port C 0 — When the ESAI is configured as GPIO, this signal is
individually programmable as input, output, or internally disconnected.
The default state after reset is GPIO disconnected.
This input is 5 V tolerant.
SCKT
PC3
Input or output
GPIO
Transmitter Serial Clock — This signal provides the serial bit rate clock
disconnected for the ESAI. SCKT is a clock input or output used by all enabled
transmitters and receivers in synchronous mode, or by all enabled
transmitters in asynchronous mode.
Input, output, or
disconnected
Port C 3 — When the ESAI is configured as GPIO, this signal is
individually programmable as input, output, or internally disconnected.
The default state after reset is GPIO disconnected.
This input is 5 V tolerant.
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Enhanced Serial Audio Interface
Table 2-11 Enhanced Serial Audio Interface Signals (continued)
State during
Reset
Signal Name
Signal Type
Signal Description
SDO5
Output
GPIO
Serial Data Output 5 — When programmed as a transmitter, SDO5 is
disconnected used to transmit data from the TX5 serial transmit shift register.
SDI0
PC6
Input
Serial Data Input 0 — When programmed as a receiver, SDI0 is used
to receive serial data into the RX0 serial receive shift register.
Input, output, or
disconnected
Port C 6 — When the ESAI is configured as GPIO, this signal is
individually programmable as input, output, or internally disconnected.
The default state after reset is GPIO disconnected.
This input is 5 V tolerant.
SDO4
SDI1
PC7
Output
Input
GPIO
Serial Data Output 4 — When programmed as a transmitter, SDO4 is
disconnected used to transmit data from the TX4 serial transmit shift register.
Serial Data Input 1 — When programmed as a receiver, SDI1 is used
to receive serial data into the RX1 serial receive shift register.
Input, output, or
disconnected
Port C 7 — When the ESAI is configured as GPIO, this signal is
individually programmable as input, output, or internally disconnected.
The default state after reset is GPIO disconnected.
This input is 5 V tolerant.
SDO3/
SDO3_1
Output
Input
GPIO
Serial Data Output 3 — When programmed as a transmitter, SDO3 is
disconnected used to transmit data from the TX3 serial transmit shift register.
When enabled for ESAI_1 operation, this is the ESAI_1 Serial Data
Output 3.
SDI2/
Serial Data Input 2 — When programmed as a receiver, SDI2 is used
SDI2_1
to receive serial data into the RX2 serial receive shift register.
When enabled for ESAI_1 operation, this is the ESAI_1 Serial Data Input
2.
PC8/PE8
Input, output, or
disconnected
Port C 8 — When the ESAI is configured as GPIO, this signal is
individually programmable as input, output, or internally disconnected.
When enabled for ESAI_1 GPIO, this is the Port E 8 signal.
The default state after reset is GPIO disconnected.
This input is 5 V tolerant.
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Enhanced Serial Audio Interface
Table 2-11 Enhanced Serial Audio Interface Signals (continued)
State during
Reset
Signal Name
Signal Type
Signal Description
SDO2/
Output
GPIO
Serial Data Output 2 — When programmed as a transmitter, SDO2 is
SDO2_1
disconnected used to transmit data from the TX2 serial transmit shift register
When enabled for ESAI_1 operation, this is the ESAI_1 Serial Data
Output 2.
SDI3/
Input
Serial Data Input 3 — When programmed as a receiver, SDI3 is used
SDI3_1
to receive serial data into the RX3 serial receive shift register.
When enabled for ESAI_1 operation, this is the ESAI_1 Serial Data Input
3.
PC9/PE9
Input, output, or
disconnected
Port C 9 — When the ESAI is configured as GPIO, this signal is
individually programmable as input, output, or internally disconnected.
When enabled for ESAI_1 GPIO, this is the Port E 9 signal.
The default state after reset is GPIO disconnected.
This input is 5 V tolerant.
SDO1/
SDO1_1
Output
GPIO
disconnected serial transmit shift register.
When enabled for ESAI_1 operation, this is the ESAI_1 Serial Data
Serial Data Output 1 — SDO1 is used to transmit data from the TX1
Output 1.
PC10/PE10 Input, output, or
disconnected
Port C 10 — When the ESAI is configured as GPIO, this signal is
individually programmable as input, output, or internally disconnected.
When enabled for ESAI_1 GPIO, this is the Port E 10 signal.
The default state after reset is GPIO disconnected.
This input is 5 V tolerant.
SDO0/
Output
GPIO
Serial Data Output 0 — SDO0 is used to transmit data from the TX0
SDO0_1
disconnected serial transmit shift register.
When enabled for ESAI_1 operation, this is the ESAI_1 Serial Data
Output 0.
PC11/
PE11
Input, output, or
disconnected
Port C 11 — When the ESAI is configured as GPIO, this signal is
individually programmable as input, output, or internally disconnected.
When enabled for ESAI_1 GPIO, this is the Port E 11 signal.
The default state after reset is GPIO disconnected.
This input is 5 V tolerant.
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Enhanced Serial Audio Interface_1
2.10 Enhanced Serial Audio Interface_1
Table 2-12 Enhanced Serial Audio Interface_1 Signals
Signal
Name
State during
Signal Type
Signal Description
Reset
FSR_1
Input or output
GPIO
Frame Sync for Receiver_1 — This is the receiver frame sync
disconnected input/output signal. In the asynchronous mode (SYN=0), the FSR pin
operates as the frame sync input or output used by all the enabled
receivers. In the synchronous mode (SYN=1), it operates as either the
serial flag 1 pin (TEBE=0), or as the transmitter external buffer enable
control (TEBE=1, RFSD=1).
When this pin is configured as serial flag pin, its direction is determined
by the RFSD bit in the RCCR register. When configured as the output
flag OF1, this pin will reflect the value of the OF1 bit in the SAICR
register, and the data in the OF1 bit will show up at the pin synchronized
to the frame sync in normal mode or the slot in network mode. When
configured as the input flag IF1, the data value at the pin will be stored
in the IF1 bit in the SAISR register, synchronized by the frame sync in
normal mode or the slot in network mode.
PE1
Input, output, or
disconnected
Port E 1—When the ESAI is configured as GPIO, this signal is
individually programmable as input, output, or internally disconnected.
The default state after reset is GPIO disconnected.
This input cannot tolerate 5 V.
FST_1
Input or output
GPIO
Frame Sync for Transmitter_1—This is the transmitter frame sync
disconnected input/output signal. For synchronous mode, this signal is the frame sync
for both transmitters and receivers. For asynchronous mode, FST is the
frame sync for the transmitters only. The direction is determined by the
transmitter frame sync direction (TFSD) bit in the ESAI transmit clock
control register (TCCR).
PE4
Input, output, or
disconnected
Port E 4—When the ESAI is configured as GPIO, this signal is
individually programmable as input, output, or internally disconnected.
The default state after reset is GPIO disconnected.
This input cannot tolerate 5 V.
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Enhanced Serial Audio Interface_1
Table 2-12 Enhanced Serial Audio Interface_1 Signals (continued)
Signal
Name
State during
Reset
Signal Type
Signal Description
SCKR_1
Input or output
GPIO
Receiver Serial Clock_1 — SCKR provides the receiver serial bit clock
disconnected for the ESAI. The SCKR operates as a clock input or output used by all
the enabled receivers in the asynchronous mode (SYN=0), or as serial
flag 0 pin in the synchronous mode (SYN=1).
When this pin is configured as serial flag pin, its direction is determined
by the RCKD bit in the RCCR register. When configured as the output
flag OF0, this pin will reflect the value of the OF0 bit in the SAICR
register, and the data in the OF0 bit will show up at the pin synchronized
to the frame sync in normal mode or the slot in network mode. When
configured as the input flag IF0, the data value at the pin will be stored
in the IF0 bit in the SAISR register, synchronized by the frame sync in
normal mode or the slot in network mode.
PE0
Input, output, or
disconnected
Port E 0 — When the ESAI is configured as GPIO, this signal is
individually programmable as input, output, or internally disconnected.
The default state after reset is GPIO disconnected.
This input cannot tolerate 5 V.
SCKT_1
PE3
Input or output
GPIO
Transmitter Serial Clock_1 — This signal provides the serial bit rate
disconnected clock for the ESAI. SCKT is a clock input or output used by all enabled
transmitters and receivers in synchronous mode, or by all enabled
transmitters in asynchronous mode.
Input, output, or
disconnected
Port E 3 — When the ESAI is configured as GPIO, this signal is
individually programmable as input, output, or internally disconnected.
The default state after reset is GPIO disconnected.
This input cannot tolerate 5 V.
SDO5_1
SDI0_1
PE6
Output
Input
GPIO
Serial Data Output 5_1 — When programmed as a transmitter, SDO5
disconnected is used to transmit data from the TX5 serial transmit shift register.
Serial Data Input 0_1 — When programmed as a receiver, SDI0 is used
to receive serial data into the RX0 serial receive shift register.
Input, output, or
disconnected
Port E 6 — When the ESAI is configured as GPIO, this signal is
individually programmable as input, output, or internally disconnected.
The default state after reset is GPIO disconnected.
This input cannot tolerate 5 V.
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SPDIF Transmitter Digital Audio Interface
Table 2-12 Enhanced Serial Audio Interface_1 Signals (continued)
Signal
Name
State during
Reset
Signal Type
Signal Description
SDO4_1
SDI1_1
PE7
Output
GPIO
Serial Data Output 4_1 — When programmed as a transmitter, SDO4
disconnected is used to transmit data from the TX4 serial transmit shift register.
Input
Serial Data Input 1_1 — When programmed as a receiver, SDI1 is used
to receive serial data into the RX1 serial receive shift register.
Input, output, or
disconnected
Port E 7 — When the ESAI is configured as GPIO, this signal is
individually programmable as input, output, or internally disconnected.
The default state after reset is GPIO disconnected.
This input is 5 V tolerant.
2.11 SPDIF Transmitter Digital Audio Interface
Table 2-13 Digital Audio Interface (DAX) Signals
Signal
Name
State During
Reset
Type
Signal Description
ACI
Input
GPIO
Audio Clock Input — This is the DAX clock input. When programmed
Disconnected to use an external clock, this input supplies the DAX clock. The external
clock frequency must be 256, 384, or 512 times the audio sampling
frequency (256 × Fs, 384 × Fs or 512 × Fs, respectively).
PD0
Input,
Port D 0 — When the DAX is configured as GPIO, this signal is
output, or
individually programmable as input, output, or internally disconnected.
disconnected
The default state after reset is GPIO disconnected.
This input is 5 V tolerant.
ADO
PD1
Output
GPIO
Digital Audio Data Output — This signal is an audio and non-audio
Disconnected output in the form of AES/EBU, CP340 and IEC958 data in a biphase
mark format.
Input,
Port D 1 — When the DAX is configured as GPIO, this signal is
output, or
individually programmable as input, output, or internally disconnected.
disconnected
The default state after reset is GPIO disconnected.
This input is 5 V tolerant.
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Timer
2.12 Timer
Table 2-14 Timer Signal
Signal
Name
State during
Reset
Type
Signal Description
TIO0
Input or
Output
Input
Timer 0 Schmitt-Trigger Input/Output — When timer 0 functions as an
external event counter or in measurement mode, TIO0 is used as input.
When timer 0 functions in watchdog, timer, or pulse modulation mode,
TIO0 is used as output.
The default mode after reset is GPIO input. This can be changed to
output or configured as a timer input/output through the timer 0
control/status register (TCSR0). If TIO0 is not being used, it is
recommended to either define it as GPIO output immediately at the
beginning of operation or leave it defined as GPIO input but connected
to Vcc through a pull-up resistor in order to ensure a stable logic level at
this input.
This input is 5 V tolerant.
2.13 JTAG/OnCE Interface
Table 2-15 JTAG/OnCE Interface
Signal
Name
Signal
Type
State during
Reset
Signal Description
TCK
Input
Input
Test Clock — TCK is a test clock input signal used to synchronize the JTAG
test logic. It has an internal pull-up resistor.
This input is 5 V tolerant.
TDI
Input
Input
Test Data Input — TDI is a test data serial input signal used for test
instructions and data. TDI is sampled on the rising edge of TCK and has an
internal pull-up resistor.
This input is 5 V tolerant.
TDO
TMS
Output
Input
Tri-stated
Input
Test Data Output — TDO is a test data serial output signal used for test
instructions and data. TDO is tri-statable and is actively driven in the shift-IR
and shift-DR controller states. TDO changes on the falling edge of TCK.
Test Mode Select — TMS is an input signal used to sequence the test
controller’s state machine. TMS is sampled on the rising edge of TCK and has
an internal pull-up resistor.
This input is 5 V tolerant.
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3 Memory Configuration
3.1
Data and Program Memory Maps
The on-chip memory configuration of the DSP56366 is affected by the state of the CE (Cache Enable),
MSW0, MSW1, and MS (Memory Switch) control bits in the OMR register, and by the SC bit in the Status
ranges for the internal memory are shown in Table 3-2 and Table 3-3. The memory maps for each memory
Table 3-1 Internal Memory Configurations
Bit Settings
Memory Sizes (24-bit words)
Prog
RAM Cache
Prog
Prog
Boot
ROM
X Data Y Data X Data Y Data
MSW1 MSW0 CE
MS
SC
ROM
40K
40K
40K
40K
40K
40K
40K
40K
n.a.
n.a.
n.a.
n.a.
n.a.
n.a.
n.a.
n.a.
RAM
13K
13K
8K
RAM
7K
7K
5K
7K
7K
5K
7K
7K
7K
7K
5K
7K
7K
5K
7K
7K
ROM
32K
32K
32K
32K
32K
32K
32K
32K
32K
32K
32K
32K
32K
32K
32K
32K
ROM
8K
8K
8K
8K
8K
8K
8K
8K
8K
8K
8K
8K
8K
8K
8K
8K
X
X
0
0
1
0
0
1
X
X
0
0
1
0
0
1
X
X
0
1
0
0
1
0
X
X
0
1
0
0
1
0
0
1
0
0
0
1
1
1
0
1
0
0
0
1
1
1
0
0
1
1
1
1
1
1
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
3K
2K
10K
8K
5K
9K
7K
4K
3K
2K
10K
8K
5K
9K
7K
4K
n.a.
1K
192
192
192
192
192
192
192
192
n.a.
n.a.
n.a.
n.a.
n.a.
n.a.
n.a.
n.a.
n.a.
n.a.
n.a.
1K
8K
11K
8K
1K
8K
1K
11K
13K
13K
8K
n.a.
1K
n.a.
n.a.
n.a.
1K
8K
11K
8K
1K
8K
1K
11K
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
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Data and Program Memory Maps
Bit Settings
Table 3-2 On-chip RAM Memory Locations
RAM Memory Locations
Prog.
RAM
Prog.
Cache
X Data
RAM
Y Data
RAM
MSW1
MSW0
CE
MS
SC
X
X
0
0
X
X
0
1
0
1
0
0
0
0
1
1
X
X
X
X
$0000 - $0BFF
$0000 - $07FF
$0000 -$27FF
n.a.
enabled
n.a.
$0000 - $33FF
$0000 - $33FF
$0000 - $1FFF
$0000 - $1FFF
$0000-$1BFF
$0000-$1BFF
$0000 - $13FF
$0000-$1BFF
$0000 - $1BFF and
$2400 - $27FF
n.a.
1
0
0
1
X
$0000 - $ 0FFF and
$2400 - $27FF
n.a.
$0000 - $2BFF
$0000-$1BFF
0
0
1
0
1
0
1
1
1
1
1
1
X
X
X
$0000 - $23FF
$0000 - $1BFF
$0000 - $0FFF
enabled
enabled
enabled
$0000 - $1FFF
$0000 - $1FFF
$0000 - $2BFF
$0000 - $13FF
$0000 - $1BFF
$0000 - $1BFF
Table 3-3 On-chip ROM Memory Locations
ROM Memory Locations
Bit Settings
Prog.
ROM
Boot.
ROM
X Data
ROM
Y Data
ROM
MSW1
MSW0
CE
MS
SC
X
X
X
X
X
0
$FF1000 -
$FFAFFF
$FF0000 -
$FF00BF
$004000-
$00BFFF
$004000-
$005FFF
X
X
X
1
no access
no access
$004000-
$00BFFF
$004000-
$005FFF
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Data and Program Memory Maps
PROGRAM
X DATA
Y DATA
$FFFFFF
$FFB000
$FFFFFF
$FFFF80
$FFF000
$FFFFFF
INTERNAL I/O
(128 words)
EXTERNAL I/O
(80 words)
INTERNAL
RESERVED
$FFFFB0
$FFFF80
EXTERNAL
INTERNAL I/O
(48 words)
40K INTERNAL
ROM
INTERNAL
RESERVED
$FF1000
EXTERNAL
INTERNAL
RESERVED
$FFF000
$FF0000
INTERNAL
RESERVED
$FF0000
$00C000
$FF00C0
$FF0000
BOOT ROM
EXTERNAL
EXTERNAL
$006000
32K INTERNAL
ROM
8K INTERNAL
ROM
$004000
$003400
EXTERNAL
$004000
$001C00
INT. RESERVED
INT. RESERVED
$000C00
$000000
13K INTERNAL
RAM
7K INTERNAL
RAM
3K INTERNAL
RAM
$000000
$000000
Figure 3-1 Memory Maps for MSW=(X,X), CE=0, MS=0, SC=0
PROGRAM
X DATA
Y DATA
$FFFFFF
$FFB000
$FFFFFF
$FFFF80
$FFF000
$FFFFFF
$FFFFB0
$FFFF80
INTERNAL I/O
(128 words)
EXTERNAL I/O
(80 words)
INTERNAL
RESERVED
EXTERNAL
INTERNAL I/O
(48 words)
40K INTERNAL
ROM
INTERNAL
RESERVED
$FF1000
EXTERNAL
INTERNAL
RESERVED
$FFF000
$FF0000
INTERNAL
RESERVED
$FF0000
$00C000
$FF00C0
$FF0000
BOOT ROM
EXTERNAL
EXTERNAL
$006000
32K INTERNAL
ROM
8K INTERNAL
ROM
$004000
$003400
EXTERNAL
$004000
$001C00
INT. RESERVED
INT. RESERVED
$000800
$000000
13K INTERNAL
RAM
7K INTERNAL
RAM
2K INTERNAL
RAM
$000000
$000000
1K I-CACHE ENABLED
Figure 3-2 Memory Maps for MSW=(X,X), CE=1, MS=0, SC=0
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Data and Program Memory Maps
PROGRAM
X DATA
Y DATA
$FFFFFF
$FFB000
$FFFFFF
$FFFF80
$FFF000
$FFFFFF
$FFFFB0
$FFFF80
INTERNAL I/O
(128 words)
EXTERNAL I/O
(80 words)
INTERNAL
RESERVED
EXTERNAL
INTERNAL I/O
(48 words)
40K INTERNAL
ROM
INTERNAL
RESERVED
$FF1000
EXTERNAL
INTERNAL
RESERVED
$FFF000
$FF0000
INTERNAL
RESERVED
$FF0000
$00C000
$FF00C0
$FF0000
BOOT ROM
EXTERNAL
EXTERNAL
$006000
32K INTERNAL
ROM
8K INTERNAL
ROM
$004000
$002000
EXTERNAL
$004000
$001400
INT. RESERVED
INT. RESERVED
$002800
$000000
8K INTERNAL
RAM
5K INTERNAL
RAM
10K INTERNAL
RAM
$000000
$000000
Figure 3-3 Memory Maps for MSW=(0,0), CE=0 MS=1, SC=0
PROGRAM
X DATA
Y DATA
$FFFFFF
$FFB000
$FFFFFF
$FFFF80
$FFF000
$FFFFFF
$FFFFB0
$FFFF80
INTERNAL I/O
(128 words)
EXTERNAL I/O
(80 words)
INTERNAL
RESERVED
EXTERNAL
INTERNAL I/O
(48 words)
40K INTERNAL
ROM
INTERNAL
RESERVED
$FF1000
EXTERNAL
INTERNAL
RESERVED
$FFF000
$FF0000
INTERNAL
RESERVED
$FF0000
$00C000
$FF00C0
$FF0000
BOOT ROM
EXTERNAL
EXTERNAL
$006000
32K INTERNAL
ROM
8K INTERNAL
ROM
EXTERNAL
$004000
$002000
$004000
$001C00
INT. RESERVED
INT. RESERVED
$002800
$002400
1K RAM
INT. RESERVED
$001C00
8K INTERNAL
RAM
7K INTERNAL
RAM
7K INTERNAL
RAM
$000000
$000000
$000000
Figure 3-4 Memory Maps for MSW=(0,1), CE=0, MS=1, SC=0
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Data and Program Memory Maps
PROGRAM
X DATA
Y DATA
$FFFFFF
$FFB000
$FFFFFF
$FFFF80
$FFF000
$FFFFFF
INTERNAL I/O
(128 words)
EXTERNAL I/O
(80 words)
INTERNAL
RESERVED
$FFFFB0
$FFFF80
EXTERNAL
INTERNAL I/O
(48 words)
40K INTERNAL
ROM
INTERNAL
RESERVED
$FF1000
EXTERNAL
INTERNAL
RESERVED
$FFF000
$FF0000
INTERNAL
RESERVED
$FF0000
$00C000
$FF00C0
$FF0000
BOOT ROM
EXTERNAL
EXTERNAL
$006000
32K INTERNAL
ROM
8K INTERNAL
ROM
EXTERNAL
$004000
$002C00
$004000
$001C00
INT. RESERVED
INT. RESERVED
$002800
$002400
1K RAM
INT. RESERVED
$001000
11K INTERNAL
RAM
7K INTERNAL
RAM
4K INTERNAL
RAM
$000000
$000000
$000000
Figure 3-5 Memory Maps for MSW=(1,0), CE=0, MS=1, SC=0
PROGRAM
X DATA
Y DATA
$FFFFFF
$FFB000
$FFFFFF
$FFFF80
$FFF000
$FFFFFF
$FFFFB0
$FFFF80
INTERNAL I/O
(128 words)
EXTERNAL I/O
(80 words)
INTERNAL
RESERVED
EXTERNAL
INTERNAL I/O
(48 words)
40K INTERNAL
ROM
INTERNAL
RESERVED
$FF1000
EXTERNAL
INTERNAL
RESERVED
$FFF000
$FF0000
INTERNAL
RESERVED
$FF0000
$00C000
$FF00C0
$FF0000
BOOT ROM
EXTERNAL
EXTERNAL
$006000
32K INTERNAL
ROM
8K INTERNAL
ROM
$004000
$002000
EXTERNAL
$004000
$001400
INT. RESERVED
INT. RESERVED
$002400
$000000
8K INTERNAL
RAM
5K INTERNAL
RAM
9K INTERNAL
RAM
$000000
$000000
1K I-CACHE ENABLED
Figure 3-6 Memory Maps for MSW=(0,0), CE=1, MS=1, SC=0
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Data and Program Memory Maps
PROGRAM
X DATA
Y DATA
$FFFFFF
$FFFFFF
$FFFF80
$FFF000
$FFFFFF
$FFFFB0
$FFFF80
INTERNAL I/O
(128 words)
EXTERNAL I/O
(80 words)
INTERNAL
RESERVED
$FFB000
EXTERNAL
INTERNAL I/O
(48 words)
40K INTERNAL
ROM
INTERNAL
RESERVED
$FF1000
EXTERNAL
INTERNAL
RESERVED
$FFF000
$FF0000
INTERNAL
RESERVED
$FF0000
$00C000
$FF00C0
$FF0000
BOOT ROM
EXTERNAL
EXTERNAL
$006000
32K INTERNAL
ROM
8K INTERNAL
ROM
$004000
$002000
EXTERNAL
$004000
$001C00
INT. RESERVED
INT. RESERVED
$002400
$001C00
INT. RESERVED
8K INTERNAL
RAM
7K INTERNAL
RAM
7K INTERNAL
RAM
$000000
$000000
$000000
1K I-CACHE ENABLED
Figure 3-7 Memory Maps for MSW=(0,1), CE=1, MS=1, SC=0
PROGRAM
X DATA
Y DATA
$FFFFFF
$FFB000
$FFFFFF
$FFFF80
$FFF000
$FFFFFF
$FFFFB0
$FFFF80
INTERNAL I/O
(128 words)
EXTERNAL I/O
(80 words)
INTERNAL
RESERVED
EXTERNAL
INTERNAL I/O
(48 words)
40K INTERNAL
ROM
INTERNAL
RESERVED
$FF1000
EXTERNAL
INTERNAL
RESERVED
$FFF000
$FF0000
INTERNAL
RESERVED
$FF0000
$00C000
$FF00C0
$FF0000
BOOT ROM
EXTERNAL
EXTERNAL
$006000
32K INTERNAL
ROM
8K INTERNAL
ROM
$004000
$002C00
EXTERNAL
$004000
$001C00
INT. RESERVED
INT. RESERVED
$002400
$001000
INT. RESERVED
11K INTERNAL
RAM
7K INTERNAL
RAM
4K INTERNAL
RAM
$000000
$000000
$000000
1K I-CACHE ENABLED
Figure 3-8 Memory Maps for MSW=(1,0), CE=1, MS=1, SC=0
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Data and Program Memory Maps
PROGRAM
X DATA
Y DATA
$FFFF
$FFFF
$FF80
$FFFF
INTERNAL I/O
(128 words)
EXTERNAL I/O
(82 words)
$FFB0
INTERNAL I/O
(46 words)
$FF80
EXTERNAL
EXTERNAL
EXTERNAL
$C000
$6000
32K INTERNAL
ROM
8K INTERNAL
ROM
$4000
$1C00
$4000
$3400
INT. RESERVED
INT. RESERVED
$0C00
$0000
13K INTERNAL
RAM
7K INTERNAL
RAM
3K INTERNAL
RAM
$0000
$0000
Figure 3-9 Memory Maps for MSW=(X,X), CE=0, MS=0, SC=1
PROGRAM
X DATA
Y DATA
$FFFF
$FFFF
$FF80
$FFFF
$FFB0
INTERNAL I/O
(128 words)
EXTERNAL I/O
(80 words)
INTERNAL I/O
(48words)
$FF80
EXTERNAL
EXTERNAL
EXTERNAL
$C000
$6000
32K INTERNAL
ROM
8K INTERNAL
ROM
$4000
$1C00
$4000
$3400
INT. RESERVED
INT. RESERVED
$0800
$0000
13K INTERNAL
RAM
7K INTERNAL
RAM
2K INTERNAL
RAM
$0000
$0000
1K I-CACHE ENABLED
Figure 3-10 Memory Maps for MSW=(X,X), CE=1, MS=0, SC=1
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Data and Program Memory Maps
PROGRAM
X DATA
Y DATA
$FFFF
$FFFF
$FF80
$FFFF
$FFB0
INTERNAL I/O
(128 words)
EXTERNAL I/O
(80 words)
INTERNAL I/O
(48words)
$FF80
EXTERNAL
EXTERNAL
EXTERNAL
$C000
$6000
32K INTERNAL
ROM
8K INTERNAL
ROM
$4000
$2000
$4000
$1400
INT. RESERVED
INT. RESERVED
$2800
$0000
8K INTERNAL
RAM
5K INTERNAL
RAM
10K INTERNAL
RAM
$0000
$0000
Figure 3-11 Memory Maps for MSW=(0,0), CE=0, MS=1, SC=1
PROGRAM
X DATA
Y DATA
$FFFF
$FFFF
$FF80
$FFFF
$FFB0
INTERNAL I/O
(128 words)
EXTERNAL I/O
(80 words)
INTERNAL I/O
(48 words)
$FF80
EXTERNAL
EXTERNAL
EXTERNAL
$C000
$6000
32K INTERNAL
ROM
8K INTERNAL
ROM
$4000
$2000
$4000
$1C00
INT. RESERVED
INT. RESERVED
$2800
$2400
1K RAM
INT. RESERVED
7K INTERNAL
RAM
$1C00
8K INTERNAL
RAM
7K INTERNAL
RAM
$0000
$0000
$0000
Figure 3-12 Memory Maps for MSW=(0,1), CE=0, MS=1, SC=1
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Data and Program Memory Maps
PROGRAM
X DATA
Y DATA
$FFFF
$FFFF
$FF80
$FFFF
INTERNAL I/O
(128 words)
EXTERNAL I/O
(80 words)
$FFB0
INTERNAL I/O
(48 words)
$FF80
EXTERNAL
EXTERNAL
EXTERNAL
$C000
$6000
32K INTERNAL
ROM
8K INTERNAL
ROM
$4000
$2C00
$4000
$1C00
INT. RESERVED
INT. RESERVED
$2800
$2400
$1000
$0000
1K RAM
INT. RESERVED
11K INTERNAL
RAM
7K INTERNAL
RAM
4K INTERNAL
RAM
$0000
$0000
Figure 3-13 Memory Maps for MSW=(1,0), CE=0, MS=1, SC=1
PROGRAM
X DATA
Y DATA
$FFFF
$FFFF
$FF80
$FFFF
$FFB0
INTERNAL I/O
(128 words)
EXTERNAL I/O
(80 words)
INTERNAL I/O
(48 words)
$FF80
EXTERNAL
EXTERNAL
EXTERNAL
$C000
$6000
32K INTERNAL
ROM
8K INTERNAL
ROM
$4000
$2000
$4000
$1400
INT. RESERVED
INT. RESERVED
$2400
$0000
8K INTERNAL
RAM
5K INTERNAL
RAM
9K INTERNAL
RAM
$0000
$0000
1K I-CACHE ENABLED
Figure 3-14 Memory Maps for MSW=(0,0), CE=1, MS=1, SC=1
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Data and Program Memory Maps
PROGRAM
X DATA
Y DATA
$FFFF
$FFFF
$FF80
$FFFF
$FFB0
INTERNAL I/O
(128 words)
EXTERNAL I/O
(80 words)
INTERNAL I/O
(48 words)
$FF80
EXTERNAL
EXTERNAL
EXTERNAL
$C000
$6000
32K INTERNAL
ROM
8K INTERNAL
ROM
$4000
$2000
$4000
$1C00
INT. RESERVED
INT. RESERVED
$2400
$1C00
INT. RESERVED
7K INTERNAL
RAM
8K INTERNAL
RAM
7K INTERNAL
RAM
$0000
$0000
$0000
1K I-CACHE ENABLED
Figure 3-15 Memory Maps for MSW=(0,1), CE=1, MS=1, SC=1
PROGRAM
X DATA
Y DATA
$FFFF
$FFFF
$FF80
$FFFF
$FFB0
INTERNAL I/O
(128 words)
EXTERNAL I/O
(80 words)
INTERNAL I/O
(48 words)
$FF80
EXTERNAL
EXTERNAL
EXTERNAL
$C000
$6000
32K INTERNAL
ROM
8K INTERNAL
ROM
$4000
$2C00
$4000
$1C00
INT. RESERVED
INT. RESERVED
$2400
$1000
$0000
INT. RESERVED
4K INTERNAL
RAM
11K INTERNAL
RAM
7K INTERNAL
RAM
$0000
$0000
1K I-CACHE ENABLED
Figure 3-16 Memory Maps for MSW=(1,0), CE=1, MS=1, SC=1
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Data and Program Memory Maps
3.1.1
Reserved Memory Spaces
The reserved memory spaces should not be accessed by the user. They are reserved for future expansion.
3.1.2
Program ROM Area Reserved for Freescale Use
The last 128 words ($FFAF80-$FFAFFF) of the Program ROM are reserved for Freescale use. This
memory area is reserved for use as expansion area for the bootstrap ROM as well as for testing purposes.
Customer code should not use this area. The contents of this Program ROM segment is defined by the
3.1.3
Bootstrap ROM
The 192-word Bootstrap ROM occupies locations $FF0000-$FF00BF. The bootstrap ROM is
factory-programmed to perform the bootstrap operation following hardware reset. The contents of the
Bootstrap ROM are defined by the Bootstrap ROM source code in Appendix A, "Bootstrap ROM
3.1.4
Dynamic Memory Configuration Switching
The internal memory configuration is altered by re-mapping RAM modules from Y and X data memory
into program memory space and vice-versa. The contents of the switched RAM modules are preserved.
The memory can be dynamically switched from one configuration to another by changing the MS, MSW0
or MSW1 bits in OMR. The address ranges that are directly affected by the switch operation are specified
in Table 3-2. The memory switch can be accomplished provided that the affected address ranges are not
being accessed during the instruction cycle in which the switch operation takes place. Accordingly, the
following condition must be observed for trouble-free dynamic switching:
NOTE
No accesses (including instruction fetches) to or from the affected address
ranges in program and data memories are allowed during the switch cycle.
NOTE
The switch cycle actually occurs 3 instruction cycles after the instruction
that modifies the MS, MSW0 or MSW1 bits.
Any sequence that complies with the switch condition is valid. For example, if the program flow executes
in the address range that is not affected by the switch, the switch condition can be met very easily. In this
case a switch can be accomplished by just changing the MS, MSW0 or MSW1 bits in OMR in the regular
program flow, assuming no accesses to the affected address ranges of the data memory occur up to 3
instructions after the instruction that changes the OMR bit. Special care should be taken in relation to the
interrupt vector routines since an interrupt could cause the DSP to fetch instructions out of sequence and
might violate the switch condition.
Special attention should be given when running a memory switch routine using the OnCE™ port. Running
the switch routine in Trace mode, for example, can cause the switch to complete after the MS bit change
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Internal I/O Memory Map
while the DSP is in Debug mode. As a result, subsequent instructions might be fetched according to the
new memory configuration (after the switch), and thus might execute improperly.
3.1.5
External Memory Support
The DSP56366 does not support the SSRAM memory type. It does support SRAM and DRAM as
indicated in the DSP56300 24-Bit Digital Signal Processor Family Manual, Freescale publication
DSP56300FM. Also, care should be taken when accessing external memory to ensure that the necessary
address lines are available. For example, when using glueless SRAM interfacing, it is possible to directly
18
address 3 × 2 memory locations (768k) when using the 18 address lines and the three programmable
address attribute lines.
3.2
Internal I/O Memory Map
The DSP56366 on-chip peripheral modules have their register files programmed to the addresses in the
internal X-I/O memory range (the top 128 locations of the X data memory space) and internal Y-I/O
Table 3-4 Internal I/O Memory Map
Peripheral
Address
Register Name
INTERRUPT PRIORITY REGISTER CORE (IPR-C)
INTERRUPT PRIORITY REGISTER PERIPHERAL (IPR-P)
PLL CONTROL REGISTER (PCTL)
IPR
X:$FFFFFF
X:$FFFFFE
X:$FFFFFD
X:$FFFFFC
X:$FFFFFB
X:$FFFFFA
X:$FFFFF9
X:$FFFFF8
X:$FFFFF7
X:$FFFFF6
X:$FFFFF5
X:$FFFFF4
X:$FFFFF3
X:$FFFFF2
X:$FFFFF1
X:$FFFFF0
X:$FFFFEF
X:$FFFFEE
X:$FFFFED
X:$FFFFEC
PLL
ONCE
BIU
ONCE GDB REGISTER (OGDB)
BUS CONTROL REGISTER (BCR)
DRAM CONTROL REGISTER (DCR)
ADDRESS ATTRIBUTE REGISTER 0 (AAR0)
ADDRESS ATTRIBUTE REGISTER 1 (AAR1)
ADDRESS ATTRIBUTE REGISTER 2 (AAR2)
ADDRESS ATTRIBUTE REGISTER 3 (AAR3) [pin not available]
ID REGISTER (IDR)
DMA
DMA STATUS REGISTER (DSTR)
DMA OFFSET REGISTER 0 (DOR0)
DMA OFFSET REGISTER 1 (DOR1)
DMA OFFSET REGISTER 2 (DOR2)
DMA OFFSET REGISTER 3 (DOR3)
DMA0
DMA SOURCE ADDRESS REGISTER (DSR0)
DMA DESTINATION ADDRESS REGISTER (DDR0)
DMA COUNTER (DCO0)
DMA CONTROL REGISTER (DCR0)
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Internal I/O Memory Map
Table 3-4 Internal I/O Memory Map (continued)
Peripheral
Address
Register Name
DMA SOURCE ADDRESS REGISTER (DSR1)
DMA DESTINATION ADDRESS REGISTER (DDR1)
DMA COUNTER (DCO1)
DMA1
X:$FFFFEB
X:$FFFFEA
X:$FFFFE9
X:$FFFFE8
X:$FFFFE7
X:$FFFFE6
X:$FFFFE5
X:$FFFFE4
X:$FFFFE3
X:$FFFFE2
X:$FFFFE1
X:$FFFFE0
X:$FFFFDF
X:$FFFFDE
X:$FFFFDD
X:$FFFFDC
X:$FFFFDB
X:$FFFFDA
X:$FFFFD9
X:$FFFFD8
X:$FFFFD7
X:$FFFFD6
X:$FFFFD5
X:$FFFFD4
X:$FFFFD3
X:$FFFFD2
X:$FFFFD1
X:$FFFFD0
X:$FFFFCF
X:$FFFFCE
X:$FFFFCD
X:$FFFFCC
X:$FFFFCB
X:$FFFFCA
X:$FFFFC9
X:$FFFFC8
DMA CONTROL REGISTER (DCR1)
DMA SOURCE ADDRESS REGISTER (DSR2)
DMA DESTINATION ADDRESS REGISTER (DDR2)
DMA COUNTER (DCO2)
DMA2
DMA3
DMA4
DMA5
DMA CONTROL REGISTER (DCR2)
DMA SOURCE ADDRESS REGISTER (DSR3)
DMA DESTINATION ADDRESS REGISTER (DDR3)
DMA COUNTER (DCO3)
DMA CONTROL REGISTER (DCR3)
DMA SOURCE ADDRESS REGISTER (DSR4)
DMA DESTINATION ADDRESS REGISTER (DDR4)
DMA COUNTER (DCO4)
DMA CONTROL REGISTER (DCR4)
DMA SOURCE ADDRESS REGISTER (DSR5)
DMA DESTINATION ADDRESS REGISTER (DDR5)
DMA COUNTER (DCO5)
DMA CONTROL REGISTER (DCR5)
PORT D CONTROL REGISTER (PCRD)
PORT D DIRECTION REGISTER (PRRD)
PORT D DATA REGISTER (PDRD)
DAX STATUS REGISTER (XSTR)
DAX AUDIO DATA REGISTER B (XADRB)
DAX AUDIO DATA REGISTER A (XADRA)
DAX NON-AUDIO DATA REGISTER (XNADR)
DAX CONTROL REGISTER (XCTR)
Reserved
PORT D
DAX
Reserved
Reserved
Reserved
Reserved
Reserved
PORT B
HOST PORT GPIO DATA REGISTER (HDR)
HOST PORT GPIO DIRECTION REGISTER (HDDR)
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Internal I/O Memory Map
Table 3-4 Internal I/O Memory Map (continued)
Address Register Name
HOST TRANSMIT REGISTER (HOTX)
Peripheral
HDI08
X:$FFFFC7
X:$FFFFC6
X:$FFFFC5
X:$FFFFC4
X:$FFFFC3
X:$FFFFC2
X:$FFFFC1
X:$FFFFC0
X:$FFFFBF
X:$FFFFBE
X:$FFFFBD
HOST RECEIVE REGISTER (HORX)
HOST BASE ADDRESS REGISTER (HBAR)
HOST PORT CONTROL REGISTER (HPCR)
HOST STATUS REGISTER (HSR)
HOST CONTROL REGISTER (HCR)
Reserved
Reserved
PORT C
PORT C CONTROL REGISTER (PCRC)
PORT C DIRECTION REGISTER (PRRC)
PORT C GPIO DATA REGISTER (PDRC)
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Internal I/O Memory Map
Table 3-4 Internal I/O Memory Map (continued)
Peripheral
Address
Register Name
ESAI
X:$FFFFBC
X:$FFFFBB
X:$FFFFBA
X:$FFFFB9
X:$FFFFB8
X:$FFFFB7
X:$FFFFB6
X:$FFFFB5
X:$FFFFB4
X:$FFFFB3
X:$FFFFB2
X:$FFFFB1
X:$FFFFB0
X:$FFFFAF
X:$FFFFAE
X:$FFFFAD
X:$FFFFAC
X:$FFFFAB
X:$FFFFAA
X:$FFFFA9
X:$FFFFA8
X:$FFFFA7
X:$FFFFA6
X:$FFFFA5
X:$FFFFA4
X:$FFFFA3
X:$FFFFA2
X:$FFFFA1
X:$FFFFA0
X:$FFFF9F
X:$FFFF9E
X:$FFFF9D
X:$FFFF9C
X:$FFFF9B
X:$FFFF9A
X:$FFFF99
X:$FFFF98
ESAI RECEIVE SLOT MASK REGISTER B (RSMB)
ESAI RECEIVE SLOT MASK REGISTER A (RSMA)
ESAI TRANSMIT SLOT MASK REGISTER B (TSMB)
ESAI TRANSMIT SLOT MASK REGISTER A (TSMA)
ESAI RECEIVE CLOCK CONTROL REGISTER (RCCR)
ESAI RECEIVE CONTROL REGISTER (RCR)
ESAI TRANSMIT CLOCK CONTROL REGISTER (TCCR)
ESAI TRANSMIT CONTROL REGISTER (TCR)
ESAI COMMON CONTROL REGISTER (SAICR)
ESAI STATUS REGISTER (SAISR)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
ESAI RECEIVE DATA REGISTER 3 (RX3)
ESAI RECEIVE DATA REGISTER 2 (RX2)
ESAI RECEIVE DATA REGISTER 1 (RX1)
ESAI RECEIVE DATA REGISTER 0 (RX0)
Reserved
ESAI TIME SLOT REGISTER (TSR)
ESAI TRANSMIT DATA REGISTER 5 (TX5)
ESAI TRANSMIT DATA REGISTER 4 (TX4)
ESAI TRANSMIT DATA REGISTER 3 (TX3)
ESAI TRANSMIT DATA REGISTER 2 (TX2)
ESAI TRANSMIT DATA REGISTER 1 (TX1)
ESAI TRANSMIT DATA REGISTER 0 (TX0)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
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Internal I/O Memory Map
Peripheral
Table 3-4 Internal I/O Memory Map (continued)
Address Register Name
X:$FFFF97
X:$FFFF96
X:$FFFF95
X:$FFFF94
X:$FFFF93
X:$FFFF92
X:$FFFF91
X:$FFFF90
X:$FFFF8F
X:$FFFF8E
X:$FFFF8D
X:$FFFF8C
X:$FFFF8B
X:$FFFF8A
X:$FFFF89
X:$FFFF88
X:$FFFF87
X:$FFFF86
X:$FFFF85
X:$FFFF84
X:$FFFF83
X:$FFFF82
X:$FFFF81
X:$FFFF80
Y:$FFFFAF
Y:$FFFFAE
Y:$FFFFAD
Reserved
Reserved
Reserved
SHI
SHI RECEIVE FIFO (HRX)
SHI TRANSMIT REGISTER (HTX)
2
SHI I C SLAVE ADDRESS REGISTER (HSAR)
SHI CONTROL/STATUS REGISTER (HCSR)
SHI CLOCK CONTROL REGISTER (HCKR)
TIMER 0 CONTROL/STATUS REGISTER (TCSR0)
TIMER 0 LOAD REGISTER (TLR0)
TIMER 0 COMPARE REGISTER (TCPR0)
TIMER 0 COUNT REGISTER (TCR0)
TIMER 1 CONTROL/STATUS REGISTER (TCSR1)
TIMER 1 LOAD REGISTER (TLR1)
TIMER 1 COMPARE REGISTER (TCPR1)
TIMER 1 COUNT REGISTER (TCR1)
TIMER 2 CONTROL/STATUS REGISTER (TCSR2)
TIMER 2 LOAD REGISTER (TLR2)
TIMER 2 COMPARE REGISTER (TCPR2)
TIMER 2 COUNT REGISTER (TCR2)
TIMER PRESCALER LOAD REGISTER (TPLR)
TIMER PRESCALER COUNT REGISTER (TPCR)
Reserved
TRIPLE TIMER
Reserved
ESAI MUX PIN
CONTROL
MUX PIN CONTROL REGISTER (EMUXR)
Reserved
Reserved
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Internal I/O Memory Map
Table 3-4 Internal I/O Memory Map (continued)
Address Register Name
Peripheral
Y:$FFFFAC
Y:$FFFFAB
Y:$FFFFAA
Y:$FFFFA9
Y:$FFFFA8
Y:$FFFFA7
Y:$FFFFA6
Y:$FFFFA5
Y:$FFFFA4
Y:$FFFFA3
Y:$FFFFA2
Y:$FFFFA1
Y:$FFFFA0
Y:$FFFF9F
Y:$FFFF9E
Y:$FFFF9D
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PORT E
PORT E CONTROL REGISTER (PCRE)
PORT E DIRECTION REGISTER(PPRE)
PORT E GPIO DATA REGISTER(PDRE)
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Internal I/O Memory Map
Table 3-4 Internal I/O Memory Map (continued)
Address
Peripheral
Register Name
ESAI_1 RECEIVE SLOT MASK REGISTER B (RSMB_1)
ESAI_1 RECEIVE SLOT MASK REGISTER A (RSMA_1)
ESAI_1 TRANSMIT SLOT MASK REGISTER B (TSMB_1)
ESAI_1 TRANSMIT SLOT MASK REGISTER A (TSMA_1)
ESAI_1 RECEIVE CLOCK CONTROL REGISTER (RCCR_)
ESAI_1 RECEIVE CONTROL REGISTER (RCR_1)
ESAI_1 TRANSMIT CLOCK CONTROL REGISTER (TCCR_1)
ESAI_1 TRANSMIT CONTROL REGISTER (TCR_1)
ESAI_1 COMMON CONTROL REGISTER (SAICR_1)
ESAI_1 STATUS REGISTER (SAISR_1)
Reserved
ESAI_1
Y:$FFFF9C
Y:$FFFF9B
Y:$FFFF9A
Y:$FFFF99
Y:$FFFF98
Y:$FFFF97
Y:$FFFF96
Y:$FFFF95
Y:$FFFF94
Y:$FFFF93
Y:$FFFF92
Y:$FFFF91
Y:$FFFF90
Y:$FFFF8F
Y:$FFFF8E
Y:$FFFF8D
Y:$FFFF8C
Y:$FFFF8B
Y:$FFFF8A
Y:$FFFF89
Y:$FFFF88
Y:$FFFF87
Y:$FFFF86
Y:$FFFF85
Y:$FFFF84
Y:$FFFF83
Y:$FFFF82
Y:$FFFF81
Y:$FFFF80
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
ESAI_1 RECEIVE DATA REGISTER 3 (RX3_1)
ESAI_1 RECEIVE DATA REGISTER 2 (RX2_1)
ESAI_1 RECEIVE DATA REGISTER 1 (RX1_1)
ESAI_1 RECEIVE DATA REGISTER 0 (RX0_1)
Reserved
ESAI_1 TIME SLOT REGISTER (TSR_1)
ESAI_1 TRANSMIT DATA REGISTER 5 (TX5_1)
ESAI_1 TRANSMIT DATA REGISTER 4 (TX4_1)
ESAI_1 TRANSMIT DATA REGISTER 3 (TX3_1)
ESAI_1 TRANSMIT DATA REGISTER 2 (TX2_1)
ESAI_1 TRANSMIT DATA REGISTER 1 (TX1_1)
ESAI_1 TRANSMIT DATA REGISTER 0 (TX0_1)
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4 Core Configuration
4.1
Introduction
This chapter contains DSP56300 core configuration information details specific to the DSP56366. These
include the following:
•
•
•
•
•
•
•
•
Operating modes
Bootstrap program
Interrupt sources and priorities
DMA request sources
OMR
PLL control register
AA control registers
JTAG BSR
For more information on specific registers or modules in the DSP56300 core, refer to the DSP56300 Family
Manual (DSP56300FM).
4.2
Operating Mode Register (OMR)
Refer to the DSP56300 Family Manual, Freescale publication DSP56300FM for a description of the OMR
bits.
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Operating Mode Register (OMR)
Table 4-1 Operating Mode Register (OMR)
SCS
EOM
18 17 16 15 14 13 12 11 10
PEN MSW 1 : 0 SEN WRP EOV EUN XYS ATE APD ABE BRT TAS BE
COM
7
23 22 21 20
19
9
8
6
5
4
3
2
1
0
CDP1:0 MS SD
EBD MD MC MB MA
PEN
- Patch Enable
ATE
APD
ABE
BRT
TAS
BE
- Address Tracing Enable
MS
SD
- Master memory Switch Mode
- Stop Delay
MSW1
MSW0
SEN
- Memory switch mode 1
- Memory switch mode 0
- Stack Extension Enable
- Extended Stack Wrap Flag
- Extended Stack Overflow Flag
- Address Priority Disable
- Asyn. Bus Arbitration Enable
- Bus Release Timing
- TA Synchronize Select
- Burst Mode Enable
EBD
MD
MC
MB
MA
- External Bus Disable
- Operating Mode D
- Operating Mode C
- Operating Mode B
- Operating Mode A
WRP
EOV
EUN
- Extended Stack Underflow Flag CDP1
- Stack Extension Space Select CDP0
- Core-Dma Priority 1
- Core-Dma Priority 0
XYS
- Reserved bit. Read as zero, should be written with zero for future compatibility
4.2.1
Asynchronous Bus Arbitration Enable (ABE) - Bit 13
The asynchronous bus arbitration mode is activated by setting the ABE bit in the OMR register. Hardware
reset clears the ABE bit.
4.2.2
Address Attribute Priority Disable (APD) - Bit 14
The Address Attribute Priority Disable (APD) bit is used to turn off the address attribute priority
mechanism. When this bit is set, more than one address attribute pin AA/RAS(2:0) may be simultaneously
asserted according to its AAR settings. The APD bit is cleared by hardware reset.
4.2.3
Address Tracing Enable (ATE) - Bit 15
The Address Tracing Enable (ATE) bit is used to turn on Address Tracing (AT) Mode. When the AT Mode
is enabled, the DSP56300 Core reflects the addresses of internal fetches and program space moves
(MOVEM) to the Address Bus (A0-A17), if the Address Bus is not needed by the DSP56300 Core for
external accesses. The ATE bit is cleared on hardware reset.
4.2.4
Patch Enable (PEN) - Bit 23
The Patch Enable function is used for patching Program ROM locations. i.e. to replace during program
execution, the contents of the Program ROM. This is done by using the Instruction Cache to supply the
instruction word instead of the Program ROM.
The Patch Enable function is activated by setting bit 23 (PEN) in the OMR Register. The PEN bit is cleared
by hardware reset.
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
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Operating Mode Register (OMR)
The Instruction Cache should be initialized with the new instructions according to the following
procedure:
These steps should be executed from external memory or by download via host interface:
1. Set Cache Enable = 1
2. Set Patch Enable = 1
3. Initialize TAGs to different values by unlock eight different external sectors
4. Lock the PATCH sector(s)
5. Move new code to locked sector(s), to the addresses that should be replaced
6. Start regular PROM program
;****************************************************************************
; PATCH initialization example
;****************************************************************************
page
132,55,0,0,0
nolist
INCLUDE "ioequ.asm"
INCLUDE "intequ.asm"
list
START
PATCH_OFSET
M_PAE
M_PROMS
M_PROME
equ
equ
equ
equ
equ
$100
128
23
$ffafec
$ffafff
; main program starting address
; patch offset
; Patch Enable
; ROM area Start
; ROM area End
org
P:START
move
#M_PROMS,r0
bset
bset
move
move
move
#M_CE,sr
#M_PAE,omr
#$800000,r1
#128,n1
; CacheEnable = 1
; PatchEnable = 1
; any external address
; 128 for 1K ICACHE, sector size
#(M_PROMS+PATCH_OFSET),r2
dup
8
punlock (r1)+n1
; initialize TAGs to different
; values
endm
plock
move
(r2)
; lock patch's sector
; (start/mid/end)
#PATCH_DATA_START,r1
;
; replace ROM code by PATCH
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Operating Modes
;
do
#(PATCH_DATA_END-PATCH_DATA_START+1),PATCH_LOOP
movem
movem
nop
p:(r1)+,x0
x0,p:(r2)+
; Do-loop restriction
PATCH_LOOP
ENDTEST
jsr
#M_PROMS
ENDTEST
; start ROM code execution
jmp
nop
nop
nop
nop
;
; patch data
;
PATCH_DATA_START
move
move
move
#5,m0
#6,m1
#7,m2
PATCH_DATA_END
;****************************************************************************
4.3
Operating Modes
MODB, MODC and MODD pins during reset. Each operating mode is briefly described below. Except for
modes 0 and 8, the operation of all other modes is defined by the Bootstrap ROM source code in Appendix
Table 4-2 DSP56366 Operating Modes
MOD
D
MOD
C
MOD
B
MOD
A
Reset
Vector
Mode
Description
0
1
2
3
4
5
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
$C00000 Expanded mode
$FF0000 Bootstrap from byte-wide memory
$FF0000 Jump to PROM starting address
$FF0000 Reserved
$FF0000 Reserved
$FF0000 Bootstrap from SHI (slave SPI mode)
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Operating Modes
Table 4-2 DSP56366 Operating Modes (continued)
MOD
D
MOD
C
MOD
B
MOD
A
Reset
Vector
Mode
Description
2
6
0
1
1
0
$FF0000 Bootstrap from SHI (slave I C mode) (HCKFR=1, 100ns filter
enabled)
2
7
8
0
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
$FF0000 Bootstrap from SHI (slave I C mode)(HCKR=0)
$008000 Expanded mode
9
$FF0000 Reserved for Burn-in testing
$FF0000 Reserved
A
B
C
D
E
F
$FF0000 Reserved
$FF0000 HDI08 Bootstrap in ISA Mode
$FF0000 HDI08 Bootstrap in HC11 non-multiplexed mode
$FF0000 HDI08 Bootstrap in 8051 multiplexed bus mode
$FF0000 HDI08 Bootstrap in 68302 bus mode
Table 4-3 DSP56366 Mode Descriptions
Mode 0 The DSP starts fetching instructions beginning at address $C00000. Memory accesses are performed using
SRAM memory access type with 31 wait states and no address attributes selected. Address $C00000 is reflected
as address $00000 on Port A pins A0-A17.
Mode 1 The bootstrap program loads instructions through Port A from external byte-wide memory, connected to the least
significant byte of the data bus (bits 7-0), and starting at address P:$D00000. The bootstrap code expects to read
3 bytes specifying the number of program words, 3 bytes specifying the address to start loading the program
words and then 3 bytes for each program word to be loaded. The number of words, the starting address and the
program words are read least significant byte first followed by the mid and then by the most significant byte. The
program words will be stored in contiguous PRAM memory locations starting at the specified starting address.
After reading the program words, program execution starts from the same address where loading started.The
SRAM memory access type is selected by the values in Address Attribute Register 1 (AAR1), with 31 wait states
for each memory access. Address $D00000 is reflected as address $00000 on Port A pins A0-A17.
Mode 2 The DSP starts fetching instructions from the starting address of the on-chip Program ROM.
Mode 3 Reserved.
Mode 4 Reserved.
Mode 5 In this mode, the internal PRAM is loaded from the Serial Host Interface (SHI). The SHI operates in the SPI slave
mode, with 24-bit word width.The bootstrap code expects to read a 24-bit word specifying the number of program
words, a 24-bit word specifying the address to start loading the program words and then a 24-bit word for each
program word to be loaded. The program words will be stored in contiguous PRAM memory locations starting at
the specified starting address. After reading the program words, program execution starts from the same address
where loading started.
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Interrupt Priority Registers
Table 4-3 DSP56366 Mode Descriptions
2
Mode 6 Same as Mode 5 except SHI interface operates in the I C slave mode with HCKFR set to 1 and the 100ns filter
enabled.
2
Mode 7 Same as Mode 5 except SHI interface operates in the I C slave mode with HCKFR set to 0.
Mode 8 The DSP starts fetching instructions beginning at address $008000. Memory accesses are performed using
SRAM memory access type with 31 wait states and no address attributes selected.
Mode 9 Reserved. Used for Burn-In testing.
Mode A Reserved.
Mode B Reserved.
Mode C Instructions are loaded through the HDI08, which is configured to interface with an ISA bus. The HOST ISA
bootstrap code expects to read a 24-bit word specifying the number of program words, a 24-bit word specifying
the address to start loading the program words and then a 24-bit word for each program word to be loaded. The
program words will be stored in contiguous PRAM memory locations starting at the specified starting address.
After reading the program words, program execution starts from the same address where loading started. The
Host Interface bootstrap load program may be stopped by setting the Host Flag 0 (HF0). This will start execution
of the loaded program from the specified starting address.
Mode D As in Mode C, but HDI08 is set for interfacing to Freescale HC11 microcontroller in non-multiplexed mode
Mode E As in Mode C, but HDI08 is set for interfacing to Intel 8051 multiplexed bus
Mode F As in Mode C, but HDI08 is set for interfacing to Freescale 68302 bus.
4.4
Interrupt Priority Registers
There are two interrupt priority registers in the DSP56366:
1. IPR-C is dedicated for DSP56300 Core interrupt sources.
2. IPR-P is dedicated for DSP56366 peripheral interrupt sources.
The interrupt priority registers are shown in Figure 4-1 and Figure 4-2. The Interrupt Priority Level bits
are defined in Table 4-4. The interrupt vectors are shown in Table 4-6 and the interrupt priorities are shown
Table 4-4 Interrupt Priority Level Bits
IPL bits
Interrupt
Priority
Level
Interrupts
Enabled
xxL1
xxL0
0
0
1
1
0
1
0
1
No
Yes
Yes
Yes
—
0
1
2
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Interrupt Priority Registers
11
10
9
7
6
5
4
3
2
1
0
8
ESL10 TAL1
TAL0 DAL1 DAL0 HDL1 HDL0 SHL1 SHL0 ESL1 ESL0
ESL11
ESAI IPL
SHI IPL
HDI08 IPL
DAX IPL
TRIPLE TIMER IPL
ESAI_1 IPL
22
23
21
20
19
18
17
16
15
14
13
12
reserved
Reserved bit. Read as zero, should be written with zero for future compatibility.
Figure 4-1 Interrupt Priority Register P
11
10
9
7
6
5
4
3
2
1
0
8
IDL2
IDL1 IDL0 ICL2 ICL1 ICL0 IBL2 IBL1 IBL0 IAL2 IAL1 IAL0
IRQA IPL
IRQA mode
IRQB IPL
IRQB mode
IRQC IPL
IRQC mode
IRQD IPL
IRQD mode
22
23
21
20
19
18
17
16
15
14
13
12
D5L1 D5L0 D4L1 D4L0 D3L1 D3L0 D2L1 D2L0 D1L1 D1L0 D0L1 D0L0
DMA0 IPL
DMA1 IPL
DMA2 IPL
DMA3 IPL
DMA4 IPL
DMA5 IPL
Figure 4-2 Interrupt Priority Register C
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Interrupt Priority Registers
Table 4-5 Interrupt Sources Priorities Within an IPL
Interrupt Source
Priority
Level 3 (Nonmaskable)
Highest
Hardware RESET
Stack Error
Illegal Instruction
Debug Request Interrupt
Trap
Lowest
Non-Maskable Interrupt
Levels 0, 1, 2 (Maskable)
Highest
IRQA (External Interrupt)
IRQB (External Interrupt)
IRQC (External Interrupt)
IRQD (External Interrupt)
DMA Channel 0 Interrupt
DMA Channel 1 Interrupt
DMA Channel 2 Interrupt
DMA Channel 3 Interrupt
DMA Channel 4 Interrupt
DMA Channel 5 Interrupt
ESAI Receive Data with Exception Status
ESAI Receive Even Data
ESAI Receive Data
ESAI Receive Last Slot
ESAI Transmit Data with Exception Status
ESAI Transmit Last Slot
ESAI Transmit Even Data
ESAI Transmit Data
SHI Bus Error
SHI Receive Overrun Error
SHI Transmit Underrun Error
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Interrupt Priority Registers
Table 4-5 Interrupt Sources Priorities Within an IPL (continued)
Priority Interrupt Source
SHI Receive FIFO Full
SHI Transmit Data
SHI Receive FIFO Not Empty
HOST Command Interrupt
HOST Receive Data Interrupt
HOST Transmit Data Interrupt
DAX Transmit Underrun Error
DAX Block Transferred
DAX Transmit Register Empty
TIMER0 Overflow Interrupt
TIMER0 Compare Interrupt
TIMER1 Overflow Interrupt
TIMER1 Compare Interrupt
TIMER2 Overflow Interrupt
TIMER2 Compare Interrupt
ESAI_1 Receive Data with Exception Status
ESAI_1 Receive Even Data
ESAI_1 Receive Data
ESAI_1 Receive Last Slot
ESAI_1 Transmit Data with Exception Status
ESAI_1 Transmit Last Slot
ESAI_1 Transmit Even Data
ESAI_1 Transmit Data
Lowest
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Interrupt Priority Registers
Table 4-6 DSP56366 Interrupt Vectors
Interrupt Priority
Interrupt
Starting Address
Interrupt Source
Level Range
VBA:$00
VBA:$02
VBA:$04
VBA:$06
VBA:$08
VBA:$0A
VBA:$0C
VBA:$0E
VBA:$10
VBA:$12
VBA:$14
VBA:$16
VBA:$18
VBA:$1A
VBA:$1C
VBA:$1E
VBA:$20
VBA:$22
VBA:$24
VBA:$26
VBA:$28
VBA:$2A
VBA:$2C
VBA:$2E
VBA:$30
VBA:$32
VBA:$34
VBA:$36
VBA:$38
VBA:$3A
VBA:$3C
VBA:$3E
VBA:$40
VBA:$42
3
Hardware RESET
Stack Error
3
3
Illegal Instruction
Debug Request Interrupt
Trap
3
3
3
Non-Maskable Interrupt (NMI)
Reserved For Future Level-3 Interrupt Source
Reserved For Future Level-3 Interrupt Source
IRQA
3
3
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
IRQB
IRQC
IRQD
DMA Channel 0
DMA Channel 1
DMA Channel 2
DMA Channel 3
DMA Channel 4
DMA Channel 5
Reserved
Reserved
DAX Underrun Error
DAX Block Transferred
Reserved
DAX Audio Data Empty
ESAI Receive Data
ESAI Receive Even Data
ESAI Receive Data With Exception Status
ESAI Receive Last Slot
ESAI Transmit Data
ESAI Transmit Even Data
ESAI Transmit Data with Exception Status
ESAI Transmit Last Slot
SHI Transmit Data
SHI Transmit Underrun Error
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Interrupt Priority Registers
Table 4-6 DSP56366 Interrupt Vectors (continued)
Interrupt
Starting Address
Interrupt Priority
Interrupt Source
Level Range
VBA:$44
VBA:$46
VBA:$48
VBA:$4A
VBA:$4C
VBA:$4E
VBA:$50
VBA:$52
VBA:$54
VBA:$56
VBA:$58
VBA:$5A
VBA:$5C
VBA:$5E
VBA:$60
VBA:$62
VBA:$64
VBA:$66
VBA:$68
VBA:$6A
VBA:$6C
VBA:$6E
VBA:$70
VBA:$72
VBA:$74
VBA:$76
VBA:$78
VBA:$7A
VBA:$7C
VBA:$7E
VBA:$80
:
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
:
SHI Receive FIFO Not Empty
Reserved
SHI Receive FIFO Full
SHI Receive Overrun Error
SHI Bus Error
Reserved
Reserved
Reserved
TIMER0 Compare
TIMER0 Overflow
TIMER1 Compare
TIMER1 Overflow
TIMER2 Compare
TIMER2 Overflow
Host Receive Data Full
Host Transmit Data Empty
Host Command (Default)
Reserved
Reserved
Reserved
Reserved
Reserved
ESAI_1 Receive Data
ESAI_1 Receive Even Data
ESAI_1 Receive Data With Exception Status
ESAI_1 Receive Last Slot
ESAI_1 Transmit Data
ESAI_1 Transmit Even Data
ESAI_1 Transmit Data with Exception Status
ESAI_1 Transmit Last Slot
Reserved
:
VBA:$FE
0 - 2
Reserved
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DMA Request Sources
4.5
DMA Request Sources
The DMA Request Source bits (DRS0-DRS4 bits in the DMA Control/Status registers) encode the source
of DMA requests used to trigger the DMA transfers. The DMA request sources may be the internal
peripherals or external devices requesting service through the IRQA, IRQB, IRQC and IRQD pins. The
Table 4-7 DMA Request Sources
DMA Request Source Bits
Requesting Device
DRS4...DRS0
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111-11111
External (IRQA pin)
External (IRQB pin)
External (IRQC pin)
External (IRQD pin)
Transfer Done from DMA channel 0
Transfer Done from DMA channel 1
Transfer Done from DMA channel 2
Transfer Done from DMA channel 3
Transfer Done from DMA channel 4
Transfer Done from DMA channel 5
DAX Transmit Data
ESAI Receive Data (RDF=1)
ESAI Transmit Data (TDE=1)
SHI HTX Empty
SHI FIFO Not Empty
SHI FIFO Full
HDI08 Receive Data
HDI08 Transmit Data
TIMER0 (TCF=1)
TIMER1 (TCF=1)
TIMER2 (TCF=1)
ESAI_1 Receive Data (RDF=1)
ESAI_1 Transmit Data (TDE=1)
Reserved
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PLL Initialization
4.6
PLL Initialization
4.6.1
PLL Multiplication Factor (MF0-MF11)
The DSP56366 PLL multiplication factor is set to 6 during hardware reset, i.e. the Multiplication Factor
Bits MF0-MF11 in the PLL Control Register (PCTL) are set to $005.
4.6.2
PLL Pre-Divider Factor (PD0-PD3)
The DSP56366 PLL Pre-Divider factor is set to 1 during hardware reset, i.e. the Pre-Divider Factor Bits
PD0-PD3 in the PLL Control Register (PCTL) are set to $0.
4.6.3
Crystal Range Bit (XTLR)
The Crystal Range (XTLR) bit controls the on-chip crystal oscillator transconductance. The on-chip
crystal oscillator is not used on the DSP56366 since no XTAL pin is available. The XTLR bit is set to zero
during hardware reset in the DSP56366.
4.6.4
XTAL Disable Bit (XTLD)
The XTAL Disable Bit (XTLD) is set to 1 (XTAL disabled) during hardware reset in the DSP56366.
4.7
Device Identification (ID) Register
The Device Identification Register (IDR) is a 24 bit read only factory programmed register used to identify
the different DSP56300 core-based family members. This register specifies the derivative number and
revision number. This information may be used in testing or by software. Table 4-8 shows the ID register
configuration.
Table 4-8 Identification Register Configuration
23
16
Reserved
$00
15
12
Revision Number
$0
11
0
Derivative Number
$366
4.8
JTAG Identification (ID) Register
The JTAG Identification (ID) Register is a 32 bit, read only thought JTAG, factory programmed register
used to distinguish the component on a board according to the IEEE 1149.1 standard. Table 4-9 shows the
JTAG ID register configuration.
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JTAG Boundary Scan Register (BSR)
Table 4-9 JTAG Identification Register Configuration
31
28
27
22
21
12
11
1
0
Version
Information
Customer Part
Number
Sequence
Number
Manufacturer
Identity
1
1
0000
000111
0001001111
00000001110
4.9
JTAG Boundary Scan Register (BSR)
The boundary scan register (BSR) in the DSP56366 JTAG implementation contains bits for all device
signal and clock pins and associated control signals. All bidirectional pins have a single register bit in the
boundary scan register for pin data, and are controlled by an associated control bit in the boundary scan
Table 4-10 DSP56366 BSR Bit Definition
Bit
#
BSR Cell
Type
Bit
#
BSR Cell
Type
Pin Name
Pin Type
Pin Name
Pin Type
SDO4_1/SDI1_1
SDO4_1/SDI1_1
IRQA
—
Control
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Control
Data
76 FST_1
77 FST_1
78 SDO5_1/SDI0_1
79 SDO5_1/SDI0_1
80 RES
—
Control
Data
0
1
Input/Output
Input
Input/Output
Control
Data
2
IRQB
Input
Input/Output
3
IRQC
Input
Input
Data
4
IRQD
Input
81 HAD0
—
Control
Data
5
D23
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
—
82 HAD0
Input/Output
—
6
D22
83 HAD1
Control
Data
7
D21
84 HAD1
Input/Output
—
8
D20
85 HAD2
Control
Data
9
D19
86 HAD2
Input/Output
—
10
11
12
13
14
15
16
D18
87 HAD3
Control
Data
D17
88 HAD3
Input/Output
—
D16
89 HAD4
Control
Data
D15
90 HAD4
Input/Output
—
D[23:13]
D14
91 HAD5
Control
Data
Input/Output
92 HAD5
Input/Output
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JTAG Boundary Scan Register (BSR)
Table 4-10 DSP56366 BSR Bit Definition (continued)
Bit
#
BSR Cell
Type
Bit
#
BSR Cell
Type
Pin Name
Pin Type
Pin Name
Pin Type
17 D13
18 D12
19 D11
20 D10
21 D9
22 D8
23 D7
24 D6
25 D5
26 D4
27 D3
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
—
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Control
Data
Data
Data
Data
Data
Data
Control
Data
Data
Data
Data
Data
Data
Data
93 HAD6
—
Control
Data
94 HAD6
Input/Output
95 HAD7
—
Control
Data
96 HAD7
Input/Output
97 HAS/A0
98 HAS/A0
99 HA8/A1
100 HA8/A1
101 HA9/A2
102 HA9/A2
103 HCS/A10
104 HCS/A10
105 TIO0
—
Control
Data
Input/Output
—
Control
Data
Input/Output
—
Control
Data
Input/Output
—
Control
Data
28 D[12:0]
29 D2
Input/Output
Input/Output
Input/Output
Input/Output
Output3
—
Control
Data
30 D1
106 TIO0
Input/Output
31 D0
107 ACI
—
Control
Data
32 A17
33 A16
34 A15
35 A[17:9]
36 A14
37 A13
38 A12
39 A11
40 A10
41 A9
108 ACI
Input/Output
—
Output3
109 ADO
Control
Data
Output3
110 ADO
Input/Output
—
—
111 HREQ/HTRQ
112 HREQ/HTRQ
113 HACK/RRQ
114 HACK/RRQ
115 HRW/RD
116 HRW/RD
117 HDS/WR
118 HDS/WR
Control
Data
Output3
Input/Output
—
Output3
Control
Data
Output3
Input/Output
—
Output3
Control
Data
Output3
Input/Output
—
Output3
Control
Data
42 A8
Output3
Input/Output
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JTAG Boundary Scan Register (BSR)
Table 4-10 DSP56366 BSR Bit Definition (continued)
Bit
#
BSR Cell
Type
Bit
#
BSR Cell
Type
Pin Name
Pin Type
Output3
Pin Name
Pin Type
43 A7
44 A6
Data
Data
119 HSCKR
120 HSCKR
121 HSCKT
122 HSCKT
123 SCKR
—
Control
Data
Output3
—
Input/Output
45 A[8:0]
46 A5
Control
Data
—
Control
Data
Output3
Output3
Output3
Output3
Output3
Output3
Input
Input/Output
47 A4
Data
—
Control
Data
48 A3
Data
124 SCKR
Input/Output
49 A2
Data
125 SCKT
—
Control
Data
50 A1
Data
126 SCKT
Input/Output
51 A0
Data
127 FSR
—
Control
Data
52 BG
Data
128 FSR
Input/Output
53 AA0
54 AA0
55 AA1
56 AA1
57 RD
—
Control
Data
129 FST
—
Control
Data
Output3
—
130 FST
Input/Output
Control
Data
131 SDO5/SDI0
132 SDO5/SDI0
133 SDO4/SDI1
134 SDO4/SDI1
135 SDO3/SDI2
136 SDO3/SDI2
137 SDO2/SDI3
138 SDO2/SDI3
139 SDO1
—
Control
Data
Output3
Output3
Output3
—
Input/Output
Data
—
Control
Data
58 WR
59 BB
Data
Input/Output
—
Control
Data
Control
Data
60 BB
Input/Output
Output2
Input
Input/Output
—
61 BR
Data
Control
Data
62 TA
Data
Input/Output
—
63 PINIT
64 SCKR_1
65 SCKR_1
66 FSR_1
67 FSR_1
68 RD,WR
Input
Data
Control
Data
Control
Data
140 SDO1
Input/Output
—
Input/Output
141 SDO0
Control
Data
Control
Data
142 SDO0
Input/Output
—
Input/Output
—
143 HREQ
Control
Data
Control
144 HREQ
Input/Output
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JTAG Boundary Scan Register (BSR)
Table 4-10 DSP56366 BSR Bit Definition (continued)
Bit
#
BSR Cell
Type
Bit
#
BSR Cell
Type
Pin Name
Pin Type
Input
Pin Name
Pin Type
Input
69 EXTAL
70 SCKT_1
71 SCKT_1
72 CAS
Data
Control
Data
145 SS
Data
Control
Data
—
146 SCK/SCL
147 SCK/SCL
148 MISO/SDA
149 MISO/SDA
150 MOSI/HA0
151 MOSI/HA0
—
Input/Output
—
Input/Output
—
Control
Data
Control
Data
73 CAS
Output3
—
Input/Output
—
74 AA2
Control
Data
Control
Data
75 AA2
Output3
Input/Output
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JTAG Boundary Scan Register (BSR)
NOTES
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5 General Purpose Input/Output
5.1
Introduction
The DSP56362 provides up to 37 bidirectional signals that can be configured as GPIO signals or as
peripheral dedicated signals. No dedicated GPIO signals are provided. All of these signals are GPIO by
default after reset. The techniques for register programming for all GPIO functionality is very similar
between these interfaces. This section describes how signals may be used as GPIO.
5.2
Programming Model
The signals description section of this manual describes the special uses of these signals in detail. There
are five groups of these signals which can be controlled separately or as groups:
•
•
•
•
•
Port B: up to 16 GPIO signals (shared with the HDI08 signals)
Port C: 12 GPIO signals (shared with the ESAI signals)
Port D: two GPIO signals (shared with the DAX signals)
Port E: 10 GPIO signals (shared with the ESAI_1 signals)
Timer: one GPIO signal (shared with the timer/event counter signal)
5.2.1
Port B Signals and Registers
When HDI08 is disabled, all 16 HDI08 signals can be used as GPIO. When HDI08 is enabled, five (HA8,
HA9, HCS, HOREQ, and HACK) of the 16 port B signals, if not used as a HDI08 signal, can be configured
as GPIO signals. The GPIO functionality of port B is controlled by three registers: host port control register
(HPCR), host port GPIO data register (HDR), and host port GPIO direction register (HDDR). These
5.2.2
Port C Signals and Registers
Each of the 12 port C signals not used as an ESAI signal can be configured individually as a GPIO signal.
The GPIO functionality of port C is controlled by three registers: port C control register (PCRC), port C
direction register (PRRC), and port C data register (PDRC). These registers are described in Section 8,
5.2.3
Port D Signals and Registers
Each of the two Port D signals not used as a DAX signal can be configured individually as a GPIO signal.
The GPIO functionality of Port D is controlled by three registers: Port D control register (PCRD), Port D
direction register (PRRD) and Port D data register (PDRD). These registers are described in Section 10,
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Programming Model
5.2.4
Port E Signals and Registers
Port E has 10 signals, shared with the ESAI_1. Six of the ESAI_1 signals have their own pin, so each of
the six signals, if not used as an ESAI_1 signal, can be configured individually as a GPIO signal. The other
four ESAI_1 signals share pins with the ESAI. For these shared pins, if the pin is not being used by the
ESAI, Port C and the ESAI_1, then it may be used as a Port E GPIO signal. The GPIO functionality of port
E is controlled by three registers: port E control register (PCRE), port E direction register (PRRE), and
port E data register (PDRE). These registers are described in Section 9, "Enhanced Serial Audio Interface
5.2.5
Timer/Event Counter Signals
The timer/event counter signal (TIO), when not used as a timer signal can be configured as a GPIO signal.
The signal is controlled by the appropriate timer control status register (TCSR). The register is described
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6 Host Interface (HDI08)
6.1
Introduction
The host interface (HDI08) is a byte-wide, full-duplex, double-buffered, parallel port that can be connected
directly to the data bus of a host processor. The HDI08 supports a variety of buses and provides glueless
connection with a number of industry standard microcomputers, microprocessors, DSPs and DMA
hardware.
The host bus can operate asynchronously to the DSP core clock, therefore the HDI08 registers are divided
into 2 banks. The host register bank is accessible to the external host and the DSP register bank is
accessible to the DSP core.
The HDI08 supports three classes of interfaces:
•
•
•
Host processor/Microcontroller (MCU) connection interface
DMA controller interface
General purpose I/O (GPIO) port
6.2
HDI08 Features
6.2.1
Interface - DSP side
•
Mapping:
— Registers are directly mapped into eight internal X data memory locations
•
•
Data Word:
— 24-bit (native) data words are supported, as are 8-bit and 16-bit words
Transfer Modes:
— DSP to Host
— Host to DSP
— Host Command
Handshaking Protocols:
— Software polled
— Interrupt driven
— Core DMA accesses
Instructions:
•
•
— Memory-mapped registers allow the standard MOVE instruction to be used to transfer data
between the DSP and the external host.
— Special MOVEP instruction provides for I/O service capability using fast interrupts.
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HDI08 Features
— Bit addressing instructions (e.g. BCHG, BCLR, BSET, BTST, JCLR, JSCLR, JSET, JSSET)
simplify I/O service routines.
6.2.2
Interface - Host Side
•
Sixteen signals are provided to support non-multiplexed or multiplexed buses:
— H0-H7/HAD0-HAD7
Host data bus (H7-H0) or host multiplexed address/data bus (HAD0-HAD7)
— HAS/HA0
Address strobe (HAS) or Host address line HA0
— HA8/HA1
Host address line HA8 or Host address line HA1
— HA9/HA2
Host address line HA9 or Host address line HA2
— HRW/HRD
Read/write select (HRW) or Read Strobe (HRD)
— HDS/HWR
Data Strobe (HDS) or Write Strobe (HWR)
— HCS/HA10
Host chip select (HCS) or Host address line HA10
— HOREQ/HTRQ
Host request (HOREQ) or Host transmit request (HTRQ)
— HACK/HRRQ
Host acknowledge (HACK) or Host receive request (HRRQ)
•
Mapping:
— HDI08 registers are mapped into eight consecutive byte locations in the external host bus
address space.
— The HDI08 acts as a memory or IO-mapped peripheral for microprocessors, microcontrollers,
etc.
•
•
Data Word:
— 8-bit
Transfer Modes:
— Mixed 8-bit, 16-bit and 24-bit data transfers
– DSP to Host
– Host to DSP
— Host Command
Handshaking Protocols:
— Software polled
•
— Interrupt-driven (Interrupts are compatible with most processors, including the MC68000,
8051, HC11 and Hitachi H8).
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HDI08 Host Port Signals
— Cycle-stealing DMA with initialization
Dedicated Interrupts:
•
•
— Separate interrupt lines for each interrupt source
— Special host commands force DSP core interrupts under host processor control, which are
useful for the following:
– Real-Time Production Diagnostics
– Debugging Window for Program Development
– Host Control Protocols
Interface Capabilities:
— Glueless interface (no external logic required) to the following:
– Freescale HC11
– Hitachi H8
– 8051 family
– Thomson P6 family
– external DMA controllers
— Minimal glue-logic (pullups, pulldowns) required to interface to the following:
– ISA bus
– Motorola 68K family
– Intel X86 family.
6.3
HDI08 Host Port Signals
The host port signals are described in Section 2, "Signal/Connection Descriptions". If the Host Interface
functionality is not required, the 16 pins may be defined as general purpose I/O pins PB0-PB15. When the
HDI08 is in use, only five host port signals (HA8, HA9, HCS, HOREQ and HACK) may be individually
programmed as GPIO pins if they are not needed for their HDI08 function. Summary of the HDI08 signals.
Table 6-1 HDI08 Signal Summary
HDI08 Port Pin
HAD0-HAD7
HAS/HA0
Multiplexed address/data bus Mode
Non Multiplexed bus Mode
GPIO Mode
PB0-PB7
PB8
HAD0-HAD7
HAS/HAS
HA8
H0-H7
HA0
HA8/HA1
HA1
PB9
HA9/HA2
HA9
HA2
PB10
HCS/HA10
HA10
HCS/HCS
PB13
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HDI08 Block Diagram
Table 6-2 Strobe Signals Support signals
HDI08 Port Pin
HRW/HRD
Single strobe bus
HRW
Dual strobe bus
GPIO Mode
PB11
HRD/HRD
HWR/HWR
HDS/HWR
HDS/HDS
PB12
Table 6-3 Host request support signals
HDI08 Port Pin
HOREQ/HTRQ
HACK/HRRQ
Vector required
HOREQ/HOREQ
HACK/HACK
No vector required
GPIO Mode
PB14
HTRQ/HTRQ
HRRQ/HRRQ
PB15
6.4
HDI08 Block Diagram
Figure 6-1 shows the HDI08 registers. The top row of registers (HCR, HSR, HDDR, HDR, HBAR, HPCR,
HOTX, HORX) can be accessed the DSP core. The bottom row of registers (ISR, ICR, CVR, IVR,
RXH:RXM:RXL and TXH:TXM:TXL) can be accessed by the host processor.
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HDI08 – DSP-Side Programmer’s Model
Core DMA Data Bus
DSP Peripheral Data Bus
24 24
24
24
24
24
24
24
24 24
HCR
HSR
HDDR
HDR
HBAR
HPCR
HOTX
HOR
Address
Comparator
24
24
5
3
ICR
ISR
CVR
IVR
Latch
RXH RXM RXL
TXH TXM RXL
8
8
8
8
8
8
8
8
8
3
8
8
HOST Bus
ICR
CVR
ISR
IVR
Interface Control Register
HCR
Host Control Register
Host Status Register
Command Vector Register
Interface Status Register
HSR
HPCR
HBAR
HOTX
HORX
HDDR
HDR
Host Port Control Register
Interrupt Vector Register
Host Base Address register
Host Transmit register
Host Receive register
RXH/RXM/RXL
TXH/TXM/TXL
Receive Register High/Middle/Low
Transmit Register High/Middle/Low
Host Data Direction Register
Host Data Register
Figure 6-1 HDI08 Block Diagram
6.5
HDI08 – DSP-Side Programmer’s Model
The DSP core threats the HDI08 as a memory-mapped peripheral occupying eight 24-bit words in X data
memory space. The DSP may use the HDI08 as a normal memory-mapped peripheral, employing either
standard polled or interrupt-driven programming techniques. Separate transmit and receive data registers
are double-buffered to allow the DSP and host processor to transfer data efficiently at high speed. Direct
memory mapping allows the DSP core to communicate with the HDI08 registers using standard
instructions and addressing modes. In addition, the MOVEP instruction allows direct data transfers
between the DSP memory and the HDI08 registers or vice-versa. The HOTX and HORX registers may be
serviced by the on-chip DMA controller for data transfers.
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HDI08 – DSP-Side Programmer’s Model
The eight host processor registers consists of two data registers and six control registers. All registers can
be accessed by the DSP core but not by the external processor.
Data registers are 24-bit registers used for high-speed data transfer to and from the DSP. They are as
follows:
•
•
Host Data Receive Register (HORX)
Host Data Transmit Register (HOTX)
The control registers are 16-bit registers used to control the HDI08 functions. The eight MSBs in the
control registers are read by the DSP as zero. The control registers are as follows:
•
•
•
•
•
•
Host control register (HCR)
Host status register (HSR)
Host base address register (HBAR)
Host port control register (HPCR)
Host GPIO data direction register (HDDR)
Host GPIO data register (HDR)
Hardware and software reset disable the HDI08. After reset, the HDI08 signals are configured as GPIO
with all pins disconnected.
6.5.1
Host Receive Data Register (HORX)
The 24-bit read-only HORX register is used for host-to-DSP data transfers. The HORX register is loaded
with 24-bit data from the transmit data registers (TXH:TXM:TXL) on the host side when both the transmit
data register empty TXDE (host side) and host receive data full HRDF (DSP side) bits are cleared. This
transfer operation sets both the TXDE and HRDF flags. The HORX register contains valid data when the
HRDF bit is set. Reading HORX clears HRDF. The DSP may program the HRIE bit to cause a host receive
data interrupt when HRDF is set. Also, a DMA channel may be programmed to read the HORX when
HRDF is set.
6.5.2
Host Transmit Data Register (HOTX)
The 24-bit write-only HOTX register is used for DSP- to-host data transfers. Writing to the HOTX register
clears the host transfer data empty flag HTDE (DSP side). The contents of the HOTX register are
transferred as 24-bit data to the receive byte registers (RXH:RXM:RXL) when both the HTDE flag (DSP
side) and receive data full RXDF flag (host side) are cleared. This transfer operation sets the RXDF and
HTDE flags. The DSP may set the HTIE bit to cause a host transmit data interrupt when HTDE is set. Also,
a DMA Channel may be programmed to write to HOTX when HTDE is set. To prevent the previous data
from being overwritten, data should not be written to the HOTX until the HTDE flag is set.
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HDI08 – DSP-Side Programmer’s Model
NOTE
When writing data to a peripheral device, there is a two-cycle pipeline delay
until any status bits affected by the operation are updated. If the programmer
reads any of those status bits within the next two cycles, the bit will not
reflect its current status. See the DSP56300 Family Manual , Freescale
publication DSP56300FM for further details.
6.5.3
Host Control Register (HCR)
The HCR is 16-bit read/write control register used by the DSP core to control the HDI08 operating mode.
The initialization values for the HCR bits are described in Section 6.5.9, "DSP-Side Registers After
Reset". The HCR bits are described in the following paragraphs.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
HDM2 HMD1 HDM0 HF3
HF2 HCIE HTIE HRIE
- Reserved bit. Read as 0. Should be written with 0 for future compatibility.
Figure 6-2 Host Control Register (HCR) (X:$FFFFC2)
6.5.3.1
HCR Host Receive Interrupt Enable (HRIE) Bit 0
The HRIE bit is used to enable the host receive data interrupt request. When the host receive data full
(HRDF) status bit in the host status register (HSR) is set, a host receive data interrupt request occurs if
HRIE is set. If HRIE is cleared, HRDF interrupts are disabled.
6.5.3.2
HCR Host Transmit Interrupt Enable (HTIE) Bit 1
The HTIE bit is used to enable the host transmit data empty interrupt request. When the host transmit data
empty (HTDE) status bit in the HSR is set, a host transmit data interrupt request occurs if HTIE is set. If
HTIE is cleared, HTDE interrupts are disabled.
6.5.3.3
HCR Host Command Interrupt Enable (HCIE) Bit 2
The HCIE bit is used to enable the host command interrupt request. When the host command pending
(HCP) status bit in the HSR is set, a host command interrupt request occurs if HCIE is set. If HCIE is
cleared, HCP interrupts are disabled. The interrupt address is determined by the host command vector
register (CVR).
NOTE
Host interrupt request priorities: If more than one interrupt request source is
asserted and enabled (e.g. HRDF=1, HCP=1, HRIE=1 and HCIE=1), the
HDI08 generates interrupt requests according to the following table:
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HDI08 – DSP-Side Programmer’s Model
Table 6-4 HDI08 IRQ
Interrupt Source
Priority
Highest
Host Command (HCP=1)
Transmit Data (HTDE=1)
Receive Data (HRDF=1)
Lowest
6.5.3.4
HCR Host Flags 2,3 (HF2,HF3) Bits 3-4
HF2 and HF3 bits are used as a general-purpose flags for DSP to host communication. HF2 and HF3 may
be set or cleared by the DSP core. HF2 and HF3 are reflected in the interface status register (ISR) on the
host side such that if they are modified by the DSP software, the host processor can read the modified
values by reading the ISR.
These two flags are not designated for any specific purpose but are general-purpose flags. They can be
used individually or as encoded pairs in a simple DSP to host communication protocol, implemented in
both the DSP and the host processor software.
6.5.3.5
HCR Host DMA Mode Control Bits (HDM0, HDM1, HDM2) Bits 5-7
The HDM[2:0] bits are used to enable the HDI08 DMA mode operation. The HDI08 DMA mode supports
external DMA controller devices connected to the HDI08 on the Host side. This mode should not be
confused with the operation of the on-chip DMA controller.
With HDM[2:0] cleared, the HDI08 does not support DMA mode operation and the TREQ and RREQ
control bits are used for host processor interrupt control via the external HOREQ output signal (or HRREQ
and HTREQ output signals if HDREQ in the ICR is set). Also, in the non-DMA mode, the HACK input
signal is used for the MC68000 Family vectored interrupt acknowledge input. If HDM[2:0] are not all
Table 6-5 HDM[2:0] Functionality
HDM
Mode
2
1
0
Description
ICR
0
0
0
DMA operation disabled
INIT
HLEND HF1
HF0
HDRQ
TREQ
RREQ
1
0
0
DMA Operation Enabled.
Host may set HM1 or HM0 in
the ICR to enable DMA
transfers.
INIT
HM1
HM0
HF1
HF0
TREQ
RREQ
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HDI08 – DSP-Side Programmer’s Model
Table 6-5 HDM[2:0] Functionality (continued)
Mode
HDM
2
1
0
Description
ICR
0
0
1
DMA Mode Data Output
Transfers Enabled.
(24-Bit words)
0
0
1
1
1
1
1
0
1
1
0
1
1
0
1
DMA Mode Data Output
Transfers Enabled.
(16-Bit words)
DMA Mode Data Output
Transfers Enabled.
(8-Bit words)
INIT
HDM1
HDM0
HF1
HF0
TREQ
RREQ
DMA Mode Data Input
Transfers Enabled.
(24-Bit words)
DMA Mode Data Input
Transfers Enabled.
(16-Bit words)
DMA Mode Data Input
Transfers Enabled.
(8-Bit words)
If HDM1 or HDM0 are set, the DMA mode is enabled, and the HOREQ signal is used to request DMA
transfers (the value of the HM1, HM0, HLEND and HDREQ bits in the ICR have no affect). When the
DMA mode is enabled, the HDM2 bit selects the direction of DMA transfers:
•
setting HDM2 sets the direction of DMA transfer to be DSP to host and enables the HOREQ signal
to request data transfer.
•
clearing HDM2 sets the direction of DMA transfer to be host to DSP and enables the HOREQ
signal to request data transfer.
The HACK input signal is used as a DMA transfer acknowledge input. If the DMA direction is from DSP
to host, the contents of the selected register are driven onto the host data bus when HACK is asserted. If
the DMA direction is from host to DSP, the selected register is written from the host data bus when HACK
is asserted.
The size of the DMA word to be transferred is determined by the DMA control bits, HDM[1:0]. Only the
data registers TXH, TXM, TXL and RXH, RXM, RXL can be accessed in DMA mode.The HDI08 data
register selected during a DMA transfer is determined by a 2-bit address counter, which is preloaded with
the value in HDM[1:0]. The address counter substitutes for the address bits of the HDI08 during a DMA
transfer. The address counter can be initialized with the INIT bit feature. After each DMA transfer on the
host data bus, the address counter is incremented to the next register. When the address counter reaches
the highest register (RXL or TXL), the address counter is not incremented but is loaded with the value in
HDM[1:0]. This allows 8-, 16- or 24-bit data to be transferred in a circular fashion and eliminates the need
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HDI08 – DSP-Side Programmer’s Model
for the DMA controller to supply the HA2, HA1, and HA0 signals. For 16- or 24-bit data transfers, the
DSP CPU interrupt rate is reduced by a factor of 2 or 3, respectively, from the host request rate – i.e., for
every two or three host processor data transfers of one byte each, there is only one 24-bit DSP CPU
interrupt.
If HDM1 or HDM0 are set, the HM[1:0] bits in the ICR register reflect the value of HDM[1:0].
The HDM[2:0] bits should be changed only while HEN is cleared in the HPCR.
6.5.3.6
HCR Reserved Bits 8-15
These bits are reserved. They read as zero and should be written with zero for future compatibility.
6.5.4
Host Status Register (HSR)
The HSR is a 16-bit read-only status register used by the DSP to read the status and flags of the HDI08. It
cannot be directly accessed by the host processor. The initialization values for the HSR bits are described
paragraphs.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DMA
HF1
HF0
HCP HTDE HRDF
- Reserved bit. Read as 0. Should be written with 0 for future compatibility.
Figure 6-3 Host Status Register (HSR) (X:FFFFC3)
6.5.4.1
HSR Host Receive Data Full (HRDF) Bit 0
The HRDF bit indicates that the host receive data register (HORX) contains data from the host processor.
HRDF is set when data is transferred from the TXH:TXM:TXL registers to the HORX register. HRDF is
cleared when HORX is read by the DSP core. If HRDF is set the HDI08 generates a receive data full DMA
request, if enabled by a DSP core DMA Channel. If HRDF is set when HRIE is set, a host receive data
interrupt request is generated. HRDF can also be cleared by the host processor using the initialize function.
6.5.4.2
HSR Host Transmit Data Empty (HTDE) Bit 1
The HTDE bit indicates that the host transmit data register (HOTX) is empty and can be written by the
DSP core. HTDE is set when the HOTX register is transferred to the RXH:RXM:RXL registers. HTDE is
cleared when HOTX is written by the DSP core. If HTDE is set the HDI08 generates a transmit data empty
DMA request, if enabled by a DSP core DMA Channel. If HTDE is set when HTIE is set, a host transmit
data interrupt request is generated. HTDE can also be set by the host processor using the initialize function.
6.5.4.3
HSR Host Command Pending (HCP) Bit 2
The HCP bit indicates that the host has set the HC bit and that a host command interrupt is pending. The
HCP bit reflects the status of the HC bit in the command vector register (CVR). HC and HCP are cleared
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HDI08 – DSP-Side Programmer’s Model
by the HDI08 hardware when the interrupt request is serviced by the DSP core. The host can clear HC,
which also clears HCP.
6.5.4.4
HSR Host Flags 0,1 (HF0,HF1) Bits 3-4
HF0 and HF1 bits are used as a general-purpose flags for host to DSP communication. HF0 and HF1 may
be set or cleared by the host. HF0 and HF1 reflect the status of host flags HF0 and HF1 in the ICR register
on the host side.
These two flags are not designated for any specific purpose but are general-purpose flags. They can be
used individually or as encoded pairs in a simple host to DSP communication protocol, implemented in
both the DSP and the host Processor software.
6.5.4.5
HSR Reserved Bits 5-6, 8-15
These bits are reserved. They read as zero and should be written with zero for future compatibility.
6.5.4.6
HSR DMA Status (DMA) Bit 7
The DMA status bit is set when the DMA mode of operation is enabled, and is cleared when the DMA
mode is disabled. The DMA mode is enabled under the following conditions:
•
HCR bits HDM[2:0] = 100 and the host processor has enabled the DMA mode by setting either or
both the ICR bits HM1 and HM0
•
Either or both of the HCR bits HDM1 and HDM0 have been set
When the DMA bit is zero, the channel not in use can be used for polled or interrupt operation by the DSP.
6.5.5
Host Base Address Register (HBAR)
The HBAR is used in multiplexed bus modes. This register selects the base address where the host side
registers are mapped into the bus address space. The address from the host bus is compared with the base
address as programmed in the base address register. If the addresses match, an internal chip select is
.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BA10 BA9
BA8
BA7
BA6
BA5
BA4
BA3
- Reserved bit. Read as 0. Should be written with 0, for future compatibility.
Figure 6-4 Host Base Address Register (HBAR) (X:$FFFFC5)
6.5.5.1
HBAR Base Address (BA[10:3]) Bits 0-7
These bits define the base address where the host side registers are mapped into the bus address space.
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6.5.5.2
HBAR Reserved Bits 8-15
These bits are reserved. They read as zero and should be written with zero for future compatibility.
HAD[0-7]
Latch
A[3:7]
HAS
HA[8:10]
Chip select
Base
DSP Peripheral
data bus
Address 8 bits
register
BA[3:7]
Figure 6-5 Self Chip Select logic
6.5.6
Host Port Control Register (HPCR)
The HPCR is a 16-bit read/write control register used by the DSP to control the HDI08 operating mode.
The initialization values for the HPCR bits are described in Section 6.5.9, "DSP-Side Registers After
Reset". The HPCR bits are described in the following paragraphs.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
HAP HRP HCSP HDDS HMUX HASP HDSP HROD
HEN HAEN HREN HCSEN HA9EN HA8EN HGEN
- Reserved bit. Read as 0. Should be written with 0, for future compatibility.
Figure 6-6 Host Port Control Register (HPCR) (X:$FFFFC4)
NOTE
To assure proper operation of the HDI08, the HPCR bits HAP, HRP, HCSP,
HDDS, HMUX, HASP, HDSP, HROD, HAEN and HREN should be
changed only if HEN is cleared. Also, the HPCR bits HAP, HRP, HCSP,
HDDS, HMUX, HASP, HDSP, HROD, HAEN, HREN, HCSEN, HA9EN
and HA8EN should not be set when HEN is set or simultaneously with
setting HEN.
6.5.6.1
HPCR Host GPIO Port Enable (HGEN) Bit 0
If the HGEN bit is set, pins configured as GPIO are enabled. If this bit is cleared, pins configured as GPIO
are disconnected: outputs are high impedance, inputs are electrically disconnected. Pins configured as
HDI08 are not affected by the state of HGEN.
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6.5.6.2
HPCR Host Address Line 8 Enable (HA8EN) Bit 1
If the HA8EN bit is set and the HDI08 is used in multiplexed bus mode, then HA8/HA1 is used as host
address line 8 (HA8). If this bit is cleared and the HDI08 is used in multiplexed bus mode, then HA8/HA1
is configured as GPIO pin according to the value of HDDR and HDR registers. HA8EN is ignored when
the HDI08 is not in the multiplexed bus mode (HMUX=0).
6.5.6.3
HPCR Host Address Line 9 Enable (HA9EN) Bit 2
If the HA9EN bit is set and the HDI08 is used in multiplexed bus mode, then HA9/HA2 is used as host
address line 9 (HA9). If this bit is cleared and the HDI08 is used in multiplexed bus mode, then HA9/HA2
is configured as GPIO pin according to the value of HDDR and HDR registers. HA9EN is ignored when
the HDI08 is not in the multiplexed bus mode (HMUX=0).
6.5.6.4
HPCR Host Chip Select Enable (HCSEN) Bit 3
If the HCSEN bit is set, then HCS/HA10 is used as host chip select (HCS) in the non-multiplexed bus
mode (HMUX=0), and as host address line 10 (HA10) in the multiplexed bus mode (HMUX=1). If this bit
is cleared, then HCS/HA10 is configured as GPIO pin according to the value of HDDR and HDR registers.
6.5.6.5
HPCR Host Request Enable (HREN) Bit 4
The HREN bit controls the host request signals. If HREN is set and the HDI08 is in the single host request
mode (HDRQ=0 in the ICR), HOREQ/HTRQ is configured as the host request (HOREQ) output.
If HREN is set in the double host request mode (HDRQ=1 in the ICR), HOREQ/HTRQ is configured as
the host transmit request (HTRQ) output and HACK/HRRQ as the host receive request (HRRQ) output.
If HREN is cleared, HOREQ/HTRQ and HACK/HRRQ are configured as GPIO pins according to the
value of HDDR and HDR registers.
6.5.6.6
HPCR Host Acknowledge Enable (HAEN) Bit 5
The HAEN bit controls the HACK signal. In the single host request mode (HDRQ=0 in the ICR), if HAEN
and HREN are both set, HACK/HRRQ is configured as the host acknowledge (HACK) input. If HAEN or
HREN is cleared, HACK/HRRQ is configured as a GPIO pin according to the value of HDDR and HDR
registers. In the double host request mode (HDRQ=1 in the ICR), HAEN is ignored.
6.5.6.7
HPCR Host Enable (HEN) Bit 6
If the HEN bit is set, the HDI08 operation is enabled as Host Interface. If cleared, the HDI08 is not active,
and all the HDI08 pins are configured as GPIO pins according to the value of HDDR and HDR registers.
6.5.6.8
HPCR Reserved Bit 7
This bit is reserved. It reads as zero and should be written with zero for future compatibility.
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6.5.6.9
HPCR Host Request Open Drain (HROD) Bit 8
The HROD bit controls the output drive of the host request signals. In the single host request mode
(HDRQ=0 in ICR), if HROD is cleared and host requests are enabled (HREN=1 and HEN=1 in HPCR),
the HOREQ signal is always driven. If HROD is set and host requests are enabled, the HOREQ signal is
an open drain output.
In the double host request mode (HDRQ=1 in the ICR), if HROD is cleared and host requests are enabled
(HREN=1 and HEN=1 in the HPCR), the HTRQ and HRRQ signals are always driven. If HROD is set and
host requests are enabled, the HTRQ and HRRQ signals are open drain outputs.
6.5.6.10 HPCR Host Data Strobe Polarity (HDSP) Bit 9
If the HDSP bit is cleared, the data strobe signals are configured as active low inputs, and data is
transferred when the data strobe is low. If HDSP is set, the data strobe signals are configured as active high
inputs, and data is transferred when the data strobe is high. The data strobe signals are either HDS by itself
or HRD and HWR together.
6.5.6.11 HPCR Host Address Strobe Polarity (HASP) Bit 10
If the HASP bit is cleared, the address strobe (HAS) signal is an active low input, and the address on the
host address/data bus is sampled when the HAS signal is low. If HASP is set, HAS is an active high address
strobe input, and the address on the host address/data bus 8 is sampled when the HAS signal is high.
6.5.6.12 HPCR Host Multiplexed bus (HMUX) Bit 11
If the HMUX bit is set, the HDI08 latches the lower portion of a multiplexed address/data bus. In this mode
the internal address line values of the host registers are taken from the internal latch. If HMUX is cleared,
it indicates that the HDI08 is connected to a non-multiplexed type of bus, and the address lines are taken
from the HDI08 input signals.
6.5.6.13 HPCR Host Dual Data Strobe (HDDS) Bit 12
If the HDDS bit is cleared, the HDI08 operates in the single strobe bus mode. In this mode, the bus has a
single data strobe signal for both reads and writes. If HDDS is set, the HDI08 operates in the dual strobe
bus mode. In this mode, the bus has two separate data strobes, one for data reads, the other for data writes.
HRW
HDS
In the single strobe bus mode, the HDS (Data-Strobe) signal qualifies the access, while the
HRW (Read/Write) signal specifies the direction of the access.
Figure 6-7 Single strobe bus
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Write data in
Data
Write cycle
HWR
Read data out
Data
HRD
Read cycle
In the dual strobe bus mode, there are separate HRD and HWR signals that specify the access
as being a read or write access, respectively.
Figure 6-8 Dual strobes bus
6.5.6.14 HPCR Host Chip Select Polarity (HCSP) Bit 13
If the HCSP bit is cleared, the chip select (HCS) signal is configured as an active low input and the HDI08
is selected when the HCS signal is low. If HCSP is set, HCS is configured as an active high input and the
HDI08 is selected when the HCS signal is high. This bit is ignored in the multiplexed mode.
6.5.6.15 HPCR Host Request Polarity (HRP) Bit 14
The HRP bit controls the polarity of the host request signals. In the single host request mode (HDRQ=0 in
the ICR), if HRP is cleared and host requests are enabled (HREN=1 and HEN=1 in the HPCR), the
HOREQ signal is an active low output. If HRP is set and host requests are enabled, the HOREQ signal is
an active high output.
In the double host request mode (HDRQ=1 in the ICR), if HRP is cleared and host requests are enabled
(HREN=1 and HEN=1 in the HPCR), the HTRQ and HRRQ signals are active low outputs. If HRP is set
and host requests are enabled, the HTRQ and HRRQ signals are active high outputs.
6.5.6.16 HPCR Host Acknowledge Polarity (HAP) Bit 15
If the HAP bit is cleared, the host acknowledge (HACK) signal is configured as an active low input, and
the HDI08 drives the contents of the HIVR register onto the host bus when the HACK signal is low. If
HAP is set, HACK is configured as an active high input, and the HDI08 outputs the contents of the HIVR
register when the HACK signal is high.
6.5.7
Data direction register (HDDR)
The HDDR controls the direction of the data flow for each of the HDI08 pins configured as GPIO. Even
when the HDI08 is used as the host interface, some of its unused signals may be configured as GPIO pins.
For information on the HDI08 GPIO configuration options, see Section 6.6.8, "General Purpose
INPUT/OUTPUT (GPIO)". If bit DRxx is set, the corresponding HDI08 pin is configured as an output
signal. If bit DRxx is cleared, the corresponding HDI08 pin is configured as an input signal. See Table 6-6.
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15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DR15 DR14 DR13 DR12 DR11 DR10 DR9
DR8
DR7
DR6
DR5
DR4
DR3
DR2
DR1
DR0
Figure 6-9 Host Data Direction Register (HDDR) (X:$FFFFC8)
6.5.8
Host Data Register (HDR)
The HDR register holds the data value of the corresponding bits of the HDI08 pins which are configured
as GPIO pins. The functionality of the Dxx bit depends on the corresponding HDDR bit (DRxx). See
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Figure 6-10 Host Data Register (HDR) (X:$FFFFC9)
Table 6-6 HDR and HDDR Functionality
HDR
HDDR
Dxx
DRxx
1
GPIO pin
non-GPIO pin
0
Read only bit. The value read is the binary value of
the pin.
Read only bit. Does not contain significant data.
Read/write bit. The value written is the value read.
The corresponding pin is configured as an input.
1
Read/write bit. The value written is the value read.
The corresponding pin is configured as an output, and
is driven with the data written to Dxx.
1
Defined by the selected configuration
6.5.9
DSP-Side Registers After Reset
Table 6-7 shows the results of the four reset types on the bits in each of the HDI08 registers accessible by
the DSP core. The hardware reset (HW) is caused by the RESET signal. The software reset (SW) is caused
by executing the RESET instruction. The individual reset (IR) is caused by clearing the HEN bit (HPCR
bit 6). The stop reset (ST) is caused by executing the STOP instruction.
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Table 6-7 DSP-Side Registers after Reset
Reset Type
Register
Name
Register
Data
HW
SW
IR
ST
Reset
Reset
Reset
Reset
HCR
HPCR
HSR
All bits
All bits
0
0
—
—
—
—
0
0
HF[1:0]
HCP
0
0
—
—
0
1
0
1
0
0
HTDE
1
1
HRDF
0
0
0
0
DMA
0
0
—
—
HBAR
HDDR
HDR
BA[10:3]
DR[15:0]
D[15:0]
HORX[23:0]
HOTX[23:0]
$80
0
$80
0
—
—
—
—
—
—
—
—
HORX
HOTX
empty
empty
empty
empty
empty
empty
empty
empty
Note: A long dash (—) denotes that the register value is not affected by the specified reset.
6.5.10 Host Interface DSP Core Interrupts
The HDI08 may request interrupt service from either the DSP core or the host processor. The DSP core
interrupts are internal and do not require the use of an external interrupt pin. When the appropriate interrupt
enable bit in the HCR is set, an interrupt condition caused by the host processor sets the appropriate bit in
the HSR, generating an interrupt request to the DSP core. The DSP core acknowledges interrupts caused
by the host processor by jumping to the appropriate interrupt service routine. The three possible interrupts
are as follows:
•
•
•
Host command
Transmit data register empty
Receive data register full
Although there is a set of vectors reserved for host command use, the host command can access any
interrupt vector in the interrupt vector table. The DSP interrupt service routine must read or write the
appropriate HDI08 register (clearing HRDF or HTDE, for example) to clear the interrupt. In the case of
host command interrupts, the interrupt acknowledge from the DSP core program controller clears the
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ENABLE
HTIE
15
0
HF3
HF2
HCIE
HRIE
HCR
X:HCR
DSP CORE INTERRUPTS
RECIEVE DATA FULL
TRANSMIT DATA EMPTY
HOST COMMAND
15
0
X:HSR
HF1
HF0
HCP
HTDE HRDF HSR
STATUS
Figure 6-11 HSR-HCR Operation
6.6
HDI08 – External Host Programmer’s Model
The HDI08 has been designed to provide a simple, high speed interface to a host processor. To the host
bus, the HDI08 appears to be eight byte-wide registers. Separate transmit and receive data registers are
double-buffered to allow the DSP core and host processor to transfer data efficiently at high speed. The
host may access the HDI08 asynchronously by using polling techniques or interrupt-based techniques.
The HDI08 appears to the host processor as a memory-mapped peripheral occupying 8 bytes in the host
•
•
•
•
A control register (ICR)
A status register (ISR)
Three data registers (RXH/TXH, RXM/TXM and RXL/TXL)
Two vector registers (IVR and CVR)
These registers can be accessed only by the host processor.
Host processors may use standard host processor instructions (e.g., byte move) and addressing modes to
communicate with the HDI08 registers. The HDI08 registers are aligned so that 8-bit host processors can
use 8/16/24-bit load and store instructions for data transfers. The HOREQ/HTRQ and HACK/HRRQ
handshake flags are provided for polled or interrupt-driven data transfers with the host processor. Because
the DSP interrupt response, most host microprocessors can load or store data at their maximum
programmed I/O instruction rate without testing the handshake flags for each transfer. If full handshake is
not needed, the host processor can treat the DSP as a fast device, and data can be transferred between the
host processor and the DSP at the fastest host processor data rate.
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One of the most innovative features of the host interface is the host command feature. With this feature,
the host processor can issue vectored interrupt requests to the DSP core. The host may select any of 128
DSP interrupt routines to be executed by writing a vector address register in the HDI08. This flexibility
allows the host programmer to execute up to 128 pre-programmed functions inside the DSP. For example,
host interrupts can allow the host processor to read or write DSP registers (X, Y, or program memory
locations), force interrupt handlers (e.g. IRQA, IRQB, etc. interrupt routines), and perform control and
debugging operations if interrupt routines are implemented in the DSP to perform these tasks.
Table 6-8 HDI08 Host Side Register Map
Host
Address
Big Endian
HLEND=0
Little Endian
HLEND=1
Function
0
1
2
3
4
5
6
7
ICR
CVR
ICR
CVR
Interface Control
Command Vector
Interface Status
Interrupt Vector
Unused
ISR
ISR
IVR
IVR
00000000
00000000
RXL/TXL
RXM/TXM
RXH/TXH
1
RXH/TXH
Receive/Transmit
Bytes
RXM/TXM
RXL/TXL
Host Data Bus
H0 - H7
Host Data Bus
H0 - H7
1
The RXH/TXH register is always mapped to the most significant byte of the DSP word.
6.6.1
Interface Control Register (ICR)
The ICR is an 8-bit read/write control register used by the host processor to control the HDI08 interrupts
and flags. The ICR cannot be accessed by the DSP core. The ICR is a read/write register, which allows the
use of bit manipulation instructions on control register bits. The control bits are described in the following
paragraphs.
Bits 2, 5 and 6 of the ICR are affected by the condition of HDM[2:0] (HCR bits 5-7), as shown in
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7
6
5
4
3
2
1
0
For HDM[2:0]=000
For HDM[2:0]=100
INIT
INIT
INIT
HLEND
HF1
HF0
HDRQ
TREQ
RREQ
HM1
HM0
HF1
HF1
HF0
HF0
TREQ
TREQ
RREQ
RREQ
For HDM1=1 and/or HDM0=1
HDM1
HDM0
HDM[1:0] - These read-only bits reflect the value of the HDM[1:0] bits in the HCR.
- Reserved bit. Read as 0. Should be written with 0 for future compatibility.
Figure 6-12 Interface Control Register (ICR)
6.6.1.1
ICR Receive Request Enable (RREQ) Bit 0
In interrupt mode (HDM[2:0]=000 or HM[1:0]=00), RREQ is used to enable host receive data requests via
the host request (HOREQ or HRRQ) signal when the receive data register full (RXDF) status bit in the
ISR is set. If RREQ is cleared, RXDF requests are disabled. If RREQ is set, the host request signal
(HOREQ or HRRQ) is asserted if RXDF is set.
In the DMA modes where HDM[2:0]=100 and (HM1≠0 or HM0≠0), RREQ must be set and TREQ must
be cleared to direct DMA transfers from DSP to host. In the other DMA modes, RREQ is ignored.
Table 6-9 summarizes the effect of RREQ and TREQ on the HOREQ, HTRQ and HRRQ signals.
6.6.1.2
ICR Transmit Request Enable (TREQ) Bit 1
In interrupt mode (HDM[2:0]=000 or HM[1:0]=00), TREQ is used to enable host transmit data requests
via the host request (HOREQ or HTRQ) signal when the transmit data register empty (TXDE) status bit
in the ISR is set. If TREQ is cleared, TXDE requests are disabled. If TREQ is set, the host request signal
(HOREQ or HTRQ) is asserted if TXDE is set.
In the DMA modes where HDM[2:0]=100 and (HM1≠0 or HM0≠0), TREQ must be set and RREQ must
be cleared to direct DMA transfers from host to DSP. In the other DMA modes, TREQ is ignored.
Table 6-9 summarizes the effect of RREQ and TREQ on the HOREQ, HTRQ and HRRQ signals.
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Table 6-9 TREQ RREQ Interrupt Mode (HDM[2:0]=000 or HM[1:0]=00)
HDRQ=0
HDRQ=1
TREQ RREQ
HOREQ signal
HTRQ signal
No Interrupts (Polling)
No Interrupts (Polling)
TXDE Request (Interrupt)
TXDE Request (Interrupt)
HRRQ signal
0
0
1
1
0
1
0
1
No Interrupts (Polling)
No Interrupts (Polling)
RXDF Request (Interrupt)
No Interrupts (Polling)
RXDF Request (Interrupt)
RXDF Request (Interrupt)
TXDE Request (Interrupt)
RXDF and TXDE Requests (Interrupts)
Table 6-10 TREQ RREQ DMA Mode (HM1≠0 or HM0≠0)
TREQ RREQ
HDRQ=0
HDRQ=1
HOREQ signal
HTRQ signal
No DMA request
HRRQ signal
0
0
1
1
0
1
0
1
No DMA request
No DMA request
DSP to Host Request (RX)
No DMA request
Reserved
DSP to Host Request (RX)
Host to DSP Request (TX)
Reserved
No DMA request
Host to DSP Request (TX)
Reserved
6.6.1.3
ICR Double Host Request (HDRQ) Bit 2
The HDRQ bit determines the functions of the HOREQ/HTRQ and HACK/HRRQ signals as shown in
Table 6-11 HDRQ
HDRQ
HOREQ/HTRQ pin
HOREQ signal
HTRQ signal
HACK/HRRQ pin
HACK signal
0
1
HRRQ signal
6.6.1.4
ICR Host Flag 0 (HF0) Bit 3
The HF0 bit is used as a general purpose flag for host-to-DSP communication. HF0 may be set or cleared
by the host processor and cannot be changed by the DSP core. HF0 is reflected in the HSR on the DSP side
of the HDI08.
6.6.1.5
ICR Host Flag 1 (HF1) Bit 4
The HF1 bit is used as a general purpose flag for host-to-DSP communication. HF1 may be set or cleared
by the host processor and cannot be changed by the DSP core. HF1 is reflected in the HSR on the DSP side
of the HDI08.
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6.6.1.6
ICR Host Little Endian (HLEND) Bit 5
If the HLEND bit is cleared, the HDI08 can be accessed by the host in big endian byte order. If set, the
HDI08 can be accessed by the host in little endian byte order. If the HLEND bit is cleared, the RXH/TXH
register is located at address $5, the RXM/TXM register is located at address $6, and the RXL/TXL
register is located at address $7. If the HLEND bit is set, the RXH/TXH register is located at address $7,
the RXM/TXM register is located at address $6, and the RXL/TXL is located at address $5. See Table 6-8
for an illustration of the effect of HLEND.
The HLEND function is available only if HDM[2:0]=000 in the host control register (HCR). When
HLEND is available, the ICR bit 6 has no function and should be regarded as reserved.
Bits 6 and 5 function as read/write HM[1:0] bits only when the HCR bits HDM[2:0]=100 (See Table 6-5).
Table 6-12 Host Mode Bit Definition
HM1
HM0
Mode
Interrupt Mode (DMA Off)
DMA Mode (24 Bit)
DMA Mode (16 Bit)
DMA Mode (8 Bit)
0
0
1
1
0
1
0
1
When both HM1 and HM0 are cleared, the DMA mode is disabled and the interrupt mode is enabled. In
interrupt mode, the TREQ and RREQ control bits are used for host processor interrupt control via the
external HOREQ output signal, and the HACK input signal is used for the MC68000 Family vectored
interrupt acknowledge input.
When HM1 and/or HM0 are set, they enable the DMA mode and determine the size of the DMA word to
be transferred. In the DMA mode, the HOREQ signal is used to request DMA transfers, the TREQ and
RREQ bits select the direction of DMA transfers (see Table 6-10), and the HACK input signal is used as
a DMA transfer acknowledge input. If the DMA direction is from DSP to host, the contents of the selected
register are enabled onto the host data bus when HACK is asserted. If the DMA direction is from host to
DSP, the selected register is written from the host data bus when HACK is asserted.
The size of the DMA word to be transferred is determined by the DMA control bits, HM0 and HM1. The
HDI08 host side data register selected during a DMA transfer is determined by a 2-bit address counter,
which is preloaded with the value in HM1 and HM0. The address counter substitutes for the HA1 and HA0
host address signals of the HDI08 during a DMA transfer. The host address signal HA2 is forced to one
during each DMA transfer. The address counter can be initialized with the INIT bit feature. After each
DMA transfer on the host data bus, the address counter is incremented to the next data register. When the
address counter reaches the highest register (RXL or TXL), the address counter is not incremented but is
loaded with the value in HM1 and HM0. This allows 8-, 16- or 24-bit data to be transferred in a circular
fashion and eliminates the need for the DMA controller to supply the HA2, HA1, and HA0 address signals.
For 16- or 24-bit data transfers, the DSP CPU interrupt rate is reduced by a factor of 2 or 3, respectively,
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HDI08 – External Host Programmer’s Model
from the host request rate – i.e., for every two or three host processor data transfers of one byte each, there
is only one 24-bit DSP CPU interrupt.
If either HDM1 or HDM0 in the HCR register are set, bits 6 and 5 become read-only bits that reflect the
value of HDM[1:0].
6.6.1.7
ICR Initialize Bit (INIT) Bit 7
The INIT bit is used by the host processor to force initialization of the HDI08 hardware. During
initialization, the HDI08 transmit and receive control bits are configured.
Using the INIT bit to initialize the HDI08 hardware may or may not be necessary, depending on the
software design of the interface.
The type of initialization done when the INIT bit is set depends on the state of TREQ and RREQ in the
HDI08. The INIT command, which is local to the HDI08, is designed to conveniently configure the HDI08
into the desired data transfer mode. The effect of the INIT command is described in Table 6-13. When the
host sets the INIT bit, the HDI08 hardware executes the INIT command. The interface hardware clears the
INIT bit after the command has been executed.
Table 6-13 INIT Command Effect
Transfer Direction
TREQ
RREQ
After INIT Execution
Initialized
0
0
1
1
0
1
0
1
INIT=0
None
INIT=0; RXDF=0; HTDE=1
DSP to Host
INIT=0; TXDE=1; HRDF=0
Host to DSP
INIT=0; RXDF=0; HTDE=1; TXDE=1; HRDF=0
Host to/from DSP
6.6.2
Command Vector Register (CVR)
The CVR is used by the host processor to cause the DSP core to execute an interrupt. The host command
feature is independent of any of the data transfer mechanisms in the HDI08. It can be used to invoke
execution of any of the 128 possible interrupt routines in the DSP core.
7
6
5
4
3
2
1
0
HC
HV6
HV5
HV4
HV3
HV2
HV1
HV0
Figure 6-13 Command Vector Register (CVR)
6.6.2.1
CVR Host Vector (HV[6:0]) Bits 0–6
The seven HV bits select the host command interrupt address to be used by the host command interrupt
logic. When the host command interrupt is recognized by the DSP interrupt control logic, the address of
the interrupt routine taken is 2 ∗ HV. The host can write HC and HV in the same write cycle.
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HDI08 – External Host Programmer’s Model
The host processor can select the starting address of any of the 128 possible interrupt routines in the DSP
by writing the interrupt routine address divided by 2 into the HV bits. The host processor can thus force
execution of any of the existing interrupt handlers (IRQA, IRQB, etc.) and can use any of the reserved or
otherwise unused addresses provided they have been pre-programmed in the DSP. HV[6:0] is set to $32
(vector location $0064) by hardware, software, individual and stop resets.
6.6.2.2
CVR Host Command Bit (HC) Bit 7
The HC bit is used by the host processor to handshake the execution of host command interrupts.
Normally, the host processor sets HC to request the host command interrupt from the DSP core. When the
host command interrupt is acknowledged by the DSP core, the HC bit is cleared by the HDI08 hardware.
The host processor can read the state of HC to determine when the host command has been accepted. After
setting HC, the host must not write to the CVR again until HC is cleared by the HDI08 hardware. Setting
HC causes the host command pending (HCP) in the HSR to be set. The host can write to the HC and HV
bits in the same write cycle.
6.6.3
Interface Status Register (ISR)
The ISR is an 8-bit read-only status register used by the host processor to interrogate the status and flags
of the HDI08. The host processor can write to this address without affecting the internal state of the HDI08,
which is useful if the user desires to access all of the HDI08 registers by stepping through the HDI08
addresses. The ISR cannot be accessed by the DSP core. The ISR bits are described in the following
paragraphs.
7
6
5
4
3
2
1
0
HREQ
HF3
HF2
TRDY
TXDE
RXDF
- Reserved bit. Read as 0. Should be written with 0 for future compatibility.
Figure 6-14 Interface Status Register (ISR)
6.6.3.1
ISR Receive Data Register Full (RXDF) Bit 0
The RXDF bit indicates that the receive byte registers (RXH:RXM:RXL) contain data from the DSP core
and may be read by the host processor. RXDF is set when the contents of HOTX is transferred to the
receive byte registers. RXDF is cleared when the receive data (RXL or RXH according to HLEND bit)
register is read by the host processor. RXDF can be cleared by the host processor using the initialize
function. RXDF may be used to assert the external HOREQ signal if the RREQ bit is set. Regardless of
whether the RXDF interrupt is enabled, RXDF indicates whether the RX registers are full and data can be
latched out (so that polling techniques may be used by the host processor).
6.6.3.2
ISR Transmit Data Register Empty (TXDE) Bit 1
The TXDE bit indicates that the transmit byte registers (TXH:TXM:TXL) are empty and can be written
by the host processor. TXDE is set when the contents of the transmit byte registers are transferred to the
HORX register. TXDE is cleared when the transmit (TXL or TXH according to HLEND bit) register is
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HDI08 – External Host Programmer’s Model
written by the host processor. TXDE can be set by the host processor using the initialize feature. TXDE
may be used to assert the external HOREQ signal if the TREQ bit is set. Regardless of whether the TXDE
interrupt is enabled, TXDE indicates whether the TX registers are full and data can be latched in (so that
polling techniques may be used by the host processor).
6.6.3.3
ISR Transmitter Ready (TRDY) Bit 2
The TRDY status bit indicates that TXH:TXM:TXL and the HORX registers are empty.
TRDY=TXDE • HRDF
If TRDY is set, the data that the host processor writes to TXH:TXM:TXL is immediately transferred to
the DSP side of the HDI08. This feature has many applications. For example, if the host processor issues
a host command which causes the DSP core to read the HORX, the host processor can be guaranteed that
the data it just transferred to the HDI08 is what is being received by the DSP core.
6.6.3.4
ISR Host Flag 2 (HF2) Bit 3
The HF2 bit in the ISR indicates the state of host flag 2 in the HCR on the DSP side. HF2 can be changed
6.6.3.5
ISR Host Flag 3 (HF3) Bit 4
The HF3 bit in the ISR indicates the state of host flag 3 in the HCR on the DSP side. HF3 can be changed
6.6.3.6
ISR Reserved Bits 5-6
These bits are reserved. They read as zero and should be written with zero for future compatibility.
6.6.3.7
ISR Host Request (HREQ) Bit 7
The HREQ bit indicates the status of the external host request output signal (HOREQ) if HDRQ is cleared.
If HDRQ is set, it indicates the status of the external transmit and receive request output signals (HTRQ
and HRRQ).
Table 6-14 Host Request Status (HREQ)
HREQ
Status [HDRQ=0]
Status [HDRQ=1]
0
HOREQ deasserted; no host processor interrupt is
requested
HTRQ and HRRQ deasserted; no host processor
interrupts are requested
1
HOREQ asserted; a host processor interrupt is
requested
HTRQ and/or HRRQ asserted; host processor
interrupts are requested
The HREQ bit may be set from either or both of two conditions – either the receive byte registers are full
or the transmit byte registers are empty. These conditions are indicated by the ISR RXDF and TXDE status
bits, respectively. If the interrupt source has been enabled by the associated request enable bit in the ICR,
HREQ is set if one or more of the two enabled interrupt sources is set.
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HDI08 – External Host Programmer’s Model
6.6.4
Interrupt Vector Register (IVR)
The IVR is an 8-bit read/write register which typically contains the interrupt vector number used with
MC68000 Family processor vectored interrupts. Only the host processor can read and write this register.
The contents of IVR are placed on the host data bus (H0–H7) when both the HOREQ and HACK signals
are asserted. The contents of this register are initialized to $0F by hardware or software reset, which
corresponds to the uninitialized interrupt vector in the MC68000 Family.
7
6
5
4
3
2
1
0
IV7
IV6
IV5
IV4
IV3
IV2
IV1
IV0
Figure 6-15 Interrupt Vector Register (IVR)
6.6.5
Receive Byte Registers (RXH:RXM:RXL)
The receive byte registers are viewed by the host processor as three 8-bit read-only registers. These
registers are the receive high register (RXH), the receive middle register (RXM) and the receive low
register (RXL). They receive data from the high, middle and low bytes, respectively, of the HOTX register
and are selected by the external host address inputs (HA2, HA1 and HA0) during a host processor read
operation.
The memory locations of the receive byte registers are determined by the HLEND bit in the ICR. If the
HLEND bit is set, the RXH is located at address $7, RXM at $6 and RXL at $5. If the HLEND bit is
cleared, the RXH is located at address $5, RXM at $6 and RXL at $7.
When data is transferred from the HOTX register to the receive byte registers, the receive data register full
(RXDF) bit is set. The host processor may program the RREQ bit to assert the external HOREQ/HRRQ
signal when RXDF is set. This indicates that the HDI08 has a full word (either 8, 16 or 24 bits) for the host
processor. When the host reads the receive byte register at host address $7, the RXDF bit is cleared.
6.6.6
Transmit Byte Registers (TXH:TXM:TXL)
The transmit byte registers are viewed as three 8-bit write-only registers by the host processor. These
registers are the transmit high register (TXH), the transmit middle register (TXM) and the transmit low
register (TXL). These registers send data to the high, middle and low bytes, respectively, of the HORX
register and are selected by the external host address inputs (HA2, HA1 and HA0) during a host processor
write operation.
If the HLEND bit in the ICR is cleared, the TXH is located at address $5, TXM at $6 and TXL at $7. If
the HLEND bit in the ICR is set, the TXH is located at address $7, TXM at $6 and TXL at $5.
Data may be written into the transmit byte registers when the transmit data register empty (TXDE) bit is
set. The host processor may program the TREQ bit to assert the external HOREQ/HTRQ signal when
TXDE is set. This informs the host processor that the transmit byte registers are empty. Writing to the data
register at host address $7 clears the TXDE bit. The contents of the transmit byte registers are transferred
as 24-bit data to the HORX register when both TXDE and the HRDF bit are cleared. This transfer
operation sets TXDE and HRDF.
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HDI08 – External Host Programmer’s Model
6.6.7
Host Side Registers After Reset
Table 6-15 shows the result of the four kinds of reset on bits in each of the HDI08 registers seen by the
host processor. The hardware reset (HW) is caused by asserting the RESET signal. The software reset
(SW) is caused by executing the RESET instruction. The individual reset (IR) is caused by clearing the
HEN bit in the HPCR register. The stop reset (ST) is caused by executing the STOP instruction.
Table 6-15 Host Side Registers After Reset
Reset Type
Register
Name
Register
Data
HW
SW
IR
ST
Reset
Reset
Reset
Reset
ICR
All Bits
HC
0
0
0
0
—
0
—
0
CVR
HV[6:0]
HREQ
$32
0
$32
0
—
—
ISR
1 if TREQ is set;
0 otherwise
1 if TREQ is set;
0 otherwise
HF3-HF2
TRDY
0
1
0
1
—
1
—
1
TXDE
1
1
1
1
RXDF
0
0
0
0
IVR
RX
TX
IV[7:0]
$0F
empty
empty
$0F
empty
empty
—
—
RXH:RXM:RXL
TXH:TXM:TXL
empty
empty
empty
empty
Note: A long dash (—) denotes that the register value is not affected by the specified reset.
6.6.8
General Purpose INPUT/OUTPUT (GPIO)
When configured as general-purpose I/O, the HDI08 is viewed by the DSP core as memory-mapped
registers (see Section 6.5, "HDI08 – DSP-Side Programmer’s Model") that control up to 16 I/O pins. The
software and hardware resets clear all DSP-side control registers and configure the HDI08 as GPIO with
all 16 signals disconnected. External circuitry connected to the HDI08 may need external
pull-up/pull-down resistors until the signals are configured for operation. The registers cleared are the
HPCR, HDDR and HDR. Selection between GPIO and HDI08 is made by clearing HPCR bits 6 through
1 for GPIO or setting these bits for HDI08 functionality. If the HDI08 is in GPIO mode, the HDDR
configures each corresponding signal in the HDR as an input signal if the HDDR bit is cleared or as an
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Servicing The Host Interface
6.7
Servicing The Host Interface
The HDI08 can be serviced by using one of the following protocols:
•
•
Polling
Interrupts
6.7.1
HDI08 Host Processor Data Transfer
To the host processor, the HDI08 appears as a contiguous block of static RAM. To transfer data between
itself and the HDI08, the host processor performs the following steps:
1. Asserts the HDI08 address to select the register to be read or written.
2. Selects the direction of the data transfer. If it is writing, the host processor drives the data on the
bus.
3. Strobes the data transfer.
6.7.2
Polling
In the polling mode of operation, the HOREQ/HTRQ signal is not connected to the host processor and
HACK must be deasserted to ensure IVR data is not being driven on H0-H7 when other registers are being
polled.
The host processor first performs a data read transfer to read the ISR register.This allows the host processor
to assess the status of the HDI08:
1. If RXDF=1, the receive byte registers are full and therefore a data read can be performed by the
host processor.
2. If TXDE=1, the transmit byte registers are empty. A data write can be performed by the host
processor.
3. If TRDY=1, the transmit byte registers and the receive data register on the DSP side are empty.
Data written by the host processor is transferred directly to the DSP side.
4. If (HF2 • HF3) ≠ 0, depending on how the host flags have been defined, may indicate an
application-specific state within the DSP core has been reached. Intervention by the host processor
may be required.
5. If HREQ=1, the HOREQ/HTRQ/HRRQ signal has been asserted, and the DSP is requesting the
attention of the host processor. One of the previous four conditions exists.
After the appropriate data transfer has been made, the corresponding status bit is updated to reflect the
transfer.
If the host processor has issued a command to the DSP by writing the CVR and setting the HC bit, it can
read the HC bit in the CVR to determine when the command has been accepted by the interrupt controller
in the DSP core. When the command has been accepted for execution, the HC bit is cleared by the interrupt
controller in the DSP core.
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Servicing The Host Interface
STATUS
7
0
$2
HREQ
0
0
HF3
HF2
TRDY TXDE RXDF ISR
Host Request
ASSERTED
HRRQ
HOREQ
HTRQ
7
0
$0 INIT
0
HLEND HF1
HF0
HDRQ TREQ RREQ
ENABLE
ICR
Figure 6-16 HDI08 Host Request Structure
6.7.3
Servicing Interrupts
If either the HOREQ/HTRQ or the HRRQ signal or both are connected to the host processor interrupt
inputs, the HDI08 can request service from the host processor by asserting one of these signals. The
HOREQ/HTRQ and/or the HRRQ signal is asserted when TXDE=1 and/or RXDF=1 and the
HOREQ/HTRQ and HRRQ are normally connected to the host processor maskable interrupt inputs. The
host processor acknowledges host interrupts by executing an interrupt service routine. The host processor
can test RXDF and TXDE to determine the interrupt source. The host processor interrupt service routine
must read or write the appropriate HDI08 data register to clear the interrupt. HOREQ/HTRQ and/or HRRQ
is deasserted under the following conditions:
•
•
The enabled request is cleared or masked
The DSP is reset.
If the host processor is a member of the MC68000 family, there is no need for the additional step when the
host processor reads the ISR to determine how to respond to an interrupt generated by the DSP. Instead,
the DSP automatically sources the contents of the IVR on the data bus when the host processor
acknowledges the interrupt by asserting HACK. The contents of the IVR are placed on the host data bus
while HOREQ and HACK are simultaneously asserted. The IVR data tells the MC680XX host processor
which interrupt routine to execute to service the DSP.
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Servicing The Host Interface
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7 Serial Host Interface
7.1
Introduction
The Serial Host Interface (SHI) is a serial I/O interface that provides a path for communication and
program/coefficient data transfers between the DSP and an external host processor. The SHI can also
communicate with other serial peripheral devices. The SHI supports two well-known and widely used
synchronous serial buses: the Freescale Serial Peripheral Interface (SPI) bus and the Philips
2
Inter-Integrated-Circuit Control (I C) bus. The SHI supports either bus protocol as either a slave or a
single-master device. To minimize DSP overhead, the SHI supports 8-bit, 16-bit and 24-bit data transfers.
The SHI has a 1 or 10-word receive FIFO that permits receiving up to 30 bytes before generating a receive
interrupt, reducing the overhead for data reception.
When configured in the SPI mode, the SHI can perform the following functions:
•
•
•
•
•
•
•
•
Identify its slave selection (in slave mode)
Simultaneously transmit (shift out) and receive (shift in) serial data
Directly operate with 8-, 16- and 24-bit words
Generate vectored interrupts separately for receive and transmit events and update status bits
Generate a separate vectored interrupt for a receive exception
Generate a separate vectored interrupt for a bus-error exception
Generate the serial clock signal (in master mode)
Trigger DMA interrupts to service the transmit and receive events
2
When configured in the I C mode, the SHI can perform the following functions:
•
•
•
•
•
•
•
•
•
•
•
•
Detect/generate start and stop events
Identify its slave (ID) address (in slave mode)
Identify the transfer direction (receive/transmit)
Transfer data byte-wise according to the SCL clock line
Generate ACK signal following a byte receive
Inspect ACK signal following a byte transmit
Directly operate with 8-, 16- and 24-bit words
Generate vectored interrupts separately for receive and transmit events and update status bits
Generate a separate vectored interrupt for a receive exception
Generate a separate vectored interrupt for a bus error exception
Generate the clock signal (in master mode)
Trigger DMA interrupts to service the transmit and receive events
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Serial Host Interface Internal Architecture
7.2
Serial Host Interface Internal Architecture
The DSP views the SHI as a memory-mapped peripheral in the X data memory space. The DSP uses the
SHI as a normal memory-mapped peripheral using standard polling or interrupt programming techniques
and DMA transfers. Memory mapping allows DSP communication with the SHI registers to be
accomplished using standard instructions and addressing modes. In addition, the MOVEP instruction
allows interface-to-memory and memory-to-interface data transfers without going through an intermediate
register. The DMA controller may be used to service the receive or transmit data path. The single master
configuration allows the DSP to directly connect to dumb peripheral devices. For that purpose, a
programmable baud-rate generator is included to generate the clock signal for serial transfers. The host
side invokes the SHI for communication and data transfer with the DSP through a shift register that may
2
be accessed serially using either the I C or the SPI bus protocols. Figure 7-1 shows the SHI block diagram.
Host Accessible
DSP Accessible
DSP
Global
Data
Bus
Clock
Generator
SCK/SCL
MISO/SDA
MOSI/HA0
SS/HA2
DSP
HCKR
HCSR
HTX
DMA
Data
Bus
Controller
Logic
Pin
Control
Logic
INPUT/OUTPUT Shift Register
(IOSR)
HREQ
HRX
(FIFO)
Slave
Address
Recognition
Unit
(SAR)
HSAR
24 BIT
Figure 7-1 Serial Host Interface Block Diagram
AA0416
7.3
SHI Clock Generator
The SHI clock generator generates the SHI serial clock if the interface operates in the master mode. The
2
clock generator is disabled if the interface operates in the slave mode, except in I C mode when the
HCKFR bit is set in the HCKR register. When the SHI operates in the slave mode, the clock is external
and is input to the SHI (HMST = 0). Figure 7-2 illustrates the internal clock path connections. It is the
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Serial Host Interface Programming Model
2
user’s responsibility to select the proper clock rate within the range as defined in the I C and SPI bus
specifications.
HMST
SHI Clock
SCK/SCL
HMST = 0
Divide By 1
Divide
By 2
Divide By
1 or 8
Clock
Logic
SHI
Controller
To
F
OSC
Divide By 256
HMST = 1
2
HDM0–HDM7
HRS
CPHA, CPOL, HI C
AA0417
Figure 7-2 SHI Clock Generator
7.4
Serial Host Interface Programming Model
The Serial Host Interface programming model has two parts:
•
•
information.
23
0
I/O Shift Register (IOSR)
IOSR
AA0418
Figure 7-3 SHI Programming Model—Host Side
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Serial Host Interface Programming Model
The SHI interrupt vector table is shown in Table 7-1 and the exception priorities generated by the SHI are
Table 7-1 SHI Interrupt Vectors
Program Address
VBA:$0040
Interrupt Source
SHI Transmit Data
VBA:$0042
SHI Transmit Underrun Error
SHI Receive FIFO Not Empty
SHI Receive FIFO Full
SHI Receive Overrun Error
SHI Bus Error
VBA:$0044
VBA:$0048
VBA:$004A
VBA:$004C
Table 7-2 SHI Internal Interrupt Priorities
Interrupt
Priority
Highest
SHI Bus Error
SHI Receive Overrun Error
SHI Transmit Underrun Error
SHI Receive FIFO Full
SHI Transmit Data
Lowest
SHI Receive FIFO Not Empty
7.4.1
SHI Input/Output Shift Register (IOSR)—Host Side
The variable length Input/Output Shift Register (IOSR) can be viewed as a serial-to-parallel and
parallel-to-serial buffer in the SHI. The IOSR is involved with every data transfer in both directions (read
2
and write). In compliance with the I C and SPI bus protocols, data is shifted in and out MSB first. In 8-bit
data transfer modes, the most significant byte of the IOSR is used as the shift register. In 16-bit data
transfer modes, the two most significant bytes become the shift register. In 24-bit transfer modes, the shift
NOTE
The IOSR cannot be accessed directly either by the host processor or by the
DSP. It is fully controlled by the SHI controller logic.
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Serial Host Interface Programming Model
23
15
7
16
8
0
Mode of Operation
8-Bit Data
Mode
16-Bit Data
Mode
24-Bit Data
Mode
Stops Data When Data Mode is Selected
Passes Data When Data Mode is Selected
AA0420
Figure 7-5 SHI I/O Shift Register (IOSR)
7.4.2
SHI Host Transmit Data Register (HTX)—DSP Side
The host transmit data register (HTX) is used for DSP-to-Host data transfers. The HTX register is 24 bits
wide. Writing to the HTX register by DSP core instructions or by DMA transfers clears the HTDE flag.
The DSP may program the HTIE bit to cause a host transmit data interrupt when HTDE is set (see
Section 7.4.6.10, "HCSR Transmit-Interrupt Enable (HTIE)—Bit 11"). Data should not be written to the
HTX until HTDE is set in order to prevent overwriting the previous data. HTX is reset to the empty state
when in stop mode and during hardware reset, software reset, and individual reset.
In the 8-bit data transfer mode the most significant byte of the HTX is transmitted; in the 16-bit mode the
two most significant bytes, and in the 24-bit mode all the contents of HTX is transferred.
7.4.3
SHI Host Receive Data FIFO (HRX)—DSP Side
The 24-bit host receive data FIFO (HRX) is a 10-word deep, First-In-First-Out (FIFO) register used for
Host-to-DSP data transfers. The serial data is received via the shift register and then loaded into the HRX.
In the 8-bit data transfer mode, the most significant byte of the shift register is transferred to the HRX (the
other bits are cleared); in the 16-bit mode the two most significant bytes are transferred (the least
significant byte is cleared), and in the 24-bit mode, all 24 bits are transferred to the HRX. The HRX may
be read by the DSP while the FIFO is being loaded from the shift register. Reading all data from HRX
clears the HRNE flag. The HRX may be read by DSP core instructions or by DMA transfers. The HRX
FIFO is reset to the empty state when the chip is in stop mode, and during hardware reset, software reset,
and individual reset.
7.4.4
SHI Slave Address Register (HSAR)—DSP Side
2
The 24-bit slave address register (HSAR) is used when the SHI operates in the I C slave mode and is
ignored in the other operational modes. HSAR holds five bits of the 7-bit slave device address. The SHI
2
also acknowledges the general call address specified by the I C protocol (eight zeroes comprising a 7-bit
address and a R/W bit), but treats any following data bytes as regular data. That is, the SHI does not
differentiate between its dedicated address and the general call address. HSAR cannot be accessed by the
host processor.
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7.4.4.1
HSAR Reserved Bits—Bits 19, 17–0
These bits are reserved. They read as zero and should be written with zero for future compatibility.
2
7.4.4.2
HSAR I C Slave Address (HA[6:3], HA1)—Bits 23–20,18
2
Part of the I C slave device address is stored in the read/write HA[6:3], HA1 bits of HSAR. The full 7-bit
slave device address is formed by combining the HA[6:3], HA1 bits with the HA0 and HA2 pins to obtain
the HA[6:0] slave device address. The full 7-bit slave device address is compared to the received address
2
2
byte whenever an I C master device initiates an I C bus transfer. During hardware reset or software reset,
HA[6:3] = 1011 and HA1 is cleared; this results in a default slave device address of 1011[HA2]0[HA0].
7.4.5
SHI Clock Control Register (HCKR)—DSP Side
The HCKR is a 24-bit read/write register that controls SHI clock generator operation. The HCKR bits
should be modified only while the SHI is in the individual reset state (HEN = 0 in the HCSR).
For proper SHI clock setup, please consult the datasheet. The programmer should not use the combination
HRS = 1 and HDM[7:0] = 00000000, since it may cause synchronization problems and improper operation
(it is an illegal combination).
The HCKR bits are cleared during hardware reset or software reset, except for CPHA, which is set. The
HCKR is not affected by the stop state.
The HCKR bits are described in the following paragraphs.
7.4.5.1
Clock Phase and Polarity (CPHA and CPOL)—Bits 1–0
The Clock Phase (CPHA) bit controls the relationship between the data on the master-in-slave-out (MISO)
and master-out-slave-in (MOSI) pins and the clock produced or received at the SCK pin. The CPOL bit
determines the clock polarity (1 = active-high, 0 = active-low).
The clock phase and polarity should be identical for both the master and slave SPI devices. CPHA and
2
CPOL are functional only when the SHI operates in the SPI mode, and are ignored in the I C mode. The
CPHA bit is set and the CPOL bit is cleared during hardware reset and software reset.
The programmer may select any of four combinations of serial clock (SCK) phase and polarity when
operating in the SPI mode (See Figure 7-6).
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Serial Host Interface Programming Model
SS
SCK (CPOL = 0, CPHA = 0)
SCK (CPOL = 0, CPHA = 1)
SCK (CPOL = 1, CPHA = 0)
SCK (CPOL = 1, CPHA = 1)
MISO/
MOSI
MSB
6
5
4
3
2
1
LSB
Internal Strobe for Data Capture
Figure 7-6 SPI Data-To-Clock Timing Diagram
AA0421
If CPOL is cleared, it produces a steady-state low value at the SCK pin of the master device whenever data
is not being transferred. If the CPOL bit is set, it produces a high value at the SCK pin of the master device
whenever data is not being transferred.
CPHA is used with the CPOL bit to select the desired clock-to-data relationship. The CPHA bit, in general,
selects the clock edge that captures data and allows it to change states. It has its greatest impact on the first
bit transmitted (MSB) in that it does or does not allow a clock transition before the data capture edge.
When the SHI is in slave mode and CPHA = 0, the SS line must be deasserted and asserted by the external
master between each successive word transfer. SS must remain asserted between successive bytes within
a word. The DSP core should write the next data word to HTX when HTDE = 1, clearing HTDE. However,
the data is transferred to the shift register for transmission only when SS is deasserted. HTDE is set when
the data is transferred from HTX to the shift register.
When the SHI is in slave mode and CPHA = 1, the SS line may remain asserted between successive word
transfers. The SS must remain asserted between successive bytes within a word. The DSP core should
write the next data word to HTX when HTDE = 1, clearing HTDE. The HTX data is transferred to the shift
register for transmission as soon as the shift register is empty. HTDE is set when the data is transferred
from HTX to the shift register.
When the SHI is in master mode and CPHA = 0, the DSP core should write the next data word to HTX
when HTDE = 1, clearing HTDE. The data is transferred immediately to the shift register for transmission.
HTDE is set only at the end of the data word transmission.
NOTE
The master is responsible for deasserting and asserting the slave device SS
line between word transmissions.
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When the SHI is in master mode and CPHA = 1, the DSP core should write the next data word to HTX
when HTDE = 1, clearing HTDE. The HTX data is transferred to the shift register for transmission as soon
as the shift register is empty. HTDE is set when the data is transferred from HTX to the shift register.
7.4.5.2
HCKR Prescaler Rate Select (HRS)—Bit 2
The HRS bit controls a prescaler in series with the clock generator divider. This bit is used to extend the
range of the divider when slower clock rates are desired. When HRS is set, the prescaler is bypassed. When
HRS is cleared, the fixed divide-by-eight prescaler is operational. HRS is ignored when the SHI operates
2
in the slave mode, except for I C when HCKFR is set. The HRS bit is cleared during hardware reset and
software reset.
NOTE
Use the equations in the SHI datasheet to determine the value of HRS for
the specific serial clock frequency required.
7.4.5.3
HCKR Divider Modulus Select (HDM[7:0])—Bits 10–3
The HDM[7:0] bits specify the divide ratio of the clock generator divider. A divide ratio between 1 and
256 (HDM[7:0] = $00 to $FF) may be selected. When the SHI operates in the slave mode, the HDM[7:0]
2
bits are ignored (except for I C when HCKFR is set). The HDM[7:0] bits are cleared during hardware reset
and software reset.
NOTE
Use the equations in the SHI datasheet to determine the value of HDM[7:0]
for the specific serial clock frequency required.
7.4.5.4
HCKR Reserved Bits—Bits 23–14, 11
These bits in HCKR are reserved. They are read as zero and should be written with zero for future
compatibility.
7.4.5.5
HCKR Filter Mode (HFM[1:0]) — Bits 13–12
The read/write control bits HFM[1:0] specify the operational mode of the noise reduction filters, as
described in Table 7-3. The filters are designed to eliminate undesired spikes that might occur on the clock
and data-in lines and allow the SHI to operate in noisy environments when required. One filter is located
in the input path of the SCK/SCL line and the other is located in the input path of the data line (i.e., the
2
SDA line when in I C mode, the MISO line when in SPI master mode, and the MOSI line when in SPI
slave mode).
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Table 7-3 SHI Noise Reduction Filter Mode
HFM1
HFM0
Description
0
0
1
1
0
1
0
1
Bypassed (Disabled)
Reserved
Narrow Spike Tolerance
Wide Spike Tolerance
When HFM[1:0] = 00, the filter is bypassed (spikes are not filtered out). This mode is useful when higher
bit-rate transfers are required and the SHI operates in a noise-free environment.
When HFM[1:0] = 10, the narrow-spike-tolerance filter mode is selected. In this mode the filters eliminate
spikes with durations of up to 50ns. This mode is suitable for use in mildly noisy environments and
imposes some limitations on the maximum achievable bit-rate transfer.
When HFM[1:0] = 11, the wide-spike-tolerance filter mode is selected. In this mode the filters eliminate
spikes up to 100 ns. This mode is recommended for use in noisy environments; the bit-rate transfer is
2
strictly limited. The wide-spike- tolerance filter mode is highly recommended for use in I C bus systems
2
as it fully conforms to the I C bus specification and improves noise immunity.
NOTE
HFM[1:0] are cleared during hardware reset and software reset.
After changing the filter bits in the HCKR to a non-bypass mode (HFM[1:0] not equal to ‘00’), the
programmer should wait at least ten times the tolerable spike width before enabling the SHI (setting the
2
HEN bit in the HCSR). Similarly, after changing the HI C bit in the HCSR or the CPOL bit in the HCKR,
while the filter mode bits are in a non-bypass mode (HFM[1:0] not equal to ‘00’), the programmer should
wait at least ten times the tolerable spike width before enabling the SHI (setting HEN in the HCSR).
7.4.6
SHI Control/Status Register (HCSR)—DSP Side
The HCSR is a 24-bit register that controls the SHI operation and reflects its status. The control bits are
read/write. The status bits are read-only. The bits are described in the following paragraphs. When in the
stop state or during individual reset, the HCSR status bits are reset to their hardware-reset state, while the
control bits are not affected.
7.4.6.1
HCSR Host Enable (HEN)—Bit 0
The read/write control bit HEN, when set, enables the SHI. When HEN is cleared, the SHI is disabled (that
is, it is in the individual reset state, see below). The HCKR and the HCSR control bits are not affected when
HEN is cleared. When operating in master mode, HEN should be cleared only when the SHI is idle
(HBUSY = 0). HEN is cleared during hardware reset and software reset.
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7.4.6.1.1
SHI Individual Reset
While the SHI is in the individual reset state, SHI input pins are inhibited, output and bidirectional pins
are disabled (high impedance), the HCSR status bits and the transmit/receive paths are reset to the same
state produced by hardware reset or software reset. The individual reset state is entered following a
one-instruction-cycle delay after clearing HEN.
2
2
7.4.6.2
HCSR I C/SPI Selection (HI C)—Bit 1
2
2
2
The read/write control bit HI C selects whether the SHI operates in the I C or SPI modes. When HI C is
2
2
2
cleared, the SHI operates in the SPI mode. When HI C is set, the SHI operates in the I C mode. HI C
affects the functionality of the SHI pins as described in Section 2, "Signal/Connection Descriptions". It is
recommended that an SHI individual reset be generated (HEN cleared) before changing HI C. HI C is
cleared during hardware reset and software reset.
2
2
7.4.6.3
HCSR Serial Host Interface Mode (HM[1:0])—Bits 3–2
The read/write control bits HM[1:0] select the size of the data words to be transferred, as shown in
Table 7-4. HM[1:0] should be modified only when the SHI is idle (HBUSY = 0). HM[1:0] are cleared
during hardware reset and software reset
.
Table 7-4 SHI Data Size
HM1
HMO
Description
8-bit data
0
0
1
1
0
1
0
1
16-bit data
24-bit data
Reserved
2
7.4.6.4
HCSR I C Clock Freeze (HCKFR)—Bit 4
The read/write control bit HCKFR determines the behavior of the SHI when the SHI is unable to service
2
2
the master request, when operating in the I C slave mode. The HCKFR bit is used only in the I C slave
mode; it is ignored otherwise.
If HCKFR is set, the SHI holds the clock line to GND if it is not ready to send data to the master during a
read transfer or if the input FIFO is full when the master attempts to execute a write transfer. In this way,
the master may detect that the slave is not ready for the requested transfer, without causing an error
condition in the slave. When HCKFR is set for transmit sessions, the SHI clock generator must be
programmed as if to generate the same serial clock as produced by the external master, otherwise
erroneous operation may result. The programmed frequency should be in the range of 1 to 0.75 times the
external clock frequency.
If HCKFR is cleared, any attempt from the master to execute a transfer when the slave is not ready results
in an overrun or underrun error condition.
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It is recommended that an SHI individual reset be generated (HEN cleared) before changing HCKFR.
HCKFR is cleared during hardware reset and software reset.
7.4.6.5
HCSR FIFO-Enable Control (HFIFO)—Bit 5
The read/write control bit HFIFO selects the receive FIFO size. When HFIFO is cleared, the FIFO has one
level. When HFIFO is set, the FIFO has 10 levels. It is recommended that an SHI individual reset be
generated (HEN cleared) before changing HFIFO. HFIFO is cleared during hardware reset and software
reset.
7.4.6.6
HCSR Master Mode (HMST)—Bit 6
The read/write control bit HMST determines the SHI operating mode. If HMST is set, the interface
operates in the master mode. If HMST is cleared, the interface operates in the slave mode. The SHI
2
supports a single-master configuration in both I C and SPI modes.
When configured as an SPI master, the SHI drives the SCK line and controls the direction of the data lines
MOSI and MISO. The SS line must be held deasserted in the SPI master mode; if the SS line is asserted
when the SHI is in SPI master mode, a bus error is generated (the HCSR HBER bit is set—see
2
2
When configured as an I C master, the SHI controls the I C bus by generating start events, clock pulses,
and stop events for transmission and reception of serial data.
It is recommended that an SHI individual reset be generated (HEN cleared) before changing HMST.
HMST is cleared during hardware reset and software reset.
7.4.6.7
HCSR Host-Request Enable (HRQE[1:0])—Bits 8–7
The read/write control bits HRQE[1:0] are used to control the HREQ pin. When HRQE[1:0] are cleared,
the HREQ pin is disabled and held in the high impedance state. If either of HRQE[1:0] are set and the SHI
is in a master mode, the HREQ pin becomes an input controlling SCK: deasserting HREQ suspends SCK.
If either of HRQE[1:0] are set and the SHI is in a slave mode, HREQ becomes an output and its operation
HRQE[1:0] are cleared during hardware reset and software reset.
Table 7-5 HREQ Function In SHI Slave Modes
HRQE1
HRQE0
HREQ Pin Operation
0
0
1
1
0
1
0
1
High impedance
Asserted if IOSR is ready to receive a new word
Asserted if IOSR is ready to transmit a new word
2
I C: Asserted if IOSR is ready to transmit or receive
SPI: Asserted if IOSR is ready to transmit and receive
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7.4.6.8
HCSR Idle (HIDLE)—Bit 9
2
The read/write control/status bit HIDLE is used only in the I C master mode; it is ignored otherwise. It is
only possible to set the HIDLE bit during writes to the HCSR. HIDLE is cleared by writing to HTX. To
ensure correct transmission of the slave device address byte, HIDLE should be set only when HTX is
empty (HTDE = 1). After HIDLE is set, a write to HTX clears HIDLE and causes the generation of a stop
event, a start event, and then the transmission of the eight MSBs of the data as the slave device address
byte. While HIDLE is cleared, data written to HTX is transmitted as is. If the SHI completes transmitting
a word and there is no new data in HTX, the clock is suspended after sampling ACK. If HIDLE is set when
the SHI completes transmitting a word with no new data in HTX, a stop event is generated.
HIDLE determines the acknowledge that the receiver sends after correct reception of a byte. If HIDLE is
cleared, the reception is acknowledged by sending a 0 bit on the SDA line at the ACK clock tick. If HIDLE
is set, the reception is not acknowledged (a 1 bit is sent). It is used to signal an end-of-data to a slave
transmitter by not generating an ACK on the last byte. As a result, the slave transmitter must release the
SDA line to allow the master to generate the stop event. If the SHI completes receiving a word and the
HRX FIFO is full, the clock is suspended before transmitting an ACK. While HIDLE is cleared the bus is
busy, that is, the start event was sent but no stop event was generated. Setting HIDLE causes a stop event
after receiving the current word.
2
HIDLE is set while the SHI is not in the I C master mode, while the chip is in the stop state, and during
hardware reset, software reset and individual reset.
NOTE
Programmers should take care to ensure that all DMA channel service to
HTX is disabled before setting HIDLE.
7.4.6.9
HCSR Bus-Error Interrupt Enable (HBIE)—Bit 10
The read/write control bit HBIE is used to enable the SHI bus-error interrupt. If HBIE is cleared, bus-error
interrupts are disabled, and the HBER status bit must be polled to determine if an SHI bus error occurred.
If both HBIE and HBER are set, the SHI requests an SHI bus-error interrupt service from the interrupt
controller. HBIE is cleared by hardware reset and software reset.
NOTE
Clearing HBIE masks a pending bus-error interrupt only after a one
instruction cycle delay. If HBIE is cleared in a long interrupt service routine,
it is recommended that at least one other instruction separate the instruction
that clears HBIE and the RTI instruction at the end of the interrupt service
routine.
7.4.6.10 HCSR Transmit-Interrupt Enable (HTIE)—Bit 11
The read/write control bit HTIE is used to enable the SHI transmit data interrupts. If HTIE is cleared,
transmit interrupts are disabled, and the HTDE status bit must be polled to determine if HTX is empty. If
both HTIE and HTDE are set and HTUE is cleared, the SHI requests an SHI transmit-data interrupt service
from the interrupt controller. If both HTIE and HTUE are set, the SHI requests an SHI
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transmit-underrun-error interrupt service from the interrupt controller. HTIE is cleared by hardware reset
and software reset.
NOTE
Clearing HTIE masks a pending transmit interrupt only after a one
instruction cycle delay. If HTIE is cleared in a long interrupt service routine,
it is recommended that at least one other instruction separate the instruction
that clears HTIE and the RTI instruction at the end of the interrupt service
routine.
7.4.6.11 HCSR Receive Interrupt Enable (HRIE[1:0])—Bits 13–12
The read/write control bits HRIE[1:0] are used to enable the SHI receive-data interrupts. If HRIE[1:0] are
cleared, receive interrupts are disabled, and the HRNE and HRFF (bits 17 and 19, see below) status bits
must be polled to determine if there is data in the receive FIFO. If HRIE[1:0] are not cleared, receive
interrupts are generated according to Table 7-6. HRIE[1:0] are cleared by hardware and software reset.
Table 7-6 HCSR Receive Interrupt Enable Bits
HRIE[1:0]
Interrupt
Condition
Not applicable
00
01
Disabled
Receive FIFO not empty
Receive Overrun Error
HRNE = 1 and HROE = 0
HROE = 1
10
11
Reserved
Not applicable
Receive FIFO full
HRFF = 1 and HROE = 0
HROE = 1
Receive Overrun Error
NOTE
Clearing HRIE[1:0] masks a pending receive interrupt only after a one
instruction cycle delay. If HRIE[1:0] are cleared in a long interrupt service
routine, it is recommended that at least one other instruction separate the
instruction that clears HRIE[1:0] and the RTI instruction at the end of the
interrupt service routine.
7.4.6.12 HCSR Host Transmit Underrun Error (HTUE)—Bit 14
The read-only status bit HTUE indicates whether a transmit-underrun error occurred. Transmit-underrun
2
errors can occur only when operating in the SPI slave mode or the I C slave mode when HCKFR is cleared.
In a master mode, transmission takes place on demand and no underrun can occur. HTUE is set when both
the shift register and the HTX register are empty and the external master begins reading the next word:
2
•
When operating in the I C mode, HTUE is set in the falling edge of the ACK bit. In this case, the
SHI retransmits the previously transmitted word.
•
When operating in the SPI mode, HTUE is set at the first clock edge if CPHA = 1; it is set at the
assertion of SS if CPHA = 0.
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If a transmit interrupt occurs with HTUE set, the transmit-underrun interrupt vector is generated. If a
transmit interrupt occurs with HTUE cleared, the regular transmit-data interrupt vector is generated.
HTUE is cleared by reading the HCSR and then writing to the HTX register. HTUE is cleared by hardware
reset, software reset, SHI individual reset, and during the stop state.
7.4.6.13 HCSR Host Transmit Data Empty (HTDE)—Bit 15
The read-only status bit HTDE indicates whether the HTX register is empty and can be written by the DSP.
HTDE is set when the data word is transferred from HTX to the shift register, except in SPI master mode
when CPHA = 0 (see HCKR). When in the SPI master mode with CPHA = 0, HTDE is set after the end
of the data word transmission. HTDE is cleared when the DSP writes the HTX either with write
instructions or DMA transfers. HTDE is set by hardware reset, software reset, SHI individual reset, and
during the stop state.
7.4.6.14 HCSR Reserved Bits—Bits 23, 18 and 16
These bits are reserved. They read as zero and should be written with zero for future compatibility.
7.4.6.15 Host Receive FIFO Not Empty (HRNE)—Bit 17
The read-only status bit HRNE indicates that the Host Receive FIFO (HRX) contains at least one data
word. HRNE is set when the FIFO is not empty. HRNE is cleared when HRX is read by the DSP (read
instructions or DMA transfers), reducing the number of words in the FIFO to zero. HRNE is cleared during
hardware reset, software reset, SHI individual reset, and during the stop state.
7.4.6.16 Host Receive FIFO Full (HRFF)—Bit 19
The read-only status bit HRFF indicates, when set, that the Host Receive FIFO (HRX) is full. HRFF is
cleared when HRX is read by the DSP (read instructions or DMA transfers) and at least one place is
available in the FIFO. HRFF is cleared by hardware reset, software reset, SHI individual reset, and during
the stop state.
7.4.6.17 Host Receive Overrun Error (HROE)—Bit 20
The read-only status bit HROE indicates, when set, that a data-receive overrun error has occurred.
2
Receive-overrun errors cannot occur when operating in the I C master mode, because the clock is
2
suspended if the receive FIFO is full; nor can they occur in the I C slave mode when HCKFR is set.
HROE is set when the shift register (IOSR) is filled and ready to transfer the data word to the HRX FIFO
and the FIFO is already full (HRFF is set). When a receive-overrun error occurs, the shift register is not
transferred to the FIFO. If a receive interrupt occurs with HROE set, the receive-overrun interrupt vector
is generated. If a receive interrupt occurs with HROE cleared, the regular receive-data interrupt vector is
generated.
HROE is cleared by reading the HCSR with HROE set, followed by reading HRX. HROE is cleared by
hardware reset, software reset, SHI individual reset, and during the stop state.
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Characteristics Of The SPI Bus
7.4.6.18 Host Bus Error (HBER)—Bit 21
The read-only status bit HBER indicates, when set, that an SHI bus error occurred when operating as a
2
master (HMST set). In I C mode, HBER is set if the transmitter does not receive an acknowledge after a
byte is transferred; then a stop event is generated and transmission is suspended. In SPI mode, HBER is
set if SS is asserted; then transmission is suspended at the end of transmission of the current word. HBER
is cleared only by hardware reset, software reset, SHI individual reset, and during the stop state.
7.4.6.19 HCSR Host Busy (HBUSY)—Bit 22
2
2
The read-only status bit HBUSY indicates that the I C bus is busy (when in the I C mode) or that the SHI
2
itself is busy (when in the SPI mode). When operating in the I C mode, HBUSY is set after the SHI detects
a start event and remains set until a stop event is detected. When operating in the slave SPI mode, HBUSY
is set while SS is asserted. When operating in the master SPI mode, HBUSY is set if the HTX register is
not empty or if the IOSR is not empty. HBUSY is cleared otherwise. HBUSY is cleared by hardware reset,
software reset, SHI individual reset, and during the stop state.
7.5
Characteristics Of The SPI Bus
The SPI bus consists of two serial data lines (MISO and MOSI), a clock line (SCK), and a Slave Select
line (SS). During an SPI transfer, a byte is shifted out one data pin while a different byte is simultaneously
shifted in through a second data pin. It can be viewed as two 8-bit shift registers connected together in a
circular manner, with one shift register on the master side and the other on the slave side. Thus the data
bytes in the master device and slave device are exchanged. The MISO and MOSI data pins are used for
transmitting and receiving serial data. When the SPI is configured as a master, MISO is the master data
input line, and MOSI is the master data output line. When the SPI is configured as a slave device, MISO
is the slave data output line, and MOSI is the slave data input line.
Clock control logic allows a selection of clock polarity and a choice of two fundamentally different
clocking protocols to accommodate most available synchronous serial peripheral devices. When the SPI
is configured as a master, the control bits in the HCKR select the appropriate clock rate, as well as the
desired clock polarity and phase format (see Figure 7-6).
The SS line allows selection of an individual slave SPI device; slave devices that are not selected do not
interfere with SPI bus activity (i.e., they keep their MISO output pin in the high-impedance state). When
the SHI is configured as an SPI master device, the SS line should be held high. If the SS line is driven low
when the SHI is in SPI master mode, a bus error is generated (the HCSR HBER bit is set).
2
7.6
Characteristics Of The I C Bus
2
The I C serial bus consists of two bidirectional lines, one for data signals (SDA) and one for clock signals
(SCL). Both the SDA and SCL lines must be connected to a positive supply voltage via a pull-up resistor.
NOTE
2
In the I C bus specifications, the standard mode (100 kHz clock rate) and a
fast mode (400 kHz clock rate) are defined. The SHI can operate in either
mode.
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2
Characteristics Of The I C Bus
7.6.1
Overview
2
The I C bus protocol must conform to the following rules:
•
•
Data transfer may be initiated only when the bus is not busy.
During data transfer, the data line must remain stable whenever the clock line is high. Changes in
SDA
SCL
Data Line
Change
Stable:
Data Valid
of Data
Allowed
AA0422
2
Figure 7-7 I C Bit Transfer
2
Accordingly, the I C bus protocol defines the following events:
•
•
Bus not busy—Both data and clock lines remain high.
Start data transfer—The start event is defined as a change in the state of the data line, from high
to low, while the clock is high (see Figure 7-8).
•
•
Stop data transfer—The stop event is defined as a change in the state of the data line, from low
to high, while the clock is high (see Figure 7-8).
Data valid—The state of the data line represents valid data when, after a start event, the data line
is stable for the duration of the high period of the clock signal. The data on the line may be changed
during the low period of the clock signal. There is one clock pulse per bit of data.
SDA
SCL
S
P
Start Event
Stop Event
AA0423
2
Figure 7-8 I C Start and Stop Events
Each 8-bit word is followed by one acknowledge bit. This acknowledge bit is a high level put on the bus
by the transmitter when the master device generates an extra acknowledge-related clock pulse. A slave
receiver that is addressed must generate an acknowledge after each byte is received. Also, a master
receiver must generate an acknowledge after the reception of each byte that has been clocked out of the
slave transmitter. The acknowledging device must pull down the SDA line during the acknowledge clock
pulse so that the SDA line is stable low during the high period of the acknowledge-related clock pulse (see
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2
Characteristics Of The I C Bus
Start
Event
Clock Pulse For
Acknowledgment
SCL From
Master Device
1
2
8
9
Data Output
by Transmitter
S
Data Output
by Receiver
AA0424
2
Figure 7-9 Acknowledgment on the I C Bus
A device generating a signal is called a transmitter, and a device receiving a signal is called a receiver. A
device controlling a signal is called a master and devices controlled by the master are called slaves. A
master receiver must signal an end-of-data to the slave transmitter by not generating an acknowledge on
the last byte clocked out of the slave device. In this case the transmitter must leave the data line high to
enable the master to generate the stop event. Handshaking may also be accomplished by using the clock
synchronizing mechanism. Slave devices can hold the SCL line low, after receiving and acknowledging a
byte, to force the master into a wait state until the slave device is ready for the next byte transfer. The SHI
supports this feature when operating as a master device and waits until the slave device releases the SCL
line before proceeding with the data transfer.
7.6.2
I2C Data Transfer Formats
2
I C bus data transfers follow the following process: after the start event, a slave device address is sent. The
address consists of seven address bits and an eighth bit as a data direction bit (R/W). In the data direction
bit, zero indicates a transmission (write), and one indicates a request for data (read). A data transfer is
always terminated by a stop event generated by the master device. However, if the master device still
wishes to communicate on the bus, it can generate another start event, and address another slave device
2
without first generating a stop event (the SHI does not support this feature when operating as an I C master
device). This method is also used to provide indivisible data transfers. Various combinations of read/write
ACK from
Slave Device
ACK from
Slave Device
ACK from
Slave Device
S Slave Address
0
A
First Data Byte
A
Data Byte
A S, P
N = 0 to M
Data Bytes
Start
Bit
R/W
Start or
Stop Bit
AA0425
2
Figure 7-10 I C Bus Protocol For Host Write Cycle
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SHI Programming Considerations
ACK from
Slave Device
ACK from
Master Device
No ACK
from Master Device
S Slave Address
1
A
Data Byte
A
Last Data Byte
1
P
N = 0 to M
Data Bytes
Start
Bit
Stop
Bit
R/W
AA0426
2
Figure 7-11 I C Bus Protocol For Host Read Cycle
NOTE
The first data byte in a write-bus cycle can be used as a user-predefined
control byte (e.g., to determine the location to which the forthcoming data
bytes should be transferred).
7.7
SHI Programming Considerations
2
The SHI implements both SPI and I C bus protocols and can be programmed to operate as a slave device
or a single-master device. Once the operating mode is selected, the SHI may communicate with an external
device by receiving and/or transmitting data. Before changing the SHI operational mode, an SHI
individual reset should be generated by clearing the HEN bit. The following paragraphs describe
programming considerations for each operational mode.
7.7.1
SPI Slave Mode
2
The SPI slave mode is entered by enabling the SHI (HEN=1), selecting the SPI mode (HI C=0), and
selecting the slave mode of operation (HMST=0). The programmer should verify that the CPHA and
CPOL bits (in the HCKR) correspond to the external host clock phase and polarity. Other HCKR bits are
ignored. When configured in the SPI slave mode, the SHI external pins operate as follows:
•
•
•
•
•
SCK/SCL is the SCK serial clock input.
MISO/SDA is the MISO serial data output.
MOSI/HA0 is the MOSI serial data input.
SS/HA2 is the SS slave select input.
HREQ is the Host Request output.
In the SPI slave mode, a receive, transmit, or full-duplex data transfer may be performed. Actually, the
interface performs data receive and transmit simultaneously. The status bits of both receive and transmit
paths are active; however, the programmer may disable undesired interrupts and ignore irrelevant status
bits. It is recommended that an SHI individual reset (HEN cleared) be generated before beginning data
reception in order to reset the HRX FIFO to its initial (empty) state (e.g., when switching from transmit to
receive data).
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SHI Programming Considerations
If a write to HTX occurs, its contents are transferred to IOSR between data word transfers. The IOSR data
is shifted out (via MISO) and received data is shifted in (via MOSI). The DSP may write HTX with either
DSP instructions or DMA transfers if the HTDE status bit is set. If no writes to HTX occur, the contents
of HTX are not transferred to IOSR, so the data shifted out when receiving is the data present in the IOSR
at the time. The HRX FIFO contains valid receive data, which the DSP can read with either DSP
instructions or DMA transfers (if the HRNE status bit is set).
The HREQ output pin, if enabled for receive (HRQE[1:0] = 01), is asserted when the IOSR is ready for
receive and the HRX FIFO is not full; this operation guarantees that the next received data word is stored
in the FIFO. The HREQ output pin, if enabled for transmit (HRQE[1:0] = 10), is asserted when the IOSR
is loaded from HTX with a new data word to transfer. If HREQ is enabled for both transmit and receive
(HRQE[1:0] = 11), it is asserted when the receive and transmit conditions are both true. HREQ is
deasserted at the first clock pulse of the next data word transfer. The HREQ line may be used to interrupt
the external master device. Connecting the HREQ line between two SHI-equipped DSPs, one operating as
an SPI master device and the other as an SPI slave device, enables full hardware handshaking if operating
with CPHA = 1.
The SS line should be kept asserted during a data word transfer. If the SS line is deasserted before the end
of the data word transfer, the transfer is aborted and the received data word is lost.
7.7.2
SPI Master Mode
2
The SPI master mode is initiated by enabling the SHI (HEN = 1), selecting the SPI mode (HI C = 0), and
selecting the master mode of operation (HMST = 1). Before enabling the SHI as an SPI master device, the
programmer should program the proper clock rate, phase and polarity in HCKR. When configured in the
SPI master mode, the SHI external pins operate as follows:
•
•
•
•
•
SCK/SCL is the SCK serial clock output.
MISO/SDA is the MISO serial data input.
MOSI/HA0 is the MOSI serial data output.
SS/HA2 is the SS input. It should be kept deasserted (high) for proper operation.
HREQ is the Host Request input.
The external slave device can be selected either by using external logic or by activating a GPIO pin
connected to its SS pin. However, the SS input pin of the SPI master device should be held deasserted
(high) for proper operation. If the SPI master device SS pin is asserted, the host bus error status bit (HBER)
is set. If the HBIE bit is also set, the SHI issues a request to the DSP interrupt controller to service the SHI
bus error interrupt.
In the SPI master mode the DSP must write to HTX to receive, transmit or perform a full-duplex data
transfer. Actually, the interface performs simultaneous data receive and transmit. The status bits of both
receive and transmit paths are active; however, the programmer may disable undesired interrupts and
ignore irrelevant status bits. In a data transfer, the HTX is transferred to IOSR, clock pulses are generated,
the IOSR data is shifted out (via MOSI) and received data is shifted in (via MISO). The DSP programmer
may write HTX (if the HTDE status bit is set) with either DSP instructions or DMA transfers to initiate
the transfer of the next word. The HRX FIFO contains valid receive data, which the DSP can read with
either DSP instructions or DMA transfers, if the HRNE status bit is set.
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SHI Programming Considerations
It is recommended that an SHI individual reset (HEN cleared) be generated before beginning data
reception in order to reset the receive FIFO to its initial (empty) state (e.g., when switching from transmit
to receive data).
The HREQ input pin is ignored by the SPI master device if the HRQE[1:0] bits are cleared, and considered
if any of them is set. When asserted by the slave device, HREQ indicates that the external slave device is
ready for the next data transfer. As a result, the SPI master sends clock pulses for the full data word transfer.
HREQ is deasserted by the external slave device at the first clock pulse of the new data transfer. When
deasserted, HREQ prevents the clock generation of the next data word transfer until it is asserted again.
Connecting the HREQ line between two SHI-equipped DSPs, one operating as an SPI master device and
the other as an SPI slave device, enables full hardware handshaking if CPHA = 1. For CPHA = 0, HREQ
should be disabled by clearing HRQE[1:0].
7.7.3
I2C Slave Mode
2
2
2
The I C slave mode is entered by enabling the SHI (HEN=1), selecting the I C mode (HI C=1), and
selecting the slave mode of operation (HMST=0). In this operational mode the contents of HCKR are
2
ignored. When configured in the I C slave mode, the SHI external pins operate as follows:
•
•
•
•
•
SCK/SCL is the SCL serial clock input.
MISO/SDA is the SDA open drain serial data line.
MOSI/HA0 is the HA0 slave device address input.
SS/HA2 is the HA2 slave device address input.
HREQ is the Host Request output.
2
When the SHI is enabled and configured in the I C slave mode, the SHI controller inspects the SDA and
SCL lines to detect a start event. Upon detection of the start event, the SHI receives the slave device
address byte and enables the slave device address recognition unit. If the slave device address byte was not
identified as its personal address, the SHI controller fails to acknowledge this byte by not driving low the
SDA line at the ninth clock pulse (ACK = 1). However, it continues to poll the SDA and SCL lines to detect
a new start event. If the personal slave device address was correctly identified, the slave device address
byte is acknowledged (ACK = 0 is sent) and a receive/transmit session is initiated according to the eighth
bit of the received slave device address byte (i.e., the R/W bit).
2
7.7.3.1
Receive Data in I C Slave Mode
A receive session is initiated when the personal slave device address has been correctly identified and the
R/W bit of the received slave device address byte has been cleared. Following a receive initiation, data in
the SDA line is shifted into IOSR MSB first. Following each received byte, an acknowledge (ACK = 0) is
2
sent at the ninth clock pulse via the SDA line. Data is acknowledged bytewise, as required by the I C bus
protocol, and is transferred to the HRX FIFO when the complete word (according to HM[1:0]) is filled
2
into IOSR. It is the responsibility of the programmer to select the correct number of bytes in an I C frame
so that they fit in a complete number of words. For this purpose, the slave device address byte does not
count as part of the data; therefore, it is treated separately.
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SHI Programming Considerations
In a receive session, only the receive path is enabled and HTX to IOSR transfers are inhibited. The HRX
FIFO contains valid data, which may be read by the DSP with either DSP instructions or DMA transfers
(if the HRNE status bit is set).
If HCKFR is cleared, when the HRX FIFO is full and IOSR is filled, an overrun error occurs and the HROE
status bit is set. In this case, the last received byte is not acknowledged (ACK=1 is sent) and the word in
2
the IOSR is not transferred to the HRX FIFO. This may inform the external I C master device of the
2
occurrence of an overrun error on the slave side. Consequently the I C master device may terminate this
session by generating a stop event.
If HCKFR is set, when the HRX FIFO is full the SHI holds the clock line to GND not letting the master
device write to IOSR, which eliminates the possibility of reaching the overrun condition.
The HREQ output pin, if enabled for receive (HRQE[1:0] = 01), is asserted when the IOSR is ready to
receive and the HRX FIFO is not full; this operation guarantees that the next received data word is stored
in the FIFO. HREQ is deasserted at the first clock pulse of the next received word. The HREQ line may
2
be used to interrupt the external I C master device. Connecting the HREQ line between two SHI-equipped
2
2
DSPs, one operating as an I C master device and the other as an I C slave device, enables full hardware
handshaking.
2
7.7.3.2
Transmit Data In I C Slave Mode
A transmit session is initiated when the personal slave device address has been correctly identified and the
R/W bit of the received slave device address byte has been set. Following a transmit initiation, the IOSR
is loaded from HTX (assuming the latter was not empty) and its contents are shifted out, MSB first, on the
SDA line. Following each transmitted byte, the SHI controller samples the SDA line at the ninth clock
pulse, and inspects the ACK status. If the transmitted byte was acknowledged (ACK = 0), the SHI
controller continues and transmits the next byte. However, if it was not acknowledged (ACK = 1), the
transmit session is stopped and the SDA line is released. Consequently, the external master device may
generate a stop event in order to terminate the session.
HTX contents are transferred to IOSR when the complete word (according to HM[1:0]) has been shifted
2
out. It is, therefore, the responsibility of the programmer to select the correct number of bytes in an I C
frame so that they fit in a complete number of words. For this purpose, the slave device address byte does
not count as part of the data; therefore, it is treated separately.
In a transmit session, only the transmit path is enabled and the IOSR-to-HRX FIFO transfers are inhibited.
When the HTX transfers its valid data word to IOSR, the HTDE status bit is set and the DSP may write a
new data word to HTX with either DSP instructions or DMA transfers.
If HCKFR is cleared and both IOSR and HTX are empty when the master device attempts a transmit
session, an underrun condition occurs, setting the HTUE status bit, and the previous word is retransmitted.
If HCKFR is set and both IOSR and HTX are empty when the master device attempts a transmit session,
the SHI holds the clock line to GND to avoid an underrun condition.
The HREQ output pin, if enabled for transmit (HRQE[1:0] = 10), is asserted when HTX is transferred to
IOSR for transmission. When asserted, HREQ indicates that the slave device is ready to transmit the next
data word. HREQ is deasserted at the first clock pulse of the next transmitted data word. The HREQ line
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SHI Programming Considerations
2
may be used to interrupt the external I C master device. Connecting the HREQ line between two
2
2
SHI-equipped DSPs, one operating as an I C master device and the other as an I C slave device, enables
full hardware handshaking.
7.7.4
I2C Master Mode
2
2
2
The I C master mode is entered by enabling the SHI (HEN=1), selecting the I C mode (HI C=1) and
2
selecting the master mode of operation (HMST=1). Before enabling the SHI as an I C master, the
programmer should program the appropriate clock rate in HCKR.
2
When configured in the I C master mode, the SHI external pins operate as follows:
•
•
•
•
•
SCK/SCL is the SCL open drain serial clock output.
MISO/SDA is the SDA open drain serial data line.
MOSI/HA0 is the HA0 slave device address input.
SS/HA2 is the HA2 slave device address input.
HREQ is the Host Request input.
2
In the I C master mode, a data transfer session is always initiated by the DSP by writing to the HTX
register when HIDLE is set. This condition ensures that the data byte written to HTX is interpreted as being
a slave address byte. This data byte must specify the slave device address to be selected and the requested
data transfer direction.
NOTE
The slave address byte should be located in the high portion of the data
word, whereas the middle and low portions are ignored. Only one byte (the
slave address byte) is shifted out, independent of the word length defined by
the HM[1:0] bits.
In order for the DSP to initiate a data transfer the following actions are to be performed:
•
•
The DSP tests the HIDLE status bit.
If the HIDLE status bit is set, the DSP writes the slave device address and the R/W bit to the most
significant byte of HTX.
•
•
The SHI generates a start event.
The SHI transmits one byte only, internally samples the R/W direction bit (last bit), and
accordingly initiates a receive or transmit session.
•
The SHI inspects the SDA level at the ninth clock pulse to determine the ACK value. If
acknowledged (ACK = 0), it starts its receive or transmit session according to the sampled R/W
value. If not acknowledged (ACK = 1), the HBER status bit in HCSR is set, which causes an SHI
Bus Error interrupt request if HBIE is set, and a stop event is generated.
2
The HREQ input pin is ignored by the I C master device if HRQE[1:0] are cleared, and considered if either
of them is set. When asserted, HREQ indicates that the external slave device is ready for the next data
2
transfer. As a result, the I C master device sends clock pulses for the full data word transfer. HREQ is
deasserted by the external slave device at the first clock pulse of the next data transfer. When deasserted,
HREQ prevents the clock generation of the next data word transfer until it is asserted again. Connecting
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SHI Programming Considerations
2
the HREQ line between two SHI-equipped DSPs, one operating as an I C master device and the other as
2
an I C slave device, enables full hardware handshaking.
2
7.7.4.1
Receive Data in I C Master Mode
A receive session is initiated if the R/W direction bit of the transmitted slave device address byte is set.
Following a receive initiation, data in the SDA line is shifted into IOSR MSB first. Following each
received byte, an acknowledge (ACK = 0) is sent at the ninth clock pulse via the SDA line if the HIDLE
2
control bit is cleared. Data is acknowledged bytewise, as required by the I C bus protocol, and is
transferred to the HRX FIFO when the complete word (according to HM[1:0]) is filled into IOSR. It is the
2
responsibility of the programmer to select the correct number of bytes in an I C frame so that they fit in a
complete number of words. For this purpose, the slave device address byte does not count as part of the
data; therefore, it is treated separately.
2
If the I C slave transmitter is acknowledged, it should transmit the next data byte. In order to terminate the
receive session, the programmer should set the HIDLE bit at the last required data word. As a result, the
last byte of the next received data word is not acknowledged, the slave transmitter releases the SDA line,
and the SHI generates the stop event and terminates the session.
In a receive session, only the receive path is enabled and the HTX-to-IOSR transfers are inhibited. If the
HRNE status bit is set, the HRX FIFO contains valid data, which may be read by the DSP with either DSP
instructions or DMA transfers. When the HRX FIFO is full, the SHI suspends the serial clock just before
acknowledge. In this case, the clock is reactivated when the FIFO is read (the SHI gives an ACK = 0 and
proceeds receiving).
2
7.7.4.2
Transmit Data In I C Master Mode
A transmit session is initiated if the R/W direction bit of the transmitted slave device address byte is
cleared. Following a transmit initiation, the IOSR is loaded from HTX (assuming HTX is not empty) and
its contents are shifted out, MSB-first, on the SDA line. Following each transmitted byte, the SHI
controller samples the SDA line at the ninth clock pulse, and inspects the ACK status. If the transmitted
byte was acknowledged (ACK=0), the SHI controller continues transmitting the next byte. However, if it
was not acknowledged (ACK=1), the HBER status bit is set to inform the DSP side that a bus error (or
2
overrun, or any other exception in the slave device) has occurred. Consequently, the I C master device
generates a stop event and terminates the session.
HTX contents are transferred to the IOSR when the complete word (according to HM[1:0]) has been
shifted out. It is, therefore, the responsibility of the programmer to select the right number of bytes in an
2
I C frame so that they fit in a complete number of words. Remember that for this purpose, the slave device
address byte does not count as part of the data.
In a transmit session, only the transmit path is enabled and the IOSR-to-HRX FIFO transfers are inhibited.
When the HTX transfers its valid data word to the IOSR, the HTDE status bit is set and the DSP may write
a new data word to HTX with either DSP instructions or DMA transfers. If both IOSR and HTX are empty,
the SHI suspends the serial clock until new data is written into HTX (when the SHI proceeds with the
transmit session) or HIDLE is set (the SHI reactivates the clock to generate the stop event and terminate
the transmit session).
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SHI Programming Considerations
7.7.5
SHI Operation During DSP Stop
The SHI operation cannot continue when the DSP is in the stop state, because no DSP clocks are active.
While the DSP is in the stop state, the SHI remains in the individual reset state.
While in the individual reset state the following is true:
2
•
•
•
If the SHI was operating in the I C mode, the SHI signals are disabled (high impedance state).
If the SHI was operating in the SPI mode, the SHI signals are not affected.
The HCSR status bits and the transmit/receive paths are reset to the same state produced by
hardware reset or software reset.
•
The HCSR and HCKR control bits are not affected.
NOTE
It is recommended that the SHI be disabled before entering the stop state.
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SHI Programming Considerations
NOTES
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8 Enhanced Serial AUDIO Interface (ESAI)
8.1
Introduction
The Enhanced Serial Audio Interface (ESAI) provides a full-duplex serial port for serial communication
with a variety of serial devices including one or more industry-standard codecs, other DSPs,
microprocessors, and peripherals which implement the Freescale SPI serial protocol. The ESAI consists
of independent transmitter and receiver sections, each section with its own clock generator. It is a superset
of the 56300 Family ESSI peripheral and of the 56000 Family SAI peripheral.
NOTE
The DSP56366 has two ESAI modules. This section describes the ESAI,
and Section 9 describes the ESAI_1. The ESAI and ESAI_1 share 4 data
pins. This is described in the ESAI_1 section.
transfers are synchronized to a clock. Additional synchronization signals are used to delineate the word
frames. The normal mode of operation is used to transfer data at a periodic rate, one word per period. The
network mode is similar in that it is also intended for periodic transfers; however, it supports up to 32
words (time slots) per period. This mode can be used to build time division multiplexed (TDM) networks.
In contrast, the on-demand mode is intended for non-periodic transfers of data and to transfer data serially
at high speed when the data becomes available. This mode offers a subset of the SPI protocol.
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Introduction
GDB DDB
TX0
Shift Register
TX1
RSMA
RSMB
SDO0 [PC11]
TSMA
TSMB
SDO1 [PC10]
Shift Register
TX2
RCCR
RCR
SDO2/SDI3 [PC9]
Shift Register
RX3
TCCR
TCR
TX3
SDO3/SDI2 [PC8]
SDO4/SDI1 [PC7]
SDO5/SDI0 [PC6]
SAICR
SAISR
Shift Register
RX2
TX4
TSR
Shift Register
RX1
Clock / Frame Sync
Generators
and
TX5
RCLK
Control Logic
Shift Register
RX0
TCLK
Figure 8-1 ESAI Block Diagram
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ESAI Data and Control Pins
8.2
ESAI Data and Control Pins
Three to twelve pins are required for operation, depending on the operating mode selected and the number
of transmitters and receivers enabled. The SDO0 and SDO1 pins are used by transmitters 0 and 1 only. The
SDO2/SDI3, SDO3/SDI2, SDO4/SDI1, and SDO5/SDI0 pins are shared by transmitters 2 to 5 with
receivers 0 to 3. The actual mode of operation is selected under software control. All transmitters operate
fully synchronized under control of the same transmitter clock signals. All receivers operate fully
synchronized under control of the same receiver clock signals.
8.2.1
Serial Transmit 0 Data Pin (SDO0)
SDO0 is used for transmitting data from the TX0 serial transmit shift register. SDO0 is an output when
data is being transmitted from the TX0 shift register. In the on-demand mode with an internally generated
bit clock, the SDO0 pin becomes high impedance for a full clock period after the last data bit has been
transmitted, assuming another data word does not follow immediately. If a data word follows immediately,
there is no high-impedance interval.
SDO0 may be programmed as a general-purpose I/O pin (PC11) when the ESAI SDO0 function is not
being used.
8.2.2
Serial Transmit 1 Data Pin (SDO1)
SDO1 is used for transmitting data from the TX1 serial transmit shift register. SDO1 is an output when
data is being transmitted from the TX1 shift register. In the on-demand mode with an internally generated
bit clock, the SDO1 pin becomes high impedance for a full clock period after the last data bit has been
transmitted, assuming another data word does not follow immediately. If a data word follows immediately,
there is no high-impedance interval.
SDO1 may be programmed as a general-purpose I/O pin (PC10) when the ESAI SDO1 function is not
being used.
8.2.3
Serial Transmit 2/Receive 3 Data Pin (SDO2/SDI3)
SDO2/SDI3 is used as the SDO2 for transmitting data from the TX2 serial transmit shift register when
programmed as a transmitter pin, or as the SDI3 signal for receiving serial data to the RX3 serial receive
shift register when programmed as a receiver pin. SDO2/SDI3 is an input when data is being received by
the RX3 shift register. SDO2/SDI3 is an output when data is being transmitted from the TX2 shift register.
In the on-demand mode with an internally generated bit clock, the SDO2/SDI3 pin becomes high
impedance for a full clock period after the last data bit has been transmitted, assuming another data word
does not follow immediately. If a data word follows immediately, there is no high-impedance interval.
SDO2/SDI3 may be programmed as a general-purpose I/O pin (PC9) when the ESAI SDO2 and SDI3
functions are not being used.
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8.2.4
Serial Transmit 3/Receive 2 Data Pin (SDO3/SDI2)
SDO3/SDI2 is used as the SDO3 signal for transmitting data from the TX3 serial transmit shift register
when programmed as a transmitter pin, or as the SDI2 signal for receiving serial data to the RX2 serial
receive shift register when programmed as a receiver pin. SDO3/SDI2 is an input when data is being
received by the RX2 shift register. SDO3/SDI2 is an output when data is being transmitted from the TX3
shift register. In the on-demand mode with an internally generated bit clock, the SDO3/SDI2 pin becomes
high impedance for a full clock period after the last data bit has been transmitted, assuming another data
word does not follow immediately. If a data word follows immediately, there is no high-impedance
interval.
SDO3/SDI2 may be programmed as a general-purpose I/O pin (PC8) when the ESAI SDO3 and SDI2
functions are not being used.
8.2.5
Serial Transmit 4/Receive 1 Data Pin (SDO4/SDI1)
SDO4/SDI1 is used as the SDO4 signal for transmitting data from the TX4 serial transmit shift register
when programmed as transmitter pin, or as the SDI1 signal for receiving serial data to the RX1 serial
receive shift register when programmed as a receiver pin. SDO4/SDI1 is an input when data is being
received by the RX1 shift register. SDO4/SDI1 is an output when data is being transmitted from the TX4
shift register. In the on-demand mode with an internally generated bit clock, the SDO4/SDI1 pin becomes
high impedance for a full clock period after the last data bit has been transmitted, assuming another data
word does not follow immediately. If a data word follows immediately, there is no high-impedance
interval.
SDO4/SDI1 may be programmed as a general-purpose I/O pin (PC7) when the ESAI SDO4 and SDI1
functions are not being used.
8.2.6
Serial Transmit 5/Receive 0 Data Pin (SDO5/SDI0)
SDO5/SDI0 is used as the SDO5 signal for transmitting data from the TX5 serial transmit shift register
when programmed as transmitter pin, or as the SDI0 signal for receiving serial data to the RX0 serial shift
register when programmed as a receiver pin. SDO5/SDI0 is an input when data is being received by the
RX0 shift register. SDO5/SDI0 is an output when data is being transmitted from the TX5 shift register. In
the on-demand mode with an internally generated bit clock, the SDO5/SDI0 pin becomes high impedance
for a full clock period after the last data bit has been transmitted, assuming another data word does not
follow immediately. If a data word follows immediately, there is no high-impedance interval.
SDO5/SDI0 may be programmed as a general-purpose I/O pin (PC6) when the ESAI SDO5 and SDI0
functions are not being used
8.2.7
Receiver Serial Clock (SCKR)
SCKR is a bidirectional pin providing the receivers serial bit clock for the ESAI interface. The direction
of this pin is determined by the RCKD bit in the RCCR register.The SCKR operates as a clock input or
output used by all the enabled receivers in the asynchronous mode (SYN=0), or as serial flag 0 pin in the
synchronous mode (SYN=1).
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When this pin is configured as serial flag pin, its direction is determined by the RCKD bit in the RCCR
register. When configured as the output flag OF0, this pin reflects the value of the OF0 bit in the SAICR
register, and the data in the OF0 bit shows up at the pin synchronized to the frame sync being used by the
transmitter and receiver sections. When this pin is configured as the input flag IF0, the data value at the
pin is stored in the IF0 bit in the SAISR register, synchronized by the frame sync in normal mode or the
slot in network mode.
SCKR may be programmed as a general-purpose I/O pin (PC0) when the ESAI SCKR function is not being
used.
NOTE
Although the external ESAI serial clock can be independent of and
asynchronous to the DSP system clock, the DSP clock frequency must be at
least three times the external ESAI serial clock frequency and each ESAI
serial clock phase must exceed the minimum of 1.5 DSP clock periods.
Table 8-1 Receiver Clock Sources (asynchronous mode only)
Receiver
RHCKD
RFSD
RCKD
Bit Clock
Source
OUTPUTS
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
SCKR
HCKR
SCKR
HCKR
SCKR
INT
SCKR
SCKR
SCKR
SCKR
FSR
FSR
HCKR
HCKR
HCKR
HCKR
SCKR
INT
FSR
FSR
8.2.8
Transmitter Serial Clock (SCKT)
SCKT is a bidirectional pin providing the transmitters serial bit clock for the ESAI interface. The direction
of this pin is determined by the TCKD bit in the TCCR register. The SCKT is a clock input or output used
by all the enabled transmitters in the asynchronous mode (SYN=0) or by all the enabled transmitters and
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Table 8-2 Transmitter Clock Sources
Transmitter
THCKD
TFSD
TCKD
Bit Clock
Source
OUTPUTS
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
SCKT
HCKT
SCKT
HCKT
SCKT
INT
SCKT
SCKT
SCKT
SCKT
FST
FST
HCKT
HCKT
HCKT
HCKT
SCKT
INT
FST
FST
SCKT may be programmed as a general-purpose I/O pin (PC3) when the ESAI SCKT function is not being
used.
NOTE
Although the external ESAI serial clock can be independent of and
asynchronous to the DSP system clock, the DSP clock frequency must be at
least three times the external ESAI serial clock frequency and each ESAI
serial clock phase must exceed the minimum of 1.5 DSP clock periods.
8.2.9
Frame Sync for Receiver (FSR)
FSR is a bidirectional pin providing the receivers frame sync signal for the ESAI interface. The direction
of this pin is determined by the RFSD bit in RCR register. In the asynchronous mode (SYN=0), the FSR
pin operates as the frame sync input or output used by all the enabled receivers. In the synchronous mode
(SYN=1), it operates as either the serial flag 1 pin (TEBE=0), or as the transmitter external buffer enable
When this pin is configured as serial flag pin, its direction is determined by the RFSD bit in the RCCR
register. When configured as the output flag OF1, this pin reflects the value of the OF1 bit in the SAICR
register, and the data in the OF1 bit shows up at the pin synchronized to the frame sync being used by the
transmitter and receiver sections. When configured as the input flag IF1, the data value at the pin is stored
in the IF1 bit in the SAISR register, synchronized by the frame sync in normal mode or the slot in network
mode.
FSR may be programmed as a general-purpose I/O pin (PC1) when the ESAI FSR function is not being
used.
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8.2.10 Frame Sync for Transmitter (FST)
FST is a bidirectional pin providing the frame sync for both the transmitters and receivers in the
synchronous mode (SYN=1) and for the transmitters only in asynchronous mode (SYN=0) (see Table 8-2).
The direction of this pin is determined by the TFSD bit in the TCR register. When configured as an output,
this pin is the internally generated frame sync signal. When configured as an input, this pin receives an
external frame sync signal for the transmitters (and the receivers in synchronous mode).
FST may be programmed as a general-purpose I/O pin (PC4) when the ESAI FST function is not being
used.
8.2.11 High Frequency Clock for Transmitter (HCKT)
HCKT is a bidirectional pin providing the transmitters high frequency clock for the ESAI interface. The
direction of this pin is determined by the THCKD bit in the TCCR register. In the asynchronous mode
(SYN=0), the HCKT pin operates as the high frequency clock input or output used by all enabled
transmitters. In the synchronous mode (SYN=1), it operates as the high frequency clock input or output
used by all enabled transmitters and receivers. When programmed as input this pin is used as an alternative
high frequency clock source to the ESAI transmitter rather than the DSP main clock. When programmed
as output it can serve as a high frequency sample clock (to external DACs for example) or as an additional
HCKT may be programmed as a general-purpose I/O pin (PC5) when the ESAI HCKT function is not
being used.
8.2.12 High Frequency Clock for Receiver (HCKR)
HCKR is a bidirectional pin providing the receivers high frequency clock for the ESAI interface. The
direction of this pin is determined by the RHCKD bit in the RCCR register. In the asynchronous mode
(SYN=0), the HCKR pin operates as the high frequency clock input or output used by all the enabled
receivers. In the synchronous mode (SYN=1), it operates as the serial flag 2 pin. For further information
When this pin is configured as serial flag pin, its direction is determined by the RHCKD bit in the RCCR
register. When configured as the output flag OF2, this pin reflects the value of the OF2 bit in the SAICR
register, and the data in the OF2 bit shows up at the pin synchronized to the frame sync being used by the
transmitter and receiver sections. When configured as the input flag IF2, the data value at the pin is stored
in the IF2 bit in the SAISR register, synchronized by the frame sync in normal mode or the slot in network
mode.
HCKR may be programmed as a general-purpose I/O pin (PC2) when the ESAI HCKR function is not
being used.
8.3
ESAI Programming Model
The ESAI can be viewed as five control registers, one status register, six transmit data registers, four
receive data registers, two transmit slot mask registers, two receive slot mask registers and a
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special-purpose time slot register. The following paragraphs give detailed descriptions and operations of
each bit in the ESAI registers.
The ESAI pins can also function as GPIO pins (Port C), described in Section 8.5, "GPIO - Pins and
8.3.1
ESAI Transmitter Clock Control Register (TCCR)
The read/write Transmitter Clock Control Register (TCCR) controls the ESAI transmitter clock generator
bit and frame sync rates, the bit clock and high frequency clock sources and the directions of the HCKT,
FST and SCKT signals. (See Figure 8-2). In the synchronous mode (SYN=1), the bit clock defined for the
transmitter determines the receiver bit clock as well. TCCR also controls the number of words per frame
for the serial data.
11
10
9
8
7
6
5
4
3
2
1
0
X:$FFFFB6
TDC2 TDC1 TDC0 TPSR TPM7 TPM6 TPM5 TPM4 TPM3 TPM2 TPM1 TPM0
23
22
21
20
19
18
17
16
15
14
13
12
THCKD TFSD TCKD THCKP TFSP TCKP TFP3
TFP2
TFP1
TFP0 TDC4 TDC3
Figure 8-2 TCCR Register
Hardware and software reset clear all the bits of the TCCR register.
The TCCR control bits are described in the following paragraphs.
8.3.1.1
TCCR Transmit Prescale Modulus Select (TPM7–TPM0) - Bits 0–7
The TPM7–TPM0 bits specify the divide ratio of the prescale divider in the ESAI transmitter clock
generator. A divide ratio from 1 to 256 (TPM[7:0]=$00 to $FF) may be selected. The bit clock output is
available at the transmit serial bit clock (SCKT) pin of the DSP. The bit clock output is also available
internally for use as the bit clock to shift the transmit and receive shift registers. The ESAI transmit clock
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RHCKD=1
RHCKD=0
PRESCALE
DIVIDE BY
DIVIDER
DIVIDE BY
1
DIVIDER
DIVIDE BY
1
F
OSC
DIVIDE
BY 2
1
OR
TO DIVIDE
TO DIVIDE
RPSR
RPM0 - RPM7
RFP0 - RFP3
HCKR
RHCKD
FLAG0 OUT
(SYNC MODE)
FLAG0 IN
(SYNC MODE)
INTERNAL BIT CLOCK
RSWS4-RSWS0
RX WORD
CLOCK
RX WORD
LENGTH DIVIDER
SYN=1
SYN=0
SCKR
RX SHIFT REGISTER
TSWS4-TSWS0
RCLOCK
TCLOCK
SYN=0
SYN=1
RCKD
INTERNAL BIT CLOCK
TX WORD
LENGTH DIVIDER
TX WORD
CLOCK
SCKT
TCKD
THCKD
TX SHIFT REGISTER
HCKT
TFP0 - TFP3
TPSR
TPM0 - TPM7
THCKD=0
DIVIDER
DIVIDE BY
1
TO DIVIDE
BY 16
PRESCALE
DIVIDE BY
1
OR
DIVIDE BY
DIVIDER
DIVIDE BY
1
TO DIVIDE
BY 256
DIVIDE
BY 2
F
OSC
THCKD=1
Notes:
1. F
is the DSP56300 Core internal clock frequency.
OSC
Figure 8-3 ESAI Clock Generator Functional Block Diagram
8.3.1.2
TCCR Transmit Prescaler Range (TPSR) - Bit 8
The TPSR bit controls a fixed divide-by-eight prescaler in series with the variable prescaler. This bit is
used to extend the range of the prescaler for those cases where a slower bit clock is desired. When TPSR
is set, the fixed prescaler is bypassed. When TPSR is cleared, the fixed divide-by-eight prescaler is
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minimum internally generated bit clock frequency is Fosc/(2 x 8 x 256)=Fosc/4096.
NOTE
Do not use the combination TPSR=1 and TPM7-TPM0=$00, which causes
synchronization problems when using the internal DSP clock as source
(TCKD=1 or THCKD=1).
8.3.1.3
TCCR Tx Frame Rate Divider Control (TDC4–TDC0) - Bits 9–13
The TDC4–TDC0 bits control the divide ratio for the programmable frame rate dividers used to generate
the transmitter frame clocks.
In network mode, this ratio may be interpreted as the number of words per frame minus one. The divide
ratio may range from 2 to 32 (TDC[4:0]=00001 to 11111) for network mode. A divide ratio of one
(TDC[4:0]=00000) in network mode is a special case (on-demand mode).
In normal mode, this ratio determines the word transfer rate. The divide ratio may range from 1 to 32
(TDC[4:0]=00000 to 11111) for normal mode. In normal mode, a divide ratio of 1 (TDC[4:0]=00000)
provides continuous periodic data word transfers. A bit-length frame sync (TFSL=1) must be used in this
case.
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RDC0 - RDC4
RFSL
RX WORD
CLOCK
RECEIVER
FRAME RATE
DIVIDER
INTERNAL RX FRAME CLOCK
SYNC
TYPE
RFSD
FSR
SYN=0
SYN=1
RFSD=1
SYN=0
RECEIVE
CONTROL
LOGIC
RECEIVE
FRAME SYNC
RFSD=0
SYN=1
FLAG1 IN
(SYNC MODE)
FLAG1OUT
(SYNC MODE)
TDC0 - TDC4
TFSL
TFSD
TX WORD
CLOCK
TRANSMITTER
FRAME RATE
DIVIDER
INTERNAL TX FRAME CLOCK
SYNC
TYPE
FST
TRANSMIT
CONTROL
LOGIC
TRANSMIT
FRAME SYNC
Figure 8-4 ESAI Frame Sync Generator Functional Block Diagram
8.3.1.4
TCCR Tx High Frequency Clock Divider (TFP3-TFP0) - Bits 14–17
The TFP3–TFP0 bits control the divide ratio of the transmitter high frequency clock to the transmitter
serial bit clock when the source of the high frequency clock and the bit clock is the internal DSP clock.
When the HCKT input is being driven from an external high frequency clock, the TFP3-TFP0 bits specify
an additional division ratio in the clock divider chain. See Table 8-3 for the specification of the divide ratio.
Table 8-3 Transmitter High Frequency Clock Divider
TFP3-TFP0
Divide Ratio
$0
$1
$2
$3
...
1
2
3
4
...
16
$F
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8.3.1.5
TCCR Transmit Clock Polarity (TCKP) - Bit 18
The Transmitter Clock Polarity (TCKP) bit controls on which bit clock edge data and frame sync are
clocked out and latched in. If TCKP is cleared the data and the frame sync are clocked out on the rising
edge of the transmit bit clock and latched in on the falling edge of the transmit bit clock. If TCKP is set
the falling edge of the transmit clock is used to clock the data out and frame sync and the rising edge of
the transmit clock is used to latch the data and frame sync in.
8.3.1.6
TCCR Transmit Frame Sync Polarity (TFSP) - Bit 19
The Transmitter Frame Sync Polarity (TFSP) bit determines the polarity of the transmit frame sync signal.
When TFSP is cleared, the frame sync signal polarity is positive (i.e the frame start is indicated by a high
level on the frame sync pin). When TFSP is set, the frame sync signal polarity is negative (i.e the frame
start is indicated by a low level on the frame sync pin).
8.3.1.7
TCCR Transmit High Frequency Clock Polarity (THCKP) - Bit 20
The Transmitter High Frequency Clock Polarity (THCKP) bit controls on which bit clock edge data and
frame sync are clocked out and latched in. If THCKP is cleared the data and the frame sync are clocked
out on the rising edge of the transmit bit clock and latched in on the falling edge of the transmit bit clock.
If THCKP is set the falling edge of the transmit clock is used to clock the data out and frame sync and the
rising edge of the transmit clock is used to latch the data and frame sync in.
8.3.1.8
TCCR Transmit Clock Source Direction (TCKD) - Bit 21
The Transmitter Clock Source Direction (TCKD) bit selects the source of the clock signal used to clock
the transmit shift registers in the asynchronous mode (SYN=0) and the transmit shift registers and the
receive shift registers in the synchronous mode (SYN=1). When TCKD is set, the internal clock source
becomes the bit clock for the transmit shift registers and word length divider and is the output on the SCKT
pin. When TCKD is cleared, the clock source is external; the internal clock generator is disconnected from
8.3.1.9
TCCR Transmit Frame Sync Signal Direction (TFSD) - Bit 22
TFSD controls the direction of the FST pin. When TFSD is cleared, FST is an input; when TFSD is set,
8.3.1.10 TCCR Transmit High Frequency Clock Direction (THCKD) - Bit 23
THCKD controls the direction of the HCKT pin. When THCKD is cleared, HCKT is an input; when
8.3.2
ESAI Transmit Control Register (TCR)
The read/write Transmit Control Register (TCR) controls the ESAI transmitter section. Interrupt enable
bits for the transmitter section are provided in this control register. Operating modes are also selected in
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.
11
10
9
8
7
6
5
4
3
2
1
0
X:$FFFFB5
TSWS1 TSWS0 TMOD1 TMOD0 TWA TSHFD TE5
TE4
TE3
TE2
TE1
TE0
23
22
21
20
19
18
17
16
15
14
13
12
TLIE
TIE
TEDIE TEIE
TPR
PADC TFSR TFSL TSWS4 TSWS3 TSWS2
Reserved bit - read as zero; should be written with zero for future compatibility.
Figure 8-5 TCR Register
Hardware and software reset clear all the bits in the TCR register.
The TCR bits are described in the following paragraphs.
8.3.2.1
TCR ESAI Transmit 0 Enable (TE0) - Bit 0
TE0 enables the transfer of data from TX0 to the transmit shift register #0. When TE0 is set and a frame
sync is detected, the transmit #0 portion of the ESAI is enabled for that frame. When TE0 is cleared, the
transmitter #0 is disabled after completing transmission of data currently in the ESAI transmit shift
register. The SDO0 output is tri-stated, and any data present in TX0 is not transmitted (i.e., data can be
written to TX0 with TE0 cleared; but data is not transferred to the transmit shift register #0).
The normal mode transmit enable sequence is to write data to one or more transmit data registers before
setting TEx. The normal transmit disable sequence is to clear TEx, TIE and TEIE after TDE equals one.
In the network mode, the operation of clearing TE0 and setting it again disables the transmitter #0 after
completing transmission of the current data word until the beginning of the next frame. During that time
period, the SDO0 pin remains in the high-impedance state.The on-demand mode transmit enable sequence
can be the same as the normal mode, or TE0 can be left enabled.
8.3.2.2
TCR ESAI Transmit 1 Enable (TE1) - Bit 1
TE1 enables the transfer of data from TX1 to the transmit shift register #1. When TE1 is set and a frame
sync is detected, the transmit #1 portion of the ESAI is enabled for that frame. When TE1 is cleared, the
transmitter #1 is disabled after completing transmission of data currently in the ESAI transmit shift
register. The SDO1 output is tri-stated, and any data present in TX1 is not transmitted (i.e., data can be
written to TX1 with TE1 cleared; but data is not transferred to the transmit shift register #1).
The normal mode transmit enable sequence is to write data to one or more transmit data registers before
setting TEx. The normal transmit disable sequence is to clear TEx, TIE and TEIE after TDE equals one.
In the network mode, the operation of clearing TE1 and setting it again disables the transmitter #1 after
completing transmission of the current data word until the beginning of the next frame. During that time
period, the SDO1 pin remains in the high-impedance state. The on-demand mode transmit enable sequence
can be the same as the normal mode, or TE1 can be left enabled.
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8.3.2.3
TCR ESAI Transmit 2 Enable (TE2) - Bit 2
TE2 enables the transfer of data from TX2 to the transmit shift register #2. When TE2 is set and a frame
sync is detected, the transmit #2 portion of the ESAI is enabled for that frame. When TE2 is cleared, the
transmitter #2 is disabled after completing transmission of data currently in the ESAI transmit shift
register. Data can be written to TX2 when TE2 is cleared but the data is not transferred to the transmit shift
register #2.
The SDO2/SDI3 pin is the data input pin for RX3 if TE2 is cleared and RE3 in the RCR register is set. If
both RE3 and TE2 are cleared the transmitter and receiver are disabled, and the pin is tri-stated. Both RE3
and TE2 should not be set at the same time.
The normal mode transmit enable sequence is to write data to one or more transmit data registers before
setting TEx. The normal transmit disable sequence is to clear TEx, TIE and TEIE after TDE equals one.
In the network mode, the operation of clearing TE2 and setting it again disables the transmitter #2 after
completing transmission of the current data word until the beginning of the next frame. During that time
period, the SDO2/SDI3 pin remains in the high-impedance state. The on-demand mode transmit enable
sequence can be the same as the normal mode, or TE2 can be left enabled.
8.3.2.4
TCR ESAI Transmit 3 Enable (TE3) - Bit 3
TE3 enables the transfer of data from TX3 to the transmit shift register #3. When TE3 is set and a frame
sync is detected, the transmit #3 portion of the ESAI is enabled for that frame. When TE3 is cleared, the
transmitter #3 is disabled after completing transmission of data currently in the ESAI transmit shift
register. Data can be written to TX3 when TE3 is cleared but the data is not transferred to the transmit shift
register #3.
The SDO3/SDI2 pin is the data input pin for RX2 if TE3 is cleared and RE2 in the RCR register is set. If
both RE2 and TE3 are cleared the transmitter and receiver are disabled, and the pin is tri-stated. Both RE2
and TE3 should not be set at the same time.
The normal mode transmit enable sequence is to write data to one or more transmit data registers before
setting TEx. The normal transmit disable sequence is to clear TEx, TIE and TEIE after TDE equals one.
In the network mode, the operation of clearing TE3 and setting it again disables the transmitter #3 after
completing transmission of the current data word until the beginning of the next frame. During that time
period, the SDO3/SDI2 pin remains in the high-impedance state. The on-demand mode transmit enable
sequence can be the same as the normal mode, or TE3 can be left enabled.
8.3.2.5
TCR ESAI Transmit 4 Enable (TE4) - Bit 4
TE4 enables the transfer of data from TX4 to the transmit shift register #4. When TE4 is set and a frame
sync is detected, the transmit #4 portion of the ESAI is enabled for that frame. When TE4 is cleared, the
transmitter #4 is disabled after completing transmission of data currently in the ESAI transmit shift
register. Data can be written to TX4 when TE4 is cleared but the data is not transferred to the transmit shift
register #4.
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The SDO4/SDI1 pin is the data input pin for RX1 if TE4 is cleared and RE1 in the RCR register is set. If
both RE1 and TE4 are cleared the transmitter and receiver are disabled, and the pin is tri-stated. Both RE1
and TE4 should not be set at the same time.
The normal mode transmit enable sequence is to write data to one or more transmit data registers before
setting TEx. The normal transmit disable sequence is to clear TEx, TIE and TEIE after TDE equals one.
In the network mode, the operation of clearing TE4 and setting it again disables the transmitter #4 after
completing transmission of the current data word until the beginning of the next frame. During that time
period, the SDO4/SDI1 pin remains in the high-impedance state. The on-demand mode transmit enable
sequence can be the same as the normal mode, or TE4 can be left enabled.
8.3.2.6
TCR ESAI Transmit 5 Enable (TE5) - Bit 5
TE5 enables the transfer of data from TX5 to the transmit shift register #5. When TE5 is set and a frame
sync is detected, the transmit #5 portion of the ESAI is enabled for that frame. When TE5 is cleared, the
transmitter #5 is disabled after completing transmission of data currently in the ESAI transmit shift
register. Data can be written to TX5 when TE5 is cleared but the data is not transferred to the transmit shift
register #5.
The SDO5/SDI0 pin is the data input pin for RX0 if TE5 is cleared and RE0 in the RCR register is set. If
both RE0 and TE5 are cleared the transmitter and receiver are disabled, and the pin is tri-stated. Both RE0
and TE5 should not be set at the same time.
The normal mode transmit enable sequence is to write data to one or more transmit data registers before
setting TEx. The normal transmit disable sequence is to clear TEx, TIE and TEIE after TDE equals one.
In the network mode, the operation of clearing TE5 and setting it again disables the transmitter #5 after
completing transmission of the current data word until the beginning of the next frame. During that time
period, the SDO5/SDI0 pin remains in the high-impedance state. The on-demand mode transmit enable
sequence can be the same as the normal mode, or TE5 can be left enabled.
8.3.2.7
TCR Transmit Shift Direction (TSHFD) - Bit 6
The TSHFD bit causes the transmit shift registers to shift data out MSB first when TSHFD equals zero or
8.3.2.8
TCR Transmit Word Alignment Control (TWA) - Bit 7
The Transmitter Word Alignment Control (TWA) bit defines the alignment of the data word in relation to
the slot. This is relevant for the cases where the word length is shorter than the slot length. If TWA is
cleared, the data word is left-aligned in the slot frame during transmission. If TWA is set, the data word is
right-aligned in the slot frame during transmission.
Since the data word is shorter than the slot length, the data word is extended until achieving the slot length,
according to the following rule:
1. If the data word is left-aligned (TWA=0), and zero padding is disabled (PADC=0), then the last data
bit is repeated after the data word has been transmitted. If zero padding is enabled (PADC=1),
zeroes are transmitted after the data word has been transmitted.
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2. If the data word is right-aligned (TWA=1), and zero padding is disabled (PADC=0), then the first
data bit is repeated before the transmission of the data word. If zero padding is enabled (PADC=1),
zeroes are transmitted before the transmission of the data word.
8.3.2.9
TCR Transmit Network Mode Control (TMOD1-TMOD0) - Bits 8-9
The TMOD1 and TMOD0 bits are used to define the network mode of ESAI transmitters according to
Table 8-4. In the normal mode, the frame rate divider determines the word transfer rate – one word is
transferred per frame sync during the frame sync time slot, as shown in Figure 8-6. In network mode, it is
possible to transfer a word for every time slot, as shown in Figure 8-6. For more details, see Section 8.4,
In order to comply with AC-97 specifications, TSWS4-TSWS0 should be set to 00011 (20-bit slot, 20-bit
word length), TFSL and TFSR should be cleared, and TDC4-TDC0 should be set to $0C (13 words in
frame). If TMOD[1:0]=$11 and the above recommendations are followed, the first slot and word will be
16 bits long, and the next 12 slots and words will be 20 bits long, as required by the AC97 protocol.
Table 8-4 Transmit Network Mode Selection
TMOD1
TMOD0
TDC4-TDC0
$0-$1F
$0
Transmitter Network Mode
Normal Mode
0
0
0
1
1
0
1
1
0
1
On-Demand Mode
Network Mode
Reserved
$1-$1F
X
$0C
AC97
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8.3.2.10 TCR Tx Slot and Word Length Select (TSWS4-TSWS0) - Bits 10-14
The TSWS4-TSWS0 bits are used to select the length of the slot and the length of the data words being
transferred via the ESAI. The word length must be equal to or shorter than the slot length. The possible
combinations are shown in Table 8-5. See also the ESAI data path programming model in Figure 8-13 and
Table 8-5 ESAI Transmit Slot and Word Length Selection
TSWS4
TSWS3
TSWS2
TSWS1
TSWS0
SLOT LENGTH
WORD LENGTH
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
1
1
1
0
1
0
0
0
1
0
0
1
1
0
0
0
1
1
0
1
1
0
0
1
1
0
1
0
0
1
0
1
0
1
0
0
1
0
1
1
0
1
0
1
1
0
0
0
0
0
1
0
0
1
1
0
0
1
1
1
0
0
1
1
1
0
0
1
0
1
0
0
1
0
1
0
1
0
1
0
0
1
0
1
1
8
8
12
8
12
8
16
20
12
16
8
12
16
20
8
24
12
16
20
24
8
32
12
16
20
24
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Table 8-5 ESAI Transmit Slot and Word Length Selection (continued)
TSWS4
TSWS3
TSWS2
TSWS1
TSWS0
SLOT LENGTH
WORD LENGTH
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
0
1
0
0
1
1
1
0
0
0
1
1
1
1
0
1
0
1
1
0
1
1
0
0
1
0
1
1
0
0
1
1
0
1
0
1
Reserved
8.3.2.11 TCR Transmit Frame Sync Length (TFSL) - Bit 15
The TFSL bit selects the length of frame sync to be generated or recognized. If TFSL is cleared, a
word-length frame sync is selected. If TFSL is set, a 1-bit clock period frame sync is selected. See
Figure 8-7 for examples of frame length selection.
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WORD LENGTH: TFSL=0, RFSL=0
SERIAL CLOCK
RX, TX FRAME SYNC
RX, TX SERIAL DATA
DATA
DATA
NOTE: Frame sync occurs while data is valid.
ONE BIT LENGTH: TFSL=1, RFSL=1
SERIAL CLOCK
RX, TX FRAME SYNC
RX, TX SERIAL DATA
DATA
DATA
NOTE: Frame sync occurs for one bit time preceding the data.
MIXED FRAME LENGTH: TFSL=1, RFSL=0
SERIAL CLOCK
RX FRAME SYNC
RX SERIAL DATA
DATA
DATA
DATA
DATA
TX FRAME SYNC
TX SERIAL DATA
MIXED FRAME LENGTH: TFSL=0, RFSL=1
SERIAL CLOCK
RX FRAME SYNC
RX SERIAL DATA
DATA
DATA
DATA
DATA
TX FRAME SYNC
TX SERIAL DATA
Figure 8-7 Frame Length Selection
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8.3.2.12 TCR Transmit Frame Sync Relative Timing (TFSR) - Bit 16
TFSR determines the relative timing of the transmit frame sync signal as referred to the serial data lines,
for a word length frame sync only (TFSL=0). When TFSR is cleared the word length frame sync occurs
together with the first bit of the data word of the first slot. When TFSR is set the word length frame sync
starts one serial clock cycle earlier (i.e together with the last bit of the previous data word).
8.3.2.13 TCR Transmit Zero Padding Control (PADC) - Bit 17
When PADC is cleared, zero padding is disabled. When PADC is set, zero padding is enabled. PADC, in
conjunction with the TWA control bit, determines the way that padding is done for operating modes where
the word length is less than the slot length. See the TWA bit description in Section 8.3.2.8, "TCR Transmit
Since the data word is shorter than the slot length, the data word is extended until achieving the slot length,
according to the following rules:
1. If the data word is left-aligned (TWA=0), and zero padding is disabled (PADC=0), then the last data
bit is repeated after the data word has been transmitted. If zero padding is enabled (PADC=1),
zeroes are transmitted after the data word has been transmitted.
2. If the data word is right-aligned (TWA=1), and zero padding is disabled (PADC=0), then the first
data bit is repeated before the transmission of the data word. If zero padding is enabled (PADC=1),
zeroes are transmitted before the transmission of the data word.
8.3.2.14 TCR Reserved Bit - Bits 18
This bit is reserved. It reads as zero, and it should be written with zero for future compatibility.
8.3.2.15 TCR Transmit Section Personal Reset (TPR) - Bit 19
The TPR control bit is used to put the transmitter section of the ESAI in the personal reset state. The
receiver section is not affected. When TPR is cleared, the transmitter section may operate normally. When
TPR is set, the transmitter section enters the personal reset state immediately. When in the personal reset
state, the status bits are reset to the same state as after hardware reset. The control bits are not affected by
the personal reset state. The transmitter data pins are tri-stated while in the personal reset state; if a stable
logic level is desired, the transmitter data pins should be defined as GPIO outputs, or external pull-up or
pull-down resistors should be used. The transmitter clock outputs drive zeroes while in the personal reset
state. Note that to leave the personal reset state by clearing TPR, the procedure described in Section 8.6,
"ESAI Initialization Examples" should be followed.
8.3.2.16 TCR Transmit Exception Interrupt Enable (TEIE) - Bit 20
When TEIE is set, the DSP is interrupted when both TDE and TUE in the SAISR status register are set.
When TEIE is cleared, this interrupt is disabled. Reading the SAISR status register followed by writing to
all the data registers of the enabled transmitters clears TUE, thus clearing the pending interrupt.
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8.3.2.17 TCR Transmit Even Slot Data Interrupt Enable (TEDIE) - Bit 21
The TEDIE control bit is used to enable the transmit even slot data interrupts. If TEDIE is set, the transmit
even slot data interrupts are enabled. If TEDIE is cleared, the transmit even slot data interrupts are
disabled. A transmit even slot data interrupt request is generated if TEDIE is set and the TEDE status flag
in the SAISR status register is set. Even time slots are all even-numbered time slots (0, 2, 4, etc.) when
operating in network mode. The zero time slot in the frame is marked by the frame sync signal and is
considered to be even. Writing data to all the data registers of the enabled transmitters or to TSR clears the
TEDE flag, thus servicing the interrupt.
Transmit interrupts with exception have higher priority than transmit even slot data interrupts, therefore if
exception occurs (TUE is set) and TEIE is set, the ESAI requests an ESAI transmit data with exception
interrupt from the interrupt controller.
8.3.2.18 TCR Transmit Interrupt Enable (TIE) - Bit 22
The DSP is interrupted when TIE and the TDE flag in the SAISR status register are set. When TIE is
cleared, this interrupt is disabled. Writing data to all the data registers of the enabled transmitters or to TSR
clears TDE, thus clearing the interrupt.
Transmit interrupts with exception have higher priority than normal transmit data interrupts, therefore if
exception occurs (TUE is set) and TEIE is set, the ESAI requests an ESAI transmit data with exception
interrupt from the interrupt controller.
8.3.2.19 TCR Transmit Last Slot Interrupt Enable (TLIE) - Bit 23
TLIE enables an interrupt at the beginning of last slot of a frame in network mode. When TLIE is set the
DSP is interrupted at the start of the last slot in a frame in network mode regardless of the transmit mask
register setting. When TLIE is cleared the transmit last slot interrupt is disabled. TLIE is disabled when
TDC[4:0]=$00000 (on-demand mode). The use of the transmit last slot interrupt is described in
8.3.3
ESAI Receive Clock Control Register (RCCR)
The read/write Receive Clock Control Register (RCCR) controls the ESAI receiver clock generator bit and
frame sync rates, word length, and number of words per frame for the serial data. The RCCR control bits
11
10
9
8
7
6
5
4
3
2
1
0
X:$FFFFB8
RDC2 RDC1 RDC0 RPSR RPM7 RPM6 RPM5 RPM4 RPM3 RPM2 RPM1 RPM0
23
22
21
20
19
18
17
16
15
14
13
12
RHCKD RFSD RCKD RHCKP RFSP RCKP RFP3 RFP2 RFP1 RFP0 RDC4 RDC3
Figure 8-8 RCCR Register
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Hardware and software reset clear all the bits of the RCCR register.
8.3.3.1 RCCR Receiver Prescale Modulus Select (RPM7–RPM0) - Bits 7–0
The RPM7–RPM0 bits specify the divide ratio of the prescale divider in the ESAI receiver clock generator.
A divide ratio from 1 to 256 (RPM[7:0]=$00 to $FF) may be selected. The bit clock output is available at
the receiver serial bit clock (SCKR) pin of the DSP. The bit clock output is also available internally for use
as the bit clock to shift the receive shift registers. The ESAI receive clock generator functional diagram is
8.3.3.2
RCCR Receiver Prescaler Range (RPSR) - Bit 8
The RPSR controls a fixed divide-by-eight prescaler in series with the variable prescaler. This bit is used
to extend the range of the prescaler for those cases where a slower bit clock is desired. When RPSR is set,
the fixed prescaler is bypassed. When RPSR is cleared, the fixed divide-by-eight prescaler is operational
(see Figure 8-3). The maximum internally generated bit clock frequency is Fosc/4, the minimum internally
generated bit clock frequency is Fosc/(2 x 8 x 256)=Fosc/4096.
NOTE
Do not use the combination RPSR=1 and RPM7-RPM0=$00, which causes
synchronization problems when using the internal DSP clock as source
(RHCKD=1 or RCKD=1).
8.3.3.3
RCCR Rx Frame Rate Divider Control (RDC4–RDC0) - Bits 9–13
The RDC4–RDC0 bits control the divide ratio for the programmable frame rate dividers used to generate
the receiver frame clocks.
In network mode, this ratio may be interpreted as the number of words per frame minus one. The divide
ratio may range from 2 to 32 (RDC[4:0]=00001 to 11111) for network mode. A divide ratio of one
(RDC[4:0]=00000) in network mode is a special case (on-demand mode).
In normal mode, this ratio determines the word transfer rate. The divide ratio may range from 1 to 32
(RDC[4:0]=00000 to 11111) for normal mode. In normal mode, a divide ratio of one (RDC[4:0]=00000)
provides continuous periodic data word transfers. A bit-length frame sync (RFSL=1) must be used in this
case.
8.3.3.4
RCCR Rx High Frequency Clock Divider (RFP3-RFP0) - Bits 14-17
The RFP3–RFP0 bits control the divide ratio of the receiver high frequency clock to the receiver serial bit
clock when the source of the receiver high frequency clock and the bit clock is the internal DSP clock.
When the HCKR input is being driven from an external high frequency clock, the RFP3-RFP0 bits specify
an additional division ration in the clock divider chain. See Table 8-6 for the specification of the divide
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Table 8-6 Receiver High Frequency Clock Divider
RFP3-RFP0
Divide Ratio
$0
$1
$2
$3
...
1
2
3
4
...
16
$F
8.3.3.5
RCCR Receiver Clock Polarity (RCKP) - Bit 18
The Receiver Clock Polarity (RCKP) bit controls on which bit clock edge data and frame sync are clocked
out and latched in. If RCKP is cleared the data and the frame sync are clocked out on the rising edge of the
receive bit clock and the frame sync is latched in on the falling edge of the receive bit clock. If RCKP is
set the falling edge of the receive clock is used to clock the data and frame sync out and the rising edge of
the receive clock is used to latch the frame sync in.
8.3.3.6
RCCR Receiver Frame Sync Polarity (RFSP) - Bit 19
The Receiver Frame Sync Polarity (RFSP) determines the polarity of the receive frame sync signal. When
RFSP is cleared the frame sync signal polarity is positive (i.e the frame start is indicated by a high level
on the frame sync pin). When RFSP is set the frame sync signal polarity is negative (i.e the frame start is
indicated by a low level on the frame sync pin).
8.3.3.7
RCCR Receiver High Frequency Clock Polarity (RHCKP) - Bit 20
The Receiver High Frequency Clock Polarity (RHCKP) bit controls on which bit clock edge data and
frame sync are clocked out and latched in. If RHCKP is cleared the data and the frame sync are clocked
out on the rising edge of the receive bit clock and the frame sync is latched in on the falling edge of the
receive bit clock. If RHCKP is set the falling edge of the receive clock is used to clock the data and frame
sync out and the rising edge of the receive clock is used to latch the frame sync in.
8.3.3.8
RCCR Receiver Clock Source Direction (RCKD) - Bit 21
The Receiver Clock Source Direction (RCKD) bit selects the source of the clock signal used to clock the
receive shift register in the asynchronous mode (SYN=0) and the IF0/OF0 flag direction in the
synchronous mode (SYN=1).
In the asynchronous mode when RCKD is set, the internal clock source becomes the bit clock for the
receive shift registers and word length divider, and is the output on the SCKR pin. In the asynchronous
mode when RCKD is cleared, the clock source is external; the internal clock generator is disconnected
from the SCKR pin, and an external clock source may drive this pin.
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In the synchronous mode when RCKD is set, the SCKR pin becomes the OF0 output flag. If RCKD is
.
Table 8-7 SCKR Pin Definition Table
Control Bits
SCKR PIN
SYN
RCKD
0
0
1
1
0
1
0
1
SCKR input
SCKR output
IF0
OF0
8.3.3.9
RCCR Receiver Frame Sync Signal Direction (RFSD) - Bit 22
The Receiver Frame Sync Signal Direction (RFSD) bit selects the source of the receiver frame sync signal
when in the asynchronous mode (SYN=0), and the IF1/OF1/Transmitter Buffer Enable flag direction in
the synchronous mode (SYN=1).
In the asynchronous mode when RFSD is set, the internal clock generator becomes the source of the
receiver frame sync, and is the output on the FSR pin. In the asynchronous mode when RFSD is cleared,
the receiver frame sync source is external; the internal clock generator is disconnected from the FSR pin,
and an external clock source may drive this pin.
In the synchronous mode when RFSD is set, the FSR pin becomes the OF1 output flag or the Transmitter
Buffer Enable, according to the TEBE control bit. If RFSD is cleared, then the FSR pin becomes the IF1
Table 8-8 FSR Pin Definition Table
Control Bits
FSR Pin
SYN
TEBE
RFSD
0
0
1
1
1
1
X
X
0
0
1
1
0
1
0
1
0
1
FSR input
FSR output
IF1
OF1
reserved
Transmitter Buffer Enable
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8.3.3.10 RCCR Receiver High Frequency Clock Direction (RHCKD) - Bit 23
The Receiver High Frequency Clock Direction (RHCKD) bit selects the source of the receiver high
frequency clock when in the asynchronous mode (SYN=0), and the IF2/OF2 flag direction in the
synchronous mode (SYN=1).
In the asynchronous mode when RHCKD is set, the internal clock generator becomes the source of the
receiver high frequency clock, and is the output on the HCKR pin. In the asynchronous mode when
RHCKD is cleared, the receiver high frequency clock source is external; the internal clock generator is
disconnected from the HCKR pin, and an external clock source may drive this pin.
When RHCKD is cleared, HCKR is an input; when RHCKD is set, HCKR is an output.
In the synchronous mode when RHCKD is set, the HCKR pin becomes the OF2 output flag. If RHCKD
Table 8-9 HCKR Pin Definition Table
Control Bits
HCKR PIN
SYN
RHCKD
0
0
1
1
0
1
0
1
HCKR input
HCKR output
IF2
OF2
8.3.4
ESAI Receive Control Register (RCR)
The read/write Receive Control Register (RCR) controls the ESAI receiver section. Interrupt enable bits
for the receivers are provided in this control register. The receivers are enabled in this register (0,1,2 or 3
receivers can be enabled) if the input data pin is not used by a transmitter. Operating modes are also
selected in this register.
11
10
9
8
7
6
5
4
3
2
1
0
X:$FFFFB7
RSWS1 RSWS0 RMOD RMOD RWA RSHFD
RE3
RE2
RE1
RE0
23
22
21
20
19
18
17
16
15
14
13
12
RLIE
RIE
REDIE REIE
RPR
RFSR RFSL RSWS4 RSWS3 RSWS2
Reserved bit - read as zero; should be written with zero for future compatibility.
Figure 8-9 RCR Register
Hardware and software reset clear all the bits in the RCR register.
The ESAI RCR bits are described in the following paragraphs.
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8.3.4.1
RCR ESAI Receiver 0 Enable (RE0) - Bit 0
When RE0 is set and TE5 is cleared, the ESAI receiver 0 is enabled and samples data at the SDO5/SDI0
pin. TX5 and RX0 should not be enabled at the same time (RE0=1 and TE5=1). When RE0 is cleared,
receiver 0 is disabled by inhibiting data transfer into RX0. If this bit is cleared while receiving a data word,
the remainder of the word is shifted in and transferred to the RX0 data register.
If RE0 is set while some of the other receivers are already in operation, the first data word received in RX0
will be invalid and must be discarded.
8.3.4.2
RCR ESAI Receiver 1 Enable (RE1) - Bit 1
When RE1 is set and TE4 is cleared, the ESAI receiver 1 is enabled and samples data at the SDO4/SDI1
pin. TX4 and RX1 should not be enabled at the same time (RE1=1 and TE4=1). When RE1 is cleared,
receiver 1 is disabled by inhibiting data transfer into RX1. If this bit is cleared while receiving a data word,
the remainder of the word is shifted in and transferred to the RX1 data register.
If RE1 is set while some of the other receivers are already in operation, the first data word received in RX1
will be invalid and must be discarded.
8.3.4.3
RCR ESAI Receiver 2 Enable (RE2) - Bit 2
When RE2 is set and TE3 is cleared, the ESAI receiver 2 is enabled and samples data at the SDO3/SDI2
pin. TX3 and RX2 should not be enabled at the same time (RE2=1 and TE3=1). When RE2 is cleared,
receiver 2 is disabled by inhibiting data transfer into RX2. If this bit is cleared while receiving a data word,
the remainder of the word is shifted in and transferred to the RX2 data register.
If RE2 is set while some of the other receivers are already in operation, the first data word received in RX2
will be invalid and must be discarded.
8.3.4.4
RCR ESAI Receiver 3 Enable (RE3) - Bit 3
When RE3 is set and TE2 is cleared, the ESAI receiver 3 is enabled and samples data at the SDO2/SDI3
pin. TX2 and RX3 should not be enabled at the same time (RE3=1 and TE2=1). When RE3 is cleared,
receiver 3 is disabled by inhibiting data transfer into RX3. If this bit is cleared while receiving a data word,
the remainder of the word is shifted in and transferred to the RX3 data register.
If RE3 is set while some of the other receivers are already in operation, the first data word received in RX3
will be invalid and must be discarded.
8.3.4.5
RCR Reserved Bits - Bits 4-5, 17-18
These bits are reserved. They read as zero, and they should be written with zero for future compatibility.
8.3.4.6
RCR Receiver Shift Direction (RSHFD) - Bit 6
The RSHFD bit causes the receiver shift registers to shift data in MSB first when RSHFD is cleared or
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8.3.4.7
RCR Receiver Word Alignment Control (RWA) - Bit 7
The Receiver Word Alignment Control (RWA) bit defines the alignment of the data word in relation to the
slot. This is relevant for the cases where the word length is shorter than the slot length. If RWA is cleared,
the data word is assumed to be left-aligned in the slot frame. If RWA is set, the data word is assumed to be
right-aligned in the slot frame.
If the data word is shorter than the slot length, the data bits which are not in the data word field are ignored.
For data word lengths of less than 24 bits, the data word is right-extended with zeroes before being stored
in the receive data registers.
8.3.4.8
RCR Receiver Network Mode Control (RMOD1-RMOD0) - Bits 8-9
The RMOD1 and RMOD0 bits are used to define the network mode of the ESAI receivers according to
Table 8-10. In the normal mode, the frame rate divider determines the word transfer rate – one word is
transferred per frame sync during the frame sync time slot, as shown in Figure 8-6. In network mode, it is
possible to transfer a word for every time slot, as shown in Figure 8-6. For more details, see Section 8.4,
In order to comply with AC-97 specifications, RSWS4-RSWS0 should be set to 00011 (20-bit slot, 20-bit
word), RFSL and RFSR should be cleared, and RDC4-RDC0 should be set to $0C (13 words in frame).
Table 8-10 ESAI Receive Network Mode Selection
RMOD1
RMOD0
RDC4-RDC0
$0-$1F
$0
Receiver Network Mode
Normal Mode
On-Demand Mode
Network Mode
Reserved
0
0
0
1
1
0
1
1
0
1
$1-$1F
X
$0C
AC97
8.3.4.9
RCR Receiver Slot and Word Select (RSWS4-RSWS0) - Bits 10-14
The RSWS4-RSWS0 bits are used to select the length of the slot and the length of the data words being
received via the ESAI. The word length must be equal to or shorter than the slot length. The possible
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Table 8-11 ESAI Receive Slot and Word Length Selection
RSWS4
RSWS3
RSWS2
RSWS1
RSWS0
SLOT LENGTH
WORD LENGTH
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
1
1
1
0
1
0
0
0
1
0
0
1
1
0
0
0
1
1
0
1
1
0
0
1
1
0
1
0
0
1
0
1
0
1
0
0
1
0
1
1
0
1
0
1
1
0
0
0
0
0
1
0
0
1
1
0
0
1
1
1
0
0
1
1
1
0
0
1
0
1
0
0
1
0
1
0
1
0
1
0
0
1
0
1
1
8
8
12
8
12
8
16
20
12
16
8
12
16
20
8
24
12
16
20
24
8
32
12
16
20
24
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Table 8-11 ESAI Receive Slot and Word Length Selection (continued)
RSWS4
RSWS3
RSWS2
RSWS1
RSWS0
SLOT LENGTH
WORD LENGTH
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
0
1
0
0
1
1
1
0
0
0
1
1
1
1
0
1
0
1
1
0
1
1
0
0
1
0
1
1
0
0
1
1
0
1
0
1
Reserved
8.3.4.10 RCR Receiver Frame Sync Length (RFSL) - Bit 15
The RFSL bit selects the length of the receive frame sync to be generated or recognized. If RFSL is cleared,
a word-length frame sync is selected. If RFSL is set, a 1-bit clock period frame sync is selected. See
Figure 8-7 for examples of frame length selection.
8.3.4.11 RCR Receiver Frame Sync Relative Timing (RFSR) - Bit 16
RFSR determines the relative timing of the receive frame sync signal as referred to the serial data lines,
for a word length frame sync only. When RFSR is cleared the word length frame sync occurs together with
the first bit of the data word of the first slot. When RFSR is set the word length frame sync starts one serial
clock cycle earlier (i.e. together with the last bit of the previous data word).
8.3.4.12 RCR Receiver Section Personal Reset (RPR) - Bit 19
The RPR control bit is used to put the receiver section of the ESAI in the personal reset state. The
transmitter section is not affected. When RPR is cleared, the receiver section may operate normally. When
RPR is set, the receiver section enters the personal reset state immediately. When in the personal reset
state, the status bits are reset to the same state as after hardware reset.The control bits are not affected by
the personal reset state.The receiver data pins are disconnected while in the personal reset state. Note that
to leave the personal reset state by clearing RPR, the procedure described in Section 8.6, "ESAI
Initialization Examples" should be followed.
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8.3.4.13 RCR Receive Exception Interrupt Enable (REIE) - Bit 20
When REIE is set, the DSP is interrupted when both RDF and ROE in the SAISR status register are set.
When REIE is cleared, this interrupt is disabled. Reading the SAISR status register followed by reading
the enabled receivers data registers clears ROE, thus clearing the pending interrupt.
8.3.4.14 RCR Receive Even Slot Data Interrupt Enable (REDIE) - Bit 21
The REDIE control bit is used to enable the receive even slot data interrupts. If REDIE is set, the receive
even slot data interrupts are enabled. If REDIE is cleared, the receive even slot data interrupts are disabled.
A receive even slot data interrupt request is generated if REDIE is set and the REDF status flag in the
SAISR status register is set. Even time slots are all even-numbered time slots (0, 2, 4, etc.) when operating
in network mode. The zero time slot is marked by the frame sync signal and is considered to be even.
Reading all the data registers of the enabled receivers clears the REDF flag, thus servicing the interrupt.
Receive interrupts with exception have higher priority than receive even slot data interrupts, therefore if
exception occurs (ROE is set) and REIE is set, the ESAI requests an ESAI receive data with exception
interrupt from the interrupt controller.
8.3.4.15 RCR Receive Interrupt Enable (RIE) - Bit 22
The DSP is interrupted when RIE and the RDF flag in the SAISR status register are set. When RIE is
cleared, this interrupt is disabled. Reading the receive data registers of the enabled receivers clears RDF,
thus clearing the interrupt.
Receive interrupts with exception have higher priority than normal receive data interrupts, therefore if
exception occurs (ROE is set) and REIE is set, the ESAI requests an ESAI receive data with exception
interrupt from the interrupt controller.
8.3.4.16 RCR Receive Last Slot Interrupt Enable (RLIE) - Bit 23
RLIE enables an interrupt after the last slot of a frame ended in network mode only. When RLIE is set the
DSP is interrupted after the last slot in a frame ended regardless of the receive mask register setting. When
RLIE is cleared the receive last slot interrupt is disabled. Hardware and software reset clear RLIE. RLIE
is disabled when RDC[4:0]=00000 (on-demand mode). The use of the receive last slot interrupt is
8.3.5
ESAI Common Control Register (SAICR)
The read/write Common Control Register (SAICR) contains control bits for functions that affect both the
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11
10
22
9
8
7
6
5
4
3
2
1
0
X:$FFFFB4
ALC
TEBE
SYN
OF2
OF1
OF0
23
21
20
19
18
17
16
15
14
13
12
Reserved bit - read as zero; should be written with zero for future compatibility.
Figure 8-10 SAICR Register
Hardware and software reset clear all the bits in the SAICR register.
8.3.5.1 SAICR Serial Output Flag 0 (OF0) - Bit 0
The Serial Output Flag 0 (OF0) is a data bit used to hold data to be send to the OF0 pin. When the ESAI
is in the synchronous clock mode (SYN=1), the SCKR pin is configured as the ESAI flag 0. If the receiver
serial clock direction bit (RCKD) is set, the SCKR pin is the output flag OF0, and data present in the OF0
bit is written to the OF0 pin at the beginning of the frame in normal mode or at the beginning of the next
time slot in network mode.
8.3.5.2
SAICR Serial Output Flag 1 (OF1) - Bit 1
The Serial Output Flag 1 (OF1) is a data bit used to hold data to be send to the OF1 pin. When the ESAI
is in the synchronous clock mode (SYN=1), the FSR pin is configured as the ESAI flag 1. If the receiver
frame sync direction bit (RFSD) is set and the TEBE bit is cleared, the FSR pin is the output flag OF1, and
data present in the OF1 bit is written to the OF1 pin at the beginning of the frame in normal mode or at the
beginning of the next time slot in network mode.
8.3.5.3
SAICR Serial Output Flag 2 (OF2) - Bit 2
The Serial Output Flag 2 (OF2) is a data bit used to hold data to be send to the OF2 pin. When the ESAI
is in the synchronous clock mode (SYN=1), the HCKR pin is configured as the ESAI flag 2. If the receiver
high frequency clock direction bit (RHCKD) is set, the HCKR pin is the output flag OF2, and data present
in the OF2 bit is written to the OF2 pin at the beginning of the frame in normal mode or at the beginning
of the next time slot in network mode.
8.3.5.4
SAICR Reserved Bits - Bits 3-5, 9-23
These bits are reserved. They read as zero, and they should be written with zero for future compatibility.
8.3.5.5
SAICR Synchronous Mode Selection (SYN) - Bit 6
The Synchronous Mode Selection (SYN) bit controls whether the receiver and transmitter sections of the
is cleared, the asynchronous mode is chosen and independent clock and frame sync signals are used for
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the transmit and receive sections. When SYN is set, the synchronous mode is chosen and the transmit and
receive sections use common clock and frame sync signals.
When in the synchronous mode (SYN=1), the transmit and receive sections use the transmitter section
clock generator as the source of the clock and frame sync for both sections. Also, the receiver clock pins
SCKR, FSR and HCKR now operate as I/O flags. See Table 8-7, Table 8-8 and Table 8-9 for the effects of
SYN on the receiver clock pins.
8.3.5.6
SAICR Transmit External Buffer Enable (TEBE) - Bit 7
The Transmitter External Buffer Enable (TEBE) bit controls the function of the FSR pin when in the
synchronous mode. If the ESAI is configured for operation in the synchronous mode (SYN=1), and TEBE
is set while FSR pin is configured as an output (RFSD=1), the FSR pin functions as the transmitter external
buffer enable control, to enable the use of an external buffers on the transmitter outputs. If TEBE is cleared
then the FSR pin functions as the serial I/O flag 1. See Table 8-8 for a summary of the effects of TEBE on
the FSR pin.
8.3.5.7
SAICR Alignment Control (ALC) - Bit 8
The ESAI is designed for 24-bit fractional data, thus shorter data words are left aligned to the MSB (bit
23). Some applications use 16-bit fractional data. In those cases, shorter data words may be left aligned to
bit 15. The Alignment Control (ALC) bit supports these applications.
If ALC is set, transmitted and received words are left aligned to bit 15 in the transmit and receive shift
registers. If ALC is cleared, transmitted and received word are left aligned to bit 23 in the transmit and
receive shift registers.
NOTE
While ALC is set, 20-bit and 24-bit words may not be used, and word length
control should specify 8-, 12- or 16-bit words, otherwise results are
unpredictable.
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ESAI Programming Model
ASYNCHRONOUS (SYN=0)
TRANSMITTER
SDO
FRAME
CLOCK
SYNC
EXTERNAL TRANSMIT CLOCK
EXTERNAL TRANSMIT FRAME SYNC
INTERNAL FRAME SYNC
SCKT
FST
FSR
INTERNAL CLOCK
ESAI BIT
CLOCK
EXTERNAL RECEIVE CLOCK
EXTERNAL RECEIVE FRAME SYNC
SCKR
CLOCK
FRAME
SYNC
SDI
RECEIVER
NOTE: Transmitter and receiver may have different clocks and frame syncs.
SYNCHRONOUS (SYN=1)
TRANSMITTER
SDO
FRAME
SYNC
CLOCK
EXTERNAL CLOCK
INTERNAL CLOCK
EXTERNAL FRAME SYNC
INTERNAL FRAME SYNC
SCKT
FST
ESAI BIT
CLOCK
CLOCK
FRAME
SYNC
SDI
RECEIVER
NOTE: Transmitter and receiver have the same clocks and frame syncs.
Figure 8-11 SAICR SYN Bit Operation
8.3.6
ESAI Status Register (SAISR)
The Status Register (SAISR) is a read-only status register used by the DSP to read the status and serial
input flags of the ESAI. See Figure 8-12. The status bits are described in the following paragraphs.
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11
23
10
9
8
7
6
5
4
3
2
1
0
X:$FFFFB3
RODF REDF
RDF
ROE
RFS
IF2
IF1
IF0
22
21
20
19
18
17
16
15
14
13
12
TODE TEDE
TDE
TUE
TFS
Reserved bit - read as zero; should be written with zero for future compatibility.
Figure 8-12 SAISR Register
8.3.6.1
SAISR Serial Input Flag 0 (IF0) - Bit 0
The IF0 bit is enabled only when the SCKR pin is defined as ESAI in the Port Control Register, SYN=1
and RCKD=0, indicating that SCKR is an input flag and the synchronous mode is selected. Data present
on the SCKR pin is latched during reception of the first received data bit after frame sync is detected. The
IF0 bit is updated with this data when the receiver shift registers are transferred into the receiver data
registers. IF0 reads as a zero when it is not enabled. Hardware, software, ESAI individual, and STOP reset
clear IF0.
8.3.6.2
SAISR Serial Input Flag 1 (IF1) - Bit 1
The IF1 bit is enabled only when the FSR pin is defined as ESAI in the Port Control Register, SYN =1,
RFSD=0 and TEBE=0, indicating that FSR is an input flag and the synchronous mode is selected. Data
present on the FSR pin is latched during reception of the first received data bit after frame sync is detected.
The IF1 bit is updated with this data when the receiver shift registers are transferred into the receiver data
registers. IF1 reads as a zero when it is not enabled. Hardware, software, ESAI individual, and STOP reset
clear IF1.
8.3.6.3
SAISR Serial Input Flag 2 (IF2) - Bit 2
The IF2 bit is enabled only when the HCKR pin is defined as ESAI in the Port Control Register, SYN=1
and RHCKD=0, indicating that HCKR is an input flag and the synchronous mode is selected. Data present
on the HCKR pin is latched during reception of the first received data bit after frame sync is detected. The
IF2 bit is updated with this data when the receive shift registers are transferred into the receiver data
registers. IF2 reads as a zero when it is not enabled. Hardware, software, ESAI individual, and STOP reset
clear IF2.
8.3.6.4
SAISR Reserved Bits - Bits 3-5, 11-12, 18-23
These bits are reserved for future use. They read as zero.
8.3.6.5
SAISR Receive Frame Sync Flag (RFS) - Bit 6
When set, RFS indicates that a receive frame sync occurred during reception of the words in the receiver
data registers. This indicates that the data words are from the first slot in the frame. When RFS is clear and
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a word is received, it indicates (only in the network mode) that the frame sync did not occur during
reception of that word. RFS is cleared by hardware, software, ESAI individual, or STOP reset. RFS is valid
only if at least one of the receivers is enabled (REx=1).
NOTE
In normal mode, RFS always reads as a one when reading data because there
is only one time slot per frame – the “frame sync” time slot.
8.3.6.6
SAISR Receiver Overrun Error Flag (ROE) - Bit 7
The ROE flag is set when the serial receive shift register of an enabled receiver is full and ready to transfer
to its receiver data register (RXx) and the register is already full (RDF=1). If REIE is set, an ESAI receive
data with exception (overrun error) interrupt request is issued when ROE is set. Hardware, software, ESAI
individual, and STOP reset clear ROE. ROE is also cleared by reading the SAISR with ROE set, followed
by reading all the enabled receive data registers.
8.3.6.7
SAISR Receive Data Register Full (RDF) - Bit 8
RDF is set when the contents of the receive shift register of an enabled receiver is transferred to the
respective receive data register. RDF is cleared when the DSP reads the receive data register of all enabled
receivers or cleared by hardware, software, ESAI individual, or STOP reset. If RIE is set, an ESAI receive
data interrupt request is issued when RDF is set.
8.3.6.8
SAISR Receive Even-Data Register Full (REDF) - Bit 9
When set, REDF indicates that the received data in the receive data registers of the enabled receivers have
arrived during an even time slot when operating in the network mode. Even time slots are all
even-numbered slots (0, 2, 4, 6, etc.). Time slots are numbered from zero to N-1, where N is the number
of time slots in the frame. The zero time slot is considered even. REDF is set when the contents of the
receive shift registers are transferred to the receive data registers. REDF is cleared when the DSP reads all
the enabled receive data registers or cleared by hardware, software, ESAI individual, or STOP resets. If
REDIE is set, an ESAI receive even slot data interrupt request is issued when REDF is set.
8.3.6.9
SAISR Receive Odd-Data Register Full (RODF) - Bit 10
When set, RODF indicates that the received data in the receive data registers of the enabled receivers have
arrived during an odd time slot when operating in the network mode. Odd time slots are all odd-numbered
slots (1, 3, 5, etc.). Time slots are numbered from zero to N-1, where N is the number of time slots in the
frame. RODF is set when the contents of the receive shift registers are transferred to the receive data
registers. RODF is cleared when the DSP reads all the enabled receive data registers or cleared by
hardware, software, ESAI individual, or STOP resets.
8.3.6.10 SAISR Transmit Frame Sync Flag (TFS) - Bit 13
When set, TFS indicates that a transmit frame sync occurred in the current time slot. TFS is set at the start
of the first time slot in the frame and cleared during all other time slots. Data written to a transmit data
register during the time slot when TFS is set is transmitted (in network mode), if the transmitter is enabled,
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during the second time slot in the frame. TFS is useful in network mode to identify the start of a frame.
TFS is cleared by hardware, software, ESAI individual, or STOP reset. TFS is valid only if at least one
transmitter is enabled (i.e. one or more of TE0, TE1, TE2, TE3, TE4 and TE5 are set).
NOTE
In normal mode, TFS always reads as a one when transmitting data because
there is only one time slot per frame – the “frame sync” time slot.
8.3.6.11 SAISR Transmit Underrun Error Flag (TUE) - Bit 14
TUE is set when at least one of the enabled serial transmit shift registers is empty (no new data to be
transmitted) and a transmit time slot occurs. When a transmit underrun error occurs, the previous data
(which is still present in the TX registers that were not written) is retransmitted. If TEIE is set, an ESAI
transmit data with exception (underrun error) interrupt request is issued when TUE is set. Hardware,
software, ESAI individual, and STOP reset clear TUE. TUE is also cleared by reading the SAISR with
TUE set, followed by writing to all the enabled transmit data registers or to TSR.
8.3.6.12 SAISR Transmit Data Register Empty (TDE) - Bit 15
TDE is set when the contents of the transmit data register of all the enabled transmitters are transferred to
the transmit shift registers; it is also set for a TSR disabled time slot period in network mode (as if data
were being transmitted after the TSR was written). When set, TDE indicates that data should be written to
all the TX registers of the enabled transmitters or to the time slot register (TSR). TDE is cleared when the
DSP writes to all the transmit data registers of the enabled transmitters, or when the DSP writes to the TSR
to disable transmission of the next time slot. If TIE is set, an ESAI transmit data interrupt request is issued
when TDE is set. Hardware, software, ESAI individual, and STOP reset clear TDE.
8.3.6.13 SAISR Transmit Even-Data Register Empty (TEDE) - Bit 16
When set, TEDE indicates that the enabled transmitter data registers became empty at the beginning of an
even time slot. Even time slots are all even-numbered slots (0, 2, 4, 6, etc.). Time slots are numbered from
zero to N-1, where N is the number of time slots in the frame. The zero time slot is considered even. This
flag is set when the contents of the transmit data register of all the enabled transmitters are transferred to
the transmit shift registers; it is also set for a TSR disabled time slot period in network mode (as if data
were being transmitted after the TSR was written). When set, TEDE indicates that data should be written
to all the TX registers of the enabled transmitters or to the time slot register (TSR). TEDE is cleared when
the DSP writes to all the transmit data registers of the enabled transmitters, or when the DSP writes to the
TSR to disable transmission of the next time slot. If TIE is set, an ESAI transmit data interrupt request is
issued when TEDE is set. Hardware, software, ESAI individual, and STOP reset clear TEDE.
8.3.6.14 SAISR Transmit Odd-Data Register Empty (TODE) - Bit 17
When set, TODE indicates that the enabled transmitter data registers became empty at the beginning of an
odd time slot. Odd time slots are all odd-numbered slots (1, 3, 5, etc.). Time slots are numbered from zero
to N-1, where N is the number of time slots in the frame. This flag is set when the contents of the transmit
data register of all the enabled transmitters are transferred to the transmit shift registers; it is also set for a
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TSR disabled time slot period in network mode (as if data were being transmitted after the TSR was
written). When set, TODE indicates that data should be written to all the TX registers of the enabled
transmitters or to the time slot register (TSR). TODE is cleared when the DSP writes to all the transmit
data registers of the enabled transmitters, or when the DSP writes to the TSR to disable transmission of the
next time slot. If TIE is set, an ESAI transmit data interrupt request is issued when TODE is set. Hardware,
software, ESAI individual, and STOP reset clear TODE.
23 16 15870
ESAI RECEIVE DATA REGISTER
RECEIVE HIGH BYTERECEIVE MIDDLE BYTERECEIVE LOW BYTE
(READ ONLY)
7
0
7070
23 16 15870
SERIAL
RECEIVE
SHIFT
RECEIVE HIGH BYTERECEIVE MIDDLE BYTERECEIVE LOW BYTE
REGISTER
7
0
7070
24 BIT
20 BIT
16 BIT
12 BIT
SDI
8 BIT
RSWS4-
RSWS0
MSB
MSB
MSB
LSB
LEAST SIGNIFICANT
ZERO FILL
8-BIT DATA
12-BIT DATA
16-BIT DATA
20-BIT DATA
24-BIT DATA
0
0
0
0
LSB
LSB
MSB
MSB
LSB
LSB
NOTES:
1. Data is received MSB first if RSHFD=0.
2. 24-bit fractional format (ALC=0).
3. 32-bit mode is not shown.
(a) Receive Registers
23 16 15870
ESAI TRANSMIT DATA
REGISTER
(WRITE ONLY)
TRANSMIT HIGH BYTETRANSMIT MIDDLE BYTETRANSMIT LOW BYTE
7070
7
0
23 16 15870
TRANSMIT HIGH BYTETRANSMIT MIDDLE BYTETRANSMIT LOW BYTE
ESAI TRANSMIT
SHIFT REGISTER
SDO
7
0
7070
MSB
MSB
MSB
LSB
* - LEAST SIGNIFICANT
BIT FILL
8-BIT DATA
12-BIT DATA
16-BIT DATA
20-BIT DATA
24-BIT DATA
*
*
*
*
LSB
LSB
MSB
MSB
LSB
LSB
NOTES:
1. Data is sent MSB first if TSHFD=0.
2. 24-bit fractional format (ALC=0).
3. 32-bit mode is not shown.
4, Data word is left-aligned
(TWA=0,PADC=0).
(b) Transmit Registers
Figure 8-13 ESAI Data Path Programming Model ([R/T]SHFD=0)
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23 16 15870
RECEIVE HIGH BYTERECEIVE MIDDLE BYTERECEIVE LOW BYTE
7070
ESAI RECEIVE DATA REGISTER
(READ ONLY)
7
0
23 16 15870
RECEIVE HIGH BYTERECEIVE MIDDLE BYTERECEIVE LOW BYTE
ESAI RECEIVE
SHIFT REGISTER
SDI
7
0
7070
MSB
MSB
MSB
LSB
LEAST SIGNIFICANT
ZERO FILL
8-BIT DATA
12-BIT DATA
16-BIT DATA
20-BIT DATA
24-BIT DATA
0
0
0
0
LSB
LSB
MSB
MSB
LSB
LSB
NOTES:
1. Data is received LSB first if RSHFD=1.
2. 24-bit fractional format (ALC=0).
3. 32-bit mode is not shown.
(a) Receive Registers
23 16 15870
TRANSMIT HIGH BYTETRANSMIT MIDDLE BYTETRANSMIT LOW BYTE
7070
7
0
ESAI TRANSMIT DATA
REGISTER
(WRITE ONLY)
ESAI TRANSMIT
23 16 15870
TRANSMIT HIGH BYTETRANSMIT MIDDLE BYTETRANSMIT LOW BYTE
SHIFT REGISTER
7
0
7070
24 BIT
20 BIT
16 BIT
12 BIT
SDO
8 BIT
LSB
TSWS4-
TSWS0
MSB
MSB
MSB
LSB
0
0
8-BIT DATA
0
0
12-BIT DATA
LSB
16-BIT DATA
MSB
MSB
LSB
20-BIT DATA
LSB
24-BIT DATA
NOTES:
1. Data is sent LSB first if TSHFD=1.
(b) Transmit Registers
2. 24-bit fractional format (ALC=0).
3. 32-bit mode is not shown.
4. Data word is left aligned (TWA=0,PADC=1).
Figure 8-14 ESAI Data Path Programming Model ([R/T]SHFD=1)
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ESAI Programming Model
8.3.7
ESAI Receive Shift Registers
The receive shift registers (see Figure 8-13 and Figure 8-14) receive the incoming data from the serial
receive data pins. Data is shifted in by the selected (internal/external) bit clock when the associated frame
sync I/O is asserted. Data is assumed to be received MSB first if RSHFD=0 and LSB first if RSHFD=1.
Data is transferred to the ESAI receive data registers after 8, 12, 16, 20, 24, or 32 serial clock cycles were
counted, depending on the slot length control bits in the RCR register.
8.3.8
ESAI Receive Data Registers (RX3, RX2, RX1, RX0)
RX3, RX2, RX1 and RX0 are 24-bit read-only registers that accept data from the receive shift registers
when they become full (see Figure 8-13 and Figure 8-14). The data occupies the most significant portion
of the receive data registers, according to the ALC control bit setting. The unused bits (least significant
portion, and 8 most significant bits when ALC=1) read as zeros. The DSP is interrupted whenever RXx
becomes full if the associated interrupt is enabled.
8.3.9
ESAI Transmit Shift Registers
The transmit shift registers contain the data being transmitted (see Figure 8-13 and Figure 8-14). Data is
shifted out to the serial transmit data pins by the selected (internal/external) bit clock when the associated
frame sync I/O is asserted. The number of bits shifted out before the shift registers are considered empty
and may be written to again can be 8, 12, 16, 20, 24 or 32 bits (determined by the slot length control bits
in the TCR register). Data is shifted out of these registers MSB first if TSHFD=0 and LSB first if
TSHFD=1.
8.3.10 ESAI Transmit Data Registers (TX5, TX4, TX3, TX2,TX1,TX0)
TX5, TX4, TX3, TX2, TX1 and TX0 are 24-bit write-only registers. Data to be transmitted is written into
these registers and is automatically transferred to the transmit shift registers (see Figure 8-13 and
Figure 8-14). The data written (8, 12, 16, 20 or 24 bits) should occupy the most significant portion of the
TXx according to the ALC control bit setting. The unused bits (least significant portion, and the 8 most
significant bits when ALC=1) of the TXx are don’t care bits. The DSP is interrupted whenever the TXx
becomes empty if the transmit data register empty interrupt has been enabled.
8.3.11 ESAI Time Slot Register (TSR)
The write-only Time Slot Register (TSR) is effectively a null data register that is used when the data is not
to be transmitted in the available transmit time slot. The transmit data pins of all the enabled transmitters
are in the high-impedance state for the respective time slot where TSR has been written. The Transmitter
External Buffer Enable pin (FSR pin when SYN=1, TEBE=1, RFSD=1) disables the external buffers
during the slot when the TSR register has been written.
8.3.12 Transmit Slot Mask Registers (TSMA, TSMB)
The Transmit Slot Mask Registers (TSMA and TSMB) are two read/write registers used by the
transmitters in network mode to determine for each slot whether to transmit a data word and generate a
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ESAI Programming Model
transmitter empty condition (TDE=1), or to tri-state the transmitter data pins. TSMA and TSMB should
each be considered as containing half a 32-bit register TSM. See Figure 8-15 and Figure 8-16. Bit number
N in TSM (TS**) is the enable/disable control bit for transmission in slot number N.
11
10
9
8
7
6
5
4
3
2
1
0
X:$FFFFB9
TS11
TS10
TS9
TS8
TS7
TS6
TS5
TS4
TS3
TS2
TS1
TS0
23
22
21
20
19
18
17
16
15
14
13
12
TS15
TS14
TS13
TS12
Reserved bit - read as zero; should be written with zero for future compatibility.
Figure 8-15 TSMA Register
11
10
9
8
7
6
5
4
3
2
1
0
X:$FFFFBA
TS27
TS26
TS25
TS24
TS23
TS22
TS21
TS20
TS19
TS18
TS17
TS16
23
22
21
20
19
18
17
16
15
14
13
12
TS31
TS30
TS29
TS28
Reserved bit - read as zero; should be written with zero for future compatibility.
Figure 8-16 TSMB Register
When bit number N in TSM is cleared, all the transmit data pins of the enabled transmitters are tri-stated
during transmit time slot number N. The data is still transferred from the transmit data registers to the
transmit shift registers but neither the TDE nor the TUE flags are set. This means that during a disabled
slot, no transmitter empty interrupt is generated. The DSP is interrupted only for enabled slots. Data that
is written to the transmit data registers when servicing this request is transmitted in the next enabled
transmit time slot.
When bit number N in TSM register is set, the transmit sequence is as usual: data is transferred from the
TX registers to the shift registers, transmitted during slot number N, and the TDE flag is set.
Using the slot mask in TSM does not conflict with using TSR. Even if a slot is enabled in TSM, the user
may chose to write to TSR instead of writing to the transmit data registers TXx. This causes all the transmit
data pins of the enabled transmitters to be tri-stated during the next slot.
Data written to the TSM affects the next frame transmission. The frame being transmitted is not affected
by this data and would comply to the last TSM setting. Data read from TSM returns the last written data.
After hardware or software reset, the TSM register is preset to $FFFFFFFF, which means that all 32
possible slots are enabled for data transmission.
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ESAI Programming Model
NOTE
When operating in normal mode, bit 0 of the mask register must be set,
otherwise no output is generated.
8.3.13 Receive Slot Mask Registers (RSMA, RSMB)
The Receive Slot Mask Registers (RSMA and RSMB) are two read/write registers used by the receiver in
network mode to determine for each slot whether to receive a data word and generate a receiver full
condition (RDF=1), or to ignore the received data. RSMA and RSMB should be considered as each
containing half of a 32-bit register RSM. See Figure 8-17 and Figure 8-18. Bit number N in RSM (RS**)
is an enable/disable control bit for receiving data in slot number N.
11
10
9
8
7
6
5
4
3
2
1
0
X:$FFFFBB
RS11
RS10
RS9
RS8
RS7
RS6
RS5
RS4
RS3
RS2
RS1
RS0
23
22
21
20
19
18
17
16
15
14
13
12
RS15
RS14
RS13
RS12
Reserved bit - read as zero; should be written with zero for future compatibility.
Figure 8-17 RSMA Register
11
10
9
8
7
6
5
4
3
2
1
0
X:$FFFFBC
RS27
RS26
RS25
RS24
RS23
RS22
RS21
RS20
RS19
RS18
RS17
RS16
23
22
21
20
19
18
17
16
15
14
13
12
RS31
RS30
RS29
RS28
Reserved bit - read as zero; should be written with zero for future compatibility.
Figure 8-18 RSMB Register
When bit number N in the RSM register is cleared, the data from the enabled receivers input pins are
shifted into their receive shift registers during slot number N. The data is not transferred from the receive
shift registers to the receive data registers, and neither the RDF nor the ROE flags are set. This means that
during a disabled slot, no receiver full interrupt is generated. The DSP is interrupted only for enabled slots.
When bit number N in the RSM is set, the receive sequence is as usual: data which is shifted into the
enabled receivers shift registers is transferred to the receive data registers and the RDF flag is set.
Data written to the RSM affects the next received frame. The frame being received is not affected by this
data and would comply to the last RSM setting. Data read from RSM returns the last written data.
After hardware or software reset, the RSM register is preset to $FFFFFFFF, which means that all 32
possible slots are enabled for data reception.
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Operating Modes
NOTE
When operating in normal mode, bit 0 of the mask register must be set to
one, otherwise no input is received.
8.4
Operating Modes
ESAI operating mode are selected by the ESAI control registers (TCCR, TCR, RCCR, RCR and SAICR).
The main operating mode are described in the following paragraphs.
8.4.1
ESAI After Reset
Hardware or software reset clears the port control register bits and the port direction control register bits,
which configure all ESAI I/O pins as disconnected. The ESAI is in the individual reset state while all ESAI
pins are programmed as GPIO or disconnected, and is active only if at least one of the ESAI I/O pins is
programmed as an ESAI pin.
8.4.2
ESAI Initialization
The correct way to initialize the ESAI is as follows:
1. Hardware, software, ESAI individual, or STOP reset.
2. Program ESAI control and time slot registers.
3. Write data to all the enabled transmitters.
4. Configure at least one pin as ESAI pin.
During program execution, all ESAI pins may be defined as GPIO or disconnected, causing the ESAI to
stop serial activity and enter the individual reset state. All status bits of the interface are set to their reset
state; however, the control bits are not affected. This procedure allows the DSP programmer to reset the
ESAI separately from the other internal peripherals. During individual reset, internal DMA accesses to the
data registers of the ESAI are not valid and data read is undefined.
The DSP programmer must use an individual ESAI reset when changing the ESAI control registers (except
for TEIE, REIE, TLIE, RLIE, TIE, RIE, TE0-TE5, RE0-RE3) to ensure proper operation of the interface.
NOTE
If the ESAI receiver section is already operating with some of the receivers,
enabling additional receivers on the fly (i.e., without first putting the ESAI
receiver in the personal reset state) by setting their REx control bits will
result in erroneous data being received as the first data word for the newly
enabled receivers.
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Operating Modes
8.4.3
ESAI Interrupt Requests
The ESAI can generate eight different interrupt requests (ordered from the highest to the lowest priority):
1. ESAI Receive Data with Exception Status.
Occurs when the receive exception interrupt is enabled (REIE=1 in the RCR register), at least one
of the enabled receive data registers is full (RDF=1), and a receiver overrun error has occurred
(ROE=1 in the SAISR register). ROE is cleared by first reading the SAISR and then reading all the
enabled receive data registers.
2. ESAI Receive Even Data
Occurs when the receive even slot data interrupt is enabled (REDIE=1), at least one of the enabled
receive data registers is full (RDF=1), the data is from an even slot (REDF=1), and no exception
has occurred (ROE=0 or REIE=0).
Reading all enabled receiver data registers clears RDF and REDF.
3. ESAI Receive Data
Occurs when the receive interrupt is enabled (RIE=1), at least one of the enabled receive data
registers is full (RDF=1), no exception has occurred (ROE=0 or REIE=0), and no even slot
interrupt has occurred (REDF=0 or REDIE=0).
Reading all enabled receiver data registers clears RDF.
4. ESAI Receive Last Slot Interrupt
Occurs, if enabled (RLIE=1), after the last slot of the frame ended (in network mode only)
regardless of the receive mask register setting. The receive last slot interrupt may be used for
resetting the receive mask slot register, reconfiguring the DMA channels and reassigning data
memory pointers. Using the receive last slot interrupt guarantees that the previous frame was
serviced with the previous setting and the new frame is serviced with the new setting without
synchronization problems. Note that the maximum receive last slot interrupt service time should
not exceed N-1 ESAI bits service time (where N is the number of bits in a slot).
5. ESAI Transmit Data with Exception Status
Occurs when the transmit exception interrupt is enabled (TEIE=1), at least one transmit data
register of the enabled transmitters is empty (TDE=1), and a transmitter underrun error has
occurred (TUE=1). TUE is cleared by first reading the SAISR and then writing to all the enabled
transmit data registers, or to the TSR register.
6. ESAI Transmit Last Slot Interrupt
Occurs, if enabled (TLIE=1), at the start of the last slot of the frame in network mode regardless of
the transmit mask register setting. The transmit last slot interrupt may be used for resetting the
transmit mask slot register, reconfiguring the DMA channels and reassigning data memory
pointers. Using the transmit last slot interrupt guarantees that the previous frame was serviced with
the previous setting and the new frame is serviced with the new setting without synchronization
problems. Note that the maximum transmit last slot interrupt service time should not exceed N-1
ESAI bits service time (where N is the number of bits in a slot).
7. ESAI Transmit Even Data
Occurs when the transmit even slot data interrupt is enabled (TEDIE=1), at least one of the enabled
transmit data registers is empty (TDE=1), the slot is an even slot (TEDE=1), and no exception has
occurred (TUE=0 or TEIE=0).
Writing to all the TX registers of the enabled transmitters or to TSR clears this interrupt request.
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Operating Modes
8. ESAI Transmit Data
Occurs when the transmit interrupt is enabled (TIE=1), at least one of the enabled transmit data
registers is empty (TDE=1), no exception has occurred (TUE=0 or TEIE=0), and no even slot
interrupt has occurred (TEDE=0 or TEDIE=0).
Writing to all the TX registers of the enabled transmitters, or to the TSR clears this interrupt
request.
8.4.4
Operating Modes – Normal, Network, and On-Demand
The ESAI has three basic operating modes and many data/operation formats.
8.4.4.1 Normal/Network/On-Demand Mode Selection
Selecting between the normal mode and network mode is accomplished by clearing or setting the
TMOD0-TMOD1 bits in the TCR register for the transmitter section, and in the RMOD0-RMOD1 bits in
the RCR register for the receiver section.
For normal mode, the ESAI functions with one data word of I/O per frame (per enabled transmitter or
receiver). The normal mode is typically used to transfer data to/from a single device.
For the network mode, 2 to 32 time slots per frame may be selected. During each frame, 0 to 32 data words
of I/O may be received/transmitted. In either case, the transfers are periodic. The frame sync signal
indicates the first time slot in the frame. Network mode is typically used in time division multiplexed
(TDM) networks of codecs, DSPs with multiple words per frame, or multi-channel devices.
Selecting the network mode and setting the frame rate divider to zero (DC=00000) selects the on-demand
mode. This special case does not generate a periodic frame sync. A frame sync pulse is generated only
when data is available to transmit. The on-demand mode requires that the transmit frame sync be internal
(output) and the receive frame sync be external (input). Therefore, for simplex operation, the synchronous
mode could be used; however, for full-duplex operation, the asynchronous mode must be used. Data
transmission that is data driven is enabled by writing data into each TX. Although the ESAI is double
buffered, only one word can be written to each TX, even if the transmit shift register is empty. The receive
and transmit interrupts function as usual using TDE and RDF; however, transmit underruns are impossible
for on-demand transmission and are disabled.
8.4.4.2
Synchronous/Asynchronous Operating Modes
The transmit and receive sections of the ESAI may be synchronous or asynchronous – i.e., the transmitter
and receiver sections may use common clock and synchronization signals (synchronous operating mode),
or they may have their own separate clock and sync signals (asynchronous operating mode). The SYN bit
in the SAICR register selects synchronous or asynchronous operation. Since the ESAI is designed to
operate either synchronously or asynchronously, separate receive and transmit interrupts are provided.
When SYN is cleared, the ESAI transmitter and receiver clocks and frame sync sources are independent.
If SYN is set, the ESAI transmitter and receiver clocks and frame sync come from the transmitter section
(either external or internal sources).
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Operating Modes
Data clock and frame sync signals can be generated internally by the DSP or may be obtained from
external sources. If internally generated, the ESAI clock generator is used to derive high frequency clock,
bit clock and frame sync signals from the DSP internal system clock.
8.4.4.3
Frame Sync Selection
The frame sync can be either a bit-long or word-long signal. The transmitter frame format is defined by
the TFSL bit in the TCR register. The receiver frame format is defined by the RFSL bit in the RCR register.
1. In the word-long frame sync format, the frame sync signal is asserted during the entire word data
transfer period. This frame sync length is compatible with Freescale codecs, SPI serial peripherals,
serial A/D and D/A converters, shift registers, and telecommunication PCM serial I/O.
2. In the bit-long frame sync format, the frame sync signal is asserted for one bit clock immediately
before the data transfer period. This frame sync length is compatible with Intel and National
components, codecs, and telecommunication PCM serial I/O.
The relative timing of the word length frame sync as referred to the data word is specified by the TFSR bit
in the TCR register for the transmitter section, and by the RFSR bit in the RCR register for the receive
section. The word length frame sync may be generated (or expected) with the first bit of the data word, or
with the last bit of the previous word. TFSR and RFSR are ignored when a bit length frame sync is
selected.
Polarity of the frame sync signal may be defined as positive (asserted high) or negative (asserted low). The
TFSP bit in the TCCR register specifies the polarity of the frame sync for the transmitter section. The
RFSP bit in the RCCR register specifies the polarity of the frame sync for the receiver section.
The ESAI receiver looks for a receive frame sync leading edge (trailing edge if RFSP is set) only when the
previous frame is completed. If the frame sync goes high before the frame is completed (or before the last
bit of the frame is received in the case of a bit frame sync or a word length frame sync with RFSR set), the
current frame sync is not recognized, and the receiver is internally disabled until the next frame sync.
Frames do not have to be adjacent – i.e., a new frame sync does not have to immediately follow the
previous frame. Gaps of arbitrary periods can occur between frames. Enabled transmitters are tri-stated
during these gaps.
When operating in the synchronous mode (SYN=1), all clocks including the frame sync are generated by
the transmitter section.
8.4.4.4
Shift Direction Selection
Some data formats, such as those used by codecs, specify MSB first while other data formats, such as the
AES-EBU digital audio interface, specify LSB first. The MSB/LSB first selection is made by
programming RSHFD bit in the RCR register for the receiver section, and by programming the TSHFD
bit in the TCR register for the transmitter section.
8.4.5
Serial I/O Flags
Three ESAI pins (FSR, SCKR and HCKR) are available as serial I/O flags when the ESAI is operating in
the synchronous mode (SYN=1). Their operation is controlled by RCKD, RFSD, TEBE bits in the RCR,
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GPIO - Pins and Registers
RCCR and SAICR registers.The output data bits (OF2, OF1 and OF0) and the input data bits (IF2, IF1 and
IF0) are double buffered to/from the HCKR, FSR and SCKR pins. Double buffering the flags keeps them
in sync with the TX and RX data lines.
Each flag can be separately programmed. Flag 0 (SCKR pin) direction is selected by RCKD, RCKD=1 for
output and RCKD=0 for input. Flag 1 (FSR pin) is enabled when the pin is not configured as external
transmitter buffer enable (TEBE=0) and its direction is selected by RFSD, RFSD=1 for output and
RFSD=0 for input. Flag 2 (HCKR pin) direction is selected by RHCKD, RHCKD=1 for output and
RHCKD=0 for input.
When programmed as input flags, the SCKR, FSR and HCKR logic values, respectively, are latched at the
same time as the first bit of the receive data word is sampled. Because the input was latched, the signal on
the input flag pin (SCKR, FSR or HCKR) can change without affecting the input flag until the first bit of
the next receive data word. When the received data words are transferred to the receive data registers, the
input flag latched values are then transferred to the IF0, IF1 and IF2 bits in the SAISR register, where they
may be read by software.
When programmed as output flags, the SCKR, FSR and HCKR logic values are driven by the contents of
the OF0, OF1 and OF2 bits in the SAICR register respectively, and are driven when the transmit data
registers are transferred to the transmit shift registers. The value on SCKR, FSR and HCKR is stable from
the time the first bit of the transmit data word is transmitted until the first bit of the next transmit data word
is transmitted. Software may change the OF0-OF2 values thus controlling the SCKR, FSR and HCKR pin
values for each transmitted word. The normal sequence for setting output flags when transmitting data is
as follows: wait for TDE (transmitter empty) to be set, first write the flags, and then write the transmit data
to the transmit registers. OF0, OF1 and OF2 are double buffered so that the flag states appear on the pins
when the transmit data is transferred to the transmit shift register (i.e., the flags are synchronous with the
data).
8.5
GPIO - Pins and Registers
The GPIO functionality of the ESAI port is controlled by three registers: Port C control register (PCRC),
Port C direction register (PRRC) and Port C data register (PDRC).
8.5.1
Port C Control Register (PCRC)
The read/write 24-bit Port C Control Register (PCRC) in conjunction with the Port C Direction Register
(PRRC) controls the functionality of the ESAI GPIO pins. Each of the PC(11:0) bits controls the
functionality of the corresponding port pin. See Table 8-12 for the port pin configurations. Hardware and
software reset clear all PCRC bits.
8.5.2
Port C Direction Register (PRRC)
The read/write 24-bit Port C Direction Register (PRRC) in conjunction with the Port C Control Register
configurations. Hardware and software reset clear all PRRC bits.
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GPIO - Pins and Registers
Table 8-12 PCRC and PRRC Bits Functionality
PDC[i]
PC[i]
Port Pin[i] Function
disconnected
GPIO input
0
0
1
1
0
1
0
1
GPIO output
ESAI
11
10
9
8
7
6
5
4
3
2
1
0
X:$FFFFBF
PC11
PC10
PC9
PC8
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
23
22
21
20
19
18
17
16
15
14
13
12
Reserved bit - read as zero; should be written with zero for future compatibility.
Figure 8-19 PCRC Register
11
10
9
8
7
6
5
4
3
2
1
0
X:$FFFFBE
PDC11 PDC10 PDC9 PDC8 PDC7 PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0
23
22
21
20
19
18
17
16
15
14
13
12
Reserved bit - read as zero; should be written with zero for future compatibility.
Figure 8-20 PRRC Register
8.5.3
Port C Data register (PDRC)
The read/write 24-bit Port C Data Register (see Figure 8-21) is used to read or write data to/from ESAI
GPIO pins. Bits PD(11:0) are used to read or write data from/to the corresponding port pins if they are
configured as GPIO. If a port pin [i] is configured as a GPIO input, then the corresponding PD[i] bit
reflects the value present on this pin. If a port pin [i] is configured as a GPIO output, then the value written
into the corresponding PD[i] bit is reflected on this pin. If a port pin [i] is configured as disconnected, the
corresponding PD[i] bit is not reset and contains undefined data.
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ESAI Initialization Examples
11
10
9
8
7
6
5
4
3
2
1
0
X:$FFFFBD
PD11
PD10
PD9
PD8
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
23
22
21
20
19
18
17
16
15
14
13
12
Reserved bit - read as zero; should be written with zero for future compatibility.
Figure 8-21 PDRC Register
8.6
ESAI Initialization Examples
8.6.1
Initializing the ESAI Using Individual Reset
•
The ESAI should be in its individual reset state (PCRC = $000 and PRRC = $000). In the individual
reset state, both the transmitter and receiver sections of the ESAI are simultaneously reset. The
TPR bit in the TCR register may be used to reset just the transmitter section. The RPR bit in the
RCR register may be used to reset just the receiver section.
•
Configure the control registers (TCCR, TCR, RCCR, RCR) according to the operating mode, but
do not enable transmitters (TE5–TE0 = $0) or receivers (RE3–RE0 = $0). It is possible to set the
interrupt enable bits which are in use during the operation (no interrupt occurs).
•
•
Enable the ESAI by setting the PCRC register and PRRC register bits according to pins which are
in use during operation.
Write the first data to be transmitted to the transmitters which are in use during operation.
This step is needed even if DMA is used to service the transmitters.
•
•
Enable the transmitters and receivers.
From now on ESAI can be serviced either by polling, interrupts, or DMA.
Operation proceeds as follows:
•
•
•
For internally generated clock and frame sync, these signals are active immediately after ESAI is
enabled (step 3 above).
Data is received only when one of the receive enable (REx) bits is set and after the occurrence of
frame sync signal (either internally or externally generated).
Data is transmitted only when the transmitter enable (TEx) bit is set and after the occurrence of
frame sync signal (either internally or externally generated). The transmitter outputs remain
tri-stated after TEx bit is set until the frame sync occurs.
8.6.2
Initializing Just the ESAI Transmitter Section
•
•
It is assumed that the ESAI is operational; that is, at least one pin is defined as an ESAI pin.
The transmitter section should be in its personal reset state (TPR = 1).
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ESAI Initialization Examples
•
Configure the control registers TCCR and TCR according to the operating mode, making sure to
clear the transmitter enable bits (TE0 - TE5). TPR must remain set.
•
•
Take the transmitter section out of the personal reset state by clearing TPR.
Write first data to the transmitters which will be used during operation. This step is needed even if
DMA is used to service the transmitters.
•
•
Enable the transmitters by setting their TE bits.
Data is transmitted only when the transmitter enable (TEx) bit is set and after the occurrence of
frame sync signal (either internally or externally generated). The transmitter outputs remain
tri-stated after TEx bit is set until the frame sync occurs.
•
From now on the transmitters are operating and can be serviced either by polling, interrupts, or
DMA.
8.6.3
Initializing Just the ESAI Receiver Section
•
•
•
It is assumed that the ESAI is operational; that is, at least one pin is defined as an ESAI pin.
The receiver section should be in its personal reset state (RPR = 1).
Configure the control registers RCCR and RCR according to the operating mode, making sure to
clear the receiver enable bits (RE0 - RE3). RPR must remain set.
•
•
•
Take the receiver section out of the personal reset state by clearing RPR.
Enable the receivers by setting their RE bits.
From now on the receivers are operating and can be serviced either by polling, interrupts, or DMA.
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9 Enhanced Serial Audio Interface 1 (ESAI_1)
9.1
Introduction
The Enhanced Serial Audio Interface I (ESAI_1) is the second ESAI peripheral in the DSP56366. It is
functionally identical to the ESAI peripheral described in Section 8, "Enhanced Serial AUDIO Interface
(ESAI)" except for minor differences described in this section. Refer to the ESAI section for functional
information about the ESAI_1, in addition to using the information in this section.
does not have the two high frequency clock pins but otherwise it is identical to the ESAI.
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Introduction
GDB DDB
TX0_1
Shift Register
TX1_1
SDO0_1 [PE11]
RSMA_1
RSMB_1
(shared with SDO0 [PC11])
TSMA_1
TSMB_1
SDO1_1 [PE10]
(shared with SDO1 [PC10])
Shift Register
TX2_1
RCCR_1
RCR_1
SDO2_1/SDI3_1 [PE9]
(shared with SDO2/SDI3 [PC9])
Shift Register
RX3_1
TCCR_1
TCR_1
TX3_1
SDO3_1/SDI2_1 [PE8]
(shared with SDO3/SDI2 [PC8])
SAICR_1
SAISR_1
Shift Register
RX2_1
TX4_1
SDO4_1/SDI1_1 [PE7]
TSR_1
Shift Register
RX1_1
Clock / Frame Sync
Generators
and
Control Logic
TX5_1
RCLK
SDO5_1/SDI0_1 [PE6]
Shift Register
RX0_1
TCLK
Figure 9-1 ESAI_1 Block Diagram
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ESAI_1 Data and Control Pins
9.2
ESAI_1 Data and Control Pins
The ESAI_1 has 6 dedicated pins and shares 4 pins with the ESAI. The pins are described in the following
sections.
9.2.1
Serial Transmit 0 Data Pin (SDO0_1)
SDO0_1 transmits data from the TX0_1 serial transmit shift register. It is shared with the ESAI SDO0
signal. The pin may be used as SDO0_1 if it is not defined as ESAI SDO0. The pin may be used as GPIO
PE11 if not used by the ESAI or ESAI_1. The ESAI_1 Multiplex Control Register (EMUXR) defines if
the pin belongs to the ESAI or to the ESAI_1.
9.2.2
Serial Transmit 1 Data Pin (SDO1_1)
SDO1_1 transmits data from the TX1_1 serial transmit shift register. It is shared with the ESAI SDO1
signal. The pin may be used as SDO1_1 if it is not defined as ESAI SDO1. The pin may be used as GPIO
PE10 if not used by the ESAI or ESAI_1. The ESAI_1 Multiplex Control Register (EMUXR) defines if
the pin belongs to the ESAI or to the ESAI_1.
9.2.3
Serial Transmit 2/Receive 3 Data Pin (SDO2_1/SDI3_1)
SDO2_1/SDI3_1 transmits data from the TX2_1 serial transmit shift register when programmed as a
transmitter pin, or receives serial data to the RX3_1 serial receive shift register when programmed as a
receiver pin. It is shared with the ESAI SDO2/SDI3 signal. The pin may be used as SDO2_1/SDI3_1 if it
is not defined as ESA I SDO2/SDI3. The pin may be used as GPIO PE9 if not used by the ESAI or ESAI_1.
The ESAI_1 Multiplex Control Register (EMUXR) defines if the pin belongs to the ESAI or to the
ESAI_1.
9.2.4
Serial Transmit 3/Receive 2 Data Pin (SDO3_1/SDI2_1)
SDO3_1/SDI2_1 transmits data from the TX3_1 serial transmit shift register when programmed as a
transmitter pin, or receives serial data to the RX2_1 serial receive shift register when programmed as a
receiver pin. It is shared with the ESAI SDO3/SDI2 signal. The pin may be used as SDO3_1/SDI2_1 if it
is not defined as ESAI SDO3/SDI2. The pin may be used as GPIO PE8 if not used by the ESAI or ESAI_1.
The ESAI_1 Multiplex Control Register (EMUXR) defines if the pin belongs to the ESAI or to the
ESAI_1.
9.2.5
Serial Transmit 4/Receive 1 Data Pin (SDO4_1/SDI1_1)
SDO4_1/SDI1_1 transmits data from the TX4_1 serial transmit shift register when programmed as a
transmitter pin, or receives serial data to the RX1_1 serial receive shift register when programmed as a
receiver pin. SDO4_1/SDI1_1 may be programmed as a general-purpose pin (PE7) when the ESAI_1
SDO4_1 and SDI1_1 functions are not being used.
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ESAI_1 Programming Model
9.2.6
Serial Transmit 5/Receive 0 Data Pin (SDO5_1/SDI0_1)
SDO5_1/SDI0_1 transmits data from the TX5_1 serial transmit shift register when programmed as
transmitter pin, or receives serial data to the RX0_1 serial shift register when programmed as a receiver
pin. SDO5_1/SDI0_1 may be programmed as a general-purpose pin (PE6) when the ESAI_1 SDO5_1 and
SDI0_1 functions are not being used.
9.2.7
Receiver Serial Clock (SCKR_1)
SCKR_1 is a bidirectional pin that provides the receivers serial bit clock for the ESAI_1 interface.
SCKR_1 may be programmed as a general-purpose I/O pin (PE0) when the ESAI_1 SCKR_1 function is
not being used.
9.2.8
Transmitter Serial Clock (SCKT_1)
SCKT_1 is a bidirectional pin that provides the transmitters serial bit clock for the ESAI_1 interface.
SCKT_1 may be programmed as a general-purpose I/O pin (PE3) when the ESAI_1 SCKT_1 function is
not being used.
9.2.9
Frame Sync for Receiver (FSR_1)
The FSR_1 pin is a bidirectional pin that provides the receivers frame sync signal for the ESAI_1 interface.
FSR_1 may be programmed as a general-purpose I/O pin (PE1) when the ESAI_1 FSR_1 function is not
being used.
9.2.10 Frame Sync for Transmitter (FST_1)
The FST_1 pin is a bidirectional pin that provides the transmitters frame sync signal for the ESAI_1
interface. FST_1 may be programmed as a general-purpose I/O pin (PE4) when the ESAI_1 FST_1
function is not being used.
9.3
ESAI_1 Programming Model
The ESAI_1 has the following registers:
•
•
•
•
•
•
•
•
One multiplex control register
Five control registers
One status register
Six transmit data registers
Four receive data registers
Two transmit slot mask registers
Two receive slot mask registers
One special-purpose time slot register
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ESAI_1 Programming Model
The ESAI_1 also contains the GPIO Port E functionality, described in Section 9.5, "GPIO - Pins and
Registers". The following paragraphs give detailed descriptions of bits in the ESAI_1 registers that differ
in functionality from their descriptions in the ESAI Programming Model.
9.3.1
ESAI_1 Multiplex Control Register (EMUXR)
The read/write ESAI_1 Multiplex Control Register (EMUXR) controls which peripheral (ESAI or
ESAI_1) is using the shared pins.
11
10
9
8
7
6
5
4
3
2
1
0
Y:$FFFFAF
EMUX3 EMUX2 EMUX1 EMUX0
23
22
21
20
19
18
17
16
15
14
13
12
Reserved bit - read as zero; should be written with zero for future compatibility.
Figure 9-2 EMUXR Register
Hardware and software reset clear all the bits of the EMUXR register. The selection of ESAI/ESAI_1 pins
Table 9-1 EMUXR ESA/ESAI_1 Pin Selection
EMUXR bit
EMUX0
ESAI pin
ESAI_1 pin
disconnected
0
1
0
1
0
1
0
1
SDO0 [PC11]
disconnected
SDO1[PC10]
disconnected
EMUX0
EMUX1
EMUX1
EMUX2
EMUX2
EMUX3
EMUX3
SDO0_1 [PE11]
disconnected
SDO1_1 [PE10]
disconnected
SDO2/SDI3 [PC9]
disconnected
SDO2_1/SDI3_1 [PE9]
disconnected
SDO3/SDI2 [PC8]
disconnected
SDO3_1/SDI2_1 [PE8]
9.3.2
ESAI_1 Transmitter Clock Control Register (TCCR_1)
The read/write Transmitter Clock Control Register (TCCR_1) controls the ESAI_1 transmitter clock
generator bit and frame sync rates, the bit rate and high frequency clock sources and the directions of the
FST_1 and SCKT_1 signals. In synchronous mode, the bit clock defined for the transmitter determines the
receiver bit clock as well. TCCR_1 also controls the number of words per frame for the serial data.
Hardware and software reset clear all the bits of the TCCR_1 register.
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ESAI_1 Programming Model
11
10
9
8
7
6
5
4
3
2
1
0
Y:$FFFF96
TDC2 TDC1 TDC0 TPSR TPM7 TPM6 TPM5 TPM4 TPM3 TPM2 TPM1 TPM0
23
22
21
20
19
18
17
16
15
14
13
12
THCKD TFSD TCKD THCKP TFSP TCKP TFP3
TFP2
TFP1
TFP0 TDC4 TDC3
Figure 9-3 TCCR_1 Register
9.3.2.1
TCCR_1 Tx High Freq. Clock Divider (TFP3-TFP0) - Bits 14–17
Since the ESAI_1 does not have the transmitter high frequency clock pin, the TFP3–TFP0 bits simply
9.3.2.2
TCCR_1 Tx High Freq. Clock Polarity (THCKP) - Bit 20
The ESAI_1 does not have the transmitter high frequency clock pin. It it recommended that THCKP
should be kept cleared.
9.3.2.3
TCCR_1 Tx High Freq. Clock Direction (THCKD) - Bit 23
The ESAI_1 does not have the transmitter high frequency clock pin. THCKD must be set for proper
ESAI_1 transmitter section operation.
Table 9-2 Transmitter Clock Sources
Transmitter
THCKD
TFSD
TCKD
Bit Clock
Source
OUTPUTS
0
1
1
1
1
X
0
0
1
1
X
0
1
0
1
Reserved
SCKT_1
INT
SCKT_1
SCKT_1
SCKT_1
INT
FST_1
FST_1
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ESAI_1 Programming Model
RHCKD=1
PRESCALE
DIVIDE BY
DIVIDER
DIVIDE BY
1
DIVIDER
DIVIDE BY
1
F
OSC
DIVIDE
BY 2
1
OR
TO DIVIDE
TO DIVIDE
RPSR
RPM0 - RPM7
RFP0 - RFP3
FLAG0 OUT
(SYNC MODE)
FLAG0 IN
(SYNC MODE)
INTERNAL BIT CLOCK
RSWS4-RSWS0
RX WORD
CLOCK
RX WORD
LENGTH DIVIDER
SYN=1
SYN=0
SCKR_1
RCKD
RX SHIFT REGISTER
TSWS4-TSWS0
RCLOCK
TCLOCK
SYN=0
SYN=1
INTERNAL BIT CLOCK
TX WORD
LENGTH DIVIDER
TX WORD
CLOCK
SCKT_1
TCKD
TX SHIFT REGISTER
TFP0 - TFP3
TPSR
TPM0 - TPM7
DIVIDER
DIVIDE BY
1
PRESCALE
DIVIDE BY
DIVIDER
DIVIDE BY
1
DIVIDE
BY 2
1
OR
F
TO DIVIDE
OSC
TO DIVIDE
THCKD=1
Notes:
1. F
is the DSP56300 Core internal clock frequency.
OSC
Figure 9-4 ESAI_1 Clock Generator Functional Block Diagram
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ESAI_1 Programming Model
RDC0 - RDC4
RX WORD
RFSL
CLOCK
RECEIVER
FRAME RATE
DIVIDER
INTERNAL RX FRAME CLOCK
SYNC
TYPE
RFSD
SYN=0
SYN=1
RFSD=1
SYN=0
FSR_1
RECEIVE
CONTROL
LOGIC
RECEIVE
FRAME SYNC
RFSD=0
SYN=1
FLAG1 IN
(SYNC MODE)
FLAG1OUT
(SYNC MODE)
TDC0 - TDC4
TFSL
TFSD
TX WORD
CLOCK
TRANSMITTER
FRAME RATE
DIVIDER
INTERNAL TX FRAME CLOCK
SYNC
TYPE
FST_1
TRANSMIT
CONTROL
LOGIC
TRANSMIT
FRAME SYNC
Figure 9-5 ESAI_1 Frame Sync Generator Functional Block Diagram
9.3.3
ESAI_1 Transmit Control Register (TCR_1)
The read/write Transmit Control Register (TCR_1) controls the ESAI_1 transmitter section. Interrupt
enable bits for the transmitter section are provided in this control register. Operating modes are also
selected in this register.
11
10
9
8
7
6
5
4
3
2
1
0
Y:$FFFF95
TSWS1 TSWS0 TMOD1 TMOD0 TWA TSHFD TE5
TE4
TE3
TE2
TE1
TE0
23
22
21
20
19
18
17
16
15
14
13
12
TLIE
TIE
TEDIE TEIE
TPR
PADC TFSR TFSL TSWS4 TSWS3 TSWS2
Reserved bit - read as zero; should be written with zero for future compatibility.
Figure 9-6 TCR_1 Register
Hardware and software reset clear all the bits in the TCR_1 register.
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ESAI_1 Programming Model
9.3.4
ESAI_1 Receive Clock Control Register (RCCR_1)
The read/write Receive Clock Control Register (RCCR_1) controls the ESAI_1 receiver clock generator
bit and frame sync rates, word length, and number of words per frame for the serial data.
11
10
9
8
7
6
5
4
3
2
1
0
Y:$FFFF98
RDC2 RDC1 RDC0 RPSR RPM7 RPM6 RPM5 RPM4 RPM3 RPM2 RPM1 RPM0
23
22
21
20
19
18
17
16
15
14
13
12
RHCKD RFSD RCKD RHCKP RFSP RCKP RFP3 RFP2 RFP1 RFP0 RDC4 RDC3
Reserved bit - read as zero; should be written with zero for future compatibility.
Figure 9-7 RCCR_1 Register
Hardware and software reset clear all the bits of the RCCR_1 register.
9.3.4.1 RCCR_1 Rx High Freq. Clock Divider (RFP3-RFP0) - Bits 14–17
Since the ESAI_1 does not have the receiver high frequency clock pin, the RFP3–RFP0 bits simply specify
9.3.4.2
RCCR_1 Rx High Freq. Clock Polarity (RHCKP) - Bit 20
The ESAI_1 does not have the receiver high frequency clock pin. It it recommended that RHCKP should
be kept cleared.
9.3.4.3
RCCR_1 Rx High Freq. Clock Direction (RHCKD) - Bit 23
The ESAI_1 does not have the receiver high frequency clock pin. RHCKD must be set for proper ESAI_1
receiver section operation.
Table 9-3 Receiver Clock Sources (asynchronous mode only)
Receiver
RHCKD
RFSD
RCKD
Bit Clock
Source
OUTPUTS
0
1
1
1
1
X
0
0
1
1
X
0
1
0
1
Reserved
SCKR_1
INT
SCKR_1
SCKR_1
SCKR_1
INT
FSR_1
FSR_1
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ESAI_1 Programming Model
9.3.5
ESAI_1 Receive Control Register (RCR_1)
The read/write Receive Control Register (RCR_1) controls the ESAI_1 receiver section.
11
10
9
8
7
6
5
4
3
2
1
0
Y:$FFFF97
RSWS1 RSWS0 RMOD RMOD RWA RSHFD
RE3
RE2
RE1
RE0
23
22
21
20
19
18
17
16
15
14
13
12
RLIE
RIE
REDIE REIE
RPR
RFSR RFSL RSWS4 RSWS3 RSWS2
Reserved bit - read as zero; should be written with zero for future compatibility.
Figure 9-8 RCR_1 Register
Hardware and software reset clear all the bits in the RCR_1 register.
9.3.6
ESAI_1 Common Control Register (SAICR_1)
The read/write Common Control Register (SAICR_1) contains control bits for functions that use both the
receive and transmit sections of the ESAI_1.
11
23
10
22
9
8
7
6
5
4
3
2
1
0
Y:$FFFF94
ALC
TEBE
SYN
OF2
OF1
OF0
21
20
19
18
17
16
15
14
13
12
Reserved bit - read as zero; should be written with zero for future compatibility.
Figure 9-9 SAICR_1 Register
Hardware and software reset clear all the bits in the SAICR_1 register.
9.3.7
ESAI_1 Status Register (SAISR_1)
The Status Register (SAISR_1) is a read-only status register used by the DSP to read the status and serial
input flags of the ESAI_1.
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ESAI_1 Programming Model
11
23
10
9
8
7
6
5
4
3
2
1
0
Y:$FFFF93
RODF REDF
RDF
ROE
RFS
IF2
IF1
IF0
22
21
20
19
18
17
16
15
14
13
12
TODE TEDE
TDE
TUE
TFS
Reserved bit - read as zero; should be written with zero for future compatibility.
Figure 9-10 SAISR_1 Register
9.3.8
ESAI_1 Receive Shift Registers
The receive shift registers receive the incoming data from the serial receive data pins. Data is shifted in by
the selected (internal/external) bit clock when the associated frame sync I/O is asserted. Data is assumed
to be received MSB first if RSHFD=0 and LSB first if RSHFD=1. Data is transferred to the ESAI_1
receive data registers after 8, 12, 16, 20, 24, or 32 serial clock cycles were counted, depending on the slot
length control bits in the RCR_1 register.
9.3.9
ESAI_1 Receive Data Registers
The Receive Data Registers RX3_1, RX2_1, RX1_1, and RX0_1 are 24-bit read-only registers that accept
data from the receive shift registers when they become full. The data occupies the most significant portion
of the receive data registers, according to the ALC control bit setting. The unused bits (least significant
portion, and 8 most significant bits when ALC=1) read as zeros. The DSP is interrupted whenever RXx_1
becomes full if the associated interrupt is enabled.
9.3.10 ESAI_1 Transmit Shift Registers
The Transmit Shift Registers contain the data being transmitted. Data is shifted out to the serial transmit
data pins by the selected (internal/external) bit clock when the associated frame sync I/O is asserted. The
number of bits shifted out before the shift registers are considered empty and may be written to again can
be 8, 12, 16, 20, 24 or 32 bits (determined by the slot length control bits in the TCR_1 register). Data is
shifted out of these registers MSB first if TSHFD=0 and LSB first if TSHFD=1.
9.3.11 ESAI_1 Transmit Data Registers
The Transmit Data registers TX5_1, TX4_1, TX3_1, TX2_1, TX1_1, and TX0_1 are 24-bit write-only
registers. Data to be transmitted is written into these registers and is automatically transferred to the
transmit shift registers. The data written (8, 12, 16, 20 or 24 bits) should occupy the most significant
portion of the TXx_1 according to the ALC control bit setting. The unused bits (least significant portion,
and the 8 most significant bits when ALC=1) of the TXx_1 are don’t care bits. The DSP is interrupted
whenever the TXx_1 becomes empty if the transmit data register empty interrupt has been enabled.
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ESAI_1 Programming Model
9.3.12 ESAI_1 Time Slot Register (TSR_1)
The write-only Time Slot Register (TSR_1) is effectively a null data register that is used when the data is
not to be transmitted in the available transmit time slot. The transmit data pins of all the enabled
transmitters are in the high-impedance state for the respective time slot where TSR_1 has been written.
The Transmitter External Buffer Enable pin (FSR_1 pin when SYN=1, TEBE=1, RFSD=1) disables the
external buffers during the slot when the TSR_1 register has been written.
9.3.13 Transmit Slot Mask Registers (TSMA_1, TSMB_1)
The Transmit Slot Mask Registers (TSMA_1 and TSMB_1) are two read/write registers used by the
transmitters in network mode to determine for each slot whether to transmit a data word and generate a
transmitter empty condition (TDE=1), or to tri-state the transmitter data pins. TSMA_1 and TSMB_1
should each be considered as containing half a 32-bit register TSM_1. See Figure 9-11 and Figure 9-12.
Bit number N in TSM_1 (TS**) is the enable/disable control bit for transmission in slot number N.
11
10
9
8
7
6
5
4
3
2
1
0
Y:$FFFF99
TS11
TS10
TS9
TS8
TS7
TS6
TS5
TS4
TS3
TS2
TS1
TS0
23
22
21
20
19
18
17
16
15
14
13
12
TS15
TS14
TS13
TS12
Reserved bit - read as zero; should be written with zero for future compatibility.
Figure 9-11 TSMA_1 Register
11
10
9
8
7
6
5
4
3
2
1
0
Y:$FFFF9A
TS27
TS26
TS25
TS24
TS23
TS22
TS21
TS20
TS19
TS18
TS17
TS16
23
22
21
20
19
18
17
16
15
14
13
12
TS31
TS30
TS29
TS28
Reserved bit - read as zero; should be written with zero for future compatibility.
Figure 9-12 TSMB_1 Register
9.3.14 Receive Slot Mask Registers (RSMA_1, RSMB_1)
The Receive Slot Mask Registers (RSMA_1 and RSMB_1) are two read/write registers used by the
receiver in network mode to determine for each slot whether to receive a data word and generate a receiver
full condition (RDF=1), or to ignore the received data. RSMA_1 and RSMB_1 should be considered as
RSM_1 (RS**) is an enable/disable control bit for receiving data in slot number N.
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Operating Modes
11
10
9
8
7
6
5
4
3
2
1
0
Y:$FFFF9B
RS11
RS10
RS9
RS8
RS7
RS6
RS5
RS4
RS3
RS2
RS1
RS0
23
22
21
20
19
18
17
16
15
14
13
12
RS15
RS14
RS13
RS12
Reserved bit - read as zero; should be written with zero for future compatibility.
Figure 9-13 RSMA_1 Register
11
10
9
8
7
6
5
4
3
2
1
0
Y:$FFFF9C
RS27
RS26
RS25
RS24
RS23
RS22
RS21
RS20
RS19
RS18
RS17
RS16
23
22
21
20
19
18
17
16
15
14
13
12
RS31
RS30
RS29
RS28
Reserved bit - read as zero; should be written with zero for future compatibility.
Figure 9-14 RSMB_1 Register
9.4
Operating Modes
ESAI_1 After Reset
9.4.1
Hardware or software reset clears the EMUXR register, the port E control register bits and the port E
direction control register bits, which configure all 6 ESAI_1 dedicated I/O pins as disconnected, and all 4
shared pins as belonging to the ESAI. The ESAI_1 is in the individual reset state while all ESAI_1 signals
are programmed as general-purpose I/O or disconnected, and is active only if at least one of the ESAI_1
I/O pins is programmed as belonging to the ESAI_1.
9.5
GPIO - Pins and Registers
The GPIO functionality of the ESAI_1 port is controlled by three registers: Port E Control register
(PCRE), Port E Direction register (PRRE) and Port E Data register (PDRE).
9.5.1
Port E Control Register (PCRE)
The read/write 24-bit Port E Control Register (PCRE) in conjunction with the Port E Direction Register
(PRRE) controls the functionality of the ESAI_1 GPIO pins. Each of the PE(11:0) bits controls the
functionality of the corresponding port pin. See Table 9-4 for the port pin configurations. Hardware and
software reset clear all PCRE bits.
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GPIO - Pins and Registers
9.5.2
Port E Direction Register (PRRE)
The read/write 24-bit Port E Direction Register (PRRE) in conjunction with the Port E Control Register
configurations. Hardware and software reset clear all PRRE bits.
Table 9-4 PCRE and PRRE Bits Functionality
PDE[i]
PE[i]
Port Pin[i] Function
disconnected
GPIO input
0
0
1
1
0
1
0
1
GPIO output
ESAI_1
11
10
9
8
7
6
5
4
3
2
1
0
Y:$FFFF9F
PE11
PE10
PE9
PE8
PE7
PE6
PE4
PE3
PE1
PE0
23
22
21
20
19
18
17
16
15
14
13
12
Reserved bit - read as zero; should be written with zero for future compatibility.
Figure 9-15 PCRE Register
11
10
9
8
7
6
5
4
3
2
1
0
Y:$FFFF9E
PDE11 PDE10 PDE9 PDE8 PDE7 PDE6
PDE4 PDE3
PDE1 PDE0
23
22
21
20
19
18
17
16
15
14
13
12
Reserved bit - read as zero; should be written with zero for future compatibility.
Figure 9-16 PRRE Register
9.5.3
Port E Data register (PDRE)
The read/write 24-bit Port E Data Register (see Figure 9-17) is used to read or write data to/from ESAI_1
GPIO pins. Bits PD(11:0) are used to read or write data from/to the corresponding port pins if they are
configured as GPIO. If a port pin [i] is configured as a GPIO input, then the corresponding PD[i] bit will
reflect the value present on this pin. If a port pin [i] is configured as a GPIO output, then the value written
into the corresponding PD[i] bit will be reflected on this pin. If a port pin [i] is configured as disconnected,
the corresponding PD[i] bit is not reset and contains undefined data.
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GPIO - Pins and Registers
11
10
9
8
7
6
5
4
3
2
1
0
Y:$FFFF9D
PD11
PD10
PD9
PD8
PD7
PD6
PD4
PD3
PD1
PD0
23
22
21
20
19
18
17
16
15
14
13
12
Reserved bit - read as zero; should be written with zero for future compatibility.
Figure 9-17 PDRE Register
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GPIO - Pins and Registers
NOTES
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10 Digital Audio Transmitter
10.1 Introduction
The Digital Audio Transmitter (DAX) is a serial audio interface module that outputs digital audio data in
the AES/EBU, CP-340 and IEC958 formats. Some of the key features of the DAX are listed below.
•
Operates on a frame basis—The DAX can handle one frame (consisting of two subframes) of
audio and non-audio data at a time.
•
Double-buffered audio and non-audio data—The DAX data path is double-buffered so the next
frame data can be stored in the DAX without affecting the frame currently being transmitted.
•
•
Direct Memory Access—Audio data and non-audio data can be written to the DAX using DMA.
Programmable clock source—Users can select the DAX clock source, and this selection
configures the DAX to operate in slave or master mode.
•
•
Supports both master mode and slave mode in a digital audio network—If the user selects a
divided DSP core clock, the DAX will operate in the master mode. If the user selects an external
clock source, the DAX will operate in the slave mode.
GPIO—Each of the two DAX pins can be configured as either GPIO or as specific DAX pin. Each
pin is independent of the other. However, at least one of the two pins must be selected as a DAX
pin to release the DAX from reset.
The accessible DAX registers are all mapped in the X I/O memory space. This allows programmers to
access the DAX using standard instructions and addressing modes. Interrupts generated by the DAX can
be handled with a fast interrupt for cases in which the non-audio data does not change from frame to frame.
When the DAX interrupts are disabled, they can still be served by DMA or by a “polling” technique. A
NOTE
instructions.
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DAX Signals
Global Data Bus
DMA Bus
23
0
23
23
0
0
23
0
XSTR
XNADR
Upload
XCTR
XADR
XADBUFB
XADBUFA
26
23
0
C-U-V
XADSR
Biphase
Encoder
ADO
ACI
PRTYG
MUX
Preamble
Generator
XNADBUF
DAX
State
Machine
DAX
Clock
MUX
Control
Signals
DAX
Clocks
DSP
Core Clock
Figure 10-1 Digital Audio Transmitter (DAX) Block Diagram
10.2 DAX Signals
The DAX has two signal lines:
•
DAX Digital Audio Output (ADO/PD1)—The ADO pin sends audio and non-audio data in the
AES/EBU, CP340, and IEC958 formats in a biphase mark format. The ADO pin may also be used
as a GPIO pin PD1 if the DAX is not operational.
•
DAX Clock Input (ACI/PD0)—When the DAX clock is configured to be supplied externally, the
external clock is applied to the ACI pin. The frequency of the external clock must be 256 times,
384 times, or 512 times the audio sampling frequency (256 × Fs, 384 × Fs, or 512 × Fs). The ACI
pin may also be used as a GPIO pin PD0 when the DAX is disabled or when operating from the
internal DSP clock.
10.3 DAX Functional Overview
The DAX consists of the following:
•
•
•
•
•
•
•
Audio data register (XADR)
Two audio data buffers (XADBUFA and XADBUFB)
Non-audio data register (XNADR)
Non-audio data buffer (XNADBUF)
Audio and non-audio data shift register (XADSR)
Control register (XCTR)
Status register (XSTR)
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DAX Programming Model
•
•
•
•
•
Parity generator (PRTYG)
Preamble generator
Biphase encoder
Clock multiplexer
Control state machine
XADR, XADBUFA, XADBUFB and XADSR creates a FIFO-like data path. Channel A is written to
XADR and moves to XADBUFA. Then channel B is written to XADR, and when XADBUFB empties
XADR moves into it. XADBUFA moves to the shift register XADSR when XADSR has shifted out its last
bit. After channel A audio and non-audio data has been shifted out, XADBUFB moves into XADSR, and
channel B audio and non audio shift begins.
The frame non-audio data (stored in XNADR) is transferred to the XADSR (for channel A) and to the
XNADBUF registers (for channel B) at the beginning of a frame transmission. This is called an “upload.”
The DAX audio data register empty (XADE) flag is set when XADR and XADBUFA are empty, and, if
the audio data register empty interrupt is enabled (XDIE=1), an interrupt request is sent to the DSP core.
The interrupt handling routine then sends the non-audio data bits to XNADR and the next frame of audio
data to XADR (two subframes).
At the beginning of a frame transmission, one of the 8-bit channel A preambles (Z-preamble for the first
subframe in a block, or X-preamble otherwise) is generated in the preamble generator, and then shifted out
to the ADO pin in the first eight time slots. The preamble is generated in biphase mark format. The
twenty-four audio and three non-audio data bits in the XADSR are shifted out to the biphase encoder,
which shifts them out through the ADO pin in the biphase mark format in the next 54 time slots. The parity
generator calculates an even parity over the 27 bits of audio and non-audio data, and then outputs the result
through the biphase encoder to the ADO pin at the last two time slots. This is the end of the first (channel
A) subframe transmission.
The second subframe transmission (channel B) starts with the preamble generator generating the channel
B preamble (Y-preamble). At the same time, channel B audio and non-audio data is transferred to the
XADSR shift-register from the XADBUFB and XNADBUF registers. The generated Y-preamble is output
immediately after the channel A parity and is followed by the audio and non-audio data in the XADSR,
which is in turn followed by the calculated parity for channel B. This completes a frame transmission.
When the channel B parity is sent, the audio data for the next frame, stored in XADBUFA and the
non-audio data bits from the XNADR, are uploaded to XADSR.
10.4 DAX Programming Model
The programmer-accessible DAX registers are shown in Figure 10-2. The registers are described in the
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DAX Internal Architecture
Table 10-1 DAX Interrupt Vectors
Address
Condition
Description
XAUR
XADE & XBLK
XADE
VBA:$28
VBA:$2A
VBA:$2E
DAX transmit underrun error
DAX block transferred
DAX audio data register empty
Table 10-2 DAX Interrupt Priority
Priority
Interrupt
DAX transmit underrun error
DAX block transferred
highest
lowest
DAX audio data register empty
10.5 DAX Internal Architecture
XCTR - Control Register - X:$FFFFD0
23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
XSB XCS1 XCS0 XBIE XUIE XDIE
XNADR - Non-Audio Data Register - X:$FFFFD1
23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
XCB XUB XVB XCA XUA XVA
XADRA - Audio Data Register A - X:$FFFFD2 and XADRB - Audio Data Register B -X:$FFFFD3
23
0
0
XSTR - Status Register - X:$FFFFD4
23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
XBLK XAURXADE
Reserved bit
Figure 10-2 DAX Programming Model
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DAX Internal Architecture
10.5.1 DAX Audio Data Register (XADR)
XADR is a 24-bit write-only register. One frame of audio data, which is to be transmitted in the next frame
slot, is transferred to this register. Successive write accesses to this register will store channel A and
channel B alternately in XADBUFA and in XADBUFB respectively. When XADR and XADBUFA are
empty, XADE bit in the XSTR is set, and, if the audio data register empty interrupt is enabled (XDIE=1),
an interrupt request is sent to the DSP core. When channel B is transferred to XADR, the XADE bit in the
XSTR is cleared. XADR can also be accessed by DMA. When XADR and XADBUFA are empty, the
DAX sends a DMA request to the core. The DMA first transfers non-audio data bits to XNADR (optional),
then transfers channel A and channel B to XADR. The XADR can be accessed with two different
successive addresses. This feature supports sending non-audio data bits, channel A and channel B to the
DAX in three successive DMA transfers.
10.5.2 DAX Audio Data Buffers (XADBUFA / XADBUFB)
XADBUFA and XADBUFB are 24-bit registers that buffer XADR from XADSR, creating a FIFO-like
data path. These registers hold the next two subframes of audio data to be transmitted. Channel A audio
data is transferred from XADR to XADBUFA if XADBUFA is empty. Channel B audio data is transferred
from XADR to XADBUFB if XADBUFB is empty. Audio data is transferred from XADBUFA and
XADBUFB alternately to XADSR provided that XADSR shifted out all the audio and non-audio bits of
the currently transmitted channel. This buffering mechanism provides more cycles for writing the next
audio data to XADR. These registers are not directly accessible by DSP instructions.
10.5.3 DAX Audio Data Shift Register (XADSR)
The XADSR is a 27-bit shift register that shifts the 24-bit audio data and the 3-bit non-audio data for one
subframe. The contents of XADBUFA or XADBUFB are directly transferred to the XADSR at the
beginning of the subframe transmission. The channel A subframe is transferred to XADSR at the same
time that the three bits of non-audio data (V-bit, U-bit and C-bit) for channel A in the DAX non-audio data
register (XNADR) are transferred to the three highest-order bits of the XADSR. At the beginning of the
channel B transmission, audio and non-audio data for channel B are transferred from the XADBUFB and
the XNADBUF to the XADSR for shifting. The data in the XADSR is shifted toward the lowest-order bit
at the fifth to thirty-first bit slot of each subframe transmission. This register is not directly accessible by
DSP instructions.
10.5.4 DAX Non-Audio Data Register (XNADR)
The XNADR is a 24-bit write-only register. It holds the three bits of non-audio data for each subframe.
XNADR can be accessed by core instructions or by DMA. The contents of the XNADR are shown in
Figure 10-2. XNADR is not affected by any of the DAX reset states. The XNADR bits are described in
the following paragraphs.
10.5.4.1 DAX Channel A Validity (XVA)—Bit 10
The value of the XVA bit is transmitted as the twenty-ninth bit (Bit 28) of channel A subframe in the next
frame.
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DAX Internal Architecture
10.5.4.2 DAX Channel A User Data (XUA)—Bit 11
The value of the XUA bit is transmitted as the thirtieth bit (Bit 29) of the channel A subframe in the next
frame.
10.5.4.3 DAX Channel A Channel Status (XCA)—Bit 12
The value of the XCA bit is transmitted as the thirty-first bit (Bit 30) of the channel A subframe in the next
frame.
10.5.4.4 DAX Channel B Validity (XVB)—Bit 13
The value of the XVB bit is transmitted as the twenty-ninth bit (Bit 28) of the channel B subframe in the
next frame.
10.5.4.5 DAX Channel B User Data (XUB)—Bit 14
The value of the XUB bit is transmitted as the thirtieth bit (Bit 29) of the channel B subframe in the next
frame.
10.5.4.6 DAX Channel B Channel Status (XCB)—Bit 15
The value of the XCB bit is transmitted as the thirty-first bit (Bit 30) of the channel B subframe in the next
frame.
10.5.4.7 XNADR Reserved Bits—Bits 0-9, 16–23
These XNADR bits are reserved. They read as 0, and should be written with 0 to ensure compatibility with
future device versions.
10.5.5 DAX Non-Audio Data Buffer (XNADBUF)
The XNADBUF is a 3-bit register that temporarily holds channel B non-audio data (XVB, XUB and XCB)
for the current transmission while the channel A data is being transmitted. This mechanism provides
programmers more instruction cycles to store the next frame’s non-audio data to the XCB, XUB, XVB,
XCA, XUA and XVA bits in the XNADR. The data in the XNADBUF register is transferred to the
XADSR along with the contents of the XADBUF register at the beginning of channel B transmission.
NOTE
The XNADBUF register is not directly accessible by DSP instructions.
10.5.6 DAX Control Register (XCTR)
The XCTR is a 24-bit read/write register that controls the DAX operation. The contents of the XCTR are
shown in Figure 10-2. XCTR is cleared by software reset and hardware reset. The XCTR bits are described
in the following paragraphs.
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DAX Internal Architecture
10.5.6.1 Audio Data Register Empty Interrupt Enable (XDIE)—Bit 0
When the XDIE bit is set, the audio data register empty interrupt is enabled and sends an interrupt request
signal to the DSP if the XADE status bit is set. When XDIE bit is cleared, this interrupt is disabled.
10.5.6.2 Underrun Error Interrupt Enable (XUIE)—Bit 1
When the XUIE bit is set, the underrun error interrupt is enabled and sends an interrupt request signal to
the DSP if the XAUR status bit is set. When XUIE bit is cleared, this interrupt is disabled.
10.5.6.3 Block Transferred Interrupt Enable (XBIE)—Bit 2
When the XBIE bit is set, the block transferred interrupt is enabled and sends an interrupt request signal
to the DSP if the XBLK and XADE status bits are set. When XBIE bit is cleared, this interrupt is disabled.
10.5.6.4 DAX Clock Input Select (XCS[1:0])—Bits 3–4
configurations selected by these bits. These bits should be changed only when the DAX is disabled.
Table 10-3 Clock Source Selection
XCS1
XCS0
DAX Clock Source
DSP Core Clock (f = 1024 x fs)
ACI Pin, f = 256 x fs
0
0
1
1
0
1
0
1
ACI Pin, f = 384 x fs
ACI Pin, f = 512 x fs
10.5.6.5 DAX Start Block (XSB)—Bit 5
The XSB bit forces the DAX to start a new block. When this bit is set, the next frame will start with “Z”
preamble and will start a new block even though the current block was not finished. This bit is cleared
when the new block starts.
10.5.6.6 XCTR Reserved Bits—Bits 6-23
These XCTR bits are reserved. They read as 0 and should be written with 0 for future compatibility.
10.5.7 DAX Status Register (XSTR)
The XSTR is a 24-bit read-only register that contains the DAX status flags. The contents of the XSTR are
shown in Figure 10-2. XSTR is cleared by software reset, hardware reset an by the stop state. The XSTR
bits are described in the following paragraphs.
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DAX Internal Architecture
10.5.7.1 DAX Audio Data Register Empty (XADE)—Bit 0
The XADE status flag indicates that the DAX audio data register XADR and the audio data buffer
XADBUFA are empty (and ready to receive the next frame’s audio data). This bit is set at the beginning
of every frame transmission (more precisely, when channel A audio data is transferred from XADBUFA
to XADSR). When XADE is set and the interrupt is enabled (XDIE = 1), an audio data register empty
interrupt request is sent to the DSP core. XADE is cleared by writing two channels of audio data to XADR.
10.5.7.2 DAX Transmit Underrun Error Flag (XAUR)—Bit 1
The XAUR status flag is set when the DAX audio data buffers XADBUFA or XADBUFB are empty and
the respective audio data upload occurs. When a DAX underrun error occurs, the previous frame data will
be retransmitted in both channels. When XAUR is set and the interrupt is enabled (XUIE = 1), an underrun
error interrupt request is sent to the DSP core. This allows programmers to write an exception handling
routine for this special case. The XAUR bit is cleared by reading the XSTR register with XAUR set,
followed by writing two channels of audio data to XADR.
10.5.7.3 DAX Block Transfer Flag (XBLK)—Bit 2
The XBLK flag indicates that the frame being transmitted is the last frame in a block. This bit is set at the
beginning of the transmission of the last frame (the 191st frame). This bit does not cause any interrupt.
However, if XBIE=1 it causes a change in the interrupt vector sent to DSP core in the event of an audio
data register empty interrupt, so that a different interrupt routine can be called (providing the next
non-audio data structures for the next block as well as storing audio data for the next frame). Writing two
channels of audio data to XADR clears this bit.
Frame #000 #001 #002 #003 #004 #005 #006 #007 #008 #009 #010 #011 #012 #013 #014 #015 #016 #017 #018 #019 #020 #021 #022 #023
XADE
XBLK
Frame #024 #025 #026 #027 #028 #029 #030 #031 #032 #033 #034 #035 #036 #037 #038 #039 #040 #041 #042 #043 #044 #045 #046 #047
XADE
XBLK
Frame #168 #169 #170 #171 #172 #173 #174 #175 #176 #177 #178 #179 #180 #181 #182 #183 #184 #185 #186 #187 #188 #189 #190 #191
XADE
XBLK
AA0608
Figure 10-3 DAX Relative Timing
10.5.7.4 XSTR Reserved Bits—Bits 3–23
These XSTR bits are reserved. They read as 0, and should be written with 0 to ensure compatibility with
future device versions.
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DAX Internal Architecture
10.5.8 DAX Parity Generator (PRTYG)
The PRTYG generates the parity bit for the subframe being transmitted. The generated parity bit ensures
that subframe bits four to thirty-one will carry an even number of ones and zeroes.
10.5.9 DAX Biphase Encoder
The DAX biphase encoder encodes each audio and non-audio bit into its biphase mark format and shifts
this encoded data out to the ADO output pin synchronously to the biphase clock.
10.5.10 DAX Preamble Generator
The DAX preamble generator automatically generates one of three preambles in the 8-bit preamble shift
register at the beginning of each subframe transmission, and shifts it out. The generated preambles always
start with “0”. Bit patterns of preambles generated in the preamble generator are shown in Table 10-4. The
preamble bits are already in the biphase mark format.
Table 10-4 Preamble Bit Patterns
Preamble
Bit Pattern
00011101
00011011
00010111
Channel
X
Y
Z
A
B
A (first in block)
There is no programmable control for the preamble selection. The first subframe to be transmitted
(immediately after the DAX is enabled) is the beginning of a block, and therefore it has a “Z” preamble.
This is followed by the second subframe, which has an “Y” preamble. After that, “X” and “Y” preambles
are transmitted alternately until the end of the block transfer (192 frames transmitted). See Figure 10-4 for
an illustration of the preamble sequence.
DAX
Enabled
Here
Z
Y
X
Y
X
Y
X
Y
Z
Y
X
Y
First Block (384 subframes)
Figure 10-4 Preamble sequence
Second Block
AA0609k
10.5.11 DAX Clock Multiplexer
The DAX clock multiplexer selects one of the clock sources and generates the biphase clock (128 × Fs)
and shift clock (64 × Fs). The clock source can be selected from the following options (see also
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DAX Programming Considerations
•
•
•
•
The internal DSP core clock—assumes 1024 × Fs
DAX clock input pin (ACI)—512 × Fs
DAX clock input pin (ACI)—384 × Fs
DAX clock input pin (ACI)—256 × Fs
Figure 10-5 shows how each clock is divided to generate the biphase and bit shift clocks
DSP Core Clock
1/4
(1024 × Fs)
ACI Pin
{256,384,512} × Fs
0
1
0
1
Biphase
Clock
1
0
1/2
1/2
2/3
(128 × Fs)
Bit Shift
Clock
(64 × Fs)
(XCS1 or XCS0)
1/2
XCS0
XCS1
AA0610
Figure 10-5 Clock Multiplexer Diagram
NOTE
For proper operation of the DAX, the DSP core clock frequency must be at
least five times higher than the DAX bit shift clock frequency (64 × Fs).
10.5.12 DAX State Machine
The DAX state machine generates a set of sequencing signals used in the DAX.
10.6 DAX Programming Considerations
The following sections describe programming considerations for the DAX.
10.6.1 Initiating A Transmit Session
To initiate the DAX operation, follow this procedure:
1. Ensure that the DAX is disabled (PC1 and PC0 bits of port control register PCR are cleared)
2. Write the non-audio data to the corresponding bits in the XNADR register
3. Write the channel A and channel B audio data in the XADR register
4. Write the transmit mode to the XCTR register
5. Enable DAX by setting PC1 bit (and by setting PC0 bit if in slave mode) in the port control register
(PCR); transmission begins.
10.6.2 Audio Data Register Empty Interrupt Handling
When the XDIE bit is set and the DAX is active, an audio data register empty interrupt (XADE = 1) is
generated once at the beginning of every frame transmission. Typically, within an XADE interrupt, the
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DAX Programming Considerations
non-audio data bits of the next frame are stored in XNADR and one frame of audio data to be transmitted
in the next frame is stored in the FIFO by two consecutive MOVEP instructions to XADR. If the non-audio
bits are not changed from frame to frame, this procedure can be handled within a fast interrupt routine.
Storing the next frame’s audio data in the FIFO clears the XADE bit in the XSTR.
10.6.3 Block Transferred Interrupt Handling
An interrupt with the XBLK vector indicates the end of a block transmission and may require some
computation to provide the next non-audio data structures that are to be transmitted within the next block.
Within the routine, the next audio data can be stored in the FIFO by two consecutive MOVEP instructions
to XADR, and the next non-audio data can be stored in the XNADR. The XBLK interrupt occurs only if
the XBIE bit in XCTR is set. If XBIE is cleared, a XADE interrupt vector will take place.
10.6.4 DAX operation with DMA
During DMA transfers, the XDIE bit of the XCTR must be cleared to avoid XADE interrupt services by
the DSP core. The initialization appearing in Section 10.6.1, "Initiating A Transmit Session" is relevant
for DMA operation. DMA transfers can be performed with or without changing non-audio bits from frame
Table 10-5 Examples of DMA configuration
Register
Non-audio data bits change
Non-audio data bits do not change
DCR2
DE=1; Enable DMA channel.
DE=1; Enable DMA channel.
DIE=1; Enable DMA interrupt.
DTM[2:0]=010; Line transfer mode.
D3D=0; Not 3D.
DIE=1; Enable DMA interrupt.
DTM[2:0]=010; Line transfer mode.
D3D=0; Not 3D.
DAM[5:3]=000; 2D mode.
DAM[5:3]=000; 2D mode.
DAM[2:0]=101; post increment by 1.
DDS[1:0]=00; X memory space.
DRS[4:0]=01010; DAX is DMA request source.
Other bits are application dependent.
DAM[2:0]=101; post increment by 1.
DDS[1:0]=00; X memory space.
DRS[4:0]=01010; DAX is DMA request source.
Other bits are application dependent.
DCO2
DCOH=number of frames in block - 1
DCOL=$002; 3 destination registers
DCOH=number of frames in block - 1
DCOL=$001; 2 destination registers
DSR2
DDR2
DOR0
first memory address of the block
XNADR address (base address + $1)
$FFFFFE; offset=-2
first memory address of the block
XADR address (base address + $2)
$FFFFFF; offset=-1
The memory organization employed for DMA transfers depends on whether or not non-audio data changes
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GPIO (PORT D) - Pins and Registers
$00000B
$00000A
$000009
$000008
$000007
$000006
$000005
$000004
$000003
$000002
$000001
$000000
Channel B
$00000B
$00000A
$00009
Channel B
Channel A
Channel B
Channel A
Channel B
Channel A
Channel B
Channel A
Channel B
Channel A
Channel B
Channel A
Channel A
Non-Audio Data
Channel B
$000008
$000007
$000006
$000005
$000004
$000003
$000002
$000001
$000000
Channel A
Non-Audio Data
Channel B
Channel A
Non-Audio Data
Channel B
Channel A
Non-Audio Data
Non-audio data bits do not
change from frame to frame
Non-audio data bits change from
frame to frame
Figure 10-6 Examples of data organization in memory
10.6.5 DAX Operation During Stop
The DAX operation cannot continue when the DSP is in the stop state since no DSP clocks are active.
While the DSP is in the stop state, the DAX will remain in the individual reset state and the status flags
are initialized as described for resets. No DAX control bits are affected. The DAX should be disabled
before the DSP enters the stop state.
10.7 GPIO (PORT D) - Pins and Registers
The Port D GPIO functionality of the DAX is controlled by three registers: Port D Control Register
(PCRD), Port D Direction Register (PRRD) and Port D Data Register (PDRD).
10.7.1 Port D Control Register (PCRD)
The read/write 24-bit DAX Port D Control Register controls the functionality of the DAX GPIO pins. Each
of the PC[1:0] bits controls the functionality of the corresponding port pin. When a PC[i] bit is set, the
corresponding port pin is configured as a DAX pin. When a PC[i] bit is cleared, the corresponding port pin
is configured as GPIO pin. If both PC1 and PC0 are cleared, the DAX is disabled. Hardware and software
reset clear all PCRD bits.
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GPIO (PORT D) - Pins and Registers
PCRD -Port D Control Register - X:$FFFFD7
23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
PC1 PC0
read as zero, should be written with zero for future compatibility
10.7.2 Port D Direction Register (PRRD)
The read/write 24-bit Port D Direction Register controls the direction of the DAX GPIO pins. When port
pin[i] is configured as GPIO, PDC[i] controls the port pin direction. When PDC[i] is set, the GPIO port
pin[i] is configured as output. When PDC[i] is cleared the GPIO port pin[i] is configured as input.
PRRD - Port D Direction Register - X:$FFFFD6
23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
PDC1
PDC0
read as zero, should be written with zero for future compatibility
Figure 10-7 Port D Direction Register (PRRD)
Table 10-6 DAX Port GPIO Control Register Functionality
PDC1
PC1
0
ADO/PD1 pin
Disconnected
Disconnected
Disconnected
Disconnected
PD1 Input
PDC0
PC0
0
ACI/PD0 pin
Disconnected
PD0 Input
PD0 Output
ACI
DAX state
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
Personal Reset
Personal Reset
Personal Reset
Enabled
0
1
0
0
0
1
1
0
Disconnected
PD0 Input
PD0 Output
ACI
Personal Reset
Personal Reset
Personal Reset
Enabled
1
PD1 Input
1
1
PD1 Input
0
1
PD1 Input
1
0
PD1 Output
PD1 Output
PD1 Output
PD1 Output
ADO
0
Disconnected
PD0 Input
PD0 Output
ACI
Personal Reset
Personal Reset
Personal Reset
Enabled
0
1
0
0
0
1
1
0
Disconnected
PD0 Input
Enabled
1
ADO
1
Enabled
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GPIO (PORT D) - Pins and Registers
Table 10-6 DAX Port GPIO Control Register Functionality
PDC1
PC1
1
ADO/PD1 pin
ADO
PDC0
PC0
0
ACI/PD0 pin
PD0 Output
ACI
DAX state
Enabled
Enabled
1
1
1
1
1
ADO
1
10.7.3 Port D Data Register (PDRD)
The read/write 24-bit Port D Data Register is used to read or write data to/from the DAX GPIO pins. Bits
PD[1:0] are used to read or write data from/to the corresponding port pins if they are configured as GPIO.
If a port pin [i] is configured as a GPIO input, then the corresponding PD[i] bit will reflect the value present
on this pin. If a port pin [i] is configured as a GPIO output, then the value written into the corresponding
PD[i] bit will be reflected on the this pin. Hardware and software reset clear all PDRD bits.
PDRD - Port D Data Register - X:$FFFFD5
23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
PD1 PD0
read as zero, should be written with zero for future compatibility
Figure 10-8 Port D Data Register (PDRD)
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11 Timer/ Event Counter
11.1 Introduction
This section describes the internal timer/event counter in the DSP56366. Each of the three timers (timer 0,
1 and 2) can use internal clocking to interrupt the DSP56366 or trigger DMA transfers after a specified
number of events (clocks). In addition, timer 0 provides external access via the bidirectional signal TIO0.
When the TIO0 pin is configured as an input, timer 0 can count or capture events, or measure the width or
period of an external signal. When TIO0 is configured as an output, timer 0 can function as a timer, a
watchdog timer, or a pulse width modulator. TIO0 can also function as a GPIO signal.
11.2 Timer/Event Counter Architecture
The timer module is composed of a common 21-bit prescaler and three independent general purpose 24-bit
timer/event counters, each having its own register set.
11.2.1 Timer/Event Counter Block Diagram
Figure 11-1 shows a block diagram of the timer/event counter. This module includes a 24-bit timer
prescaler load register (TPLR), a 24-bit timer prescaler count register (TPCR), a 21-bit prescaler clock
counter, and three timers. Each of the three timers may use the prescaler clock as its clock source.
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Timer/Event Counter Architecture
GDB
24
24
24
TPLR
TPCR
24
Timer Prescaler
Count Register
Timer Prescaler
Load Register
Timer 0
Timer 1
Timer 2
21-bit Prescaler
Counter
AA0673
TIO0
Figure 11-1 Timer/Event Counter Block Diagram
CLK/2
11.2.2 Individual Timer Block Diagram
Figure 11-2 shows the structure of an individual timer module. The three timers are identical in structure,
but only timer 0 is externally accessible.
Each timer includes a 24-bit counter, a 24-bit read/write timer control and status register (TCSR), a 24-bit
read-only timer count register (TCR), a 24-bit write-only timer load register (TLR), a 24-bit read/write
timer compare register (TCPR), and logic for clock selection and interrupt/DMA trigger generation.
The timer mode is controlled by the TC[3:0] bits of the timer control/status register (TCSR). Timer modes
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Timer/Event Counter Programming Model
GDB
24
24
TCSR
24
24
TCR
24
TCPR
TLR
Control/Status
Register
Load
Count
Compare
Register
Register
Register
9
24
24
24
2
24
Timer Control
Logic
Counter
=
Timer interrupt/
DMA request
TIO
(Timer 0
only)
CLK/2 prescaler CLK
AA0676
Figure 11-2 Timer Block Diagram
11.3 Timer/Event Counter Programming Model
The DSP56366 views each timer as a memory-mapped peripheral with four registers occupying four 24-bit
words in the X data memory space. Either standard polled or interrupt programming techniques can be
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Timer/Event Counter Programming Model
23
0
0
Timer Prescaler Load
Register (TPLR)
TPLR = $FFFF83
23
Timer Prescaler Count
Register (TPCR)
TPLR = $FFFF82
7
6
5
4
3
2
1
0
TC1 TC0
TC3 TC2
TCIE TOIE TE
Timer Control/Status
Register (TCSR)
TCSR0 = $FFFF8F
TCSR1 = $FFFF8B
TCSR2 = $FFFF87
15
14
22
13
12
DI
11
10
18
9
8
PCE
DO
DIR
TRM
INV
23
21
20
19
17
16
TCF TOF
23
0
Timer Load
Register (TLR)
TLR0 = $FFFF8E
TLR1 = $FFFF8A
TLR2 = $FFFF86
23
23
0
0
Timer Compare
Register (TCPR)
TCPR0 = $FFFF8D
TCPR1 = $FFFF89
TCPR2 = $FFFF85
Timer Count
Register (TCR)
TCR0 = $FFFF8C
TCR1 = $FFFF88
TCR2 = $FFFF84
- reserved, read as 0, should be written with 0 for future compatibility
Figure 11-3 Timer Module Programmer’s Model
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Timer/Event Counter Programming Model
11.3.1 Prescaler Counter
The prescaler counter is a 21-bit counter that is decremented on the rising edge of the prescaler input clock.
The counter is enabled when at least one of the three timers is enabled (i.e., one or more of the timer enable
(TE) bits are set) and is using the prescaler output as its source (i.e., one or more of the PCE bits are set).
11.3.2 Timer Prescaler Load Register (TPLR)
The TPLR is a 24-bit read/write register that controls the prescaler divide factor (i.e., the number that the
prescaler counter will load and begin counting from) and the source for the prescaler input clock. See
23
22
21
20
19
18
17
16
15
14
13
12
PS1
PS0
PL20
PL19
PL18
PL17
PL16
PL15
PL14
PL13
PL12
11
10
9
8
7
6
5
4
3
2
1
0
PL11
PL10
PL9
PL8
PL7
PL6
PL5
PL4
PL3
PL2
PL1
PL0
— reserved, read as 0, should be written with 0 for future compatibility
Figure 11-4 Timer Prescaler Load Register (TPLR)
11.3.2.1 TPLR Prescaler Preload Value PL[20:0] Bits 20–0
These 21 bits contain the prescaler preload value. This value is loaded into the prescaler counter when the
counter value reaches zero or the counter switches state from disabled to enabled.
If PL[20:0] = N, then the prescaler counts N + 1 source clock cycles before generating a prescaler clock
pulse. Therefore, the prescaler divide factor = (preload value) + 1.
The PL[20:0] bits are cleared by the hardware RESET signal or the software RESET instruction.
11.3.2.2 TPLR Prescaler Source PS[1:0] Bits 22-21
The two prescaler source (PS) bits control the source of the prescaler clock. Table 9-1 summarizes PS bit
functionality. The prescaler’s use of the TIO0 signal is not affected by the TCSR settings of timer 0.
If the prescaler source clock is external, the prescaler counter is incremented by signal transitions on the
TIO0 signal. The external clock is internally synchronized to the internal clock. The external clock
frequency must be lower than the DSP56366 internal operating frequency divided by 4 (CLK/4).
The PS[1:0] bits are cleared by the hardware RESET signal or the software RESET instruction.
NOTE
To ensure proper operation, change the PS[1:0] bits only when the prescaler
counter is disabled. Disable the prescaler counter by clearing the TE bit in
the TCSR of each of three timers.
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Timer/Event Counter Programming Model
Table 11-1 Prescaler Source Selection
PS1
0
PS0
0
PRESCALER CLOCK SOURCE
Internal CLK/2
TIO0
0
1
1
0
Reserved
Reserved
1
1
11.3.2.3 TPLR Reserved Bit 23
This reserved bit is read as zero and should be written with zero for future compatibility.
11.3.3 Timer Prescaler Count Register (TPCR)
The TPCR is a 24-bit read-only register that reflects the current value in the prescaler counter. See
23
22
21
20
19
18
17
16
15
14
13
12
PC20
PC19
PC18
PC17
PC16
PC15
PC14
PC13
PC12
11
10
9
8
7
6
5
4
3
2
1
0
PC11
PC10
PC9
PC8
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
— reserved, read as 0, should be written with 0 for future compatibility
Figure 11-5 Time Prescaler Count Register (TPCR)
11.3.3.1 TPCR Prescaler Counter Value PC[20:0] Bits 20–0
These 21 bits contain the current value of the prescaler counter.
11.3.3.2 TPCR Reserved Bits 23–21
These reserved bits are read as zero and should be written with zero for future compatibility.
11.3.4 Timer Control/Status Register (TCSR)
The TCSR is a 24-bit read/write register controlling the timer and reflecting its status.
11.3.4.1 TCSR Timer Enable (TE) Bit 0
The timer enable (TE) bit is used to enable or disable the timer. Setting TE enables the timer and clears the
timer counter. The counter starts counting according to the mode selected by the timer control (TC[3:0])
bit values.
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Timer/Event Counter Programming Model
Clearing the TE bit disables the timer. The TE bit is cleared by the hardware RESET signal or the software
RESET instruction.
NOTE
When timer 0 is disabled and TIO0 is not in GPIO mode, the pin is tri-stated.
To prevent undesired spikes on TIO0 when Timer 0 is switched from
tri-state to an active state, TIO0 should be tied to the power supply with a
pullup or pulldown resistor.
11.3.4.2 TCSR Timer Overflow Interrupt Enable (TOIE) Bit 1
The TOIE bit is used to enable the timer overflow interrupts. Setting TOIE enables overflow interrupt
generation. The timer counter can hold a maximum value of $FFFFFF. When the counter value is at the
maximum value and a new event causes the counter to be incremented to $000000, the timer generates an
overflow interrupt.
Clearing the TOIE bit disables overflow interrupt generation. The TOIE bit is cleared by the hardware
RESET signal or the software RESET instruction.
11.3.4.3 TCSR Timer Compare Interrupt Enable (TCIE) Bit 2
The Timer Compare Interrupt Enable (TCIE) bit is used to enable or disable the timer compare interrupts.
Setting TCIE enables the compare interrupts. In the timer, PWM, or watchdog modes, a compare interrupt
is generated after the counter value matches the value of the TCPR. The counter will start counting up from
the number loaded from the TLR and if the TCPR value is N, an interrupt occurs after (N – M + 1) events,
where M is the value of TLR.
Clearing the TCIE bit disables the compare interrupts. The TCIE bit is cleared by the hardware RESET
signal or the software RESET instruction.
11.3.4.4 TCSR Timer Control (TC[3:0]) Bits 4–7
The four TC bits control the source of the timer clock, the behavior of the TIO0 signal, and the timer mode
of operation. Table 11-2 summarizes the TC bit functionality. A detailed description of the timer operating
The TC bits are cleared by the hardware RESET signal or the software RESET instruction.
NOTE
If the clock is external, the counter is incremented by the transitions on the
TIO0 signal. The external clock is internally synchronized to the internal
clock, and its frequency should be lower than the internal operating
frequency divided by 4 (CLK/4).
To ensure proper operation, the TC[3:0] bits should be changed only when
the timer is disabled (when the TE bit in the TCSR has been cleared).
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Timer/Event Counter Programming Model
Table 11-2 Timer Control Bits for Timer 0
Mode Characteristics
Bit Settings
Mode
Number
TC3
TC2
TC1
TC0
Mode Function
TIO0
Clock
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Timer and GPIO
Timer pulse
GPIO
Output
Output
Input
Input
Input
Input
Output
—
Internal
Internal
Internal
External
Internal
Internal
Internal
Internal
—
2
Timer toggle
3
Event counter
Input width measurement
Input period measurement
Capture event
Pulse width modulation
Reserved
4
5
6
7
8
9
Watchdog pulse
Watchdog toggle
Reserved
Output
Output
—
Internal
Internal
—
10
11
12
13
14
15
Reserved
—
—
Reserved
—
—
Reserved
—
—
Reserved
—
—
1
The GPIO function is enabled only if all of the TC[3:0] bits are zero.
Table 11-3 Timer Control Bits for Timers 1 and 2
TC3
0
TC2
0
TC1
0
TC0
0
Clock
Internal
—
Mode
Timer
0
0
0
1
Reserved
Reserved
Reserved
Reserved
0
0
1
X
—
0
1
X
X
—
1
X
X
X
—
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Timer/Event Counter Programming Model
11.3.4.5 TCSR Inverter (INV) Bit 8
The INV bit affects the polarity of the incoming signal on the TIO0 input signal and the polarity of the
output pulse generated on the TIO0 output signal. The effects of the INV bit are summarized in Table 11-4.
This bit is not in use for timers 1 and 2. It should be left cleared.
Table 11-4 Inverter (INV) Bit Operation
TIO0 Programmed as Input
TIO0 Programmed as Output
INV = 0 INV = 1
Bit written to GPIO put on Bit written to GPIO
Mode
INV = 0
INV = 1
0
GPIO signal on the TIO0
signal read directly
GPIO signal on the TIO0
signal inverted
TIO0 signal directly
inverted and put on
TIO0 signal
1
2
3
Counter is incremented on Counter is incremented on
the rising edge of the the falling edge of the
signal from the TIO0 signal signal from the TIO0 signal
—
—
Counter is incremented on Counter is incremented on TCRx output put on TIO0
TCRx output inverted and
put on TIO0 signal
the rising edge of the
the falling edge of the
signal directly
signal from the TIO0 signal signal from the TIO0 signal
Counter is incremented on Counter is incremented on
—
—
the rising edge of the
the falling edge of the
signal from the TIO0 signal signal from the TIO0 signal
4
5
Width of the high input
pulse is measured.
Width of the low input pulse —
is measured.
—
—
Period is measured
Period is measured
—
between the rising edges between the falling edges
of the input signal.
of the input signal.
6
Event is captured on the
rising edge of the signal
from the TIO0 signal
Event is captured on the
falling edge of the signal
from the TIO0 signal
—
—
7
9
—
—
—
—
—
—
Pulse generated by the
timer has positive polarity timer has negative polarity
Pulse generated by the
Pulse generated by the
timer has positive polarity timer has negative polarity
Pulse generated by the
10
Pulse generated by the
Pulse generated by the
timer has positive polarity timer has negative polarity
The INV bit is cleared by the hardware RESET signal or the software RESET instruction.
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Timer/Event Counter Programming Model
NOTE
The INV bit affects both the timer and GPIO modes of operation. To ensure
correct operation, this bit should be changed only when one or both of the
following conditions is true:
•
•
The timer has been disabled by clearing the TE bit in the TCSR.
The timer is in GPIO mode.
The INV bit does not affect the polarity of the prescaler source when TIO0 is used as input to the prescaler.
11.3.4.6 TCSR Timer Reload Mode (TRM) Bit 9
The TRM bit controls the counter preload operation.
In timer (0–3) and watchdog (9–10) modes, the counter is preloaded with the TLR value after the TE bit
is set and the first internal or external clock signal is received. If the TRM bit is set, the counter is reloaded
each time after it reaches the value contained by the TCR. In PWM mode (7), the counter is reloaded each
time counter overflow occurs. In measurement (4–5) modes, if the TRM and the TE bits are set, the counter
is preloaded with the TLR value on each appropriate edge of the input signal.
If the TRM bit is cleared, the counter operates as a free-running counter and is incremented on each
incoming event. The TRM bit is cleared by the hardware RESET signal or the software RESET instruction.
11.3.4.7 TCSR Direction (DIR) Bit 11
The DIR bit determines the behavior of the TIO0 signal when it is used as a GPIO pin. When the DIR bit
is set, the TIO0 signal is an output; when the DIR bit is cleared, the TIO0 signal is an input. The TIO0
signal can be used as a GPIO only when the TC[3:0] bits are all cleared. If any of the TC[3:0] bits are set,
then the GPIO mode is disabled and the DIR bit has no effect.
The DIR bit is cleared by the hardware RESET signal or the software RESET instruction.
This bit is not in use for timers 1 and 2. It should be left cleared.
11.3.4.8 TCSR Data Input (DI) Bit 12
The DI bit reflects the value of the TIO0 signal. If the INV bit is set, the value of the TIO0 signal is inverted
before it is written to the DI bit. If the INV bit is cleared, the value of the TIO0 signal is written directly
to the DI bit.
DI is cleared by the hardware RESET signal or the software RESET instruction.
11.3.4.9 TCSR Data Output (DO) Bit 13
The DO bit is the source of the TIO0 value when it is a data output signal. The TIO0 signal is data output
when the GPIO mode is enabled and DIR is set. A value written to the DO bit is written to the TIO0 signal.
If the INV bit is set, the value of the DO bit is inverted when written to the TIO0 signal. When the INV bit
is cleared, the value of the DO bit is written directly to the TIO0 signal. When GPIO mode is disabled,
writing the DO bit has no effect.
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Timer/Event Counter Programming Model
The DO bit is cleared by the hardware RESET signal or the software RESET instruction.
This bit is not in use for timers 1 and 2. It should be left cleared.
11.3.4.10 TCSR Prescaler Clock Enable (PCE) Bit 15
The PCE bit is used to select the prescaler clock as the timer source clock. When the PCE bit is cleared,
the timer uses either an internal (CLK/2) signal or an external signal (TIO0) as its source clock. When the
PCE bit is set, the prescaler output is used as the timer source clock for the counter regardless of the timer
operating mode. To ensure proper operation, the PCE bit should be changed only when the timer is
disabled (when the TE bit is cleared). Which source clock is used for the prescaler is determined by the
PS[1:0] bits of the TPLR. Timers 1 and 2 can be clocked by the prescaler clock derived from TIO0.
11.3.4.11 TCSR Timer Overflow Flag (TOF) Bit 20
The TOF bit is set to indicate that counter overflow has occurred. This bit is cleared by writing a 1 to the
TOF bit. Writing a 0 to the TOF bit has no effect. The bit is also cleared when the timer overflow interrupt
is serviced.
The TOF bit is cleared by the hardware RESET signal, the software RESET instruction, the STOP
instruction, or by clearing the TE bit to disable the timer.
11.3.4.12 TCSR Timer Compare Flag (TCF) Bit 21
The TCF bit is set to indicate that the event count is complete. In the timer, PWM, and watchdog modes,
the TCF bit is set when (N – M + 1) events have been counted (N is the value in the compare register and
M is the TLR value). In the measurement modes, the TCF bit is set when the measurement has been
completed.
The TCF bit is cleared by writing a one into the TCF bit. Writing a zero into the TCF bit has no effect. The
bit is also cleared when the timer compare interrupt is serviced.
The TCF bit is cleared by the hardware RESET signal, the software RESET instruction, the STOP
instruction, or by clearing the TE bit to disable the timer.
NOTE
The TOF and TCF bits are cleared by writing a one to the specific bit. In
order to assure that only the desired bit is cleared, do not use the BSET
command. The proper way to clear these bits is to write (using a MOVEP
instruction) a one to the flag to be cleared and a zero to the other flag.
11.3.4.13 TCSR Reserved Bits (Bits 3, 10, 14, 16-19, 22, 23)
These reserved bits are read as zero and should be written with zero for future compatibility.
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Timer Modes of Operation
11.3.5 Timer Load Register (TLR)
The TLR is a 24-bit write-only register. In all modes, the counter is preloaded with the TLR value after the
TE bit in the TCSR is set and a first event occurs. The programmer must initialize the TLR to ensure
correct operation in the appropriate timer operating modes.
•
In timer modes, if the timer reload mode (TRM) bit in the TCSR is set, the counter is reloaded each
time after it has reached the value contained by the timer compare register (TCR) and the new event
occurs.
•
•
•
In measurement modes, if the TRM bit in the TCSR is set and the TE bit in the TCSR is set, the
counter is reloaded with the value in the TLR on each appropriate edge of the input signal.
In PWM modes, if the TRM bit in the TCSR is set, the counter is reloaded each time after it has
overflowed and the new event occurs.
In watchdog modes, if the TRM bit in the TCSR is set, the counter is reloaded each time after it
has reached the value contained by the TCR and the new event occurs. In this mode, the counter is
also reloaded whenever the TLR is written with a new value while the TE bit in the TCSR is set.
•
In all modes, if the TRM bit in the TCSR is cleared (TRM = 0), the counter operates as a
free-running counter.
11.3.6 Timer Compare Register (TCPR)
The TCPR is a 24-bit read/write register that contains the value to be compared to the counter value. These
two values are compared every timer clock after the TE bit in the TCSR is set. When the values match, the
timer compare flag (TCF) bit is set and an interrupt is generated if interrupts are enabled (if the timer
compare interrupt enable (TCIE) bit in the TCSR is set). The programmer must initialize the TCPR to
ensure correct operation in the appropriate timer operating modes. The TCPR is ignored in measurement
modes.
11.3.7 Timer Count Register (TCR)
The TCR is a 24-bit read-only register. In timer and watchdog modes, the counter’s contents can be read
at any time by reading the TCR register. In measurement modes, the TCR is loaded with the current value
of the counter on the appropriate edge of the input signal, and its value can be read to determine the width,
period, or delay of the leading edge of the input signal. When the timer is in measurement modes, the TIO0
signal is used for the input signal.
11.4 Timer Modes of Operation
Each timer has various operational modes that meet a variety of system requirements. These modes are as
follows:
•
Timer
— GPIO, mode 0: Internal timer interrupt generated by the internal clock
— Pulse, mode 1: External timer pulse generated by the internal clock
— Toggle, mode 2: Output timing signal toggled by the internal clock
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Timer Modes of Operation
— Event counter, mode 3: Internal timer interrupt generated by an external clock
•
Measurement
— Input width, mode 4: Input pulse width measurement
— Input pulse, mode 5: Input signal period measurement
— Capture, mode 6: Capture external signal
PWM, mode 7: Pulse Width Modulation
Watchdog
•
•
— Pulse, mode 9: Output pulse, internal clock
— Toggle, mode 10: Output toggle, internal clock
These modes are described in detail below. Timer modes are selected by setting the TC[3:0] bits in the
TCSR. Table 11-2 and Table 11-3 show how the different timer modes are selected by setting the bits in
NOTE
To ensure proper operation, the TC[3:0] bits should be changed only when
the timer is disabled (i.e., when the TE bit in the TCSR is cleared).
11.4.1 Timer Modes
11.4.1.1 Timer GPIO (Mode 0)
Bit Settings
Mode Characteristics
TC3
TC2
TC1
TC0
TIO0
Clock
#
KIND
NAME
0
0
0
0
GPIO
Internal
0
Timer
GPIO
In this mode, the timer generates an internal interrupt when a counter value is reached (if the timer compare
interrupt is enabled). Note that any of the three timers can be placed in GPIO mode to generate internal
interrupts, but only timer 0 provides actual external GPIO access on the TIO0 signal.
Set the TE bit to clear the counter and enable the timer. Load the value the timer is to count into the TCPR.
The counter is loaded with the TLR value when the first timer clock signal is received. The timer clock
can be taken from either the DSP56366 clock divided by two (CLK/2) or from the prescaler clock output.
Each subsequent clock signal increments the counter.
When the counter equals the TCPR value, the TCF bit in TCSR is set, and a compare interrupt is generated
if the TCIE bit is set. If the TRM bit in the TCSR is set, the counter is reloaded with the TLR value at the
next timer clock and the count is resumed. If the TRM bit is cleared, the counter continues to be
incremented on each timer clock signal.
This process is repeated until the timer is disabled (i.e., TE is cleared).
If the counter overflows, the TOF bit is set, and if TOIE is set, an overflow interrupt is generated.
The counter contents can be read at any time by reading the TCR.
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Timer Modes of Operation
11.4.1.2 Timer Pulse (Mode 1)
Bit Settings
Mode Characteristics
TC3
TC2
TC1
TC0
TIO0
Clock
#
KIND
NAME
0
0
0
1
Output
Internal
1
Timer
Pulse
In this mode, the timer generates a compare interrupt when the timer count reaches a preset value. In
addition, timer 0 provides an external pulse on its TIO0 signal.
Set the TE bit to clear the counter and enable the timer. The value to which the timer is to count is loaded
into the TCPR. The counter is loaded with the TLR value when the first timer clock signal is received. The
TIO0 signal is loaded with the value of the INV bit. The timer clock signal can be taken from either the
DSP56366 clock divided by two (CLK/2) or from the prescaler clock output. Each subsequent clock signal
increments the counter.
When the counter matches the TCPR value, the TCF bit in TCSR is set and a compare interrupt is
generated if the TCIE bit is set. The polarity of the TIO0 signal is inverted for one timer clock period.
If the TRM bit is set, the counter is loaded with the TLR value on the next timer clock and the count is
resumed. If the TRM bit is cleared, the counter continues to be incremented on each timer clock.
This process is repeated until the TE bit is cleared (disabling the timer).
The value of the TLR sets the delay between starting the timer and the generation of the output pulse. To
generate successive output pulses with a delay of X clocks between signals, the TLR value should be set
to X/2 and the TRM bit should be set.
This process is repeated until the timer is disabled (i.e., TE is cleared).
If the counter overflows, the TOF bit is set, and if TOIE is set, an overflow interrupt is generated.
The counter contents can be read at any time by reading the TCR.
11.4.1.3 Timer Toggle (Mode 2)
Bit Settings
Mode Characteristics
TC3
TC2
TC1
TC0
TIO0
Clock
#
KIND
NAME
0
0
1
0
Output
Internal
0
Timer
Toggle
In this mode, the timer generates a periodic interrupt; timer 0 also toggles the polarity of the TIO0 signal.
Set the TE bit in the TCR to clear the counter and enable the timer. The value the timer is to count is loaded
into the TPCR. The counter is loaded with the TLR value when the first timer clock signal is received. The
TIO0 signal is loaded with the value of the INV bit. The timer clock signal can be taken from either the
DSP56366 clock divided by two (CLK/2) or from the prescaler clock output. Each subsequent clock signal
increments the counter.
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Timer Modes of Operation
When the counter value matches the value in the TCPR, the polarity of the TIO0 output signal is inverted.
The TCF bit in the TCSR is set and a compare interrupt is generated if the TCIE bit is set.
If the TRM bit is set, the counter is loaded with the value of the TLR when the next timer clock is received,
and the count is resumed. If the TRM bit is cleared, the counter continues to be incremented on each timer
clock.
This process is repeated until the TE bit is cleared, disabling the timer.
The TLR value in the TCPR sets the delay between starting the timer and toggling the TIO0 signal. To
generate output signals with a delay of X clock cycles between toggles, the TLR value should be set to X/2
and the TRM bit should be set.
This process is repeated until the timer is disabled (i.e., TE is cleared). If the counter overflows, the TOF
bit is set, and if TOIE is set, an overflow interrupt is generated.
The counter contents can be read at any time by reading the TCR.
11.4.1.4 Timer Event Counter (Mode 3)
Bit Settings
Mode Characteristics
TC3
TC2
TC1
TC0
TIO0
Clock
#
KIND
NAME
0
0
1
1
Input
External
3
Timer
Event Counter
In this mode, the timer counts internal events and issues an interrupt when a preset number of events is
counted. Timer 0 can also count external events.
Set the TE bit to clear the counter and enable the timer. The number of events the timer is to count is loaded
into the TPCR. The counter is loaded with the TLR value when the first timer clock signal is received. The
timer clock signal is provided by the prescaler clock output. Timer 0 can be also be clocked from the TIO0
input signal. Each subsequent clock signal increments the counter. If an external clock is used, it must be
internally synchronized to the internal clock and its frequency must be less than the DSP56366 internal
operating frequency divided by 4.
The value of the INV bit in the TCSR determines whether low-to-high (0 to 1) transitions or high-to-low
(1 to 0) transitions increment the counter. If the INV bit is set, high-to-low transitions increment the
counter. If the INV bit is cleared, low-to-high transitions increment the counter.
When the counter matches the value contained in the TCPR, the TCF bit in the TCSR is set and a compare
interrupt is generated if the TCIE bit is set. If the TRM bit is set, the counter is loaded with the value of
the TLR when the next timer clock is received, and the count is resumed. If TRM bit is cleared, the counter
continues to be incremented on each timer clock.
This process is repeated until the timer is disabled (i.e., TE is cleared). If the counter overflows, the TOF
bit is set, and if TOIE is set, an overflow interrupt is generated.
The counter contents can be read at any time by reading the TCR.
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Timer Modes of Operation
11.4.2 Signal Measurement Modes
The following signal measurement modes are provided:
•
•
•
Measurement input width
Measurement input period
Measurement capture
These functions are available only on timer 0.
11.4.2.1 Measurement Accuracy
The external signal is synchronized with the internal clock used to increment the counter. This
synchronization process can cause the number of clocks measured for the selected signal value to vary
from the actual signal value by plus or minus one counter clock cycle.
11.4.2.2 Measurement Input Width (Mode 4)
Bit Settings
Mode Characteristics
Kind
TC3
TC2
TC1
TC0
Mode
Name
Input Width
TIO0
Clock
0
1
0
0
4
Measurement
Input
Internal
In this mode, the timer 0 counts the number of clocks that occur between opposite edges of an input signal.
Set the TE bit to clear the counter and enable the timer. Load the timer’s count value into the TLR. After
the first appropriate transition (as determined by the INV bit) occurs on the TIO0 input pin, the counter is
loaded with the TLR value on the first timer clock signal received either from the DSP56366 clock divided
by two (CLK/2) or from the prescaler clock input. Each subsequent clock signal increments the counter.
If the INV bit is set, the timer starts on the first high-to-low (1 to 0) signal transition on the TIO0 signal.
If the INV bit is cleared, the timer starts on the first low-to-high (0 to 1) transition on the TIO0 signal.
When the first transition opposite in polarity to the INV bit setting occurs on the TIO0 signal, the counter
stops. The TCF bit in the TCSR is set and a compare interrupt is generated if the TCIE bit is set. The value
of the counter (which measures the width of the TIO0 pulse) is loaded into the TCR. The TCR can be read
to determine the external signal pulse width.
If the TRM bit is set, the counter is loaded with the TLR value on the first timer clock received following
the next valid transition occurring on the TIO0 input pin and the count is resumed. If the TRM bit is
cleared, the counter continues to be incremented on each timer clock.
This process is repeated until the timer is disabled (i.e., TE is cleared).
If the counter overflows, the TOF bit is set, and if TOIE is set, an overflow interrupt is generated.
The counter contents can be read at any time by reading the TCR.
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Timer Modes of Operation
11.4.2.3 Measurement Input Period (Mode 5)
Bit Settings
Mode Characteristics
TC3
TC2
TC1
TC0
Mode
Name
Kind
TIO0
Clock
0
1
0
1
5
Input Period
Measurement
Input
Internal
In this mode, the timer counts the period between the reception of signal edges of the same polarity across
the TIO0 signal.
Set the TE bit to clear the counter and enable the timer. The value the timer is to count is loaded into the
TLR. The value of the INV bit determines whether the period is measured between consecutive
low-to-high (0 to 1) transitions of TIO0 or between consecutive high-to-low (1 to 0) transitions of TIO0.
If INV is set, high-to-low signal transitions are selected. If INV is cleared, low-to-high signal transitions
are selected.
After the first appropriate transition occurs on the TIO0 input pin, the counter is loaded with the TLR value
on the first timer clock signal received from either the DSP56366 clock divided by two (CLK/2) or the
prescaler clock output. Each subsequent clock signal increments the counter.
On the next signal transition of the same polarity that occurs on TIO0, the TCF bit in the TCSR is set and
a compare interrupt is generated if the TCIE bit is set. The contents of the counter are loaded into the TCR.
The TCR then contains the value of the time that elapsed between the two signal transitions on the TIO0
signal.
After the second signal transition, if the TRM bit is set, the TE bit is set to clear the counter and enable the
timer. The counter is repeatedly loaded and incremented until the timer is disabled. If the TRM bit is
cleared, the counter continues to be incremented until it overflows.
This process is repeated until the timer is disabled (i.e., TE is cleared).
If the counter overflows, the TOF bit is set, and if TOIE is set, an overflow interrupt is generated.
The counter contents can be read at any time by reading the TCR.
11.4.2.4 Measurement Capture (Mode 6)
Bit Settings
Mode Characteristics
Kind
TC3
TC2
TC1
TC0
Mode
Name
TIO0
Clock
0
1
1
0
6
Capture
Measurement
Input
Internal
In this mode, the timer counts the number of clocks that elapse between starting the timer and receiving
an external signal.
Set the TE bit to clear the counter and enable the timer. The value the timer is to count is loaded into the
TLR. When the first timer clock signal is received, the counter is loaded with the TLR value. The timer
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Timer Modes of Operation
clock signal can be taken from either the DSP56366 clock divided by two (CLK/2) or from the prescaler
clock output. Each subsequent clock signal increments the counter.
At the first appropriate transition of the external clock detected on the TIO0 signal, the TCF bit in the
TCSR is set and, if the TCIE bit is set, a compare interrupt is generated. The counter halts. The contents
of the counter are loaded into the TCR. The value of the TCR represents the delay between the setting of
the TE bit and the detection of the first clock edge signal on the TIO0 signal.
If the INV bit is set, a high-to-low transition signals the end of the timing period. If INV is cleared, a
low-to-high transition signals the end of the timing period.
If the counter overflows, the TOF bit is set, and if TOIE is set, an overflow interrupt is generated.
The counter contents can be read at any time by reading the TCR.
11.4.3 Pulse Width Modulation (PWM, Mode 7)
Bit Settings
Mode Characteristics
TC3
TC2
TC1
TC0
Mode
Name
Pulse Width Modulation
Kind
TIO0
Clock
0
1
1
1
7
PWM
Output
Internal
In this mode, the timer generates periodic pulses of a preset width. This function is available only on
timer 0.
Set the TE bit to clear the counter and enable the timer. The value the timer is to count is loaded into the
TPCR. When first timer clock is received from either the DSP56366 internal clock divided by two (CLK/2)
or the prescaler clock output, the counter is loaded with the TLR value. Each subsequent timer clock
increments the counter.
When the counter equals the value in the TCPR, the TIO0 output pin is toggled and the TCF bit in the
TCSR is set. The contents of the counter are placed into the TCR. If the TCIE bit is set, a compare interrupt
is generated. The counter continues to be incremented on each timer clock.
If counter overflow has occurred, the TIO0 output pin is toggled, the TOF bit in TCSR is set, and an
overflow interrupt is generated if the TOIE bit is set. If the TRM bit is set, the counter is loaded with the
TLR value on the next timer clock and the count is resumed. If the TRM bit is cleared, the counter
continues to be incremented on each timer clock.
This process is repeated until the timer is disabled by clearing the TE bit.
TIO0 signal polarity is determined by the value of the INV bit. When the counter is started by setting the
TE bit, the TIO0 signal assumes the value of the INV bit. On each subsequent toggling of the TIO0 signal,
the polarity of the TIO0 signal is reversed. For example, if the INV bit is set, the TIO0 signal generates the
following signal: 1010. If the INV bit is cleared, the TIO0 signal generates the following signal: 0101.
The counter contents can be read at any time by reading the TCR.
The value of the TLR determines the output period ($FFFFFF − TLR + 1). The timer counter increments
the initial TLR value and toggles the TIO0 signal when the counter value exceeds $FFFFFF.
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Timer Modes of Operation
The duty cycle of the TIO0 signal is determined by the value in the TCPR. When the value in the TLR is
incremented to a value equal to the value in the TCPR, the TIO0 signal is toggled. The duty cycle is equal
to ($FFFFFF – TCPR) divided by ($FFFFFF − TLR + 1). For a 50% duty cycle, the value of TCPR is equal
to ($FFFFFF + TLR + 1) / 2.
NOTE
The value in TCPR must be greater than the value in TLR.
11.4.4 Watchdog Modes
11.4.4.1 Watchdog Pulse (Mode 9)
Bit Settings
Mode Characteristics
Kind
TC3
TC2
TC1
TC0
Mode
Name
TIO0
Clock
1
0
0
1
9
Pulse
Watchdog
Output
Internal
In this mode, the timer generates an interrupt at a preset rate. Timer 0 also generates pulse on TIO0. The
signal period is equal to the period of one timer clock.
Set the TE bit to clear the counter and enable the timer. The value the timer is to count is loaded into the
TCPR. The counter is loaded with the TLR value on the first timer clock received from either the
DSP56366 internal clock divided by two (CLK/2) or the prescaler clock output. Each subsequent timer
clock increments the counter.
When the counter matches the value of the TCPR, the TCF bit in the TCSR is set and a compare interrupt
is generated if the TCIE bit is also set.
If the TRM bit is set, the counter is loaded with the TLR value on the next timer clock and the count is
resumed. If the TRM bit is cleared, the counter continues to be incremented on each subsequent timer
clock.
This process is repeated until the timer is disabled (i.e., TE is cleared).
If the counter overflows, the TOF bit is set, and if TOIE is set, an overflow interrupt is generated. Timer 0
also generates an output pulse on the TIO0 signal with a pulse width equal to the timer clock period. The
pulse polarity is determined by the value of the INV bit. If the INV bit is set, the pulse polarity is high
(logical 1). If the INV bit is cleared, the pulse polarity is low (logical 0).
The counter contents can be read at any time by reading the TCR.
The counter is reloaded whenever the TLR is written with a new value while the TE bit is set.
NOTE
In this mode, internal logic preserves the TIO0 value and direction for an
additional 2.5 internal clock cycles after the DSP56366 hardware RESET
signal is asserted. This ensures that a valid RESET signal is generated when
the TIO0 signal is used to reset the DSP56366.
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Timer Modes of Operation
11.4.4.2 Watchdog Toggle (Mode 10)
Bit Settings
Mode Characteristics
Kind
TC3
TC2
TC1
TC0
Mode
NAME
TIO0
Clock
1
0
1
0
10
Toggle
Watchdog
Output
Internal
In this mode, the timer generates an interrupt at a preset rate. Timer 0 also toggles the output on TIO0.
Set the TE bit to clear the counter and enable the timer. The value the timer is to count is loaded into the
TPCR. The counter is loaded with the TLR value on the first timer clock received from either the
DSP56366 internal clock divided by two (CLK/2) or the prescaler clock output. Each subsequent timer
clock increments the counter. The TIO0 signal is set to the value of the INV bit.
When the counter equals the value in the TCPR, the TCF bit in the TCSR is set, and a compare interrupt
is generated if the TCIE bit is also set. If the TRM bit is set, the counter is loaded with the TLR value on
the next timer clock and the count is resumed. If the TRM bit is cleared, the counter continues to be
incremented on each subsequent timer clock
When counter overflow has occurred, the polarity of the TIO0 output pin is inverted, the TOF bit in the
TCSR is set, and an overflow interrupt is generated if the TOIE bit is also set. The TIO0 polarity is
determined by the INV bit.
The counter is reloaded whenever the TLR is written with a new value while the TE bit is set. This process
is repeated until the timer is disabled by clearing the TE bit. The counter contents can be read at any time
by reading the TCR register.
NOTE
In this mode, internal logic preserves the TIO0 value and direction for an
additional 2.5 internal clock cycles after the DSP56366 hardware RESET
signal is asserted. This ensures that a valid RESET signal is generated when
the TIO0 signal is used to reset the DSP56366.
11.4.5 Reserved Modes
Modes 8, 11, 12, 13, 14, and 15 are reserved.
11.4.6 Special Cases
The following special cases apply during wait and stop state.
11.4.6.1 Timer Behavior during Wait
Timer clocks are active during the execution of the WAIT instruction and timer activity is undisturbed. If
a timer interrupt is generated, the DSP56366 leaves the wait state and services the interrupt.
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Timer Modes of Operation
11.4.6.2 Timer Behavior during Stop
During the execution of the STOP instruction, the timer clocks are disabled, timer activity is stopped, and
the TIO0 signal is disconnected. Any external changes that happen to the TIO0 signal is ignored when the
DSP56366 is the stop state. To ensure correct operation, the timers should be disabled before the
DSP56366 is placed into the stop state.
11.4.7 DMA Trigger
Each timer can also be used to trigger DMA transfers. For this to occur, a DMA channel must be
programmed to be triggered by a timer event. The timer issues a DMA trigger on every event in all modes
of operation. The DMA channel does not have the capability to save multiple DMA triggers generated by
the timer. To ensure that all DMA triggers are serviced, the user must provide for the preceding DMA
trigger to be serviced before the next trigger is received by the DMA channel.
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Timer Modes of Operation
NOTES
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
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Appendix A Bootstrap ROM Contents
A.1
DSP56366 Bootstrap Program
; BOOTSTRAP CODE FOR DSP56366 Rev. 0 silicon - (C) Copyright 1999 Motorola Inc.
;
;
; Revision 0.0 1999/JAN/26 - Modified from 56362_RevA_regular_boot_rev01.asm:
;
;
;
;
;
- Change the length of xram and the length of yram
in burn-in code
- Change the address of the reserved area in the
Program ROM to $FFAF80 - $FFAFFF
; Revision 0.1 1999/MAR/29 - Enabled 100ns I2C filter in bootstrap
;
;
;
mode 0110.
- Added 5 NOP instructions after OnCE enable.
; This is the Bootstrap program contained in the DSP56366 192-word Boot
; ROM. This program can load any program RAM segment from an external
; EPROM, from the Host Interface or from the SHI serial interface.
;
;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; If MD:MC:MB:MA=x000, then the Boot ROM is bypassed and the DSP56366
; will start fetching instructions beginning with address $C00000 (MD=0)
; or $008000 (MD=1) assuming that an external memory of SRAM type is
; used. The accesses will be performed using 31 wait states with no
; address attributes selected (default area).
;
;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; If MD:MC:MB:MA=0001, then it loads a program RAM segment from consecutive
; byte-wide P memory locations, starting at P:$D00000 (bits 7-0).
; The memory is selected by the Address Attribute AA1 and is accessed with
; 31 wait states.
; The EPROM bootstrap code expects to read 3 bytes
; specifying the number of program words, 3 bytes specifying the address
; to start loading the program words and then 3 bytes for each program
; word to be loaded. The number of words, the starting address and the
; program words are read least significant byte first followed by the
; mid and then by the most significant byte.
; The program words will be condensed into 24-bit words and stored in
; contiguous PRAM memory locations starting at the specified starting address.
; After reading the program words, program execution starts from the same
; address where loading started.
;
;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; If MD:MC:MB:MA=0010, then the bootstrap code jumps to the internal
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DSP56366 Bootstrap Program
; Program ROM, without loading the Program RAM.
;
;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Operation mode MD:MC:MB:MA=0011 is reserved.
;
;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; If MD:MC:MB:MA=01xx, then the Program RAM is loaded from the SHI.
;
;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Operation mode MD:MC:MB:MA=1001 is used for burn-in testing.
;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Operation mode MD:MC:MB:MA=1010 is reserved
; Operation mode MD:MC:MB:MA=1011 is reserved
;
;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; If MD:MC:MB:MA=1100, then it loads the program RAM from the Host
; Interface programmed to operate in the ISA mode.
; The HOST ISA bootstrap code expects to read a 24-bit word
; specifying the number of program words, a 24-bit word specifying the address
; to start loading the program words and then a 24-bit word for each program
; word to be loaded. The program words will be stored in
; contiguous PRAM memory locations starting at the specified starting address.
; After reading the program words, program execution starts from the same
; address where loading started.
; The Host Interface bootstrap load program may be stopped by
; setting the Host Flag 0 (HF0). This will start execution of the loaded
; program from the specified starting address.
;
;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; If MD:MC:MB:MA=1101, then it loads the program RAM from the Host
; Interface programmed to operate in the HC11 non multiplexed mode.
;
; The HOST HC11 bootstrap code expects to read a 24-bit word
; specifying the number of program words, a 24-bit word specifying the address
; to start loading the program words and then a 24-bit word for each program
; word to be loaded. The program words will be stored in
; contiguous PRAM memory locations starting at the specified starting address.
; After reading the program words, program execution starts from the same
; address where loading started.
; The Host Interface bootstrap load program may be stopped by
; setting the Host Flag 0 (HF0). This will start execution of the loaded
; program from the specified starting address.
;
;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; If MD:MC:MB:MA=1110, then it loads the program RAM from the Host
; Interface programmed to operate in the 8051 multiplexed bus mode,
; in double-strob pin configuration.
; The HOST 8051 bootstrap code expects accesses that are byte wide.
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DSP56366 Bootstrap Program
; The HOST 8051 bootstrap code expects to read 3 bytes forming a 24-bit word
; specifying the number of program words, 3 bytes forming a 24-bit word
; specifying the address to start loading the program words and then 3 bytes
; forming 24-bit words for each program word to be loaded.
; The program words will be stored in contiguous PRAM memory locations
; starting at the specified starting address.
; After reading the program words, program execution starts from the same
; address where loading started.
; The Host Interface bootstrap load program may be stopped by setting the
; Host Flag 0 (HF0). This will start execution of the loaded program from
; the specified starting address.
;
; The base address of the HDI08 in multiplexed mode is 0x80 and is not
; modified by the bootstrap code. All the address lines are enabled
; and should be connected accordingly.
;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; If MD:MC:MB:MA=1111, then it loads the program RAM from the Host
; Interface programmed to operate in the MC68302 (IMP) bus mode,
; in single-strob pin configuration.
; The HOST MC68302 bootstrap code expects accesses that are byte wide.
; The HOST MC68302 bootstrap code expects to read 3 bytes forming a 24-bit word
; specifying the number of program words, 3 bytes forming a 24-bit word
; specifying the address to start loading the program words and then 3 bytes
; forming 24-bit words for each program word to be loaded.
; The program words will be stored in contiguous PRAM memory locations
; starting at the specified starting address.
; After reading the program words, program execution starts from the same
; address where loading started.
; The Host Interface bootstrap load program may be stopped by setting the
; Host Flag 0 (HF0). This will start execution of the loaded program from
; the specified starting address.
;
page
opt
132,55,0,0,0
cex,mex,mu
;;
;;;;;;;;;;;;;;;;;;;; GENERAL EQUATES ;;;;;;;;;;;;;;;;;;;;;;;;
;;
BOOT
equ
$D00000
; this is the location in P memory
; on the external memory bus
; where the external byte-wide
; EPROM is located
AARV
equ
$D00409
$FF1000
; AAR1 selects the EPROM as CE~
; mapped as P from $D00000 to
; $DFFFFF, active low
PROMADDR equ
; Starting PROM address
MA
MB
MC
MD
EQU
EQU
EQU
EQU
0
1
2
3
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DSP56366 Bootstrap Program
;;
;;;;;;;;;;;;;;;;;;;; DSP I/O REGISTERS ;;;;;;;;;;;;;;;;;;;;;;;;
;;
M_AAR1 EQU
M_OGDB EQU
$FFFFF8
$FFFFFC
; Address Attribute Register 1
; OnCE GDB Register
M_HPCR EQU
M_HSR EQU
M_HORX EQU
$FFFFC4
$FFFFC3
$FFFFC6
$0
$3
$6
; Host Polarity Control Register
; Host Status Register
; Host Receive Register
; Host Receive Data Full
; Host Flag 0
HRDF
HF0
EQU
EQU
EQU
HEN
; Host Enable
M_HRX EQU
M_HCSR EQU
M_HCKR EQU
$FFFF94
$FFFF91
$FFFF90
17
1
4
12
13
; SHI Receive FIFO
; SHI Control/Status Register
; SHI Clock Control Register
; SHI FIFO Not Empty flag
; SHI I2C Enable Control Bit
; SHI I2C Clock Freeze Control Bit
; SHI I2C Filter Mode Bit 0
; SHI I2C Filter Mode Bit 1
HRNE
HI2C
EQU
EQU
HCKFR EQU
HFM0
HFM1
EQU
EQU
ORG PL:$ff0000,PL:$ff0000
; bootstrap code starts at $ff0000
START
movep #$0,X:M_OGDB
; enable OnCE
nop
; 5 NOP instructions, needed for test procedure
nop
nop
nop
nop
clr a #$0,r5
jset #MD,omr,OMR1XXX
jset #MC,omr,SHILD
jclr #MB,omr,EPROMLD
; clear a and init R5 with 0
; If MD:MC:MB:MA=1xxx go to OMR1XXX
; If MD:MC:MB:MA=01xx, go load from SHI
; If MD:MC:MB:MA=0001, go load from EPROM
jset #MA,omr,RESERVED ; If MD:MC:MB:MA=0011, go to RESERVED
;========================================================================
; This is the routine that jumps to the internal Program ROM.
; MD:MC:MB:MA=0010
move #PROMADDR,r1
bra <FINISH
; store starting PROM address in r1
;========================================================================
; This is the routine that loads from SHI.
; MD:MC:MB:MA=0100 - reserved for SHI
; MD:MC:MB:MA=0101 - Bootstrap from SHI (SPI slave)
; MD:MC:MB:MA=0110 - Bootstrap from SHI (I2C slave, HCKFR=1,100ns filter)
; MD:MC:MB:MA=0111 - Bootstrap from SHI (I2C slave, HCKFR=0)
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DSP56366 Bootstrap Program
SHILD
; This is the routine which loads a program through the SHI port.
; The SHI operates in the slave
; mode, with the 10-word FIFO enabled, and with the HREQ pin enabled for
; receive operation. The word size for transfer is 24 bits. The SHI
; operates in the SPI or in the I2C mode, according to the bootstrap mode.
;
; The program is downloaded according to the following rules:
; 1) 3 bytes - Define the program length.
; 2) 3 bytes - Define the address to which to start loading the program to.
; 3) 3n bytes (while n is the program length defined by the first 3 bytes)
; The program words will be stored in contiguous PRAM memory locations starting
; at the specified starting address.
; After storing the program words, program execution starts from the same
; address where loading started.
move #$A9,r1
; prepare SHI control value in r1
; HEN=1, HI2C=0, HM1-HM0=10, HCKFR=0, HFIFO=1, HMST=0,
; HRQE1-HRQE0=01, HIDLE=0, HBIE=0, HTIE=0, HRIE1-HRIE0=00
jclr
jclr
bset
#MA,omr,SHI_CF
; If MD:MC:MB:MA=01x0, go to SHI clock freeze
#MB,omr,shi_loop ; If MD:MC:MB:MA=0101, select SPI mode
#HI2C,r1
; otherwise select I2C mode.
; enable SHI
shi_loop
movep r1,x:M_HCSR
jclr
#HRNE,x:M_HCSR,* ; wait for no. of words
movep x:M_HRX,a0
jclr
#HRNE,x:M_HCSR,* ; wait for starting address
movep x:M_HRX,r0
move
r0,r1
do
a0,_LOOP2
jclr
#HRNE,x:M_HCSR,* ; wait for HRX not empty
movep x:M_HRX,p:(r0)+
nop
; store in Program RAM
; req. because of restriction
_LOOP2
SHI_CF
bra
<FINISH
bset #HI2C,r1
; select I2C mode.
bset #HCKFR,r1
; enable clock freeze in I2C mode.
; enable 100ns noise filter
; enable 100ns noise filter
; If MD:MC:MB:MA=0110, go to I2C load
; If MD:MC:MB:MA=0100, go to reserved
bset #HFM0,x:M_HCKR
bset #HFM1,x:M_HCKR
jset #MB,omr,shi_loop
bra
<RESERVED
;========================================================================
; This is the routine that loads from external EPROM.
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DSP56366 Bootstrap Program
; MD:MC:MB:MA=0001
EPROMLD
move #BOOT,r2
movep #AARV,X:M_AAR1
do #6,_LOOP9
movem p:(r2)+,a2
asr #8,a,a
; r2 = address of external EPROM
; aar1 configured for SRAM types of access
; read number of words and starting address
; Get the 8 LSB from ext. P mem.
; Shift 8 bit data into A1
;
_LOOP9
move a1,r0
move a1,r1
; starting address for load
; save it in r1
; a0 holds the number of words
; read program words
; Each instruction has 3 bytes
; Get the 8 LSB from ext. P mem.
; Shift 8 bit data into A1
; Go get another byte.
do a0,_LOOP10
do #3,_LOOP11
movem p:(r2)+,a2
asr #8,a,a
_LOOP11
movem a1,p:(r0)+
nop
; Store 24-bit result in P mem.
; pipeline delay
_LOOP10
; and go get another 24-bit word.
; Boot from EPROM done
bra
<FINISH
OMR1XXX
jclr #MC,omr,BURN_RESER ; IF MD:MC:MB:MA=101x, go to RESERVED
; IF MD:MC:MB:MA=1001, go to BURN
jclr #MB,omr,OMR1IS0
; IF MD:MC:MB:MA=110x, go to look for ISA/HC11
jclr #MA,omr,I8051HOSTLD ; If MD:MC:MB:MA=1110, go load from 8051 Host
; If MD:MC:MB:MA=1111, go load from MC68302 Host
;========================================================================
; This is the routine which loads a program through the HDI08 host port
; The program is downloaded from the host MCU with the following rules:
; 1) 3 bytes - Define the program length.
; 2) 3 bytes - Define the address to which to start loading the program to.
; 3) 3n bytes (while n is the program length defined by the 3 first bytes)
; The program words will be stored in contiguous PRAM memory locations starting
; at the specified starting address.
; After reading the program words, program execution starts from the same
; address where loading started.
; The host MCU may terminate the loading process by setting the HF1=0 and HF0=1.
; When the downloading is terminated, the program will start execution of the
; loaded program from the specified starting address.
; The HDI08 boot ROM program enables the following busses to download programs
; through the HDI08 port:
;
; C - ISA
;
- Dual strobes non-multiplexed bus with negative strobe
pulses dual positive request
; D - HC11
;
- Single strobe non-multiplexed bus with positive strobe
pulse single negative request.
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DSP56366 Bootstrap Program
- Dual strobes multiplexed bus with negative strobe pulses
; E - i8051
;
dual negative request.
; F - MC68302
;
- Single strobe non-multiplexed bus with negative strobe
pulse single negative request.
;========================================================================
MC68302HOSTLD
movep #%0000000000111000,x:M_HPCR
; Configure the following conditions:
; HAP = 0 Negative host acknowledge
; HRP = 0 Negative host request
; HCSP = 0 Negatice chip select input
; HDDS = 0 Single strobe bus (R/W~ and DS)
; HMUX = 0 Non multiplexed bus
; HASP = 0 (address strobe polarity has no
;
meaning in non-multiplexed bus)
; HDSP = 0 Negative data stobes polarity
; HROD = 0 Host request is active when enabled
; spare = 0 This bit should be set to 0 for
;
future compatability
; HEN = 0 When the HPCR register is modified
HEN should be cleared
;
; HAEN = 1 Host acknowledge is enabled
; HREN = 1 Host requests are enabled
; HCSEN = 1 Host chip select input enabled
; HA9EN = 0 (address 9 enable bit has no
;
meaning in non-multiplexed bus)
; HA8EN = 0 (address 8 enable bit has no
meaning in non-multiplexed bus)
; HGEN = 0 Host GPIO pins are disabled
;
bra
<HDI08CONT
OMR1IS0
jset #MA,omr,HC11HOSTLD ; If MD:MC:MB:MA=1101, go load from HC11 Host
; If MD:MC:MB:MA=1100, go load from ISA HOST
ISAHOSTLD
movep #%0101000000011000,x:M_HPCR
; Configure the following conditions:
; HAP = 0 Negative host acknowledge
; HRP = 1 Positive host request
; HCSP = 0 Negatice chip select input
; HDDS = 1 Dual strobes bus (RD and WR)
; HMUX = 0 Non multiplexed bus
; HASP = 0 (address strobe polarity has no
;
meaning in non-multiplexed bus)
; HDSP = 0 Negative data stobes polarity
; HROD = 0 Host request is active when enabled
; spare = 0 This bit should be set to 0 for
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DSP56366 Bootstrap Program
;
future compatability
; HEN = 0 When the HPCR register is modified
HEN should be cleared
;
; HAEN = 0 Host acknowledge is disabled
; HREN = 1 Host requests are enabled
; HCSEN = 1 Host chip select input enabled
; HA9EN = 0 (address 9 enable bit has no
;
meaning in non-multiplexed bus)
; HA8EN = 0 (address 8 enable bit has no
meaning non-multiplexed bus)
; HGEN = 0 Host GPIO pins are disabled
;
bra
HC11HOSTLD
movep #%0000001000011000,x:M_HPCR
; Configure the following conditions:
<HDI08CONT
; HAP = 0 Negative host acknowledge
; HRP = 0 Negative host request
; HCSP = 0 Negatice chip select input
; HDDS = 0 Single strobe bus (R/W~ and DS)
; HMUX = 0 Non multiplexed bus
; HASP = 0 (address strobe polarity has no
;
meaning in non-multiplexed bus)
; HDSP = 1 Negative data stobes polarity
; HROD = 0 Host request is active when enabled
; spare = 0 This bit should be set to 0 for
;
future compatability
; HEN = 0 When the HPCR register is modified
HEN should be cleared
;
; HAEN = 0 Host acknowledge is disabled
; HREN = 1 Host requests are enabled
; HCSEN = 1 Host chip select input enabled
; HA9EN = 0 (address 9 enable bit has no
;
meaning in non-multiplexed bus)
; HA8EN = 0 (address 8 enable bit has no
meaning in non-multiplexed bus)
; HGEN = 0 Host GPIO pins are disabled
;
bra
<HDI08CONT
I8051HOSTLD
movep #%0001110000011110,x:M_HPCR
; Configure the following conditions:
; HAP = 0 Negative host acknowledge
; HRP = 0 Negatice host request
; HCSP = 0 Negatice chip select input
; HDDS = 1 Dual strobes bus (RD and WR)
; HMUX = 1 Multiplexed bus
; HASP = 1 Positive address strobe polarity
; HDSP = 0 Negative data stobes polarity
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DSP56366 Bootstrap Program
; HROD = 0 Host request is active when enabled
; spare = 0 This bit should be set to 0 for
future compatability
; HEN = 0 When the HPCR register is modified
HEN should be cleared
;
;
; HAEN = 0 Host acknowledge is disabled
; HREN = 1 Host requests are enabled
; HCSEN = 1 Host chip select input enabled
; HA9EN = 1 Enable address 9 input
; HA8EN = 1 Enable address 8 input
; HGEN = 0 Host GPIO pins are disabled
HDI08CONT
bset
jclr
#HEN,x:M_HPCR
; Enable the HDI08 to operate as host
; interface (set HEN=1)
; wait for the program length to be
; written
#HRDF,x:M_HSR,*
movep x:M_HORX,a0
jclr
#HRDF,x:M_HSR,*
; wait for the program starting address
; to be written
movep x:M_HORX,r0
move
r0,r1
do
a0,HDI08LOOP
; set a loop with the downloaded length
HDI08LL
jset
jclr
enddo
bra
#HRDF,x:M_HSR,HDI08NW
#HF0,x:M_HSR,HDI08LL
; If new word was loaded then jump to
; read that word
; If HF0=0 then continue with the
; downloading
; Must terminate the do loop
<HDI08LOOP
HDI08NW
movep x:M_HORX,p:(r0)+
nop
; Move the new word into its destination
; location in the program RAM
; pipeline delay
HDI08LOOP
;========================================================================
; This is the exit handler that returns execution to normal
; expanded mode and jumps to the RESET vector.
FINISH
andi #$0,ccr
jmp (r1)
; Clear CCR as if RESET to 0.
; Then go to starting Prog addr.
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DSP56366 Bootstrap Program
;========================================================================
; MD:MC:MB:MA=1001 is used for Burn-in code
BURN_RESER
jclr #MB,omr,BURN
; IF MD:MC:MB:MA=1001, go to BURN
;========================================================================
; The following modes are reserved, some of which are used for internal testing
; MD:MC:MB:MA=0011 is reserved
; MD:MC:MB:MA=1010 is reserved
; MD:MC:MB:MA=1011 is reserved
RESERVED
bra
<*
;========================================================================
; Code for burn-in
;========================================================================
M_PCRC EQU
M_PDRC EQU
M_PRRC EQU
$FFFFBF
$FFFFBD
$FFFFBE
$3
;; Port C GPIO Control Register
;; Port C GPIO Data Register
;; Port C Direction Register
SCKT
EQU
;; SCKT is GPIO bit #3 in ESAI (Port C)
EQUALDATA
equ
0
;; 1 if xram and yram are of equal
;; size and addresses, 0 otherwise.
if
(EQUALDATA)
start_dram
length_dram
else
equ
equ
0
;;
$1600 ;; same addresses
start_xram
length_xram
start_yram
length_yram
endif
equ
equ
equ
equ
0
;; 13k XRAM
;; 7k YRAM
$3400
0
$1c00
start_pram
length_pram
equ
equ
0
$C00
;; 3k PRAM
BURN
;; get PATTERN pointer
clr b #PATTERNS,r6
;; b is the error accumulator
move
#<(NUM_PATTERNS-1),m6 ;; program runs forever in
;; cyclic form
;; configure SCKT as gpio output.
movep b,x:M_PDRC
;; clear GPIO data register
bclr
bset
#SCKT,x:M_PCRC
#SCKT,x:M_PRRC
;; Define SCKT as output GPIO pin
;; SCKT toggles means test pass
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DSP56366 Bootstrap Program
;; r5 = test fail flag = $000000
lua
(r5)-,r7
;; r7 = test pass flag = $FFFFFF
burnin_loop
do #9,burn1
;;----------------------------
;; test RAM
;; each pass checks 1 pattern
;;----------------------------
move
move
move
p:(r6)+,x1
p:(r6)+,x0
p:(r6)+,y0
;; pattern for x memory
;; pattern for y memory
;; pattern for p memory
;; write pattern to all memory locations
if
(EQUALDATA)
;; x/y ram symmetrical
;; write x and y memory
clr a #start_dram,r0
;; start of x/y ram
;; length of x/y ram
move
rep
#>length_dram,n0
n0
mac x0,x1,a x,l:(r0)+
;; exercise mac, write x/y ram
;; x/y ram not symmetrical
else
;; write x memory
clr a #start_xram,r0
;; start of xram
;; length of xram
move
rep
#>length_xram,n0
n0
mac x0,y0,a x1,x:(r0)+
;; exercise mac, write xram
;; write y memory
clr a #start_yram,r1
;; start of yram
;; length of yram
move
rep
#>length_yram,n1
n1
mac x1,y0,a x0,y:(r1)+
;; exercise mac, write yram
endif
;; write p memory
clr a #start_pram,r2
;; start of pram
;; length of pram
move
rep
#>length_pram,n2
n2
move
y0,p:(r2)+
;; write pram
;; check memory contents
(EQUALDATA)
if
;; x/y ram symmetrical
;; check dram
clr a #start_dram,r0
;; restore pointer, clear a
;; a0=a2=0
do
n0,_loopd
x:(r0),a1
x1,a
move
eor
add
a,b
;; accumulate error in b
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DSP56366 Bootstrap Program
move
eor
y:(r0)+,a1
x0,a
;; a0=a2=0
add
a,b
;; accumulate error in b
_loopd
else
;; x/y ram not symmetrical
;; check xram
clr a #start_xram,r0
;; restore pointer, clear a
;; a0=a2=0
do
n0,_loopx
x:(r0)+,a1
x1,a
move
eor
add
a,b
;; accumulate error in b
_loopx
_loopy
;; check yram
clr a #start_yram,r1
;; restore pointer, clear a
;; a0=a2=0
do
n1,_loopy
y:(r1)+,a1
x0,a
move
eor
add
a,b
;; accumulate error in b
endif
;; check pram
clr a #start_pram,r2
;; restore pointer, clear a
;; a0=a2=0
do
n2,_loopp
p:(r2)+,a1
y0,a
move
eor
add
a,b
;; accumulate error in b
_loopp
;;---------------------------------------------------
;; toggle pin if no errors, stop execution otherwise.
;;---------------------------------------------------
;; if error
tne
r5,r7
;; r7=$FFFFFF as long as test pass
;; condition codes preserved
;; this instr can be removed in case of shortage
;; write pass/fail flag to OnCE
movep r7,x:M_OGDB
;; condition codes preserved
;; this instr can be removed in case of shortage
beq
label1
bclr
enddo
#SCKT,x:M_PDRC
;; clear SCKT if error,
;; terminate the loop normally
;; this instr can be removed in case of shortage
;; and stop execution
bra
<burn1
label1
burn1
;; if no error
;; toggle pin and keep on looping
bchg
#SCKT,x:M_PDRC
;; test completion
debug
wait
;; enter debug mode if OnCE port enabled
;; this instr can be removed in case of shortage
;; enter wait otherwise (OnCE port disabled)
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
A-12
Freescale Semiconductor
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DSP56366 Bootstrap Program
BURN_END
PATTERNS
ORG PL:,PL:
dsm
4
;; align for correct modulo addressing
ORG PL:BURN_END,PL:BURN_END
dup PATTERNS-*
dc *
; write address in unused Boot ROM location
endm
ORG
PL:PATTERNS,PL:PATTERNS ;; Each value is written to all memories
dc
dc
dc
dc
$555555
$AAAAAA
$333333
$F0F0F0
NUM_PATTERNS
equ
*-PATTERNS
;========================================================================
; This code fills the unused bootstrap rom locations with their address
dup $FF00C0-*
dc *
endm
;========================================================================
; Reserved Area in the Program ROM: upper 128 words.
; Address range: $FFAF80 - $FFAFFF
;========================================================================
ORG PL:$FFAF80,PL:$FFAF80
; This code fills the unused rom locations with their address
dup $FFB000-$14-*
dc *
endm
; Code segment for testing of ROM Patch
; This code segment is located in the uppermost addresses of the Program ROM
ORG PL:$FFB000-$14,PL:$FFB000-$14
move
move
#$80000,r0
#$0,x0
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
Freescale Semiconductor
A-13
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DSP56366 Bootstrap Program
move
move
move
move
move
move
move
move
move
move
move
move
move
move
move
move
move
x0,x:(r0)+
#$1,x0
x0,x:(r0)+
#$2,x0
x0,x:(r0)+
#$3,x0
x0,x:(r0)+
#$4,x0
x0,x:(r0)+
#$5,x0
x0,x:(r0)+
#$6,x0
x0,x:(r0)+
#$7,x0
x0,x:(r0)+
#$8,x0
x0,x:(r0)+
end
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
A-14
Freescale Semiconductor
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Appendix B Equates
;*********************************************************************************
;
;
;
EQUATES for DSP56366 interrupts
Last update: April 24, 2000
;*********************************************************************************
page
opt
132,55,0,0,0
mex
intequ ident 1,0
if @DEF(I_VEC)
;leave user definition as is.
else
I_VEC
equ
$0
endif
;------------------------------------------------------------------------
; Non-Maskable interrupts
;------------------------------------------------------------------------
I_RESET EQU I_VEC+$00 ; Hardware RESET
I_STACK EQU I_VEC+$02 ; Stack Error
I_ILL
EQU I_VEC+$04 ; Illegal Instruction
EQU I_VEC+$04 ; Illegal Instruction
EQU I_VEC+$06 ; Debug Request
I_IINST
I_DBG
I_TRAP EQU I_VEC+$08 ; Trap
I_NMI
EQU I_VEC+$0A ; Non Maskable Interrupt
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
Freescale Semiconductor
B-1
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Equates
;------------------------------------------------------------------------
; Interrupt Request Pins
;------------------------------------------------------------------------
I_IRQA EQU I_VEC+$10 ; IRQA
I_IRQB EQU I_VEC+$12 ; IRQB
I_IRQC EQU I_VEC+$14 ; IRQC
I_IRQD EQU I_VEC+$16 ; IRQD
;------------------------------------------------------------------------
; DMA Interrupts
;------------------------------------------------------------------------
I_DMA0 EQU I_VEC+$18 ; DMA Channel 0
I_DMA1 EQU I_VEC+$1A ; DMA Channel 1
I_DMA2 EQU I_VEC+$1C ; DMA Channel 2
I_DMA3 EQU I_VEC+$1E ; DMA Channel 3
I_DMA4 EQU I_VEC+$20 ; DMA Channel 4
I_DMA5 EQU I_VEC+$22 ; DMA Channel 5
;------------------------------------------------------------------------
; DAX Interrupts
;------------------------------------------------------------------------
I_DAXTUE
I_DAXBLK
EQU I_VEC+$28 ; DAX Underrun Error
EQU I_VEC+$2A ; DAX Block Transferred
I_DAXTD EQU I_VEC+$2E ; DAX Audio Data Empty
;------------------------------------------------------------------------
; ESAI Interrupts
;------------------------------------------------------------------------
I_ESAIRD EQU I_VEC+$30 ; ESAI Receive Data
I_ESAIRED EQU I_VEC+$32 ; ESAI Receive Even Data
I_ESAIRDE EQU I_VEC+$34 ; ESAI Receive Data With Exception Status
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
B-2
Freescale Semiconductor
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Equates
I_ESAIRLS EQU I_VEC+$36 ; ESAI Receive Last Slot
I_ESAITD EQU I_VEC+$38 ; ESAI Transmit Data
I_ESAITED EQU I_VEC+$3A ; ESAI Transmit Even Data
I_ESAITDE EQU I_VEC+$3C ; ESAI Transmit Data With Exception Status
I_ESAITLS EQU I_VEC+$3E ; ESAI Transmit Last Slot
;------------------------------------------------------------------------
; SHI Interrupts
;------------------------------------------------------------------------
I_SHITD
EQU I_VEC+$40 ; SHI Transmit Data
I_SHITUE EQU I_VEC+$42 ; SHI Transmit Underrun Error
I_SHIRNE EQU I_VEC+$44 ; SHI Receive FIFO Not Empty
I_SHIRFF EQU I_VEC+$48 ; SHI Receive FIFO Full
I_SHIROE EQU I_VEC+$4A ; SHI Receive Overrun Error
I_SHIBER
EQU I_VEC+$4C ; SHI Bus Error
;------------------------------------------------------------------------
; Timer Interrupts
;------------------------------------------------------------------------
I_TIM0C EQU I_VEC+$54 ; TIMER 0 compare
I_TIM0OF EQU I_VEC+$56 ; TIMER 0 overflow
I_TIM1C EQU I_VEC+$58 ; TIMER 1 compare
I_TIM1OF EQU I_VEC+$5A ; TIMER 1 overflow
I_TIM2C EQU I_VEC+$5C ; TIMER 2 compare
I_TIM2OF EQU I_VEC+$5E ; TIMER 2 overflow
;------------------------------------------------------------------------
; HDI08 Interrupts
;------------------------------------------------------------------------
I_HI08RX EQU I_VEC+$60 ; Host Receive Data Full
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
Freescale Semiconductor
B-3
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Equates
I_HI08TX EQU I_VEC+$62 ; Host Transmit Data Empty
I_HI08CM EQU I_VEC+$64 ; Host Command (Default)
;------------------------------------------------------------------------
; ESAI_1 Interrupts
;------------------------------------------------------------------------
I_ESAI1RD EQU I_VEC+$70 ; ESAI_1 Receive Data
I_ESAI1RED EQU I_VEC+$72 ; ESAI_1 Receive Even Data
I_ESAI1RDE EQU I_VEC+$74 ; ESAI_1 Receive Data With Exception Status
I_ESAI1RLS EQU I_VEC+$76 ; ESAI_1 Receive Last Slot
I_ESAI1TD EQU I_VEC+$78 ; ESAI_1 Transmit Data
I_ESAI1TED EQU I_VEC+$7A ; ESAI_1 Transmit Even Data
I_ESAI1TDE EQU I_VEC+$7C ; ESAI_1 Transmit Data With Exception Status
I_ESAI1TLS EQU I_VEC+$7E ; ESAI_1 Transmit Last Slot
;------------------------------------------------------------------------
; INTERRUPT ENDING ADDRESS
;------------------------------------------------------------------------
I_INTEND EQU I_VEC+$FF ; last address of interrupt vector space
;------------------ end of intequ.asm ------------------------
;*********************************************************************************
;
;
;
EQUATES for DSP56366 I/O registers and ports
Last update: August 23, 2000
;*********************************************************************************
page
opt
132,55,0,0,0
mex
ioequ ident 1,0
;------------------------------------------------------------------------
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
B-4
Freescale Semiconductor
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Equates
;
;
;
EQUATES for I/O Port Programming
;------------------------------------------------------------------------
;
Register Addresses
EQU
M_HDR
$FFFFC9
$FFFFC8
$FFFFBF
$FFFFBE
$FFFFBD
$FFFFD7
$FFFFD6
$FFFFD5
$FFFF9F
$FFFF9E
$FFFF9D
$FFFFFC
; Host port GPIO data Register
; Host port GPIO direction Register
; Port C Control Register
M_HDDR EQU
M_PCRC EQU
M_PRRC EQU
M_PDRC EQU
M_PCRD EQU
M_PRRD EQU
M_PDRD EQU
M_PCRE EQU
M_PRRE EQU
M_PDRE EQU
M_OGDB EQU
; Port C Direction Register
; Port C GPIO Data Register
; Port D Control register
; Port D Direction Data Register
; Port D GPIO Data Register
; Port E Control register
; Port E Direction Data Register
; Port E GPIO Data Register
; OnCE GDB Register
;------------------------------------------------------------------------
;
;
;
EQUATES for Exception Processing
;------------------------------------------------------------------------
Register Addresses
;
M_IPRC EQU
M_IPRP EQU
$FFFFFF
$FFFFFE
; Interrupt Priority Register Core
; Interrupt Priority Register Peripheral
;
Interrupt Priority Register Core (IPRC)
M_IAL
EQU
$7
0
; IRQA Mode Mask
M_IAL0 EQU
; IRQA Mode Interrupt Priority Level (low)
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
Freescale Semiconductor
B-5
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Equates
M_IAL1 EQU
M_IAL2 EQU
1
; IRQA Mode Interrupt Priority Level (high)
; IRQA Mode Trigger Mode
2
M_IBL
EQU
$38
3
; IRQB Mode Mask
M_IBL0 EQU
M_IBL1 EQU
M_IBL2 EQU
; IRQB Mode Interrupt Priority Level (low)
; IRQB Mode Interrupt Priority Level (high)
; IRQB Mode Trigger Mode
4
5
M_ICL
EQU
$1C0
6
; IRQC Mode Mask
M_ICL0 EQU
M_ICL1 EQU
M_ICL2 EQU
; IRQC Mode Interrupt Priority Level (low)
; IRQC Mode Interrupt Priority Level (high)
; IRQC Mode Trigger Mode
7
8
M_IDL
EQU
$E00
9
; IRQD Mode Mask
M_IDL0 EQU
M_IDL1 EQU
M_IDL2 EQU
; IRQD Mode Interrupt Priority Level (low)
; IRQD Mode Interrupt Priority Level (high)
; IRQD Mode Trigger Mode
10
11
M_D0L
EQU
$3000
12
; DMA0 Interrupt priority Level Mask
; DMA0 Interrupt Priority Level (low)
; DMA0 Interrupt Priority Level (high)
; DMA1 Interrupt Priority Level Mask
; DMA1 Interrupt Priority Level (low)
; DMA1 Interrupt Priority Level (high)
; DMA2 Interrupt priority Level Mask
; DMA2 Interrupt Priority Level (low)
; DMA2 Interrupt Priority Level (high)
; DMA3 Interrupt Priority Level Mask
; DMA3 Interrupt Priority Level (low)
; DMA3 Interrupt Priority Level (high)
; DMA4 Interrupt priority Level Mask
M_D0L0 EQU
M_D0L1 EQU
13
M_D1L
EQU
$C000
14
M_D1L0 EQU
M_D1L1 EQU
15
M_D2L
EQU
$30000
16
M_D2L0 EQU
M_D2L1 EQU
17
M_D3L
EQU
$C0000
18
M_D3L0 EQU
M_D3L1 EQU
19
M_D4L
EQU
$300000
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
B-6
Freescale Semiconductor
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Equates
M_D4L0 EQU
M_D4L1 EQU
20
; DMA4 Interrupt Priority Level (low)
; DMA4 Interrupt Priority Level (high)
; DMA5 Interrupt priority Level Mask
; DMA5 Interrupt Priority Level (low)
; DMA5 Interrupt Priority Level (high)
21
M_D5L
EQU
$C00000
22
M_D5L0 EQU
M_D5L1 EQU
23
;
Interrupt Priority Register Peripheral (IPRP)
M_ESL
EQU
$3
0
; ESAI Interrupt Priority Level Mask
; ESAI Interrupt Priority Level (low)
; ESAI Interrupt Priority Level (high)
; SHI Interrupt Priority Level Mask
; SHI Interrupt Priority Level (low)
; SHI Interrupt Priority Level (high)
; HDI08 Interrupt Priority Level Mask
; HDI08 Interrupt Priority Level (low)
; HDI08 Interrupt Priority Level (high)
; DAX Interrupt Priority Level Mask
; DAX Interrupt Priority Level (low)
; DAX Interrupt Priority Level (high)
;Timer Interrupt Priority Level Mask
;Timer Interrupt Priority Level (low)
;Timer Interrupt Priority Level (high)
; ESAI_1 Interrupt Priority Level Mask
; ESAI_1 Interrupt Priority Level (low)
; ESAI_1 Interrupt Priority Level (high)
M_ESL0 EQU
M_ESL1 EQU
1
M_SHL
EQU
$C
2
M_SHL0 EQU
M_SHL1 EQU
3
M_HDL
EQU
$30
4
M_HDL0 EQU
M_HDL1 EQU
5
M_DAL
EQU
$C0
6
M_DAL0 EQU
M_DAL1 EQU
M_TAL EQU
M_TAL0 EQU
M_TAL1 EQU
7
$300
8
9
M_ES1L
EQU
$C00
M_ESL10 EQU
M_ESL11 EQU
0
1
;------------------------------------------------------------------------
;
;
;
EQUATES for Direct Memory Access (DMA)
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
Freescale Semiconductor
B-7
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Equates
;------------------------------------------------------------------------
;
Register Addresses Of DMA
M_DSTR EQU
M_DOR0 EQU
M_DOR1 EQU
M_DOR2 EQU
M_DOR3 EQU
$FFFFF4
$FFFFF3
$FFFFF2
$FFFFF1
$FFFFF0
; DMA Status Register
; DMA Offset Register 0
; DMA Offset Register 1
; DMA Offset Register 2
; DMA Offset Register 3
;
Register Addresses Of DMA0
M_DSR0 EQU
M_DDR0 EQU
M_DCO0 EQU
M_DCR0 EQU
$FFFFEF
$FFFFEE
$FFFFED
$FFFFEC
; DMA0 Source Address Register
; DMA0 Destination Address Register
; DMA0 Counter
; DMA0 Control Register
;
Register Addresses Of DMA1
M_DSR1 EQU
M_DDR1 EQU
M_DCO1 EQU
M_DCR1 EQU
$FFFFEB
$FFFFEA
$FFFFE9
$FFFFE8
; DMA1 Source Address Register
; DMA1 Destination Address Register
; DMA1 Counter
; DMA1 Control Register
;
Register Addresses Of DMA2
M_DSR2 EQU
M_DDR2 EQU
M_DCO2 EQU
M_DCR2 EQU
$FFFFE7
$FFFFE6
$FFFFE5
$FFFFE4
; DMA2 Source Address Register
; DMA2 Destination Address Register
; DMA2 Counter
; DMA2 Control Register
;
Register Addresses Of DMA3
M_DSR3 EQU
M_DDR3 EQU
M_DCO3 EQU
$FFFFE3
$FFFFE2
$FFFFE1
; DMA3 Source Address Register
; DMA3 Destination Address Register
; DMA3 Counter
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
B-8
Freescale Semiconductor
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Equates
M_DCR3 EQU
$FFFFE0
; DMA3 Control Register
;
Register Addresses Of DMA4
M_DSR4 EQU
M_DDR4 EQU
M_DCO4 EQU
M_DCR4 EQU
$FFFFDF
$FFFFDE
$FFFFDD
$FFFFDC
; DMA4 Source Address Register
; DMA4 Destination Address Register
; DMA4 Counter
; DMA4 Control Register
;
Register Addresses Of DMA5
M_DSR5 EQU
M_DDR5 EQU
M_DCO5 EQU
M_DCR5 EQU
$FFFFDB
$FFFFDA
$FFFFD9
$FFFFD8
; DMA5 Source Address Register
; DMA5 Destination Address Register
; DMA5 Counter
; DMA5 Control Register
;
DMA Control Register
M_DSS
EQU
$3
; DMA Source Space Mask (DSS0-Dss1)
; DMA Source Memory space 0
; DMA Source Memory space 1
; DMA Destination Space Mask (DDS-DDS1)
; DMA Destination Memory Space 0
; DMA Destination Memory Space 1
; DMA Address Mode Mask (DAM5-DAM0)
; DMA Address Mode 0
M_DSS0 EQU
M_DSS1 EQU
0
1
M_DDS
EQU
$C
M_DDS0 EQU
M_DDS1 EQU
2
3
M_DAM
EQU
$3f0
M_DAM0 EQU
M_DAM1 EQU
M_DAM2 EQU
M_DAM3 EQU
M_DAM4 EQU
M_DAM5 EQU
4
5
; DMA Address Mode 1
6
; DMA Address Mode 2
7
; DMA Address Mode 3
8
; DMA Address Mode 4
9
; DMA Address Mode 5
M_D3D
M_DRS
M_DRS0
EQU
EQU
10
$F800
11
; DMA Three Dimensional Mode
; DMA Request Source Mask (DRS0-DRS4)
;DMA Request Source bit 0
EQU
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
Freescale Semiconductor
B-9
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Equates
M_DRS1
M_DRS2
M_DRS3
M_DRS4
EQU
EQU
EQU
EQU
12
13
14
15
;DMA Request Source bit 1
;DMA Request Source bit 2
;DMA Request Source bit 3
;DMA Request Source bit 4
; DMA Continuous Mode
M_DCON EQU
M_DPR EQU
16
$60000
17
; DMA Channel Priority
M_DPR0 EQU
M_DPR1 EQU
; DMA Channel Priority Level (low)
; DMA Channel Priority Level (high)
; DMA Transfer Mode Mask (DTM2-DTM0)
; DMA Transfer Mode 0
18
M_DTM
EQU
$380000
19
M_DTM0 EQU
M_DTM1 EQU
M_DTM2 EQU
20
; DMA Transfer Mode 1
21
; DMA Transfer Mode 2
M_DIE
M_DE
;
EQU
EQU
22
; DMA Interrupt Enable bit
; DMA Channel Enable bit
23
DMA Status Register
M_DTD
EQU
$3F
0
; Channel Transfer Done Status MASK (DTD0-DTD5)
; DMA Channel Transfer Done Status 0
; DMA Channel Transfer Done Status 1
; DMA Channel Transfer Done Status 2
; DMA Channel Transfer Done Status 3
; DMA Channel Transfer Done Status 4
; DMA Channel Transfer Done Status 5
; DMA Active State
M_DTD0 EQU
M_DTD1 EQU
M_DTD2 EQU
M_DTD3 EQU
M_DTD4 EQU
M_DTD5 EQU
M_DACT EQU
1
2
3
4
5
8
M_DCH
EQU
$E00
9
; DMA Active Channel Mask (DCH0-DCH2)
; DMA Active Channel 0
M_DCH0 EQU
M_DCH1 EQU
M_DCH2 EQU
10
11
; DMA Active Channel 1
; DMA Active Channel 2
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
B-10
Freescale Semiconductor
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Equates
;------------------------------------------------------------------------
;
;
;
EQUATES for Phase Locked Loop (PLL)
;------------------------------------------------------------------------
Register Addresses Of PLL
M_PCTL EQU $FFFFFD
PLL Control Register
;
; PLL Control Register
;
M_MF
EQU
$FFF
; Multiplication Factor Bits Mask (MF0-MF11)
;Multiplication Factor bit 0
;Multiplication Factor bit 1
;Multiplication Factor bit 2
;Multiplication Factor bit 3
;Multiplication Factor bit 4
;Multiplication Factor bit 5
;Multiplication Factor bit 6
;Multiplication Factor bit 7
;Multiplication Factor bit 8
;Multiplication Factor bit 9
;Multiplication Factor bit 10
;Multiplication Factor bit 11
; Division Factor Bits Mask (DF0-DF2)
;Division Factor bit 0
M_MF0
M_MF1
M_MF2
M_MF3
M_MF4
M_MF5
M_MF6
M_MF7
M_MF8
M_MF9
M_MF10
M_MF11
M_DF
EQU 0
EQU 1
EQU 2
EQU 3
EQU 4
EQU 5
EQU 6
EQU 7
EQU 8
EQU 9
EQU 10
EQU 11
EQU
$7000
M_DF0
M_DF1
M_DF2
EQU 12
EQU 13
EQU 14
;Division Factor bit 1
;Division Factor bit 2
M_XTLR EQU
M_XTLD EQU
M_PSTP EQU
15
16
17
; XTAL Range select bit
; XTAL Disable Bit
; STOP Processing State Bit
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
Freescale Semiconductor
B-11
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Equates
M_PEN
EQU
18
19
$F00000
; PLL Enable Bit
M_COD EQU
; PLL Clock Output Disable Bit
; PreDivider Factor Bits Mask (PD0-PD3)
;PreDivider Factor bit 0
;PreDivider Factor bit 1
;PreDivider Factor bit 2
;PreDivider Factor bit 3
M_PD
EQU
M_PD0
M_PD1
M_PD2
M_PD3
EQU 20
EQU 21
EQU 22
EQU 23
;------------------------------------------------------------------------
;
;
;
EQUATES for BIU
;------------------------------------------------------------------------
;
Register Addresses Of BIU
M_BCR
M_DCR
EQU
EQU
$FFFFFB
$FFFFFA
$FFFFF9
$FFFFF8
$FFFFF7
$FFFFF6
$FFFFF5
; Bus Control Register
; DRAM Control Register
M_AAR0 EQU
M_AAR1 EQU
M_AAR2 EQU
M_AAR3 EQU
; Address Attribute Register 0
; Address Attribute Register 1
; Address Attribute Register 2
; Address Attribute Register 3
; ID Register
M_IDR
;
EQU
Bus Control Register
M_BA0W EQU
$1F
; Area 0 Wait Control Mask (BA0W0-BA0W4)
;Area 0 Wait Control Bit 0
;Area 0 Wait Control Bit 1
;Area 0 Wait Control Bit 2
;Area 0 Wait Control Bit 3
;Area 0 Wait Control Bit 4
M_BA0W0 EQU 0
M_BA0W1 EQU 1
M_BA0W2 EQU 2
M_BA0W3 EQU 3
M_BA0W4 EQU 4
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
B-12
Freescale Semiconductor
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Equates
M_BA1W EQU
$3E0
; Area 1 Wait Control Mask (BA1W0-BA14)
;Area 1 Wait Control Bit 0
;Area 1 Wait Control Bit 1
;Area 1 Wait Control Bit 2
;Area 1 Wait Control Bit 3
;Area 1 Wait Control Bit 4
; Area 2 Wait Control Mask (BA2W0-BA2W2)
;Area 2 Wait Control Bit 0
;Area 2 Wait Control Bit 1
;Area 2 Wait Control Bit 2
; Area 3 Wait Control Mask (BA3W0-BA3W3)
;Area 3 Wait Control Bit 0
;Area 3 Wait Control Bit 1
;Area 3 Wait Control Bit 2
; Default Area Wait Control Mask (BDFW0-BDFW4)
;Default Area Wait Control bit 0
;Default Area Wait Control bit 1
;Default Area Wait Control bit 2
;Default Area Wait Control bit 3
;Default Area Wait Control bit 4
; Bus State
M_BA1W0 EQU 5
M_BA1W1 EQU 6
M_BA1W2 EQU 7
M_BA1W3 EQU 8
M_BA1W4 EQU 9
M_BA2W EQU
$1C00
M_BA2W0 EQU 10
M_BA2W1 EQU 11
M_BA2W2 EQU 12
M_BA3W EQU
$E000
M_BA3W0 EQU 13
M_BA3W1 EQU 14
M_BA3W2 EQU 15
M_BDFW EQU
M_BDFW0 EQU
M_BDFW1 EQU
M_BDFW2 EQU
M_BDFW3 EQU
M_BDFW4 EQU
$1F0000
16
17
18
19
20
M_BBS
M_BLH
M_BRH
;
EQU
EQU
EQU
21
22
23
; Bus Lock Hold
; Bus Request Hold
DRAM Control Register
M_BCW
M_BCW0
EQU
EQU
$3
0
; In Page Wait States Bits Mask (BCW0-BCW1)
; In Page Wait States Bit 0
M_BCW1 EQU
M_BRW EQU
1
; In Page Wait States Bit 1
$C
; Out Of Page Wait States Bits Mask (BRW0-BRW1)
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
Freescale Semiconductor
B-13
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Equates
M_BRW0
M_BRW1
M_BPS
EQU
EQU
2
;Out of Page Wait States bit 0
; Out of Page Wait States bit 1
; DRAM Page Size Bits Mask (BPS0-BPS1)
; DRAM Page Size Bits 0
; DRAM Page Size Bits 1
; Page Logic Enable
3
EQU
$300
4
M_BPS0
M_BPS1
EQU
EQU
5
M_BPLE EQU
11
M_BME
M_BRE
EQU
EQU
12
; Mastership Enable
13
; Refresh Enable
M_BSTR EQU
EQU
EQU
14
; Software Triggered Refresh
; Refresh Rate Bits Mask (BRF0-BRF7)
; Refresh Rate Bit 0
M_BRF
M_BRF0
M_BRF1
M_BRF2
M_BRF3
M_BRF4
M_BRF5
M_BRF6
M_BRF7
M_BRP
;
$7F8000
15
EQU
EQU
EQU
EQU
EQU
EQU
EQU
16
; Refresh Rate Bit 1
17
; Refresh Rate Bit 2
18
; Refresh Rate Bit 3
19
; Refresh Rate Bit 4
20
; Refresh Rate Bit 5
21
; Refresh Rate Bit 6
22
; Refresh Rate Bit 7
EQU
23
; Refresh prescaler
Address Attribute Registers
M_BAT
M_BAT0
M_BAT1
EQU
EQU
EQU
$3
0
; External Access Type and Pin Definition Bits Mask (BAT0-BAT1)
; External Access Type and Pin Definition Bits 0
; External Access Type and Pin Definition Bits 1
; Address Attribute Pin Polarity
1
M_BAAP EQU
M_BPEN EQU
M_BXEN EQU
M_BYEN EQU
2
3
; Program Space Enable
4
; X Data Space Enable
5
; Y Data Space Enable
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
B-14
Freescale Semiconductor
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Equates
M_BAM
M_BPAC EQU
EQU
EQU
EQU
6
; Address Muxing
7
; Packing Enable
M_BNC
M_BNC0
M_BNC1
M_BNC2
M_BNC3
M_BAC
M_BAC0
M_BAC1
M_BAC2
M_BAC3
M_BAC4
M_BAC5
M_BAC6
M_BAC7
M_BAC8
M_BAC9
M_BAC10
M_BAC11
;
$F00
8
; Number of Address Bits to Compare Mask (BNC0-BNC3)
; Number of Address Bits to Compare 0
; Number of Address Bits to Compare 1
; Number of Address Bits to Compare 2
; Number of Address Bits to Compare 3
; Address to Compare Bits Mask (BAC0-BAC11)
; Address to Compare Bits 0
EQU
EQU
EQU
9
10
11
$FFF000
12
13
14
15
16
17
18
19
20
21
22
23
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
; Address to Compare Bits 1
; Address to Compare Bits 2
; Address to Compare Bits 3
; Address to Compare Bits 4
; Address to Compare Bits 5
; Address to Compare Bits 6
; Address to Compare Bits 7
; Address to Compare Bits 8
; Address to Compare Bits 9
EQU
EQU
; Address to Compare Bits 10
; Address to Compare Bits 11
control and status bits in SR
M_C
EQU
EQU
0
; Carry
M_V
1
; Overflow
; Zero
M_Z
EQU
EQU
EQU
EQU
EQU
2
3
4
5
6
M_N
; Negative
; Unnormalized
; Extension
; Limit
M_U
M_E
M_L
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
Freescale Semiconductor
B-15
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Equates
M_S
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
7
; Scaling Bit
M_I0
M_I1
M_S0
M_S1
M_SC
M_DM
M_LF
M_FV
M_SA
M_CE
M_SM
M_RM
M_CP
M_CP0
M_CP1
;
8
; Interupt Mask Bit 0
; Interupt Mask Bit 1
; Scaling Mode Bit 0
9
10
11
13
14
15
16
17
19
20
21
$c00000
22
23
; Scaling Mode Bit 1
; Sixteen_Bit Compatibility
; Double Precision Multiply
; DO-Loop Flag
; DO-Forever Flag
; Sixteen-Bit Arithmetic
; Instruction Cache Enable
; Arithmetic Saturation
; Rounding Mode
; mask for CORE-DMA priority bits in SR
; bit 0 of priority bits in SR
; bit 1 of priority bits in SR
control and status bits in OMR
M_MA
M_MB
M_MC
M_MD
M_EBD
M_SD
M_MS
M_CDP
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
0
; Operating Mode A
1
; Operating Mode B
2
; Operating Mode C
3
; Operating Mode D
4
; External Bus Disable bit in OMR
; Stop Delay
6
7
;Memory Switch Mode
$300
8
; mask for CORE-DMA priority bits in OMR
; bit 0 of priority bits in OMR Core DMA
; bit 1 of priority bits in OMR Core DMA
M_CDP0 EQU
M_CDP1 EQU
9
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
B-16
Freescale Semiconductor
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Equates
M_BE
EQU
EQU
EQU
10
11
12
13
; Burst Enable
M_TAS
M_BRT
; TA Synchronize Select
; Bus Release Timing
M_ABE EQU
M_APD EQU
M_ATE EQU
;Async. Bus Arbitration Enable
;Addess Priority Disable
14
15
;Address Tracing Enable
M_XYS
M_EUN
M_EOV
M_WRP
M_SEN
EQU
16
; Stack Extension space select bit in OMR.
; Extensed stack UNderflow flag in OMR.
; Extended stack OVerflow flag in OMR.
; Extended WRaP flag in OMR.
; Stack Extension Enable bit in OMR.
; Patch Enable
EQU
EQU
EQU
EQU
17
18
19
20
M_PAEN EQU
23
;------------------------------------------------------------------------
;
;
;
EQUATES for DAX (SPDIF Tx)
;------------------------------------------------------------------------
Register Addresses
;
M_XSTR EQU
M_XADRB EQU
$FFFFD4
$FFFFD3
$FFFFD2
$FFFFD2
$FFFFD1
$FFFFD0
; DAX Status Register (XSTR)
; DAX Audio Data Register B (XADRB)
;DAX Audio Data Register (XADR)
; DAX Audio Data Register A (XADRA)
; DAX Non-Audio Data Register (XNADR)
; DAX Control Register (XCTR)
M_XADR
EQU
M_XADRA EQU
M_XNADR EQU
M_XCTR EQU
;
status bits in XSTR
M_XADE EQU
M_XAUR EQU
0
1
; DAX Audio Data Register Empty (XADE)
; DAX Trasmit Underrun Error Flag (XAUR)
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
Freescale Semiconductor
B-17
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Equates
M_XBLK EQU
2
; DAX Block Transferred (XBLK)
;
non-audio bits in XNADR
M_XVA
M_XUA
M_XCA
M_XVB
M_XUB
M_XCB
;
EQU
EQU
EQU
EQU
EQU
EQU
10
11
12
13
14
15
; DAX Channel A Validity (XVA)
; DAX Channel A User Data (XUA)
; DAX Channel A Channel Status (XCA)
; DAX Channel B Validity (XVB)
; DAX Channel B User Data (XUB)
; DAX Channel B Channel Status (XCB)
control bits in XCTR
M_XDIE EQU
M_XUIE EQU
M_XBIE EQU
M_XCS0 EQU
M_XCS1 EQU
0
1
2
3
4
5
; DAX Audio Data Register Empty Interrupt Enable (XDIE)
; DAX Underrun Error Interrupt Enable (XUIE)
; DAX Block Transferred Interrupt Enable (XBIE)
; DAX Clock Input Select 0 (XCS0)
; DAX Clock Input Select 1 (XCS1)
M_XSB
EQU
; DAX Start Block (XSB)
;------------------------------------------------------------------------
;
;
;
EQUATES for SHI
;------------------------------------------------------------------------
;
Register Addresses
M_HRX
M_HTX
EQU
EQU
$FFFF94
$FFFF93
$FFFF92
$FFFF91
$FFFF90
; SHI Receive FIFO (HRX)
; SHI Transmit Register (HTX)
M_HSAR EQU
M_HCSR EQU
M_HCKR EQU
; SHI I2C Slave Address Register (HSAR)
; SHI Control/Status Register (HCSR)
; SHI Clock Control Register (HCKR)
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
B-18
Freescale Semiconductor
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Equates
;
HSAR bits
EQU
M_HA6
M_HA5
M_HA4
M_HA3
M_HA1
;
23
22
21
20
18
; SHI I2C Slave Address (HA6)
; SHI I2C Slave Address (HA5)
; SHI I2C Slave Address (HA4)
; SHI I2C Slave Address (HA3)
; SHI I2C Slave Address (HA1)
EQU
EQU
EQU
EQU
control and status bits in HCSR
M_HBUSY EQU
M_HBER EQU
M_HROE EQU
M_HRFF EQU
M_HRNE EQU
M_HTDE EQU
M_HTUE EQU
M_HRIE1 EQU
M_HRIE0 EQU
M_HTIE EQU
M_HBIE EQU
M_HIDLE EQU
M_HRQE1 EQU
M_HRQE0 EQU
M_HMST EQU
M_HFIFO EQU
M_HCKFR EQU
22
21
20
19
17
15
14
13
12
11
10
9
; SHI Host Busy (HBUSY)
; SHI Bus Error (HBER)
; SHI Receive Overrun Error (HROE)
; SHI Receivr FIFO Full (HRFF)
; SHI Receive FIFO Not Empty (HRNE)
; SHI Host Transmit data Empty (HTDE)
; SHI Host Transmit Underrun Error (HTUE)
; SHI Receive Interrupt Enable (HRIE1)
; SHI Receive Interrupt Enable (HRIE0)
; SHI Transmit Interrupt Enable (HTIE)
; SHI Bus-Error Interrupt Enable (HBIE)
; SHI Idle (HIDLE)
8
; SHI Host Request Enable (HRQE1)
; SHI Host Request Enable (HRQE0)
; SHI Master Mode (HMST)
7
6
5
; SHI FIFO Enable Control (HFIFO)
; SHI Clock Freeze (HCKFR)
4
M_HM1
M_HM0
EQU
EQU
3
; SHI Serial Host Interface Mode (HM1)
; SHI Serial Host Interface Mode (HM0)
; SHI I2c/SPI Selection (HI2C)
; SHI Host Enable (HEN)
2
M_HI2C EQU
M_HEN EQU
1
0
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
Freescale Semiconductor
B-19
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Equates
;
control bits in HCKR
M_HFM1 EQU
M_HFM0 EQU
M_HDM7 EQU
M_HDM6 EQU
M_HDM5 EQU
M_HDM4 EQU
M_HDM3 EQU
M_HDM2 EQU
M_HDM1 EQU
M_HDM0 EQU
13
12
10
9
; SHI Filter Model (HFM1)
; SHI Filter Model (HFM0)
; SHI Divider Modulus Select (HDM7)
; SHI Divider Modulus Select (HDM6)
; SHI Divider Modulus Select (HDM5)
; SHI Divider Modulus Select (HDM4)
; SHI Divider Modulus Select (HDM3)
; SHI Divider Modulus Select (HDM2)
; SHI Divider Modulus Select (HDM1)
; SHI Divider Modulus Select (HDM0)
; SHI Prescalar Rate Select (HRS)
; SHI Clock Polarity (CPOL)
8
7
6
5
4
3
M_HRS
EQU
2
M_CPOL EQU
M_CPHA EQU
1
0
; SHI Clock Phase (CPHA)
;------------------------------------------------------------------------
;
;
EQUATES for ESAI_1 Registers
; register bit equates can be the same as for the ESAI register bit equates.
;------------------------------------------------------------------------
;
Register Addresses
M_EMUXR EQU
M_RSMB_1 EQU
M_RSMA_1 EQU
M_TSMB_1 EQU
M_TSMA_1 EQU
M_RCCR_1 EQU
$FFFFAF
$FFFF9C
$FFFF9B
$FFFF9A
$FFFF99
$FFFF98
; MUX PIN CONTROL REGISTER (EMUXR)
; ESAI_1 Receive Slot Mask Register B (RSMB_1)
; ESAI_1 Receive Slot Mask Register A (RSMA_1)
; ESAI_1 Transmit Slot Mask Register B (TSMB_1)
; ESAI_1 Transmit Slot Mask Register A (TSMA_1)
; ESAI_1 Receive Clock Control Register (RCCR_1)
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
B-20
Freescale Semiconductor
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Equates
M_RCR_1 EQU
M_TCCR_1 EQU
M_TCR_1 EQU
M_SAICR_1 EQU
M_SAISR_1 EQU
M_RX3_1 EQU
M_RX2_1 EQU
M_RX1_1 EQU
M_RX0_1 EQU
M_TSR_1 EQU
M_TX5_1 EQU
M_TX4_1 EQU
M_TX3_1 EQU
M_TX2_1 EQU
M_TX1_1 EQU
M_TX0_1 EQU
$FFFF97
$FFFF96
$FFFF95
$FFFF94
$FFFF93
$FFFF8B
$FFFF8A
$FFFF89
$FFFF88
$FFFF86
$FFFF85
$FFFF84
$FFFF83
$FFFF82
$FFFF81
$FFFF80
; ESAI_1 Receive Control Register (RCR_1)
; ESAI_1 Transmit Clock Control Register (TCCR_1)
; ESAI_1 Transmit Control Register (TCR_1)
; ESAI_1 Control Register (SAICR_1)
; ESAI_1 Status Register (SAISR_1)
; ESAI_1 Receive Data Register 3 (RX3_1)
; ESAI_1 Receive Data Register 2 (RX2_1)
; ESAI_1 Receive Data Register 1 (RX1_1)
; ESAI_1 Receive Data Register 0 (RX0_1)
; ESAI_1 Time Slot Register (TSR_1)
; ESAI_1 Transmit Data Register 5 (TX5_1)
; ESAI_1 Transmit Data Register 4 (TX4_1)
; ESAI_1 Transmit Data Register 3 (TX3_1)
; ESAI_1 Transmit Data Register 2 (TX2_1)
; ESAI_1 Transmit Data Register 1 (TX1_1)
; ESAI_1 Transmit Data Register 0 (TX0_1)
;------------------------------------------------------------------------
;
;
;
EQUATES for ESAI
;------------------------------------------------------------------------
Register Addresses
;
M_RSMB EQU
M_RSMA EQU
M_TSMB EQU
M_TSMA EQU
M_RCCR EQU
$FFFFBC
$FFFFBB
$FFFFBA
$FFFFB9
$FFFFB8
; ESAI Receive Slot Mask Register B (RSMB)
; ESAI Receive Slot Mask Register A (RSMA)
; ESAI Transmit Slot Mask Register B (TSMB)
; ESAI Transmit Slot Mask Register A (TSMA)
; ESAI Receive Clock Control Register (RCCR)
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
Freescale Semiconductor
B-21
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Equates
M_RCR
EQU
$FFFFB7
$FFFFB6
$FFFFB5
$FFFFB4
$FFFFB3
$FFFFAB
$FFFFAA
$FFFFA9
$FFFFA8
$FFFFA6
$FFFFA5
$FFFFA4
$FFFFA3
$FFFFA2
$FFFFA1
$FFFFA0
; ESAI Receive Control Register (RCR)
; ESAI Transmit Clock Control Register (TCCR)
; ESAI Transmit Control Register (TCR)
; ESAI Control Register (SAICR)
M_TCCR EQU
M_TCR EQU
M_SAICR EQU
M_SAISR EQU
; ESAI Status Register (SAISR)
M_RX3
M_RX2
M_RX1
M_RX0
M_TSR
M_TX5
M_TX4
M_TX3
M_TX2
M_TX1
M_TX0
;
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
; ESAI Receive Data Register 3 (RX3)
; ESAI Receive Data Register 2 (RX2)
; ESAI Receive Data Register 1 (RX1)
; ESAI Receive Data Register 0 (RX0)
; ESAI Time Slot Register (TSR)
; ESAI Transmit Data Register 5 (TX5)
; ESAI Transmit Data Register 4 (TX4)
; ESAI Transmit Data Register 3 (TX3)
; ESAI Transmit Data Register 2 (TX2)
; ESAI Transmit Data Register 1 (TX1)
; ESAI Transmit Data Register 0 (TX0)
RSMB Register bits
M_RS31 EQU
M_RS30 EQU
M_RS29 EQU
M_RS28 EQU
M_RS27 EQU
M_RS26 EQU
M_RS25 EQU
M_RS24 EQU
M_RS23 EQU
M_RS22 EQU
15
14
13
12
11
10
9
; ESAI
; ESAI
; ESAI
; ESAI
; ESAI
; ESAI
; ESAI
; ESAI
; ESAI
; ESAI
8
7
6
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
B-22
Freescale Semiconductor
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Equates
M_RS21 EQU
M_RS20 EQU
M_RS19 EQU
M_RS18 EQU
M_RS17 EQU
M_RS16 EQU
5
4
3
2
1
0
; ESAI
; ESAI
; ESAI
; ESAI
; ESAI
; ESAI
;
RSMA Register bits
M_RS15 EQU
M_RS14 EQU
M_RS13 EQU
M_RS12 EQU
M_RS11 EQU
M_RS10 EQU
15
14
13
12
11
10
9
; ESAI
; ESAI
; ESAI
; ESAI
; ESAI
; ESAI
; ESAI
; ESAI
; ESAI
; ESAI
; ESAI
; ESAI
; ESAI
; ESAI
; ESAI
; ESAI
M_RS9
M_RS8
M_RS7
M_RS6
M_RS5
M_RS4
M_RS3
M_RS2
M_RS1
M_RS0
;
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
8
7
6
5
4
3
2
1
0
TSMB Register bits
M_TS31 EQU
M_TS30 EQU
M_TS29 EQU
M_TS28 EQU
15
14
13
12
; ESAI
; ESAI
; ESAI
; ESAI
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
Freescale Semiconductor
B-23
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Equates
M_TS27 EQU
M_TS26 EQU
M_TS25 EQU
M_TS24 EQU
M_TS23 EQU
M_TS22 EQU
M_TS21 EQU
M_TS20 EQU
M_TS19 EQU
M_TS18 EQU
M_TS17 EQU
M_TS16 EQU
11
10
9
; ESAI
; ESAI
; ESAI
; ESAI
; ESAI
; ESAI
; ESAI
; ESAI
; ESAI
; ESAI
; ESAI
; ESAI
8
7
6
5
4
3
2
1
0
;
TSMA Register bits
M_TS15 EQU
M_TS14 EQU
M_TS13 EQU
M_TS12 EQU
M_TS11 EQU
M_TS10 EQU
15
14
13
12
11
10
9
; ESAI
; ESAI
; ESAI
; ESAI
; ESAI
; ESAI
; ESAI
; ESAI
; ESAI
; ESAI
; ESAI
; ESAI
; ESAI
; ESAI
M_TS9
M_TS8
M_TS7
M_TS6
M_TS5
M_TS4
M_TS3
M_TS2
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
8
7
6
5
4
3
2
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
B-24
Freescale Semiconductor
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Equates
M_TS1
M_TS0
;
EQU
EQU
1
0
; ESAI
; ESAI
RCCR Register bits
M_RHCKD EQU
M_RFSD EQU
M_RCKD EQU
M_RHCKP EQU
M_RFSP EQU
M_RCKP EQU
23
22
21
; ESAI
; ESAI
; ESAI
;ESAI
20
19
18
; ESAI
;ESAI
M_RFP
EQU
$3C000
;ESAI MASK
; ESAI
; ESAI
; ESAI
; ESAI
;ESAI MASK
; ESAI
; ESAI
; ESAI
; ESAI
; ESAI
; ESAI
M_RFP3 EQU
M_RFP2 EQU
M_RFP1 EQU
M_RFP0 EQU
17
16
15
14
M_RDC
EQU
$3E00
13
M_RDC4 EQU
M_RDC3 EQU
M_RDC2 EQU
M_RDC1 EQU
M_RDC0 EQU
M_RPSR EQU
12
11
10
9
8
M_RPM
EQU
$FF
7
M_RPM7 EQU
M_RPM6 EQU
M_RPM5 EQU
M_RPM4 EQU
M_RPM3 EQU
M_RPM2 EQU
; ESAI
; ESAI
; ESAI
; ESAI
; ESAI
; ESAI
6
5
4
3
2
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
Freescale Semiconductor
B-25
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Equates
M_RPM1 EQU
M_RPM0 EQU
1
0
; ESAI
; ESAI
;
RCR Register bits
M_RLIE EQU
M_RIE EQU
23
22
21
20
; ESAI
; ESAI
; ESAI
; ESAI
M_REDIE EQU
M_REIE EQU
M_RPR
EQU
19
;
ESAI
M_RFSR EQU
M_RFSL EQU
16
15
; ESAI
; ESAI
M_RSWS
EQU
$7C00
;ESAI MASK
; ESAI
M_RSWS4 EQU
M_RSWS3 EQU
M_RSWS2 EQU
M_RSWS1 EQU
M_RSWS0 EQU
14
13
12
11
10
; ESAI
; ESAI
; ESAI
; ESAI
M_RMOD
EQU
$300
M_RMOD1 EQU
M_RMOD0 EQU
M_RWA EQU
M_RSHFD EQU
9
; ESAI
; ESAI
8
7
; ESAI
; ESAI
6
M_RE
M_RE3
M_RE2
M_RE1
M_RE0
;
EQU
$F
EQU
EQU
EQU
EQU
3
2
1
0
; ESAI
; ESAI
; ESAI
; ESAI
TCCR Register bits
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
B-26
Freescale Semiconductor
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Equates
M_THCKD EQU
M_TFSD EQU
M_TCKD EQU
M_THCKP EQU
M_TFSP EQU
M_TCKP EQU
23
22
21
; ESAI
; ESAI
; ESAI
;ESAI
20
19
18
; ESAI
; ESAI
M_TFP
EQU
$3C000
M_TFP3 EQU
M_TFP2 EQU
M_TFP1 EQU
M_TFP0 EQU
17
16
15
14
; ESAI
; ESAI
; ESAI
; ESAI
M_TDC
EQU
$3E00
;
M_TDC4 EQU
M_TDC3 EQU
M_TDC2 EQU
M_TDC1 EQU
M_TDC0 EQU
M_TPSR EQU
13
12
11
10
9
; ESAI
; ESAI
; ESAI
; ESAI
; ESAI
; ESAI
;
8
M_TPM
EQU
$FF
7
M_TPM7 EQU
M_TPM6 EQU
M_TPM5 EQU
M_TPM4 EQU
M_TPM3 EQU
M_TPM2 EQU
M_TPM1 EQU
M_TPM0 EQU
; ESAI
; ESAI
; ESAI
; ESAI
; ESAI
; ESAI
; ESAI
; ESAI
6
5
4
3
2
1
0
;
TCR Register bits
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
Freescale Semiconductor
B-27
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Equates
M_TLIE EQU
23
22
21
20
; ESAI
; ESAI
; ESAI
; ESAI
M_TIE
EQU
M_TEDIE EQU
M_TEIE EQU
M_TPR
EQU
EQU
19
17
;
;
ESAI
ESAI
M_PADC
M_TFSR EQU
M_TFSL EQU
M_TSWS EQU
M_TSWS4 EQU
M_TSWS3 EQU
M_TSWS2 EQU
M_TSWS1 EQU
M_TSWS0 EQU
16
15
; ESAI
; ESAI
$7C00
14
; ESAI
; ESAI
; ESAI
; ESAI
; ESAI
13
12
11
10
M_TMOD
EQU
$300
M_TMOD1 EQU
M_TMOD0 EQU
M_TWA EQU
M_TSHFD EQU
M_TEM
9
8
; ESAI
; ESAI
7
; ESAI
; ESAI
6
EQU
$3F
M_TE5
M_TE4
M_TE3
M_TE2
M_TE1
M_TE0
;
EQU
EQU
EQU
EQU
EQU
EQU
5
4
3
2
1
0
; ESAI
; ESAI
; ESAI
; ESAI
; ESAI
; ESAI
control bits of SAICR
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
B-28
Freescale Semiconductor
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Equates
M_ALC EQU 8
M_TEBE EQU
;ESAI
; ESAI
7
6
2
1
0
M_SYN
M_OF2
M_OF1
M_OF0
;
EQU
EQU
EQU
EQU
; ESAI
; ESAI
; ESAI
; ESAI
status bits of SAISR
M_TODE EQU
M_TEDE EQU
17
16
15
14
13
10
9
; ESAI
; ESAI
; ESAI
; ESAI
; ESAI
; ESAI
; ESAI
; ESAI
; ESAI
; ESAI
; ESAI
; ESAI
; ESAI
M_TDE
M_TUE
M_TFS
EQU
EQU
EQU
M_RODF EQU
M_REDF EQU
M_RDF
M_ROE
M_RFS
M_IF2
M_IF1
M_IF0
EQU
EQU
EQU
EQU
EQU
EQU
8
7
6
2
1
0
;------------------------------------------------------------------------
;
;
;
EQUATES for HDI08
;------------------------------------------------------------------------
;
Register Addresses
M_HOTX
EQU
$FFFFC7
; HOST Transmit Register (HOTX)
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
Freescale Semiconductor
B-29
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Equates
M_HORX
EQU
$FFFFC6
$FFFFC5
$FFFFC4
$FFFFC3
$FFFFC2
; HOST Receive Register (HORX)
; HOST Base Address Register (HBAR)
; HOST Port Control Register (HPCR)
; HOST Status Register (HSR)
M_HBAR EQU
M_HPCR EQU
M_HSR
M_HCR
;
EQU
EQU
; HOST Control Register (HCR)
HCR bits
M_HRIE EQU
M_HOTIE EQU
M_HCIE EQU
$0
$1
$2
$3
$4
$5
$6
$7
; HOST Receive interrupts Enable
; HOST Transmit Interrupt Enable
; HOST Command Interrupt Enable
; HOST Flag 2
M_HF2
M_HF3
EQU
EQU
; HOST Flag 3
M_HODM0 EQU
M_HODM1 EQU
M_HODM2 EQU
; HOST DMA Mode Control Bit 0
; HOST DMA Mode Control Bit 1
; HOST DMA Mode Control Bit 2
;
HSR bits
M_HRDF EQU
M_HOTDE EQU
$0
$1
$2
$3
$4
$7
; HOST Receive Data Full
; HOST Receive Data Emptiy
; HOST Command Pending
; HOST Flag 0
M_HCP
M_HF0
M_HF1
M_DMA
EQU
EQU
EQU
EQU
; HOST Flag 1
; HOST DMA Status
;
HPCR bits
M_HGEN EQU
M_HA8EN EQU
M_HA9EN EQU
$0
$1
$2
; HOST Port Enable
; HOST Address 8 Enable
; HOST Address 9 Enable
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
B-30
Freescale Semiconductor
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Equates
M_HCSEN EQU
M_HREN EQU
M_HAEN EQU
$3
$4
$5
; HOST Chip Select Enable
; HOST Request Enable
; HOST Acknowledge Enable
; HOST Enable
M_HOEN
M_HROD
EQU
EQU
$6
$8
$9
; HOST Request Open Dranin mode
; HOST Data Strobe Polarity
; HOST Address Strobe Polarity
; HOST Multiplexed bus select
; HOST Double/Single Strobe select
; HOST Chip Select Polarity
; HOST Request Polarity
M_HDSP EQU
M_HASP EQU
M_HMUX EQU
M_HDDS EQU
M_HCSP EQU
$a
$b
$c
$d
$e
$f
M_HRP
M_HAP
;
EQU
EQU
; HOST Acknowledge Polarity
HBAR BITS
M_BA EQU $FF
M_BA10 EQU 7
M_BA9 EQU 6
M_BA8 EQU 5
M_BA7 EQU 4
M_BA6 EQU 3
M_BA5 EQU 2
M_BA4 EQU 1
M_BA3 EQU 0
;-----------------------------------------------------------------------
;
;
;
EQUATES for TIMER
;------------------------------------------------------------------------
Register Addresses Of TIMER0
;
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
Freescale Semiconductor
B-31
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Equates
M_TCSR0 EQU
M_TLR0 EQU
M_TCPR0 EQU
M_TCR0 EQU
$FFFF8F
$FFFF8E
$FFFF8D
$FFFF8C
; TIMER0 Control/Status Register
; TIMER0 Load Reg
; TIMER0 Compare Register
; TIMER0 Count Register
;
Register Addresses Of TIMER1
M_TCSR1 EQU
M_TLR1 EQU
M_TCPR1 EQU
M_TCR1 EQU
$FFFF8B
$FFFF8A
$FFFF89
$FFFF88
; TIMER1 Control/Status Register
; TIMER1 Load Reg
; TIMER1 Compare Register
; TIMER1 Count Register
;
Register Addresses Of TIMER2
M_TCSR2 EQU
M_TLR2 EQU
M_TCPR2 EQU
M_TCR2 EQU
M_TPLR EQU
M_TPCR EQU
$FFFF87
$FFFF86
$FFFF85
$FFFF84
$FFFF83
$FFFF82
; TIMER2 Control/Status Register
; TIMER2 Load Reg
; TIMER2 Compare Register
; TIMER2 Count Register
; TIMER Prescaler Load Register
; TIMER Prescalar Count Register
;
Timer Control/Status Register Bit Flags
M_TE
EQU
0
; Timer Enable
M_TOIE EQU
M_TCIE EQU
1
; Timer Overflow Interrupt Enable
; Timer Compare Interrupt Enable
; Timer Control Mask (TC0-TC3)
; Inverter Bit
2
M_TC
EQU
EQU
EQU
EQU
EQU
EQU
EQU
$F0
8
M_INV
M_TRM
M_DIR
M_DI
9
; Timer Restart Mode
; Direction Bit
11
12
13
15
; Data Input
M_DO
; Data Output
M_PCE
; Prescaled Clock Enable
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
B-32
Freescale Semiconductor
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Equates
M_TOF
M_TCF
;
EQU
EQU
20
21
; Timer Overflow Flag
; Timer Compare Flag
Timer Prescaler Register Bit Flags
EQU $600000 ; Prescaler Source Mask
M_PS
M_PS0 EQU 21
M_PS1 EQU 22
; Timer Control Bits
M_TC0
M_TC1
M_TC2
M_TC3
EQU
EQU
EQU
EQU
4
5
6
7
; Timer Control 0
; Timer Control 1
; Timer Control 2
; Timer Control 3
;------------------ end of ioequ.asm ------------------------
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
Freescale Semiconductor
B-33
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Equates
NOTES
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
B-34
Freescale Semiconductor
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Appendix C JTAG BSDL
-- FILENAME : 56366TQFP_revA.bsdl
--
-- M O T O R O L A S S D T J T A G S O F T W A R E
-- BSDL File Generated: Mon Jan 18 10:13:53 1999
--
-- Revision History:
--
entity DSP56366 is
generic (PHYSICAL_PIN_MAP : string := "TQFP144");
port ( TDO:out
TDI:in
bit;
bit;
bit;
bit;
bit;
bit;
bit;
bit;
bit;
bit;
TMS:in
TCK:in
SCK:inout
SDO0:inout
SDO1:inout
SDOI23:inout
PINIT:in
SDOI32:inout
SVCC:linkage bit_vector(0 to 1);
SGND:linkage bit_vector(0 to 1);
SDOI41:inout
SDOI50:inout
FST:inout
bit;
bit;
bit;
bit;
bit;
bit;
bit;
bit;
FSR:inout
SCKT:inout
SCKR:inout
HSCKT:inout
HSCKR:inout
QVCC:linkage bit_vector(0 to 3);
QGND:linkage bit_vector(0 to 3);
QVCCH:linkage bit_vector(0 to 2);
HP:inout
ADO:inout
ACI:inout
TIO:inout
bit_vector(0 to 15);
bit;
bit;
bit;
HVCC:linkage bit;
HGND:linkage bit;
SS_:in
HREQ_:inout
RESET_:in
bit;
bit;
bit;
PVCC:linkage bit;
PCAP:linkage bit;
PGND:linkage bit;
AA:out
bit_vector(0 to 2);
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
Freescale Semiconductor
C-1
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JTAG BSDL
CAS_:out
EXTAL:in
bit;
bit;
CVCC:linkage bit_vector(0 to 1);
CGND:linkage bit_vector(0 to 1);
TA_:in
bit;
BR_:buffer bit;
BB_:inout
WR_:out
RD_:out
BG_:in
bit;
bit;
bit;
bit;
A:out
bit_vector(0 to 17);
AVCC:linkage bit_vector(0 to 2);
AGND:linkage bit_vector(0 to 3);
D:inout
bit_vector(0 to 23);
DVCC:linkage bit_vector(0 to 3);
DGND:linkage bit_vector(0 to 3);
MODD:in
MODC:in
MODB:in
MODA:in
MOSI:inout
SDA:inout
bit;
bit;
bit;
bit;
bit;
bit;
bit;
bit;
bit;
bit;
bit;
bit);
SDO41_1:inout
SDO50_1:inout
FST_1:inout
FSR_1:inout
SCKR_1:inout
SCKT_1:inout
use STD_1149_1_1994.all;
attribute COMPONENT_CONFORMANCE of DSP56366 : entity is "STD_1149_1_1993";
attribute PIN_MAP of DSP56366 : entity is PHYSICAL_PIN_MAP;
constant TQFP144 : PIN_MAP_STRING :=
"SCK:
1, " &
"SS_:
2, " &
"HREQ_:
"SDO0:
"SDO1:
"SDOI23:
"SDOI32:
"SVCC:
"SGND:
"SDOI41:
"SDOI50:
"FST:
3, " &
4, " &
5, " &
6, " &
7, " &
(8, 25), " &
(9, 26), " &
10, " &
11, " &
12, " &
"FSR:
13, " &
"SCKT:
"SCKR:
"HSCKT:
"HSCKR:
"QVCC:
"QGND:
14, " &
15, " &
16, " &
17, " &
(18, 56, 91, 126), " &
(19, 54, 90, 127), " &
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
C-2
Freescale Semiconductor
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JTAG BSDL
"QVCCH:
"HP:
(20, 49, 95), " &
(43, 42, 41, 40, 37, 36, 35, 34, 33, 32, 31, 22, 21, 30, 24, 23), " &
"ADO:
"ACI:
"TIO:
"HVCC:
"HGND:
"RESET_:
"PVCC:
"PCAP:
"PGND:
27, " &
28, " &
29, " &
38, " &
39, " &
44, " &
45, " &
46, " &
47, " &
"SDO50_1: 48, " &
"FST_1:
"AA:
50, " &
(70, 69, 51), " &
"CAS_:
"SCKT_1:
"EXTAL:
"CVCC:
"CGND:
"FSR_1:
"SCKR_1:
"PINIT:
"TA_:
52, " &
53, " &
55, " &
(57, 65), " &
(58, 66), " &
59, " &
60, " &
61, " &
62, " &
"BR_:
63, " &
"BB_:
64, " &
"WR_:
67, " &
"RD_:
68, " &
"BG_:
71, " &
"A:
(72, 73, 76, 77, 78, 79, 82, 83, 84, 85, 88, 89, 92, 93, 94, 97, 98, 99), " &
(74, 80, 86), " &
(75, 81, 87, 96), " &
"AVCC:
"AGND:
"D:
(100, 101, 102, 105, 106, 107, 108, 109, 110, 113, 114, 115, 116, 117, 118,
121, " &
"122, 123, 124, 125, 128, 131, 132, 133), " &
"DVCC:
"DGND:
"MODD:
"MODC:
"MODB:
"MODA:
(103, 111, 119, 129), " &
(104, 112, 120, 130), " &
134, " &
135, " &
136, " &
137, " &
"SDO41_1: 138, " &
"TDO:
"TDI:
"TCK:
"TMS:
"MOSI:
"SDA:
139, " &
140, " &
141, " &
142, " &
143, " &
144 ";
attribute TAP_SCAN_IN
of TDI : signal is true;
attribute TAP_SCAN_OUT of TDO : signal is true;
attribute TAP_SCAN_MODE of TMS : signal is true;
attribute TAP_SCAN_CLOCK of TCK : signal is (20.0e6, BOTH);
attribute INSTRUCTION_LENGTH of DSP56366 : entity is 4;
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
Freescale Semiconductor
C-3
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JTAG BSDL
attribute INSTRUCTION_OPCODE of DSP56366 : entity is
"EXTEST
"SAMPLE
"IDCODE
"CLAMP
"HIGHZ
(0000)," &
(0001)," &
(0010)," &
(0101)," &
(0100)," &
"ENABLE_ONCE (0110)," &
"DEBUG_REQUEST(0111)," &
"BYPASS
(1111)";
attribute INSTRUCTION_CAPTURE of DSP56366 : entity is "0001";
attribute IDCODE_REGISTER of DSP56366 : entity is
"0000"
& -- version
"000111"
"0001001111"
& -- manufacturer's use
& -- sequence number
"00000001110" & -- manufacturer identity
"1"; -- 1149.1 requirement
attribute REGISTER_ACCESS of DSP56366 : entity is
"ONCE[8] (ENABLE_ONCE,DEBUG_REQUEST)" ;
attribute BOUNDARY_LENGTH of DSP56366 : entity is 152;
attribute BOUNDARY_REGISTER of DSP56366 : entity is
-- num
"0
cell port func
safe [ccell dis rslt]
1)," &
(BC_1, *,
control,
"1
(BC_6, SDO41_1, bidir,
X,
0, 1, Z)," &
"2
"3
"4
"5
"6
"7
"8
"9
(BC_1, MODA,
(BC_1, MODB,
(BC_1, MODC,
(BC_1, MODD,
(BC_6, D(23),
(BC_6, D(22),
(BC_6, D(21),
(BC_6, D(20),
(BC_6, D(19),
(BC_6, D(18),
(BC_6, D(17),
(BC_6, D(16),
(BC_6, D(15),
(BC_1, *,
input,
input,
input,
input,
bidir,
bidir,
bidir,
bidir,
bidir,
bidir,
bidir,
bidir,
bidir,
control,
bidir,
bidir,
bidir,
bidir,
X)," &
X)," &
X)," &
X)," &
1,
X,
X,
X,
X,
X,
X,
X,
X,
1)," &
X,
X,
X,
X,
15, 1, Z)," &
15, 1, Z)," &
15, 1, Z)," &
15, 1, Z)," &
15, 1, Z)," &
15, 1, Z)," &
15, 1, Z)," &
15, 1, Z)," &
15, 1, Z)," &
"10
"11
"12
"13
"14
"15
"16
"17
"18
"19
-- num
"20
"21
"22
"23
"24
"25
"26
"27
(BC_6, D(14),
(BC_6, D(13),
(BC_6, D(12),
(BC_6, D(11),
15, 1, Z)," &
15, 1, Z)," &
15, 1, Z)," &
28, 1, Z)," &
cell port func
safe [ccell dis rslt]
(BC_6, D(10),
(BC_6, D(9),
(BC_6, D(8),
(BC_6, D(7),
(BC_6, D(6),
(BC_6, D(5),
(BC_6, D(4),
(BC_6, D(3),
bidir,
X,
X,
X,
X,
X,
X,
X,
X,
28, 1, Z)," &
28, 1, Z)," &
28, 1, Z)," &
28, 1, Z)," &
28, 1, Z)," &
28, 1, Z)," &
28, 1, Z)," &
28, 1, Z)," &
bidir,
bidir,
bidir,
bidir,
bidir,
bidir,
bidir,
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
C-4
Freescale Semiconductor
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JTAG BSDL
"28
"29
"30
"31
"32
"33
"34
"35
"36
"37
"38
"39
-- num
"40
"41
"42
"43
"44
"45
"46
"47
"48
"49
"50
"51
"52
"53
"54
"55
"56
"57
"58
"59
-- num
"60
"61
"62
"63
"64
"65
"66
"67
"68
"69
"70
"71
"72
"73
"74
"75
"76
"77
"78
"79
-- num
(BC_1, *,
control,
bidir,
bidir,
1)," &
X,
X,
X,
X,
X,
X,
1)," &
X,
X,
(BC_6, D(2),
(BC_6, D(1),
(BC_6, D(0),
(BC_1, A(17),
(BC_1, A(16),
(BC_1, A(15),
(BC_1, *,
(BC_1, A(14),
(BC_1, A(13),
(BC_1, A(12),
(BC_1, A(11),
28, 1, Z)," &
28, 1, Z)," &
28, 1, Z)," &
35, 1, Z)," &
35, 1, Z)," &
35, 1, Z)," &
bidir,
output3,
output3,
output3,
control,
output3,
output3,
output3,
output3,
35, 1, Z)," &
35, 1, Z)," &
35, 1, Z)," &
35, 1, Z)," &
X,
X,
cell port func
safe [ccell dis rslt]
(BC_1, A(10),
(BC_1, A(9),
(BC_1, A(8),
(BC_1, A(7),
(BC_1, A(6),
(BC_1, *,
(BC_1, A(5),
(BC_1, A(4),
(BC_1, A(3),
(BC_1, A(2),
(BC_1, A(1),
(BC_1, A(0),
(BC_1, BG_,
(BC_1, *,
(BC_1, AA(0),
(BC_1, *,
(BC_1, AA(1),
(BC_1, RD_,
(BC_1, WR_,
(BC_1, *,
output3,
X,
X,
X,
X,
X,
1)," &
X,
X,
X,
X,
X,
X,
X)," &
1)," &
X,
1)," &
X,
35, 1, Z)," &
35, 1, Z)," &
45, 1, Z)," &
45, 1, Z)," &
45, 1, Z)," &
output3,
output3,
output3,
output3,
control,
output3,
output3,
output3,
output3,
output3,
output3,
input,
control,
output3,
control,
output3,
output3,
output3,
control,
45, 1, Z)," &
45, 1, Z)," &
45, 1, Z)," &
45, 1, Z)," &
45, 1, Z)," &
45, 1, Z)," &
53, 1, Z)," &
55, 1, Z)," &
68, 1, Z)," &
68, 1, Z)," &
X,
X,
1)," &
cell port func
safe [ccell dis rslt]
(BC_6, BB_,
(BC_1, BR_,
(BC_1, TA_,
(BC_1, PINIT,
(BC_1, *,
(BC_6, SCKR_1, bidir,
(BC_1, *,
(BC_6, FSR_1,
(BC_1, *,
(BC_1, EXTAL,
(BC_1, *,
(BC_6, SCKT_1, bidir,
(BC_1, *,
(BC_1, CAS_,
(BC_1, *,
(BC_1, AA(2),
(BC_1, *,
(BC_6, FST_1,
(BC_1, *,
(BC_6, SDO50_1, bidir,
cell port func
bidir,
output2,
input,
input,
control,
X,
59, 1, Z)," &
X)," &
X)," &
X)," &
1)," &
X,
1)," &
X,
1)," &
X)," &
1)," &
X,
1)," &
X,
1)," &
X,
1)," &
X,
1)," &
X,
64, 1, Z)," &
66, 1, Z)," &
control,
bidir,
control,
input,
control,
70, 1, Z)," &
72, 1, Z)," &
74, 1, Z)," &
76, 1, Z)," &
78, 1, Z)," &
control,
output3,
control,
output3,
control,
bidir,
control,
safe [ccell dis rslt]
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
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JTAG BSDL
"80
"81
"82
"83
"84
"85
"86
"87
"88
"89
"90
"91
"92
"93
"94
"95
"96
"97
"98
"99
-- num
(BC_1, RESET_, input,
X)," &
1)," &
X,
1)," &
X,
1)," &
X,
1)," &
X,
1)," &
X,
1)," &
X,
1)," &
X,
1)," &
X,
(BC_1, *,
(BC_6, HP(0),
(BC_1, *,
(BC_6, HP(1),
(BC_1, *,
(BC_6, HP(2),
(BC_1, *,
(BC_6, HP(3),
(BC_1, *,
(BC_6, HP(4),
(BC_1, *,
(BC_6, HP(5),
(BC_1, *,
(BC_6, HP(6),
(BC_1, *,
control,
bidir,
control,
bidir,
control,
bidir,
control,
bidir,
control,
bidir,
control,
bidir,
control,
bidir,
control,
bidir,
81, 1, Z)," &
83, 1, Z)," &
85, 1, Z)," &
87, 1, Z)," &
89, 1, Z)," &
91, 1, Z)," &
93, 1, Z)," &
95, 1, Z)," &
97, 1, Z)," &
(BC_6, HP(7),
(BC_1, *,
(BC_6, HP(8),
(BC_1, *,
control,
bidir,
control,
1)," &
X,
1)," &
cell port func
safe [ccell dis rslt]
"100 (BC_6, HP(9),
"101 (BC_1, *,
"102 (BC_6, HP(10), bidir,
"103 (BC_1, *, control,
"104 (BC_6, HP(13), bidir,
bidir,
control,
X,
1)," &
X,
1)," &
X,
1)," &
X,
1)," &
X,
1)," &
X,
1)," &
X,
1)," &
X,
99, 1, Z)," &
101, 1, Z)," &
103, 1, Z)," &
105, 1, Z)," &
107, 1, Z)," &
109, 1, Z)," &
111, 1, Z)," &
113, 1, Z)," &
115, 1, Z)," &
117, 1, Z)," &
"105 (BC_1, *,
"106 (BC_6, TIO,
"107 (BC_1, *,
"108 (BC_6, ACI,
"109 (BC_1, *,
"110 (BC_6, ADO,
"111 (BC_1, *,
"112 (BC_6, HP(14), bidir,
"113 (BC_1, *, control,
"114 (BC_6, HP(15), bidir,
"115 (BC_1, *, control,
"116 (BC_6, HP(11), bidir,
"117 (BC_1, *, control,
"118 (BC_6, HP(12), bidir,
control,
bidir,
control,
bidir,
control,
bidir,
control,
1)," &
X,
1)," &
X,
"119 (BC_1, *,
-- num
control,
cell port func
1)," &
safe [ccell dis rslt]
"120 (BC_6, HSCKR,
"121 (BC_1, *,
"122 (BC_6, HSCKT,
"123 (BC_1, *,
"124 (BC_6, SCKR,
"125 (BC_1, *,
"126 (BC_6, SCKT,
"127 (BC_1, *,
"128 (BC_6, FSR,
"129 (BC_1, *,
"130 (BC_6, FST,
"131 (BC_1, *,
bidir,
control,
bidir,
control,
bidir,
control,
bidir,
control,
bidir,
control,
bidir,
X,
1)," &
X,
1)," &
X,
1)," &
X,
1)," &
X,
1)," &
X,
1)," &
X,
119, 1, Z)," &
121, 1, Z)," &
123, 1, Z)," &
125, 1, Z)," &
127, 1, Z)," &
129, 1, Z)," &
131, 1, Z)," &
control,
"132 (BC_6, SDOI50, bidir,
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"133 (BC_1, *,
"134 (BC_6, SDOI41, bidir,
"135 (BC_1, *, control,
"136 (BC_6, SDOI32, bidir,
"137 (BC_1, *, control,
"138 (BC_6, SDOI23, bidir,
control,
1)," &
X,
1)," &
X,
1)," &
X,
133, 1, Z)," &
135, 1, Z)," &
137, 1, Z)," &
"139 (BC_1, *,
-- num
control,
cell port func
1)," &
safe [ccell dis rslt]
"140 (BC_6, SDO1,
"141 (BC_1, *,
"142 (BC_6, SDO0,
"143 (BC_1, *,
"144 (BC_6, HREQ_,
"145 (BC_1, SS_,
"146 (BC_1, *,
"147 (BC_6, SCK,
"148 (BC_1, *,
"149 (BC_6, SDA,
"150 (BC_1, *,
"151 (BC_6, MOSI,
bidir,
control,
bidir,
control,
bidir,
input,
control,
bidir,
control,
bidir,
control,
bidir,
X,
1)," &
X,
1)," &
X,
X)," &
1)," &
X,
1)," &
X,
1)," &
X,
139, 1, Z)," &
141, 1, Z)," &
143, 1, Z)," &
146, 1, Z)," &
148, 1, Z)," &
150, 1, Z)";
end DSP56366;
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
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JTAG BSDL
NOTES
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Appendix D Programmer’s Reference
D.1
Introduction
This section has been compiled as a reference for programmers. It contains a table showing the addresses
of all the DSPs memory-mapped peripherals, an interrupt address table, an interrupt exception priority
table, a quick reference to the host interface, and programming sheets for the major programmable
registers on the DSP.
D.1.1
Peripheral Addresses
Table D-1 lists the memory addresses of all on-chip peripherals.
D.1.2
Interrupt Addresses
Table D-2 lists the interrupt starting addresses and sources.
D.1.3
Interrupt Priorities
Table D-3 lists the priorities of specific interrupts within interrupt priority levels.
D.1.4
Host Interface Quick Reference
Table D-4 is a quick reference guide to the host interface (HDI08).
D.1.5
Programming Sheets
The remaining figures describe major programmable registers on the DSP56366.
D.2
Internal I/O Memory Map
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Internal I/O Memory Map
Table D-1. Internal I/O Memory Map
Register Name
Peripheral
Address
IPR
X:$FFFFFF
X:$FFFFFE
X:$FFFFFD
X:$FFFFFC
X:$FFFFFB
X:$FFFFFA
X:$FFFFF9
X:$FFFFF8
X:$FFFFF7
X:$FFFFF6
X:$FFFFF5
X:$FFFFF4
X:$FFFFF3
X:$FFFFF2
X:$FFFFF1
X:$FFFFF0
X:$FFFFEF
X:$FFFFEE
X:$FFFFED
X:$FFFFEC
X:$FFFFEB
X:$FFFFEA
X:$FFFFE9
X:$FFFFE8
X:$FFFFE7
X:$FFFFE6
X:$FFFFE5
X:$FFFFE4
X:$FFFFE3
X:$FFFFE2
X:$FFFFE1
X:$FFFFE0
INTERRUPT PRIORITY REGISTER CORE (IPR-C)
INTERRUPT PRIORITY REGISTER PERIPHERAL (IPR-P)
PLL CONTROL REGISTER (PCTL)
PLL
ONCE
BIU
ONCE GDB REGISTER (OGDB)
BUS CONTROL REGISTER (BCR)
DRAM CONTROL REGISTER (DCR)
ADDRESS ATTRIBUTE REGISTER 0 (AAR0)
ADDRESS ATTRIBUTE REGISTER 1 (AAR1)
ADDRESS ATTRIBUTE REGISTER 2 (AAR2)
ADDRESS ATTRIBUTE REGISTER 3 (AAR3) [pin not available]
ID REGISTER (IDR)
DMA
DMA STATUS REGISTER (DSTR)
DMA OFFSET REGISTER 0 (DOR0)
DMA OFFSET REGISTER 1 (DOR1)
DMA OFFSET REGISTER 2 (DOR2)
DMA OFFSET REGISTER 3 (DOR3)
DMA0
DMA1
DMA2
DMA3
DMA SOURCE ADDRESS REGISTER (DSR0)
DMA DESTINATION ADDRESS REGISTER (DDR0)
DMA COUNTER (DCO0)
DMA CONTROL REGISTER (DCR0)
DMA SOURCE ADDRESS REGISTER (DSR1)
DMA DESTINATION ADDRESS REGISTER (DDR1)
DMA COUNTER (DCO1)
DMA CONTROL REGISTER (DCR1)
DMA SOURCE ADDRESS REGISTER (DSR2)
DMA DESTINATION ADDRESS REGISTER (DDR2)
DMA COUNTER (DCO2)
DMA CONTROL REGISTER (DCR2)
DMA SOURCE ADDRESS REGISTER (DSR3)
DMA DESTINATION ADDRESS REGISTER (DDR3)
DMA COUNTER (DCO3)
DMA CONTROL REGISTER (DCR3)
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Internal I/O Memory Map
Table D-1. Internal I/O Memory Map (continued)
Peripheral
Address
Register Name
DMA SOURCE ADDRESS REGISTER (DSR4)
DMA DESTINATION ADDRESS REGISTER (DDR4)
DMA COUNTER (DCO4)
DMA4
X:$FFFFDF
X:$FFFFDE
X:$FFFFDD
X:$FFFFDC
X:$FFFFDB
X:$FFFFDA
X:$FFFFD9
X:$FFFFD8
X:$FFFFD7
X:$FFFFD6
X:$FFFFD5
X:$FFFFD4
X:$FFFFD3
X:$FFFFD2
X:$FFFFD1
X:$FFFFD0
X:$FFFFCF
X:$FFFFCE
X:$FFFFCD
X:$FFFFCC
X:$FFFFCB
X:$FFFFCA
X:$FFFFC9
X:$FFFFC8
X:$FFFFC7
X:$FFFFC6
X:$FFFFC5
X:$FFFFC4
X:$FFFFC3
X:$FFFFC2
X:$FFFFC1
X:$FFFFC0
X:$FFFFBF
X:$FFFFBE
X:$FFFFBD
DMA CONTROL REGISTER (DCR4)
DMA SOURCE ADDRESS REGISTER (DSR5)
DMA DESTINATION ADDRESS REGISTER (DDR5)
DMA COUNTER (DCO5)
DMA5
DMA CONTROL REGISTER (DCR5)
PORT D CONTROL REGISTER (PCRD)
PORT D DIRECTION REGISTER (PRRD)
PORT D DATA REGISTER (PDRD)
DAX STATUS REGISTER (XSTR)
DAX AUDIO DATA REGISTER B (XADRB)
DAX AUDIO DATA REGISTER A (XADRA)
DAX NON-AUDIO DATA REGISTER (XNADR)
DAX CONTROL REGISTER (XCTR)
Reserved
PORT D
DAX
Reserved
Reserved
Reserved
Reserved
Reserved
PORT B
HDI08
HOST PORT GPIO DATA REGISTER (HDR)
HOST PORT GPIO DIRECTION REGISTER (HDDR)
HOST TRANSMIT REGISTER (HOTX)
HOST RECEIVE REGISTER (HORX)
HOST BASE ADDRESS REGISTER (HBAR)
HOST PORT CONTROL REGISTER (HPCR)
HOST STATUS REGISTER (HSR)
HOST CONTROL REGISTER (HCR)
Reserved
Reserved
PORT C
PORT C CONTROL REGISTER (PCRC)
PORT C DIRECTION REGISTER (PRRC)
PORT C GPIO DATA REGISTER (PDRC)
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Internal I/O Memory Map
Table D-1. Internal I/O Memory Map (continued)
Address
Peripheral
Register Name
ESAI RECEIVE SLOT MASK REGISTER B (RSMB)
ESAI RECEIVE SLOT MASK REGISTER A (RSMA)
ESAI TRANSMIT SLOT MASK REGISTER B (TSMB)
ESAI TRANSMIT SLOT MASK REGISTER A (TSMA)
ESAI RECEIVE CLOCK CONTROL REGISTER (RCCR)
ESAI RECEIVE CONTROL REGISTER (RCR)
ESAI TRANSMIT CLOCK CONTROL REGISTER (TCCR)
ESAI TRANSMIT CONTROL REGISTER (TCR)
ESAI COMMON CONTROL REGISTER (SAICR)
ESAI STATUS REGISTER (SAISR)
Reserved
ESAI
X:$FFFFBC
X:$FFFFBB
X:$FFFFBA
X:$FFFFB9
X:$FFFFB8
X:$FFFFB7
X:$FFFFB6
X:$FFFFB5
X:$FFFFB4
X:$FFFFB3
X:$FFFFB2
X:$FFFFB1
X:$FFFFB0
X:$FFFFAF
X:$FFFFAE
X:$FFFFAD
X:$FFFFAC
X:$FFFFAB
X:$FFFFAA
X:$FFFFA9
X:$FFFFA8
X:$FFFFA7
X:$FFFFA6
X:$FFFFA5
X:$FFFFA4
X:$FFFFA3
X:$FFFFA2
X:$FFFFA1
X:$FFFFA0
X:$FFFF9F
X:$FFFF9E
X:$FFFF9D
X:$FFFF9C
X:$FFFF9B
X:$FFFF9A
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
ESAI RECEIVE DATA REGISTER 3 (RX3)
ESAI RECEIVE DATA REGISTER 2 (RX2)
ESAI RECEIVE DATA REGISTER 1 (RX1)
ESAI RECEIVE DATA REGISTER 0 (RX0)
Reserved
ESAI TIME SLOT REGISTER (TSR)
ESAI TRANSMIT DATA REGISTER 5 (TX5)
ESAI TRANSMIT DATA REGISTER 4 (TX4)
ESAI TRANSMIT DATA REGISTER 3 (TX3)
ESAI TRANSMIT DATA REGISTER 2 (TX2)
ESAI TRANSMIT DATA REGISTER 1 (TX1)
ESAI TRANSMIT DATA REGISTER 0 (TX0)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
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Internal I/O Memory Map
Table D-1. Internal I/O Memory Map (continued)
Address Register Name
Peripheral
X:$FFFF99
X:$FFFF98
X:$FFFF97
X:$FFFF96
X:$FFFF95
X:$FFFF94
X:$FFFF93
X:$FFFF92
X:$FFFF91
X:$FFFF90
X:$FFFF8F
X:$FFFF8E
X:$FFFF8D
X:$FFFF8C
X:$FFFF8B
X:$FFFF8A
X:$FFFF89
X:$FFFF88
X:$FFFF87
X:$FFFF86
X:$FFFF85
X:$FFFF84
X:$FFFF83
X:$FFFF82
X:$FFFF81
X:$FFFF80
Y:$FFFFAF
Reserved
Reserved
Reserved
Reserved
Reserved
SHI
SHI RECEIVE FIFO (HRX)
SHI TRANSMIT REGISTER (HTX)
2
SHI I C SLAVE ADDRESS REGISTER (HSAR)
SHI CONTROL/STATUS REGISTER (HCSR)
SHI CLOCK CONTROL REGISTER (HCKR)
TIMER 0 CONTROL/STATUS REGISTER (TCSR0)
TIMER 0 LOAD REGISTER (TLR0)
TRIPLE TIMER
TIMER 0 COMPARE REGISTER (TCPR0)
TIMER 0 COUNT REGISTER (TCR0)
TIMER 1 CONTROL/STATUS REGISTER (TCSR1)
TIMER 1 LOAD REGISTER (TLR1)
TIMER 1 COMPARE REGISTER (TCPR1)
TIMER 1 COUNT REGISTER (TCR1)
TIMER 2 CONTROL/STATUS REGISTER (TCSR2)
TIMER 2 LOAD REGISTER (TLR2)
TIMER 2 COMPARE REGISTER (TCPR2)
TIMER 2 COUNT REGISTER (TCR2)
TIMER PRESCALER LOAD REGISTER (TPLR)
TIMER PRESCALER COUNT REGISTER (TPCR)
Reserved
Reserved
ESAI MUX PIN
CONTROL
ESAI MUX PIN CONTROL REGISTER (EMUXR)
Y:$FFFFAE
Y:$FFFFAD
Y:$FFFFAC
Y:$FFFFAB
Y:$FFFFAA
Y:$FFFFA9
Y:$FFFFA8
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
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Internal I/O Memory Map
Peripheral
Table D-1. Internal I/O Memory Map (continued)
Address Register Name
Y:$FFFFA7
Y:$FFFFA6
Y:$FFFFA5
Y:$FFFFA4
Y:$FFFFA3
Y:$FFFFA2
Y:$FFFFA1
Y:$FFFFA0
Y:$FFFF9F
Y:$FFFF9E
Y:$FFFF9D
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PORT E
PORT E CONTROL REGISTER (PCRE)
PORT E DIRECTION REGISTER(PRRE)
PORT E GPIO DATA REGISTER(PDRE)
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Internal I/O Memory Map
Table D-1. Internal I/O Memory Map (continued)
Address Register Name
Peripheral
ESAI_1
Y:$FFFF9C
Y:$FFFF9B
Y:$FFFF9A
Y:$FFFF99
Y:$FFFF98
Y:$FFFF97
Y:$FFFF96
Y:$FFFF95
Y:$FFFF94
Y:$FFFF93
Y:$FFFF92
Y:$FFFF91
Y:$FFFF90
Y:$FFFF8F
Y:$FFFF8E
Y:$FFFF8D
Y:$FFFF8C
Y:$FFFF8B
Y:$FFFF8A
Y:$FFFF89
Y:$FFFF88
Y:$FFFF87
Y:$FFFF86
Y:$FFFF85
Y:$FFFF84
Y:$FFFF83
Y:$FFFF82
Y:$FFFF81
Y:$FFFF80
ESAI_1 RECEIVE SLOT MASK REGISTER B (RSMB_1)
ESAI_1 RECEIVE SLOT MASK REGISTER A (RSMA_1)
ESAI_1 TRANSMIT SLOT MASK REGISTER B (TSMB_1)
ESAI_1 TRANSMIT SLOT MASK REGISTER A (TSMA_1)
ESAI_1 RECEIVE CLOCK CONTROL REGISTER (RCCR_1)
ESAI_1 RECEIVE CONTROL REGISTER (RCR_1)
ESAI_1 TRANSMIT CLOCK CONTROL REGISTER (TCCR_1)
ESAI_1 TRANSMIT CONTROL REGISTER (TCR_1)
ESAI_1 COMMON CONTROL REGISTER (SAICR_1)
ESAI_1 STATUS REGISTER (SAISR_1)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
ESAI_1 RECEIVE DATA REGISTER 3 (RX3_1)
ESAI_1 RECEIVE DATA REGISTER 2 (RX2_1)
ESAI_1 RECEIVE DATA REGISTER 1 (RX1_1)
ESAI_1 RECEIVE DATA REGISTER 0 (RX0_1)
Reserved
ESAI_1 TIME SLOT REGISTER (TSR_1)
ESAI_1 TRANSMIT DATA REGISTER 5 (TX5_1)
ESAI_1 TRANSMIT DATA REGISTER 4 (TX4_1)
ESAI_1 TRANSMIT DATA REGISTER 3 (TX3_1)
ESAI_1 TRANSMIT DATA REGISTER 2 (TX2_1)
ESAI_1 TRANSMIT DATA REGISTER 1 (TX1_1)
ESAI_1 TRANSMIT DATA REGISTER 0 (TX0_1)
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Interrupt Vector Addresses
D.3
Interrupt Vector Addresses
Table D-2. DSP56366 Interrupt Vectors
Interrupt
Starting Address
Interrupt Priority
Interrupt Source
Level Range
3
VBA:$00
VBA:$02
VBA:$04
VBA:$06
VBA:$08
VBA:$0A
VBA:$0C
VBA:$0E
VBA:$10
VBA:$12
VBA:$14
VBA:$16
VBA:$18
VBA:$1A
VBA:$1C
VBA:$1E
VBA:$20
VBA:$22
VBA:$24
VBA:$26
VBA:$28
VBA:$2A
VBA:$2C
VBA:$2E
VBA:$30
VBA:$32
VBA:$34
VBA:$36
VBA:$38
VBA:$3A
VBA:$3C
VBA:$3E
VBA:$40
Hardware RESET
Stack Error
3
3
Illegal Instruction
Debug Request Interrupt
Trap
3
3
3
Non-Maskable Interrupt (NMI)
Reserved For Future Level-3 Interrupt Source
Reserved For Future Level-3 Interrupt Source
IRQA
3
3
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
IRQB
IRQC
IRQD
DMA Channel 0
DMA Channel 1
DMA Channel 2
DMA Channel 3
DMA Channel 4
DMA Channel 5
Reserved
Reserved
DAX Underrun Error
DAX Block Transferred
Reserved
DAX Audio Data Empty
ESAI Receive Data
ESAI Receive Even Data
ESAI Receive Data With Exception Status
ESAI Receive Last Slot
ESAI Transmit Data
ESAI Transmit Even Data
ESAI Transmit Data with Exception Status
ESAI Transmit Last Slot
SHI Transmit Data
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Interrupt Vector Addresses
Table D-2. DSP56366 Interrupt Vectors (continued)
Interrupt
Starting Address
Interrupt Priority
Interrupt Source
Level Range
VBA:$42
VBA:$44
VBA:$46
VBA:$48
VBA:$4A
VBA:$4C
VBA:$4E
VBA:$50
VBA:$52
VBA:$54
VBA:$56
VBA:$58
VBA:$5A
VBA:$5C
VBA:$5E
VBA:$60
VBA:$62
VBA:$64
VBA:$66
VBA:$68
VBA:$6A
VBA:$6C
VBA:$6E
VBA:$70
VBA:$72
VBA:$74
VBA:$76
VBA:$78
VBA:$7A
VBA:$7C
VBA:$7E
VBA:$80
:
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
0 - 2
:
SHI Transmit Underrun Error
SHI Receive FIFO Not Empty
Reserved
SHI Receive FIFO Full
SHI Receive Overrun Error
SHI Bus Error
Reserved
Reserved
Reserved
TIMER0 Compare
TIMER0 Overflow
TIMER1 Compare
TIMER1 Overflow
TIMER2 Compare
TIMER2 Overflow
Host Receive Data Full
Host Transmit Data Empty
Host Command (Default)
Reserved
Reserved
Reserved
Reserved
Reserved
ESAI_1 Receive Data
ESAI_1 Receive Even Data
ESAI_1 Receive Data With Exception Status
ESAI_1 Receive Last Slot
ESAI_1 Transmit Data
ESAI_1 Transmit Even Data
ESAI_1 Transmit Data with Exception Status
ESAI_1 Transmit Last Slot
Reserved
:
VBA:$FE
0 - 2
Reserved
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Interrupt Source Priorities (within an IPL)
D.4
Interrupt Source Priorities (within an IPL)
Table D-3. Interrupt Sources Priorities Within an IPL
Priority
Level 3 (Nonmaskable)
Highest
Interrupt Source
Hardware RESET
Stack Error
Illegal Instruction
Debug Request Interrupt
Trap
Lowest
Non-Maskable Interrupt
Levels 0, 1, 2 (Maskable)
Highest
IRQA (External Interrupt)
IRQB (External Interrupt)
IRQC (External Interrupt)
IRQD (External Interrupt)
DMA Channel 0 Interrupt
DMA Channel 1 Interrupt
DMA Channel 2 Interrupt
DMA Channel 3 Interrupt
DMA Channel 4 Interrupt
DMA Channel 5 Interrupt
ESAI Receive Data with Exception Status
ESAI Receive Even Data
ESAI Receive Data
ESAI Receive Last Slot
ESAI Transmit Data with Exception Status
ESAI Transmit Last Slot
ESAI Transmit Even Data
ESAI Transmit Data
SHI Bus Error
SHI Receive Overrun Error
SHI Transmit Underrun Error
SHI Receive FIFO Full
SHI Transmit Data
SHI Receive FIFO Not Empty
HOST Command Interrupt
HOST Receive Data Interrupt
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
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Interrupt Source Priorities (within an IPL)
Table D-3. Interrupt Sources Priorities Within an IPL (continued)
Priority Interrupt Source
HOST Transmit Data Interrupt
DAX Transmit Underrun Error
DAX Block Transferred
DAX Transmit Register Empty
TIMER0 Overflow Interrupt
TIMER0 Compare Interrupt
TIMER1 Overflow Interrupt
TIMER1 Compare Interrupt
TIMER2 Overflow Interrupt
TIMER2 Compare Interrupt
ESAI_1 Receive Data with Exception Status
ESAI_1 Receive Even Data
ESAI_1 Receive Data
ESAI_1 Receive Last Slot
ESAI_1 Transmit Data with Exception Status
ESAI_1 Transmit Last Slot
ESAI_1 Transmit Even Data
ESAI_1 Transmit Data
Lowest
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
Freescale Semiconductor
D-11
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Host Interface—Quick Reference
D.5
Host Interface—Quick Reference
Table D-4. HDI08 Programming Model
Bit
Reset Type
Reg
Comments
HW /
SW
Num Mnemonic
Name
Val
Function
IR
ST
DSP SIDE
HCR
0
1
2
HRIE
HTIE
HCIE
Receive Interrupt Enable
Transmit Interrupt Enable
0
1
HRRQ interrupt disabled
HRRQ interrupt enabled
0
-
-
-
-
-
-
0
1
HTRQ interrupt disabled
HTRQ interrupt enabled
0
Host Command Interrupt
Enable
0
1
HCP interrupt disabled
HCP interrupt enabled
0
3
4
HF2
HF3
Host Flag 2
Host Flag 3
0
0
-
-
7-5
HDM[2:0] Host DMA Mode
000 DMA operation disabled
000
100 DMA operation enabled
001 24-bit host-to-DSP DMA enabled
010 16-bit host-to-DSP DMA enabled
011 8-bit host-to-DSP DMA enabled
101 24-bit DSP-to-host DMA enabled
110 16-bit DSP-to-host DMA enabled
111 8-bit DSP-to-host DMA enabled
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
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Host Interface—Quick Reference
Reset Type
Table D-4. HDI08 Programming Model (continued)
Bit
Reg
Comments
HW /
SW
Num Mnemonic
Name
Val
Function
IR
ST
HPCR
0
1
HGEN
Host GPIO Enable
0
1
GPIO pin disconnected
GPIO pins active
0
-
-
HA8EN
Host Address Line 8
Enable
0
HA8/HA1 = GPIO
this bit is treated
as 1 if HMUX=0
0
-
-
-
-
this bit is treated
as 0 if HEN=0
1
0
HA8/HA1 = HA8/HA1
HA9/HA2 = GPIO
2
HA9EN
Host Address Line 9
Enable
this bit is treated
as 1 if HMUX=0
0
this bit is treated
as 0 if HEN=0
1
HA9/HA2 = HA9/HA2
3
4
HCSEN
HREN
Host Chip Select Enable
Host Request Enable
0
1
HCS/HA10 = GPIO
this bit is treated
as 0 if HEN=0
0
0
-
-
-
-
HCS/HA10 = HCS/HA10
0
1
0
HOREQ/HTRQ = GPIO
HACK/HRRQ=GPIO
this bit is treated
as 0 if HEN=0
HOREQ/HTRQ=HOREQ/HTRQ
HACK/HRRQ=HACK/HRRQ
5
HAEN
Host Acknowledge Enable
HACK/HRRQ = GPIO
this bit is ignored if
HDRQ=1
0
-
-
this bit is treated
as 0 if HREN=0
1
HACK/HRRQ= HACK
this bit is treated
as 0 if HEN=0
6
HEN
HROD
HDSP
HASP
HMUX
HDDS
HCSP
HRP
Host Enable
0
1
Host Port=GPIO
Host Port Active
0
0
0
0
0
0
0
0
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
8
Host Request Open Drain
Host Data Strobe Polarity
0
1
HOREQ/HTRQ/HRRQ=driven
this bit is ignored if
HEN=0
HOREQ/HTRQ/HRRQ=open drain
9
0
1
HDS/HRD/HWR active low
HDS/HRD/HWR active high
this bit is ignored if
HEN=0
10
11
12
13
14
15
Host Address Strobe
Polarity
0
1
HAS active low
HAS active high
this bit is ignored if
HEN=0
Host Multiplxed Bus
0
1
Separate address and data lines
Multiplexed address/data
this bit is ignored if
HEN=0
Host Dual Data Strobe
Host Chip Select Polarity
Host Request polarity
Host Acknowledge Polarity
0
1
Single Data Strobe (HDS)
this bit is ignored if
HEN=0
Double Data Strobe (HWR, HRD)
0
1
HCS active low
HCS active high
this bit is ignored if
HEN=0
0
1
HOREQ/HTRQ/HRRQ active low
HOREQ/HTRQ/HRRQ active high
this bit is ignored if
HEN=0
HAP
0
1
HACK active low
HACK active high
this bit is ignored if
HEN=0
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
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Host Interface—Quick Reference
Table D-4. HDI08 Programming Model (continued)
Bit
Reset Type
Reg
Comments
HW /
SW
Num Mnemonic
Name
Val
Function
IR
ST
HSR
0
1
2
HRDF
HTDE
HCP
Host Receive Data Full
Host Transmit Data Empty
Host Command Pending
0
1
no receive data to be read
receive data register is full
0
0
0
1
0
transmit data register empty
transmit data reg. not empty
1
0
1
0
1
0
0
1
no host command pending
host command pending
3
4
7
HF0
HF1
DMA
Host Flag0
Host Flag1
DMA Status
0
0
0
-
-
-
-
-
-
0
1
DMA mode disabled
DMA mode enabled
HBAR
HORX
HOTX
HDR
7-0
BA10-BA3 Host base Address
Register
$80
23-0
23-0
15-0
DSP Receive Data
Register
empty
DSP Transmit Data
Register
empty
D15-D0
GPIO Pin Data
$000
0
-
-
-
-
HDDR
15-0 DR15-DR0 GPIO Pin Direction
0
1
Input
$000
0
Output
Host Side
ICR
0
1
2
RREQ
TREQ
HDRQ
Receive Request Enable
Transmit Request Enable
Double Host Request
0
1
HRRQ interrupt disabled
HRRQ interrupt enabled
0
0
0
-
-
-
-
-
-
0
1
HTRQ interrupt disabled
HTRQ interrupt enabled
0
1
HOREQ/HTRQ=HOREQ,
HACK/HRRQ=HACK
available if
HDM2-HDM0=000
HOREQ/HTRQ=HTRQ,
HACK/HRRQ=HRRQ
3
4
5
HF0
HF1
Host Flag 0
0
0
0
-
-
-
-
-
-
Host Flag 1
HLEND
Host Little Endian
0
1
“Big Endian” order
“Little Endian” order
available if
HDM2-HDM0=000
6-5
7
HM1-HM0 Host Mode Control
00 Interrupt Mode
available if
HDM2-HDM0=100
00
0
-
-
-
-
01 24-bit DMA enabled
10 16-bit DMA enabled
11 8-bit DMA enabled
INIT
Initialize
1
Reset data paths according to
TREQ and RREQ
cleared by HDI08
hardware
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
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Programming Sheets
Reset Type
Table D-4. HDI08 Programming Model (continued)
Bit
Reg
Comments
HW /
SW
Num Mnemonic
Name
Val
Function
IR
ST
ISR
0
1
2
RXDF
TXDE
TRDY
Receive Data Register Full
0
1
host receive register is empty
host receive register is full
0
1
1
0
0
Transmit Data Register
Empty
1
0
host transmit register empty
host transmit register full
1
1
1
1
Transmitter Ready
1
0
transmit FIF O (6 deep) is empty
transmit FIFO is not empty
3
4
7
HF2
HF3
Host Flag2
Host Flag3
Host Request
0
0
0
-
-
-
-
HREQ
0
1
HOREQ pin is deasserted
0
0
HOREQ pin is asserted (if enabled)
CVR
6-0
7
HV6-HV0 Host Command Vector
default vector
$2A
0
-
-
HC
Host Command
0
1
no host command pending
host command pending
cleared by HDI08
hardware when
the HC int. req. is
serviced
0
0
RXH/M/L 7-0
TXH/M/L 7-0
Host Receive Data
Register
empty
empty
-
Host Transmit Data
Register
IVR
7-0
IV7-IV0
Interrupt Register
68000 family vector register
$0F
-
D.6
Programming Sheets
The worksheets shown on the following pages contain listings of major programmable registers for the
DSP56366. The programming sheets are grouped into the following order:
•
•
•
•
•
•
•
Central Processor
Host Interface (HDI08)
Serial Host Interface (SHI)
Two Enhanced Serial Audio Interfaces (ESAI and ESAI_1)
Digital Audio Interface (DAX)
Timer/Event Controller (TEC)
GPIO (Ports B-E)
Each sheet provides room to write in the value of each bit and the hexadecimal value for each register.
Programmers can photocopy these sheets and reuse them for each application development project.
For details on the instruction set of the DSP56300 family chips, see the DSP56300 Family Manual.
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
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Programming Sheets
Date:
Application:
Programmer
:
Sheet 1 of 5
Carry
Overfow
Zero
Negative
Central Processor
Unnormalized ( U = Acc(47) xnor Acc(46) )
Extension
Limit
FFT Scaling ( S = Acc(46) xor Acc(45) )
Interrupt Mask
Exceptions Masked
00 None
01 IPL 0
10 IPL 0, 1
11 IPL 0, 1, 2
I(1:0)
Scaling Mode
S(1:0) Scaling Mode
00
01
10
11
No scaling
Scale down
Scale up
Reserved
Reserved
Sixteen-Bit Compatibilitity
Double Precision Multiply Mode
Loop Flag
DO-Forever Flag
Sixteenth-Bit Arithmetic
Reserved
Instruction Cache Enable
Arithmetic Saturation
Rounding Mode
Core Priority
CP(1:0) Core Priority
00
01
10
11
0 (lowest)
1
2
3 (highest)
23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
I0
7
S
6
L
5
E
4
U
3
N
2
Z
1
V
0
C
RM SM CE
SA FV LF DM SC
S1 S0 I1
CP1 CP0
*
0
*
0
Extended Mode Register (MR)
Read/Write
Mode Register (MR)
Reset = $C00300
Condition Code Register (CCR)
= Reserved, Program as 0
Status Register (SR)
*
Figure D-1. Status Register (SR)
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
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Programming Sheets
Date:
Application:
Programmer:
Sheet 2 of 5
Central Processor
Chip Operating Modes
MOD(D:A) Reset Vector Description
See Core Configuration Section.
External Bus Disable
Stop Delay
Memory Switch Mode
Core-DMA Priority
CDP(1:0)
Core-DMA Priority
Core vs DMA Priority
DMA accesses > Core
DMA accesses = Core
DMA accesses < Core
00
01
10
11
Burst Mode Enable
TA Synchronize Select
Bus Release Timing
Asynchronous Bus Arbitration Enable
Address Priority Disable
Address Tracing Enable
Stack Extension Space Select
Extended Stack Underflow Flag
Extended Stack Overflow Flag
Extended Stack Wrap Flag
Stack Extension Enable
Memory Switch Mode
Patch Enable
23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
MSW1 MSW0
EUN
ABE
XYS ATE APD BRT TAS BE CDP1CDP0 MS SD
PEN
SEN WRPEOV
EBD MD MC MB MA
*
0
System Stack Control
Status Register (SCS)
Extended Chip Operating
Mode Register (COM)
Chip Operating Mode
Register (COM)
Operating Mode Register (OMR) Read/Write Reset = $00030X
=
Reserved, Program as 0
*
Figure D-2. Operating Mode Register (OMR)
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
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Programming Sheets
Date:
Application:
Programmer:
Sheet 1 of 6
HOST (HDI08)
DSP Side
Host Receive Data (usually read by program)
23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Receive High Byte
Receive Middle Byte
Receive Low Byte
Host Receive Register (HORX)
X:$FFFEC6 Read Only
Reset = empty
Host Transmit Data (usually loaded by program)
23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Transmit High Byte
Transmit Middle Byte
Transmit Low Byte
Host Transmit Register (HOTX)
X:$FFFEC7 Write Only
Reset = empty
Figure D-6. Host Receive and Host Transmit Data Registers
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
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Programming Sheets
Date:
Application:
Programmer:
Sheet 2 of 6
Host Receive Interrupt Enable
0 = Disable 1 = Enable if HRDF = 1
HOST
(HDI08)
Host Transmit Interrupt Enable
0 = Disable 1 = Enable if HTDE = 1
Host Command Interrupt Enable
0 = Disable 1 = Enable if HCP = 1
Host Flag 2
Host Flag 3
Host DMA Control Bits
See Table 6-5 in Section 6
7
15
8
6
5
4
3
2
1
0
HDM0 HF3 HF2 HCIE HTIE HRIE
HDM2 HDM1
* *
0 0
Host Control Register (HCR)
X:$FFFFC2 Read /Write
Reset = $0
= Reserved, Program as 0
*
DSP Side
Host Receive Data Full
0 = Wait
1 = Read
Host Transmit Data Empty
0 = Wait 1 = Write
Host Command Pending
0 = Wait
1 = Ready
Host Flags
Read Only
DMA status
8
7
6
5
4
3
2
1
0
15
0 = DMA Mode Disabled
1 = DMA Mode Enabled
HF1 HF0 HCP HTDE HRDF
DMA
* * * *
0 0
0 0
Host Status Register (HSR)
X:$FFFFC3
Reset = $2
= Reserved, Program as 0
*
Figure D-7. Host Control and Status Registers
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
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Programming Sheets
Date:
Application:
Programmer:
Sheet 3 of 6
DSP Side
HOST (HDI08)
15
8
7
6
5
4
3
2
1
0
BA10
BA9
BA8
BA7
BA6
BA5
BA4
BA3
Host Base Address Register (HBAR)
X:$FFFFC5
* *
0 0
Reset = $80
Host GPIO Port Enable
0 = GPIO Pins Disconnected
1 = GPIO Pin Enable
Host Request Open Drain
HDRQ
HROD
HREN/HEW
0
0
1
1
0
1
0
1
1
1
1
1
Host Address Line 8 Enable
0 Æ HA8 = GPIO, 1 Æ HA8 = HA8
Host Address Line 9 Enable
0 Æ HA9 = GPIO, 1 Æ HA9 = HA9
Host Data Strobe Polarity
0 = Strobe Active Low, 1 = Strobe Active High
Host Chip Select Enable
0 Æ HCS/HAI0 = GPIO,
1 Æ HCS/HA10 = HCS, if HMUX = 0
1 Æ HCS/HA10 = HC10, if HMUX = 1
Host Address Strobe Polarity
0 = Strobe Active Low, 1 = Strobe Active High
Host Multiplexed Bus
0 = Nonmultiplexed, 1 = Multiplexed
Host Request Enable
0 Æ HOREQ/HACK = GPIO,
1 Æ HOREQ = HOREQ,
if HDRQ = 0
Host Dual Data Strobe
0 = Single Strobe, 1 = Dual Strobe
Host Chip Select Polarity
0 = HCS Active Low
HTRQ & HRRQ Enable
1 = HCS Active High
Host Acknowledge Enable
0 Æ HACK = GPIO
If HDRQ & HREN = 1,
HACK = HACK
Host Request Polarity
HDRQ
HRP
Host Enable
0
0
1
1
0
1
0
1
HOREQ Active Low
HOREQ Active High
HTRQ,HRRQ Active Low
HTRQ,HRRQ Active High
0 Æ HDI08 Disable
Pins = GPIO
1 Æ HDI08 Enable
Host Acknowledge Polarity
0 = HACK Active Low, 1 = HACK Active High
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
HAP
HRP HCSP HDDS HMUX HASP HDSP HROD
HEN
HAEN HREN HCSEN HA9EN HA8EN HGEN
Host Port Control
Register (HPCR)
*
0
X:$FFFFC4
Read/Write
Reset = $0
= Reserved, Program as 0
*
Figure D-8. Host Base Address and Host Port Control
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
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Programming Sheets
Date:
Application:
Programmer:
Sheet 4 of 6
Processor Side
HOST (HDI08)
Receive Request Enable
DMA Off
DMA On
0 = Interrupts Disabled
0 = Host -> DSP
1 = Interrupts Enabled
1 = DSP -> Host
Transmit Request Enable
DMA Off
DMA On
0 = Interrupts Disabled
0 = DSP -> Host
1 = Interrupts Enabled
1 = Host -> DSP
HDRQ HOREQ/HTRQ HACK/HRRQ
0
1
HOREQ
HTRQ
HACK
HRRQ
Host Flags
Write Only
Host Little Endian
Initialize (Write Only)
0 = No Action
1 = Initialize DMA
7
6
5
4
3
2
1
0
HDM[2:0] = 000
INIT
HLEND HF1
HF0
HDRQ TREQ RREQ
*
For HM[1:0] bits, see
Table 6-12 in Section 6
0
HDM[2:0] = 100
HF1
HM1
HM0
TREQ
RREQ
*
HF0
HF0
0
INIT
INIT (HDM1) (HDM0)
HF1
TREQ RREQ
HDM1 and/or HDM0 = 1
*
0
Interrupt Control Register (ICR)
$0 R/W
Reset = $0
Receive Data Register Full
0 = Wait
1 = Read
Transmit Data Register Empty
0 = Wait 1 = Write
Transmitter Ready
0 = Data in HI 1 = Data Not in HI
Host Flags
Read Only
Host Request
0 = HOREQ Deasserted 1 = HOREQ Asserted
7
6
5
4
3
2
1
0
HREQ
HF3
HF2
TRDY TXDE RXDF
Interrupt Status Register (ISR)
*
*
0 0
$2 R/W
Reset = $0
= Reserved, Program as 0
*
Figure D-9. Host Interrupt Control and Interrupt Status
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
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Programming Sheets
Date:
Application:
Programmer:
Sheet 5 of 6
Processor Side
HOST (HDI08)
7
6
5
4
3
2
1
0
IV7
IV6
IV5
IV4
IV3
IV2
IV1
IV0
Interrupt Vector Register (IVR)
$3 R/W
Reset = $0F
Contains the interrupt vector or number
Host Vector
Contains Host Command Interrupt Address ÷ 2
Host Command
Handshakes Executing Host Command Interrupts
7
6
5
4
3
2
1
0
HC
HV6
HV5
HV4
HV3
HV2
HV1
HV0
Command Vector Register (CVR)
$1 R/W
Reset = $32
Contains the host command interrupt address
Figure D-10. Host Interrupt Vector and Command Vector
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
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Programming Sheets
Date:
Application:
Programmer:
Sheet 6 of 6
HOST (HDI08)
Processor Side
Host Receive Data (HLEND = 0)
7
0 7
0 7
0 7
0
Receive Low Byte
Receive Middle Byte
Receive High Byte
Not Used
0
0
0
0
0
0
0
0
$7
$6
$5
$4
Host Receive Data (HLEND = 1)
7
0 7
0 7
0 7
0
Receive Low Byte
Receive Middle Byte
Receive High Byte
Not Used
0
0
0
0
0
0
0
0
$5
$6
$7
$4
Receive Byte Registers
$7, $6, $5, $4 Read Only
Reset = Empty
Receive Byte Registers
Host Transmit Data (HLEND = 0)
7
0 7
0 7
0 7
0
Transmit Low Byte
Transmit Middle Byte
Transmit High Byte
Not Used
0
0
0
0
0
0
0
0
$7
$6
$5
$4
Host Transmit Data (HLEND = 1)
7
0 7
0 7
0 7
0
Transmit Low Byte
Transmit Middle Byte
Transmit High Byte
Not Used
0
0
0
0
0
0
0
0
$5
$6
$7
$4
Transmit Byte Registers
$7, $6, $5, $4 Write Only
Reset = Empty
Transmit Byte Registers
Figure D-11. Host Receive and Transmit Byte Registers
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
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Programming Sheets
Date:
Application:
Programmer:
Sheet 1 of 3
TEC
PS (1:0)
00
Prescaler Clock Source
Internal CLK/2
TIO0
01
10
Reserved
11
Reserved
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
PS1 PS0
Prescaler Preload Value (PL [0:20])
*
0
= Reserved, Program as 0
Timer Prescaler Load Register
TPLR:$FFFF83 Read/Write
Reset = $000000
*
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Current Value of Prescaler Counter (PC [0:20])
* * *
0 0 0
Timer Prescaler Count Register
TPCR:$FFFF82 Read Only
Reset = $000000
= Reserved, Program as 0
*
Figure D-30. Timer Prescaler Load and Prescaler Count Registers (TPLR, TPCR)
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
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Programming Sheets
Date:
Application:
Programmer:
Sheet 2 of 3
Inverter Bit 8
0 = 0- to-1 transitions on TIO input increment the counter,
or high pulse width measured, or high pulse output on TIO
TEC
1 = 1-to-0 transitions on TIO input increment the counter,
or low pulse width measured, or low pulse output on TIO
Timer Control Bits 4 – 7 (TC0 – TC3)
TIO Clock Mode
GPIO Internal Timer
Output Internal Timer Pulse
Output Internal Timer Toggle
Input External Event Counter
Timer Reload Mode Bit 9
TC (3:0)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0 = Timer operates as a free
running counter
1 = Timer is reloaded when
selected condition occurs
Input
Input
Input
Internal Input Width
Internal Input Period
Internal Capture
Direction Bit 11
0 = TIO pin is input
1 = TIO pin is output
Output Internal Pulse Width Modulation
Reserved
–
–
Data Input Bit 12
0 = Zero read on TIO pin
1 = One read on TIO pin
Output Internal Watchdog Pulse
Output Internal Watchdog Toggle
–
–
–
–
–
–
–
–
–
–
Reserved
Reserved
Reserved
Reserved
Reserved
Data Output Bit 13
0 = Zero written to TIO pin
1 = One written to TIO pin
Timer Enable Bit 0
Prescaled Clock Enable Bit 15
0 = Clock source is CLK/2 or TIO
1 = Clock source is prescaler output
0 = Timer Disabled
1 = Timer Enabled
Timer Overflow Interrupt Enable Bit 1
0 = Overflow Interrupts Disabled
1 = Overflow Interrupts Enabled
Timer Compare Flag Bit 21
0 = “1” has been written to TCSR(TCF),
or timer compare interrupt serviced
Timer Compare Interrupt Enable Bit 2
0 = Compare Interrupts Disabled
1 = Compare Interrupts Enabled
1 = Timer Compare has occurred
Timer Overflow Flag Bit 20
0 = “1” has been written to TCSR(TOF),
or timer Overflow interrupt serviced
1 = Counter wraparound has occurred
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
TCF TOF
PCE
DO
DI
DIR
TRM INV TC3 TC2 TC1 TC0
TCIE TOIE TE
* * * * * * *
*
0
*
0
0 0
0 0 0 0
0
Timer Control/Status Register
TCSR0:$FFFF8F Read/Write
TCSR1:$FFFF8B Read/Write
TCSR2:$FFFF87 Read/Write
Reset = $000000
= Reserved, Program as 0
*
Note that for Timers 1 and 2, TC (3:0) = 0000 is the only valid combination.
All other combinations are reserved.
Figure D-31. Timer Control/Status Register
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
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Programming Sheets
Date:
Application:
Programmer:
Sheet 3 of 3
TEC
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
7
7
6
6
6
5
5
5
4
4
4
3
3
3
2
2
2
1
1
1
0
0
0
Timer Reload Value
Timer Load Register
TLR0:$FFFF8E Write Only
TLR1:$FFFF8A Write Only
TLR2:$FFFF86 Write Only
Reset = $XXXXXX
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
Value Compared to Counter Value
Timer Compare Register
TCPR0:$FFFF8D Read/Write
TCPR1:$FFFF89 Read/Write
TCPR2:$FFFF85 Read/Write
Reset = $XXXXXX
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
Timer Count Value
Timer Count Register
TCR0:$FFFF8C Read Only
TCR1:$FFFF88 Read Only
TCR2:$FFFF84 Read Only
Reset = $000000
Figure D-32. Timer Load, Compare and Count Registers
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
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Programming Sheets
Date:
Application:
Programmer:
Sheet 1 of 4
Port B (HDI08)
GPIO
15 14 13 12 11 10
9
8
DR8
7
DR7
6
DR6
5
DR5
4
DR4
3
DR3
2
DR2
1
DR1
0
DR0
Host Data
Direction Register
(HDDR)
DR15 DR14 DR13 DR12 DR11 DR10 DR9
X:$FFFFC8
Read/Write
Reset = $0
DRx = 1
→
PBx is Output
DRx = 0
→
PBx is Input
15 14 13 12 11 10
9
D9
8
D8
7
D7
6
D6
5
D5
4
D4
3
D3
2
D2
1
D1
0
D0
Host Data
Register
(HDR)
D15
D14
D13
D12
D11
D10
X:$FFFFC9
Read/Write
Reset = Undefined
Dx holds value of corresponding HDI08 GPIO pin.
Function depends on HDDR.
See the HDI08 HPCR Register (Figure D-8) for additional Port B GPIO control bits.
Figure D-33. GPIO Port B
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
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Programming Sheets
Date:
Application:
Programmer:
Sheet 2 of 4
Port C (ESAI)
GPIO
3
2
1
0
23
11
9
8
PC8
7
PC7
6
PC6
5
PC5
4
PC4
10
PC10
PC11
PC9
Port C Control Register
(PCRC)
PC2
PC3
PC1
PC0
*
0
X:$FFFFBF
Read/Write
Reset = $0
= Reserved, Program as 0
*
23
11
10
PDC10
9
8
7
6
5
4
3
2
1
0
Port C Direction Register
(PRRC)
PDC9 PDC8 PDC7 PDC6 PDC5 PDC4
PDC3 PDC2
PDC11
PDC0
PDC1
*
0
X:$FFFFBE
Read/Write
Reset = $0
= Reserved, Program as 0
*
PCn = 0 & PDCn = 0 -> Port pin PCn disconnected
PCn = 1 & PDCn = 0 -> Port pin PCn configured as input
PCn = 0 & PDCn = 1 -> Port pin PCn configured as output
PCn = 1 & PDCn = 1 -> Port pin configured as ESAI
5
23 11
9
8
7
6
4
3
10
2
1
0
PD0
Port C GPIO Data Register
(PDRC)
PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3
PD2
PD1
*
0
X:$FFFFBD
Read/Write
Reset = undefined
= Reserved, Program as 0
*
If port pin n is GPIO input, then PDn reflects the value on port pin n
if port pin n is GPIO output, then value written to PDn is reflected on port pin n
Figure D-34. GPIO Port C
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
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Programming Sheets
Date:
Application:
Programmer:
Sheet 3 of 4
Port D (DAX)
GPIO
23
6
5
4
3
2
1
0
Port D Control Register
PC1 PC0
(PCRD)
X:$FFFFD7
Read/Write
Reset = $0
* *
0 0
* * *
0 0 0
*
0
= Reserved, Program as 0
*
23
6
5
4
3
2
1
0
Port D Direction Register
(PRRD)
PDC1 PDC0
* *
0
* * *
0
*
0
0
0
0
X:$FFFFD6
Read/Write
Reset = $0
= Reserved, Program as 0
*
PCn = 0 & PDCn = 0 -> Port pin PDn disconnected
PCn = 1 & PDCn = 0 -> Port pin PDn configured as input
PCn = 0 & PDCn = 1 -> Port pin PDn configured as output
PCn = 1 & PDCn = 1 -> Port pin configured as DAX
23
6
5
4
3
2
1
0
PD1 PD0
Port D GPIO Data Register
(PDRD)
* *
0 0
* *
0 0
* *
0 0
X:$FFFFD5
Read/Write
Reset = $0
= Reserved, Program as 0
*
If port pin n is GPIO input, then PDn reflects the value on port pin n
if port pin n is GPIO output, then value written to PDn is reflected on port pin n
Figure D-35. GPIO Port D
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Programming Sheets
Date:
Application:
Programmer:
Sheet 4 of 4
Port E (ESAI_1)
GPIO
3
2
1
0
23 11
9
8
7
6
5
4
10
Port E Control Register
(PCRE)
PC6
PC4
PC10 PC9
PC7
PC11
PC8
PC1
PC3
*
0
*
0
*
0
PC0
Y:$FFFF9F
Read/Write
Reset = $0
= Reserved, Program as 0
*
23
11
10
9
8
7
6
5
4
3
2
1
0
Port E Direction Register
(PRRE)
PDC4
PDC3
PDC11 PDC10 PDC9 PDC8
PDC6
PDC7
PDC0
*
0
*
0
*
0
PDC1
Y:$FFFF9E
Read/Write
Reset = $0
= Reserved, Program as 0
*
PCn = 0 & PDCn = 0 -> Port pin PEn disconnected
PCn = 1 & PDCn = 0 -> Port pin PEn configured as input
PCn = 0 & PDCn = 1 -> Port pin PEn configured as output
PCn = 1 & PDCn = 1 -> Port pin configured as ESAI_1
2
5
23 11
9
8
7
6
4
3
10
1
0
PD0
Port E GPIO Data Register
(PDRE)
PD4 PD3
PD11 PD10 PD9 PD8
PD6
PD7
PD1
*
*
0
*
0
0
Y:$FFFF9D
Read/Write
Reset = undefined
= Reserved, Program as 0
*
If port pin n is GPIO input, then PDn reflects the value on port pin n
if port pin n is GPIO output, then value written to PDn is reflected on port pin n
Figure D-36. GPIO Port E
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
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Programming Sheets
NOTES
DSP56366 24-Bit Digital Signal Processor User Manual, Rev. 4
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Index
Numerics
Transmit Register Empty Interrupt Handling
10
A
adder
DAX Audio Data register Empty (XADE) status
flag 8
B
bus
buses
C
DAX Transmit Underrun error (XAUR) status flag
8
CPHA and CPOL (HCKR Clock Phase and Polar-
ity Controls) 7
D
DSP56366 24-Bit Digital Signal Processor, Rev. 4
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HCSR
E
2
2
HI C (HCSR Serial Host Interface I C/SPI Selec-
Host
HRIE0-HRIE1 (HCSR Receive Interrupt Enable)
14
F
G
I
2
H
2
HA1, HA3-HA6 (HSAR I C Slave Address) 7
DSP56366 24-Bit Digital Signal Processor, Rev. 4
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2
2
I C Mode 1
Internal Exception Priorities
P
Interrupt Vectors
J
L
Programming Model
M
memory
O
DSP56366 24-Bit Digital Signal Processor, Rev. 4
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R
reserved bits
in TCSR register
RESET 8
S
HCSR
HCKR
HCSR
SRAM
2
HREQ
HSAR
2
T
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bits 0-20—Prescaler Load Value bits
(PL0-PL20) 5
bits 21-22—Prescaler Source bits (PL0-PL20)
5
bit 2—Timer Compare Interrupt Enable bit
(TCIE) 7
V
timer
X
timer mode
Y
Timer module
bits 0-20—Prescaler Counter Value bits
(PC0-PC20) 6
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