CY8C20x36/46/66, CY8C20396
CapSense™ Applications
Features
■ 1.71V to 5.5V Operating Range
■ Versatile Analog Mux
❐ Common Internal Analog Bus
❐ Simultaneous Connection of IO
❐ High PSRR Comparator
❐ Low Dropout Voltage Regulator for All Analog Resources
■ Low Power CapSense™ Block
❐ Configurable Capacitive Sensing Elements
❐ Supports Combination of CapSense Buttons, Sliders,
Touchpads, Touch Screens, and Proximity Sensor
■ Additional System Resources
❐ I C™ Slave:
■ Powerful Harvard Architecture Processor
❐ M8C Processor Speeds Running to 24 MHz
❐ Low Power at High Speed
2
• Selectable to 50 kHz, 100 kHz, or 400 kHz
• No Clock Stretching Required (under most conditions)
❐ Interrupt Controller
• Implementation During Sleep Modes with Less Than
100 µA
• Hardware Address Validation
❐ SPI™ Master and Slave: Configurable 46.9 kHz - 12 MHz
❐ Three 16-Bit Timers
❐ Watchdog and Sleep Timers
❐ Internal Voltage Reference
❐ Integrated Supervisory Circuit
❐ Temperature Range: -40°C to +85°C
■ Flexible On-Chip Memory
❐ Three Program/Data Storage Size Options:
• CY8C20x36: 8K Flash / 1K SRAM
• CY8C20x46: 16K Flash / 2K SRAM
• CY8C20x66: 32K Flash / 2K SRAM
❐ 50,000 Flash Erase/Write Cycles
❐ Partial Flash Updates
■ Complete Development Tools
❐ Free Development Tool (PSoC Designer™)
❐ Full Featured, In-Circuit Emulator and Programmer
❐ Full Speed Emulation
❐ Flexible Protection Modes
❐ In-System Serial Programming (ISSP)
■ Full-Speed USB
❐ Available on CY8C20396 and CY8C20666 Only
❐ 12 Mbps USB 2.0 Compliant
❐ Eight Unidirectional Endpoints
❐ One Bidirectional Control Endpoint
❐ Dedicated 512 Byte Buffer
❐ Complex Breakpoint Structure
❐ 128K Trace Memory
■ Package Options
❐ CY8C20x36:
• 16-Pin 3 x 3 x 0.6 mm QFN
• 24-Pin 4 x 4 x 0.6 mm QFN
• 32-Pin 5 x 5 x 0.6 mm QFN
❐ CY8C20x46:
• 16-Pin 3 x 3 x 0.6 mm QFN
• 24-Pin 4 x 4 x 0.6 mm QFN
• 32-Pin 5 x 5 x 0.6 mm QFN
❐ CY8C20396: 24-Pin 4 x 4 x 0.6 mm QFN
❐ CY8C20x66:
❐ Internally Regulated at 3.3V
■ Precision, Programmable Clocking
❐ Internal Main Oscillator: 6/12/24 MHz ± 5%
❐ Internal Low Speed Oscillator at 32 kHz for Watchdog and
Sleep Timers
❐ Precision 32 kHz Oscillator for Optional External Crystal
(CY8C20x46/66 only)
❐ 0.25% Accuracy for USB with No External Components
(CY8C20396 and CY8C20666 only)
• 32-Pin 5 x 5 x 0.6 mm QFN
• 48-Pin 7 x 7 x 1.0 mm QFN (with USB)
• 48-Pin SSOP
■ Programmable Pin Configurations
❐ Up to 36 GPIO (Depending on Package)
❐ Dual Mode GPIO: All GPIO Support Digital IO and Analog
Input
❐ 25 mA Sink Current on All GPIO
❐ Pull up, High Z, Open Drain Modes on All GPIO
❐ CMOS Drive Mode(5 mA Source Current) on Ports 0 and 1:
• 20 mA (at 3.0V) Total Source Current on Port 0
• 20 mA (at 3.0V) Total Source Current on Port 1
❐ Selectable, Regulated Digital IO on Port 1
❐ Configurable Input Threshold on Port 1
❐ Hot Swap Capability on all Port 1 GPIO
Cypress Semiconductor Corporation
Document Number: 001-12696 Rev. *D
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised March 17, 2009
Download from Www.Somanuals.com. All Manuals Search And Download.
CY8C20x36/46/66, CY8C20396
®
Figure 1. Analog System Block Diagram
PSoC Functional Overview
The PSoC family consists of on-chip Controller devices. These
devices are designed to replace multiple traditional MCU-based
components with one, low cost single-chip programmable
component. A PSoC device includes configurable analog and
digital blocks, and programmable interconnect. This architecture
allows the user to create customized peripheral configurations,
to match the requirements of each individual application.
Additionally, a fast CPU, Flash program memory, SRAM data
memory, and configurable IO are included in a range of
convenient pinouts.
IDAC
Vr
The architecture for this device family, as shown in the Block
Diagram on page 2, is comprised of three main areas: the Core,
the CapSense Analog System, and the System Resources
(including a full speed USB port). A common, versatile bus allows
connection between IO and the analog system. Each
Reference
Buffer
Cinternal
CY8C20x36/46/66, CY8C20396 PSoC device includes
a
dedicated CapSense block that provides sensing and scanning
control circuitry for capacitive sensing applications. Depending
on the PSoC package, up to 36 general purpose IO (GPIO) are
also included. The GPIO provides access to the MCU and
analog mux.
Comparator
Mux
Mux
Refs
PSoC Core
CapSenseCounters
CSCLK
The PSoC Core is a powerful engine that supports a rich
instruction set. It encompasses SRAM for data storage, an
interrupt controller, sleep and watchdog timers, and IMO
(internal main oscillator) and ILO (internal low speed oscillator).
The CPU core, called the M8C, is a powerful processor with
speeds up to 24 MHz. The M8C is a four-MIPS, 8-bit Harvard
architecture microprocessor.
CapSense
ClockSelect
IMO
Oscillator
System Resources provide additional capability, such as
configurable USB and I2C slave/SPI master-slave
communication interface, three 16-bit programmable timers, and
various system resets supported by the M8C.
Analog Multiplexer System
The Analog Mux Bus can connect to every GPIO pin. Pins are
connected to the bus individually or in any combination. The bus
also connects to the analog system for analysis with the
CapSense block comparator.
The Analog System is composed of the CapSense PSoC block
and an internal 1.2V analog reference, which together support
capacitive sensing of up to 36 inputs.
Switch control logic enables selected pins to precharge
continuously under hardware control. This enables capacitive
measurement for applications such as touch sensing. Other
multiplexer applications include:
CapSense Analog System
The Analog System contains the capacitive sensing hardware.
Several hardware algorithms are supported. This hardware
performs capacitive sensing and scanning without requiring
external components. Capacitive sensing is configurable on
each GPIO pin. Scanning of enabled CapSense pins are
completed quickly and easily across multiple ports.
■ Complex capacitive sensing interfaces, such as sliders and
touchpads.
■ Chip-wide mux that allows analog input from any IO pin.
■ Crosspoint connection between any IO pin combinations.
When designing capacitive sensing applications, refer to the
latest signal-to-noise signal level requirements Application
Documentation >> Application Notes. In general, and unless
otherwise noted in the relevant Application Notes, the minimum
signal-to-noise ratio (SNR) for CapSense applications is 5:1.
Document Number: 001-12696 Rev. *D
Page 3 of 34
Download from Www.Somanuals.com. All Manuals Search And Download.
CY8C20x36/46/66, CY8C20396
Additional System Resources
Getting Started
System Resources, some of which are listed in the previous
sections, provide additional capability useful to complete
systems. Additional resources include low voltage detection and
power on reset. The merits of each system resource are listed
here:
The quickest way to understand PSoC silicon is to read this data
sheet and then use the PSoC Designer Integrated Development
Environment (IDE). This data sheet is an overview of the PSoC
integrated circuit and presents specific pin, register, and
electrical specifications.
■ The I2C slave/SPI master-slave module provides 50/100/400
kHz communication over two wires. SPI communication over
three or four wires runs at speeds of 46.9 kHz to 3 MHz (lower
for a slower system clock).
For in depth information, along with detailed programming
details, see the PSoC Programmable System-on-Chip™
Technical Reference Manual for CY8C28xxx PSoC devices.
®
■ The I2C hardware address recognition feature reduces the
already low power consumption by eliminating the need for
CPU intervention until a packet addressed to the target device
is received.
Application Notes
Application notes are an excellent introduction to the wide variety
of possible PSoC designs. They are located here:
www.cypress.com/psoc. Select Application Notes under the
Documentation tab.
■ Low Voltage Detection (LVD) interrupts can signal the
application of falling voltage levels, while the advanced POR
(Power-On-Reset) circuit eliminates the need for a system
supervisor.
■ An internal reference provides an absolute reference for capac-
itive sensing.
Development Kits
PSoC Development Kits are available online from Cypress at
www.cypress.com/shop and through a growing number of
regional and global distributors, which include Arrow, Avnet, Digi-
Key, Farnell, Future Electronics, and Newark.
■ The 5.5V maximum input, 1.8/2.5/3V-selectable output, low-
dropout regulator (LDO) provides regulation for IOs. A register-
controlled bypass mode allows the user to disable the LDO.
■ Standard Cypress PSoC IDE tools are available for debugging
the CY8C20x36/46/66, CY8C20396 family of parts. However,
the additional trace length and a minimal ground plane in the
Flex-Pod can create noise problems that make it difficult to
debug a Power PSoC design. A custom bonded On-Chip
Debug (OCD) device is available in an 48-pin QFN package.
The OCD device is recommended for debugging designs that
have high current and/or high analog accuracy requirements.
The QFN package is compact and is connected to the ICE
through a high density connector.
Training
training covers a wide variety of topics and skill levels to assist
you in your designs.
CYPros Consultants
Solutions Library
Visit our growing library of solution focused designs at
www.cypress.com/solutions. Here you can find various
application designs that include firmware and hardware design
files that enable you to complete your designs quickly.
Technical Support
For assistance with technical issues, search KnowledgeBase
find an answer to your question, call technical support at 1-800-
541-4736.
Document Number: 001-12696 Rev. *D
Page 4 of 34
Download from Www.Somanuals.com. All Manuals Search And Download.
CY8C20x36/46/66, CY8C20396
Development Tools
PSoC Designer™ is a Microsoft® Windows-based, integrated
development environment for the Programmable System-on-
Chip (PSoC) devices. The PSoC Designer IDE and application
runs on Windows XP and Windows Vista.
Code Generation Tools
PSoC Designer supports multiple third-party C compilers and
assemblers. The code generation tools work seamlessly within
the PSoC Designer interface and have been tested with a full
range of debugging tools. The choice is yours.
This system provides design database management by project,
an integrated debugger with In-Circuit Emulator, in-system
programming support, and built-in support for third-party assem-
blers and C compilers.
Assemblers. The assemblers allow assembly code to be
merged seamlessly with C code. Link libraries automatically use
absolute addressing or are compiled in relative mode, and linked
with other software modules to get absolute addressing.
PSoC Designer also supports C language compilers developed
specifically for the devices in the PSoC family.
C Language Compilers. C language compilers are available
that support the PSoC family of devices. The products allow you
to create complete C programs for the PSoC family devices.
PSoC Designer Software Subsystems
System-Level View
The system-level view is a drag-and-drop visual embedded
system design environment based on PSoC Express. In this
view you solve design problems the same way you might think
about the system. Select input and output devices based upon
system requirements. Add a communication interface and define
the interface to the system (registers). Define when and how an
output device changes state based upon any/all other system
devices. Based upon the design, PSoC Designer automatically
selects one or more PSoC devices that match your system
requirements.
The optimizing C compilers provide all the features of C tailored
to the PSoC architecture. They come complete with embedded
libraries providing port and bus operations, standard keypad and
display support, and extended math functionality.
Debugger
PSoC Designer has a debug environment that provides
hardware in-circuit emulation, allowing you to test the program in
a physical system while providing an internal view of the PSoC
device. Debugger commands allow the designer to read and
program and read and write data memory, read and write IO
registers, read and write CPU registers, set and clear break-
points, and provide program run, halt, and step control. The
debugger also allows the designer to create a trace buffer of
registers and memory locations of interest.
PSoC Designer generates all embedded code, then compiles
and links it into a programming file for a specific PSoC device.
Chip-Level View
The chip-level view is a more traditional integrated development
environment (IDE) based on PSoC Designer 4.x. You choose a
base device to work with and then select different onboard
analog and digital components called user modules that use the
PSoC blocks. Examples of user modules are ADCs, DACs,
Amplifiers, and Filters. You configure the user modules for your
chosen application and connect them to each other and to the
proper pins. Then you generate your project. This prepopulates
your project with APIs and libraries that you can use to program
your application.
Online Help System
The online help system displays online, context-sensitive help
for the user. Designed for procedural and quick reference, each
functional subsystem has its own context-sensitive help. This
system also provides tutorials and links to FAQs and an Online
Support Forum to aid the designer in getting started.
In-Circuit Emulator
A low cost, high functionality ICE (In-Circuit Emulator) is
available for development support. This hardware has the
capability to program single devices.
The tool also supports easy development of multiple configura-
tions and dynamic reconfiguration. Dynamic reconfiguration
allows for changing configurations at run time.
The emulator consists of a base unit that connects to the PC by
way of a USB port. The base unit is universal and operates with
all PSoC devices. Emulation pods for each device family are
available separately. The emulation pod takes the place of the
PSoC device in the target board and performs full speed (24
MHz) operation.
Hybrid Designs
You can begin in the system-level view, allow it to choose and
configure your user modules, routing, and generate code, then
switch to the chip-level view to gain complete control over on-
chip resources. All views of the project share common code
editor, builder, and common debug, emulation, and programming
tools.
Document Number: 001-12696 Rev. *D
Page 5 of 34
Download from Www.Somanuals.com. All Manuals Search And Download.
CY8C20x36/46/66, CY8C20396
Designing with PSoC Designer
The development process for the PSoC device differs from that
of a traditional fixed function microprocessor. The configurable
analog and digital hardware blocks give the PSoC architecture a
unique flexibility that pays dividends in managing specification
change during development and by lowering inventory costs.
These configurable resources, called PSoC Blocks, have the
ability to implement a wide variety of user-selectable functions.
Organize and Connect
You build signal chains at the chip level by interconnecting user
modules to each other and the IO pins, or connect system-level
inputs, outputs, and communication interfaces to each other with
valuator functions.
In the system-level view selecting a potentiometer driver to
control a variable speed fan driver and setting up the valuators
to control the fan speed based on input from the pot selects,
places, routes, and configures a programmable gain amplifier
(PGA) to buffer the input from the potentiometer, an analog-to-
digital converter (ADC) to convert the potentiometer’s output to
a digital signal, and a PWM to control the fan.
The PSoC development process can be summarized in the
following four steps:
1. Select Components
2. Configure Components
3. Organize and Connect
4. Generate, Verify, and Debug
In the chip-level view, you perform the selection, configuration,
and routing so that you have complete control over the use of all
on-chip resources.
Select Components
Both the system-level and chip-level views provide a library of
pre-built, pre-tested hardware peripheral components. In the
system-level view these components are called “drivers” and
correspond to inputs (a thermistor, for example), outputs (a
brushless DC fan, for example), communication interfaces (I C-
bus, for example), and the logic to control how they interact with
one another (called valuators).
Generate, Verify, and Debug
When you are ready to test the hardware configuration or move
on to developing code for the project, you perform the “Generate
Configuration Files” step. This causes PSoC Designer to
generate source code that automatically configures the device to
your specification and provides the software for the system.
2
Both system-level and chip-level designs generate software
based on your design. The chip-level design provides application
programming interfaces (APIs) with high-level functions to
control and respond to hardware events at run time and interrupt
service routines that you can adapt as needed. The system-level
design also generates a C main() program that completely
controls the chosen application and contains placeholders for
custom code at strategic positions allowing you to further refine
the software without disrupting the generated code.
In the chip-level view the components are called “user modules.”
User modules make selecting and implementing peripheral
devices simple, and come in analog, digital, and programmable
system-on-chip varieties.
Configure Components
Each of the components you select establishes the basic register
settings that implement the selected function. They also provide
parameters and properties that allow you to tailor their precise
configuration to your particular application. For example, a Pulse
Width Modulator (PWM) User Module configures one or more
digital PSoC blocks, one for each 8 bits of resolution. The user
module parameters permit you to establish the pulse width and
duty cycle. Configure the parameters and properties to corre-
spond to your chosen application. Enter values directly or by
selecting values from drop-down menus.
A complete code development environment allows you to
develop and customize your applications in C, assembly
language, or both.
The last step in the development process takes place inside
PSoC Designer’s Debugger (access by clicking the Connect
icon). PSoC Designer downloads the HEX image to the In-Circuit
Emulator (ICE) where it runs at full speed. PSoC Designer
debugging capabilities rival those of systems costing many times
more. In addition to traditional single-step, run-to-breakpoint and
watch-variable features, the debug interface provides a large
trace buffer and allows you to define complex breakpoint events
that include monitoring address and data bus values, memory
locations and external signals.
Both the system-level drivers and chip-level user modules are
documented in data sheets that are viewed directly in PSoC
Designer. These data sheets explain the internal operation of the
component and provide performance specifications. Each data
sheet describes the use of each user module parameter or driver
property, and other information you may need to successfully
implement your design.
Document Number: 001-12696 Rev. *D
Page 6 of 34
Download from Www.Somanuals.com. All Manuals Search And Download.
CY8C20x36/46/66, CY8C20396
Document Conventions
Acronyms Used
Units of Measure
The following table lists the acronyms that are used in this
document.
A units of measure table is located in the Electrical Specifications
section. Table 9 on page 15 lists all the abbreviations used to
measure the PSoC devices.
Table 1. Acronyms
Numeric Naming
Acronym
AC
Description
alternating current
Hexadecimal numbers are represented with all letters in
uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or
‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’
prefix, the C coding convention. Binary numbers have an
appended lowercase ‘b’ (for example, 01010100b’ or
‘01000011b’). Numbers not indicated by an ‘h’, ‘b’, or 0x are
decimal.
API
application programming interface
central processing unit
direct current
CPU
DC
FSR
GPIO
GUI
full scale range
general purpose IO
graphical user interface
in-circuit emulator
ICE
ILO
internal low speed oscillator
internal main oscillator
input/output
IMO
IO
LSb
least-significant bit
LVD
low voltage detect
MSb
POR
PPOR
PSoC®
SLIMO
SRAM
most-significant bit
power on reset
precision power on reset
Programmable System-on-Chip™
slow IMO
static random access memory
Document Number: 001-12696 Rev. *D
Page 7 of 34
Download from Www.Somanuals.com. All Manuals Search And Download.
CY8C20x36/46/66, CY8C20396
Pinouts
The CY8C20x36/46/66, CY8C20396 PSoC device is available in a variety of packages which are listed and illustrated in the following
tables. Every port pin (labeled with a “P”) is capable of Digital IO and connection to the common analog bus. However, Vss, Vdd, and
XRES are not capable of Digital IO.
16-Pin QFN
[2]
Table 2. Pin Definitions - CY8C20236, CY8C20246 PSoC Device
Type
Figure 2. CY8C20236, CY8C20246 PSoC Device
Pin
No.
Name
Description
Digital Analog
1
2
3
4
5
6
IO
I
I
I
I
I
I
P2[5] Crystal output (XOut)
P2[3] Crystal input (XIn)
P1[7] I2C SCL, SPI SS
P1[5] I2C SDA, SPI MISO
P1[3] SPI CLK
IO
AI, XOut, P2[5]
AI, XIn, P2[3]
1
2
P0[4], AI
IOHR
IOHR
IOHR
IOHR
12
11
10
QFN
(Top View)
XRES
P1[4], EXTCLK, AI
P1[2], AI
AI, I2C SCL, SPI SS, P1[7]
AI, I2C SDA, SPI MISO, P1[5]
3
4
9
P1[1] ISSP CLK , I2C SCL, SPI
MOSI
7
8
Power
Vss Ground connection
IOHR
I
P1[0] ISSP DATA , I2C SDA, SPI
CLK
9
IOHR
IOHR
I
I
P1[2]
10
P1[4] Optional external clock
(EXTCLK)
11
Input
XRES Active high external reset with
internal pull down
12
13
14
15
16
IOH
Power
I
P0[4]
Vdd Supply voltage
P0[7]
IOH
IOH
IOH
I
I
I
P0[3] Integrating input
P0[1] Integrating input
LEGEND A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output.
Notes
1. These are the ISSP pins, which are not High Z at POR (Power On Reset).
2. During power up or reset event, device P1[1] and P1[0] may disturb the I2C bus. Use alternate pins if you encounter any issues.
Document Number: 001-12696 Rev. *D
Page 8 of 34
Download from Www.Somanuals.com. All Manuals Search And Download.
CY8C20x36/46/66, CY8C20396
24-Pin QFN
Table 3. Pin Definitions - CY8C20336, CY8C20346
Type
Pin
Figure 3. CY8C20336, CY8C20346 PSoC Device
Name
Description
No.
Digital Analog
1
2
3
4
5
6
7
IO
I
I
I
I
I
I
I
P2[5]
P2[3]
P2[1]
P1[7]
P1[5]
P1[3]
P1[1]
Crystal output (XOut)
Crystal input (XIn)
IO
18
17
16
15
AI, XOut, P2[5]
AI, XIn, P2[3]
1
2
3
4
5
6
P0[4], AI
P0[2], AI
P0[0], AI
P2[0], AI
XRES
IO
IOHR
IOHR
IOHR
IOHR
I2C SCL, SPI SS
I2C SDA, SPI MISO
SPI CLK
MOSI
AI, P2[1]
QFN
(Top View)
AI, I2C SCL, SPI SS, P1[7]
AI, I2C SDA, SPI MISO, P1[5]
AI, SPI CLK, P1[3]
14
13
P1[6], AI
8
NC
No connection
9
Power
Vss
P1[0]
Ground connection
CLK
10
IOHR
I
11
12
IOHR
IOHR
I
I
P1[2]
P1[4]
Optional external clock input
(EXTCLK)
13
14
IOHR
I
P1[6]
Input
XRES Active high external reset with
internal pull down
15
16
17
18
19
20
21
22
23
24
CP
IO
I
I
I
I
I
P2[0]
P0[0]
P0[2]
P0[4]
P0[6]
IOH
IOH
IOH
IOH
Power
Power
Vdd
Supply voltage
IOH
IOH
IOH
IOH
I
I
I
I
P0[7]
P0[5]
P0[3]
P0[1]
Vss
Integrating input
Integrating input
Center pad must be connected
to ground
LEGEND A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output.
Note
3. The center pad (CP) on the QFN package must be connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not connected to ground, it
must be electrically floated and not connected to any other signal.
Document Number: 001-12696 Rev. *D
Page 9 of 34
Download from Www.Somanuals.com. All Manuals Search And Download.
CY8C20x36/46/66, CY8C20396
24-Pin QFN with USB Pinout
Table 4. Pin Definitions - CY8C20396 PSoC Device
Type
Pin No.
Name
Description
Figure 4. CY8C20396 PSoC Device
Digital Analog
1
2
IO
I
I
I
I
I
I
I
P2[5]
P2[3]
P2[1]
P1[7]
P1[5]
P1[3]
P1[1]
VSS
D+
IO
3
IO
18
17
16
15
P2[5]
P2[3]
1
2
P0[2]
4
IOHR
IOHR
IOHR
IOHR
I2C SCL, SPI SS
P0[0]
XRES
P2[1]
3
4
5
6
QFN
(Top View)
5
I2C SDA, SPI MISO
SPI CLK
I2C SCL, SPI SS, P1[7]
I2C SDA, SPI MISO, P1[5]
SPI CLK, P1[3]
P1[6]
P1[4], EXTCLK
P1[2]
6
14
13
7
ISSP CLK, I2C SCL, SPI MOSI
Ground
8
Power
9
IO
IO
I
I
USB D+
10
11
12
13
14
D-
USB D-
Power
VDD
P1[0]
P1[2]
P1[4]
Supply
IOHR
IOHR
IOHR
I
I
I
ISSP DATA, I2C SDA
Optional external clock input
(EXTCLK)
15
16
IOHR
I
P1[6]
RESET INPUT
XRES
Active high external reset with
internal pull down
17
18
19
20
21
22
23
24
CP
IOH
IOH
IOH
IOH
IOH
IOH
IOH
IOH
I
I
I
I
I
I
I
I
P0[0]
P0[2]
P0[4]
P0[6]
P0[7]
P0[5]
P0[3]
P0[1]
VSS
Integrating input
Integrating input
Power
Thermal pad must be
connected to Ground
LEGEND I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output
Document Number: 001-12696 Rev. *D
Page 10 of 34
Download from Www.Somanuals.com. All Manuals Search And Download.
CY8C20x36/46/66, CY8C20396
32-Pin QFN
Table 5. Pin Definitions - CY8C20436/46/66 PSoC Device
Type
Pin
Figure 5. CY8C20436/46/66 PSoC Device
Name
Description
No.
Digital Analog
1
IOH
IO
I
I
I
I
I
I
I
I
I
I
I
P0[1]
P2[7]
P2[5]
P2[3]
P2[1]
P3[3]
P3[1]
P1[7]
P1[5]
P1[3]
P1[1]
Vss
Integrating input
2
3
IO
Crystal output (XOut)
Crystal input (XIn)
AI, P0[1]
AI, P2[7]
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
P0[0], AI
P2[6], AI
P2[4], AI
P2[2], AI
P2[0], AI
P3[2], AI
P3[0], AI
XRES
4
IO
AI, XOut, P2[5]
AI, XIn, P2[3]
AI, P2[1]
5
IO
QFN
(Top View)
6
IO
7
IO
AI, P3[3]
AI, P3[1]
AI, I2C SCL, SPI SS, P1[7]
8
IOHR
IOHR
IOHR
IOHR
I2C SCL, SPI SS
I2C SDA, SPI MISO
SPI CLK.
9
10
11
12
13
14
15
Power
Ground connection.
IOHR
IOHR
IOHR
I
I
I
P1[0]
P1[2]
P1[4]
Optional external clock input
(EXTCLK)
16
17
IOHR
I
P1[6]
Input
XRES Active high external reset with
internal pull down
18
IO
I
P3[0]
19
20
21
22
23
24
25
26
27
28
29
30
31
32
CP
IO
IO
I
I
I
I
I
I
I
I
I
P3[2]
P2[0]
P2[2]
P2[4]
P2[6]
P0[0]
P0[2]
P0[4]
P0[6]
IO
IO
IO
IOH
IOH
IOH
IOH
Power
Vdd
Supply voltage
IOH
IOH
IOH
I
I
I
P0[7]
P0[5]
P0[3]
Vss
Integrating input
Power
Power
Ground connection
Vss
Center pad must be connected to
ground
LEGEND A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output.
Document Number: 001-12696 Rev. *D
Page 11 of 34
Download from Www.Somanuals.com. All Manuals Search And Download.
CY8C20x36/46/66, CY8C20396
48-Pin QFN
[2, 3]
Table 6. Pin Definitions - CY8C20666 PSoC Device
Figure 6. CY8C20666 PSoC Device
Pin
No.
Name
Description
1
NC
No connection
NC
AI, P2[7]
P2[6],AI
P2[4],AI
36
35
34
33
32
31
1
2
2
IO
IO
I
I
I
I
I
I
I
I
I
I
I
I
P2[7]
P2[5]
P2[3]
P2[1]
P4[3]
P4[1]
P3[7]
P3[5]
P3[3]
P3[1]
P1[7]
P1[5]
NC
3
Crystal output (XOut)
Crystal input (XIn)
AI, XOut, P2[5]
3
4
5
6
P2[2],AI
P2[0],AI
P4[2],AI
P4[0],AI
4
IO
AI, XIn , P2[3]
AI, P2[1]
5
IO
AI, P4[3]
QFN
(Top View)
6
IO
AI, P4[1]
AI, P3[7]
30
29
28
27
P3[6],AI
P3[4], AI
7
8
9
10
7
IO
AI, P3[5]
AI, P3[3]
AI, P3[1]
P3[2],AI
8
IO
], AI
P3[0
9
IO
XRES
26
25
11
12
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
IO
AI, I2C SCL, SPI SS, P1[7]
P1[6], AI
IO
IOHR
IOHR
I2C SCL, SPI SS
I2C SDA, SPI MISO
No connection
No connection
SPI CLK
NC
IOHR
IOHR
I
I
P1[3]
P1[1]
Vss
Power
Ground connection
IO
IO
D+
D-
Power
Vdd
Supply voltage
IOHR
IOHR
IOHR
I
I
I
P1[0]
P1[2]
P1[4]
Optional external clock input
(EXTCLK)
25
26
IOHR
I
P1[6]
Input
XRES Active high external reset with
internal pull down
27
28
29
IO
IO
IO
I
I
I
P3[0]
P3[2]
P3[4]
Pin
No.
Name
Description
30
31
32
33
34
35
36
37
38
39
IO
IO
I
I
I
I
I
I
I
I
I
I
P3[6]
P4[0]
P4[2]
P2[0]
P2[2]
P2[4]
P2[6]
P0[0]
P0[2]
P0[4]
40
41
42
43
44
45
46
47
48
CP
IOH
I
P0[6]
Vdd
Power
Supply voltage
IO
NC
No connection
No connection
IO
NC
IO
IOH
I
I
I
P0[7]
P0[5]
P0[3]
Vss
IO
IOH
IOH
IO
Integrating input
IOH
IOH
IOH
Power
Ground connection
IOH
I
P0[1]
Vss
Power
Center pad must be connected to ground
LEGEND A = Analog, I = Input, O = Output, NC = No Connection H = 5 mA High Output Drive, R = Regulated Output.
Document Number: 001-12696 Rev. *D
Page 12 of 34
Download from Www.Somanuals.com. All Manuals Search And Download.
CY8C20x36/46/66, CY8C20396
48-Pin SSOP
Table 7. Pin Definitions - CY8C20566 PSoC Device
Figure 7. CY8C20566 PSoC Device
Name
Description
P0[7]
P0[5]
P0[3]
P0[1]
P2[7]
1
2
3
4
5
6
VDD
P0[6]
P0[4]
P0[2]
P0[0]
P2[6]
P2[4]
P2[2]
P2[0]
P3[6]
P3[4]
P3[2]
P3[0]
XRES
NC
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
1
IOH
IOH
IOH
IOH
IO
IO
IO
IO
IO
IO
IO
IO
IO
P0[7]
P0[5]
P0[3]
P0[1]
P2[7]
P2[5]
P2[3]
P2[1]
NC
2
3
P2[5]
P2[3]
4
7
8
9
5
P2[1]
NC
NC
P4[3]
P4[1]
NC
6
IO
XTAL Out
XTAL In
7
IO
10
11
12
13
14
8
IO
9
No connection
No connection
SSOP
10
NC
P3[7]
11 IO
12 IO
13
IO
IO
P4[3]
P4[1]
NC
P3[5] 15
P3[3] 16
P3[1] 17
NC
NC
33
32
31
30
29
28
27
26
25
No connection
NC
NC
P1[7]
18
19
20
NC
NC
NC
P1[6]
14 IO
15 IO
16 IO
17 IO
18
IO
IO
IO
IO
P3[7]
P3[5]
P3[3]
P3[1]
NC
P1[5] 21
P1[3]
P1[1] 23
22
P1[4]
P1[2]
No connection
VSS
24
P1[0]
19
NC
No connection
20 IOHR IO
21 IOHR IO
22 IOHR IO
23 IOHR IO
24
P1[7]
P1[5]
P1[3]
P1[1]
VSS
P1[0]
P1[2]
P1[4]
P1[6]
NC
I2C SCL, SPI SS
I2C SDA, SPI MISO
SPI CLK
Ground Pin
25 IOHR IO
26 IOHR IO
27 IOHR IO
28 IOHR IO
29
EXT CLK
No connection
No connection
No connection
No connection
30
NC
31
NC
32
NC
Name
Description
33
34
35
NC
NC
No connection
No connection
41
42
IO
IO
IO
IO
IO
IO
P2[2]
P2[4]
P2[6]
XRES Active high external reset with internal 43
pull down
36 IO
37 IO
38 IO
39 IO
40 IO
IO
IO
IO
IO
IO
P3[0]
P3[2]
P3[4]
P3[6]
P2[0]
44
45
46
47
48
IOH IO
IOH IO
IOH IO
IOH IO
Power
P0[0]
P0[2]
P0[4]
P0[6]
Vdd
Power Pin
LEGEND A = Analog, I = Input, O = Output, NC = No Connection, H = 5 mA High Output Drive, R = Regulated Output Option.
Document Number: 001-12696 Rev. *D
Page 13 of 34
Download from Www.Somanuals.com. All Manuals Search And Download.
CY8C20x36/46/66, CY8C20396
48-Pin QFN OCD
The 48-pin QFN part is for the CY8C20066 On-Chip Debug (OCD) PSoC device. Note that this part is only used for in-circuit
[4]
debugging.
[2, 3]
Table 8. Pin Definitions - CY8C20066 PSoC Device
Figure 8. CY8C20066 PSoC Device
Pin
No.
Name
Description
1
OCDOE
P2[7]
P2[5]
P2[3]
P2[1]
P4[3]
P4[1]
P3[7]
P3[5]
P3[3]
P3[1]
P1[7]
P1[5]
CCLK
HCLK
P1[3]
P1[1]
Vss
OCD mode direction pin
OCDO
2
IO
IO
I
I
I
I
I
I
I
I
I
I
I
I
P2[6], AI
P2[4], AI
36
35
34
33
32
31
1
2
E
A
I
, P2[7]
3
Crystal output (XOut)
Crystal input (XIn)
AI, XOut, P2[5]
3
4
5
6
P2[2], AI
P2[0], AI
P4[2], AI
P4[0], AI
4
IO
AI, XIn , P2[3]
AI, P2[1]
5
IO
6
IO
AI, P4[3]
QFN
(Top View)
AI, P4[1]
AI, P3[7]
30
29
28
27
P3[6], AI
P3[4], AI
7
8
9
10
7
IO
8
IO
AI, P3[5]
AI, P3[3]
P3[2], AI
P3[0], AI
9
IO
AI, P3[1]
XRES
26
25
11
12
10
11
12
13
14
15
16
17
18
19
20
21
22
23
IO
AI, I2C SCL, SPI SS, P1[7]
P1[6], AI
IO
IOHR
IOHR
I2C SCL, SPI SS
I2C SDA, SPI MISO
OCD CPU clock output
OCD high speed clock output
SPI CLK.
IOHR
IOHR
I
I
Power
Ground connection
IO
IO
D+
D-
Power
Vdd
Supply voltage
IOHR
IOHR
I
I
P1[0]
P1[2]
Pin
No.
Name
Description
24
IOHR
IOHR
I
I
P1[4]
Optional external clock input
(EXTCLK)
37
IOH
I
P0[0]
25
26
P1[6]
38
39
IOH
IOH
I
I
P0[2]
P0[4]
Input
XRES
Active high external reset with
internal pull down
27
28
29
30
31
32
33
34
35
36
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
I
I
I
I
I
I
I
I
I
I
P3[0]
P3[2]
P3[4]
P3[6]
P4[0]
P4[2]
P2[0]
P2[2]
P2[4]
P2[6]
40
41
42
43
44
45
46
47
48
CP
IOH
I
P0[6]
Vdd
Power
Supply voltage
OCDO OCD even data IO
OCDE OCD odd data output
IOH
IOH
IOH
I
I
I
P0[7]
P0[5]
P0[3]
Vss
Integrating input
Power
IOH
Power
Ground connection
I
P0[1]
Vss
Center pad must be connected to ground
LEGEND A = Analog, I = Input, O = Output, NC = No Connection H = 5 mA High Output Drive, R = Regulated Output.
Note
4. This part is available in limited quantities for In-Circuit Debugging during prototype development. It is not available in production volumes.
Document Number: 001-12696 Rev. *D
Page 14 of 34
Download from Www.Somanuals.com. All Manuals Search And Download.
CY8C20x36/46/66, CY8C20396
Electrical Specifications
This section presents the DC and AC electrical specifications of the CY8C20x36/46/66, CY8C20396 PSoC devices. For the latest
electrical specifications, confirm that you have the most recent data sheet by visiting the web at http://www.cypress.com/psoc.
Figure 9. Voltage versus CPU Frequency
Figure 10. IMO Frequency Trim Options
5.5V
5.5V
SLIMO SLIMO SLIMO
Mode
= 01
Mode
= 00
Mode
= 10
1.71V
1.71V
750 kHz
3 MHz
750 kHz
3 MHz
6 MHz 12 MHz 24 MHz
24 MHz
IMO Frequency
CPU Frequency
The following table lists the units of measure that are used in this section.
Table 9. Units of Measure
Symbol
Unit of Measure
degree Celsius
Symbol
Unit of Measure
°C
mA
ms
mV
nA
ns
milli-ampere
milli-second
milli-volts
dB
decibels
fF
femto farad
hertz
Hz
nanoampere
nanosecond
nanovolts
KB
Kbit
kHz
ksps
kΩ
1024 bytes
1024 bits
nV
Ω
kilohertz
ohm
kilo samples per second
kilohm
pA
pF
pp
ppm
ps
picoampere
picofarad
MHz
MΩ
μA
megahertz
megaohm
microampere
microfarad
microhenry
microsecond
microwatts
peak-to-peak
parts per million
picosecond
μF
sps
s
samples per second
μH
μs
sigma: one standard deviation
volts
V
μW
Document Number: 001-12696 Rev. *D
Page 15 of 34
Download from Www.Somanuals.com. All Manuals Search And Download.
CY8C20x36/46/66, CY8C20396
Comparator User Module Electrical Specifications
The following table lists the guaranteed maximum and minimum specifications. Unless stated otherwise, the specifications are for the
entire device voltage and temperature operating range: –40°C <= TA <= 85°C, 1.71V <= Vdd <= 5.5V.
Table 10. Comparator User Module Electrical Specifications
Symbol
Description
Min
Typ
70
Max
100
30
Units
ns
Conditions
50 mV overdrive
T
Comparator Response Time
COMP
Offset
2.5
20
mV
Current
PSRR
80
µA Average DC current, 50 mV
overdrive
Supply voltage >2V
Supply voltage <2V
80
40
dB Power Supply Rejection Ratio
dB Power Supply Rejection Ratio
V
Input
0
1.5
Range
ADC Electrical Specifications
Table 11. ADC User Module Electrical Specifications
Symbol
Input
Description
Min
Typ
Max
Units
Conditions
V
Input Voltage Range
Vss
1.3
V
This gives 72% of maximum
code
IN
C
Input Capacitance
Resolution
5
pF
IN
RES
S8
8
10
Bits Settings 8, 9, or 10
8-Bit Sample Rate
23.4375
5.859
ksps Data Clock set to 6 MHz.
Sample Rate = 0.001/
(2^Resolution/Data clock)
S10
10-Bit Sample Rate
ksps Data Clock set to 6 MHz.
Sample Rate = 0.001/
(2^Resolution/Data clock)
DC Accuracy
DNL
INL
Differential Nonlinearity
-1
-2
0
+2
+2
LSB For any configuration
Integral Nonlinearity
Offset Error
LSB For any configuration
Eoffset
15
90
mV
I
Operating Current
Data Clock
275
350
12
μA
ADC
F
2.25
MHz Source is chip’s internal main
oscillator. See device data
sheet for accuracy.
CLK
PSRR Power Supply Rejection Ration
PSRR (Vdd>3.0V)
24
30
12
0
dB
PSRR (2.2 < Vdd < 3.0)
PSRR (2.0 < Vdd < 2.2)
PSRR (Vdd < 2.0)
dB
dB
dB
Egain Gain Error
1
5
%FSR For any resolution
R
Input Resistance
1/(500fF*
1/(400fF*
1/(300fF*
Ω
Equivalent switched cap input
resistance for 8-, 9-, or 10-bit
resolution.
IN
Data-Clock) Data-Clock) Data-Clock)
Note
5. Monotonicity is not guaranteed.
Document Number: 001-12696 Rev. *D
Page 16 of 34
Download from Www.Somanuals.com. All Manuals Search And Download.
CY8C20x36/46/66, CY8C20396
Absolute Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested.
Table 12. Absolute Maximum Ratings
Symbol
Description
Conditions
Min
Typ
Max
Units
T
Storage Temperature
Higher storage temperatures reduces data
retention time. Recommended Storage
Temperature is +25°C ± 25°C. Extended
–55
+25
+125
°C
STG
o
duration storage temperatures above 85 C
degrades reliability.
Vdd
Supply Voltage Relative to Vss
DC Input Voltage
–0.5
Vss – 0.5
Vss –0.5
–25
–
–
–
–
–
–
+6.0
Vdd + 0.5
Vdd + 0.5
+50
V
V
V
V
IO
IOZ
MIO
DC Voltage Applied to Tri-state
Maximum Current into any Port Pin
Electro Static Discharge Voltage
Latch up Current
V
I
mA
V
ESD
LU
Human Body Model ESD
2000
–
In accordance with JESD78 standard
–
200
mA
Operating Temperature
Table 13. Operating Temperature
Symbol
Description
Ambient Temperature
Conditions
Min
Typ
Max
Units
T
–40
–
+85
°C
A
T
Operational Die Temperature
The temperature rise fromambientto junction
is package specific. Refer the table Thermal
Impedances per Package on page 28. The
user must limit the power consumption to
comply with this requirement.
J
–40
–
+100
°C
DC Chip-Level Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 14. DC Chip-Level Specifications
Symbol
Vdd
Description
Supply Voltage
Conditions
Min
Typ
Max
Units
Refer the table DC POR and LVD
Specifications on page 21
1.71
–
5.5
V
I
I
I
Supply Current, IMO = 24 MHz
Supply Current, IMO = 12 MHz
Supply Current, IMO = 6 MHz
Deep Sleep Current
Conditions are Vdd = 3.0V, T = 25°C,
CPU = 24 MHz. CapSense running at 12
MHz, no IO sourcing current
–
–
–
2.88
1.71
1.16
4.0
2.6
1.8
mA
mA
mA
DD24
DD12
DD6
A
Conditions are Vdd = 3.0V, T = 25°C,
A
CPU = 12 MHz. CapSense running at 12
MHz, no IO sourcing current
Conditions are Vdd = 3.0V, T = 25°C,
A
CPU = 6 MHz. CapSense running at 6 MHz,
no IO sourcing current
I
I
Vdd = 3.0V, T = 25°C, IO regulator turned off
–
–
0.1
–
μA
μA
SB0
A
Standby Current with POR, LVD and Vdd = 3.0V, T = 25°C, IO regulator turned off
Sleep Timer
1.07
1.5
SB1
A
Document Number: 001-12696 Rev. *D
Page 17 of 34
Download from Www.Somanuals.com. All Manuals Search And Download.
CY8C20x36/46/66, CY8C20396
DC General Purpose IO Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0V to 5.5V and
–40°C ≤ T ≤ 85°C, 2.4V to 3.0V and –40°C ≤ T ≤ 85°C, or 1.71V to 2.4V and –40°C ≤ T ≤ 85°C, respectively. Typical parameters
A
A
A
apply to 5V and 3.3V at 25°C and are for design guidance only.
Table 15. 3.0V to 5.5V DC GPIO Specifications
Symbol
Description
Pull up Resistor
Conditions
Min
Typ
5.6
–
Max
8
Units
kΩ
R
4
PU
V
V
V
High Output Voltage
Port 2 or 3 Pins
IOH < 10 μA, maximum of 10 mA source Vdd - 0.2
current in all IOs
–
V
OH1
High Output Voltage
Port 2 or 3 Pins
IOH = 1 mA, maximum of 20 mA source
current in all IOs
Vdd - 0.9
–
–
–
–
V
V
OH2
OH3
High Output Voltage
Port 0 or 1 Pins with LDO Regulator current in all IOs
IOH < 10 μA, maximum of 10 mA source Vdd - 0.2
Disabled for Port 1
V
V
V
V
V
V
V
V
High Output Voltage
Port 0 or 1 Pins with LDO Regulator current in all IOs
Disabled for Port 1
IOH = 5 mA, maximum of 20 mA source
Vdd - 0.9
2.85
2.20
2.35
1.90
1.60
1.20
–
–
3.00
–
–
3.3
–
V
V
V
V
V
V
V
V
OH4
OH5
OH6
OH7
OH8
OH9
OH10
OL
High Output Voltage
Port 1 Pins with LDO Regulator
Enabled for 3V Out
IOH < 10 μA, Vdd > 3.1V, maximum of
4 IOs all sourcing 5 mA
High Output Voltage
Port 1 Pins with LDO Regulator
Enabled for 3V Out
IOH = 5 mA, Vdd > 3.1V, maximum of
20 mA source current in all IOs
High Output Voltage
Port 1 Pins with LDO Enabled for 2.5V 20 mA source current in all IOs
Out
IOH < 10 μA, Vdd > 2.7V, maximum of
2.50
–
2.75
–
High Output Voltage
Port 1 Pins with LDO Enabled for 2.5V 20 mA source current in all IOs
Out
IOH = 2 mA, Vdd > 2.7V, maximum of
High Output Voltage
Port 1 Pins with LDO Enabled for 1.8V 20 mA source current in all IOs
Out
IOH < 10 μA, Vdd > 2.7V, maximum of
1.80
–
2.1
–
High Output Voltage
Port 1 Pins with LDO Enabled for 1.8V 20 mA source current in all IOs
Out
IOH = 1 mA, Vdd > 2.7V, maximum of
Low Output Voltage
IOL = 25 mA, Vdd > 3.3V, maximum of
60 mA sink current on even port pins (for
example, P0[2] and P1[4]) and 60 mA sink
current on odd port pins (for example, P0[3]
and P1[5])
–
0.75
V
V
V
I
Input Low Voltage
–
2.00
–
–
–
0.80
V
V
IL
IH
H
Input High Voltage
Input Hysteresis Voltage
Input Leakage (Absolute Value)
Pin Capacitance
80
–
1
5
mV
μA
pF
–
0.001
1.7
IL
C
Package and pin dependent
Temp = 25°C
0.5
PIN
Document Number: 001-12696 Rev. *D
Page 18 of 34
Download from Www.Somanuals.com. All Manuals Search And Download.
CY8C20x36/46/66, CY8C20396
Table 16. 2.4V to 3.0V DC GPIO Specifications
Symbol Description
Pull up Resistor
Conditions
Min
4
Typ
5.6
–
Max
8
Units
kΩ
R
PU
V
V
V
High Output Voltage
Port 2 or 3 Pins
IOH < 10 μA, maximum of 10 mA
source current in all IOs
Vdd - 0.2
–
V
OH1
High Output Voltage
Port 2 or 3 Pins
IOH = 0.2 mA, maximum of 10 mA
source current in all IOs
Vdd - 0.4
Vdd - 0.2
–
–
–
–
V
V
OH2
OH3
High Output Voltage
Port 0 or 1 Pins with LDO Regulator
IOH < 10 μA, maximum of 10 mA
source current in all IOs
Disabled for Port 1
V
V
V
V
High Output Voltage
Port 0 or 1 Pins with LDO Regulator
Disabled for Port 1
IOH = 2 mA, maximum of 10 mA source Vdd - 0.5
current in all IOs
–
1.80
–
–
2.1
–
V
V
V
V
OH4
OH5A
OH6A
OL
High Output Voltage
Port 1 Pins with LDO Enabled for 1.8V 20 mA source current in all IOs
Out
IOH < 10 μA, Vdd > 2.4V, maximum of
1.50
1.20
–
High Output Voltage
Port 1 Pins with LDO Enabled for 1.8V 20 mA source current in all IOs
Out
IOH = 1 mA, Vdd > 2.4V, maximum of
Low Output Voltage
IOL = 10 mA, maximum of 30 mA sink
current on even port pins (for example,
P0[2] and P1[4]) and 30 mA sink
current on odd port pins (for example,
P0[3] and P1[5])
–
0.75
V
V
V
I
Input Low Voltage
–
1.4
–
–
–
0.72
V
V
IL
IH
H
Input High Voltage
Input Hysteresis Voltage
Input Leakage (Absolute Value)
Capacitive Load on Pins
80
–
1
5
mV
μA
pF
–
0.001
1.7
IL
C
Package and pin dependent
Temp = 25 C
0.5
PIN
o
Table 17. 1.71V to 2.4V DC GPIO Specifications
Symbol Description
Pull up Resistor
Conditions
Min
4
Typ
5.6
–
Max
8
Units
kΩ
R
PU
V
V
V
High Output Voltage
Port 2 or 3 Pins
IOH = 10 μA, maximum of 10 mA
source current in all IOs
Vdd - 0.2
–
V
OH1
High Output Voltage
Port 2 or 3 Pins
IOH = 0.5 mA, maximum of 10 mA
source current in all IOs
Vdd - 0.5
Vdd - 0.2
–
–
–
–
V
V
OH2
OH3
High Output Voltage
Port 0 or 1 Pins with LDO Regulator
Disabled for Port 1
IOH = 100 μA, maximum of 10 mA
source current in all IOs
V
High Output Voltage
Port 0 or 1 Pins with LDO Regulator
Disabled for Port 1
IOH=2mA, maximumof10mAsource Vdd - 0.5
current in all IOs
–
–
–
V
V
OH4
OL
V
Low Output Voltage
IOL = 5 mA, maximum of 20 mA sink
current on even port pins (for example,
P0[2] and P1[4]) and 30 mA sink
current on odd port pins (for example,
P0[3] and P1[5])
–
0.4
V
V
Input Low Voltage
Input High Voltage
–
–
–
0.3 x Vdd
V
V
IL
0.65 x Vdd
IH
Document Number: 001-12696 Rev. *D
Page 19 of 34
Download from Www.Somanuals.com. All Manuals Search And Download.
CY8C20x36/46/66, CY8C20396
Table 17. 1.71V to 2.4V DC GPIO Specifications (continued)
Symbol
Description
Input Hysteresis Voltage
Input Leakage (Absolute Value)
Capacitive Load on Pins
Conditions
Min
–
Typ
80
Max
Units
mV
μA
V
–
1
5
H
I
–
0.001
1.7
IL
C
Package and pin dependent
Temp = 25 C
0.5
pF
PIN
o
Table 18.DC Characteristics – USB Interface
Symbol
Rusbi
Rusba
Vohusb
Volusb
Vdi
Description
USB D+ Pull Up Resistance
USB D+ Pull Up Resistance
Static Output High
Conditions
With idle bus
Min
0.900
1.425
2.8
Typ
Max
1.575
3.090
3.6
Units
kΩ
kΩ
V
-
-
-
-
-
-
While receiving traffic
Static Output Low
0.3
V
Differential Input Sensitivity
0.2
0.8
V
Vcm
Differential Input Common Mode
Range
2.5
V
Vse
Cin
Single Ended Receiver Threshold
Transceiver Capacitance
0.8
-
2.0
50
V
-
-
pF
μA
kΩ
Ω
Iio
Hi-Z State Data Line Leakage
PS/2 Pull Up Resistance
On D+ or D- line
-10
3
+10
7
Rps2
Rext
5
External USB Series Resistor
In series with each USB pin
21.78
22.0
22.22
DC Analog Mux Bus Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 19. DC Analog Mux Bus Specifications
Symbol
Description
Conditions
Min
Typ
Max
Units
R
Switch Resistance to Common Analog
Bus
–
–
800
Ω
SW
R
Resistance of Initialization Switch to
Vss
–
–
800
Ω
GND
The maximum pin voltage for measuring R
and R
is 1.8V
GND
SW
DC Low Power Comparator Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 20. DC Comparator Specifications
Symbol
Description
Conditions
Min
Typ
Max
Units
V
Low Power Comparator (LPC)
common mode
Maximum voltage limited to Vdd
0.0
–
1.8
V
LPC
I
LPC supply current
LPC voltage offset
–
–
10
40
30
μA
LPC
V
2.5
mV
OSLPC
Document Number: 001-12696 Rev. *D
Page 20 of 34
Download from Www.Somanuals.com. All Manuals Search And Download.
CY8C20x36/46/66, CY8C20396
DC POR and LVD Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 21. DC POR and LVD Specifications
Symbol
Description
Conditions
Min
Typ
Max
Units
Vdd Value for PPOR Trip
Vdd must be greater than or equal to
V
PORLEV[1:0] = 00b, HPOR = 0 1.71Vduringstartup, resetfromtheXRES
PORLEV[1:0] = 00b, HPOR = 1 pin, or reset from watchdog.
PORLEV[1:0] = 01b, HPOR = 1
1.61
–
1.66
2.36
2.60
2.82
1.71
2.41
2.66
2.95
V
V
V
V
PPOR0
PPOR1
PPOR2
PPOR3
V
V
V
PORLEV[1:0] = 10b, HPOR = 1
Vdd Value for LVD Trip
VM[2:0] = 000b
VM[2:0] = 001b
VM[2:0] = 010b
VM[2:0] = 011b
VM[2:0] = 100b
VM[2:0] = 101b
VM[2:0] = 110b
VM[2:0] = 111b
[6]
V
V
V
V
V
V
V
V
2.40
2.64
2.85
2.45
2.71
2.92
3.02
3.13
1.90
1.80
4.73
2.51
2.78
2.99
3.09
3.20
2.32
1.84
4.83
V
V
V
V
V
V
V
V
LVD0
LVD1
LVD2
LVD3
LVD4
LVD5
LVD6
LVD7
[7]
[8]
2.95
3.06
1.84
[9]
1.75
4.62
DC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 22. DC Programming Specifications
Symbol
Vdd
Description
Conditions
Min
Typ
Max
Units
Supply Voltage for Flash Write
Operations
1.71
–
–
V
IWRITE
I
Supply Current During
Programming or Verify
–
–
5
–
–
25
mA
V
DDP
V
V
Input Low Voltage During
Programming or Verify
See the appropriate DC General Purpose
V
IL
ILP
Input High Voltage During
Programming or Verify
See appropriate DC General Purpose IO
Specifications on page 18 table on pages
15 or 16
V
–
V
IHP
IH
I
I
Input Current when Applying Vilp Driving internal pull down resistor
to P1[0] or P1[1] During
Programming or Verify
–
–
–
0.2
1.5
mA
mA
ILP
Input Current when Applying Vihp Driving internal pull down resistor
to P1[0] or P1[1] During
–
IHP
Programming or Verify
V
V
Output Low Voltage During
Programming or Verify
–
–
–
Vss + 0.75
Vdd
V
V
OLP
Output High Voltage During
Programming or Verify
See appropriate DC General Purpose IO
Specifications on page 18 table on page
V
OH
OHP
16. For Vdd > 3V use V
OH4
Flash
Flash
Flash Write Endurance
Flash Data Retention
Erase/write cycles per block
50,000
10
–
–
–
-
ENPB
Following maximum Flash write cycles;
ambient temperature of 55°C
20
Years
DR
Notes
6. Always greater than 50 mV above V
7. Always greater than 50 mV above V
8. Always greater than 50 mV above V
9. Always greater than 50 mV above V
voltage for falling supply.
PPOR1
PPOR2
PPOR3
PPOR0
voltage for falling supply.
voltage for falling supply.
voltage for falling supply.
Document Number: 001-12696 Rev. *D
Page 21 of 34
Download from Www.Somanuals.com. All Manuals Search And Download.
CY8C20x36/46/66, CY8C20396
AC Chip-Level Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 23. AC Chip-Level Specifications
Symbol
Description
Conditions
Min
24
Typ
–
Max
–
Units
MHz
MHz
kHz
F
F
F
F
Maximum Operating Frequency
Maximum Processing Frequency
Internal Low Speed Oscillator Frequency
MAX
24
–
–
CPU
19
32
24
50
25.2
32K1
IMO24
Internal Main Oscillator Frequency at 24
MHz Setting
22.8
MHz
F
F
Internal Main Oscillator Frequency at 12
MHz Setting
11.4
5.7
12
12.6
6.3
MHz
MHz
IMO12
IMO6
Internal Main Oscillator Frequency at 6
MHz Setting
6.0
DC
T
Duty Cycle of IMO
Supply Ramp Time
40
0
50
–
60
–
%
μs
ms
μs
IMO
RAMP
XRST
XRST2
T
T
External Reset Pulse Width at Power Up After supply voltage is valid
1
External Reset Pulse Width after Power Applies after part has booted
Up
10
AC General Purpose IO Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 24. AC GPIO Specifications
Symbol
Description
Conditions
Min
Typ
Max
Units
F
GPIO Operating Frequency
Normal Strong Mode Port 0, 1
0
–
6 MHz for
1.71V<Vdd<2.4V
MHz
GPIO
0
–
–
–
–
–
–
–
12 MHz for
2.4V<Vdd<5.5V
TRise23
Rise Time, Strong Mode, Cload = 50 pF Vdd = 3.0 to 3.6V, 10% – 90%
Ports 2 or 3
15
15
10
10
10
10
80
80
50
80
50
70
ns
ns
ns
ns
ns
ns
TRise23L Rise Time, Strong Mode Low Supply,
Cload = 50 pF, Ports 2 or 3
Vdd = 1.71 to 3.0V, 10% – 90%
TRise01
Rise Time, Strong Mode, Cload = 50 pF Vdd = 3.0 to 3.6V, 10% – 90%
Ports 0 or 1
LDO enabled or disabled
TRise01L Rise Time, Strong Mode Low Supply,
Cload = 50 pF, Ports 0 or 1
Vdd = 1.71 to 3.0V, 10% – 90%
LDO enabled or disabled
TFall
Fall Time, Strong Mode, Cload = 50 pF Vdd = 3.0 to 3.6V, 10% – 90%
All Ports
TFallL
Fall Time, Strong Mode Low Supply,
Cload = 50 pF, All Ports
Vdd = 1.71 to 3.0V, 10% – 90%
Document Number: 001-12696 Rev. *D
Page 22 of 34
Download from Www.Somanuals.com. All Manuals Search And Download.
CY8C20x36/46/66, CY8C20396
Figure 11. GPIO Timing Diagram
90%
GPIO Pin
Output
Voltage
10%
TRise23
TRise01
TRise23L
TRise01L
TFall
TFallL
Table 25.AC Characteristics – USB Data Timings
Symbol
Tdrate
Description
Full speed data rate
Conditions
Min
12–0.25%
-18.5
-9
Typ
12
–
Max
Units
Average bit rate
To next transition
To pair transition
To next transition
To pair transition
To SE0 transition
12 + 0.25% MHz
Tdjr1
Receiver data jitter tolerance
Receiver data jitter tolerance
Driver differential jitter
Driver differential jitter
18.5
9
ns
ns
ns
ns
ns
Tdjr2
–
Tudj1
Tudj2
Tfdeop
-3.5
–
3.5
4.0
5
-4.0
–
Source jitter for differential
transition
-2
–
Tfeopt
Tfeopr
Tfst
Source SE0 interval of EOP
Receiver SE0 interval of EOP
160
82
–
–
–
175
14
ns
ns
ns
Width of SE0 interval during
differential transition
Table 26.AC Characteristics – USB Driver
Symbol Description
Transition rise time
Conditions
Min
4
Typ
–
Max
20
Units
ns
Tr
Tf
50 pF
50 pF
Transition fall time
4
–
20
ns
TR
Rise/fall time matching
Output signal crossover voltage
90.00
1.3
–
111.1
2.0
%
Vcrs
–
V
AC Comparator Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 27. AC Low Power Comparator Specifications
Symbol
Description
Comparator Response Time, 50 50 mV overdrive does not include
mV Overdrive offset voltage.
Conditions
Min
Typ
Max
Units
T
100
ns
LPC
AC Analog Mux Bus Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 28. AC Analog Mux Bus Specifications
Symbol
Description
Switch Rate
Conditions
Min
Typ
Max
Units
F
Maximumpinvoltagewhenmeasuring
switch rate is 1.8Vp-p
–
–
6.3
MHz
SW
Document Number: 001-12696 Rev. *D
Page 23 of 34
Download from Www.Somanuals.com. All Manuals Search And Download.
CY8C20x36/46/66, CY8C20396
AC External Clock Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 29. AC External Clock Specifications
Symbol
Description
Conditions
Min
0.750
20.6
20.6
150
Typ
–
Max
25.2
5300
–
Units
MHz
ns
F
Frequency
High Period
Low Period
OSCEXT
–
–
–
–
–
ns
Power Up IMO to Switch
–
–
μs
AC Programming Specifications
Figure 12. AC Waveform
SCLK (P1[1])
TRSCLK
TFSCLK
SDATA (P1[0])
TSSCLK
THSCLK
TDSCLK
The following table lists the guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 30. AC Programming Specifications
Symbol
Description
Rise Time of SCLK
Conditions
Min
1
Typ
–
Max
20
20
–
Units
ns
T
RSCLK
FSCLK
SSCLK
HSCLK
SCLK
T
T
T
F
T
T
T
T
T
Fall Time of SCLK
1
–
ns
Data Set up Time to Falling Edge of SCLK
Data Hold Time from Falling Edge of SCLK
Frequency of SCLK
40
40
0
–
ns
–
–
ns
–
8
MHz
ms
ms
ns
Flash Erase Time (Block)
–
–
18
25
60
85
130
ERASEB
WRITE
DSCLK
DSCLK3
DSCLK2
Flash Block Write Time
–
–
Data Out Delay from Falling Edge of SCLK 3.6 < Vdd
–
–
Data Out Delay from Falling Edge of SCLK 3.0 ≤ Vdd ≤ 3.6
Data Out Delay from Falling Edge of SCLK 1.71 ≤ Vdd ≤ 3.0
–
–
ns
–
–
ns
Document Number: 001-12696 Rev. *D
Page 24 of 34
Download from Www.Somanuals.com. All Manuals Search And Download.
CY8C20x36/46/66, CY8C20396
AC SPI Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 31. AC SPI Specifications
Symbol
Description
Conditions
Min
Typ
Max
Units
F
Output clock frequency is half
of input clock rate.
–
–
12
MHz
Maximum Input Clock Frequency Selection,
Master 2.4V<Vdd<5.5V
SPIM
Output clock frequency is half
of input clock rate
6
MHz
Maximum Input Clock Frequency Selection,
Master(21)1.71V<Vdd<2.4V
F
T
Maximum Input Clock Frequency Selection,
Slave 2.4<Vdd<5.5V
–
–
–
12
6
MHz
MHz
ns
SPIS
Maximum Input Clock Frequency Selection,
Slave 1.71V<Vdd<2.4V
Width of SS_ Negated Between Transmissions
50
–
SS
2
AC I C Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
2
Table 32. AC Characteristics of the I C SDA and SCL Pins
Standard Mode Fast Mode
Symbol
Description
Units
Min
0
Max
100
–
Min Max
F
T
SCL Clock Frequency
0
400
–
kHz
SCLI2C
Hold Time (repeated) START Condition. After this period, the first clock pulse is
generated.
4.0
0.6
μs
HDSTAI2C
T
T
T
T
T
LOW Period of the SCL Clock
HIGH Period of the SCL Clock
Setup Time for a Repeated START Condition
Data Hold Time
4.7
4.0
4.7
0
–
–
–
–
–
1.3
0.6
0.6
0
–
–
–
–
–
μs
μs
μs
μs
ns
LOWI2C
HIGHI2C
SUSTAI2C
HDDATI2C
SUDATI2C
[1
Data Setup Time
250
100
0]
T
T
T
Setup Time for STOP Condition
4.0
4.7
–
–
–
–
0.6
1.3
0
–
–
μs
μs
ns
SUSTOI2C
BUFI2C
SPI2C
Bus Free Time Between a STOP and START Condition
Pulse Width of spikes are suppressed by the input filter.
50
2
Figure 13. Definition for Timing for Fast/Standard Mode on the I C Bus
SDA
SCL
TSPI2C
T
LOWI2C
TSUDATI2C
THDSTAI2C
TBUFI2C
TSUSTOI2C
TSUSTAI2C
THDDATI2C
THDSTAI2C
THIGHI2C
S
Sr
P
S
Note
10. A Fast-Mode I2C-bus device can be used in a Standard Mode I2C-bus system, but the requirement t
≥ 250 ns must then be met. This automatically be the case
SU;DAT
if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the
SDA line t + t = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.
rmax
SU;DAT
Document Number: 001-12696 Rev. *D
Page 25 of 34
Download from Www.Somanuals.com. All Manuals Search And Download.
CY8C20x36/46/66, CY8C20396
Packaging Information
This section illustrates the packaging specifications for the CY8C20x36/46/66, CY8C20396 PSoC device, along with the thermal
impedances for each package.
Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of
the emulation tools’ dimensions, refer to the document titled PSoC Emulator Pod Dimensions at
Figure 14. 16-Pin Chip On Lead 3x3 mm (Sawn)
001-09116 *D
Figure 15. 24-Pin (4x4 x 0.6 mm) QFN
001-13937 *B
Document Number: 001-12696 Rev. *D
Page 26 of 34
Download from Www.Somanuals.com. All Manuals Search And Download.
CY8C20x36/46/66, CY8C20396
Figure 16. 32-Pin (5x5 x 0.6 mm) QFN
SEE NOTE 1
TOP VIEW
BOTTOM VIEW
SIDE VIEW
NOTES:
1. HATCH AREA IS SOLDERABLE EXPOSED PAD
2. BASED ON REF JEDEC # MO-248
3. PACKAGE WEIGHT: 0.0388g
001-42168 *C
4. DIMENSIONS ARE IN MILLIMETERS
Figure 17. 48-Pin (300 MIL) SSOP
.020
1
24
0.395
0.420
0.292
0.299
DIMENSIONS IN INCHES MIN.
MAX.
25
48
0.620
0.630
0.005
0.010
SEATING PLANE
.010
0.088
0.092
0.095
0.110
GAUGE PLANE
0.004
0.024
0.040
0.025
BSC
0°-8°
0.008
0.016
0.008
0.0135
51-85061 *C
Document Number: 001-12696 Rev. *D
Page 27 of 34
Download from Www.Somanuals.com. All Manuals Search And Download.
CY8C20x36/46/66, CY8C20396
Figure 18. 48-Pin (7x7 mm) QFN
001-13191 *C
Important Notes
■ For information on the preferred dimensions for mounting QFN packages, see the following Application Note at
■ Pinned vias for thermal conduction are not required for the low power PSoC device.
Thermal Impedances
Table 33. Thermal Impedances per Package
[11]
Package
Typical θ
JA
o
32.69 C/W
16 QFN
o
[12]
20.90 C/W
24 QFN
32 QFN
o
[12]
19.51 C/W
o
69 C/W
48 SSOP
o
[12]
17.68 C/W
48 QFN
Solder Reflow Peak Temperature
This table lists the minimum solder reflow peak temperature to achieve good solderability.
Table 34. Solder Reflow Peak Temperature
Package
16 QFN
24 QFN
32 QFN
48 SSOP
48 QFN
Maximum Peak Temperature
Minimum Peak Temperature
o
o
240 C
260 C
o
o
240 C
260 C
o
o
240 C
260 C
o
o
220 C
260 C
o
o
240 C
260 C
Notes
11. T = T + Power x θ .
JA
J
A
12. To achieve the thermal impedance specified for the QFN package, the center thermal pad must be soldered to the PCB ground plane.
o
o
13. Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 ± 5 C with Sn-Pb or 245 ± 5 C with Sn-Ag-Cu paste.
Refer to the solder manufacturer specifications.
Document Number: 001-12696 Rev. *D
Page 28 of 34
Download from Www.Somanuals.com. All Manuals Search And Download.
CY8C20x36/46/66, CY8C20396
Development Tool Selection
Software
Development Kits
All development kits are sold at the Cypress Online Store.
PSoC Designer™
At the core of the PSoC development software suite is PSoC
Designer. This is used by thousands of PSoC developers. This
robust software is facilitating PSoC designs for half a decade.
PSoC Designer is available free of charge at
http://www.cypress.com under DESIGN RESOURCES >>
Software and Drivers.
CY3215-DK Basic Development Kit
The CY3215-DK is for prototyping and development with PSoC
Designer. This kit supports in-circuit emulation and the software
interface enables users to run, halt, and single step the
processor and view the content of specific memory locations.
PSoC Designer supports the advance emulation features also.
The kit includes:
PSoC Programmer
■ PSoC Designer Software CD
PSoC Programmer is flexible enough and is used on the bench
in development and is also suitable for factory programming.
PSoC Programmer works either as a standalone programming
application or operates directly from PSoC Designer or PSoC
Express. PSoC Programmer software is compatible with both
PSoC ICE Cube In-Circuit Emulator and PSoC MiniProg. PSoC
programmer is available free of charge at
■ ICE-Cube In-Circuit Emulator
■ ICE Flex-Pod for CY8C29x66 Family
■ Cat-5 Adapter
■ Mini-Eval Programming Board
■ 110 ~ 240V Power Supply, Euro-Plug Adapter
■ iMAGEcraft C Compiler (Registration Required)
■ ISSP Cable
C Compilers
PSoC Designer comes with a free HI-TECH C Lite C compiler.
The HI-TECH C Lite compiler is free, supports all PSoC devices,
integrates fully with PSoC Designer and PSoC Express, and
runs on Windows versions up to 32-bit Vista. Compilers with
additional features are available at additional cost from their
manufactures.
■ USB 2.0 Cable and Blue Cat-5 Cable
■ 2 CY8C29466-24PXI 28-PDIP Chip Samples
CY3210-ExpressDK PSoC Express Development Kit
■ HI-TECH C PRO for the PSoC is available from
The CY3210-ExpressDK is for advanced prototyping and
development with PSoC Express (used with ICE-Cube In-Circuit
Emulator). It provides access to I C buses, voltage reference,
2
switches, upgradeable modules, and more. The kit includes:
■ PSoC Express Software CD
■ Express Development Board
■ Four Fan Modules
■ Two Proto Modules
■ MiniProg In-System Serial Programmer
■ MiniEval PCB Evaluation Board
■ Jumper Wire Kit
■ USB 2.0 Cable
■ Serial Cable (DB9)
■ 110 ~ 240V Power Supply, Euro-Plug Adapter
■ 2 CY8C24423A-24PXI 28-PDIP Chip Samples
■ 2 CY8C27443-24PXI 28-PDIP Chip Samples
■ 2 CY8C29466-24PXI 28-PDIP Chip Samples
Document Number: 001-12696 Rev. *D
Page 29 of 34
Download from Www.Somanuals.com. All Manuals Search And Download.
CY8C20x36/46/66, CY8C20396
Device Programmers
Evaluation Tools
All device programmers are purchased from the Cypress Online
Store.
All evaluation tools are sold at the Cypress Online Store.
CY3210-MiniProg1
CY3216 Modular Programmer
The CY3210-MiniProg1 kit enables the user to program PSoC
devices via the MiniProg1 programming unit. The MiniProg is a
small, compact prototyping programmer that connects to the PC
via a provided USB 2.0 cable. The kit includes:
The CY3216 Modular Programmer kit features a modular
programmer and the MiniProg1 programming unit. The modular
programmer includes three programming module cards and
supports multiple Cypress products. The kit includes:
■ MiniProg Programming Unit
■ Modular Programmer Base
■ Three Programming Module Cards
■ MiniProg Programming Unit
■ PSoC Designer Software CD
■ Getting Started Guide
■ MiniEval Socket Programming and Evaluation Board
■ 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample
■ 28-Pin CY8C27443-24PXI PDIP PSoC Device Sample
■ PSoC Designer Software CD
■ Getting Started Guide
■ USB 2.0 Cable
■ USB 2.0 Cable
CY3207ISSP In-System Serial Programmer (ISSP)
CY3210-PSoCEval1
The CY3207ISSP is a production programmer. It includes
protection circuitry and an industrial case that is more robust than
the MiniProg in a production programming environment.
Note that CY3207ISSP needs special software and is not
compatible with PSoC Programmer. The kit includes:
The CY3210-PSoCEval1 kit features an evaluation board and
the MiniProg1 programming unit. The evaluation board includes
an LCD module, potentiometer, LEDs, and plenty of bread-
boarding space to meet all of your evaluation needs. The kit
includes:
■ CY3207 Programmer Unit
■ PSoC ISSP Software CD
■ Evaluation Board with LCD Module
■ MiniProg Programming Unit
■ 110 ~ 240V Power Supply, Euro-Plug Adapter
■ USB 2.0 Cable
■ 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample (2)
■ PSoC Designer Software CD
■ Getting Started Guide
■ USB 2.0 Cable
CY3214-PSoCEvalUSB
The CY3214-PSoCEvalUSB evaluation kit features
a
development board for the CY8C24794-24LFXI PSoC device.
Special features of the board include both USB and capacitive
sensing development and debugging support. This evaluation
board also includes an LCD module, potentiometer, LEDs, an
enunciator and plenty of bread boarding space to meet all of your
evaluation needs. The kit includes:
■ PSoCEvalUSB Board
■ LCD Module
■ MIniProg Programming Unit
■ Mini USB Cable
■ PSoC Designer and Example Projects CD
■ Getting Started Guide
■ Wire Pack
Document Number: 001-12696 Rev. *D
Page 30 of 34
Download from Www.Somanuals.com. All Manuals Search And Download.
CY8C20x36/46/66, CY8C20396
Accessories (Emulation and Programming)
Table 35. Emulation and Programming Accessories
[14]
[15]
Part Number
CY8C20236-24LKXI
CY8C20336-24LQXI
CY8C20436-24LQXI
CY8C20396-24LQXI
CY8C20246-24LKXI
CY8C20346-24LQXI
CY8C20446-24LQXI
CY8C20466-24LQXI
CY8C20566-24PVXI
CY8C20666-24LTXI
Pin Package
16 QFN
Flex-Pod Kit
Foot Kit
Adapter
CY3250-20266QFN
CY3250-20366QFN
CY3250-20466QFN
CY3250-16QFN-RK
CY3250-20366QFN
CY3250-32QFN-RK
See note 15
See note 15
See note 15
24 QFN
32 QFN
Not Available
16 QFN
24 QFN
32 QFN
32 QFN
48 SSOP
48 QFN
CY3250-20266QFN
CY3250-20366QFN
CY3250-20466QFN
CY3250-20466QFN
CY3250-20X66
CY3250-16QFN-FK
CY3250-24QFN-FK
CY3250-32QFN-FK
CY3250-32QFN-FK
CY3250-48SSOP-FK
CY3250-48QFN-FK
CY3250-20666QFN
Third-Party Tools
Build a PSoC Emulator into Your Board
Several tools have been specially designed by the following
third-party vendors to accompany PSoC devices during
development and production. Specific details for each of these
Documentation >> Evaluation Boards.
For details on how to emulate your circuit before going to volume
production using an on-chip debug (OCD) non-production PSoC
device, refer Application Note “Debugging - Build a PSoC
AN2323.
Notes
14. Flex-Pod kit includes a practice flex-pod and a practice PCB, in addition to two flex-pods.
15. Foot kit includes surface mount feet that can be soldered to the target PCB.
16. Programming adapter converts non-DIP package to DIP footprint. Specific details and ordering information for each of the adapters can be found at
Document Number: 001-12696 Rev. *D
Page 31 of 34
Download from Www.Somanuals.com. All Manuals Search And Download.
CY8C20x36/46/66, CY8C20396
Ordering Information
The following table lists the CY8C20x36/46/66, CY8C20396 PSoC devices key package features and ordering codes.
Table 36. PSoC Device Key Features and Ordering Information
Flash
SRAM CapSense Digital IO Analog XRES
Package
Ordering Code
USB
(Bytes) (Bytes)
Blocks
Pins
Inputs
Pin
Yes
Yes
16-Pin (3x3x0.6mm) QFN
CY8C20236-24LKXI
CY8C20236-24LKXIT
8K
8K
1K
1K
1
1
13
13
No
No
16-Pin (3x3x0.6mm) QFN
(Tape and Reel)
13
13
24-Pin (4x4x0.6mm) QFN
CY8C20336-24LQXI
CY8C20336-24LQXIT
8K
8K
1K
1K
1
1
20
20
20
20
Yes
Yes
No
No
24-Pin (4x4x0.6mm) QFN
(Tape and Reel)
32-Pin (5x5x0.6mm) QFN
CY8C20436-24LQXI
CY8C20436-24LQXIT
8K
8K
1K
1K
1
1
28
28
28
28
Yes
Yes
No
No
32-Pin (5x5x0.6mm) QFN
(Tape and Reel)
24-Pin (4x4x0.6mm) QFN
CY8C20396-24LQXI
CY8C20396-24LQXIT
16K
16K
2K
2K
1
1
19
19
19
19
Yes
Yes
Yes
Yes
24-Pin (4x4x0.6mm) QFN
(Tape and Reel)
16 Pin (3x3 x 0.6 mm) QFN
CY8C20246-24LKXI
CY8C20246-24LKXIT
16K
16K
2048
2048
1
1
13
13
Yes
Yes
No
No
13
16 Pin (3x3 x 0.6 mm) QFN
(Tape and Reel)
13
24 Pin (4x4 x 0.6 mm) QFN
CY8C20346-24LQXI
CY8C20346-24LQXIT
16K
16K
2048
2048
1
1
20
20
Yes
Yes
No
No
20
24 Pin (4x4 x 0.6 mm) QFN
(Tape and Reel)
20
32 Pin (5x5 x 0.6 mm) QFN
CY8C20446-24LQXI
CY8C20446-24LQXIT
16K
16K
2048
2048
1
1
28
28
Yes
Yes
No
No
28
32 Pin (5x5 x 0.6 mm) QFN
(Tape and Reel)
28
32 Pin (5x5 x 0.6 mm) QFN
CY8C20466-24LQXI
CY8C20466-24LQXIT
32K
32K
2048
2048
1
1
28
28
Yes
Yes
No
No
28
32 Pin (5x5 x 0.6 mm) QFN
(Tape and Reel)
28
48-Pin SSOP
CY8C20566-24PVXI
CY8C20566-24PVXIT
32K
32K
2048
2048
1
1
36
36
Yes
Yes
No
No
36
48-Pin SSOP
(Tape and Reel)
36
48 Pin (7x7 mm) QFN
CY8C20666-24LTXI
CY8C20666-24LTXIT
32K
32K
2048
2048
1
1
36
36
Yes
Yes
Yes
Yes
36
48 Pin (7x7 mm) QFN
(Tape and Reel)
36
[4]
48 Pin (7x7 mm) QFN (OCD)
CY8C20066-24LTXI
32K
2048
1
36
Yes
Yes
36
Notes
17. Dual-function Digital IO Pins also connect to the common analog mux.
Document Number: 001-12696 Rev. *D
Page 32 of 34
Download from Www.Somanuals.com. All Manuals Search And Download.
CY8C20x36/46/66, CY8C20396
Document History Page
Document Title: CY8C20x36/46/66, CY8C20396 CapSenseTM Applications
Document Number: 001-12696
Revision
**
ECN
Origin of Change Submission Date
Description of Change
766857
HMT
See ECN
See ECN
New silicon and document (Revision **).
*A
*B
1242866 HMT
Add features. Update all applicable sections. Update specs.
Fix 24-pin QFN pinout moving pins inside. Update package
revisions. Update and add to Emulation and Programming
Accessories table.
2174006 AESA
See ECN
Added 48-Pin SSOP Part Pinout
Modified symbol R
Specification
to R
in Table DC Analog Mux Bus
VDD
GND
Added footnote in Table DC Analog Mux Bus Specification
Added 16K FLASH Parts. Updated Notes, Package Diagrams
and Ordering Information table. Updated Thermal Impedance
and Solder Reflow tables
*C
2587518 TOF/JASM/MNU/ 10/13/08
HMT
Converted from Preliminary to Final
Fixed broken links. Updated data sheet template.
Added operating voltage ranges with USB
ADC resolution changed from 10-bit to 8-bit
Included ADC specifications table
Included Comparator specification table
Included Voh7, Voh8, Voh9, Voh10 specs
Flash data retention – condition added to Note
Input leakage spec changed to 1 μA max
GPIO rise time for ports 0,1 and ports 2,3 made common
AC Programming specifications updated
Included AC Programming cycle timing diagram
AC SPI specification updated
The VIH for 3.0<Vdd<2.4 changed to 1.6 from 2.0
Added USB specification
Added SPI CLK to P1[0]
Updated package diagrams
Updated thermal impedances for QFN packages
Updated F
Updated voltage ranges for F
parameter in Table 23
GPIO
and F
in Table 30
SPIM
SPIS
Update Development Tools, add Designing with PSoC
Designer. Edit, fix links, notes and table format. Update R
IN
formula, fix TRise parameter names in GPIO figure, fix Switch
Rate note. Update maximum data in Table 20. DC POR and
LVD Specifications.
*D
2649637 SNV/AESA
03/17/2009
Changed title to “CY8C20x36/46/66, CY8C20396
CapSense™ Applications”. Updated data sheet Features, pin
information, and ordering information sections. Updated
package diagram 001-42168 to *C.
Document Number: 001-12696 Rev. *D
Page 33 of 34
Download from Www.Somanuals.com. All Manuals Search And Download.
CY8C20x36/46/66, CY8C20396
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at cypress.com/sales.
Products
PSoC
PSoC Solutions
General
Clocks & Buffers
Wireless
Low Power/Low Voltage
Precision Analog
LCD Drive
Memories
Image Sensors
CAN 2.0b
USB
CapSense™, PSoC Designer™, and Programmable System-on-Chip™ are trademarks and PSoC® is a registered trademark of Cypress Semiconductor Corporation. All other trademarks or registered
trademarks referenced herein are property of the respective corporations. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the
Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. All products and company names
mentioned in this document may be the trademarks of their respective holders.
© Cypress Semiconductor Corporation, 2007-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-12696 Rev. *D
Revised March 17, 2009
Page 34 of 34
Download from Www.Somanuals.com. All Manuals Search And Download.
|