Technical
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The information in this document is subject to change without notice.
COMPAQ COMPUTER CORPORATION SHALL NOT BE LIABLE FOR TECHNICAL OR
EDITORIAL ERRORS OR OMISSIONS HEREIN; NOR FOR INCIDENTAL OR
CONSEQUENTIAL DAMAGES RESULTING FROM THE FURNISHING, PERFORMANCE,
OR USE OF THIS MATERIAL. IT IS THE RESPONSIBILITY OF MANUFACTURERS TO
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COMPLY WITH FCC CLASS B EMISSIONS REQUIREMENTS.
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1998 Compaq Computer Corporation
All rights reserved. Printed in the USA
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Product names mentioned in this document may be trademarks and/or registered trademarks of other companies.
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Technical Reference Guide
for
Compaq Deskpro EN Series of Personal Computers, Desktop and Minitower Form Factors
Third Edition - September 1998
Document Number DSK-113C/0498
Compaq Deskpro EN Series of Personal Computers
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TABLE OF CONTENTS
CHAPTER 1 INTRODUCTION.............................................................................................................
1.1
1.1.1
1.1.2
1.2
1.2.1
1.2.2
1.2.3
1.2.4
1.2.5
ABOUT THIS GUIDE ........................................................................................................... 1-1
USING THIS GUIDE ..................................................................................................... 1-1
ADDITIONAL INFORMATION SOURCES.................................................................. 1-1
NOTATIONAL CONVENTIONS.......................................................................................... 1-2
VALUES........................................................................................................................ 1-2
RANGES........................................................................................................................ 1-2
SIGNAL LABELS.......................................................................................................... 1-2
REGISTER NOTATION AND USAGE ......................................................................... 1-2
BIT NOTATION............................................................................................................ 1-2
COMMON ACRONYMS AND ABBREVIATIONS.............................................................. 1-3
1.3
CHAPTER 2 SYSTEM OVERVIEW.....................................................................................................
2.1
2.2
2.2.1
2.2.2
2.3
2.3.1
2.3.2
2.3.3
INTRODUCTION.................................................................................................................. 2-1
FEATURES AND OPTIONS................................................................................................. 2-2
STANDARD FEATURES.............................................................................................. 2-2
OPTIONS....................................................................................................................... 2-3
MECHANICAL DESIGN ...................................................................................................... 2-4
CABINET LAYOUTS.................................................................................................... 2-4
CHASSIS LAYOUTS..................................................................................................... 2-6
BOARD LAYOUTS....................................................................................................... 2-8
SYSTEM ARCHITECTURE................................................................................................ 2-10
PROCESSOR............................................................................................................... 2-12
SYSTEM MEMORY.................................................................................................... 2-13
SUPPORT CHIPSET.................................................................................................... 2-13
MASS STORAGE........................................................................................................ 2-13
SERIAL AND PARALLEL INTERFACES .................................................................. 2-14
UNIVERSAL SERIAL BUS INTERFACE ................................................................... 2-14
GRAPHICS SUBSYSTEM........................................................................................... 2-14
AUDIO SUBSYSTEM ................................................................................................. 2-14
SPECIFICATIONS.............................................................................................................. 2-15
2.4
2.4.1
2.4.2
2.4.3
2.4.4
2.4.5
2.4.6
2.4.7
2.4.8
2.5
CHAPTER 3 PROCESSOR/MEMORY SUBSYSTEM ........................................................................
3.1
3.2
3.2.1
3.2.2
3.2.3
3.2.4
INTRODUCTION.................................................................................................................. 3-1
PROCESSOR/MEMORY SUBSYSTEM .............................................................................. 3-2
PROCESSOR................................................................................................................. 3-3
PROCESSOR CHANGING/UPGRADING..................................................................... 3-5
SYSTEM MEMORY...................................................................................................... 3-6
SUBSYSTEM CONFIGURATION................................................................................. 3-9
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CHAPTER 4 SYSTEM SUPPORT.........................................................................................................
4.1
4.2
4.2.1
4.2.2
4.2.3
4.2.4
4.2.5
4.2.6
4.2.7
INTRODUCTION.................................................................................................................. 4-1
PCI BUS OVERVIEW........................................................................................................... 4-2
PCI CONNECTOR......................................................................................................... 4-3
PCI BUS MASTER ARBITRATION.............................................................................. 4-4
PCI BUS TRANSACTIONS........................................................................................... 4-5
OPTION ROM MAPPING ............................................................................................. 4-8
PCI INTERRUPT MAPPING......................................................................................... 4-9
PCI POWER MANAGEMENT SUPPORT..................................................................... 4-9
PCI CONFIGURATION............................................................................................... 4-10
AGP BUS OVERVIEW ....................................................................................................... 4-11
BUS TRANSACTIONS................................................................................................ 4-11
AGP CONFIGURATION ............................................................................................. 4-14
AGP CONNECTOR..................................................................................................... 4-15
ISA BUS OVERVIEW......................................................................................................... 4-16
ISA CONNECTOR ...................................................................................................... 4-17
ISA BUS TRANSACTIONS......................................................................................... 4-18
DIRECT MEMORY ACCESS...................................................................................... 4-20
INTERRUPTS.............................................................................................................. 4-23
INTERVAL TIMER..................................................................................................... 4-27
ISA CONFIGURATION............................................................................................... 4-27
SYSTEM CLOCK DISTRIBUTION.................................................................................... 4-28
REAL-TIME CLOCK AND CONFIGURATION MEMORY............................................... 4-29
I/O MAP AND REGISTER ACCESSING............................................................................ 4-46
SYSTEM I/O MAP ...................................................................................................... 4-46
GPIO UTILIZATION................................................................................................... 4-47
SYSTEM MANAGEMENT SUPPORT ............................................................................... 4-51
FLASH ROM WRITE PROTECT ................................................................................ 4-52
PASSWORD PROTECTION........................................................................................ 4-52
I/O SECURITY ............................................................................................................ 4-53
USER SECURITY........................................................................................................ 4-53
TEMPERATURE SENSING ........................................................................................ 4-54
SMART COVER LOCK............................................................................................... 4-55
SMART COVER REMOVAL SENSOR....................................................................... 4-55
POWER MANAGEMENT ........................................................................................... 4-56
4.3
4.3.1
4.3.2
4.3.3
4.4
4.4.1
4.4.2
4.4.3
4.4.4
4.4.5
4.4.6
4.5
4.6
4.7
4.7.1
4.7.2
4.8
4.8.1
4.8.2
4.8.3
4.8.4
4.8.5
4.8.6
4.8.7
4.8.8
CHAPTER 5 INPUT/OUTPUT INTERFACES.....................................................................................
5.1
5.2
5.2.1
5.2.2
5.3
5.3.1
5.3.2
5.4
INTRODUCTION.................................................................................................................. 5-1
ENHANCED IDE INTERFACE ............................................................................................ 5-1
IDE PROGRAMMING................................................................................................... 5-1
IDE CONNECTOR ........................................................................................................ 5-8
DISKETTE DRIVE INTERFACE.......................................................................................... 5-9
DISKETTE DRIVE PROGRAMMING ........................................................................ 5-10
DISKETTE DRIVE CONNECTOR.............................................................................. 5-13
SERIAL INTERFACES....................................................................................................... 5-14
RS-232 INTERFACE ................................................................................................... 5-14
SERIAL INTERFACE PROGRAMMING.................................................................... 5-15
5.4.1
5.4.2
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5.5
5.5.1
5.5.2
5.5.3
5.5.4
5.5.5
PARALLEL INTERFACE ................................................................................................... 5-20
STANDARD PARALLEL PORT MODE ..................................................................... 5-20
ENHANCED PARALLEL PORT MODE..................................................................... 5-21
EXTENDED CAPABILITIES PORT MODE ............................................................... 5-21
PARALLEL INTERFACE PROGRAMMING.............................................................. 5-22
PARALLEL INTERFACE CONNECTOR ................................................................... 5-26
KEYBOARD/POINTING DEVICE INTERFACE ............................................................... 5-27
KEYBOARD INTERFACE OPERATION ................................................................... 5-27
POINTING DEVICE INTERFACE OPERATION ....................................................... 5-29
KEYBOARD/POINTING DEVICE INTERFACE PROGRAMMING ......................... 5-29
KEYBOARD/POINTING DEVICE INTERFACE CONNECTOR................................ 5-33
UNIVERSAL SERIAL BUS INTERFACE........................................................................... 5-34
USB KEYBOARD CONSIDERATIONS...................................................................... 5-34
USB CONFIGURATION.............................................................................................. 5-34
USB CONTROL........................................................................................................... 5-35
USB CONNECTOR ..................................................................................................... 5-35
5.6
5.6.1
5.6.2
5.6.3
5.6.4
5.7
5.7.1
5.7.2
5.7.3
5.7.4
CHAPTER 6 AUDIO SUBSYSTEM ......................................................................................................
6.1
6.2
6.2.1
6.2.2
6.3
6.3.1
6.3.2
6.4
INTRODUCTION.................................................................................................................. 6-1
FUNCTIONAL DESCRIPTION............................................................................................. 6-2
PCM AUDIO PROCESSING.......................................................................................... 6-4
FM SYNTHESIS AUDIO PROCESSING....................................................................... 6-7
PROGRAMMING.................................................................................................................. 6-8
CONFIGURATION........................................................................................................ 6-8
CONTROL..................................................................................................................... 6-9
SPECIFICATIONS.............................................................................................................. 6-11
CHAPTER 7 POWER SUPPLY AND DISTRIBUTION.......................................................................
7.1
7.2
7.2.1
7.2.2
7.3
7.3.1
7.3.2
7.4
INTRODUCTION.................................................................................................................. 7-1
POWER SUPPLY ASSEMBLY/CONTROL .......................................................................... 7-1
POWER SUPPLY ASSEMBLY..................................................................................... 7-2
POWER CONTROL....................................................................................................... 7-3
POWER DISTRIBUTION...................................................................................................... 7-5
3.5/5/12 VDC DISTRIBUTION...................................................................................... 7-5
LOW VOLTAGE DISTRIBUTION................................................................................ 7-6
SIGNAL DISTRIBUTION..................................................................................................... 7-7
CHAPTER 8 BIOS ROM .......................................................................................................................
8.1
8.2
8.2.1
8.2.2
8.2.3
8.2.4
INTRODUCTION.................................................................................................................. 8-1
BOOT/RESET FUNCTIONS................................................................................................. 8-2
BOOT BLOCK............................................................................................................... 8-2
QUICKBOOT................................................................................................................. 8-2
SILENTBOOT ............................................................................................................... 8-2
RESET ........................................................................................................................... 8-2
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8.3
8.4
8.4.1
MEMORY DETECTION AND CONFIGURATION.............................................................. 8-3
DESKTOP MANAGEMENT SUPPORT ............................................................................... 8-4
SYSTEM ID................................................................................................................... 8-6
SYSTEM INFORMATION TABLE ............................................................................... 8-6
EDID RETRIEVE ........................................................................................................ 8-13
DRIVE FAULT PREDICTION..................................................................................... 8-13
SYSTEM MAP RETRIEVAL....................................................................................... 8-14
FLASH ROM FUNCTIONS ......................................................................................... 8-15
POWER BUTTON FUNCTIONS................................................................................. 8-15
ACCESSING CMOS.................................................................................................... 8-16
ACCESSING CMOS FEATURE BITS......................................................................... 8-16
8.4.2
8.4.3
8.4.4
8.4.5
8.4.6
8.4.7
8.4.8
8.4.9
8.4.10 SECURITY FUNCTIONS............................................................................................ 8-18
8.5
8.5.1
8.6
8.6.1
8.6.2
8.6.3
PNP SUPPORT.................................................................................................................... 8-19
SMBIOS....................................................................................................................... 8-20
POWER MANAGEMENT FUNCTIONS ............................................................................ 8-21
INDEPENDENT PM SUPPORT .................................................................................. 8-21
ACPI SUPPORT........................................................................................................... 8-21
APM SUPPORT ........................................................................................................... 8-22
USB LEGACY SUPPORT ................................................................................................... 8-24
BIOS UPGRADING............................................................................................................. 8-24
8.7
8.8
APPENDIX A ERROR MESSAGES AND CODES...............................................................................
A.1 INTRODUCTION................................................................................................................. A-1
A.2 POWER-ON MESSAGES..................................................................................................... A-1
A.3 BEEP/KEYBOARD LED CODES ........................................................................................ A-1
A.4 POWER-ON SELF TEST (POST) MESSAGES.................................................................... A-2
A.5 PROCESSOR ERROR MESSAGES (1XX XX
A.6 MEMORY ERROR MESSAGES (2XX XX)........................................................................... A-4
A.7 KEYBOARD ERROR MESSAGES (30X-XX) ....................................................................... A-4
A.8 PRINTER ERROR MESSAGES (4XX XX) ............................................................................ A-5
A.9 VIDEO (GRAPHICS) ERROR MESSAGES (5XX XX
-
) ...................................................................... A-3
-
-
-
).......................................................... A-5
) ......................................................... A-6
A.10
A.11
A.12
A.13
A.14
A.15
A.16
A.17
A.18
A.19
A.20
A.21
DISKETTE DRIVE ERROR MESSAGES (6XX XX
SERIAL INTERFACE ERROR MESSAGES (11XX XX
MODEM COMMUNICATIONS ERROR MESSAGES (12XX XX
-
-
) ................................................... A-6
).................................... A-7
-
HARD DRIVE ERROR MESSAGES (17XX XX
-
) ............................................................... A-8
) ............................................................... A-9
HARD DRIVE ERROR MESSAGES (19XX XX
-
VIDEO (GRAPHICS) ERROR MESSAGES (24XX XX
AUDIO ERROR MESSAGES (3206-XX)......................................................................... A-10
NETWORK INTERFACE ERROR MESSAGES (60XX XX) ........................................... A-10
SCSI INTERFACE ERROR MESSAGES (65XX XX, 66XX XX, 67XX XX) ....................... A-11
POINTING DEVICE INTERFACE ERROR MESSAGES (8601-XX).............................. A-11
CEMM PRIVILEDGED OPS ERROR MESSAGES........................................................ A-12
CEMM EXCEPTION ERROR MESSAGES ................................................................... A-12
-
) .................................................... A-9
-
-
-
-
APPENDIX B ASCII CHARACTER SET .............................................................................................
B.1 INTRODUCTION..................................................................................................................B-1
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APPENDIX C KEYBOARD...................................................................................................................
C.1
C.2
INTRODUCTION..................................................................................................................C-1
KEYSTROKE PROCESSING................................................................................................C-2
C.2.1
C.2.2
C.2.3
C.2.4
C.2.5
TRANSMISSIONS TO THE SYSTEM ..........................................................................C-3
KEYBOARD LAYOUTS ...............................................................................................C-4
KEYS.............................................................................................................................C-6
KEYBOARD COMMANDS...........................................................................................C-9
SCAN CODES ...............................................................................................................C-9
APPENDIX D COMPAQ 10/100 TX PCI INTEL WOL UTP CONTROLLER CARD.......................
D.1 INTRODUCTION................................................................................................................. D-1
D.2 FUNCTIONAL DESCRIPTION............................................................................................ D-2
D.2.1
D.2.2
D.2.3
D.2.4
STATUS INDICATORS................................................................................................ D-2
CARD POWER AND CLOCK...................................................................................... D-3
82558 CONTROLLER .................................................................................................. D-3
POWER MANAGEMENT SUPPORT........................................................................... D-4
D.3 CONFIGURATION/CONTROL ........................................................................................... D-5
D.4 RJ-45 CONNECTOR............................................................................................................ D-5
D.5 SPECIFICATIONS............................................................................................................... D-5
APPENDIX E WIDE ULTRA SCSI HOST ADAPTER ........................................................................
E.1
E.2
E.3
INTRODUCTION..................................................................................................................E-1
FUNCTIONAL DESCRIPTION.............................................................................................E-2
SCSI ADAPTER PROGRAMMING ......................................................................................E-3
E.3.1
E.3.2
E.4
E.5
E.6
SCSI ADAPTER CONFIGURATION ............................................................................E-3
SCSI ADAPTER CONTROL .........................................................................................E-3
SPECIFCATIONS .................................................................................................................E-3
USER GUIDELINES .............................................................................................................E-4
SCSI CONNECTORS ............................................................................................................E-5
APPENDIX F ATI RAGE PRO AGP 1X/2X GRAPHICS CARDS.......................................................
F.1
F.2
F.2.1
F.3
F.4
F.4.1
F.4.2
F.5
F.6
F.6.1
INTRODUCTION..................................................................................................................F-1
FUNCTIONAL DESCRIPTION.............................................................................................F-2
ATI RAGE PRO TURBO AGP GRAPHICS CONTROLLER .........................................F-3
DISPLAY MODES................................................................................................................F-4
PROGRAMMING..................................................................................................................F-5
CONFIGURATION........................................................................................................F-5
CONTROL.....................................................................................................................F-5
MONITOR POWER MANAGEMENT CONTROL ...............................................................F-6
CONNECTORS.....................................................................................................................F-6
MEMORY EXPANSION CONNECTOR.......................................................................F-6
MONITOR CONNECTOR.............................................................................................F-7
ATI MULTIMEDIA CHANNEL CONNECTOR............................................................F-8
F.6.2
F.6.3
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LIST OF FIGURES
FIGURE 2–1. COMPAQ DESKPRO EN PERSONAL COMPUTER WITH MONITOR ........................................... 2-1
FIGURE 2–2. CABINET LAYOUTS, FRONT VIEW...................................................................................... 2-4
FIGURE 2–3. CABINET LAYOUTS, REAR VIEW........................................................................................ 2-5
FIGURE 2–4. DESKTOP CHASSIS LAYOUT, TOP VIEW.............................................................................. 2-6
FIGURE 2–5. MINITOWER CHASSIS LAYOUT, LEFT SIDE VIEW ................................................................ 2-7
FIGURE 2–6. SYSTEM BOARD CONNECTOR AND SWITCH LOCATIONS ...................................................... 2-8
FIGURE 2–7. BACKLPANE BOARD CONNECTOR, HEADER AND SWITCH LOCATIONS ................................ 2-9
,
FIGURE 2–8. SYSTEM ARCHITECTURE, BLOCK DIAGRAM...................................................................... 2-11
FIGURE 2–9. PROCESSOR PACKAGE COMPARISON ................................................................................ 2-12
FIGURE 3–1. PROCESSOR/MEMORY SUBSYSTEM ARCHITECTURE ............................................................ 3-2
FIGURE 3–2. PENTIUM II PROCESSOR NTERNAL
I
ARCHITECTURE ............................................................ 3-3
ARCHITECTURE............................................................... 3-4
FIGURE 3–3. CELERON PROCESSOR NTERNAL
I
FIGURE 3–4. SYSTEM MEMORY MAP..................................................................................................... 3-8
FIGURE 4–1. PCI BUS DEVICES AND FUNCTIONS.................................................................................... 4-2
FIGURE 4–2. PCI BUS CONNECTOR (32-BIT TYPE)................................................................................. 4-3
FIGURE 4–3. TYPE 0 CONFIGURATION CYCLE........................................................................................ 4-6
FIGURE 4–4. PCI CONFIGURATION SPACE MAP...................................................................................... 4-7
FIGURE 4–5. AGP 1X DATA TRANSFER (PEAK TRANSFER RATE: 266 MB/S) ........................................ 4-12
FIGURE 4–6. AGP 2X DATA TRANSFER (PEAK TRANSFER RATE: 532 MB/S) ........................................ 4-13
FIGURE 4–7. AGP BUS CONNECTOR ................................................................................................... 4-15
FIGURE 4–8. ISA BUS BLOCK DIAGRAM............................................................................................. 4-16
FIGURE 4–9. ISA EXPANSION CONNECTOR.......................................................................................... 4-17
FIGURE 4–10. MASKABLE NTERRUPT
I
PROCESSING, BLOCK DIAGRAM.................................................. 4-23
FIGURE 4–11. CONFIGURATION MEMORY MAP .................................................................................... 4-29
FIGURE 5–1. 40-PIN IDE CONNECTOR. ................................................................................................. 5-8
FIGURE 5–2. 34-PIN DISKETTE DRIVE CONNECTOR.............................................................................. 5-13
FIGURE 5–3. SERIAL NTERFACES
FIGURE 5–4. SERIAL NTERFACE
FIGURE 5–5. PARALLEL NTERFACE
FIGURE 5–6. 8042-TO-KEYBOARD TRANSMISSION OF CODE EDH, TIMING DIAGRAM............................ 5-27
FIGURE 5–7. KEYBOARD OR POINTING DEVICE NTERFACE CONNECTOR............................................... 5-33
FIGURE 5–8. UNIVERSAL SERIAL BUS CONNECTOR ONE OF TWO AS VIEWED FROM REAR OF CHASSIS)..... 5-35
I
BLOCK DIAGRAM ............................................................................. 5-14
I
CONNECTOR (MALE DB-9 AS VIEWED FROM REAR OF CHASSIS) ........... 5-14
I
CONNECTOR (FEMALE DB-25 AS VIEWED FROM REAR OF CHASSIS).. 5-26
I
(
FIGURE 6–1. AUDIO SUBSYSTEM BLOCK DIAGRAM ................................................................................ 6-3
FIGURE 6–2. ANALOG SIGNAL SAMPLING/QUANTIZING .......................................................................... 6-4
FIGURE 6–3. DAC OPERATION ............................................................................................................. 6-5
FIGURE 6–4. AUDIO SUBSYSTEM TO
FIGURE 6–5. FM SYNTHESIS PATCH...................................................................................................... 6-7
FIGURE 6–6. AUDIO CAR TO-ISA BUS FM AUDIO DATA FORMAT.......................................................... 6-7
-
-ISA BUS PCM AUDIO DATA FORMATS / BYTE ORDERING .............. 6-6
-
FIGURE 7–1. POWER DISTRIBUTION AND CONTROL, BLOCK DIAGRAM.................................................... 7-1
FIGURE 7–2. POWER CABLE DIAGRAM .................................................................................................. 7-5
FIGURE 7–3. LOW VOLTAGE SUPPLY, BLOCK DIAGRAM......................................................................... 7-6
FIGURE 7–4. SIGNAL DISTRIBUTION DIAGRAM....................................................................................... 7-7
FIGURE 7–5. BACKPLANE HEADER PINOUTS........................................................................................... 7-8
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FIGURE C–1. KEYSTROKE PROCESSING ELEMENTS, BLOCK DIAGRAM ....................................................C-2
FIGURE C–2. KEYBOARD-TO-SYSTEM TRANSMISSION OF CODE 58H, TIMING DIAGRAM..........................C-3
FIGURE C–3. U.S. ENGLISH (101-KEY) KEYBOARD KEY POSITIONS.......................................................C-4
FIGURE C–4. NATIONAL (102-KEY) KEYBOARD KEY POSITIONS............................................................C-4
FIGURE C–5. U.S. ENGLISH WINDOWS (101W-KEY) KEYBOARD KEY POSITIONS ...................................C-5
FIGURE C–6. NATIONAL WINDOWS (102W-KEY) KEYBOARD KEY POSITIONS ........................................C-5
FIGURE D–1. COMPAQ 10/100 TX WOL CONTROLLER CARD LAYOUT (PCA# 323550-001) ................. D-1
FIGURE D–2. COMPAQ 10/100 TX PCI INTEL WOL UTP CONTROLLER CARD BLOCK DIAGRAM ........... D-2
FIGURE D–3. 82558 CONTROLLER NTERNAL ARCHITECTURE............................................................... D-3
I
FIGURE D–4. ETHERNET TPE CONNECTOR (RJ-45, VIEWED FROM CARD EDGE) ..................................... D-5
FIGURE E–1. WIDE ULTRA SCSI HOST ADAPTER CARD LAYOUT ...........................................................E-1
FIGURE E–2. ADAPTEC AHA-2940U ULTRA SCSI ADAPTER CARD BLOCK DIAGRAM.............................E-2
FIGURE E–3. ULTRA SCSI CONNECTOR (50-PIN AS SEEN FROM REAR OF CARD
,
)........................................E-5
).................................E-6
FIGURE E–4. WIDE ULTRA SCSI CONNECTOR (68-PIN AS SEEN FROM TOP OF CARD
,
FIGURE F–1. ATI RAGE PRO AGP GRAPHICS CARD LAYOUT (NLX VERSION SHOWN) ...........................F-1
FIGURE F–2. ATI RAGE PRO AGP GRAPHICS CARD BLOCK DIAGRAM .................................................F-2
FIGURE F–3. ATI 3DRAGE PRO GRAPHICS CONTROLLER NTERNAL ARCHITECTURE...............................F-3
I
FIGURE F–4. VGA MONITOR CONNECTOR, (FEMALE DB-15, AS VIEWED FROM REAR). .............................F-7
FIGURE F–5. AMC CONNECTOR (40-PIN HEADER P1) ...........................................................................F-8
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LIST OF TABLES
TABLE 1–1. ACRONYMS AND ABBREVIATIONS....................................................................................... 1-3
TABLE 2–1. MODEL DIFFERENCES....................................................................................................... 2-10
TABLE 2–2. SUPPORT CHIPSETS .......................................................................................................... 2-13
TABLE 2–3. GRAPHICS SUBSYSTEM COMPARISON ................................................................................ 2-14
TABLE 2–4. ENVIRONMENTAL SPECIFICATIONS.................................................................................... 2-15
TABLE 2–5. ELECTRICAL SPECIFICATIONS ........................................................................................... 2-15
TABLE 2–6. PHYSICAL SPECIFICATIONS............................................................................................... 2-15
TABLE 2–7. DISKETTE DRIVE SPECIFICATIONS..................................................................................... 2-16
TABLE 2–8. 24X CD-ROM DRIVE SPECIFICATIONS.............................................................................. 2-16
TABLE 2–9. HARD DRIVE SPECIFICATIONS........................................................................................... 2-17
TABLE 3–1. PROCESSOR COMPARISON................................................................................................... 3-3
TABLE 3–2. BUS/CORE SPEED SWITCH SETTINGS................................................................................... 3-5
TABLE 3–3. SPD ADDRESS MAP (SDRAM DIMM)............................................................................... 3-7
TABLE 3–4. HOST/PCI BRIDGE CONFIGURATION REGISTERS (443BX, FUNCTION 0) ............................... 3-9
TABLE 4–1. PCI BUS CONNECTOR PINOUT............................................................................................ 4-3
TABLE 4–2. PCI BUS MASTERING DEVICES ........................................................................................... 4-4
TABLE 4–3. PCI DEVICE CONFIGURATION ACCESS ................................................................................ 4-6
TABLE 4–4. PCI FUNCTION CONFIGURATION ACCES.............................................................................. 4-7
TABLE 4–5. PCI DEVICE DENTIFICATION ............................................................................................. 4-8
I
TABLE 4–6. PCI/ISA BRIDGE CONFIGURATION REGISTERS (82371, FUNCTION 0)................................. 4-10
TABLE 4–7. PCI/AGP BRIDGE CONFIGURATION REGISTERS (82371, FUNCTION 1)............................... 4-14
TABLE 4–8. AGP BUS CONNECTOR PINOUT ....................................................................................... 4-15
TABLE 4–9. ISA EXPANSION CONNECTOR PINOUT............................................................................. 4-17
TABLE 4–10. DEFAULT DMA CHANNEL ASSIGNMENTS ....................................................................... 4-20
TABLE 4–11. DMA PAGE REGISTER ADDRESSES ................................................................................. 4-21
TABLE 4–12. DMA CONTROLLER REGISTERS...................................................................................... 4-22
TABLE 4–13. MASKABLE NTERRUPT
I
PRIORITIES AND ASSIGNMENTS.................................................... 4-24
CONTROL REGISTERS.................................................................. 4-24
TABLE 4–14. MASKABLE NTERRUPT
I
TABLE 4–15. INTERVAL TIMER FUNCTIONS ......................................................................................... 4-27
TABLE 4–16. INTERVAL TIMER CONTROL REGISTERS........................................................................... 4-27
TABLE 4–17. CLOCK GENERATION AND DISTRIBUTION ........................................................................ 4-28
TABLE 4–18. CONFIGURATION MEMORY (CMOS) MAP....................................................................... 4-30
TABLE 4–19. SYSTEM I/O MAP........................................................................................................... 4-46
TABLE 4–20. 82371 SOUTH BRIDGE GENERAL PURPOSE NPUT PORT UTILIZATION ............................... 4-47
I
TABLE 4–21. 82371 SOUTH BRIDGE GENERAL PURPOSE OUTPUT PORT UTILIZATION ............................ 4-48
TABLE 4–22. 87307 I/O CONTROLLER PNP STANDARD CONTROL REGISTERS ...................................... 4-49
TABLE 4–23. SYSTEM MANAGEMENT CONTROL REGISTERS................................................................. 4-51
TABLE 5–1. IDE PCI CONFIGURATION REGISTERS .............................................................................. 5-2
TABLE 5–2. IDE BUS MASTER CONTROL REGISTERS ........................................................................... 5-2
TABLE 5–3. IDE ATA CONTROL REGISTERS....................................................................................... 5-3
TABLE 5–4. IDE CONTROLLER COMMANDS ........................................................................................ 5-6
TABLE 5–5. 40-PIN IDE CONNECTOR PINOUT ...................................................................................... 5-8
TABLE 5–6. DISKETTE DRIVE CONTROLLER CONFIGURATION REGISTERS ............................................ 5-10
TABLE 5–7. DISKETTE DRIVE CONTROLLER REGISTERS ...................................................................... 5-11
TABLE 5–8. 34-PIN DISKETTE DRIVE CONNECTOR PINOUT.................................................................. 5-13
x
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TABLE 5–9. DB-9 SERIAL CONNECTOR PINOUT.................................................................................. 5-14
TABLE 5–10. SERIAL NTERFACE
TABLE 5–11. SERIAL NTERFACE
TABLE 5–12. PARALLEL NTERFACE
TABLE 5–13. PARALLEL NTERFACE
I
I
CONFIGURATION REGISTERS.............................................................. 5-15
CONTROL REGISTERS........................................................................ 5-16
I
I
CONFIGURATION REGISTERS......................................................... 5-22
CONTROL REGISTERS ................................................................... 5-23
TABLE 5–14. DB-25 PARALLEL CONNECTOR PINOUT .......................................................................... 5-26
TABLE 5–15. 8042-TO-KEYBOARD COMMANDS .................................................................................. 5-28
TABLE 5–16. KEYBOARD/MOUSE NTERFACE CONFIGURATION REGISTERS ........................................... 5-29
I
TABLE 5–17. CPU COMMANDS TO THE 8042...................................................................................... 5-31
TABLE 5–18. KEYBOARD/POINTING DEVICE CONNECTOR PINOUT........................................................ 5-33
TABLE 5–19. USB INTERFACE CONFIGURATION REGISTERS................................................................. 5-34
TABLE 5–20. USB CONTROL REGISTERS............................................................................................. 5-35
TABLE 5–21. USB CONNECTOR PINOUT.............................................................................................. 5-35
TABLE 6–1. AUDIO MODE DIFFERENCES ............................................................................................... 6-6
TABLE 6–2. AUDIO SUBSYSTEM I/O MAP .............................................................................................. 6-9
TABLE 6–3. COMPATIBILITY MODE AUDIO MIXER CONTROL REGISTER MAPPING................................... 6-9
TABLE 6–4. EXTENDED MODE AUDIO MIXER CONTROL REGISTER MAPPING ........................................ 6-10
TABLE 6–5. FM SYNTHESIZER CONTROL REGISTER MAPPING.............................................................. 6-10
TABLE 6–6. AUDIO SUBSYSTEM SPECIFICATIONS ................................................................................. 6-11
TABLE 7–1. POWER SUPPLY ASSEMBLY SPECIFICATIONS........................................................................ 7-2
TABLE 8–1. DESKTOP MANAGEMENT FUNCTIONS (INT15) .................................................................... 8-4
TABLE 8–1. PNP BIOS FUNCTIONS..................................................................................................... 8-19
TABLE 8–2. APM BIOS FUNCTIONS (INT15) ..................................................................................... 8-23
TABLE A–1. POWER-ON MESSAGES ..................................................................................................... A-1
TABLE A–2. BEEP/KEYBOARD LED CODES.......................................................................................... A-1
TABLE A–3. POWER-ON SELF TEST (POST) MESSAGES........................................................................ A-2
TABLE A–4. PROCESSOR ERROR MESSAGES ......................................................................................... A-3
TABLE A–5. MEMORY ERROR MESSAGES............................................................................................. A-4
TABLE A–6. KEYBOARD ERROR MESSAGES.......................................................................................... A-4
TABLE A–7. PRINTER ERROR MESSAGES.............................................................................................. A-5
TABLE A–8. VIDEO (GRAPHICS) ERROR MESSAGES .............................................................................. A-5
TABLE A–9. DISKETTE DRIVE ERROR MESSAGES.................................................................................. A-6
TABLE A–10. SERIAL NTERFACE
I
ERROR MESSAGES ............................................................................. A-6
ERROR MESSAGES............................................................................. A-7
TABLE A–11. SERIAL NTERFACE
I
TABLE A–12. HARD DRIVE ERROR MESSAGES...................................................................................... A-8
TABLE A–13. HARD DRIVE ERROR MESSAGES...................................................................................... A-9
TABLE A–14. HARD DRIVE MESSAGES ................................................................................................. A-9
TABLE A–15. AUDIO ERROR MESSAGES............................................................................................. A-10
TABLE A–16. NETWORK NTERFACE
TABLE A–17. SCSI INTERFACE ERROR MESSAGES ............................................................................. A-11
TABLE A–18. POINTING DEVICE NTERFACE ERROR MESSAGES........................................................... A-11
I
ERROR MESSAGES ...................................................................... A-10
I
TABLE A–19. CEMM PRIVILEGED OPS ERROR MESSAGES.................................................................. A-12
TABLE A–20. CEMM EXCEPTION ERROR MESSAGES ......................................................................... A-12
TABLE B–1. ASCII CHARACTER SET ....................................................................................................B-1
T
ABLE C–1. KEYBOARD TO
-
-SYSTEM COMMANDS .................................................................................C-9
TABLE C–2. KEYBOARD SCAN CODES.................................................................................................C-10
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TABLE D–1. OPERATING SPECIFICATIONS............................................................................................. D-5
TABLE E–1. ULTRA SCSI HOST ADAPTER CARD CONTROL REGISTER MAPPING ......................................E-3
TABLE E–2. ULTRA SCSI HOST ADAPTER CARD SPECIFICATIONS...........................................................E-3
TABLE E–3. WIDE ULTRA SCSI ADAPTER CARD TYPICAL CONFIGURATION ............................................E-4
TABLE E–4. SCSI CONNECTOR PINOUT ................................................................................................E-5
TABLE E–5. WIDE ULTRA SCSI CONNECTOR PINOUT............................................................................E-6
TABLE F–1. 2D GRAPHICS DISPLAY MODES (W/SGRAM)......................................................................F-4
TABLE F–2. 3D GRAPHICS DISPLAY MODES ..........................................................................................F-4
TABLE F–3. ATI RAGE PRO PCI CONFIGURATION SPACE REGISTERS ..................................................F-5
TABLE F–4. STANDARD VGA MODE I/O MAPPING................................................................................F-5
TABLE F–5. MONITOR POWER MANAGEMENT CONDITIONS....................................................................F-6
TABLE F–6. DB-15 MONITOR CONNECTOR PINOUT...............................................................................F-7
TABLE F–7. MULTIMEDIA NTERFACE CONNECTOR PINOUT ...................................................................F-8
I
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Technical Reference Guide
Chapter 1
INTRODUCTION
1.1
ABOUT THIS GUIDE
This guide provides technical information about the Compaq Deskpro EN Series of Personal
Computers in desktop and minitower form factors. This document includes information
regarding system design, function, and features that can be used by programmers, engineers,
technicians, and system administrators.
This and other support documentation is available online and can be downloaded in .PDF format
from the following WEB site: http://www.compaq.com/support/index.htm.
1.1.1 USING THIS GUIDE
This guide consists of chapters and appendices. The chapters primarily describe the hardware
and firmware elements contained within the chassis and specifically deal with the system board
and the power supply assembly. The appendices contain general information about standard
peripheral devices such as the keyboard as well as separate audio or other interface cards, as well
as other general information in tabular format.
1.1.2 ADDITIONAL INFORMATION SOURCES
This guide does not describe in detail other manufacturer’s components used in the product
covered. For more information on individual commercial-off-the-shelf (COTS) components refer
to the indicated manufacturers’ documentation. The products covered by this guide use
architecture based on industry-standard specifications that can be referenced for detailed
information.
Hardcopy documentation sources:
♦
♦
The Lotus/Intel/Microsoft Expanded Memory Specification, Ver. 4.0
PCI Local Bus Specification Revision 2.1
Online information sources:
♦
♦
♦
♦
Compaq Computer Corporation: http://www.compaq.com
Intel Corporation: http://www.intel.com
National Semiconductor Incorporated: http://www.national.com
ATI Incorporated: http://www.atitech.com
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Chapter 1 Introduction
1.2
NOTATIONAL CONVENTIONS
1.2.1 VALUES
Hexadecimal values are indicated by the letter “h” following an alpha-numerical value. Binary
values are indicated by the letter “b” following a value of ones and zeros. Memory addresses
expressed as “SSSS:OOOO” (SSSS = 16-bit segment, OOOO = 16-bit offset) can be assumed as
a hexadecimal value. Values that have no succeeding letter can be assumed to be decimal.
1.2.2 RANGES
Ranges or limits for a parameter are shown as a pair of values separated by two dots:
Example: Bits <7..4> = bits 7, 6, 5, and 4.
1.2.3 SIGNAL LABELS
Signal names are indicated using abbreviations, acronyms, or, if possible, the full signal name in
all capital letters. Signals that are meant to be active low are indicated with a dash immediately
following the name.
1.2.4 REGISTER NOTATION AND USAGE
This guide uses standard Intel naming conventions in discussing the microprocessor’s (CPU)
internal registers. Registers that are accessed through programmable I/O using an indexing
scheme are indicated using the following format:
03C5.17h
Index port
Data port
In the example above, register 03C5.17h is accessed by writing the index port value 17h to the
index address (03C4h), followed by a write to or a read from port 03C5h.
1.2.5 BIT NOTATION
Bit values are labeled with bit <0> representing the least-significant bit (LSb) and bit <7>
representing the most-significant bit (MSb) of a byte. Bytes, words, double words, and quad
words are typically shown with most-significant portions on the left or top and the least-
significant portions on the right or bottom respectively.
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1.3
COMMON ACRONYMS AND ABBREVIATIONS
Table 1-1 lists the acronyms and abbreviations used in this guide.
Table 1-1.
Acronyms and Abbreviations
Acronym/Abbreviation
A
Description
ampere
AC
alternating current
ACPI
A/D
Advanced Configuration and Power Interface
analog-to-digital
AGP
API
APM
ASIC
AT
Accelerated graphics port
application programming interface
advanced power management
application-specific integrated circuit
1. attention (commands) 2. 286-based PC architecture
AT attachment (mode)
audio-video interleaved
Advanced VGA
binary-coded decimal
basic input/output system
second/new revision
bit block transfer
Bayonet Neill-Concelman (connector)
bits per second
ATA
AVI
AVGA
BCD
BIOS
bis
BitBLT
BNC
bps or b/s
BSP
Bootstrap processor
BTO
CAS
CD
Built to order
column address strobe
compact disk
CD-ROM
CDS
CF
compact disk read-only memory
compct disk system
carry flag
CGA
Ch
color graphics adapter
channel
CLUT
cm
color look-up table (pallete)
centimeter
CMC
CMOS
Cntlr
codec
CPQ
CPU
CRT
CSM
CTO
DAA
DAC
db
cache/memory controller
complimentary metal-oxide semiconductor (configuration memory)
controller
compressor/decompressor
Compaq
central processing unit
cathode ray tube
Compaq system management / Compaq server management
Configure to order
direct access arrangement
digital-to-analog converter
decibel
DC
direct current
DCH
DDC
DF
DOS compatibility hole
Display Data Channel
direction flag
Continued
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Chapter 1 Introduction
Table 1-1. Acronyms and Abbreviations Continued
Acronym/Abbreviation
Description
DIMM
DIN
DIP
dual inline memory module
Deutche IndustriNorm (connector standard)
dual inline package
DMA
DMI
dpi
direct memory access
Desktop management interface
dots per inch
DRAM
DRQ
EDID
EDO
EEPROM
EGA
EIA
EISA
EPP
EIDE
ESCD
EV
dynamic random access memory
data request
extended display identification data
extended data out (RAM type)
electrically eraseable PROM
enhanced graphics adapter
Electronic Industry Association
extended ISA
enhanced parallel port
enhanced IDE
Extended System Configuration Data (format)
Environmental Variable (data)
Exchangeable Card Architecture
first in / first out
ExCA
FIFO
FL
flag (register)
FM
frequency modulation
fast page mode (RAM type)
Floating point unit (numeric or math coprocessor)
foot
FPM
FPU
ft
GB
gigabyte
GND
GPIO
GPOC
GART
GUI
h
ground
general purpose I/O
general purpose open-collector
Graphics address re-mapping table
graphics user interface
hexadecimal
HW
hardware
hex
hexadecimal
Hz
hertz
IDE
IEEE
IF
integrated drive element
Institute of Electrical and Electronic Engineers
interrupt flag
I/F
interface
in
inch
INT
interrupt
I/O
input/output
IPL
initial program loader
InfraRed Data Association
interrupt request
industry standard architecture
Joint Electron Device Engineering Council
kilobits / kilobytes (x 1024 bits / x 1024 bytes)
kilobits per second
IrDA
IRQ
ISA
JEDEC
Kb / KB
Kb/s
kg
kilogram
KHz
kv
kilohertz
kilovolt
Continued
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Table 1-1. Acronyms and Abbreviations Continued
Acronym/Abbreviation
Description
lb
pound
LAN
local area network
LCD
liquid crystal display
LED
light-emitting diode
LIF
LSI
LSb / LSB
LUN
low insertion force (socket)
large scale integration
least significant bit / least significant byte
logical unit (SCSI)
MMX
MPEG
ms
multimedia extensions
Motion Picture Experts Group
millisecond
MSb / MSB
mux
most significant bit / most significant byte
multiplex
MVA
MVW
n
motion video acceleration
motion video window
variable parameter/value
network interface card/controller
nickel cadmium
nickel-metal hydride
non-maskable interrupt
nanosecond
NIC
NiCad
NiMH
NMI
ns
NT
nested task flag
NTSC
NVRAM
OEM
OS
National Television Standards Committee
non-volatile random access memory
original equipment manufacturer
operating system
PAL
PC
1. programmable array logic 2. phase altering line
personal computer
PCI
peripheral component interconnect
pulse code modulation
Personal Computer Memory Card International Association
parity flag
PCM
PCMCIA
PF
PIN
PIO
personal identification number
Programmed I/O
POST
PROM
PTR
power-on self test
programmable read-only memory
pointer
RAM
RAS
rcvr
random access memory
row address strobe
receiver
RF
resume flag
RGB
RH
red/green/blue (monitor input)
Relative humidity
RMS
ROM
RPM
RTC
root mean square
read-only memory
revolutions per minute
real time clock
R/W
read/write
Continued
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Chapter 1 Introduction
Table 1-1. Acronyms and Abbreviations Continued
Acronym/Abbreviation
Description
SCSI
SDRAM
SEC
SECAM
SF
small computer system interface
Synchronous Dynamic RAM
Single Edge-Connector
sequential colour avec memoire (sequential color with memory)
sign flag
SGRAM
SIMM
SIT
SMART
SMI
SMM
SMRAM
SPD
SPP
SRAM
STN
SVGA
SW
Synchronous Graphics RAM
single in-line memory module
system information table
Self Monitor Analysis Report Technology
system management interrupt
system management mode
system management RAM
serial presence detect
standard parallel port
static RAM
super twist pneumatic
super VGA
software
TAD
TAM
TCP
TF
telephone answering device
telephone answering machine
tape carrier package
trap flag
TFT
thin-film transistor
TIA
TPE
TPI
Telecommunications Information Administration
twisted pair ethernet
track per inch
TTl
TV
transistor-transistor logic
television
TX
transmit
UART
UDMA
us / µs
USB
UTP
V
universal asynchronous receiver/transmitter
Ultra DMA
microsecond
Universal Serial Bus
unshielded twisted pair
volt
VESA
VGA
vib
Video Electronic Standards Association
video graphics adapter
vibrato
VLSI
VRAM
W
very large scale integration
Video RAM
watt
WOL
WRAM
ZF
Wake on LAN
Windows RAM
zero flag
ZIF
zero insertion force (socket)
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Technical Reference Guide
Chapter 2
SYSTEM OVERVIEW
INTRODUCTION
2.1
The Compaq Deskpro EN Series of desktop and minitower Personal Computers (Figure 2-1)
delivers an outstanding combination of manageability, serviceability, and consistency for
enterprise environments. Based on Intel Pentium II and Celeron processors, the Deskpro EN
Series emphasizes performance and industry compatibility. These models feature architectures
incorporating the PCI, AGP, and ISA buses. All models are easily upgradable and expandable to
keep pace with the needs of the office enterprise.
Figure 2–1.
Compaq Deskpro EN Desktop Personal Computers with Monitor
This chapter includes the following topics:
♦
♦
♦
♦
Features and options (2.2)
Mechanical design (2.3)
System architecture (2.4)
Specifications (2.5)
page 2-2
page 2-4
page 2-8
page 2-13
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Chapter 2 System Overview
2.2
FEATURES AND OPTIONS
This section describes the standard features and available options.
2.2.1 STANDARD FEATURES
The following standard features are included on all models:
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
Pentium II or Celeron processor
High-performance 2D/3D AGP graphics card
Embedded 16-bit full-duplex audio with Compaq Premier Sound
3.5 inch, 1.44-MB diskette drive
Extended IDE controller support for up to four IDE drives
Hard drive fault prediction
Two serial interfaces
Parallel interface
Two universal serial bus ports
Two PCI slots
Two combo PCI/ISA slots
10/100 NIC card
Compaq Enhanced keyboard w/Windows support
Mouse
APM 1.2 power management support
Plug ’n Play compatible (with ESCD support)
Intelligent Manageability support
Energy Star compliant
Security features including:
•
•
•
•
•
•
•
•
•
Flash ROM Boot Block
Diskette drive disable, boot disable, write protect
Power-on password
Administrator password
QuickLock/QuickBlank
Smart Cover lock
Smart Cover removal sense
Serial port disable
Parallel port disable
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2.2.2 OPTIONS
The following items are available as options for all models and may be included in the standard
configuration of some models:
♦
♦
System Memory:
16-MB DIMM (ECC and non-ECC)
32-MB DIMM (ECC and non-ECC)
64-MB DIMM (ECC and nonECC)
128-MB DIMM (ECC and non-ECC)
Hard drives/controllers: 3.2 GB UATA
4.3 GB Wide Ultra SCSI
9.1 GB Wide Ultra SCSI
Wide Ultra SCSI PCI controller
6.4 GB UATA
♦
♦
Removeable media drives: 1.44 MB diskette drive
32x CD-ROM drive
PS-120 Power Drive
Communications cards: Compaq 10/100TX PCI Intel with WOL UTP
Netelligent 10/100, TX PCI UTP TLAN
3COM Fast EtherLink XL 10/100TX PCI
Compaq Netelligent 56.6 Baud ISA Modem
♦
Graphics cards/memory: ATI RAGE PRO Turbo AGP card
ATI RAGE PRO Turbo AGP 2X card
4-MB SGRAM SODIMM (for RAGE PRO AGP 2X card)
Matrox MGA-G100A card
Matrox Millennium G200-SD card
8-MB SDRAM SODIMM (for Millennium G200-SD card)
Compaq Deskpro Computers are easily upgraded and enhanced with peripheral devices designed
to meet PCI and ISA standards. The Compaq Deskpro Personal Computers are compatible with
peripherals designed for Plug ’n Play operation.
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Chapter 2 System Overview
2.3
MECHANICAL DESIGN
The Compaq Deskpro EN Series uses a desktop form factor. This section illustrates the
mechanical particulars of the bezel, chassis, and major board assemblies.
2.3.1 CABINET LAYOUTS
1
2
3
4
5
1
2
3
5
6
7
6
7
Desktop
Minitower
Item
Function
1.44 MB Diskette Drive (5.25” drive bay)
CD-ROM Drive (CDS models) (5.25“ drive bay)
Internal Drive (5.25”) bay
Internal Drive (3.5”) bay
Power Button
Power On/Sleep Indicator
Hard Drive Activity Indicator
1
2
3
4
5
6
7
Figure 2–2. Cabinet Layouts, Front View
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Technical Reference Guide
2
1
3
5
4
6
8
9
4
6
9
1
2
10 12 14 16 20
8
7
11
13
10
12
14
16
15
17
18
19
20
3
5
11 13
15 17 18 19
7
Desktop
Minitower
Item
Function
1
2
3
4
5
AC Line In Connector
Smart Cover Lock Screws
Line Voltage Switch
USB Interface Port B
USB Interface Port A
100TX speed LED
6
7
Activity LED
8
Link LED
9
NIC Connector
10
11
12
13
14
15
16
17
18
19
20
SCSI connector
Audio Headphone Input
Audio Microphone Input
Audio Line Output
Audio Line Input
Keyboard Connector
Mouse Connector
Parallel Interface Connector
Serial Interface Connector (COM1)
Serial Interface Connector (COM2)
Graphics Monitor Connector
Figure 2–3. Cabinet Layouts, Rear View
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Chapter 2 System Overview
2.3.2 CHASSIS LAYOUTS
Figures 2-4 and 2-5 show the layout of key assemblies within the desktop and minitower chassis
respectively. For serviceability this system features an expansion card cage that allows easy
removal of the backplane and expansion cards as a single assembly. The tilt drive cage tilts up for
easy removal/replacement of drives. For detailed information on servicing the chassis refer to the
multimedia training CD-ROM and/or the maintenance and service guide for this system.
PCI Slot 4 (SCSI Card)
ISA Slot
PCI Slot 3
ISA Slot
PCI Slot 2
Back
PCI Slot 1 (NIC Card)
Expansion Card Cage
Slots On Backplane,
Rear View
Power Supply
AGP NLX
Graphics Card
Wide-Ultra
SCSI Card
Tilt Drive Cage
System Board
Chassis Fan
Speaker
Processor
Front
Figure 2–4. Desktop Chassis Layout, Top View
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ISA Slot
Power Supply
ISA Slot
PCI Slot 5
PCI Slot 4
PCI Slot 3
Drive Bays
PCI Slot 2 (SCSI Card)
PCI Slot 1 (NIC Card)
Expansion Card Cage
Slots On Backplane,
Rear View @ 90°
Front
Back
Wide-Ultra
SCSI Card
Processor
Speaker
System Board
AGP NLX
Graphics Card
Figure 2–5. Minitower Chassis Layout, Left Side View
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Chapter 2 System Overview
2.3.3 BOARD LAYOUTS
Figure 2-6 shows the location of connectors and switches for the system board, which is the same
for all models and both formfactors.
1
2
3
6
7
5
4
16
15
8
14
13
12
9
11
10
System Board (NLX-Type)
(P/N 007998-xxx
or 008123-xxx [1])
Item
1
2
Function
Serial I/F (COM2)
Serial I/F (COM1)
Parallel I/F
Item
7
8
Function
(bottom) USB Port A I/F
Backplane Connector
Processor Slot 1
3
9
4
4
5
5
6
6
7
(top) Mouse connector
(bottom) Keyboard connector
(top) Audio Line Input
(bottom) Audio Line Output
(top) Audio Mic Input
(bottom) Audio Headphone Output
(top) USB Port B I/F
10
11
12
13
14
15
16
Heat Sink Thermal Diode Connector [2]
DIMM Sockets
Frequency/Password DIP Switch
Heat Sink Thermal Diode Connector [3]
CMOS Clear Jumper
AGP Slot (NLX-type)
Battery
NOTE:
[1] The two system boards are electrically identical. There are slight differences in the location of some
components. Later production units use the 008123-xxx board.
[2] PCA # 008123
[3] PCA # 007998
Figure 2–6. System Board Connector and Switch Locations
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Figure 2-7 shows the connector and switch locations for the two types of backplane boards.
1
2
3
6
7
9
1
2
7
8
3
5
6
9
5
4
10
4
11
11
10 12
18 17 16 15
System Board Side
12 14
13
18 17 16 15
System Board Side
14 13
Power Supply Side
Power Supply Side
Desktop Backplane Board
(P/N 008001-xxx
Minitower Backplane Board
(P/N 008058-xxx)
or 009663-xxx [5])
Item Function
Item
10
11
12
13
14
15
16
17
18
Function
1
2
3
PCI connector J20 (slot 1)
PCI connector J21 (slot 2)
ISA connector J10 [1]
CD audio input header P7
Secondary EIDE connector P21
Diskette drive connector P10
Primary EIDE connector P20
Power button/LED header P5
Fan header P8
Speaker header P6
SCSI LED header P29
NIC WOL header P9
4
5
PCI connector J22 (slot 3) [2]
ISA connector J11 [3]
6
7
8
9
Smart Cover sensor switch
PCI connector J23 (slot 4) [4]
PCI connector J24 (slot 5)
Power supply connector P1
NOTES:
[1] Shares slot with item 4 on desktop backplane (combo slot 1)
[2] Shares slot with item 3 on desktop backplane (combo slot 1)
[3] Shares slot with item 7 on desktop backplane (combo slot 2)
[4] Shares slot with item 5 on desktop backplane (combo slot 2)
[5] Later production units use the 009663-001 board
Figure 2–7. Backplane Board Connector, Header, and Switch Locations
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Chapter 2 System Overview
2.4
SYSTEM ARCHITECTURE
The Compaq Deskpro EN Series of Personal Computers is based on an Intel Pentium II processor
matched with the Intel 440BX AGPset. The basic architecture (Figure 2-8), uses three main
buses: the Host bus, the Peripheral Component Interconnect (PCI) bus, and the Industry Standard
Architecture (ISA) bus.
The Host and memory buses provide high performance support for CPU, cache and system
memory accesses, and operate at 66 or 100 MHz, depending on the speed of the microprocessor.
The PCI bus provides support for the UATA controllers, USB ports, and PCI expansion devices.
The PCI bus operates at 33 MHz. This system also includes an Accelerated Graphics Port (AGP)
slot for an AGP graphics card. The AGP bus is closely associated with the PCI bus but operates at
66 MHz and allows data pipelining, sideband addressing, and frame mode transfers for increased
3D graphics performance.
The ISA bus provides a standard 8-MHz interface for the input/output (I/O) devices such as the
keyboard, diskette drive, serial and parallel interfaces, as well as the addition of 16- or 8-bit
expansion devices.
The north and south bridge functions are provided by the 440BX AGPset designed to compliment
the processor. The support chipset also provides memory controller and data buffering functions
as well as bus control and arbitration functions.
The I/O interfaces and diskette drive controller are integrated into the PC87307 I/O Controller.
This component also includes the real time clock and battery-backed configuration memory
(CMOS).
Table 2-1 lists differences between system models:
Table 2-1.
Model Differences
Model 3200
DT/MT
Model 4300
DT/MT
Model 6400
T
DT/M
Model 9100
MT
Form Factor
CPU Speed (MHz)
Host Bus Speed (MHz)
Hard Drive
266/300/333
66
3.2 GB UATA
333/350/400
66/100/100
4.3 GB SCSI
300/333/350/400
66/66/100/100
6.4 GB UATA
400/450
100
9.1 GB SCSI
System Memory:
Standard
Maximum installable
Graphics Controller
16/32 MB SDRAM
384 MB
ATI RAGE PRO
Turbo
32/64 MB ECC
384 MB
ATI RAGE PRO
Turbo
32/64 MB SDRAM
384 MB
ATI RAGE PRO
Turbo
64 MB ECC
384 MB
ATI RAGE PRO
Turbo
AGP 1X Card
AGP 2X Card
AGP 1X/2X Card
AGP 2X Card
NOTE:
Only BTO configurations shown.
The following subsections provide a description of the key functions and subsystems.
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Pentium II or
Celeron
Processor
66-/100- MHz 64-Bit Host Bus
66-MHz
32-Bit
AGP Bus
66-/100-MHz
64-Bit
Mem. Bus
82443BX
(North
System
Memory
Graphics
Cntlr. Card
Bridge)
33-MHz
32-Bit
PCI Bus
Wide Ultra
SCSI
Hard Drive
Wide Ultra SCSI
Cntlr. Card
10/100 NIC
Card
System
Security
Logic
Pri.
IDE I/F
IDE
Hard Drive
82371
(South
Bridge)
USB
I/F (2)
Sec.
IDE I/F
Beep Audio
16-Bit ISA Bus
BIOS
ROM
CD Audio
Audio
Subsystem
87307 I/O Controller
Power
Supply
Keyboard/
Mouse I/F
Diskette
I/F
Serial
I/F (2)
Parallel
I/F
CDS Desktops and all Minitower models.
3200 and 6400 models only.
4300 and 9100 models only.
Figure 2–8. Compaq Deskpro EN System Architecture, Block diagram
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Chapter 2 System Overview
2.4.1 PROCESSOR
The Deskpro EN Series includes models based on Pentium II and Celeron processors. The
processor and heat sink is mounted as an assembly (Figure 2-9) in a slot (Slot 1) on the system
board. The Pentium II processor includes a microprocessor and a secondary (L2) cache contained
in a single edge connector (SEC) cartridge to which a heat sink is attached. The Celeron
processor includes a microprocessor mounted on a single edge processor package (SEPP) board.
On these systems the SEPP board of the Celeron processor is contained within a SEPP board
housing and heat sink.
Heat Sink
SEPP Board
Microprocessor
SEC Cartridge
Secondary (L2) Cache
Microprocessor
SEPP Board
Housing
Pentium II Processor
Assembly
Celeron Processor
Assembly
Figure 2–9. Processor Assembly Comparison
The Pentium II and Celeron processors are backward-compatible with software written for the
Pentium MMX, Pentium Pro, Pentium, and x86 microprocessors. The integrated microprocessor
provides performance enhancements for multi-byte and floating-point processing.
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2.4.2 SYSTEM MEMORY
This system provides three 168-pin DIMM sockets with 16, 32 or 64 megabytes of RAM
installed depending on model. System memory can be expanded up to 384 megabytes using 16-,
32-, 64-, and 128-MB DIMMs. This system supports SDRAM, EDO, and ECC DIMMs. Models
3200 and 6400 come with SDRAM installed while models 4300 and 9100 come with ECC
DIMMs installed. Non-parity DIMMs are installed as standard but parity DIMMs are supported.
2.4.3 SUPPORT CHIPSETS
Table 2-2 shows the functions provided by the key components on the system board.
Table 2-2.
Support Chipsets
Component Name
PCI Arbitration Controller (PAC) North Bridge
Component Type
Function
Memory Controller
Host/PCI Bridge
PCI/ISA Bridge
EIDE Controller
DMA Controller
Interrupt Controller
Timer/Counter
82443BX
PCI-ISA/IDE eXcelerator (PIIX4E) South Bridge
82371
NMI Registers
Reset Control Reg.
USB I/F (2)
Super I/O Controller
87307
Keyboard I/F
Diskette I/F
Serial I/F
Parallel I/F
RTC/CMOS Mem.
GPIO Ports
Clock Generator
System Security ASIC
CY2280
Compaq ASIC
Clock Generator
Super I/O Security
Smart Cover Lock
ROM Write Protect
Temperature Shutdown
SM/WOL Interrupts
Diskette Write Disable
Pwr LED Blink Cntrl.
PS On sig. Cntrl.
2.4.4 MASS STORAGE
All models include a 3.5 inch 1.44-MB diskette drive installed. Either an EIDE or SCSI hard
drive is also installed, depending on model. All models include a PCI bus mastering Enhanced
IDE (EIDE) controller that provides two EIDE interfaces supporting up to four IDE devices.
Models equipped with a SCSI drive include a Wide Ultra SCSI adapter board. A 32x CD-ROM is
included on desktop CDS models and on all MT models.
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Chapter 2 System Overview
2.4.5 SERIAL AND PARALLEL INTERFACES
All models include two serial ports and a parallel port accessible at the rear of the chassis. The
serial and parallel ports are integrated into a PC87307 I/O Controller component. The serial port
is RS-232-C/16550-compatible and operates at baud rates up to 115,200. The parallel interface is
Enhanced Parallel Port (EPP1.9) and Enhanced Capability Port (ECP) compatible, and supports
bi-directional data transfers.
2.4.6 UNIVERSAL SERIAL BUS INTERFACE
All models feature two Universal Serial Bus (USB) ports that provide a high speed interface for
future systems and/or peripherals. The USB operates at 12 Mbps and provides hot
plugging/unplugging (Plug ’n Play) functionality.
2.4.7 GRAPHICS SUBSYSTEM
The graphics subsystem is conatained on a card installed into the AGP slot. Two types of
graphics controllers are used, depending on the microprocessor employed on the system board as
indicated in Table 2-3.
Table 2-3.
Graphics Subsystem Comparison
266-/300-/333-MHz Processor
350-/400-/4500 MHz Processor
Graphics Controller
Graphics Memory
Standard installed:
Expandable to:
ATI Rage Pro Turbo AGP
ATI Rage Pro Turbo AGP 2X
4 MB SGRAM
N/A
4 MB SGRAM
8 MB SGRAM
Maximum Resolution
w/ standard mem.
w/ max. mem.
1600 x 1200 @ 65K colors
--
1600 x 1200 @ 65K colors
1600 x 1200 @ 16.7M colors
2.4.8 AUDIO SUBSYSTEM
All models feature the Compaq Premier Sound system. The system board includes an embedded
16-bit full-duplex subsystem based on the ES1869 graphics controller. The audio output is
processed through a six-level equalizer designed to work with the chassis acoustics. A low-
distortion 5-watt amplifier drives a long-excursion speaker for optimum sound. The audio
subsystem is compatible with software written for industry-common sound hardware.
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2.5
SPECIFICATIONS
This section includes the environmental, electrical, and physical specifications for the Compaq
DESKPRO EN Series Personal Computers.
Table 2-4.
Environmental Specifications
Parameter
Air Temperature
Shock
Vibration
Humidity
Operating
50o to 95o F (10o to 35o C)
N/A
Nonoperating
-24o to 140o F (-30o to 60o C)
60.0 g for 2 ms half-sine pulse
0.0005g^ 2/Hz, 10-500 Hz [1]
95% RH @ 36o C
0.000215g^ 2/hz, 10-300 Hz [1]
90% RH @ 36o C (no hard drive)
10,000 ft (3048 m)
Maximum Altitude
30,000 ft (9,144 m)
NOTE:
Values are subject to change without notice.
[1] 0.5 grms nominal
Table 2-5.
Electrical Specifications
Parameter
U.S.
International
Input Line Voltage:
Nominal:
Maximum:
110 - 120 VAC
90 - 132 VAC
200 - 240 VAC
180 - 264 VAC
Input Line Frequency Range:
Nominal:
Maximum:
50 - 60 Hz
47 - 63 Hz
50 - 60 Hz
47 - 63 Hz
Power Supply:
Maximum Continuous Power
Maximum Peak Power
Maximum Line Current Draw
200 watts
200 watts
5.5 A
200 watts
200 watts
3.0 A
Table 2-6.
Physical Specifications
Parameter
Height
Width
Depth
Weight [1]
Desktop
Minitower
5.88 in (14.93 cm)
19.16 in (48.66 cm)
16.82 in (42.72 cm)
32.0 lb (14.50 kg)
20.25 in (51.44 cm)
8.38 in (21.29 cm)
18.60 in (47.24 cm)
40.0 lb (18.20 kg)
NOTES:
Metric figures in parenthesis.
[1] System weight may differ depending on installed drives/peripherals.
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Chapter 2 System Overview
Table 2-7.
Diskette Drive Specifications
(Compaq SP# 179161-001)
Parameter
Measurement
Media Type
3.5 in 1.44 MB/720 KB diskette
Height
1/3 bay (1 in)
512
Bytes per Sector
Sectors per Track:
High Density
18
9
Low Density
Tracks per Side:
High Density
Low Density
Read/Write Heads
Average Access Time:
Track-to-Track (high/low)
Average (high/low)
Settling Time
80
80
2
3 ms/6 ms
94 ms/173ms
15 ms
Latency Average
100 ms
Table 2-8.
32x CD-ROM Drive Specifications
(SP# 327659-001)
Parameter
Interface Type
Transfer Rate:
Max. Sustained
Burst
Measurement
IDE
4800 KB/s
16.6 MB/s
Media Type
Mode 1,2, Mixed Mode, CD-DA,
Photo CD, Cdi, CD-XA
Capacity:
Mode 1, 12 cm
Mode 2, 12 cm
8 cm
Center Hole Diameter
Disc Diameter
Disc Thickness
Track Pitch
550 MB
640 MB
180 MB
15 mm
8/12 cm
1.2 mm
1.6 um
Laser
Beam Divergence
Output Power
Type
53.5 +/- 1.5 °
53.6 0.14 mW
GaAs
Wave Length
Average Access Time:
Random
Full Stroke
Audio Output Level
Cache Buffer
790 +/- 25 nm
<100 ms
<150 ms
0.7 Vrms
128 KB
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Table 2-9.
Hard Drive Specifications
3.2 GB
4.3 GB
(# 179287-001)
Wide-Ultra SCSI
65
6.4 GB
9.1 GB
(# 179288-001)
Wide-Ultra SCSI
65
Parameter
Interface
Drive Type
(# 166873-001)
EIDE-UATA
65
(# 166973-001)
EIDE-UATA
65
Drive Size
5.25 in
5.25 in
5.25 in
5.25 in
Transfer Rate
Seek Time (w/settling)
Single Track
Average
Full Stroke
33.3 MB/s
40.0 MB/s
33.3 MB/s
40.0 MB/s
<1.0 ms
<9.7 ms
<18.0 ms
.76 ms
7.5 ms
17.0 ms
2.0 ms
<9.7 ms
20.0 ms
.76 ms
7.5 ms
15.0 ms
Disk Format:
# of Cylinders
# of Data Heads
# of Sectors per Track
Buffer Size
6697
15
63
256 KB
SMART II
8420
8
165-264
512 KB
SMART II
13325
15
63
256 KB
SMART II
8420
10
165-264
512 KB
SMART II
Drive Fault Prediction
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Chapter 3
PROCESSOR/
MEMORY SUBSYSTEM
3.1
INTRODUCTION
This chapter describes the processor/cache memory subsystem of the Compaq Deskpro EN Series
of desktop and minitower Personal Computers. These systems are shipped either with an Intel
Pentium II or Celeron processor and either 32 or 64 megabytes of system memory, depending on
configuration.
This chapter includes the following topics:
♦
Processor/memory subsystem [3.2]
page 3-2
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Chapter 3 Processor/Memory Subsystem
3.2
PROCESSOR/MEMORY SUBSYSTEM
The subsystem features an Intel Pentium II or Celeron processor with the North Bridge
(82443BX), and either 32 or 64 megabytes of system memory (Figure 3-1). The 64-bit Host and
memory buses operate at either 66- or 100-MHz depending on the speed of the processor. The 32-
bit PCI bus operates at 33-MHz.
Processor
(in Slot 1)
System Memory
66-/100-MHz
Cntl
64-Bit Host Bus
J2
J3
J1
66-/100-MHz
Mem. Data Bus
66-MHz
32-Bit
AGP Bus
North
Bridge
32-MB
DIMM
DIMM
DIMM
Graphics
Subsystem
(82443BX)
Mem. Addr.
33-MHz 32-Bit PCI Bus
Optional module
Figure 3–1. Processor/Memory Subsystem Architecture
The processor is mounted in a slot 1-type connector that facilitates easy changing/upgrading.
Replacing the processor may require reconfiguring DIP switch SW1 to select the correct bus
frequency/core frequency combination. Frequency selection is described in detail later in this
section.
The North Bridge (82443BX) provides Host/memory/PCI bridge functions and controls data
transfers with system memory over the 64-bit memory data bus. The 443BX supports SDRAM,
EDO, FPM, and ECC DIMM modules. Three DIMM sockets allow the system memory to be
expanded to 384 megabytes.
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3.2.1 PROCESSOR
The system board includes a Slot 1-type interface that accommodates a Pentium II or Celeron
processor. Table 3-1 provides a comparison between the key parameters of the Pentium II and
Celeron processors.
Table 3-1.
Processor Comparsion
Pentium II
266-333
266-333 MHz
512 KB
Celeron
266/300
300 MHz
0 KB
Celeron
300A/333
300/333 MHz
128 KB
Pentium II
350
350 MHz
512 KB
Pentium II
400
400 MHz
512 KB
Pentium II
450
450 MHz
512 KB
CPU Freq.
L2 Cache
L2 Cache Freq.
Host Bus Freq.
133-166 MHz
66 MHz
--
300/333 MHz
66 MHz
175 MHz
100 MHz
200 MHz
100 MHz
225 MHz
100 MHz
66 MHz
3.2.1.1 Pentium II Processor
The Intel Pentium II processor is packaged in a Single Edge Connector (SEC) cartridge that
contains the microprocessor and a 512-KB ECC secondary (L2) cache. The processor’s
architecture (Figure 3-2) includes a dual-ALU MMX-supporting CPU, branch prediction logic,
dual-pipeline floating point unit (FPU) coprocessor, and a 32-KB L1 cache that is split into two
16-KB 4-way, set-associative caches for handling code and data separately. These functions
operate at core processing speed (Figure 3-2), which ranges from 266 to 400 megahertz
depending on version.
Pentium II Processor
CPU
FPU
32-KB
L1
512-KB
L2
Cache
Cache
Branch
Prediction
FSB
I/F
Host bus speed
Core processing speed
½ Core processing speed
Figure 3–2. Pentium II Processor Internal Architecture
The Pentium II processor includes 512 kilobytes of SRAM for the write-through L2 cache.
Accesses with the L2 cache occur at 50% of the core processing speed. The front side bus (FSB,
also referred to as the Host bus) interface of the 266-, 300-, and 333-MHz processors operates at
66-MHz. The FSB interface of the 350- and 400-MHz processors operates at 100 MHz. The
Pentium II processor is software-compatible with earlier generation x86 microprocessors.
NOTE: Later versions of the Pentium II processor require updated BIOS firmware.
Refer to section 3.2.2 for upgrading information.
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Chapter 3 Processor/Memory Subsystem
3.2.1.2 Celeron Processor
Select systems are shipped with the Intel Celeron processor. The Celeron processor (Figure 3-3)
uses a CPU/FPU core that is functionally the same as that of the Pentium II described previously
and provides the same level of branch prediction, math co-processing, MMX support, and L1
cache operation. Processing and Host bus speed ratios follow those of the Pentium II processors
and are set and determined with the same methods. Note that the Celeron 300 does not include
an L2 cache. The L2 cache of the Celeron 300A and 333 operates at processor (CPU) speed.
Celeron Processor
CPU
FPU
32-KB
L1
128-KB
L2
Cache
Cache [1]
Branch
Prediction
FSB
I/F
[1] Not present on Celeron 266 or 300 processors.
Core processing speed
Host bus speed
Figure 3–3. Celeron Processor Internal Architecture
Like the Pentium II processor, the Celeron processor is software-compatible with earlier
generation Pentium MMX, Pentium, and x86 processors.
NOTE: Later versions of the Celeron processor require updated BIOS firmware. Refer
to section 3.2.2 for upgrading information.
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3.2.2 PROCESSOR CHANGING/UPGRADING
The slot 1 design allows for easy changing and/or upgrading of the processor/cache complex.
Changing the processor requires disconnection/re-connection of the heat sink sensor cable and
may require upgrading the BIOS firmware and re-configuration of the bus/core speed switch
discussed in the following paragraphs.
3.2.2.1 BIOS Upgrading
The Pentium II 450 and Celeron 300A/333 processors require BIOS firmware dated 7/30/98 or
later. Installing and running one of these processors in a system with BIOS dated earlier than
7/30/98 will likely cause the system to halt (lockup).
The BIOS (ROM) version may be checked using either the Compaq Diagnostics or Compaq
Insight utility.
3.2.2.2 Processor Speed Selection
Changing the processor may require re-configuration of the bus/core frequency ratio. The system
board includes a six-position DIP switch (SW), of which positions 2-5 are read by the processor
(while RESET- is active) to select the bus-to-core frequency ratio. Table 3-2 shows the possible
switch configurations for this system and the resultant core (or processing) frequency, based on
the front side bus (FSB or Host bus) frequency.
Table 3-2.
Bus/Core Speed Switch Settings
Core Frequency
DIP SW1 Settings
2 3 4 5 [1]
1 0 0 0
1 1 0 0
0 0 1 0
Bus/Core
Freq. Ratio
w/66-MHz FSB
w/100-MHz FSB
1/3
2/7
1/4
2/9
1/5
200
233
266
300
333
300
350
400
450
500
0 1 1 0
1 0 1 0
NOTES:
Shipping configurations are unshaded.
[1] 0 = Switch Closed (On), 1 = Switch Open (Off)
The DIP switch settings should be set to match the processor installed.
Configuring for a speed higher than that which the processor is
designed could result in unreliable operation and possible system damage.
The processor sets the clock generator to the appropriate bus frequency. Software can determine
the operating speed by reading the bus speed from an MSR register in the processor.
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Chapter 3 Processor/Memory Subsystem
3.2.3 SYSTEM MEMORY
The system board contains three 168-pin DIMM sockets for system memory. This system is
designed for using SDRAM or ECC DIMMs. As shipped from the factory the standard
configuration has 16, 32, or 64 megabytes of memory installed. The system memory is
expandable up to a maximum of 384 megabytes. Single or double-sided DIMMs may be used. In
expanding the standard memory using modules from third party suppliers the following DIMM
type is recommended: 66- or 100-MHz unbuffered RAM supporting CAS latency (CL) 2 or 3
with a data access time (clock-to-data out) of 9.0 ns or less @ CL=2 or CL=3.
NOTE: The DIMM speed should compliment the host bus speed of the processor (i.e.,
use 66-MHz DIMMs in a system with a 266/66 processor and 100-MHz DIMMs in a
system with a 350/100 processor). All systems are factory-shipped with 100-MHz
DIMMs.
The RAM type and operating parameters are detected during POST by the system BIOS using the
serial presence detect (SPD) method. This method employs an I2C bus to communicate with an
EEPROM on each installed DIMM. The EEPROM holds the type and operating parameter data.
The supported format complies with the JEDEC specification for 128-byte EEPROMs. This
system also provides support for 256-byte EEPROMs to include additional Compaq-added
features such as part number and serial number. The SPD format as supported in this system is
shown in Table 3-3.
The key SPD bytes that BIOS checks for compatibility are 2, 9, 10, 18, 23, and 24. If BIOS
detects EDO DIMMs a “memory incompatible” message will be displayed and the system
will halt. If ECC DIMMs are used, all DIMMs installed must be ECC for ECC benefits (error
logging) to be realized.
Once BIOS determines the DIMM type the DRAM speed and CAS latency is checked based on
the following criteria:
Access
from
Bus Speed
66 MHz
100 MHz
Cycle Time
15 ns
Clock
9 ns @ 50 pf loading
6 ns @ 50 pf loalding
10 ns
NOTE: Refer to chapter 8 for a description of the BIOS procedure of interrogating
DIMMs.
Only CAS latencies of 2 or 3 are supported. If DIMMs with unequal CAS latencies are installed
then operation will occur based on the DIMM with the greatest latency.
If an incompatible DIMM is detected the NUM LOCK will blink for a short period of time during
POST and an error message may or may not be displayed before the system hangs.
The system memory map is shown in Figure 3-3.
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Table 3-3.
SPD Address Map (SDRAM DIMM)
Byte
0
1
2
3
4
5
6, 7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
Description
Notes
[1]
[2]
Byte
27
28
Description
Notes
[7]
[7]
No. of Bytes Written Into EEPROM
Total Bytes (#) In EEPROM
Memory Type
No. of Row Addresses On DIMM
No. of Column Addresses On DIMM
No. of Module Banks On DIMM
Data Width of Module
Voltage Interface Standard of DIMM
Cycletime @ Max CAS Latency (CL)
Access From Clock
Config. Type (Parity, Nonparity, etc.)
Refresh Rate/Type
Width, Primary DRAM
Error Checking Data Width
Min. Clock Delay
Burst Lengths Supported
No. of Banks For Each Mem. Device
CAS Latencies Supported
CS# Latency
Min. Row Prechge. Time
Min. Row Active to Delay
Min. RAS to CAS Delay
Reserved
Superset Data
SPD Revision
Checksum Bytes 0-62
JEP-106E ID Code
DIMM OEM Location
OEM’s Part Number
OEM’s Rev. Code
Manufacture Date
OEM’s Assembly S/N
OEM Specific Data
Reserved
Compaq header “CPQ1”
Header checksum
Unit serial number
DIMM ID
29
[7]
[3]
30, 31
32..61
62
63
64-71
72
73-90
91, 92
93, 94
95-98
99-125
126, 127
128-131
132
[7]
[7]
[8]
[8]
[8]
[8]
[8]
[8]
[8]
[4]
[4]
[4] [5]
[6]
[9]
[9]
[9] [10]
[9] [11]
[9]
[4]
[4]
[4]
[4]
133-145
146
147
Write Latency
DIMM Attributes
Checksum
Reserved
148-255
[9]
Memory Device Attributes
Min. CLK Cycle Time at CL X-1
Max. Acc. Time From CLK @ CL X-1
Min. CLK Cycle Time at CL X-2
Max. Acc. Time From CLK @ CL X-2
[7]
[7]
[7]
[7]
NOTES:
[1] Programmed as 128 bytes by the DIMM OEM
[2] Must be programmed to 256 bytes.
[3] High order bit defines redundant addressing: if set (1), highest order RAS# address must be
re-sent as highest order CAS# address.
[4] Refer to memory manufacturer’s datasheet
[5] MSb is Self Refresh flag. If set (1), assembly supports self refresh.
[6] Back-to-back random column addresses.
[7] Field format proposed to JEDEC but not defined as standard at publication time.
[8] Field specified as optional by JEDEC but required by this system.
[9] Compaq usage. This system requires that the DIMM EEPROM have this
space available for reads/writes.
[10] Serial # in ASCII format (MSB is 133). Intended as backup identifier in case vender data is invalid.
Can also be used to indicate s/n mismatch and flag system adminstrator of possible system
Tampering.
[11] Contains the socket # of the module (first module is “1”). Intended as backup identifier (refer to
note [10]).
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Chapter 3 Processor/Memory Subsystem
Figure 3-3 shows the system memory map for the system.
4 GB
FFFF FFFFh
FFE0 0000h
FFDF FFFFh
High BIOS Area
(2 MB)
PCI Memory
(18 MB)
FEC1 0000h
FEC0 FFFFh
APIC Config. Space
(64 KB)
FEC0 0000h
FEBF FFFFh
Host,
PCI, AGP Area
PCI Memory
Expansion
(2548 MB)
4000 0000h
3FFF FFFFh
1 GB
Host/PCI Memory
Expansion
(1008 MB)
0100 0000h
00FF FFFFh
16 MB
1 MB
Host, PCI,
ISA Area
Extended Memory
(15 MB)
0010 0000h
000F FFFFh
System BIOS Area
(64 KB)
000F 0000h
000E FFFFh
Extended BIOS Area
(64 KB)
000E 0000h
000D FFFFh
Option ROM
(128 KB)
000C 0000h
000B FFFFh
Graphics/SMRAM
RAM (128 KB)
DOS Compatibility
Area
000A 0000h
0009 FFFFh
640 KB
512 KB
Fixed Mem. Area
(128 KB)
0008 0000h
0007 FFFFh
Base Memory
(512 KB)
0000 0000h
NOTE: All locations in memory are cacheable. Base memory is always mapped to DRAM. The next 128 KB fixed
memory area can, through the north bridge, be mapped to DRAM or to PCI space. Graphics RAM area is mapped
to PCI or AGP locations.
Figure 3–4. System Memory Map
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3.2.4 SUBSYSTEM CONFIGURATION
The 443BX north bridge component provides the configuration function for the
processor/memory subsystem. Table 3-4 lists the configuration registers used for setting and
checking such parameters as memory control and PCI bus operation. These registers reside in the
PCI Configuration Space and accessed using the methods described in Chapter 4, section 4.2.
Table 3-4.
Host/PCI Bridge Configuration Registers (82443BX, Function 0)
PCI Config.
Addr.
00, 01h
02, 03h
04, 05h
06, 07h
08h
Reset
Value
8086h
7190h
0006h
0210h
--
PCI Config.
Addr.
6A, 6Bh
6C..6Fh
70h
Reset
Value
00h
55h
00h
Register
Vender ID
Device ID
Command
Status
Revision ID
Register
DRAM Control Reg.
Memory Buffer Strength
Multi-Transaction Timer
CPU Latency Timer
SMRAM Control
71h
72h
10h
02h
09..0Bh
0Dh
0Eh
10..13h
50, 51h
53h
55..56h
57h
Class Code
Latency Timer
Header Type
--
00h
00h
8
00h
83h
00h
01h
00h
00h
01h
00h
90h
91h
92h
93h
A0..A3h
A4..A7h
A8..ABh
B0..B3h
B4h
B8..BBh
BCh
BDh
Error Command
00h
00h
00h
00h
N/A
N/A
00h
00h
Error Status Register 0
Error Status Register 1
Reset Control
AGP Capability Identifier
AGP Status
AGP Command
AGP Control
Aperture Size
Aperture Base Config.
PAC Config. Reg.
Data Buffer Control
DRAM Row Type
DRAM Control
DRAM Timing
PAM 0..6 Registers
DRAM Row Boundary
Fixed DRAM Hole
58h
0000h
0000h
00h
59..5Fh
60..67h
68h
Aperture Translation Table
Aperture I/F Timer
Low Priority Timer
00h
NOTES:
Refer to Intel Inc. documentation for detailed description of registers.
Assume unmarked locations/gaps as reserved.
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Chapter 4
SYSTEM SUPPORT
4.1
INTRODUCTION
This chapter covers subjects dealing with basic system architecture and covers the following
topics:
♦
♦
♦
♦
♦
♦
♦
PCI bus overview (4.2)
AGP bus overview (4.3)
ISA bus overview (4.4)
System clock distribution (4.5)
Real-time clock and configuration memory (4.6) page 4-29
I/O map and register accessing (4.7)
System management (4.8)
page 4-2
page 4-11
page 4-16
page 4-28
page 4-46
page 4-51
This chapter covers functions provided by off-the-shelf chipsets and therefore describes only basic
aspects of these functions as well as information unique to the Compaq Deskpro EN Series of
Personal Computers. For detailed information on specific components, refer to the applicable
manufacturer’s documentation.
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Chapter 4 System Support
4.2
PCI BUS OVERVIEW
NOTE: This section describes the PCI bus in general and highlights bus
implementation in this particular system. For detailed information regarding PCI bus
operation, refer to the PCI Local Bus Specification Revision 2.1.
This system implements a 5-V, 32-bit Peripheral Component Interconnect (PCI) bus operating at
33 MHz. The PCI bus uses a shared address/data bus design. On the first clock cycle of a PCI bus
transaction the bus carries address information. On subsequent cycles, the bus carries data. PCI
transactions occur synchronously with the Host bus at 33 MHz. All I/O transactions involve the
PCI bus. All ISA transactions involving the microprocessor, cache, and memory also involve the
PCI bus. Memory cycles will involve the PCI if the access is initiated by a device or subsystem
other than the microprocessor.
The PCI bus handles address/data transfers through the identification of devices and functions on
the bus (Figure 4-1). A device is defined as a component or slot that resides on the PCI bus. A
function is defined as the end source or target of the bus transaction. A device (component or
slot) may contain one or more functions (i.e., in this system the PCI/ISA Bridge function, EIDE
controller function, USB function, and ACPI function are contained within the South Bridge
component).
Host Bus
PCI Connector Slot 5
PCI Connector Slot 4
82443 North Bridge
PCI Connector Slot 3
PCI Connector Slot 2
PCI Connector Slot 1
Host/PCI
Bridge
PCI/AGP
Bridge
Function
Function
32-Bit PCI Bus
PCI/ISA
Bridge
Function
EIDE
Controller
Function
USB
I/F
Function
Power
Manage
Function
82371 South Bridge
ISA Bus
Minitower only
Figure 4–1. PCI Bus Devices and Functions
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4.2.1 PCI CONNECTOR
B1
B49
A49
B62
B52
A52
A1
A62
Figure 4–2. PCI Bus Connector (32-Bit Type)
Table 4-1.
PCI Bus Connector Pinout
Pin
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
--
B Signal
-12 VDC
TCK
GND
TDO
+5 VDC
+5 VDC
INTB-
INTD-
PRSNT1-
RSVD
PRSNT2-
GND
GND
RSVD
GND
CLK
GND
REQ-
+5 VDC
AD31
AD29
GND
AD27
AD25
+3.3 VDC
C/BE3-
AD23
GND
AD21
AD19
+3.3 VDC
--
A Signal
TRST-
+12 VDC
TMS
TDI
+5 VDC
INTA-
INTC-
+5 VDC
Reserved
+5 VDC
Reserved
GND
GND
Reserved
RST-
+5 VDC
GNT-
GND
PME-
AD30
+3.3 VDC
AD28
AD26
GND
AD24
Pin
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
--
B Signal
AD17
A Signal
AD16
C/BE2-
GND
IRDY-
+3.3 VDC
DEVSEL-
GND
LOCK-
PERR-
+3.3 VDC
SERR-
+3.3 VDC
C/BE1-
AD14
GND
AD12
AD10
GND
Key
Key
AD08
AD07
+3.3 VDC
AD05
AD03
GND
AD01
+5 VDC
ACK64-
+5 VDC
+5 VDC
--
+3.3 VDC
FRAME-
GND
TRDY-
GND
STOP-
+3.3 VDC
SDONE
SBO-
GND
PAR
AD15
+3.3 VDC
AD13
AD11
GND
AD09
Key
Key
C/BE0-
+3.3 VDC
AD06
AD04
GND
IDSEL
+3.3 VDC
AD22
AD20
GND
AD02
AD00
+5 VDC
REQ64-
+5 VDC
+5 VDC
--
AD18
--
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Chapter 4 System Support
4.2.2 PCI BUS MASTER ARBITRATION
The PCI bus supports a bus master/target arbitration scheme. A bus master is a device that has
been granted control of the bus for the purpose of initiating a transaction. A target is a device that
is the recipient of a transaction. Request (REQ), Grant (GNT), and FRAME signals are used by
PCI bus masters for gaining access to the PCI bus. When a PCI device needs access to the PCI
bus (and does not already own it), the PCI device asserts it’s REQn signal to the PCI bus arbiter
(a function of the system controller component). If the bus is available, the arbiter asserts the
GNTn signal to the requesting device, which then asserts FRAME and conducts the address
phase of the transaction with a target. If the PCI device already owns the bus, a request is not
needed and the device can simply assert FRAME and conduct the transaction. Table 4-1 shows
the grant and request signals assignments for the devices on the PCI bus.
Table 4-2.
PCI Bus Mastering Devices
REQ/GNT Line
REQ0/GNT0
REQ1/GNT1
REQ2/GNT2
REQ3/GNT3
REQ4/GNT4
GREQ/GGNT
Device
PCI Connector Slot 1
PCI Connector Slot 2
PCI Connector Slot 3
PCI Connector Slot 4
PCI Connector Slot 5 [1]
AGP Slot
NOTE:
[1] Minitower only.
PCI bus arbitration is based on a round-robin scheme that complies with the fairness algorithm
specified by the PCI specification. The bus parking policy allows for the current PCI bus owner
(excepting the PCI/ISA bridge) to maintain ownership of the bus as long as no request is asserted
by another agent. Note that most CPU-to-DRAM and AGP-to-DRAM accesses can occur
concurrently with PCI traffic, therefore reducing the need for the Host/PCI bridge to compete for
PCI bus ownership.
The PCI bus arbiter of the 443BX includes a Multi-Transaction Timer (MTT) that provides
additional control for bus agents that perform fragmented accesses or have real-time access
requirements. The MTT allows the use of lower-cost peripherals (by the reduction of data
buffering) for multimedia applications such as video capture, serial bus, and RAID SCSI
controllers.
The 82443 and the 82371 support the passive release mechanism, which reduces PCI bus latency
caused by an ISA initiator owning the bus for long periods of time.
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4.2.3 PCI BUS TRANSACTIONS
The PCI bus consists of a 32-bit path (AD31-00 lines) that uses a multiplexed scheme for
handling both address and data transfers. A bus transaction consists of an address cycle and one
or more data cycles, with each cycle requiring a clock (PCICLK) cycle. High performance is
realized during burst modes in which a transaction with contiguous memory locations requires
that only one address cycle be conducted and subsequent data cycles are completed using auto-
incremented addressing. Four types of address cycles can take place on the PCI bus; I/O,
memory, configuration, and special. Address decoding is distributed (left up to each device on
the PCI bus).
4.2.3.1 I/O and Memory Cycles
For I/O and memory cycles, a standard 32-bit address decode (AD31..0) for byte-level addressing
is handled by the appropriate PCI device. For memory addressing, PCI devices decode the
AD31..2 lines for dword-level addressing and check the AD1,0 lines for burst (linear-
incrementing) mode. In burst mode, subsequent data phases are conducted a dword at a time with
addressing assumed to increment accordingly (four bytes at a time).
4.2.3.2 Configuration Cycles
Devices on the PCI bus must comply with PCI protocol that allows configuration of that device
by software. In this system, configuration mechanism #1 (as described in the PCI Local Bus
specification Rev. 2.1) is employed. This method uses two 32-bit registers for initiating a
configuration cycle for accessing the configuration space of a PCI device. The configuration
address register (CONFIG_ADDRESS) at 0CF8h holds a value that specifies the PCI bus, PCI
device, and specific register to be accessed. The configuration data register (CONFIG_DATA) at
0CFCh contains the configuration data.
PCI Configuration Address Register
PCI Configuration Data Register
I/O Port 0CF8h, R/W, (32-bit access only)
I/O Port 0CFCh, R/W, (8-, 16-, 32-bit access)
Bit
Function
Bit
Function
31
Configuration Enable
0 = Disabled
31..0
Configuration Data.
1 = Enable
30..24
23..16
15..11
Reserved - read/write 0s
Bus Number. Selects PCI bus
PCI Device Number. Selects PCI
device for access
10..8
Function Number. Selects function of
selected PCI device.
Register Index. Specifies config. reg.
Configuration Cycle Type ID.
00 = Type 0
7..2
1,0
01 = Type 1
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Chapter 4 System Support
Figure 4-3 shows how the loading of 0CF8h results in a Type 0 configuration cycle on the PCI
bus. The Device Number (bits <15..11> determines which one of the AD31..11 lines is to be
asserted high for the IDSEL signal, which acts as a “chip select” function for the PCI device to be
configured.
3130
24 23
16 15
Bus
Number
11 10
Function
Number
8
7
2 1 0
Device
Number
Register
Reserved
0 0
Register 0CF8h
Results in:
Index
31
11 10
8
7
2 1 0
AD31..0
w/Type 0
Function
Number
Register
Index
IDSEL (only one signal line asserted)
Config. Cycle
Figure 4–3. Type 0 Configuration Cycle
Type 0 configuration cycles are used for configuring devices on PCI bus # 0. Type 1
configuration cycles (reg. 0CF8h bits <1,0> = 01b) are passed on to PCI bus # 1 (if present).
Table 4-3 shows the standard configuration of device numbers and IDSEL connections for
components and slots residing on a PCI bus.
Table 4-3.
PCI Component Configuration Access
Device
No. [1]
0
IDSEL
Wired to:
AD11
PCI Component
82443 (North Bridge)
AGP slot
Bus
0
1
0
AD16
USB
0
9
AD20
PCI Connector 1 (PCI slot 1)
PCI Connector 2 (PCI slot 2)
PCI Connector 3 (PCI slot 3)
PCI Connector 4 (PCI slot 4)
PCI Connector 5 (PCI slot 5) [2]
82371 (South Bridge)
0
0
0
0
0
0
13
14
15
16
17
20
AD24
AD25
AD26
AD27
AD29
AD31
NOTES
[1] CF8h bits <15..11>
[2] Minitower only.
The function number (CF8h, bits <10..8>) is used to select a particular function within a
multifunction device. Configurable functions present in system as shipped from the factory are
listed in Table 4-4.
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Table 4-4.
PCI Function Configuration Access
PCI Function
Device No.
Function No.
Host/PCI Bridge (82443)
PCI/AGP Bridge (82443)
PCI/ISA Bridge (82371)
IDE Interface (82371)
USB Interface (82371)
Power Management Cntlr. (82371)
0
0
20
20
20
20
0
1
0
1
2
3
The register index (CF8h, bits <7..2>) identifies the 32-bit location within the configuration
space of the PCI device to be accessed. All PCI devices can contain up to 256 bytes of
configuration data (see Figure 4-4), of which the first 64 bytes comprise the configuration space
header.
Register
Index
31
24 23
16 15
8
7
0
FCh
Device-Specific Area
40h
Min_Lat
BIST
Min_GNT
Interrupt Pin
Interrupt Line
3Ch
Base Address Registers and Exp. ROM Address
Configuration
Space
Header
Latency Timer
Cache Line Size
Revision ID
Header Type
Class Code
0Ch
08h
04h
Command
Vender ID
Status
Device ID
00h
Data required by PCI protocol
Not required
Figure 4–4. PCI Configuration Space Map
Each PCI device is identified with a vender ID (assigned to the vender by the PCI Special Interest
Group) and a device ID (assigned by the vender). The device and vender IDs for the devices on
the system board are listed in Table 4-5.
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Table 4-5.
System Board PCI Device Identification
Vender ID
PCI Device
Device ID
North Bridge (82443 PAC):
Host/PCI Bridge (Function 0)
PCI/AGP Bridge (Function 1) [1]
South Bridge (82371 PIIX4):
PCI/ISA Bridge (Function 0)
EIDE Controller (Function 1)
USB I/F (Function 2)
8086h
8086h
7190h
7191h
8086h
8086h
8086h
8086h
7110h
7111h
7112h
7113h
Power Mngmt. Cntlr (Function 3)
NOTES:
[1] Graphics Address Remapping Table (GART) used on all systems.
4.2.3.3 Special Cycles
There are two types of special cycles that may occur on the PCI bus. The first type is initiated by
the host and is used to perform the following functions: Shutdown, Flush, Halt, Write Back,
Flush Acknowledge, Branch Trace Message, and Stop/Grant. These cycles start like all other PCI
cycles and terminate with a master abort.
The second type of special cycle is initiated by writing to 0CF8h, Bus # = all 0s, Device = all 1s,
(Function # all 1s, and Register = all 0s) and 0CFCh to generate a Type 0 configuration cycle.
This Type 0 cycle, however, does not assert any of the IDSEL lines and therefore results in a
master abort with FFFFh returned to the microprocessor.
4.2.4 OPTION ROM MAPPING
During POST, the PCI bus is scanned for devices that contain their own specific firmware in
ROM. Such option ROM data, if detected, is loaded into system memory’s DOS compatibility
area (refer to the system memory map shown in chapter 3).
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4.2.5 PCI INTERRUPT MAPPING
The PCI bus provides for four interrupt signals; INTA-, INTB-, INTC-, and INTD-. These
signals may be generated by on-board PCI devices or by devices installed in the PCI slots. In
order to minimize latency, INTA-..INTD- signal routing from the interrupt controller of the
82371south bridge to PCI slots/devices is distributed evenly as shown below:
Interrupt Cntlr.
INTA-
PCI Slot 1
INTA-
INTB-
INTC-
INTD-
PCI Slot 2
INTD-
INTA-
INTB-
INTC-
PCI Slot 3
INTC-
INTD-
INTA-
INTB-
PCI Slot 4
INTB-
INTC-
INTD-
INTA-
PCI Slot 5 AGP Slot
USB
--
--
INTD-
INTA-
INTB-
INTC-
--
--
INTA-
INTB-
INTB-
INTC-
INTD-
--
INTD-
NOTE: PCI Slot 5 on minitower only.
Interrupts generated by PCI devices can be configured to share the standard AT (IRQn) interrupt
lines. Two devices that share a single PCI interrupt must also share the corresponding AT
interrupt.
4.2.6 PCI POWER MANAGEMENT SUPPORT
This system complies with the PCI Power Management Interface Specification (rev 1.0). The PCI
Power Management Enable (PME-) signal is supported by the 440BX chipset and allows
compliant PCI and AGP peripherals to initiate the power management routine.
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4.2.7 PCI CONFIGURATION
PCI bus operations, especially those that involve ISA bus interaction, require the configuration of
certain parameters such as PCI IRQ routing, top of memory accessible by ISA, SMI generation,
and clock throttling characteristics. These parameters are handled by the PCI/ISA bridge
function (PCI function #0) of the South Bridge component and configured through the PCI
configuration space registers listed in Table 4-6. Configuration is provided by BIOS at power-up
but re-configurable by software.
Table 4-6.
PCI/ISA Bridge Configuration Registers
(82371, Function 0)
PCI Config.
Addr.
00, 01h
02, 03h
04, 05h
06, 07h
08h
09-0Bh
0Eh
4Ch
Reset
Value
8086h
7111h
PCI Config.
Addr.
63h
64h
69h
6A, 6Bh
76, 77h
80h
Reset
Value
80h
Register
Vender ID
Device ID
Command
Status
Revision ID
Class Code
Header Type
DMA Aliasing Control
APIC/BIOS Control
PCI Interrupt Routing
PCI Interrupt Routing
PCI Interrupt Routing
Register
PCI Interrupt Routing
Serial Interrupt Control
Memory Map Control
SERR-/PCI Cycle Retry
DMA Enable/Ch. Routing
A12 Mask/X-Y Base Addr.
USB Passive Rel. Enable
DMA Channel Select
DMA 0-3 Base PTR
DMA 4-7 Base PTR
GPIO/Misc. Funct. Select
RTC/RAM Control
02h
00h
00h
00h
00h
00h
00h
00h
21h
82h
00h
0003h
80h
80h
80h
90, 91h
92, 93h
94, 95h
B0-B3h
CBh
4E-4Fh
60h
61h
62h
NOTE: Assume unmarked locations/gaps as reserved.
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4.3
AGP BUS OVERVIEW
NOTE: This section describes the AGP bus in general. For a detailed description of
AGP bus operations refer to the AGP Interface Specification available at the following
AGP forum web site: http://www.agpforum.org/index.htm
The Accelerated Graphics Port (AGP) bus is specifically designed as an economical yet high-
performance interface for 3D graphics adapters. The AGP interface is designed to give graphics
adapters dedicated pipelined access to system memory for the purpose of off-loading texturing, z-
buffering, and alpha blending used in 3D graphics operations. By off-loading a large portion of
3D data to system memory the AGP graphics adapter only requires enough memory for frame
buffer (display image) refreshing.
4.3.1 BUS TRANSACTIONS
The operation of the AGP bus is based on the 66-MHz PCI specification but includes additional
mechanisms to increase bandwidth. During the configuration phase the AGP bus acts in
accordance with PCI protocol. Once operation with the AGP adapter involves graphics data
handling, AGP-defined protocols take effect. The AGP graphics adapter acts generally as the
AGP master, but can also behave as a “PCI” target during fast writes from the north bridge.
Key differences between the AGP interface and the PCI interface are as follows:
♦
♦
Address phase and associated data transfer phase are disconnected transactions. Addressing
and data transferring occur as contiguous actions on the PCI bus. On the AGP bus a request
for data and the transfer of data may be separated by other operations.
Commands on the AGP bus specify system memory accesses only. Unlike the PCI bus,
commands involving I/O and configuration are not required or allowed. The system memory
address space used in AGP operations is the same linear space used by PCI memory space
commands, but is further specified by the graphics address re-mapping table (GART) of the
north bridge component.
♦
♦
Data transactions on the AGP bus involve eight bytes or multiples of eight bytes. The AGP
memory addressing protocol uses 8-byte boundaries as opposed to PCI’s 4-byte boundaries. If
a transfer of less than eight bytes is needed, the remaining bytes are filled with arbitrary data
that is discarded by the target.
Pipelined requests are defined by length or size on the AGP bus. The PCI bus defines
transfer lengths with the FRAME- signal.
There are two basic types of transactions on the AGP bus: data requests (addressing) and data
transfers. These actions are separate from each other.
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Chapter 4 System Support
4.3.1.1 Data Request
Requesting data is accomplished in one of two ways; either multiplexed addressing (using the
AD lines for addressing/data) or demultiplexed (“sideband”) addressing (using the SBA lines for
addressing only and the AD lines for data only). Even though there are only eight SBA lines (as
opposed to the 32 AD lines) sideband addressing maximizes efficiency and throughput by
allowing the AD lines to be exclusively used for data transfers. Sideband addressing occurs at
the same rate (1X or 2X) as data transfers. The differences in rates will be discussed in the next
section describing data transfers. Note also that sideband addressing is limited to 48 bits (address
bits 48-63 are assumed zero).
The north bridge supports both SBA and AD addressing methods and all three data transfer
rates, but the method and rate is selected by the AGP graphics adapter.
4.3.1.2 Data Transfers
Data transfers use the AD lines and occur as the result of data requests described previously.
Each transaction resulting from a request involves at least eight bytes, requiring the 32 AD lines
to handle at least two transfers per request. The 443BX supports two transfer rates: 1X and 2X.
Regardless of the rate used, the speed of the bus clock is constant at 66 MHz. The following
subsections describe how the use of additional strobe signals makes possible higher transfer rates.
AGP 1X Transfers
In AGP 1X transfers the 66-MHz CLK signal is used to qualify the control and data signals.
Each 4-byte data transfer is synchronous with one CLK cycle so it takes two CLK cycles for a
minimum 8-byte transfer (Figure 4-5 shows two 8-byte transfers). The GNT- and TRDY- signals
retain their traditional PCI functions. The ST0..3 signals are used for priority encoding, with
“000” for low priority and “001” indicating high priority.
T1
T2
T3
T4
T5
T6
T7
CLK
AD
D1A
xxx
D1B
xxx
D2A
D2B
xxx
GNT-
TRDY-
ST0..2
xxx
00x
xxx
Figure 4–5. AGP 1X Data Transfer (Peak Transfer Rate: 266 MB/s)
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AGP 2X Transfers
In AGP 2X transfers, clocking is basically the same as in 1X transfers except that the 66-MHz
CLK signal is used to qualify only the control signals. The data bytes are latched by an additional
strobe (AD_STBx) signal so that an 8-byte transfer occurs in one CLK cycle (Figure 4-6). The
first four bytes (DnA) are latched by the receiving agent on the falling edge of AD_STBx and the
second four bytes (DnB) are latched on the rising edge of AD_STBx.
T1
T2
T3
T4
T5
T6
T7
CLK
AD
D1A D1B D2A D2B D3A D3B D4A D4B
AD_STBx
GNT-
TRDY-
ST0..2
xxx
xxx
xxx
xxx
00x
xxx
Figure 4–6. AGP 2X Data Transfer (Peak Transfer Rate: 532 MB/s)
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Chapter 4 System Support
4.3.2 AGP CONFIGURATION
AGP bus operations require the configuration of certain parameters involving system memory
access by the AGP graphics adapter. The AGP bus interface is configured as a PCI device
integrated within the north bridge (82443, device 1) component. The AGP function is, from the
PCI bus perspective, treated essentially as a PCI/PCI bridge and configured through PCI
configuration registers (Table 4-7). Configuration is accomplished by BIOS during POST.
NOTE: Configuration of the AGP bus interface involves functions 0 and 1 of the
82443. Function 0 registers (listed in Table 3-4) include functions that affect basic
control (GART) of the AGP.
Table 4-7.
PCI/AGP Bridge Function Configuration Registers
(82443BX, Function 1)
PCI Config.
Addr.
00, 01h
02, 03h
04, 05h
06, 07h
08h
0A, 0Bh
0Eh
18h
Reset
Value
8086h
7191h
0000h
0220h
00h
0406h
01h
00h
PCI Config.
Addr.
1Bh
1Ch
1Dh
1E, 1Fh
20, 21h
22, 23h
24, 25h
26, 27h
3Eh
Reset
Value
00h
F0h
00h
02A0h
FFF0h
0000h
FFF0h
0000h
80h
Register
Vender ID
Device ID
Command
Status
Revision ID
Class Code
Header Type
Primary Bus Number
Secondary Bus Number
Subordinate Bus Number
Register
Sec. Master Latency Timer
I/O Base Address
I/O Limit Address
Sec. PCI/PCI Status
Memory Base Address
Memory Limit Address
Prefetch Mem. Base Addr.
Prefetch Mem. Limit Addr.
PCI/PCI Bridge Control
Reserved
19h
1Ah
00h
00h
3F-FFh
00h
NOTE:
Assume unmarked locations/gaps as reserved. Refer to Intel documentation for detailed
register descriptions.
The AGP graphics adapter (actually its resident controller) is configured as a standard PCI
device.
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4.3.3 AGP CONNECTOR
A66
A1
A21 A26
B66
B1
B21 B26
Figure 4–7. AGP Bus Connector
Table 4-8.
AGP Bus Connector Pinout
Pin
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
20
21
22
A Signal
+12 VDC
RSVD
GND
USBN
GND
INTA-
RESET
GNT-
VDD3
ST1
RSVD
PIPE-
GND
RSVD
SBA1
VDD3
SBA3
RSVD
GND
SBA5
SBA7
(Key)
B Signal
OVRCNT-
VDD
VDD
USBF
GND
INTB-
CLK
REQ-
VDD3
ST0
Pin
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
A Signal
(Key)
(Key)
(Key)
B Signal
(Key)
(Key)
(Key)
Pin
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
A Signal
VDD3
TRDY-
STOP-
PME-
GND
PAR
PAD15
NC
PAD13
PAD11
GND
PAD09
CBE0-
NC
RSVD
PAD06
GND
PAD04
PAD02
NC
B Signal
VDD3
DEVSEL-
NC
PERR-
GND
SERR-
CBE1-
NC
PAD14
PAD12
GND
PAD10
PAD08
NC
AD_STB0
PAD07
GND
PAD05
PAD03
NC
PAD01
RSVD
PAD30
PAD28
VDD3
PAD26
PAD24
GND
RSVD
CBE3-
NC
PAD22
PAD20
GND
PAD18
PAD16
NC
PAD31
PAD29
VDD3
PAD27
PAD25
GND
AD_STB1
PAD23
NC
PAD21
PAD19
GND
PAD17
CBE2-
NC
ST2
RBF-
GND
RSVD
SBA0
VDD3
SBA2
SB_STB
GND
SBA4
DBA6
(Key)
FRAME-
RSVD
GND
IRDY-
RSVD
GND
PAD00
RSVD
RSVD
RSVD
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Chapter 4 System Support
4.4
ISA BUS OVERVIEW
NOTE: This section describes the ISA bus in general and highlights bus
implementation in this particular system. For detailed information regarding ISA bus
operation, refer to the Compaq Extended Industry Standard Architecture (EISA)
Technical Reference Guide.
The industry standard architecture (ISA) bus provides an 8-/16-bit path for standard I/O
peripherals as well as for optional devices that can be installed in the ISA expansion slots. Figure
4-8 shows the key functions and devices that reside on the ISA bus.
PCI Bus
82371 South Bridge
ISA Connector 2
ISA Connector 1
BIOS
ROM
PCI/ISA
Bridge Function
8-/16-Bit ISA Bus
PC 87307B I/O Controller
Keyboard/
Mouse I/F
Diskette
I/F
Serial
I/F (2)
Parallel
I/F
Figure 4–8. ISA Bus Block Diagram
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4.4.1 ISA CONNECTOR
16-Bit ISA Connection
8-Bit ISA Connection
D1
B1
C1
A1
Figure 4–9. ISA Expansion Connector
Table 4-9.
ISA Expansion Connector Pinout
16-Bit ISA Interface
8-Bit ISA Interface
Pin
Signal
GND
Pin
Signal
I/O CHK-
SD7
SD6
SD5
SD4
SD3
SD2
SD1
Pin
Signal
M16-
Pin
Signal
SBHE-
LA23
LA22
LA21
LA20
LA19
LA18
LA17
MRDC-
MWTC-
SD8
B01
B02
B03
B04
B05
B06
B07
B08
B09
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
A01
A02
A03
A04
A05
A06
A07
A08
A09
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
D01
D02
D03
D04
D05
D06
D07
D08
D09
D10
D11
D12
D13
D14
D15
D16
D17
D18
C01
C02
C03
C04
C05
C06
C07
C08
C09
C10
C11
C12
C13
C14
C15
C16
C17
C18
RESDRV
+5 VDC
IRQ9
-5 VDC
DRQ2
-12 VDC
NOWS-
+12 VDC
GND
SMWTC-
SMRDC-
IOWC-
IORC-
DAK3-
DRQ3
DAK1
DRQ1
REFRESH-
BCLK
IRQ7
IRQ6
IRQ5
IRQ4
IRQ3
DAK2-
T-C
BALE
+5 VDC
OSC
I/O16-
IRQ10
IRQ11
IRQ12
IRQ15
IRQ14
DAK0-
DRQ0
DAK5-
DRQ5
DAK6-
DRQ6
DAK7-
DRQ7
+5 VDC
GRAB-
GND
SD0
BUSRDY
DMA
SA19
SA18
SA17
SA16
SA15
SA14
SA13
SA12
SA11
SA10
SA9
SA8
SA7
SA6
SA5
SA4
SA3
SA2
SA1
SD9
SD10
SD11
SD12
SD13
SD14
SD15
GND
SA0
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Chapter 4 System Support
4.4.2 ISA BUS TRANSACTIONS
The ISA bus supports 8- and 16-bit transfers at an 8-MHz rate. Devices limited to 8-bit transfers
use the lower byte portion (data lines 7..0) while 16-bit transfers use the full bandwidth (data
lines 15..0). Addressing is handled by two classifications of address signals: latched and
latchable. Latched address signals ( SA19..0) select the specific byte within the 1-MB section of
memory defined by address lines LA23..17. Latchable address lines (LA23..17) provide a longer
setup time for pre-chip selection or for pre-address decoding for high-speed memory and allow
access to up to 16 megabytes of physical memory on the ISA bus. The SA19..17 signals have the
same values as the LA19..17 signals for all memory cycles. The I/O cycles use only the SA15..0
signals.
The key control signals are described as follows:
♦
♦
MRDC- (Memory Read Cycle): MRDC- is active on all ISA memory reads accessing
memory from 000000h to FFFFFFh.
SMEMR- (System Memory Read): SMEMR- is asserted by the PCI/ISA bridge to request an
ISA memory device to drive data onto the data lines for accesses below one megabyte.
SMEMR- is a delayed version of MRDC-.
♦
♦
MWTC- (Memory Write Cycle): MWTC- is active on all ISA memory write cycles accessing
memory from 000000h to FFFFFFh.
SMEMW- (System Memory Write): SMEMW- is asserted by the PCI/ISA bridge to request
an ISA memory device to accept data from the data lines for access below one megabyte.
SMEMW- is a delayed version of MWTC-.
♦
♦
♦
♦
♦
♦
IORC- (Input/Output Read Cycle): IORC- commands an ISA I/O device to drive data onto
the data lines.
IOWC- (Input/Output Write Cycle): IOWC- commands an ISA I/O device to accept data
from the data lines.
SBHE- (System Byte High Enable): SBHE- indicates that a byte is being transferred on the
upper half (D15..8) of the data lines.
SA0- (System Address Bit <0>): This bit is the complement of SBHE- and indicates that a
byte is being transferred on the lower half (D7..0) of the data lines.
M16- (16-bit Memory Cycle): M16- is asserted by 16-bit ISA devices to indicate 16-bit
memory cycle capability.
IO16- (16-bit I/O Cycle): IO16- is asserted by 16-bit ISA devices to indicate 16-bit I/O cycle
transfer capability.
If the address on the SA lines is above one megabyte, SMRDC- and SMWTC- will not be active.
The MRDC- and MWTC- signals are active for memory accesses up to 16 megabytes and can be
used by any device that uses the full 16-bit ISA bus. To request a 16-bit transfer, a device asserts
either the M16- (memory) or IO16- (I/O) signal when the device is addressed.
When another device (such as a DMA device or another bus master) takes control of the ISA, the
Bus Address Latch Enable (BALE) signal is held active for the duration of the operation. As a
result, signals LA23..17 are always enabled and must be held stable for the duration of each bus
cycle.
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When the address changes, devices on the bus may decode the latchable address (LA23..17) lines
and then latch them. This arrangement allows devices to decode chip selects and M16- before the
next cycle actually begins.
The following guidelines apply to optional ISA devices installed in the system:
♦
♦
♦
♦
On bus lines that can be driven by a controller board, the driver should be able to sink a
minimum of 20 ma at 0.5 VDC and source 2 ma at 3.75 VDC.
On bus lines that are driven in the low direction only (open collector), the driver should be
able to sink 20 ma at 0.5 VDC.
The load on any logic line from a single bus slot should not exceed 2.0 ma in the low state
(at 0.5 VDC) or 0.1 ma in the high state (at 3.75 VDC).
The logic-high voltage at the bus ranges from 3.75 VDC to 5.5 VDC. The logic low voltage
ranges from 0 VDC to 0.8 VDC.
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Chapter 4 System Support
4.4.3 DIRECT MEMORY ACCESS
Direct Memory Access (DMA) is a method by which an ISA device accesses system memory
without involving the microprocessor. DMA is normally used to transfer blocks of data to or from
an ISA I/O device. DMA reduces the amount of CPU interactions with memory, freeing the CPU
for other processing tasks.
NOTE: This section describes DMA in general. For detailed information regarding
DMA operation, refer to the Compaq Extended Industry Standard Architecture (EISA)
Technical Reference Guide. Note, however, that EISA enhancements as described in the
referenced document are not supported in this (ISA only) system.
The South Bridge component includes the equivalent of two 8237 DMA controllers cascaded
together to provide eight DMA channels. Table 4-10 lists the default configuration of the DMA
channels.
Table 4-10.
Default DMA Channel Assignments
DMA Channel
Device ID
Controller 1 (byte transfers)
0
Spare & ISA conn. pins D8, D9
1
2
3
Audio subsystem & ISA conn. pins B17, B18
Diskette drive & ISA conn. pins B6, B26
ECP LPT1 & ISA conn. pins B15, B16
Controller 2 (word transfers)
4
5
6
7
Cascade for controller 1
Spare & ISA conn. pins D10, D11
Spare & ISA conn. pins D12, D13
Spare & ISA conn. pins. D14, D15
All channels in DMA controller 1 operate at a higher priority than those in controller 2. Note
that channel 4 is not available for use other than its cascading function for controller 1. The
DMA controller 2 can transfer words only on an even address boundary. The DMA controller
and page register define a 24-bit address that allows data transfers within the address space of
the CPU. The DMA controllers operate at 8 MHz.
The DMA logic is accessed through two types of I/O mapped registers; page registers and
controller registers. The mapping is the same regardless of the support chipset used.
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4.4.3.1 Page Registers
The DMA page register contains the eight most significant bits of the 24-bit address and works
in conjunction with the DMA controllers to define the complete (24-bit)address for the DMA
channels. Table 4-11 lists the page register port addresses.
Table 4-11.
DMA Page Register Addresses
DMA Channel
Page Register I/O Port
Controller 1 (byte transfers)
Ch 0
Ch 1
Ch 2
Ch 3
087h
083h
081h
082h
Controller 2 (word transfers)
Ch 4
Ch 5
n/a
08Bh
Ch 6
089h
Ch 7
08Ah
Refresh
08Fh [see note]
NOTE:
The DMA memory page register for the refresh channel must be
programmed with 00h for proper operation.
The memory address is derived as follows:
24-Bit Address - Controller 1 (Byte Transfers)
8-Bit Page Register
A23..A16
8-Bit DMA Controller
A15..A00
24-Bit Address - Controller 2 (Word Transfers)
8-Bit Page Register
A23..A17
16-Bit DMA Controller
A16..A01, (A00 = 0)
Note that address line A16 from the DMA memory page register is disabled when DMA
controller 2 is selected. Address line A00 is not connected to DMA controller 2 and is always 0
when word-length transfers are selected.
By not connecting A00, the following applies:
♦
♦
The size of the the block of data that can be moved or addressed is measured in 16-bits
(words) rather than 8-bits (bytes).
The words must always be addressed on an even boundary.
DMA controller 1 can move up to 64 Kbytes of data per DMA transfer. DMA controller 2 can
move up to 64 Kwords (128 Kbytes) of data per DMA transfer. Word DMA operations are only
possible between 16-bit memory and 16-bit peripherals.
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Chapter 4 System Support
The RAM refresh is designed to perform a memory read cycle on each of the 512 row addresses
in the DRAM memory space. Refresh operations are used to refresh memory on the 32-bit
memory bus and the ISA bus. The refresh address is provided on lines SA00 through SA08.
Address lines LA23..17, SA18,19 are driven low.
The remaining address lines are in an undefined state during the refresh cycle. The refresh
operations are driven by a 69.799-KHz clock generated by Interval Timer 1, Counter 1. The
refresh rate is 128 refresh cycles in 2.038 ms.
4.4.3.2 DMA Controller Registers
Table 4-12 lists the DMA Controller Registers and their I/O port addresses. Note that there is a
set of registers for each DMA controller.
Table 4-12.
DMA Controller Registers
Register
Status
Command
Mode
Write Single Mask Bit
Write All Mask Bits
Controller 1
008h
008h
00Bh
00Ah
00Fh
009h
000h
000h
001h
001h
002h
002h
003h
003h
004h
004h
005h
005h
006h
006h
007h
007h
00Dh
00Ch
00Dh
00Eh
Controller 2
0D0h
0D0h
0D6h
0D4h
0DEh
0D2h
0C0h
0C0h
0C2h
0C2h
0C4h
0C4h
0C6h
0C6h
0C8h
0C8h
0CAh
0CAh
0CCh
0CCh
0CEh
0CEh
0DAh
0D8h
0DAh
0DCh
R/W
R
W
W
W
W
W
W
R
W
R
W
R
W
R
W
R
W
R
W
R
Software DRQx Request
Base and Current Address - Ch 0
Current Address - Ch 0
Base and Current Word Count - Ch 0
Current Word Count - Ch 0
Base and Current Address - Ch 1
Current Address - Ch 1
Base and Current Word Count - Ch 1
Current Word Count - Ch 1
Base and Current Address - Ch 2
Current Address - Ch 2
Base and Current Word Count - Ch 2
Current Word Count - Ch 2
Base and Current Address - Ch 3
Current Address - Ch 3
Base and Current Word Count - Ch 3
Current Word Count - Ch 3
Temporary (Command)
Reset Pointer Flip-Flop (Command)
Master Reset (Command)
Reset Mask Register (Command)
NOTE:
W
R
R
W
W
W
For a detailed description of the DMA registers, refer to the Compaq EISA Technical Reference Guide.
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4.4.4 INTERRUPTS
The microprocessor uses two types of interrupts; maskable and nonmaskable. A maskable
interrupt can be enabled or disabled within the microprocessor by the use of the STI and CLI
instructions. A nonmaskable interrupt cannot be masked off within the microprocessor but may
be inhibited by hardware or software means external to the microprocessor.
4.4.4.1 Maskable Interrupts
The maskable interrupt is a hardware-generated signal used by peripheral functions within the
system to get the attention of the microprocessor. Peripheral functions produce a unique INTA-D
(PCI) or IRQ0-15 (ISA) signal that is routed to interrupt processing logic that asserts the
interrupt (INTR) input to the microprocessor. The microprocessor halts execution to determine
the source of the interrupt and then services the peripheral as appropriate.
IRQ1,3..7,
South Bridge Component
IRQ1,3..7
9..12,
14,15
ISA Peripherals
& SM Functions
Interrupt
Cntlr. 1
INTR
IRQ9..12,
14,15
Microprocessor
IRQ2
Interrupt
Cntlr. 2
INTA-..D-
PCI IRQ
Routing
PCI Peripherals
Figure 4–10. Maskable Interrupt Processing, Block Diagram
The South Bridge component, which includes the equivalent of two 8259 interrupt controllers
cascaded together, handles the standard AT-type (ISA) interrupt signals (IRQn). The South
Bridge also receives the PCI interrupt signals (PINTA-..PINTD-) from PCI devices. The PCI
interrupts can be configured by PCI Configuration Registers 60h..63h to share the standard ISA
interrupts (IRQn). The power-up default configuration has the PIRQn disabled. Table 4-13 lists
the standard source configuration for maskable interrupts and their priorities. If more than one
interrupt is pending, the highest priority (lowest number) is processed first.
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Table 4-13.
Maskable Interrupt Priorities and Assignments
Priority
1
2
Signal Label
IRQ0
Source (Typical)
Interval timer 1, counter 0
Keyboard
IRQ1
3
4
5
6
7
8
9
10
11
12
13
14
15
--
IRQ8-
IRQ9
Real-time clock
Spare and ISA connector pin B04
Spare and ISA connector pin D03
Spare and ISA connector pin D04
Mouse and ISA connector pin D05
Coprocessor (math)
IDE primary I/F and ISA connector pin D07
IDE secondary I/F and ISA connector pin D06
Serial port (COM2) and ISA connector pin B25
Serial port (COM1) and ISA connector pin B24
Audio subsystem and ISA connector pin B23
Diskette drive controller and ISA connector pin B22
Parallel port (LPT1)
IRQ10
IRQ11
IRQ12
IRQ13
IRQ14
IRQ15
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
IRQ2
NOT AVAILABLE (Cascade from interrupt controller 2)
Interrupts generated by PCI devices can be configured to share the standard AT (IRQn) interrupt
lines. Refer to section 4.2.5 “PCI Interrupt Mapping” for information on PCI interrupts.
Maskable Interrupt processing is controlled and monitored through standard AT-type I/O-
mapped registers. These registers are listed in Table 4-14.
Table 4-14.
Maskable Interrupt Control Registers
I/O Port
020h
Register
Base Address, Int. Cntlr. 1
021h
0A0h
0A1h
Initialization Command Word 2-4, Int. Cntlr. 1
Base Address, Int. Cntlr. 2
Initialization Command Word 2-4, Int. Cntlr. 2
The initialization and operation of the interrupt control registers follows standard AT-type
protocol.
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4.4.4.2 Non-Maskable Interrupts
Non-maskable interrupts cannot be masked (inhibited) within the microprocessor itself but may
be maskable by software using logic external to the microprocessor. There are two non-maskable
interrupt signals: the NMI- and the SMI-. These signals have service priority over all maskable
interrupts, with the SMI- having top priority over all interrupts including the NMI-.
NMI- Generation
The Non-Maskable Interrupt (NMI-) signal can be generated by one of the following actions:
♦
♦
♦
Parity errors detected on the ISA bus (activating IOCHK-).
Parity errors detected on a PCI bus (activating SERR- or PERR-).
Microprocessor internal error (activating IERRA or IERRB)
The IOCHK-, SERR-, and PERR- signals are routed through the south bridge component, which
in turn activates the NMI to the microprocessor.
The NMI Status Register at I/O port 061h contains NMI source and status data as follows:
NMI Status Register 61h
Bit
Function
7
NMI Status:
0 = No NMI from system board parity error.
1 = NMI requested, read only
6
IOCHK- NMI:
0 = No NMI from IOCHK-
1 = IOCHK- is active (low), NMI requested, read only
Interval Timer 1, Counter 2 (Speaker) Status
Refresh Indicator (toggles with every refresh)
IOCHK- NMI Enable/Disable:
5
4
3
0 = NMI from IOCHK- enabled
1 = NMI from IOCHK- disabled and cleared (R/W)
System Board Parity Error (PERR/SERR) NMI Enable:
0 = Parity error NMI enabled
2
1 = Parity error NMI disabled and cleared (R/W)
Speaker Data (R/W)
Inteval Timer 1, Counter 2 Gate Signal (R/W)
0 = Counter 2 disabled
1
0
1 = Counter 2 enabled
Functions not related to NMI activity.
After the active NMI has been processed, status bits <7> or <6> are cleared by pulsing bits <2>
or <3> respectively.
The NMI Enable Register (070h, <7>) is used to enable/disable the NMI signal. Writing 80h to
this register masks generation of the NMI-. Note that the lower six bits of register at I/O port 70h
affect RTC operation and should be considered when changing NMI- generation status.
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Chapter 4 System Support
SMI- Generation
The SMI- (System Management Interrupt) is typically used for power management functions.
When power management is enabled, inactivity timers are monitored. When a timer times out,
SMI- is asserted and invokes the microprocessor’s SMI handler. The SMI- handler works with
the APM BIOS to service the SMI- according to the cause of the timeout.
Although the SMI- is primarily used for power managment the interrupt is also employed for the
QuickLock/QuickBlank functions as well.
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4.4.5 INTERVAL TIMER
The interval timer generates pulses at software (programmable) intervals. A 8254-compatible
timer is integrated into the South Bridge chip. The timer function provides three counters, the
functions of which are listed in Table 4-15.
Table 4-15.
Interval Timer Functions
Counter
Function
System Clock
Refresh
Gate
Clock In
1.193 MHz
1.193 MHz
1.193 MHz
Clock Out
IRQ0
Refresh Req.
Speaker Input
0
1
2
Always on
Always on
Port 61, bit<0>
Speaker Tone
The interval timer is controlled through the I/O mapped registers listed in Table 4-16.
Table 4-16.
Interval Timer Control Registers
I/O Port
040h
041h
042h
043h
Register
Read or write value, counter 0
Read or write value, counter 1
Read or write value, counter 2
Control Word
Interval timer operation follows standard AT-type protocol. For a detailed description of timer
registers and operation, refer to the Compaq Extended Industry Standard Architecture Expansion
Bus Technical Reference Guide.
4.4.6 ISA CONFIGURATION
The working relationship between the PCI and ISA buses requires that certain parameters be
configured. The PC/ISA bridge function of the South Bridge component includes configuration
registers to set parameters such as PCI IRQ routing and top-of-memory available to ISA/DMA
devices. These parameters are programmed by BIOS during power-up, using registers listed
previously in Table 4-6.
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Chapter 4 System Support
4.5
SYSTEM CLOCK DISTRIBUTION
The system uses a Cypress CY2280 or compatible part for generation of most clock signals.
Table 4-17 lists the system board clock signals and how they are distributed.
Table 4-17.
Clock Generation and Distribution
Frequncy/Signal
Source
Destination
66, 100 MHz
(CPUCLK) [1]
66 MHz
CY2280
Processor, 82443 N. Bridge
North Bridge
“
AGP Slot
48 MHz
82371 S. Bridge, 87307 I/O Cntlr.
PCI Slots, 82371 S. Bridge
W48C67
South Bridge, ISA slots
ISA slots
33 MHz (PCICLK)
14.31818 MHz
14.31818 MHz
8.33 MHz (BCLK)
32.77 KHz
“
Crystal
CY2280
South Bridge
Crystal
South Bridge
NOTE:
[1] Depending on processor speed (refer to
Chapter 3, “Processor/Memory Subsystem”).
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4.6
REAL-TIME CLOCK AND CONFIGURATION MEMORY
The Real-time clock (RTC) and configuration memory functions are provided by the PC87307
I/O controller. The RTC uses the first 14 of 256 bytes of configuration memory and is
MC146818-compatible. As shown in the following figure, the 87307 controller provides 256
bytes of configuration memory, divided into two 128-byte banks. The RTC/configuration memory
can be accessed using conventional OUT and IN assembly language instructions using I/O ports
70h/71h, although the suggested method is to use the INT15 AX=E823h BIOS call.
87307
Register D
Register C
Register B
Register A
Year
Month
0Dh
0Ch
0Bh
FFh
Upper Config.
Memory Area
(128 bytes)
0Ah
09h
08h
07h
06h
05h
04h
03h
02h
01h
00h
80h
7Fh
Date of Month
Day of Week
Hours (Alarm)
Hours (Timer)
Minutes (Alarm)
Minutes (Timer)
Seconds (Alarm)
Seconds (Timer)
Lower Config.
Memory Area
(114 bytes)
0Eh
0Dh
RTC Area
(14 bytes)
00h
CMOS
Figure 4–11. Configuration Memory Map
A lithium 3-VDC battery is used for maintaining the RTC and configuration memory while the
system is powered down. During system operation a wire-Ored circuit allows the RTC and
configuration memory to draw power from the power supply.
The battery is located in a battery holder on the system board and has a life expectancy of four to
eight years. When the battery has expired it is replaced with a Renata CR2032 or equivalent 3-
VDC lithium battery.
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Table 4-18 lists the mapping of the configuration memory. Locations 00h-3Fh may be accessed
using OUT/IN assembly language instructions or BIOS function INT15, AX=E823h. All other
locations should be accessed using the INT15, AX=E845h function (refer to Chapter 8 for BIOS
function descriptions).
Table 4-18.
Configuration Memory (CMOS) Map
Location
00-0Dh
0Eh
Function
Real-time clock
Diagnostic status
Location
41h-44h
45h
Function
Hood Removal Time Stamp
Keyboard snoop byte
0Fh
System reset code
46h
Diskette drive status
10h
Diskette drive type
47h
Last IPL device
11h
12h
13h
Reserved
Hard drive type
Security functions
48h-4Bh
4Ch-4Fh
51h
IPL priority
BVC priority
ECC DIMM status
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
24h
Equipment installed
52h
53h
54h
55h
Board revision (from boot block)
SWSMI command
SWSMI data
Base memory size, low byte/KB
Base memory size, high byte/KB
Extended memory, low byte/KB
Extended memory, high byte/KB
Hard drive 1, primary controller
Hard drive 2, primary controller
Hard drive 1, secondary controller
Hard drive 2, secondary controller
Enhanced hard drive support
Reserved
APM command
56h
Erase-Ease keyboard byte
Saved CMOS location 10h-2Fh
Administrator password
ECMOS diagnostic byte
Total super ext. memory tested good
Microprocessor chip ID
Microprocessor chip revision
Hood removal status byte
Fast boot date
57h-76H
77h-7Fh
80h
81h-82h
83h
84h
85h
86h
Power management functions
System board ID
25h
26h
27h
28h
29h
2Ah
2Bh
2Ch
2Dh
2Eh-2Fh
30h-31h
32h
33h
34h
35h
System architecture data
Auxiliary peripheral configuration
Speed control external drive
Expanded/base mem. size, IRQ12
Miscellaneous configuration
Hard drive timeout
System inactivity timeout
Monitor timeout, Num Lock Cntrl
Additional flags
Checksum of locations 10h-2Dh
Total extended memory tested
Century
Miscellaneous flags set by BIOS
International language
APM status flags
87h
Fast boot status byte
POST error logging
8Dh-8Fh
90h-91h
92h
93h
94h
97h
9Bh
9Ch
9Dh
Total super extended memory configured
Miscellaneous configuration byte
Miscellaneous PCI features
ROM flash/power button status
Asset/test prompt byte
Ultra-33 DMA enable byte
Mode-2 Configuration
ESS audio configuration
ECP DMA configuration
Serial number
9Eh
9Fh-AFh
B0h-C3h
C7h
Custom drive types 65, 66, 68, 15
Serial port 1 address
Serial port 2 address
C8h
36h
37h-3Fh
40h
ECC POST test single bit
Power-on password
Miscellaneous Disk Bits
C9h
DEh-DFh
E0h-FFh
COM1/COM2 port configuration
Checksum of locations 90h to DDh
Client Management error log
NOTE:
Assume unmarked gaps are reserved.
The contents of configuration memory (including the password) can be cleared by the following
procedure:
1. Turn off unit and disconnect AC power cord from the rear chassis connector.
2. Remove jumper from pins 1 and 2 of header E50 and place on pins 2 and 3 for 15 seconds.
3. Replace jumper to original configuration (pins 1 and 2).
4. Re-connect AC power cord to the chassis and turn unit on.
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RTC Control Register A, Byte 0Ah
Bit
Function
7
Update in Progress. Read only.
0 = Time update will not occur before 2444 us
1 = Time update will occur within 2444 us
Divider Chain Control. R/W.
00x = Oscillator disabled.
010 = Normal operation (time base frequency = 32.768 KHz).
11x = Divider chain reset.
6..4
3..0
Periodic Interrupt Control. R/W. Specifies the periodic interrupt interval.
0000 = none
1000 = 3.90625 ms
1001 = 7.8125 ms
1010 = 15. 625 ms
1011 = 31.25 ms
1100 = 62.50 ms
1101 = 125 ms
0001 = 3.90625 ms
0010 = 7.8125 ms
0011 = 122.070 us
0100 = 244.141 us
0101 = 488.281 us
0110 = 976.562 us
0111 = 1.953125 ms
1110 = 250 ms
1111 = 500 ms
RTC Control Register B, Byte 0Bh
Bit
Function
7
Time Update Enable/disable
0 = Normal operation, 1 = Disable time updating for time set
Periodic Interrupt Enable/Disable.
6
5
4
0 = Disable,
1 = Enable interval specified by Register A
Alarm Interrupt Enable/disable
0 = Disabled, 1 = Enabled
End-of-Update Interrupt Enable/Disable
0 = Disabled, 1 = Enabled
Reserved (read 0)
3
2
Time/Date Format Select
0 = BCD format, 1 = Binary format
Time Mode
1
0
0 = 12-hour mode, 1 = 24-hour mode
Automatic Daylight Savings Time Enable/Disable
0 = Disable
1 = Enable (Advance 1 hour on 1st Sunday in April, retreat 1 hour on last Sunday in October).
RTC Status Register C, Byte 0Ch
Bit
7
6
5
4
Function
If set, interrupt output signal active (read only)
If set, indicates periodic interrupt flag
If set, indicates alarm interrupt
If set, indicates end-of-update interrupt
Reserved
3..0
RTC Status Register D, Byte 0Dh
Bit
Function
7
RTC Power Status
0 = RTC has lost power
1 = RTC has not lost power
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6..0
Reserved
Configuration Byte 0Eh, Diagnostic Status
Default Value = 00h
This byte contains diagnostic status data.
Configuration Byte 0Fh, System Reset Code
Default Value = 00h
This byte contains the system reset code.
Configuration Byte 10h, Diskette Drive Type
Bit
7..4
3..0
Function
Primary (Drive A) Diskette Drive Type
Secondary (Drive B) Diskette Drive Type
Valid values for bits <7..4> and bits <3..0>:
0000 = Not installed
0001 = 360-KB drive
0010 = 1.2-MB drive
0011 = 720-KB drive
0100 = 1.44-MB/1.25-MB drive
0110 = 2.88-MB drive
(all other values reserved)
Configuration Byte 12h, Hard Drive Type
Bit
Function
7..4
Primary Controller 1, Hard Drive 1 Type:
0000 = none
1000 = Type 8
0001 = Type 1
0010 = Type 2
0011 = Type 3
0100 = Type 4
0101 = Type 5
0110 = Type 6
0111 = Type 7
1001 = Type 9
1010 = Type 10
1011 = Type 11
1100 = Type 12
1101 = Type 13
1110 = Type 14
1111 = other (use bytes 19h)
3..0
Primary Controller 1, Hard Drive 2 Type:
0000 = none
1000 = Type 8
0001 = Type 1
0010 = Type 2
0011 = Type 3
0100 = Type 4
0101 = Type 5
0110 = Type 6
0111 = Type 7
1001 = Type 9
1010 = Type 10
1011 = Type 11
1100 = Type 12
1101 = Type 13
1110 = Type 14
1111 = other (use bytes 1Ah)
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Configuration Byte 13h, Security Functions
Default Value = 00h
Bit
7
Function
Reserved
6
QuickBlank Enable After Standby:
0 = Disable
1 = Enable
5
Administrator Password:
0 = Not present
1 = Present
4
3
Reserved
Diskette Boot Enable:
0 = Enable
1 = Disable
2
1
0
QuickLock Enable:
0 = Disable
1 = Enable
Network Server Mode/Security Lock Override:
0 = Disable
1 = Enable
Password State (Set by BIOS at Power-up)
0 = Not set
1 = Set
Configuration Byte 14h, Equipment Installed
Default Value (standard configuration) = 03h
Bit
Function
7,6
No. of Diskette Drives Installed:
00 = 1 drive
01 = 2 drives
10 = 3 drives
11 = 4 drives
5..2
1
Reserved
Coprocessor Present
0 = Coprocessor not installed
1 = Coprocessor installed
Diskette Drives Present
0
0 = No diskette drives installed
1 = Diskette drive(s) installed
Configuration Bytes 15h and 16h, Base Memory Size
Default Value = 280h
Bytes 15h and 16h hold a 16-bit value that specifies the base memory size in 1-KB (1024)
increments. Valid base memory sizes are 512 and 640 kilobytes .
Configuration Bytes 17h and 18h, Extended Memory Size
Bytes 17h and 18h hold a 16-bit value that specifies the extended memory size in 1-KB
increments.
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Chapter 4 System Support
Configuration Bytes 19h-1Ch, Hard Drive Types
Byte 19h contains the hard drive type for drive 1 of the primary controller if byte 12h bits <7..4>
hold 1111b. Byte 1Ah contains the hard drive type for drive 2 of the primary controller if byte
12h bits <3..0> hold 1111b. Bytes1Bh and 1Ch contain the hard drive types for hard drives 1 and
2 of the secondary controller.
Configuration Byte 1Dh, Enhanced IDE Hard Drive Support
Default Value = F0h
Bit
7
6
5
4
Function
EIDE - Drive C (83h)
EIDE - Drive D (82h)
EIDE - Drive E (81h)
EIDE - Drive F (80h)
Reserved
3..0
Values for bits <7..4> :
0 = Disable
1 = Enable for auto-configure
Configuration Byte 1Fh, Power Management Functions
Default Value = 00h
Bit
7..4
3
Function
Reserved
Slow Processor Clock for Low Power Mode
0 = Processor runs at full speed
1 = Processor runs at slow speed
Reserved
2
1
Monitor Off Mode
0 = Turn monitor power off after 45 minutes in standby
1 = Leave monitor power on
Energy Saver Mode Indicator (Blinking LED)
0 = Disable
0
1 = Enable
Configuration Byte 24h, System Board Identification
Default Value = 7Eh
Configuration memory location 24h holds the system board ID.
Configuration Byte 25h, System Architecture Data
Default Value = 0Bh
Bit
7..4
3
Function
Reserved
Unmapping of ROM:
0 = Allowed
1 = Not allowed
2
Reserved
1,0
Diagnostic Status Byte Address
00 = Memory locations 80C00000h-80C00004h
01 = I/O ports 878h-87Ch
11 = neither place
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Configuration Byte 26h, Auxiliary Peripheral Configuration
Default Value = 00h
Bit
Function
7,6
I/O Delay Select
00 = 420 ns (default)
01 = 300 ns
10 = 2600 ns
11 = 540 ns
5
4
3
2
1
0
Alternative A20 Switching
0 = Disable port 92 mode
1 = Enable port 92 mode
Bi-directional Print Port Mode
0 = Disabled
1 = Enabled
Graphics Type
0 = Color
1 = Monochrome
Hard Drive Primary/Secondary Address Select:
0 = Primary
1 = Secondary
Diskette I/O Port
0 = Primary
1 = Secondary
Diskette I/O Port Enable
0 = Primary
1 = Secondary
Configuration Byte 27h, Speed Control/External Drive
Default Value = 00h
Bit
Function
7
Boot Speed
0 = Max MHz
1 = Fast speed
Reserved
6..0
Configuration Byte 28h, Expanded and Base Memory, IRQ12 Select
Default Value = 00h
Bit
Function
7
IRQ12 Select
0 = Mouse
1 = Expansion bus
Base Memory Size:
00 = 640 KB
01 = 512 KB
10 = 256 KB
11 = Invalid
6,5
4..0
Internal Compaq Memory:
00000 = None
00001 = 512 KB
00010 = 1 MB
00011 = 1.5 MB
.
.
11111 = 15.5 MB
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Chapter 4 System Support
Configuration Byte 29h, Miscellaneous Configuration Data
Default Value = 00h
Bit
7..5
4
Function
Reserved
Primary Hard Drive Enable (Non-PCI IDE Controllers)
0 = Disable
1 = Enable
Reserved
3..0
Configuration Byte 2Ah, Hard Drive Timeout
Default Value = 02h
Bit
7..5
4..0
Function
Reserved
Hard Drive Timeout
00000 = Disabled
00001 = 1 minute
00010 = 2 minutes
.
.
10101 = 21 minutes
Configuration Byte 2Bh, System Inactivity Timeout
Default Value = 23h
Bit
7
Function
Reserved
6,5
Power Conservation Boot
00 = Reserved
01 = PC on
10 = PC off
11 = Reserved
4..0
System Inactive Timeout. (Index to SIT system timeout record)
00000 = Disabled
Configuration Byte 2Ch, ScreenSave and NUMLOCK Control
Default Value = 00h
Bit
7
Function
Reserved
6
Numlock Control
0 = Numlock off at power on
1 = Numlock on at power on
Screen Blank Control:
5
0 = No screen blank
1 = Screen blank w/QuickLock
ScreenSave Timeout. (Index to SIT monitor timeout record)
000000 = Disabled
4..0
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Configuration Byte 2Dh, Additional Flags
Default Value = 00h
Bit
7..5
4
Function
Reserved
Memory Test
0 = Test memory on power up only
1 = Test memory on warm boot
POST Error Handling (BIOS Defined)
0 = Display “Press F1 to Continue” on error
1 = Skip F1 message
Reserved
3
2..0
Configuration Byte 2Eh, 2Fh, Checksum
These bytes hold the checksum of bytes 10h to 2Dh.
Configuration Byte 30h, 31h, Total Extended Memory Tested
This location holds the amount of system memory that checked good during the POST.
Configuration Byte 32h, Century
This location holds the Century value in a binary coded decimal (BCD) format.
Configuration Byte 33h, Miscellaneous Flags
Default Value = 80h
Bit
Function
7
Memory Above 640 KB
0 = No, 1 = Yes
6
5
Reserved
Weitek Numeric Coprocessor Present:
0 = Not installed, 1 = Installed
Standard Numeric Coprocessor Present:
0 = Not installed, 1 = Installed
Reserved
4
3..0
Configuration Byte 34h, International Language Support
Default Value = 00h
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Chapter 4 System Support
Configuration Byte 35h, APM Status Flags
Default Value = 11h
Bit
Function
7..6
Power Conservation State:
00 = Ready
01 = Standby
10 = Suspend
11 = Off
5,4
3
Reserved
32-bit Connection:
0 = Disconnected, 1 = Connected
16-bit Connection
0 = Disconnected, 1 = Connected
Real Mode Connection
0 = Disconnected, 1 = Connected
Power Management Enable:
0 = Disabled
2
1
0
1 = Enabled
Configuration Byte 36h, ECC POST Test Single Bit Errors
Default Value = 01h
Bit
7
6
5
4
3
2
1
0
Function
Row 7 Error Detect
Row 6 Error Detect
Row 5 Error Detect
Row 4 Error Detect
Row 3 Error Detect
Row 2 Error Detect
Row 1 Error Detect
Row 0 Error Detect
0 = No single bit error detected.
1 = Single bit error detected.
Configuration Byte 37h-3Fh, Power-On Password
These eight locations hold the power-on password.
Configuration Byte 40h, Miscellaneous Disk Data
Configuration Bytes 41h-44h, Hood Removal Time Stamp
These four bytes record the time at which the hood of the system was removed:
Byte 41h, month & day
Byte 42h, year and month
Byte 43h, minutes and seconds
Byte 44h, removal flag and minutes
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Configuration Byte 45h, Keyboard Snoop Data
Default Value = xxh
Bit
Function
7
Cntrl/F10 Key Status:
0 = Cntrl & F10 keys not pressed
1 = Cntrl & F10 keys pressed
F10 Key Status:
6
0 = F10 key not pressed
1 = F10 key pressed
Reserved
Key Pressed Flag:
0 = Key not pressed
1 = Key pressed
5..1
0
Configuration Byte 46h, Diskette/Hard Drive Status
Default Value = xxh
Bit
7,6
5
Function
Reserved
Partition On HD:
0 = Not set, 1 = Set
Setup Disk:
4
3
2
1
0
0 = Not present, 1 = Present
ROMPAQ or DIAGS Diskette:
0 = Not present, 1 = Present
Boot Diskette in Drive A:
0 = No, 1 = Yes
Drive B: Present:
0 = Not present, 1 = Present
Drive A: Present:
0 = Not present, 1 = Present
Configuration Bytes 47h-4Fh, IPL Data
These bytes hold initial program load (IPL) data for boot purposes:
Byte 47h, last IPL device
Bytes 48h-4Bh, IPL priority
Byte 4Ch-4Fh, BCV priority
Configuration Byte 51h, ECC Status Byte
Default Value = xxh
Bit
7
6
5
4
Function
ECC Status for DIMM 3
ECC Status for DIMM 2
ECC Status for DIMM 1
ECC Status for DIMM 0
Reserved
3..0
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Configuration Byte 52h, Board Revision
This byte holds the board revision as copied from the boot block sector.
Configuration Byte 53h, 54h, SW SMI Command/Data Bytes
Configuration Byte 55h, APM Command Byte
Configuration Byte 56h, Miscellaneous Flags Byte
Bit
Function
7
CAS Latency:
0 = 2, 1 = 3
6
IR Port Enable Flag:
0 = Disabled (COM2 config. for standard serial port)
1 = Enabled (COM2 config. for IrDA)
Warm Boot Enable Flag:
0 = Disable, 1 = Enable
POST Terse/Verbose Mode
0 = Verbose, 1 = Terse
Erase Ease Keyboard Mode:
000 = Backspace/Spacebar
001 = Spacebar/Backspace
010 = Spacebar/Spacebar
011-111 = Invalid
5
4
3..1
0
Configurable Power Supply:
0 = Power switch active
1 = Power switch inhibited
Configuration Byte 57h-76h, CMOS Copy
Configuration Bytes 77h-7Fh, Administrator Password
Configuration Byte 80h, CMOS Diagnostic Flags Byte
Default Value = 00h. Set bit indicates function is valid.
Bit
7
6
Function
CMOS Initialization (Set CMOS to Default)
Setup password locked
5
4
PnP should not reject SETs because Diags is active
Reserved
3
2
1
0
Manufacturing diagnostics diskette found
Invalid electronic serial number
Boot maintenance partition once
Invalid CMOS checksum
Configuration Byte 81h, 82h, Total Super Extended Memory Tested
This byte holds the value of the amount of extended system memory that tested good during
POST. The amount is given in 64-KB increments.
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Configuration Byte 83h, Microprocessor Identification
This byte holds the component ID and chip revision of the microprocessor.
Configuration Byte 84h, Microprocessor Revision
Configuration Byte 85h, Administration Mode
Bit
7,6
5
Function
Reserved
ESCD Buffering:
0 = No buffering, 1 = ESCD buffered at F000h.
Hood Lock Enable:
4
0 = Disabled, 1 = Enabled
User Mode Flag
Administration Mode Flag
Level Support:
3
2
1
0 = Level 1, 1 = Level 2
Feature Support Bit
0 = Disabled, 1 = Enabled
0
Configuration Byte 86h, Fast Boot Date
Configuration Byte 87h, Fast Boot Select
Bit
7..3
2
Function
1
0
Configuration Byte 88h, Fast Boot Date (Year/Century)
Configuration Byte 89h, APM Resume Timer
Bit <7> indicates the timer status: 0 = disabled, 1 = timer set.
Configuration Byte 8Ah-8Fh, APM Resume Timer
These bytes hold the APM timer values:
Byte 8Ah, minutes
Byte 8Bh, hours
Byte 8Ch, day
Byte 8Dh, month
Byte 8Eh, year
Byte 8Fh, century
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Configuration Byte 90h, 91h, Total Super Extended Memory Configured
This byte holds the value of the amount of extended system memory that is configured.
The amount is given in 64-KB increments.
Configuration Byte 92h, Miscellaneous Configuration Byte
Default Value = 18h
Bit
7..5
4
Function
Reserved
Diskette Write Control:
0 = Disable
1 = Enable
3..1
0
Reserved
Diskette Drive Swap Control:
0 = Don’t swap
1 = Swap drive A: and B:
Configuration Byte 93h, PCI Configuration Byte
Default Value = 00h
Bit
Function
7
Onboard SCSI Status:
0 = Hidden
1 = Active
6
5
Onboard NIC Status:
0 = Hidden
1 = Active
Onboard USB Status:
0 = Hidden
1 = Active
3
2
Reserved
ISA Passive Release:
0 = Enabled
1 = Disabled
1
0
PCI Bus Master Enable
0 = Enabled
1 = Disabled
PCI VGA Palette Snoop
0 = Disable
1 = Enable
If palette snooping is enabled, then a primary PCI graphics card may share a common palette
with the ISA graphics card. Palette snooping should only be enabled if all of the following
conditions are met:
♦
♦
♦
♦
An ISA card connects to a PCI graphics card through the VESA connector.
The ISA card is connected to a color monitor.
The ISA card uses the RAMDAC on the PCI card
The palette snooping feature (sometimes called “RAMDAC shadowing”) on the PCI card is
enabled and functioning properly.
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Configuration Byte 94h, ROM Flash/Power Button Status
Default Value = 00h
Bit
7..5
4
Function
Reserved
ROM Flash In Progress (if set)
Reserved
3
2
1
0
Power Button Inhibited (if set)
User-Forced Bootblock (if set)
ROM Flash In Progress (if set)
Configuration Byte 97h, Asset/Test Prompt Byte
Default Value = 00h
Bit
Function
7,6
Test Prompt:
01 = Fake F1
10 = Fake F2
11 = Fake F10
Asset Value
5..0
Configuration Byte 9Bh, Ultra-33 DMA Enable Byte
Default Value = 00h
Bit
7..4
3
2
1
Function
Reserved
Secondary Slave Enabled for U-33 if Set
Secondary Master Enabled for U-33 if Set
Primary Slave Enabled for U-33 if Set
Primary Master Enabled for U-33 if Set
0
Configuration Byte 9Ch, Mode-2 Configuration Byte
Default Value = 1Ch
Bit
7,6
5
Function
Reserved
Mode 2 Support
0 = Disable
1 = Enable
4
Secondary Hard Drive Controller
0 = Disable
1 = Enable
3,2
Secondary Hard Drive Controller IRQ
00 = IRQ10
01 = IRQ11
10 = IRQ12
11 = IRQ15
1,0
Reserved
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Configuration Byte 9Dh, ESS Audio Configuration Byte
Default Value = 12h
Bit
7
6,5
Function
Reserved for Game Port Enable
Audio Address
00 = 22xh
01 = 23xh
10 = 24xh
11 = 25xh
4,3
2,1
0
DMA Channel
00 = Disabled
01 = DMA0
10 = DMA1
11 = DMA3
IRQ Select
00 = IRQ9
01 = IRQ5
10 = IRQ7
11 = IRQ10
ESS Audio Chip Enable
0 = Enabled
1 = Disabled
Configuration Byte 9Eh, ECP DMA Configuration Byte
Default Value = 03h
Bit
7..4
3
Function
Reserved
SafeStart Control:
0 = Disable
1 = Enable
2..0
ECP DMA Channel
000 = Invalid
100 = Disabled
All other values (001-011, 101-111) refer to channel no.
Configuration Byte 9Fh-AFh, Asset Tag Serial Number
Configuration Bytes B0h-C3h; Custom Hard Drive Information
These bytes contain the number of cylinders, heads, and sectors per track for hard drives C, D, E,
and F respectively. The mapping for each drive is as follows:
Drive 65 (C)
B0h
Drive 66 (D)
B5h
Drive 68 (E)
BAh
Drive 15 (F)
BFh
Function
No. of Cylinders, Low Byte
No. of Cylinders, High Byte
No. of Heads
B1h
B2h
B6h
B7h
BBh
BCh
C0h
C1h
B3h
B8h
BDh
C2h
Max ECC Bytes
B4h
B9h
BEh
C3h
No. of Sectors Per Track
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Configuration Byte C7h, C8h, Serial Ports 1 and 2 (Respectively) Configuration Bytes
Default Value = FEh, 7Dh
Bit
Function
7..2
Base I/O Address (in packed format)
(Algorithm: [Addr. - 200h] / 8)
(i.e., 3Fh = 3F8h, 1Fh = 2F8h, 00 = 200h)
Interrupt:
1..0
00 = Reserved
01 = IRQ3
10 = IRQ4
11 = Reserved
Configuration Bytes CAh, DBh; Chassis Serial Number
Configuration Bytes DEh, DFh; Checksum of Locations 90h-DDh
Configuration Bytes E0h-FFh; Client Management Error Log
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Chapter 4 System Support
4.7
I/O MAP AND REGISTER ACCESSING
4.7.1 SYSTEM I/O MAP
Table 4-19.
System I/O Map
I/O Port
Function
0000..000Fh
0020..0021h
0040..0043h
0060h
DMA Controller 1
Interrupt Controller 1
Timer 1
Keyboard Controller Data Byte
0061h
NMI, Speaker Control
0064h
0070h
0071h
Keyboard Controller Command/Status Byte
NMI Enable, RTC/Lower CMOS Index
RTC Data
0078h-007Bh
007Ch-007Fh
0080..008Fh
0092h
GPIO Port 1 Control (87307 I/O controller)
GPIO Port 2 Control (87307 I/O controller)
DMA Page Registers
Port A, Fast A20/Reset
00A0..00A1h
00B2h, 00B3h
00C0..00DFh
00F0h
Interrupt Controller 2
APM Control/Status Ports
DMA Controller 2
Math Coprocessor Busy Clear
015C, 015Dh
0170..0177h
01F0..01FFh
0201..024Fh
0278..027Bh
02F8..02FFh
0371.. 0375h
0376h
87307 I/O Controller Configuration Registers (Index, Data)
Hard Drive (IDE) Controller 2
Hard Drive (IDE) Controller 1
Audio subsystem control (primary & secondary addresses)
Parallel Port (LPT2)
Serial Port (COM2)
Diskette Drive Controller Alternate Addresses
IDE Controller Alternate Address
IDE Controller Alternate Address, Diskette Drive Controller Alternate Address
Parallel Port (LPT1)
FM synthesizer (alias addresses)
Graphics Controller
0377h
0378..037Fh
0388..038Bh
03B0..03DFh
03E8..03EFh
03F0..03F5h
03F6, 03F7h
03F8..03FFh
04D0, 04D1h
0C00, 0C01h
0C06, 0C07h
0C50, 0C51h
0C52h
Serial Port (COM3)
Diskette Drive Controller Primary Addresses
Diskette Drive Controller Primary Addresses, Hard Drive Controller Primary Addresses
Serial Port (COM1)
Master, Slave Edge/Level INTR Control Register
PCI IRQ Mapping Index, Data
Reserved - Compaq proprietary use only
System Management Configuration Registers (Index, Data)
General Purpose Port
0C7Ch
Machine ID
0CF8h
0CF9h
PCI Configuration Address (dword access)
Reset Control Register
0CFCh
FF00..FF07h
PCI Configuration Data (byte, word, or dword access)
IDE Bus Master Register
NOTE: Assume unmarked gaps are reserved/unused.
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4.7.2 GPIO UTILIZATION
This section describes the utilization of general purpose input/output (GPIO) ports provided by
the south bridge (82371) and I/O controller (87307) components used in this system.
4.7.2.1 82371 South Bridge GPIO Utilization
The 82371 South Bridge component includes a number of single and dual purpose pins available
as general purpose input/output (GPIO) ports. The GPIO ports are configured during POST by
BIOS through the PCI configuration registers B0-B3h (82371, function 0). The GPI ports are
monitored through registers of the Power Management function (function 3) at I/O address PM
base +30h. The GPO ports are controlled through a register of function 3 at I/O address PM base
+34h.
Tables 4-20 and 4-21 list the utilization of the GPI and GPO ports respectively in this system.
Table 4-20.
82371 South Bridge General Purpose Input Port Utilization
GP Input Port
GPI #0
Function
IOCHK- function for ISA bus.
GPI #1
SCI- event status.
GPI #2..5
GPI #6
GPI #7
Not used.
Interrupt (IRQ8) for RTC (in 87307 I/O controller).
Not used.
GPI #8
GPI #9
Magic packet SMI event status. When read low, magic packet has occurred.
Not used.
GPI #10
GPI #11
GPI #12
GPI #13
GPI #14, 15
GPI #16
GPI #17
GPI #18
GPI #19
GPI #20
GPI #21
Wakeup w/ IRQ12. Will, in S1 state, be high if an IRQ12 (mouse interrupt) occurred.
Not used
Wake up w/ IRQ1. Will, in S1 state, be high if an IRQ1 (keyboard interrupt) occurred.
PME status.
Backplane revision bits <0, 1>
Not used.
Primary IDE cable type: 0 = 80-pin cable attached, 1 = 40-pin cable attached.
Secondary IDE cable type: 0 = 80-pin cable attached, 1 = 40-pin cable attached.
Chassis fan status: 0 = fan not connected, 1 = fan connected.
Processor thermal caution status: 0 = not occurred, 1 = occurred.
Themal sensor: 0 = diode connected, 1 = diode not connected.
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Chapter 4 System Support
Table 4-21.
82371 South Bridge General Purpose Output Port Utilization
GP Output Port
GPO #0
Function
PCI reset. When low will generate a PCI RST- to PCI slots.
GPO #1-7
GPO #8
ISA bus address signals LA17-23.
Not used.
GPO #9
Not used.
GPO #10
GPO #11
GPO #12
GPO #13
GPO #14
GPO #15
GPO #16
GPO #17
GPO #18
GPO #19
GPO #20
GPO #21
GPO #22, 23
GPO #24
GPO #25
GPO #26
GPO #27
GPO #28-30
Not used.
Not used.
Not used.
Not used.
Not used
Not used.
Power management suspend control signal.
CPU clock stop. When cleared inhibits the clock generator from producing CPU clock.
PCI clock stop. When cleared inhibits the clock generator from producing PCI clock.
Not used.
Power management suspend control signal.
Not used.
X-bus control signals.
Not used.
Not used.
Not used.
Chassis fan control. When cleared (0) shuts down the chassis fan.
Not used.
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4.7.2.2 87307 I/O Controller Functions
The 87307 I/O controller contains various functions such as the keyboard/mouse interfaces,
diskette interface, serial interfaces, and parallel interface. While the control of these interfaces
uses standard AT-type I/O addressing, the configuration of these functions uses indexed ports
unique to the 87307. In this system, hardware strapping selects I/O addresses 015Ch and 015Dh
at reset as the Index/Data ports for accessing the logical devices within the 87307. The hardware
strapping also places the 87307 into PnP motherboard mode. The integrated logical devices are
listed as follows:
Table 4-22 lists the PnP standard control registers for the 87307.
Table 4-22.
87307 I/O Controller PnP Standard Control Registers
Index
00h
01h
02h
03h
04h
05h
06h
07h
Function
Set RD_DATA Port
Serial Isolation
Configuration Control
Wake (CSN)
Resource Data
Status
Reset Value
00h
00h
Card Select Number (CSN)
Logical Device Select:
00h
00h
00h = 8042 Controller (Keyboard I/F)
01h = 8042 Controller (Mouse I/F)
02h = RTC/APC Configuration
03h = Diskette Controller
04h = Parallel Port
05h = UART 2 (Serial Port B / IrDA)
06h = UART 1 (Serial Port A)
07h = GPIO Ports
08h = Power Management
Super I/O ID Register (SID)
SIO Configuration 1 Register
SIO Configuration 1 Register
Programmable Chip Select Configuration Index
Programmable Chip Select Configuration Data
20h
21h
22h
23h
24h
A0h
16h
02h
00h
00h
NOTE:
For a detailed description of registers refer to appropriate National documentation.
The configuration registers are accessed by writing the appropriate logical device’s number to
index 07h and writing the desired offset to the index register. The data is then either written to or
read from the data register.
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Chapter 4 System Support
87307 GPIO Utilization
The 87307 I/O Controller provides 11 general purpose pins that can be individually configured as
either inputs or outputs. These pins are mapped as two general purpose ports and utilized as
shown below.
GPIO Port 1 Data, I/O Addr. 078h, (87307 I/O Controller),
Bit
7
Function
GPIO17 (not used)
6
GPIO16 (config. as input): Cover Lock Detect.
Read 0, no solenoid
Read 1, solenoid
5
4
GPIO15 (config. as output): Cover Alarm Clear.
Write 0 to clear alarm.
GPIO14 (config. as input): Cover Removed Detect.
Read 0, cover has been removed
Read 1, cover is secure
3..0
GPIO13-10 (config. as input):
Backplane identification (BP_ID3-0)
GPIO Port 1 Direction/Output Type/PU Cntrl., I/O Addr. 079-07Bh, (87307 I/O
Controller)
GPIO Port 2 Data, I/O Addr. 07Ch, (87307 I/O Controller),
Bit
7..4
3
Function
GPIO27..24 Not Available
GPIO23 (config. as input): Ring Detect
Read 0, no ring received
Write 1, ring detected
2..0
GPIO22..20 Not Available
GPIO Port 2 Direction/Output Type/PU Cntrl., I/O Addr. 07D-07Fh, (87307 I/O
Controller)
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4.8
SYSTEM MANAGEMENT SUPPORT
This section describes the hardware support of functions involving security, safety, identification,
and power consumption of the system. System management functions are handled largely by a
System Security ASIC. Most functions are controlled through registers (Table 4-23) accessed
using the indexed method through I/O ports 0C50h (index) and 0C51h (Data).
Table 4-23.
System Management Control Registers
Index
00h
02h
03h
05h
12h
13h
20h
21h
22h
30h
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
Function
Identification
Temperature Status / Clear
Temperature Interrupt / SMI Enable
Power On LED Blink Control
General Purpose Open Collector (GPOC) Bits
Secured GPOC Bits
Power Button Control
SMI / SCI Source
SMI / SCI Mapping
REQ/GNT Control
Super I/O Security Control
Super I/O Index Address Low
Super I/O Index Address High
Super I/O Index Data
Super I/O Data Address Low
Super I/O Data Address High
Super I/O Write Block 0
Super I/O Write Block 1
Super I/O Write Block 2
Super I/O Write Block 3
The following subsections describe the system management functions. Any BIOS interaction
required of these functions is described in Chapter 8, “BIOS” or in the Compaq BIOS Technical
Reference Guide.
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Chapter 4 System Support
4.8.1 FLASH ROM WRITE PROTECT
The system BIOS firmware is contained in a flash ROM device that can be re-written with
updated code if necessary. The ROM is write-protected with a Black Box* security feature. The
Black Box feature uses the Administrator password to protect against unauthorized writes to the
flash ROM. During the boot sequence, the BIOS checks for the presence of the ROMPAQ
diskette. If ROMPAQ is detected and the password is locked into the Black Box with the Protect
Resources command, an Access Resources command followed by Administrator password entry
must occur before the ROM can be flashed. If the Permanently Lock Resources command has
been invoked, the power must be cycled before the ROM can be flashed. The system ROM is
write-protected as follows:
Start Addr.
C0000h
F0000h
F8000h
FA000h
End Addr.
EFFFFh
F7FFFh
F9FFFh
FFFFFh
Data Type
Option ROM
System BIOS
ESCD
Protection
Password write-protected
Password write-protected
Never write-protected
Always write-protected
Boot Block
The flashing functions are handled using the INT15 AX-E822h BIOS interface.
4.8.2 PASSWORD PROTECTION
When enabled, the user is prompted to enter the power-on password during POST. If an
incorrect entry is made, the system halts and does not boot. The Power-On password is stored in
eight bytes at configuration memory locations 37h-3Fh. These locations are physically located
within the 87307. At the time a new password is written into 37h-3Fh, the password is also
written into Black Box* logic contained within the System Security ASIC. The Black Box logic
is used for power-on password protection support instead of the port 92 sequence used on other
systems. The Black Box logic prevents inadvertent or unauthorized access to the password bytes
of the 87307 by monitoring I/O ports 70/71h for access to the 37h-3Fh CMOS range and
inhibiting the AEN signal to the 87307 if such access is detected. Slot 1 of the Black Box logic
can be written to at runtime, allowing the user to change the power on password without cycling
power and going through the F10 method. The Black Box password cannot be read.
The power-on password function can be disabled by setting DIP SW1 position 1 to on (closed).
The administrator password is stored in eight bytes at configuration memory locations 78h-7Fh.
If the administrator password function is enabled, the user is prompted to enter the password
before running F10-Setup or before booting from a ROMPAQ diskette. If an incorrect entry is
made, the system halts and does not boot. The administrator password is also stored in the Black
Box* logic. Black Box logic acting as the sentry for the administrator password by preventing
inadvertent or unauthorized writing to the Flash ROM.
*
Black Box logic is Compaq-proprietary and controlled exclusively through the BIOS ROM.
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4.8.3 I/O SECURITY
The 87307 I/O controller allows various I/O functions to be disabled through configuration
registers. In addition, the configuration registers of the 87307 are further protected by Client
Management (CM) logic (contained within a Compaq ASIC) that can be set (using BIOS call
INT 15 AX=E829h) to block access to the 87307 configuration registers of the following
functions:
♦
♦
♦
Diskette drive
Serial port
Parallel port
In blocking 87307 functions, the CM logic monitors ISA I/O cycles and can detect, through
index address-matching, when an attempt is made to access a function provided by the 87307. If
the CM logic has been set to block access, then ISA bus signal AEN or IOWC-, both which the
CM logic provides to the 87307, is disabled, effectively inhibiting the I/O access.
The USB controller can also be blocked from access by the CM logic. In this case the CM logic
can be set to block the routing of the REQ/GNT signals to the USB controller, thereby disabling
the interface.
4.8.4 USER SECURITY
When enabled, the user is prompted to enter the power-on password during POST. If an
incorrect entry is made, the system halts and does not boot. The Power-On password is stored in
eight bytes at configuration memory locations 37h-3Fh. These locations are physically located
within the 87307.
The power-on password function can be disabled by setting DIP SW1 position 1 to on (closed).
The administrator password is stored in eight bytes at configuration memory locations 78h-7Fh.
If the administrator password function is enabled, the user is prompted to enter the password
before running F10-Setup or before booting from a ROMPAQ diskette. If an incorrect entry is
made, the system halts and does not boot.
The QuickLock feature allows, if enabled in F10-Setup through CMOS location 13h bit <2>, the
user to lock the keyboard by invoking the Ctrl-Alt-L keystrokes. This initiates an SMI and the
SMI handler then takes the action required to lock the keyboard. If the QuickBlank feature is
enabled at that time then the screen will be blanked as well. The user then must enter the power-
on password to re-activate the keyboard and/or display .
NOTE: Although the SMI is used for initiating QuickLock/QuickBlank functions, these
functions are not considered power management features.
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4.8.5 TEMPERATURE SENSING
This system employs two sensors for monitoring the temperature inside the chassis. A thermister
attached to the heat sink of the Pentium II SEC cartridge is used to detect the caution level. This
thermister, connected to the system board through header P15, is part of sensing logic that
provides input to a Compaq ASIC. The sensing logic is set to trip when 179.6 °F (82 °C) is
reached. At that time the Compaq ASIC can generate an SMI (if so configured, see registers
below) resulting in a warning to the user and/or the chassis fan being turned on. Three general
purpose input ports of the 82371south bridge monitor status of the Thermal Caution circuitry.
They are listed below with their default values:
1. 82371 GPI #19 – Chassis fan connection (1 = fan connected)
2. 82371 GPI #20 – Thermal Caution event status (0 = caution event has not occurred)
3. 82371 GPI #21 – Thermal sensor connection status (0 = connected)
The Pentium II processor contains a sensor utilized to detect a deadly condition. When the
processor temperature reaches 135 °F the THERMTRIP- signal is asserted and recorded in a
Compaq ASIC (see following registers). Assertion of THERMTRIP- also results in turning off
the system’s clock generator, effectively shutting down the system.
The following two indexed registers are used by BIOS and available to software for controlling
the temperature sense function.
I/O Port C51.02h, Temperature Status/Clear Register
Bit
7..2
1
Function
Reserved
Temperature Deadly (RO)
0 = Normal
1 = Critical temperature detected
Reserved
0
NOTE: Bits 1,0 are cleared when read but will be instantly reset if condition remains.
I/O Port C51.03h, Temperature Interrupt/SMI Enable Register
Bit
7..3
2
Function
Reserved
Temperature Deadly Shutdown Disable:
0 = Initiate shutdown w/deadly condition.
1 = Do not initiate shutdown.
Reserved
1,0
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4.8.6 SMART COVER LOCK
The chassis cover (also known as the “hood”) can be locked to prevent unauthorized personnel
from removing the cover and changing the system hardware. The locking mechanism consists of
a solenoid controlled by the Setup utility through the Client Management logic in a Compaq
ASIC. The presence of the Smart Cover Lock (actually of the solenoid) is detected by logic and
readable by software at 87307 GPIO port 1 bit <6>.
The cover lock mechanism can be bypassed in an emergency by removing three screws on the
rear of the chassis with the Smart Cover Lock Failsafe Key.
4.8.7 SMART COVER REMOVAL SENSOR
This system includes a cover removal indication function. The system can, upon power-up,
notify the user if the computer cover has been removed. The sensor consists of a plunger switch
mounted on the backplane (riser card) that comes in contact with the chassis cover. When the
cover is removed, the switch is activated and the battery-backed logic places a high at 87307
GPIO port 1 bit <4>. This bit will remain set (whether or not the cover is replaced) until the
system is powered up and the user completes the boot sequence successfully, at which time the
hood alarm bit <5> will be cleared. Through Setup, the user can set this function to one of three
levels of support for a “hood removed” condition:
Level 0 - Hood removal indication is essentially disabled at this level. During POST, Bit <4> is
cleared and no other action is taken by BIOS.
Level 1 - During POST the message “The computer’s cover has been removed since the last
system start up” is displayed and time stamps in CMOS and SIT are updated.
Level 2 - During POST the “The computer’s cover has been removed since the last system start
up” message is displayed, time stamps in CMOS and SIT are updated, and user is prompted for
administrator password.
NOTE: If the user invokes Setup through F10 the administrator password is not
requested again.
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4.8.8 POWER MANAGEMENT
This system provides baseline hardware support of ACPI- and APM-compliant firmware and
software. The major power-consuming components (processor, chipset, I/O controller, and fan)
can be placed into a reduced power mode upon software command either automatically or by user
control. The system can then be brought back up (“wake-up”) by events defined by the ACPI
specification. The ACPI wake-up events supported by this system are listed as follows:
ACPI Wake-Up Event
Power Button
RTC Alarm
Wake on LAN (w/NIC)
PME
System Wakes From
Sleep/Soft-Off
Sleep/Soft-Off
Sleep/Soft-Off
Sleep/Soft-Off
Sleep/Soft-Off
Sleep
Serial port Ring
USB
Keyboard
Sleep
Mouse
Sleep
4.8.8.1 Power Button
This system uses an ACPI-compliant power button that also provides a legacy mode as well. In
legacy mode the system is alternately powered on or off each time the button is pressed and
released. In ACPI mode the power supply, when on, will turn off only after the button is pressed
and held for over four seconds. The power button mode is controlled by ROM-based Setup
through a Compaq ASIC. A detailed description of system power control is provided in Chapter 7
“Power and Signal Distribution.”
4.8.8.2 Fan Control
The system contains two fans; a power supply fan (contained within the power supply assembly)
and a chassis fan mounted in the front of the chassis. The operation of both fans involves
temperature conditions and energy conservation but different logic is used for each.
The power supply fan is on during normal operation. In sleep mode the power supply fan is
(normally) shut down by software using logic in a Compaq ASIC, which asserts a FAN OFF
signal routed to the power supply assembly. The power supply assembly, however, includes a
temperature sensor that can override the FAN OFF signal if necessary.
The chassis fan is controlled by the thermister attached to the processor heat sink as well as shut
down logic. The temperature-sensing operation is discussed in section 4.8.5. To conserve energy
during sleep mode 82371 GPO port #27 is cleared resulting in the chassis fan being shut down.
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4.8.8.3 Hard Drive Spindown Control
The timeout parameter stored in the SIT record 04h and indexed through CMOS location 2Ah
(bits <4..0>) represents the period of hard drive inactivity required to elapse before the hard drive
is allowed to spin down. The timeout value is downloaded from CMOS to a timer on the hard
drive. The timeout period can be set in incremental values of 0 (timeout disabled), 10, 15
(default), 20, 30, and 60 minutes. A timed-out and spun-down hard drive will automatically spin
back up upon the next drive access. It is normal for the user to detect a certain amount of access
latency in this situation.
4.8.8.4 Monitor Power Control
The VESA display power management signaling protocol defines different power consumption
conditions and uses the HSYNC and VSYNC signals of the monitor interface to select a
monitor’s power condition. This capability is dependent on the graphics controller employed in
the system. For compliance to the monitor power control feature refer to the applicable appendix
of the installed graphics controller card.
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Chapter 5
INPUT/OUTPUT INTERFACES
INTRODUCTION
5.1
This chapter describes the standard (i.e., system board) interfaces that provide input and output
(I/O) porting of data and specifically discusses interfaces that are controlled through I/O-mapped
registers. The I/O interfaces are integrated functions of the south bridge (82371) and the I/O
controller (87307). The following I/O interfaces are covered in this chapter:
♦
♦
♦
♦
♦
♦
Enhanced ID interface (5.2)
Diskette drive interface (5.3)
Serial interfaces (5.4)
Parallel interface (5.5)
Keyboard/pointing device interface (5.6)
Universal serial bus interface (5.7)
page 5-1
page 5-9
page 5-14
page 5-20
page 5-27
page 5-34
5.2
ENHANCED IDE INTERFACE
The enhanced IDE (EIDE) interface consists of primary and secondary controllers (integrated
into the south bridge component) that can support IDE devices each. Devices that may connect to
the IDE interface include hard drives, CD-ROM drives, PD-CD-ROM drives, and 120-MB
floptical drives.
Two 40-pin keyed IDE data connectors (one for each controller) are provided on the system
board. Each connector can support two devices and can be configured independently for PIO
modes 1-4, DMA modes 1-2, or Ultra ATA modes 0-2. In standard configuration an IDE drive is
attached to the primary connector and the CD-ROM (if installed) is attached to the secondary
connector.
NOTE:
With only one device connected to a controller, a 40-conductor cable 10 inches
or shorter will allow UATA mode 2 operation. Two devices on the same 40-pin/10”cable
will limit operation to UATA mode 1 (25 MB/s). For a controller to provide UATA
mode 2 operation with two devices connected requires an optional 80-conductor cable.
Pin 34 is used by BIOS for 40-/80-conductor cable detection. On the 40-conductor cable,
pin 34 is high (+5 VDC). On the 80-conductor cable, pin 34 is low (grounded).
5.2.1 IDE PROGRAMMING
The IDE interface is configured as a PCI device and controlled through standard I/O mapped
registers.
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5.2.1.1 IDE Configuration Registers
The IDE controller is integrated into the south bridge (82371) component and configured as a
PCI device with bus mastering capability. The PCI configuration registers for the IDE controller
function (PCI device #20, function #1) are listed in Table 5-1.
Table 5-1.
EIDE PCI Configuration Registers (82371 Function 1)
PCI
Value
on
PCI
Value
on
Reset
Conf.
Addr.
00-01h
02-03h
04-05h
06-07h
08h
Conf.
Addr.
24-3Fh
40, 41h
42, 43h
44h
45-47h
48h
49h
Register
Vender ID
Device ID
PCI Command
PCI Status
Revision ID
Programming
Sub-Class
Reset
8086h
7111h
0000h
0000h
0Ah
Register
Reserved
IDE Timing (Primary)
IDE Timing (Secondary)
Slave IDE Timing
Reserved
UDMA Timing
Reserved
09h
0Ah
01h
01h
0Bh
0Dh
0Eh
0F-1Fh
20-23h
Base Class Code
Master Latency Timer
Header Type
Reserved
80h
0000h
80h
00h
00h
4A, 4Bh
4C-F7h
F8-FBh
FC-FFh
--
UDMA Timing
Reserved
Manufacturer’s ID
Reserved
BMIDE Base Address
--
--
NOTE:
Assume unmarked gaps are reserved and/or not used.
5.2.1.2 IDE Bus Master Control Registers
The IDE interface can perform PCI bus master operations using the I/O mapped control registers
listed in Table 5-2.
Table 5-2.
IDE Bus Master Control Registers
I/O Addr.
Offset
00h
02h
04h
08h
0Ah
Size
(Bytes)
Default
Value
00h
00h
0000 0000h
00h
Register
2
2
4
2
2
4
Bus Master IDE Command (Primary)
Bus Master IDE Status (Primary)
Bus Master IDE Descriptor Ptr (Pri.)
Bus Master IDE Command (Secondary)
Bus Master IDE Status (Secondary)
Bus Master IDE Descriptor Ptr (Sec.)
00h
0000 0000h
0Ch
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5.2.1.3 IDE ATA Control Registers
The IDE controller of the 82586 decodes the addressing of the standard AT attachment (ATA)
registers for the connected drive, which is where the ATA control registers actually reside. The
primary and secondary interface connectors are mapped as shown in Table 5-3.
Table 5-3.
IDE ATA Control Registers
Primary
I/O Addr.
1F0h
Secondary
I/O Addr.
170h
Register
Data
Error
R/W
R/W
R
1F1h
171h
1F1h
171h
Features
W
1F2h
1F3h
1F4h
1F5h
1F6h
1F7h
172h
173h
174h
175h
176h
177h
Sector Count
Sector Number
Cylinder Low
Cylinder High
Drive/Head
Status
R/W
R/W
R/W
R/W
R/W
R
1F7h
3F6h
3F6h
3F7h
177h
376h
376h
377h
Command
Alternate Status
Drive Control
Drive Address
n/a for hard drive
W
R
W
R
3F7h
377h
W
The following paragraphs describe the IDE ATA control registers.
Data Register, I/O Port 1F0h/170h
This register is used for transferring all data to and from the hard drive controller. This register
is also used for transferring the sector table during format commands. All transfers are high-
speed 16-bit I/O operation except for Error Correction Code (ECC) bytes during Read/Write
Long commands.
Error Register, I/O Port 1F1h/171h (Read Only)
The Error register contains error status from the last command executed by the hard drive
controller. The contents of this register are valid when the following conditions exist:
♦
♦
Error bit is set in the Status register
Hard drive controller has completed execution of its internal diagnostics
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Chapter 5 Input/Output Interfaces
The contents of the Error register are interpreted as a diagnostic status byte after the execution of
a diagnostic command or when the system is initialized.
Bit
7
6
Function
Bad Block Mark Detected in Requested Sector ID Field (if set)
Non-correctable Data Error (if set)
5
Reserved
4
3
Requested Sector ID Field Not Found (if set)
Reserved
2
Requested Command Aborted Due To Invalid Hard Drive
Status or Invalid Command Code (if set)
Track 0 Not Found During Re-calibration Command (if set)
Data Address Mark Not Found After Correct ID Field (if set)
1
0
Set Features Register, I/O Port 1F1h/171h (Write Only)
This register is command-specific and may be used to enable and disable features of the interface.
Sector Count Register, I/O Port 1F2h/172h
This register defines either:
♦
or
♦
the number of sectors of data to be read or written
the number of sectors per track for format commands
If the value in this register is zero, a count of 256 sectors is specified. The sector count is
decremented as each sector is accessed, so that the value indicates the number of sectors left to
access when an error occurs in a multi-sector operation. During the Initialize Drive Parameters
command, this register contains the number of sectors per track.
Sector Number Register, I/O Port 1F3h/173h
The Sector Number register contains the starting sector number for a hard drive access.
Cylinder Low, Cylinder High Registers, I/O Port 1F4h, 1F5h/174h, 175h
These registers contain the starting cylinder number for each hard drive access. The three most-
significant bits of the value are held in byte address 1F5h (bits <2..0>) while the remaining bits
are held in location 1F4h.
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Drive Select/Head Register, I/O Port 1F6h/176h
Bit
7
Function
Reserved
6,5
Sector Size:
00 = Reserved
01 = 512 bytes/sector
10, 11 = Reserved
Drive Select:
4
0 = Drive 1
1 = Drive 2
3..0
Head Select Number:
0000 = 0
0001 = 1
0010 = 2
0011 = 3
0100 = 4
0101 = 5
0110 = 6
0111 = 7
1000 = 8
1001 = 9
1010 = 10
1011 = 11
1100 = 12
1101 = 13
1110 = 14
1111 = 15
NOTE:
Setting bit <4> to 1 when Drive 2 is not present may cause remaining
controller registers to not respond until Drive 1 is selected again.
Status Register, I/O Port 1F7h/177h (Read Only)
The contents of this register are updated at the completion of each command. If the Busy bit is
set, no other bits are valid. Reading this register clears the IRQ14 interrupt.
Bit
7
6
Function
Controller Busy. If set, controller is executing a command.
READY- Signal Active (if set).
5
WRITE FAULT- Signal Active (if set).
4
3
SEEK COMPLETE- Signal Active (if set)
Data Request. If set, the controller is ready for a byte or word-
length data transfer. Bit should be verified before each transfer.
Correctable Data Error Flag. If set, data error has occurred and
has been corrected.
2
1
0
INDEX- Signal Active (if set).
Error Detected. When set, indicates error has occurred. Other
bits in register should be checked to determine error source.
NOTE:
Register status of an error condition does not change
until register is read.
The alternate Status register at location 3F6h holds the same status data as location 1F7h but
does not clear hardware conditions when read.
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Chapter 5 Input/Output Interfaces
Command Register, I/O Port 1F7h/177h (Write Only)
The IDE controller commands are written to this register. The command write action should be
prefaced with the loading of data into the appropriate registers. Execution begins when the
command is written to 1F7h/177h. Table 5-4 lists the standard IDE commands.
Table 5-4.
IDE Controller Commands
Command
Initialize Drive Parameters
Seek
Value
91h
7xh
Recalibrate
1xh
Read Sectors with Retries
Read Long with Retries
Write Sectors with Retries
Write Long with Retries
Verify Sectors with Retries
Format Track
20h*
22h*
30h*
32h*
40h
50h
Execute Controller Diagnostic
Idle
Idle Immediate
Enter Low Power and Enable/Disable Timeout
Enter Idle and Enable/Disable Timeout
Check Status
90h
97h, E3h
95h, E1h
96h
97h
98h
Identify
ECh
Read Buffer
E4h
Write Buffer
E8h
NOP
00h
Read DMA with Retry
Read DMA without Retry
Read Multiple
C8h
C9h
C4h
Set Features
EFh
Set Multiple Mode
Sleep
Standby
Standby Immediate
Write DMA with Retry
Write DMA without Retry
Write Multiple
C6h
99h, E6h
96h, E2h
94h, E0h
CAh
CBh
C5h
Write Same
E9h
Write Verify
3Ch
* Without retries, add one to the value.
Alternate Status Register, I/O Port 3F6h/376h (Read Only)
The alternate Status register at location 3F6h holds the same status data as location 1F7h but
does not clear hardware conditions when read.
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Drive Control Register, I/O Port 3F6h/376h (Write Only)
Bit
7..3
2
Function
Reserved
Controller Control:
0 = Re-enable
1 = Reset
1
0
Interrupt Enable/Disable
0 = Disable interrupts
1 = Enable interrupts
Reserved
Drive Access Register, I/O Port 3F7h/377h (Read Only)
Bit
7
Function
Reserved
6
5..2
WRITE GATE- Signal Active (if set)
Head Select:
0000 = 15
0001 = 14
0010 = 13
0011 = 12
0100 = 11
0101 = 10
0110 = 9
1000 = 7
1001 = 6
1010 = 5
1011 = 4
1100 = 3
1101 = 2
1110 = 1
1111 = 0
0111 = 8
1,0
Drive Select:
00 = Disabled
01 = Drive 1 selected
10 = Drive 0 selected
11 = Invalid
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Chapter 5 Input/Output Interfaces
5.2.2 IDE CONNECTOR
This system uses a standard 40-pin connector for IDE devices. Device power is supplied through
a separate connector.
Figure 5–1. 40-Pin IDE Connector.
Table 5-5.
40-Pin IDE Connector Pinout
Pin
1
2
3
4
5
6
7
8
Signal
RESET- Reset
Description
Pin
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Signal
DRQ
GND
IOW-
GND
Description
DMA Request
Ground
I/O Write
Ground
GND
DD7
DD8
DD6
DD9
DD5
DD10
DD4
DD11
DD3
DD12
DD2
DD13
DD1
DD14
DD0
DD15
GND
--
Ground
Data Bit <7>
Data Bit <8>
Data Bit <6>
Data Bit <9>
Data Bit <5>
Data Bit <10>
Data Bit <4>
Data Bit <11>
Data Bit <3>
Data Bit <12>
Data Bit <2>
Data Bit <13>
Data Bit <1>
Data Bit <14>
Data Bit <0>
Data Bit <15>
Ground
IOR-
GND
I/O Read
Ground
IORDY
CSEL
DAK-
GND
IRQn
IO16-
DA1
DSKPDIAG
DA0
DA2
I/O Channel Ready
Cable Select
DMA Acknowledge
Ground
Interrupt Request [1]
16-bit I/O
Address 1
Pass Diagnostics
Address 0
9
10
11
12
13
14
15
16
17
18
19
20
Address 2
Chip Select
Chip Select
CS0-
CS1-
HDACTIVE- Drive Active (front panel LED) [2]
GND Ground
Key
NOTES:
[1] Primary connector wired to IRQ14, secondary connector wired to IRQ15.
[2] Pin 39 is used for spindle sync and drive activity (becomes SPSYNC/DACT-)
when synchronous drives are connected.
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5.3
DISKETTE DRIVE INTERFACE
The diskette drive interface supports up to two diskette drives, each of which connect to a
standard 34-pin diskette drive connector. All models come standard with a 3.5-inch 1.44-MB
diskette drive installed as drive A. An additional diskette drive (either a 3.5-inch 720-KB, 1.44-
MB, or 2.88-MB drive or a 5.25-inch 360-KB or 1.2-MB drive) may also be installed as drive B.
The drive designation is determined by which connector is used on the diskette drive cable. The
drive attached to the end connector is drive A while the drive attached to the second (next to the
end) connector) is drive B.
On all models, the diskette drive interface function is integrated into the 87307 I/O controller
component. The internal logic of the I/O controller is software-compatible with standard 82077-
type logic. The diskette drive controller has three operational phases in the following order:
♦
♦
♦
Command phase - The controller receives the command from the system.
Execution phase - The controller carries out the command.
Results phase - Status and results data is read back from the controller to the system.
The Command phase consists of several bytes written in series from the CPU to the data register
(3F5h/375h). The first byte identifies the command and the remaining bytes define the
parameters of the command. The Main Status register (3F4h/374h) provides data flow control
for the diskette drive controller and must be polled between each byte transfer during the
Command phase.
The Execution phase starts as soon as the last byte of the Command phase is received. An
Execution phase may involve the transfer of data to and from the diskette drive, a mechnical
control function of the drive, or an operation that remains internal to the diskette drive controller.
Data transfers (writes or reads) with the diskette drive controller are by DMA, using the DRQ2
and DACK2- signals for control.
The Results phase consists of the CPU reading a series of status bytes (from the data register
(3F5h/375h)) that indicate the results of the command. Note that some commands do not have a
Result phase, in which case the Execution phase can be followed by a Command phase.
During periods of inactivity, the diskette drive controller is in a non-operation mode known as
the Idle phase.
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5.3.1 DISKETTE DRIVE PROGRAMMING
5.3.1.1 Diskette Drive Interface Configuration
The diskette drive controller must be configured for a specific address and also must be enabled
before it can be used. Address selection and enabling of the diskette drive interface are affected
by firmware through the PnP configuration registers of the 87307 I/O controller.
The PnP configuration registers are accessed through I/O registers 15Ch (index) and 15Dh
(data). The diskette drive I/F is initiated by firmware selecting logical device 3 of the 87307. This
is accomplished by the following sequence:
1. Write 07h to I/O register 15Ch.
2. Write 03h to I/O register 15Dh (this selects the diskette drive I/F).
3. Write 30h to I/O register 15Ch.
4. Write 01h to I/O register 15Dh (this activates the interface).
The diskette drive I/F configuration registers are listed in the following table:
Table 5-6.
Diskette Drive Interface Configuration Registers
Index
Address
30h
31h
60h
61h
70h
71h
74h
Reset
Value
01h
00h
03h
F0h
06h
03h
02h
04h
--
Function
Activate
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
I/O Range Check
Base Address MSB
Base Address LSB
Interrupt Select
Interrupt Type
DMA Channel Select
Report DMA Assignment
Configuration Data
Drive ID
75h
F0h
F1h
R/W
R/W
--
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5.3.1.2 Diskette Drive Interface Control
The BIOS function INT 13 provides basic control of the diskette drive interface. The diskette
drive interface can be controlled by software through I/O-mapped registers listed in Table 5-7.
Table 5-7.
Diskette Drive Interface Control Registers
Primary
Address
3F1h
Alternate
Address
371h
Register
Media ID
R/W
R
3F2h
3F4h
3F5h
3F7h
372h
374h
375h
377h
Drive Control
Main Status
Data
Drive Status
Data Transfer Rate
W
R
R/W
R
W
The base address (3F1h or 371h) and enabling of the diskette drive controller is selected through
the Function Enable Register (FER, addr. 399.00h) of the 87307 I/O controller. Address selection
and enabling is automatically done by the BIOS during POST but can also be accomplished with
the Setup utility and other software.
The following paragraphs describe the diskette drive interface control registers.
Media ID Register, I/O Port 3F1h/371h (Read Only)
Bit
Function
7..5
Media Type:
xx1 = Invalid
000 = 5.25 inch drive
010 = 2.88 MB (3.5 inch drive)
100 = 1.44 MB (3.5 inch drive)
110 = 720 KB (3.5 inch drive)
Reserved
4..2
1,0
Tape Select:
00 = None
01 = Drive 1
10 = Drive 2
11 = Drive 3
Drive Control Register, I/O Port 3F2h/372h (Write Only)
Bit
7,6
5
Function
Reserved
Drive 2 Motor
0 = Off, 1 = On
Drive 1 Motor
4
3
0 = Off, 1 = On
Interrupt / DMA Enable
0 = Disabled, 1 = Enabled
Controller Enable
0 = Reset controller, 1 = Enable controller
Drive Select
2
1,0
00 = Drive 1
01 = Drive 2
10 = Reserved
11 = Tape drive
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Chapter 5 Input/Output Interfaces
Main Status Register, I/O Port 3F4h/374h (Read Only)
Bit
7
Function
Request for Master. When set, indicates the controller is ready
to send or receive data from the CPU. Cleared immediately
after a byte transfer. Indicates interrupt pin status during non-
DMA phase.
6
Data I/O Direction.
0 = Expecting a write
1 = Expecting a read
5
4
Non-DMA Execution. When set, indicates controller is in the
execution phase of a byte transfer in non-DMA mode.
Command In Progress. When set, indicates that first byte of
command phase has been received. Cleared when last byte in
result phase is read.
3..0
Drive Busy Indicators. Bit is set after the last byte of the
command phase of a seek or recalibrate command is given by
the corresponding drive:
<3>, Drive 3
<2>, Drive 2
<1>, Drive 1
<0>, Drive 0
Data Register, I/O Port 3F5h/375h
Data commands are written to, and data and status bytes are read from this register.
Data Transfer Rate Register, I/O Port 3F7h/377h (Write Only)
Bit
7
Function
Software Reset
6
5
Low Power Mode (if set)
Reserved
4..2
Write Precompensation Delay
000 = Default values for selected data rate (default)
Data Rate Select:
1,0
00 = 500 Kb/s
01 = 300 Kb/s
10 = 250 Kb/s
11 = 1 or 2 Mb/s (depending on TUP reg. Bit <1>)
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5.3.2 DISKETTE DRIVE CONNECTOR
This system uses a standard 34-pin connector (refer to Figure 5-2 and Table 5-8 for the pinout)
for diskette drives. Drive power is supplied through a separate connector.
2
1
8
7
10
9
16 18
24 26
32 34
28 30
4
6
5
12 14
20 22
17
25
27
33
29 31
13 15
21 23
11
19
Figure 5–2. 34-Pin Diskette Drive Connector.
Table 5-8.
34-Pin Diskette Drive Connector Pinout
Pin
1
2
3
4
5
6
7
8
Signal
GND
LOW DEN-
---
MEDIA ID-
GND
DRV 4 SEL- Drive 4 select
GND
INDEX-
GND
MTR 1 ON-
GND
DRV 2 SEL- Drive 2 select
GND Ground
DRV 1 SEL- Drive 1 select
Description
Ground
Low density select
(KEY)
Media identification
Ground
Pin
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
Signal
DIR-
GND
STEP-
GND
WR DATA-
GND
WR ENABLE-
GND
TRK 00-
GND
WR PRTK-
GND
RD DATA-
GND
SIDE SEL-
GND
DSK CHG-
Description
Drive head direction control
Ground
Drive head track step control
Ground
Write data
Ground
Enable for WR DATA-
Ground
Heads at track 00 indicator
Ground
Media write protect status
Ground
Ground
Media index is detected
Ground
Activates drive motor
Ground
9
10
11
12
13
14
15
16
17
Data and clock read off disk
Ground
Head select (side 0 or 1)
Ground
GND
MTR 2 ON-
GND
Ground
Activates drive motor
Ground
Drive door opened indicator
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Chapter 5 Input/Output Interfaces
5.4
SERIAL INTERFACES
The serial interfaces transmit and receive asynchronous serial data with external devices. The
serial interface function is provided by the 87307 I/O controller component, which includes two
16550/16450-compatible UARTs. Each UART is supported by a DB-9 connector on the rear of
the chassis.
87307
DB-9 A (RS-232)
TX/RX/CNTRL
UART1
(Log. Dev. 6)
DB-9 B (RS-232)
TX/RX/CNTRL
UART2
(Log. Dev. 5)
Figure 5–3. Serial Interfaces Block Diagram
5.4.1 RS-232 INTERFACE
The DB-9 connector-based interface complies with EIA standard RS-232-C, which includes
modem control signals and supports baud rates up to 115.2 Kbps. The DB-9 connector is shown
in the following figure and the pinout of the connector is listed in Table 5-9.
Figure 5–4. Serial Interface Connector (Male DB-9 as viewed from rear of chassis)
Table 5-9.
DB-9 Serial Connector Pinout
Pin
1
2
3
4
Signal
CD
RX Data
TX Data
DTR
Description
Pin
6
7
8
9
--
Signal
DSR
RTS
CTS
RI
Description
Data Set Ready
Request To Send
Clear To Send
Ring Indicator
--
Carrier Detect
Receive Data
Transmit Data
Data Terminal Ready
Ground
5
GND
--
Each DB-9 port is independently configurable as to it’s COMn (address) designation.
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5.4.2 SERIAL INTERFACE PROGRAMMING
5.4.2.1 Serial Interface Configuration
The serial interfaces must be configured for a specific address range (COM1, COM2, etc.) and
also must be activated before it can be used. Address selection and activation of the serial
interface are affected through the PnP configuration registers of the 87307 I/O controller.
The PnP configuration registers are accessed through I/O registers 15Ch (index) and 15Dh
(data). Each serial interface is initiated by firmware selecting logical device 5 or 6 of the 87307.
This is accomplished by the following sequence:
1. Write 07h to I/O register 15Ch.
2. Write 05h or 06h to I/O register 15Dh (for selecting UART2 or UART1).
3. Write 30h to I/O register 15Ch.
4. Write 01h to I/O register 15Dh (this activates the interface).
The serial interface configuration registers are listed in the following table:
Table 5-10.
Serial Interface Configuration Registers
Index
Address
30h
31h
60h
61h
70h
71h
74h
Reset
Value [1]
00h / 00h
00h / 00h
02h / 03h
F8h / F8h
03h / 04h
03h / 03h
04h / 04h
04h / 04h
--
Function
Activate
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
I/O Range Check
Base Address MSB
Base Address LSB
Interrupt Select
Interrupt Type
DMA Channel Select
Report DMA Assignment
Configuration Data
75h
F0h
R/W
NOTES:
[1] Device 5 (UART2) / Device 6 (UART1)
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Chapter 5 Input/Output Interfaces
5.4.2.2 Serial Interface Control
The BIOS function INT 14 provides basic control of the serial interface. The serial interface can
be controlled by software through the registers listed in Table 5-11.
Table 5-11.
Serial Interface Control Registers
Address
Base
Register
R/W
R/W
R/W
R/W
RO
R/W
R/W
RO
Receive Buffer / Transmit Holding [1]
Baud Rate Divisor Latch [2]
Interrupt Enable
Interrupt ID
Line Control
Modem Control
Line Status
Base, Base + 1
Base + 1
Base + 2
Base + 3
Base + 4
Base + 5
Base + 6
Base + 7
Modem Status
Scratch Pad
RO
R/W
NOTES:
Base Address:
COM1 = 3F8h
COM2 = 2F8h
[1] This register holds receive data when read from and transmit data when written to.
[2] When bit <7> of the Line Control register is set (1), writing to 3F8h and 3F9h
programs the divisor rate for the baud rate generator.
Receive Buffer / Transmit Holding Register, I/O Port 3F8h/2F8h
When read by the CPU, this byte contains receive data. When written to by the CPU, the byte
contains data to be transmitted.
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Baud Rate Divisor Latch Register, I/O Port 3F8h, 3F9h/2F8, 2F9h
When bit <7> of the Line Control register is set (1), a write to this pair of locations loads the
decimal value used to divide the 1.8462-MHz clock to create the desired baud rate for serial
transmission. The possible baud rates are shown as follows:
Baud Rate
50
Decimal Divisor
Baud Rate
2400
3600
4800
7200
Decimal Divisor
2304
1536
1047
857
768
384
192
96
48
32
24
16
12
6
3
2
1
75
110
134.5
150
300
9600
19200
38400
57600
115200
600
1200
1800
2000
64
58
Divisor = 1846200 / (Desired baud rate X 16)
Interrupt Enable Register, I/O Port 3F9h/2F9h
Bits <3..0> of this register are used for enabling interrupt sources. A set bit enables interrupt
generation by the associated source.
Bit
7..4
3
Function
Reserved
Modem Status Interrupt Enable (if set) (CTS, DSR, RI, CD)
Receiver Line Status Interrupt Enable (if set) (Overrun error,
parity error, framing error, break)
2
1
0
Transmitter Holding Register Empty Interrupt Enable (if set)
Baud Rate Divisor Interrupt Enable (if set)
Interrupt ID Register, I/O Port 3FAh/2FAh (Read Only)
This read-only register indicates the serial controller as the source of the interrupt (bit <0>) as
well as the reason (bits <3..1>) for the interrupt. Reading this register clears the interrupt and
sets bit <0>.
Bit
Function
7,6
FIFO Enable/Disable
0 = Disabled
1 = Enabled
5,4
Reserved
3..1
Interrupt Source:
000 = Modem status (lowest priority)
001 = Transmitter holding reg. Empty
010 = Received data available
011 = Receiver line status reg.
100,101 = Reserved
110 = Character time-out (highest priority)
111 = Reserved
0
Interrupt Pending (if cleared)
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Chapter 5 Input/Output Interfaces
FIFO Control Register, I/O Port 3FAh/2FAh (Write Only)
This write-only register enables and clears the FIFOs and sets the trigger level and DMA mode.
Bit
Function
7,6
Receiver Trigger Level
00 = 1 byte
01 = 4 bytes
Reserved
10 = 8 bytes
11 = 14 bytes
5..3
2
Transmit FIFO Reset (if set)
1
Receive FIFO Reset (if set)
0
FIFOs Enable/Disable
0 = Disable TX/RX FIFOs, 1 = Enable TX/RX FIFOs
Line Control Register, I/O Port 3FBh/2FBh
This register specifies the data transmission format.
Bit
Function
7
RX Buffer / TX Holding Reg. And Divisor Rate Reg. Access
0 = RX buffer, TX holding reg., and Interrupt En. Reg. Are accessable.
1 = Divisor Latch reg. is accessable.
Break Control (forces SOUT signal low if set)
Stick Parity. If set, even parity bit is logic 0, odd parity bit is logic 1
Parity Type
6
5
4
0 = Odd, 1 = Even
3
2
Parity Enable:
0 = Disabled,
Stop Bit:
1 = Enabled
0 = 1 stop bit,
Word Size:
00 = 5 bits
1 = 2 stop bits
1,0
10 = 7 bits
11 = 8 bits
01 = 6 bits
Modem Control Register, I/O Port 3FCh/2FCh
This register controls the modem signal lines
Bit
7..5
4
3
2
Function
Reserved
Internal Loopback Enabled (if set)
Serial Interface Interrupts Enabled (if set)
Reserved
1
0
RTS Signal Active (if set)
DTR Signal Active (if set)
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Line Status Register, I/O Port 3FDh/2FDh (Read Only)
This register contains the status of the current data transfer. Bits <2..0> are cleared when read.
Bit
7
6
Function
Parity Error, Framing Error, or Break Cond. Exists (if set)
TX Holding Reg. and Transmitter Shift Reg. Are Empty (if set)
TX Holding Reg. Is Empty (if set)
5
4
3
2
Break Interrupt Has Occurred (if set)
Framing Error Has Occurred (if set)
Parity Error Has Occurred (if set)
1
0
Overrun Error Has Occurred (if set)
Data Register Ready To Be Read (if set)
Modem Status Register, I/O Port 3FEh/2FEh (Read Only)
This register contains the status of the modem signal lines. A set bit indicates that the associated
signal is active.
Bit
7
Function
DCD- Active
6
RI- Active
5
DSR Active
4
CTS Active
3
2
1
0
DCD- Changed Since Last Read
RI- Changed From Low to High Since Last Read
DSR- Has Changed State Since Last Read
CTS- Has Changed State Since Last Read
Scratch Pad Register, I/O Port 3FFh/2FFh
This register is not used in this system.
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Chapter 5 Input/Output Interfaces
5.5
PARALLEL INTERFACE
The parallel interface provides connection to a peripheral device that has a compatible interface,
the most common being a printer. The parallel interface function is integrated into the 87307 I/O
controller component and provides bi-directional 8-bit parallel data transfers with a peripheral
device. The parallel interface supports three main modes of operation:
♦
♦
♦
Standard Parallel Port (SPP) mode
Enhanced Parallel Port (EPP) mode
Extended Capabilities Port (ECP) mode
These three modes (and their submodes) provide complete support as specified for an IEEE 1284
parallel port.
5.5.1 STANDARD PARALLEL PORT MODE
The Standard Parallel Port (SPP) mode uses software-based protocol and includes two sub-modes
of operation, compatible and extended, both of which can provide data transfers up to 150 KB/s.
In the compatible mode, CPU write data is simply presented on the eight data lines. A CPU read
of the parallel port yields the last data byte that was written.
The following steps define the standard procedure for communicating with a printing device:
1. The system checks the Printer Status register. If the Busy, Paper Out, or Printer Fault signals
are indicated as being active, the system either waits for a status change or generates an error
message.
2. The system sends a byte of data to the Printer Data register, then pulses the printer STROBE
signal (through the Printer Control register) for at least 500 ns.
3. The system then monitors the Printer Status register for acknowledgment of the data byte
before sending the next byte.
In extended mode, a direction control bit (CTR 37Ah, bit <5>) controls the latching of output
data while allowing a CPU read to fetch data present on the data lines, thereby providing bi-
directional parallel transfers to occur.
The SPP mode uses three registers for operation: the Data register (DTR), the Status register
(STR) and the Control register (CTR). Address decoding in SPP mode includes address lines A0
and A1.
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5.5.2 ENHANCED PARALLEL PORT MODE
In Enhanced Parallel Port (EPP) mode, increased data transfers are possible (up to 2 MB/s) due
to a hardware protocol that provides automatic address and strobe generation. EPP revisions 1.7
and 1.9 are both supported. For the parallel interface to be initialized for EPP mode, a
negotiation phase is entered to detect whether or not the connected peripheral is compatible with
EPP mode. If compatible, then EPP mode can be used. In EPP mode, system timing is closely
coupled to EPP timing. A watchdog timer is used to prevent system lockup.
Five additional registers are available in EPP mode to handle 16- and 32-bit CPU accesses with
the parallel interface. Address decoding includes address lines A0, A1, and A2.
5.5.3 EXTENDED CAPABILITIES PORT MODE
The Extended Capabilities Port (ECP) mode, like EPP, also uses a hardware protocol-based
design that supports transfers up to 2 MB/s. Automatic generation of addresses and strobes as
well as Run Length Encoding (RLE) decompression is supported by ECP mode. The ECP mode
includes a bi-directional FIFO buffer that can be accessed by the CPU using DMA or
programmed I/O. For the parallel interface to be initialized for ECP mode, a negotiation phase is
entered to detect whether or not the connected peripheral is compatible with ECP mode. If
compatible, then ECP mode can be used.
Ten control registers are available in ECP mode to handle transfer operations. In accessing the
control registers, the base address is determined by address lines A2-A9, with lines A0, A1, and
A10 defining the offset address of the control register. Registers used for FIFO operations are
accessed at their base address + 400h (i.e., if configured for LPT1, then 378h + 400h = 778h).
The ECP mode includes several sub-modes as determined by the Extended Control register. Two
submodes of ECP allow the parallel port to be controlled by software. In these modes, the FIFO
is cleared and not used, and DMA and RLE are inhibited.
NOTE: The 87307 does not support ECP v1.7 submode of ECP mode 4.
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Chapter 5 Input/Output Interfaces
5.5.4 PARALLEL INTERFACE PROGRAMMING
5.5.4.1 Parallel Interface Configuration
The parallel interface must be configured for a specific address range (LPT1, LPT2, etc.) and
also must be enabled before it can be used. When configured for EPP or ECP mode, additional
considerations must be taken into account. Address selection, enabling, and EPP/ECP mode
parameters of the parallel interface are affected through the PnP configuration registers of the
87307 I/O controller. Address selection and enabling are automatically done by the BIOS during
POST but can also be accomplished with the Setup utility and other software.
The PnP configuration registers are accessed through I/O registers 15Ch (index) and 15Dh
(data). The parallel interface is initiated by firmware selecting logical device 4 of the 87307. This
is accomplished by the following sequence:
1. Write 07h to I/O register 15Ch.
2. Write 04h to I/O register 15Dh (for selecting the parallel interface).
3. Write 30h to I/O register 15Ch.
4. Write 01h to I/O register 15Dh (this activates the interface).
The parallel interface configuration registers are listed in the following table:
Table 5-12.
Parallel Interface Configuration Registers
Index
Address
30h
31h
60h
61h
70h
71h
74h
Reset
Value
01h
00h
02h
78h
07h
00h
04h
04h
--
Function
Activate
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
I/O Range Check
Base Address MSB
Base Address LSB
Interrupt Select
Interrupt Type
DMA Channel Select
Report DMA Assignment
Configuration Data
75h
F0h
R/W
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5.5.4.2 Parallel Interface Control
The BIOS function INT 17 provides simplified control of the parallel interface. Basic functions
such as initialization, character printing, and printer status are provide by subfunctions of INT
17. The parallel interface is controllable by software through a set of I/O mapped registers. The
number and type of registers available depends on the mode used (SPP, EPP, or ECP). Table 5-13
lists the parallel registers and associated functions based on mode.
Table 5-13.
Parallel Interface Control Registers
I/O
Address
Base
SPP Mode
Ports
LPT1,2,3
LPT1,2,3
EPP Mode
Ports
LPT1,2
LPT1,2
LPT1,2
LPT1,2
LPT1,2
LPT1,2
LPT1,2
LPT1,2
--
ECP Mode
Ports
LPT1,2,3
LPT1,2,3
LPT1,2,3
--
Register
Data
Status
Control
Address
Data Port 0
Data Port 1
Data Port 2
Base + 1h
Base + 2h
Base + 3h
Base + 4h
Base + 5h
Base + 6h
Base + 7h
Base + 400h
Base + 400h
Base + 400h
Base + 400h
Base + 401h
Base + 402h
LPT1,2,3
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
Data Port 3
Parallel Data FIFO
ECP Data FIFO
Test FIFO
Configuration Register A
Configuration Register B
Extended Control Register
LPT1,2,3
LPT1,2,3
LPT1,2,3
LPT1,2,3
LPT1,2,3
LPT1,2,3
--
--
--
--
--
Base Address:
LPT1 = 378h
LPT2 = 278h
LPT3 = 3BCh
The following paragraphs describe the individual registers. Note that only the LPT1-based
addresses are given in these descriptions.
Data Register, I/O Port 378h
Data written to this register is presented to the data lines D0-D7. A read of this register when in
SPP-compatible mode yields the last byte written. A read while in SPP-extended or ECP mode
yields the status of data lines D0-D7 (i.e., receive data).
In ECP mode in the forward (output) direction, a write to this location places a tagged command
byte into the FIFO and reads have no effect.
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Chapter 5 Input/Output Interfaces
Status Register, I/O Port 379h, Read Only
This register contains the current printer status. Reading this register clears the interrupt
condition of the parallel port.
Bit
7
Function
Printer Busy (if 0)
6
5
4
3
Printer Acknowledgment Of Data Byte (if 0)
Printer Out Of Paper (if 1)
Printer Selected/Online (if 1)
Printer Error (if 0)
2
Reserved
1
0
EPP Interrupt Occurred (if set while in EPP mode)
EPP Timeout Occurred (if set while in EPP mode)
Control Register, I/O Port 37Ah
This register provides the printer control functions.
Bit
7,6
5
Function
Reserved
Direction Control for PS/2 and ECP Modes:
0 = Forward. Drivers enabled. Port writes to peripheral (default)
1 = Backward. Tristates drivers and data is read from peripheral
Acknowledge Interrupt Enable
0 = Disable ACK interrupt
4
1 = Enable interrupt on rising edge of ACK
Printer Select (if 0)
Printer Initialize (if 1)
Printer Auto Line Feed (if 0)
Printer Strobe (if 0)
3
2
1
0
Address Register, I/O Port 37Bh (EPP Mode Only)
This register is used for selecting the EPP register to be accessed.
Data Port Registers 0-3, I/O Ports 37C-Fh (EPP Mode Only)
These registers are used for reading/writing data. Port 0 is used for all transfers. Ports 1-3 are
used for transferring the additional bytes of 16- or 32-bit transfers through port 0.
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FIFO Register, I/O Port 7F8h (ECP Mode Only)
While in ECP/forward mode, this location is used for filling the 16-byte FIFO with data bytes.
Reads have no effect (except when used in Test mode). While in ECP/backward mode, reads
yield data bytes from the FIFO.
Configuration Register A, I/O Port 7F8h (ECP Mode Only)
A read of this location yields 10h, while writes have no effect.
Configuration Register B, I/O Port 7F9h (ECP Mode, Read Only)
A read of this location yields the status defined as follows:
Bit
7
6
Function
Reserved (always 0)
Status of Selected IRQn.
Selected IRQ Indicator:
00 = IRQ7
5,4
11 = IRQ5
All other values invalid.
Reserved (always 1)
Reserved (always 000)
3
2..0
Extended Control Register B, I/O Port 7FAh (ECP ModeOnly)
This register defines the ECP mode functions.
Bit
Function
7..5
ECP Submode Select:
000 = Standard forward mode (37Ah <5> forced to 0). Writes are
controlled by software and FIFO is reset.
001 = PS/2 mode. Reads and writes are software controlled and
FIFO is reset.
010 = Parallel Port FIFO forward mode (37Ah <5> forced to 0). Writes are
hardware controlled.
011 = ECP FIFO mode. Direction determined by 37Ah, <5>. Reads and
writes are hardware controlled.
ECP Interrupt Mask:
0 = Interrupt is generated on ERR- assertion.
1 = Interrupt is inhibited.
ECP DMA Enable/Disable.
0 = Disabled
1 = Enabled
ECP Interrupt Generation with DMA
0 = Enabled
4
3
2
1
0
1 = Disabled
FIFO Full Status (Read Only)
0 = Not full (at least 1 empty byte)
1 = Full
FIFO Empty Status (Read Only)
0 = Not empty (contains at least 1 byte)
1 = Empty
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Chapter 5 Input/Output Interfaces
5.5.5 PARALLEL INTERFACE CONNECTOR
Figure 5-5 and Table 5-14 show the connector and pinout of the parallel interface connector.
Figure 5–5. Parallel Interface Connector (Female DB-25 as viewed from rear of chassis)
Table 5-14.
DB-25 Parallel Connector Pinout
Pin
1
2
3
4
5
6
7
8
Signal
STB-
D0
D1
D2
D3
D4
D5
D6
Description
Strobe
Data 0
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
Acknowledge
Busy
Paper End
Select
Pin
14
15
16
17
18
19
20
21
22
23
24
25
--
Signal
LF-
Description
Line Feed
Error
ERR-
INIT-
SLCTIN-
GND
GND
GND
GND
GND
GND
GND
GND
--
Initialize Paper
Select In
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
--
9
D7
10
11
12
13
ACK-
BSY
PE
SLCT
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5.6
KEYBOARD/POINTING DEVICE INTERFACE
The keyboard/pointing device interface provides the connection of an enhanced keyboard and a
mouse using PS/2-type connections. The keyboard/pointing device interface function is provided
by the 87307 I/O controller component, which integrates 8042-compatible keyboard controller
logic (hereafter referred to as simply the “8042”) to communicate with the keyboard and pointing
device using bi-directional serial data transfers. The 8042 handles scan code translation and
password lock protection for the keyboard as well as communications with the pointing device.
This section describes the interface itself. The keyboard is discussed in the Appendix C.
5.6.1 KEYBOARD INTERFACE OPERATION
The data/clock link between the 8042 and the keyboard is uni-directional for Keyboard Mode 1
and bi-directional for Keyboard Modes 2 and 3. (These modes are discussed in detail in
Appendix C). This section describes Mode 2 (the default) mode of operation.
Communication between the keyboard and the 8042 consists of commands (originated by either
the keyboard or the 8042) and scan codes from the keyboard. A command can request an action
or indicate status. The keyboard interface uses IRQ1 to get the attention of the CPU.
The 8042 can send a command to the keyboard at any time. When the 8042 wants to send a
command, the 8042 clamps the clock signal from the keyboard for a minimum of 60 us. If the
keyboard is transmitting data at that time, the transmission is allowed to finish. When the 8042 is
ready to transmit to the keyboard, the 8042 pulls the data line low, causing the keyboard to
respond by pulling the clock line low as well, allowing the start bit to be clocked out of the 8042.
The data is then transferred serially, LSb first, to the keyboard (Figure 5-6). An odd parity bit is
sent following the eighth data bit. After the parity bit is received, the keyboard pulls the data line
low and clocks this condition to the 8042. When the keyboard receives the stop bit, the clock line
is pulled low to inhibit the keyboard and allow it to process the data.
D1
0
D2
1
D3
1
D4
0
D5
1
D6
1
Parity
1
Start
Bit
D0
(LSb)
D7
(MSb)
Stop
Bit
0
1
1
0
Data
Clock
Tcy
Tcl Tch
Parameter
Tss Tsh
Th
Minimum Maximum
Tcy (Cycle Time)
Tcl (Clock Low)
Tch (Clock High)
Th (Data Hold)
Tss (Stop Bit Setup) 8 us
Tsh (Stop Bit Hold) 15 us
0 us
25 us
25 us
0 us
80 us
35 us
45 us
25 us
20 us
25 us
Figure 5–6. 8042-To-Keyboard Transmission of Code EDh, Timing Diagram
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Chapter 5 Input/Output Interfaces
Control of the data and clock signals is shared by the 8042and the keyboard depending on the
originator of the transferred data. Note that the clock signal is always generated by the keyboard.
After the keyboard receives a command from the 8042, the keyboard returns an ACK code. If a
parity error or timeout occurs, a Resend command is sent to the 8042.
Table 5-15 lists and describes commands that can be issued by the 8042 to the keyboard.
Table 5-15.
8042-To-Keyboard Commands
Command
Value
Description
Set/Reset Status Indicators
EDh
Enables LED indicators. Value EDh is followed by an option
byte that specifies the indicator as follows:
Bits <7..3> not used
Bit <2>, Caps Lock (0 = off, 1 = on)
Bit <1>, NUM Lock (0 = off, 1 = on)
Bit <0>, Scroll Lock (0 = off, 1 = on)
Keyboard returns EEh when previously enabled.
Echo
EEh
Invalid Command
Select Alternate Scan Codes
EFh/F1h These commands are not acknowledged.
F0h
Instructs the keyboard to select another set of scan codes
and sends an option byte after ACK is received:
01h = Mode 1
02h = Mode 2
03h = Mode 3
Read ID
F2h
F3h
Instructs the keyboard to stop scanning and return two
keyboard ID bytes.
Instructs the keyboard to change typematic rate and delay
to specified values:
Set Typematic Rate/Display
Bit <7>, Reserved - 0
Bits <6,5>, Delay Time
00 = 250 ms
01 = 500 ms
10 = 750 ms
11 = 1000 ms
Bits <4..0>, Transmission Rate:
00000 = 30.0 ms
00001 = 26.6 ms
00010 = 24.0 ms
00011 = 21.8 ms
:
11111 = 2.0 ms
Enable
F4h
F5h
F6h
Instructs keyboard to clear output buffer and last typematic
key and begin key scanning.
Resets keyboard to power-on default state and halts
scanning pending next 8042 command.
Resets keyboard to power-on default state and enable
scanning.
Default Disable
Set Default
Set Keys - Typematic
Set Keys - Make/Brake
Set Keys - Make
Set Keys - Typematic/Make/Brake
Set Type Key - Typematic
Set Type Key - Make/Brake
Set Type Key - Make
Resend
F7h
F8h
F9h
FAh
FBh
FCh
FDh
FEh
FFh
Clears keyboard buffer and sets default scan code set. [1]
Clears keyboard buffer and sets default scan code set. [1]
Clears keyboard buffer and sets default scan code set. [1]
Clears keyboard buffer and sets default scan code set. [1]
Clears keyboard buffer and prepares to receive key ID. [1]
Clears keyboard buffer and prepares to receive key ID. [1]
Clears keyboard buffer and prepares to receive key ID. [1]
8042 detected error in keyboard transmission.
Resets program, runs keyboard BAT, defaults to Mode 2.
Reset
Note:
[1] Used in Mode 3 only.
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5.6.2 POINTING DEVICE INTERFACE OPERATION
The pointing device (typically a mouse) connects to a 6-pin DIN-type connector that is identical
to the keyboard connector both physically and electrically. The operation of the interface (clock
and data signal control) is the same as for the keyboard. The pointing device interface uses the
IRQ12 interrupt.
5.6.3 KEYBOARD/POINTING DEVICE INTERFACE PROGRAMMING
5.6.3.1 8042 Configuration
The keyboard/pointing device interface must be enabled and configured for a particular speed
before it can be used. Enabling and speed parameters of the 8042 logic are affected through the
PnP configuration registers of the 87307 I/O controller. Enabling and speed control are
automatically set by the BIOS during POST but can also be accomplished with the Setup utility
and other software.
The PnP configuration registers are accessed through I/O registers 15Ch (index) and 15Dh
(data). The keyboard and mouse interfaces are initiated by firmware selecting logical device 0 or
1 of the 87307. This is accomplished by the following sequence:
1. Write 07h to I/O register 15Ch.
2. Write 00h or 01h to I/O register 15Dh (for selecting the keyboard or mouse interface).
3. Write 30h to I/O register 15Ch.
4. Write 01h to I/O register 15Dh (this activates the interface).
The parallel interface configuration registers are listed in the following table:
Table 5-16.
Keyboard/Mouse Interface Configuration Registers
Index
Address
30h
31h
60h
61h
62h
63h
70h
71h
74h
75h
F0h
Reset
Value [2]
01h / 00h
00h / na
02h / na
78h / na
00h / na
00h / na
01h / 0Ch
01h / 01h
04h / 04h
04h / 04h
-- / na
Function
Activate
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
I/O Range Check [1]
Base Address MSB [1]
Base Address LSB [1]
Command Base Address MSB [1]
Command Base Address LSB [1]
Interrupt Select
Interrupt Type
DMA Channel Select
Report DMA Assignment
Configuration Data [1]
R/W
NOTES:
[1] Keyboard I/F only.
[2] Keyboard I/F / Mouse I/F
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Chapter 5 Input/Output Interfaces
5.6.3.2 8042 Control
The BIOS function INT 16 is typically used for controlling interaction with the keyboard. Sub-
functions of INT 16 conduct the basic routines of handling keyboard data (i.e., translating the
keyboard’s scan codes into ASCII codes). The keyboard/pointing device interface is accessed by
the CPU through I/O mapped ports 60h and 64h, which provide the following functions:
♦
♦
♦
♦
Output buffer reads
Input buffer writes
Status reads
Command writes
Ports 60h and 64h can be accessed using the IN instruction for a read and the OUT instruction
for a write. Prior to reading data from port 60h, the “Output Buffer Full” status bit (64h, bit <0>)
should be checked to ensure data is available. Likewise, before writing a command or data, the
“Input Buffer Empty” status bit (64h, bit <1>) should also be checked to ensure space is
available.
I/O Port 60h
I/O port 60h is used for accessing the input and output buffers. This register is used to send and
receive data from the keyboard and the pointing device. This register is also used to send the
second byte of multi-byte commands to the 8042 and to receive responses from the 8042 for
commands that require a response.
A read of 60h by the CPU yields the byte held in the output buffer. The output buffer holds data
that has been received from the keyboard and is to be transferred to the system.
A CPU write to 60h places a data byte in the input byte buffer and sets the CMD/ DATA bit of
the Status register to DATA. The input buffer is used for transferring data from the system to the
keyboard. All data written to this port by the CPU will be transferred to the keyboard except
bytes that follow a multibyte command that was written to 64h
I/O Port 64h
I/O port 64h is used for reading the status register and for writing commands. A read of 64h by
the CPU will yield the status byte defined as follows:
Bit
7..4
3
Function
General Purpose Flags.
CMD/DATA Flag (reflects the state of A2 during a CPU write).
0 = Data
1 = Command
2
1
General Purpose Flag.
Input Buffer Full. Set (to 1) upon a CPU write. Cleared by
IN A, DBB instruction.
0
Output Buffer Full (if set). Cleared by a CPU read of the buffer.
A CPU write to I/O port 64h places a command value into the input buffer and sets the
CMD/DATA bit of the status register (bit <3>) to CMD.
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Table 5-18 lists the commands that can be sent to the 8042 by the CPU. The 8042 uses IRQ1 for
gaining the attention of the CPU.
Table 5-17.
CPU Commands To The 8042
Value
20h
Command Description
Put current command byte in port 60h.
60h
Load new command byte. This is a two-byte operation described as follows:
1. Write 60h to port 64h.
2. Write the command byte to port 60h as follows:
Bit <7> Reserved
<6> Keyboard Code Conversion
0 = Do not convert codes
1 = Convert codes to 9-bit 8088/8086-compatible format
Bit <5> Pointing Device Enable
0 = Enable pointing device
1 = Disable pointing device
Bit <4> Keyboard Enable
0 = Enable keyboard
1 = Disable keyboard
Bit <3> Reserved
Bit <2> System Flag
0 = Cold boot
1 = CPU reset (exit from protected mode)
Bit <1> Pointing Device Interrupt Enable
0 = Disable interrupt
1 = Enable interrupt
Bit <0> Keyboard Interrupt Enable
0 = Disable interrupt
1 = Enable interrupt
A4h
A5h
Test password installed. Tests whether or not a password is installed in the 8042:
If FAh is returned, password is installed.
If F1h is returned, no password is installed.
Load password. This multi-byte operation places a password in the 8042 using the following manner:
1. Write A5h to port 64h.
2. Write each character of the password in 9-bit scan code (translated) format to port 60h.
3. Write 00h to port 60h.
A6h
A7h
A8h
A9h
Enable security. This command places the 8042 in password lock mode following the A5h command.
The correct password must then be entered before further communication with the 8042 is allowed.
Disable pointing device. This command sets bit <5> of the 8042 command byte, pulling the clock line
of the pointing device interface low.
Enable pointing device. This command clears bit <5> of the 8042 command byte, activating the clock
line of the pointing device interface.
Test the clock and data lines of the pointing device interface and place test results in the output buffer.
00h = No error detected
01h = Clock line stuck low
02h = Clock line stuck high
03h = Data line stuck low
04h = Data line stuck high
AAh
ABh
Initialization. This command causes the 8042 to inhibit the keyboard and pointing device and places
55h into the output buffer.
Test the clock and data lines of the keyboard interface and place test results in the output buffer.
00h = No error detected
01h = Clock line stuck low
02h = Clock line stuck high
03h = Data line stuck low
04h = Data line stuck high
ADh
AEh
Disable keyboard command (sets bit <4> of the 8042 command byte).
Enable keyboard command (clears bit <4> of the 8042 command byte).
Continued
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Chapter 5 Input/Output Interfaces
Table 5-17. CPU Commands To The 8042 (Continued)
Value
Command Description
C0h
Read input port of the 8042. This command directs the 8042 to transfer the contents of the input port
to the output buffer so that they can be read at port 60h. The contents are as follows:
Bit <7> Password Enable:
0 = Disabled
1 = Enabled
Bit <6> External Boot Enable:
0 = Enabled
1 = Disabled
Bit <5> Setup Enable:
0 = Enabled
1 = Disabled
Bit <4> VGA Enable:
0 = Enabled
1 = Disabled
Bit <3> Diskette Writes:
0 = Disabled
1 = Enabled
Bit <2> Reserved
Bit <1> Pointing Device Data Input Line
Bit <0> Keyboard Data Input Line
C2h
C3h
D0h
Poll Input Port High. This command directs the 8042 to place bits <7..4> of the input port into the
upper half of the status byte on a continous basis until another command is received.
Poll Input Port Low. This command directs the 8042 to place bits <3..0> of the input port into the lower
half of the status byte on a continous basis until another command is received.
Read output port. This command directs the 8042 to transfer the contents of the output port to the
output buffer so that they can be read at port 60h. The contents are as follows:
Bit <7> Keyboard data stream
Bit <6> Keyboard clock
Bit <5> IRQ12 (pointing device interrupt)
Bit <4> IRQ1 (keyboard interrupt)
Bit <3> Pointing device clock
Bit <2> Pointing device data
Bit <1> A20 Control:
0 = Hold A20 low
1 = Enable A20
Bit <0> Reset Line Status;
0 = Inactive
1 = Active
D1h
D2h
Write output port. This command directs the 8042 to place the next byte written to port 60h into the
output port (only bit <1> can be changed).
Echo keyboard data. Directs the 8042 to send back to the CPU the next byte written to port 60h as if
it originated from the keyboard. No 11-to-9 bit translation takes place but an interrupt (IRQ1) is
generated if enabled.
D3h
Echo pointing device data. Directs the 8042 to send back to the CPU the next byte written to port 60h
as if it originated from the pointing device. An interrupt (IRQ12) is generated if enabled.
Write to pointing device. Directs the 8042 to send the next byte written to 60h to the pointing device.
Read test inputs. Directs the 8042 to transfer the test bits 1 and 0 into bits <1,0> of the output buffer.
Pulse output port. Controls the pulsing of bits <3..0> of the output port (0 = pulse, 1 = don’t pulse).
Note that pulsing bit <0> will reset the system.
D4h
E0h
F0h-
FFh
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5.6.4 KEYBOARD/POINTING DEVICE INTERFACE CONNECTOR
There are separate connectors for the keyboard and pointing device. Both connectors are identical
both physically and electrically. Figure 5-7 and Table 5-18 show the connector and pinout of the
keyboard/pointing device interface connectors.
Figure 5–7. Keyboard or Pointing Device Interface Connector
(as viewed from rear of chassis)
Table 5-18.
Keyboard/Pointing Device Connector Pinout
Pin
1
2
Signal
DATA
NC
Description
Data
Not Connected
Ground
Pin
4
5
6
Signal
+ 5 VDC
CLK
Description
Power
Clock
3
GND
NC
Not Connected
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Chapter 5 Input/Output Interfaces
5.7
UNIVERSAL SERIAL BUS INTERFACE
The Universal Serial Bus (USB) interface provides up to 12 Mb/s data transfers between the host
system and peripherals designed with a compatible USB interface. This high speed interface
supports hot-plugging of compatible devices, making possible system configuration changes
without powering down or even rebooting systems. The USB interface supports both
isochronous and asynchronous communications, and integrates a 5 VDC power bus that can
eliminate the need for external powering of small remote peripherals.
5.7.1 USB KEYBOARD CONSIDERATIONS
The BIOS ROM checks the USB port, during POST, for the presence of a USB keyboard. This
allows a system with only a USB keyboard to be used during ROM-based setup and also on a
system with an OS that does not include a USB driver.
On such a system a keystroke will generate an SMI and the SMI handler will retrieve the data
from the device and convert it to PS/2 data. The data will be passed to the keyboard controller
and processed as in the PS/2 interface. Changing the delay and/or typematic rate of a USB
keyboard though BIOS function INT 16 is not supported.
The system does not support hot-plugging of a USB keyboard, nor is a keyboard attached to a
USB hub supported. A PS/2 keyboard and a USB keyboard can, however, be connected and used
simultaneously.
5.7.2 USB CONFIGURATION
The USB interface functions as a PCI device (7) within the 82371AB component (function 2) and
is configured using PCI Configuration Registers as listed in Table 5-19.
Table 5-19.
USB Interface Configuration Registers
PCI Config.
Addr.
00, 01h
02, 03h
04, 05h
06, 07h
08h
Reset
Value
8086h
7112h
0000h
0280h
00h
PCI Config.
Addr.
0Dh
0Eh
20-23h
3Ch
Reset
Value
00h
80h
All 0’s
00h
Register
Vender ID
Device ID
PCI Command
PCI Status
Register
Latency Timer
Header Type
I/O Space Base Address
Interrupt Line
Interrupt Pin
Revision ID
3Dh
04h
09h
0Ah
0Bh
Programming I/F
Sub Class Code
Base Class Code
00h
03h
0Ch
60h
C0, C1h
--
Miscellaneous Control 1
Miscellaneous Control 2
--
10h
2000h
--
NOTES:
Assume unmarked locations/gaps as reserved.
Refer to applicable Intel documentation for detailed descriptions of registers.
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5.7.3 USB CONTROL
The USB is controlled through I/O registers as listed in table 5-20.
Table 5-20.
USB Control Registers
I/O Addr.
00, 01h
02, 03h
04, 05h
06, 07
Register
Command
Status
Interupt Enable
Frame No.
08, 0B
0Ch
10, 11h
12, 13h
Frame List Base Address
Start of Frame Modify
Port 1 Status/Control
Port 2 Status/Control
5.7.4 USB CONNECTOR
The USB interface provides two identical connectors (ports A and B).
1
2
3
4
Figure 5–8. Universal Serial Bus Connector (one of two as viewed from rear of chassis)
Table 5-21.
USB Connector Pinout
Pin
1
2
Signal
Vcc
USB-
Description
+5 VDC
Data (minus)
Pin
3
4
Signal
USB+
GND
Description
Data (plus)
Ground
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Chapter 6
AUDIO SUBSYSTEM
6.1
INTRODUCTION
This chapter describes the audio subsystem, which features Compaq Premier Sound. The audio
subsystem is compatible with software written for industry-standard sound subsystems. The audio
subsystem can capture and playback .WAV files (as used in most Windows applications). Support
for FM synthesis for playback of MIDI (.MID) files is also included.
This chapter covers the following subjects:
♦
♦
♦
Functional description (6.2) page 6-2
Programming (6.3)
Specifications (6.4)
page 6-8
page 6-11
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Chapter 6 Audio Subsystem
6.2
FUNCTIONAL DESCRIPTION
A block diagram of the audio subsystem is shown in Figure 6-1. The architecture is based on the
ES1869 audio controller that provides the ADC, DAC, FM synthesis, spatializer 3D audio, and
mixing functions. The audio output is processed though a six-level equalizer designed to
compensate for chassis acoustics. A 5-watt low-distortion amplifier (TDA7056A) drives a long-
excursion speaker for optimum sound. All audio functions are controlled by software. The
software volume control uses 6-bit resolution providing 64 levels.
In addition to the connections provided for CD-ROM, four analog interfaces are provided to
connect to external audio devices and are discussed in the following paragraphs.
Line In - This input uses a three-conductor (stereo) mini-jack for connecting left and right
channel line-level signals (20-K ohm impedance). A typical connection would be to a tuner’s
Line Out or Record Out jacks, or to a tape deck’s Line Out or Playback Output jacks. A less
optimum but acceptable connection would be to the headphone output of the tape deck or CD
player.
Line Out - This output uses a three-conductor (stereo) mini-jack for connecting left and right
channel line-level signals (20-K ohm impedance). A typical connection would be to a tape
recorder’s Line In or Record In jacks, to an amplifier’s Line In jacks, or to “powered” computer
speakers that contain amplifiers. Plugging into the Line Out mutes the internal speaker.
Mic In - This input uses a three-conductor (stereo) mini-jack that is specifically designed for
connecting a condenser microphone with an impedance of 1-K ohms. This is the default
recording input after a system reset.
Headphone Out - This output uses a three-conductor (stereo) mini-jack for connecting a pair of
stereo headphones with a minimum impedance of 16 ohms. This jack can also be used to connect
a pair of un-powered or powered speakers of the type designed to be used with portable
radio/cassette/CD players). Using this connector defeats (mutes) the internal speaker and Line
Out signals.
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(L/R)
(L)
Headphones
(R)
Out
Mic In
Equalizer
Circuit
P6
Power
(L+R)
Amp
Mute
(L/R)
(L)
(R)
(L/R)
Line In
ES1869
Audio
Mute
Splitter
Controller
Backplane
Connector
CD Audio (L)
(R)
(L/R)
(L)
Line
(R)
Out
Beep Audio
82371
North Bridge
ISA Bus
Figure 6–1. Audio Subsystem Block Diagram
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Chapter 6 Audio Subsystem
6.2.1 PCM AUDIO PROCESSING
The audio subsystem uses pulse code modulation (PCM) for processing audio that is applied from
external sources to the Mic In and Line In input jacks, as well as audio from an installed CD-
ROM drive. The PCM method is also used in playback of .WAV file data commonly used in
Windows applications.
6.2.1.1 ADC Operation
The Analog-to-Digital Converter (ADC) receives an analog signal and, using pulse code
modulation (PCM) converts it into digital data that can be handled by normal logic circuitry. The
conversion process consists of measuring (sampling) the analog signal at intervals to determine
the amplitude and frequency (see Figure 6-2). The frequency of sampling intervals is a
programmable parameter known as the sampling rate. The higher the sampling rate, the more
accurate the digital representation will be.
Quantized Values
8-Bit
16-Bit
FFFF
FFh
80h
8000h
0000h
00h
S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10
Time
Figure 6–2. Analog Signal Sampling/Quantizing
Each sample is quantized into a digital code that specifies the voltage level of the analog signal at
that particular time. The quantizing format options are as follows:
Mono or stereo
8- or 16-bit
Signed or unsigned
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6.2.1.2 DAC Operation
The digital-to-analog conversion (DAC) simply reverses the procedure of the ADC. The digital
audio data stream is received by the DAC and the quantized values are decoded at the sampling
rate (Figure 6-3A) into DC levels, resulting in a discrete level wave form (Figure 6-3B). A filter
provides the final shaping of the wave (Figure 6-3C) before it is applied to the analog output
circuitry.
Quantized
Values
S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10
A. Quantized Value Decoding
B. Discrete Level Waveform
C. Final Analog Output
Figure 6–3. DAC Operation
Compressed sound formats efficiently use space by concentrating sampling/quantizing in the
middle of the sound spectrum and are suited for voice capture/playback. The DAC of the ES1869
controller supports two type of compressed sound; ADPCM and ESPCM. The ADPCM
compressed format is compatible with common industry sound subsystems while ESPCM is a
proprietary format that offers greater performance.
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Chapter 6 Audio Subsystem
6.2.1.3 PCM Configuration Modes
PCM operation can be configured for compatible ( common sound board functionality) mode or
set up for extended mode, which has some performance advantages. Table 6-1 lists the
differences between the modes of operation.
Table 6-1.
Audio Mode Differences
Compatibility
Extended
Function
Mode
Mode
FIFO Size Available
64 bytes (SW Control)
256 bytes (HW Control)
Mono 8-bit ADC, DAC
Mono 16-bit ADC, DAC
Stereo 8-bit ADC, DAC
Stereo 16-bit ADC
44 KHz Max Sampling
22 KHz Max Sampling
22 KHz Max Sampling
44 KHz Max Sampling
44 KHz Max Sampling
44 KHz Max Sampling
44 KHz Max Sampling
n/a
Stereo 16-bit DAC
11 KHz Max Sampling
44 KHz Max Sampling
Signed/Unsigned Control
AGC During Capture
Programmed I/O Block Transfer
FIFO Status Flags
No
Yes
No
Yes
Yes
Mono Only (22 KHz)
No
No
Yes
Auto Reload DMA
Yes
Time Base for Programmable Time
ADC/DAC Jitter
Sound Blaster Pro Compatible
1 MHz or 1.5 MHz
+/- 2 usec
Yes
800 KHz or 400 KHz
None
No
6.2.1.4 PCM Bus Cycles
The I/O and DMA cycles used by PCM operations to process .WAV data follow standard ISA bus
conventions. All bus transfers occur at the bytes level. Programmed I/O cycles are always used
for programming the control registers and may also be used for transferring audio data to and
from the audio subsystem as well. Quantized audio data is built using the “little endian” format
(LSB occupies the lowest memory address). Data transfers over the ISA occur as shown below.
31
24
16
8
0
Sample 6 Sample 5 Sample 4 Sample 3 Sample 2 Sample 1
8-bit Mono
8-bit Stereo
16-bit Mono
16-bit Stereo
Sample 3 Sample 3 Sample 2 Sample 2 Sample 1 Sample 1
Right
Left
Right
Left
Right
Left
Sample 3
Sample 2
Sample 1
Mono Hi
Mono Lo
Mono Hi
Mono Lo
Mono Hi
Mono Lo
Sample 1
Sample 3
Sample 2
Left Hi
Left Lo
Right Hi
Right Lo
Left Hi
Left Lo
Time
Figure 6–4. Audio Subsystem-to-ISA Bus PCM Audio Data Formats / Byte Ordering
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6.2.2 FM SYNTHESIS AUDIO PROCESSING
The audio subsystem supports playback of MIDI (.MID) files. A .MID file does not contain
audio information in the same way that .WAV files do. In .MID files, audio data consists of note
on/off, tone type, and amplification information. Audio stored in the .MID file format has the
benefit of taking up far less space than audio stored as .WAV files.
The ES1869 controller includes a 20-voice, four-operator frequency modulated (FM) synthesizer.
In FM synthesis, one signal (the carrier) is forced to vary from it’s center frequency by another
signal (the modulator) resulting in a sideband or “harmonic” frequency. The frequency of the
harmonic is determined by the original carrier frequency and the modulating frequency. The
number of harmonics generated is determined by the strength (amplitude) of the modulating
signal. The microsystem that produces the FM signal is called a patch (Figure 6-5).
Frequency Cntrl
Modulator
Oscillator
Modulating Signal
Frequency Cntrl
Amplitude Cntrl
Carrier
FM Signal
Oscillator
Figure 6–5. FM Synthesis Patch
Note that while an analog representation is shown in Figure 6-6. Synthesis occurs as a digital
operation with the results being sent to the DAC.
The FM synthesis process is a playback-only operation involving the writing of .MID data to the
audio subsystem over the ISA bus. The only reads involve checking the controller for status.
Figure 6-6 shows the ISA bus transaction for FM synthesis. Note that if a succeeding data byte is
meant for the same location as the previous byte, the address does not need to be re-written.
A0
IOR-
or
IOC-
Address
Address
Data
or
Data 7..0
Data
Figure 6–6. Audio Car-to-ISA Bus FM Audio Data Format
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Chapter 6 Audio Subsystem
6.3
PROGRAMMING
All programming aspects of the audio subsystem relate directly to the programmability of the
ES1869 controller, upon which the audio subsystem is based. This section describes only the
basic mapping of the audio functions. For a detailed description of the ES1869s registers and
capabilities refer to the ES1869 AudioDrive Data Sheet, ESS Technology, Inc.
6.3.1 CONFIGURATION
The audio subsystem is automatically configured as to base address, DMA, and interrupts
following installation and power up through an on-board EEPROM that provides Plug ‘n Play
support. Software can identify the ES1869 controller by reading indexed address 2n5.40h
successively (where n = 2 for primary address or 4 for secondary address), which should yield the
values 18h, 69h, followed by the base address of the ES1869.
The typical reset/power-up configuration for the audio subsystem is as follows:
Base Address:
Interrupt:
DMA Channel:
Power Management:
220h
IRQ5
1
Automatic
The audio subsystem can be configured or either single DMA channel mode or dual DMA
channel mode. Single DMA channel mode means that capture and playback operations share the
same (playback) DMA channel and only one operation, capture or playback, is possible at a time.
Dual DMA channel operation allows simultaneous capture/playback (full duplex) operation to
occur if desired, but requires the use of two DMA channels. Typically, dual DMA operation
would use DMA channel 1 for capture (recording) and DMA channel 0 or 3 for playback.
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6.3.2 CONTROL
The audio subsystem is controlled through I/O mapped registers listed in Table 6-2.
Table 6-2.
Audio Subsystem I/O Map
I/O
I/O
Address
201h
2n0-2n3
2n4h
Function
Joystick
FM Synthesizer Address/Data [1]
Mixer Address
Mixer Data
Activity/Power Status
Reset Control
Power Management
FM Synthesizer Address/Data [2]
Address
2nAh
2nCh (Read)
2nCh (Write)
2nEh
Function
Read Buffer Input Data
Status
Command/Data
2n5h
Data Available Status
FIFO I/O Address (Extended Mode)
MPU-401 Port
FM Synthesizer (alias of 2n0-2n3h)
--
2n6h (Read)
2n6h (Write)
2n7h
2nFh
3n0, 3n1h
388-38Bh
--
2n8, 2n9h
NOTES:
n = 2 for primary address (default), = 4 for secondary address.
[1] 20-voice operation
[2] 11-voice operation
Not supported
6.3.2.1 PCM Control
The audio subsystem can operate in either Sound Blaster-compatible mode (the default) or in
extended capability mode.
Table 6-3 lists the audio mixer control registers used by software written for Sound Blaster and
other common audio peripherals. These registers are accessed by writing the index value to I/O
port 2n4h and reading the value from or writing the value to I/O port 2n5h.
Table 6-3.
Compatibility Mode Audio Mixer Control Register Mapping
Index
00h
04h
0Ah
0Ch
0Eh
Function
Mixer Reset
Voice Volume
Mic Volume
ADC Recording Source [1]
Stereo/Mono Switch [1]
Index
22h
26h
28h
2Eh
--
Function
Master Volume
FM Volume
CD Volume
Line Volume
--
NOTE: Refer to OEM’s ES1869 data sheet for detailed register descriptions.
[1] The filter functions used in Sound Blaster subsystems are not used in the audio subsystem.
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Chapter 6 Audio Subsystem
The Extended Mode registers are listed in Table 6-4. Like the compatibility registers listed
previously, these registers are accessed by writing the index value to I/O port 2n4h and reading
the value from or writing the value to I/O port 2n5h. Extended mode offers better performance by
providing more precise (higher bit resolution) control of audio levels and more control of audio
processing.
Table 6-4.
Extended Mode Audio Mixer Control Register Mapping
Index
14h
1Ah
1Ch
1Eh
32h
36h
38h
Function
Voice Volume
Mic Volume
ADC (recording) Source
Stereo/Mono Switch
Master Volume
FM Volume
Index
60, 62h
64h
66h
74h
76h
78h
7Ah
Function
Master Volume (Left, Right)
Master Volume Control
Volume Int. Req. Clear
DMA Transfer( 2nd) Count Reload (Low)
DMA Transfer (2nd) Count Reload (Hi)
2nd DMA Control 1
CD Volume
2nd DMA Control 2
3Eh
Line Volume
7Eh
Test Register
NOTE: Refer to OEM’s ES1869 data sheet for detailed registers descriptions.
6.3.2.2 FM Synthesis Control
The FM synthesis logic is typically mapped at 388h-38Bh. A total of 243 registers in two banks
are available. Accessing the registers is accomplished by first writing the index to register 388h
(for bank 0) or 38Ah (for bank 1) followed by writing the data to either 389h or 38Bh (for bank 0
or bank 1 respectively). If a succeeding data byte is destined for the same location then the
address need not be re-written. Location 388h can be read for FM synthesizer status. Table 6-5
lists the FM synthsizer control registers.
Table 6-5.
FM Synthesizer Control Register Mapping
Index
01h
Bank 0 Function
Test - all 0s
Bank 1 Function
Test - all 0s
02h
Timer 1
Not Used
03h
Timer 2
Not Used
04h
05h
08h
20-35h
40-55h
60-75h
80-95h
A0-A8h
B0-B8h
BDh
Timer Mask/Timer Start
Not Used
4-Operator Configure
4-Operator Enable
Not Used
Same as bank 0
Same as bank 0
Same as bank 0
Same as bank 0
Same as bank 0
Same as bank 0
Not Used
Key Scale (KSR) # Determiner
AM, Vib, EG Type, KSR, Mult.
Key Scale Level, Tone Level
Attack Rate, Decay Rate
Sustain Level, Release Rate
Frequency Number
Key On, Block Octave, Frequency No.
Depth of Block Octave, Frequency No.
Stereo Left/Right, Feedback, Connection
Wave Select
C0-C8h
E0-F5h
Same as bank 0
Same as bank 0
NOTE: Refer to OEM’s ES1869 data sheet for detailed registers descriptions.
Abbreviations:
AM Amplitude Modulation (tremolo)
Vib Vibrato
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6.4
SPECIFICATIONS
Table 6-6.
Audio Subsystem Specifications
Paramemter
Sampling Rate
Maximum Input Voltage:
Mic In
Measurement
5.51 KHz to 44 KHz (prgmbl)
.125 Vp-p
1.4 Vrms
Line In
Impedance
Mic In
Line In
Line Out
Headphone Out
Power output (max):
Headphone output
Power amp
1 K ohms (nom)
30 K ohms (nom)
30 K ohms (nom)
16 ohms (min)
60 mW into 16 ohms
5 watts into 8 ohms
Total Harmonic Distortion (power amp):
@ 0.5 watts
@ 5 watts
Mic Preamp Gain
Volume Range
Input
1 %
10 %
26 db
0 - 22.5 db
-46.5 - +10 db
450 - 4000 Hz
Output
Frequency Response (speaker)
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Chapter 6 Audio Subsystem
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Chapter 7
POWER and SIGNAL
DISTRIBUTION
7.1
INTRODUCTION
This chapter describes the power supply and method of general power and signal distribution in
the Compaq Deskpro INDY Personal Computer. Topics covered in this chapter include:
♦
♦
♦
Power supply assembly/control (7.2) page 7-1
Power distribution (7.3)
Signal distribution (7.4)
page 7-5
page 7-7
7.2
POWER SUPPLY ASSEMBLY/CONTROL
This system features a power supply assembly that is controlled through programmable logic
(Figure 7-1).
Front Bezel
System Board
Power On/Off
Slots, Chipsets, Logic
Power On
& Voltage Regulators
+3.3 VDC
PS
On
Fan
Off
+5 AUX
+5 VDC
110/220 VAC
-5 VDC
Power Supply
Assembly
+12 VDC
Drives
-12 VDC
NOTE:
All signals shown entering and exiting the system board pass through the backplane card.
Figure 7–1.
Power Distribution and Control, Block Diagram
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Chapter 7 Power and Signal Distribution
POWER SUPPLY ASSEMBLY
7.2.1
The power supply assembly is contained in a single unit that features a selectable input voltage:
90-132 VAC and 180-264 VAC. The power supply assembly provides +3.3 VDC, +5 VDC, -5
VDC, +12 VDC, and -12 VDC potentials for the system board, expansion board(s), and installed
drives. These voltages are controlled through the power button on the front panel of the system
unit. Pressing and releasing the power button results in system board logic asserting the PS On
signal, which activates the power supply assembly.
The power supply also produces an auxiliary voltage (+5 AUX). The +5 AUX voltage is used for
powering the power button and other logic required for wake-up operation and is produced as
long as the unit is plugged into a live AC outlet.
NOTE: Minimum loading requirements for the power supply must be met at all times to
ensure normal operation and to meet specifications.
Table 7-1 shows the specifications for the power supply.
Table 7-1.
Power Supply Assembly Specifications
(P/N 334112-xxx)
Range/
Tolerance
Min. Current
Loading [1]
Max.
Current
Surge
Current [2]
Max.
Ripple
Parameter
Input Line Voltage:
110 VAC Setting
220 VAC Setting
Line Frequency
Steady State Input (VAC) Current:
+3.3 VDC Output
+5 VDC Output
-5 VDC Output
+5 AUX Output
+12 VDC Output
-12 VDC Output
90 - 132 VAC
180-264 VAC
47 - 63 Hz
--
+/- 1%
+/- 5 %
+/- 10 %
+/- 5 %
+/- 5 %
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
5.50 A
10.0 A
25.0 A
0.15 A
2.00 A
4.50 A
0.15 A
1.40 A
1.40 A
0.00 A
0.10 A
0.07 A
0.00 A
10.0 A
25.0 A
0.15 A
2.00 A
7.00 A
0.15 A
50 mV
50 mV
100 mV
50 mV
120 mV
200 mV
+/- 10 %
NOTES:
[1] Minimum loading requirements must be met at all times to ensure normal operation
and specification compliance.
[2] Surge duration no longer than 10 seconds and +12 tolerance +/- 10%.
The power supply assembly contains a fan that can be shut down by the Fan Off signal, which is
asserted from the system board logic during sleep (suspend) states. The power supply can
override the Fan Off signal if the temperature in the power supply assembly is too high.
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7.2.2 POWER CONTROL
The power supply assembly is controlled digitally by the PS On signal (Figure 6-1). When PS On
is asserted, the Power Supply Assembly is activated and all voltage outputs (+3 VDC, +5 AUX,
+/-5 VDC, +/-12 VDC) are produced. When PS On is de-asserted, the Power Supply Assembly is
off and all voltages (except +5 AUX) are not generated. Note that +5 AUX is always produced as
long as the system is connected to a live AC source (as indicated by an illuminated system board
LED).
7.2.2.1 Power Button
The PS On signal is typically controlled through the Power Button which, when pressed and
released, applies a negative (grounding) pulse to the power control logic. (Refer to section 7.2.2.3
for PS On control select.) The resultant action of pressing the power button depends on the state
and mode of the system at that time and is described as follows:
System State
Pressed Power Button Results In:
Off
Negative pulse, of which the falling edge results in power control logic asserting
PS On signal to Power Supply Assembly, which then initializes. ACPI four-
second counter is not active.
On, ACPI Disabled
On, ACPI Enabled
Negative pulse, of which the falling edge causes power control logic to de-assert
the PS On signal. ACPI four-second counter is not active.
Pressed and Released Under Four Seconds:
Negative pulse, of which the falling edge causes power control logic to
generate SMI-, set a bit in the SMI source register, set a bit for button status,
and start four-second counter. Software should clear the button status bit
within four seconds and the Suspend state is entered. If the status bit is
not cleared by software in four seconds PS On is de-asserted and the
power supply assembly shuts down (this operation is meant as a guard if
the OS is hung).
Pressed and Held At least Four Seconds Before Release:
If the button is held in for at least four seconds and then released, PS On is
negated, de-activating the power supply.
7.2.2.2 Power LED Indications
Two LEDs are used to indicate system power status. The front panel (bezel) power LED provides
a visual indication of three key system conditions listed as follows:
Power LED
Condition
Steady On
Normal full-on operation
Blinking @ 1 Hz
Blinking @ 4 Hz
Sleep (suspend) state
Thermal condition: processor has overheated and shut down
An additional LED is mounted on the system board. This LED is connected to the +5 AUX bus
and will be on as long as the system unit is connected to live AC power regardless of the status
of the PS On signal. The AC line cord should always be disconnected and the system board LED
should not be illuminated before servicing the unit.
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Chapter 7 Power and Signal Distribution
7.2.2.3 PS On Control Select
The assertion of the PS On signal can be controlled through DIP switch SW1-6 as follows:
SW1-6 Closed (on) – PS On signal is asserted when unit is plugged into a live AC socket and
power supply assembly produces all voltages (system boots immediately).
SW1-6 Open (off) – PS On signal asserted by pressed power button.
7.2.2.4 Wake Up Events
The PS On signal can also be activated with a power “wake-up” of the system due to the
occurrence of a magic packet, serial port ring, or PCI power management (PME) event. These
events can be individually enabled by the Setup utility through the GPIO of the system security
ASIC to wake up the system from a sleep (low power) state. The wake up sequence for each event
occurs as follows:
♦
Wake On LAN (WOL) - If a compliant network interface controller is installed and enabled
for remote wake-up, reception of a “Magic Packet” results in the assertion of the high R-
MPKT pulse signal (received through the WOL header P9) to the power control logic, which
will assert PS On. Note that the NIC adapter must be able to draw five volts power from
header P9 during the system sleep state.
♦
♦
Modem Ring – A ring indication on serial port A (COM1) will, if enabled, be detected by the
power control logic and cause the PS On signal to be asserted.
PME Event – A power management event that asserts the PME- signal on the PCI bus can
be enabled to cause the power control logic to generate the PS On signal. Note that the PCI
card must have a second source of power to operate during the system unit’s sleep state.
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7.3
POWER DISTRIBUTION
7.3.1 3.5/5/12 VDC DISTRIBUTION
The power supply assembly includes a multi-connector cable assembly that routes +3.3 VDC, +5
VDC, -5 VDC, +12 VC, and -12 VDC to the system board as well as to the individual drive
assemblies.
P6
P6
P5
P3
Drive
Assemblies
4
3
2
1
P4
P3-P5
1
2
3
4
Power Supply
Assembly
P1 (ATX-type)
P1
(SP# 334112-001)
11 12 13 14 15 16 17 18 19 20
Backplane
Board
1
2
3
4
5
6
7
8
9 10
Connector
Pin 1
+3.3
+3.3
+12
+5
Pin 2
+3.3RS
-12
GND
GND
Pin 3
Pin 4
Pin 5
RTN
RTN
Pin 6
+5
RSRTN
Pin 7
RTN
RTN
Pin 8
Fan Off
-5
Pin 9
+5AUX
+5
Pin 10
+12
+5
P1
P1 [1]
P3-P5
P6
RTN
RTN
GND
GND
+5
PS On
+5
+12
NOTES:
[1] This row represents pins 11-20 of the P1 connector.
All + and - values are VDC.
RTN = Return (signal ground)
GND = Power ground
RS = Remote sense
= Deviation from ATX standard. PWR GD signal is produced by the south bridge component.
Figure 7–2. Power Cable Diagram
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Chapter 7 Power and Signal Distribution
7.3.2 LOW VOLTAGE DISTRIBUTION
Voltages less than 3.3 VDC and processor core voltage are produced through regulator circuitry
on the system board.
LM317
Regulator
Circuit
+5 AUX
+3 AUX
2.5 VDC
Power Button and
Wake Up Logic
LM317
Regulator
Circuit
+5 VDC
Pull-Up Logic
Power Supply
+3.3 VDC
Regulator
Circuit
VTT (+1.5 VDC)
+5 VDC
Processor
+12 VDC
VID0
VID1
VID2
VID3
VID4
VccP (see text)
Regulator
Circuit
Processor
Figure 7–3. Low Voltage Supply, Block Diagram
The VccP regulator produces the VccP (processor core) voltage according to the state of the
VID4..0 signals from the processor. This allows automatic selection of the proper core voltage
depending on the installed processor component. The possible voltages available are listed as
follows:
VID4..0 VccP
VID4..0 VccP
VID4..0 VccP
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
3.5 VDC
11011
11100
11101
11110
00000
00001
00010
00011
00100
00101
00110
2.4 VDC
2.3 VDC
2.2 VDC
2.1 VDC
2.05 VDC
2.00 VDC
1.95 VDC
1.90 VDC
1.85 VDC
1.80 VDC
1.75 VDC
00111
01000
01001
01010
01011
01100
01101
01110
01111
11111
1.70 VDC
3.4 VDC
3.3 VDC
3.2 VDC
3.1 VDC
3.0 VDC
2.9 VDC
2.8 VDC
2.7 VDC
2.6 VDC
2.5 VDC
1.65 VDC
1.60 VDC
1.55 VDC
1.50 VDC
1.45 VDC
1.40 VDC
1.35 VDC
1.30 VDC
CPU not installed
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7.4
SIGNAL DISTRIBUTION
Figure 7-4 shows general signal distribution between the main subassemblies of the system unit.
PCI Bus
PCI
Slot
Pwr On
WOL
10/100
NIC
Card
WOL
WOL
Conn
Pwr Btn
HD Activity
P9 [1]
P5 [1]
P29
+5AUX
Blk LED
PCI Bus
Power On/Off
LED
Conn
Pwr/HD LEDs, Pwr Btn
HD Activity
LED
ISA Bus
Conn
Wide Ultra
SCSI
Hard Drive
PCI Bus
PCI
Slot
Wide Ultra SCSI
Controller Card
3/5/12
VDC
3.3, 5
12 VDC
Power
5,
12 VDC
Power
Conn
Fan/PS
Cntrl
P1
Fan Off
Supply
Assembly
PS On
Riser
Card
Conn
J50
Backplane
Board
Hood Sw
IDE I/F
System
Board
IDE I/F
IDE I/F
Pri. IDE
5, 12 VDC
IDE
Hard Drive
P20
Conn
CD-ROM
Sec. IDE
Conn
5, 12 VDC
P21
CD
Audio
CD Audio
Dsk I/F
Audio
Conn
P7 [1]
Dsk. I/F
Diskette Drive
Dsk.
Conn
5, 12 VDC
P10
Fan
Conn
Fan Sens.
Audio
Fan Pwr
Audio
Chassis Fan
P8 [1]
P6
Spkr
Conn
Chassis Spkr
AGP Bus
Graphics
Card
AGP
Slot
Kybd/
Mouse
Conn
Keyboard
J6
Mouse
NOTES:
CDS models and minitowers.
3200 and 6400 models
4300 and 9100 models
[1] See Figure 7-5 for header pinout.
Figure 7–4. Signal Distribution Diagram
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Chapter 7 Power and Signal Distribution
Header P5
(Panel LEDs, Pwr Btn)
Pins
1,3
2,3
4
5
6
7
8
9,10
Function
Cover Lock & 12 VDC
Cover Unlock & 12 VDC
Not connected
Power LED (-)
HD LED (-)
Power LED (+)
HD LED (+)
Power Button
1
2
4
6
3
5
7
9
8
10
Header P7
(CD Audio)
1
Pins
1,3
2
Function
Signal ground
Left Audio Channel
Right Audio Channel
2
3
4
4
Header P8
(Chassis Fan)
Pins
Function
1
2
1
2
3
4
Fan present sense
Fan Power (-)
Key
4
Fan Power (+)
Header P9
(Wake On LAN)
Pins
Function
+5 AUX
Ground
1
2
3
1
2
3
WOL signal
NOTE:
No polarity consideration required for cable connection to
header P6 (speaker) or P29 (SCSI HD LED).
Figure 7–5. Backplane Header Pinouts
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Chapter 8
BIOS ROM
8.1
INTRODUCTION
The Basic Input/Output System (BIOS) of the computer is a collection of machine language
programs stored as firmware in read-only memory (ROM). The BIOS ROM includes such
functions as Power-On Self Test (POST), PCI device initialization, Plug ‘n Play support, power
management activities, and Setup. This chapter includes the following topics:
♦
♦
♦
♦
♦
Boot/reset functions (8.2)
page 8-2
page 8-3
page 8-4
page 8-19
page 8-21
Memory detection and configuration (8.3)
Desktop management support (8.4)
PnP support (8.5)
Power management functions (8.6)
The firmware contained in the BIOS ROM supports the following operating systems and
specifications:
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
DOS 6.2
Windows 3.1
Windows for Workgroups 3.11
Windows 95
Windows 98
Windows NT 3.5 and 4.0
OS/2 ver 2.1
OS/2 Warp
SCO Unix
DMI 2.0
Intel Wired for Management (WfM) initiative
The microprocessor accesses the BIOS ROM as a 128-KB block from E0000h to FFFFFh. The
BIOS data is shadowed in a 64-KB block in the upper memory area. The BIOS segments are
dynamically paged in and out of the 64-KB block as they are needed.
NOTE:
This chapter describes BIOS in general and focuses on aspects of BIOS unique
to this particular system. For detailed information regarding the BIOS, refer to the
Compaq Basic Input/Output System Technical Reference Guide.
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Chapter 8 BIOS ROM
8.2
BOOT/RESET FUNCTIONS
The system supports new system boot functions to support remote ROM flashing and PC97
requirements. This system also supports the EL Torito specification for bootable CDs.
8.2.1 BOOT BLOCK
This system includes 24 KB of write-protected boot block ROM that provides a way to recover
from a failed remote flashing of the system BIOS ROM. Early during the boot process, the boot
block code checks the system ROM. If validated, the system BIOS continues the boot sequence.
If the system ROM fails the check, the boot block code provides the minimum amount of support
necessary to allow booting the system from the diskette drive (bypassing the security measures)
re-flashing the system ROM with a ROMPAQ diskette. Since video is not available during the
initial boot sequence the boot block routine uses the keyboard LEDs to communicate status as
follows:
Num Lock
Off
Caps Lock
On
Scroll Lock
Meaning
Off
Off
On
On
Administrator password required.
Boot failed. Reset required for retry.
Flash failed (set by ROMPAQ).
Flash complete (set by ROMPAQ).
On
Off
On
Off
Off
On
8.2.2 QUICKBOOT
The QuickBoot mode (programmable through the INT 15, AX=E845h call) skips certain portions
of the POST (such as the memory count) during the boot process unless the hood has been
detected as being removed. The QuickBoot mode is programmable as to be invoked always, never
(default) or every x-number of days.
8.2.3 SILENTBOOT
When in the SilentBoot mode, the boot process skips certain audio and visual aspects of POST
(such as the speed beeps and screen messages). Error messages are still displayed. The
QuickBoot mode is programmable by the Setup utility (through the INT 15, AX=E845h call) as
to either TERSE (default) or VERBOSE mode.
8.2.4 RESET
There are two types of system resets: hard and soft. A hard reset is traditionally generated after
power-up and produced by the circuitry generating the PWRGOOD signal. The 82371 south
bridge, however, allows software to generate a hard reset. This is accomplished by first writing a
one (1) to bit <1> of I/O port 0CF9h. A one is then written to bit <2> of 0CF9h. This causes the
82371 to create a hard reset by asserting CPURST#, PCIRST#, and RSTDRV for at least 1 ms.
After the reset the 82371 automatically clears bit <2> of 0CF9h.
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8.3
MEMORY DETECTION AND CONFIGURATION
This system uses the Serial Presence Detect (SPD) method of determining the installed DIMM
configuration. The BIOS communicates with an EEPROM on each DIMM through an I2C-type
bus to obtain data on the following DIMM parameters:
♦
♦
♦
♦
Presence
Size
Type
Timing/CAS latency
NOTE: Refer to Chapter 3, “Processor/Memory Subsystem” for the SPD format and DIMM
data specific to this system.
The BIOS performs memory detection and configuration with the following steps:
1. Set Memory Buffer Strength – The memory controller must be configured for correct buffer
drive strength. The BIOS provides this function by reading the number of module banks,
ECC enable/disable status, and SDRAM width data from the DIMMs and transferring that
data to the memory controller. SPD bytes checked: 5, 11, 13
2. Determine DIMM Presence/Type – The BIOS checks each memory socket for DIMM
presence. If present, the DIMM type and CAS latency is determined. SPD bytes checked: 2,
9, 10, 18, 23, 24.
Check Sequence:
a. SPD byte 2 is read for all slots first. A failed read or returned value of other than 02h
(EDO) or 04h (SDRAM) results in the slot marked as empty. If mixed types are detected
then only SDRAMs are used (see chapter 3 for details).
b. SPD byte 18 is read for maximum CAS latency, followed by reads of bytes 9 and 10 for
bus speed compatibility. A DIMM detected as too-slow results in an error.
c. If the DIMM can handle the memory bus speed at maximum CAS latency then bytes 23
and 24 are checked to see if the DIMM can work maximum CAS latency minus 1. Once
all slots are checked, the greatest CAS latency (2 or 3) is used. A DIMM detected as
incompatible will result in a bit in CMOS being set and the Num Lock LED on the
keyboard will blink for a short time. Depending on the progress of the BIOS routine a
POST message may be displayed before the system locks up.
3. Initialize SDRAM – If SDRAM are installed then each row containing SDRAM will be
initialized. This step includes pre-charging all banks, sending a CAS-before-RAS command,
sending a Mode-Register-Set-Enable command, reading DIMM location/CAS latency data,
and sending a Normal Op command.
4. Memory Sizing – The SPD bytes 3, 4, and 17 are checked for number of row and column
addresses and (for SDRAM) the number of internal banks.
5. Memory Timing – For SDRAM, the memory controller requires the RAS pre-charge time
and the RAS-to-CAS delay time. SPD bytes checked: 27and 29.
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Chapter 8 BIOS ROM
8.4
DESKTOP MANAGEMENT SUPPORT
Desktop Management deals with issues of security, identification, and system management
functions. Desktop Management is provided by BIOS INT 15 functions listed Table 8-1.
Table 8-1.
Desktop Management Functions (INT15)
AX
Function
Mode
E800h
E807h
E813h
E814h
E816h
E817h
E818h
E819h
E81Ah
E81Bh
E81Eh
E820h
E822h
E827h
E828h
E845h
E846h
Get system ID
Real, 16-, & 32-bit Prot.
Real, 16-, & 32-bit Prot.
Real, 16-, & 32-bit Prot.
Real, 16-, & 32-bit Prot.
Real, 16-, & 32-bit Prot.
Real
Get System Information Table
Get monitor information
Get system revision
Get temperature status
Get drive attribute
Get drive off-line test
Get chassis serial number
Write chassis serial number
Get drive threshold
Real
Real, 16-, & 32-bit Prot.
Real
Real
Real
Real
Get drive ID
System Memory Map
Flash ROM/Sys. Admin. Fnc.
DIMM EEPROM Access
Inhibit power button
Access CMOS Feature Bits
Security Functions
Real, 16-, & 32-bit Prot.
Real, 16-, & 32-bit Prot.
Real, 16-, & 32-bit Prot.
Real, 16-, & 32-bit Prot.
Real, 16-, & 32-bit Prot.
All 32-bit protected mode calls are accessed by using the industry-standard BIOS32 Service
Directory. Using the service directory involves three steps:
1. Locating the service directory.
2. Using the service directory to obtain the entry point for the client management functions.
3. Calling the client management service to perform the desired function.
The BIOS32 Service Directory is a 16-byte block that begins on a 16-byte boundary between the
physical address range of 0E0000h-0FFFFFh. The format is as follows:
Offset No. Bytes
Description
00h
04h
08h
09h
0Ah
0Bh
4
4
1
1
1
5
Service identifier (four ASCII characters)
Entry point for the BIOS32 Service Directory
Revision level
Length of data structure (no. of 16-byte units)
Checksum (should add up to 00h)
Reserved (all 0s)
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To support Windows NT an additional table to the BIOS32 table has been defined to contain 32-
bit pointers for the DDC and SIT locations. The Windows NT extension table is as follows:
; Extension to BIOS SERVICE directory table (next paragraph)
db
db
db
dd
dw
db
dd
dw
db
dd
dw
“32OS”
2
“$DDC”
?
; sig
; number of entries in table
; DDC POST buffer sig
; 32-bit pointer
; byte size
; SIT sig
; 32-bit pointer
; byte size
; ESCD sig
; 32-bit pointer
; bytes size
?
“$SIT”
?
?
“$ERB”
?
?
The service identifier for Desktop Management functions is “$CLM.” Once the service identifier
is found and the checksum verified, a FAR call is invoked using the value specified at offset 04h
to retrieve the CM services entry point. The following entry conditions are used for calling the
Desktop Management service directory:
INPUT:
EAX
= Service Identifier [$CLM]
EBX (31..8)
EBX (7..0)
CS
= Reserved
= Must be set to 00h
= Code selector set to encompass the physical page holding
entry point as well as the immediately following physical page.
It must have the same base. CS is execute/read.
= Data selector set to encompass the physical page holding
entry point as well as the immediately following physical page.
It must have the same base. DS is read only.
= Stack selector must provide at least 1K of stack space and be 32-bit.
DS
SS
(I/O permissions must be provided so that the BIOS can support as necessary)
OUTPUT:
AL
= Return code:
00h, requested service is present
80h, requested service is not present
81h, un-implemented function specified in BL
86h and CF=1, function not supported
EBX
ECX
EDX
= Physical address to use as the selector BASE for the service
= Value to use as the selector LIMIT for the service
= Entry point for the service relative to the BASE returned in EBX
The following subsections describe aspects of Desktop Management unique to this system. For a
general description of these BIOS functions refer to the Compaq BIOS Technical Reference
Guide.
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Chapter 8 BIOS ROM
8.4.1 SYSTEM ID
The INT 15, AX=E800h BIOS function can be used to identify the system board. This function
will return the system ID in the BX register.
System Board
CMOS ID
ROM Type
System ID
007998 or 008123
7Eh
686T3
0400h
8.4.2 SYSTEM INFORMATION TABLE
The System Information Table (SIT) is a comprehensive list of fixed configuration information
arranged into records. The INT 15 AX=E807h BIOS function accesses the SIT by returning a
pointer in ES:BX to indicate the location of the SIT. This section lists the default values that
should be read from the SIT. For specific bit descriptions and more detailed information on the
SIT refer to the Compaq Basic Input/Output System (BIOS) Technical Reference Guide.
Power Conservation Record, SIT Record 01h
Default
Byte
00h
01h
02h
03h
04h
05h
06h-0Bh
0Ch
Function
Record ID
No. of Data Bytes in Record
Volume, CPU Speed, Screensave, PWR Consv. Mode
LED Blink, Popup, APM, PC Level, MAXBRIGHT Control
SW Power Cntrl., Screensave/Hard Drive Timeouts, PWR
Magic Packet Flag, SMI, Modem Installed
Popup Location
Value
01h
0Bh
07h
C4h
90h
[1]
[2]
39h
Quick Engy. Save, Magic Packet PWR, Suspend, CPU Sp.
NOTES:
[1] Will be determined at runtime
[2] Unsupported function - read all 0s.
Timeout Counter Record (System Standby), SIT Record 02h
Default
Value
02h
09h
0
10
15
20
30
Byte
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
Function
Record ID for System Standby Timeout
No. of Data Bytes in Record
First Value
60
120
180
240
Last Value
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Timeout Counter Record (Video Screensave), SIT Record 03h
Default
Value
03h
0Ch
0
Byte [1]
00h
01h
Function
Record ID for Video Screensave Timeout
No. of Data Bytes in Record
First Value
02h
03h
5
04h
10
05h
15
06h
20
07h
30
08h
40
09h
50
0Ah
0Bh
0Ch
0Dh
60
120
180
240
Last Value
NOTE:
[1] Offset from byte 00h of timeout record 02h.
Timeout Counter Record (Hard Drive), SIT Record 04h
Default
Value
04h
06h
0
Byte [1]
15h
16h
Function
Record ID for Hard Drive Timeout
No. of Data Bytes in Record
First Value
17h
18h
10
19h
15
1Ah
1Bh
1Ch
20
30
60
Last Value
NOTE:
[1] Offset from byte 00h of timeout record 02h.
Security Record, SIT Record 05h
Default
Value
05h
04h
7Fh
1Fh
7Ah
[1]
Byte
00h
01h
02h
03h
04h
05h
Function
Record ID
No. of Data Bytes in Record
NVRAM/HD Lock, QuickLock/QuickBlank, FD Boot, PWR Pwd
Virus Detect, Serial/Parallel Cntrl., FD Drive Cntl., Stby Cntrl.
Diskette Drive Fnct., Password Functions
Password Locking, Ownership Tag Length
NOTE:
[1] Determined by system at runtime.
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Chapter 8 BIOS ROM
Processor/Memory/Cache Record, SIT Record 06h
Default
Value
06h
Byte
00h
Function
Record ID
01h
02h, 03h
04h
No. of Data Bytes in Record
Installed Microprocessor Speed
Cache Configuration
L2 Cache Size
0Eh
[1]
07h
20h
05h
06h
L2 Cache Speed
00h
07h
08h, 09h
Total Memory Amount Adjustment
Total Soldered Memory
06h
0000h
8001h
0000h
00h
0Ah, 0Bh Maximum Memory Installable
0Ch, 0Dh Reserved
0Eh
0Fh
Processor Designer
System Cache Error Correction
01h
NOTE: [1] Determined by system at runtime.
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Peripheral and Input Device Record, SIT Record 07h
Default
Value
07h
3Ah
27h
Byte
00h
01h
02h
Function
Record ID
No. of Data Bytes in Record
DMA Functions, SCSI Support, Flashable ROM, Setup
Partition, 101 Keyboard
03h
Erase-Eaze Kybd. Support in ROM, El Torito CD Boot
Support, QuickBoot, ROM Functions
Formfactor
Softdrive 1 & 2 Data
Softdrive 3 & 4 Data
53h
04h
05h
06h
07h-0Ah
0Bh
0Ch
[1]
FFh
FFh
B0 B5 BA BFh
00h
12h
00h
[1]
Softdrive 1-4 Starting Address
Panel ID
Integrated Monitor, ROM Socket, No. of Prog. Serial Ports
Parallel Port Mode, Modem Type
Drive Fault Prediction Support for Drives 0-3
PCI Bus Master CMOS Data
VGA Palette Snoop Function
Misc. PCI Information
0Dh
0Eh
0Fh, 10h
11h, 12h
13h
14h, 15h
16h
17h
18h
19h
1Ah
0000h
0000h
01h
0000h
00h
[1]
I/O Address for I2C Device
I2C Information Byte
ATAPI Device Information (Logical Devices 1 & 2)
ATAPI Device Information (Logical Devices 3 & 4)
3-D Audio Support
BIOS Supported Features
Misc. Features (Power Inhibit Support)
[1]
00h
01h
01h
[1]
1Bh
1Ch, 1Dh Back-to-Back I/O Delay Index 0
1Eh, 1Fh
20h, 21h
22h, 23h
24h
Back-to-Back I/O Delay Index 1
Back-to-Back I/O Delay Index 2
Back-to-Back I/O Delay Index 3
Back-to-Back I/O Delay NVRAM Location
Bit Mask for Byte 24h
[1]
[1]
[1]
n/a
25h
n/a
26h
27h
28h-2Bh
2Ch-2Dh
2Eh
2Fh
30h
31h
32h
O/S Boot NVRAM Location
Bit Mask for Byte 26h
00h
00h
[1]
IDE Drive 0-3 Max DMA/PIO Mode
Offset Address in EBDA for Bezel Button
Processor Upgrade Mounting
Parallel Port Connector Type/Pinout
Serial Port Connector Type
Serial Port Maximum Speed
Serial Port Maximum Speed
Serial Port Maximum Speed
DMA Burst Mode Support
n/a
06h
41h
01h
01h
C2h
00h
[1]
33h
34h
35h
36h
37h
38h
39h
3Ah
3Bh
Keyboard Connector Type
System UDMA Capabilities
Diskette Type Installed
On-Board NIC Speed
On-Board NIC Attributes
03h
0Fh
01h
00h
00h
[1]
General Purpose Software Support
System EDMA Support
0Fh
NOTE:
[1] Determined at run time.
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Chapter 8 BIOS ROM
Memory Module Information Record, SIT Record 08h
Default
Value
08h
0Dh
03h
00h
[1]
Byte
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
Function
Record ID
No. of Data Bytes in Record
No. of Sockets
Memory Socket Location 0
Memory Installed In Location 0
Memory Speed In Location 0
Memory Form Factor 0
Memory Socket Location 1
Memory Installed In Location 1
Memory Speed In Location 1
Memory Form Factor 1
Memory Socket Location 2
Memory Installed In Location 2
Memory Speed In Location 2
Memory Form Factor 2
[1]
03h
01h
[1]
[1]
03h
02h
[1]
[1]
03h
NOTE: [1] Determined at runtime.
Timeout Default Record, SIT Record 09h
Default
Value
09h
Byte
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
Function
Record ID
No. of Data Bytes in Record
High Power - Standby
High Power - Hard Drive/System Idle
High Power - Screensave
High Power - Maximum Brightness
High Power - Processor Speed
Medium Power - Standby
Medium Power - Hard Drive/System Idle
Medium Power - Screensave
Medium Power - Maximum Brightness
Medium Power - Processor Speed
0Ah
15 min
15 min
15 min
100 min
100 min
15 min
15 min
15 min
100 min
100 min
CMOS/NVRAM Information Record, SIT Record 0Ah
Default
Value
0Ah
05h
00h
00h
00h
00h
00h
Byte
00h
01h
02h
03h
04h
05h
06h
Function
Record ID
No. of Data Bytes in Record
Size of EISA NVRAM or Extended CMOS (Low Byte)
Size of EISA NVRAM or Extended CMOS (High Byte)
Size of High CMOS (Low Byte)
Size of High CMOS (High Byte)
NVRAM Storage Device Access Type
Automatic Server Recovery Record, SIT Record 0Bh (Not Used)
Memory Banks Information Record, SIT Record 0Ch (Not Used)
Multiprocessor Feature Information Record, SIT Record 0Dh (Not Used)
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Extended Disk Support Record, SIT Record 0Eh
Default
Value
0Eh
02h
[1]
[1]
Byte
00h
01h
02h
03h
Function
Record ID
No. of Data Bytes in Record
Pointer To Extended Disk table (High Byte)
Pointer To Extended Disk table (Low Byte)
NOTE: [1] Determined at runtime.
System Record, SIT Record 0Fh (Not Used)
Product Name Header Record, SIT Record 10h
Default
Byte
00h
Function
Record ID
Value
10h
01h
02h-12
13h
No. of Data Bytes in Record
Product Name
Terminator Byte
12h
“Compaq Deskpro EN”
00h
DC-DC Converter Record, SIT Record 11h (Not Used)
Processor Microcode Patch Record, SIT Record 12h
Default
Value
Byte
Function
00h
Record ID
12h
01h
No. of Data Bytes in Record
Patch 1 Version
3Ch
02h-05h
06h-09h
0Ah-0Dh
0Eh-11h
12h-15h
16h-19h
1Ah-1Dh
1Eh-21h
22h-25h
26h-29h
2Ah-2Dh
2Eh-31h
32h-35h
36h-39h
3Ah-3Dh
00000020h
09031996h
00000632h
00000032h
12121996h
00000633h
00000033h
06161997h
00000634h
00000005h
08151997h
00000650h
00000015h
11241997h
00000650h
Patch 1 Date
Patch 1 Family/Model/Stepping
Patch 2 Version
Patch 2 Date
Patch 2 Family/Model/Stepping
Patch 3 Version
Patch 3 Date
Patch 3 Family/Model/Stepping
Patch 4 Version
Patch 4 Date
Patch 4 Family/Model/Stepping
Patch 5 Version
Patch 5 Date
Patch 5 Family/Model/Stepping
System Hood Removal Record, SIT Record 13h
Default
Value
13h
Byte
00h
Function
Record ID
01h
No. of Data Bytes in Record
09h
02h-05h
06h
07h
08h
09h
Hood Removed Time Stamp (Year/Month/Day/Hours/Min/Sec
Hood Removal Support CMOS Byte Offset
Hood Removal Support Bit Location
Hood Removal NOBOOT CMOS Byte Offset
Hood Removal NOBOOT CMOS Bit Location
Software Hood Lock
[1]
00h
30h
00h
00h
[1]
0Ah
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Chapter 8 BIOS ROM
NOTE: [1] Determined at runtime.
DMI System Slots Support Record, SIT Record 16h
Default
Value
16h
1Ah
[1]
0Fh
05h
[1]
03h
00h
06h
05h
[1]
03h
01h
06h
05h
[1]
03h
02h
06h
05h
[1]
03h
03h
06h
05h
[1]
Byte
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
Function
Record ID
No. of Data Bytes in Record
Number of Slots
Type of Slot
Data Width of Slot
Slot Usage/Length/Virtual
Slot Category
Slot ID
Type of Slot
Data Width of Slot
Slot Usage/Length/Virtual
Slot Category
Slot ID
Type of Slot
Data Width of Slot
Slot Usage/Length/Virtual
Slot Category
Slot ID
Type of Slot
Data Width of Slot
Slot Usage/Length/Virtual
Slot Category
Slot ID
Type of Slot
Data Width of Slot
Slot Usage/Length/Virtual
Slot Category
03h
04h
Slot ID
NOTE:
[1] Determined at runtime.
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8.4.3 EDID RETRIEVE
The BIOS function INT 15, AX=E813h is a tri-modal call that retrieves the VESA extended
display identification data (EDID). Two subfunctions are provided: AX=E813h BH=00h retrieves
the EDID information while AX=E813h BX=01h determines the level of DDC support.
Input:
AX
BH
BH
= E813h
= 00 Get EDID .
= 01 Get DDC support level
If BH = 00 then
DS:(E)SI = Pointer to a buffer (128 bytes) where ROM will return block
If 32-bit protected mode then
DS:(E)SI = Pointer to $DDC location
Output:
(Successful)
If BH = 0:
DS:SI=Buffer with EDID file.
= Number of bytes written
= 0
CX
CF
AH
=00h Completion of command
If BH = 1:
BH
= System DDC support
<0>=1 DDC1 support
<1>=1 DDC2 support
BL
= Monitor DDC support
<0>=1 DDC1 support
<1>=1 DDC2 support
<2>=1 Screen blanked during transfer
(Failure)
CF
= 1
AH
= 86h or 87h
8.4.4 DRIVE FAULT PREDICTION
The Compaq BIOS provides direct Drive Fault Prediction support for IDE-type hard drives. This
feature is provided through two BIOS calls. Function INT 15, AX=E817h is used to retrieve a
512-byte block of drive attribute data while the INT 15, AX=E81Bh is used to retrieve the drive’s
warranty threshold data. If data is returned indicating possible failure then the following
message is displayed:
“1720-Intellisafe Hard Drive detects imminent failure”
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Chapter 8 BIOS ROM
8.4.5 SYSTEM MAP RETRIEVAL
The BIOS function INT 15, AX=E820h will return base memory and ISA/PCI memory
contiguous with base memory as normal memory ranges. This real mode call will indicate
chipset-defined address holes that are not in use, motherboard memory-mapped devices, and all
occurrences of the system BIOS as reserved. Standard PC address ranges will not be reported.
Input:
EBX
ECX
EDX
= continuation value or 00000000h to start at beginning of map
= number of bytes to copy (>=20)
= 534D4150h ('SMAP')
ES:DI = buffer for result (see below)
Offset Size Description
00h QWORD base address
08h QWORD length in bytes
10h DWORD type of address range
01h memory, available to OS
02h reserved, not available (e.g. system ROM, memory-mapped device)
other: not defined
Output:
If CF=0 (success)
EAX
EBX
ECX
= 534D4150h ('SMAP')
= next offset from which to copy or 00000000h if finished
= actual length returned in bytes
ES:DI buffer filled
If CF=1 (failure)
AH = Error Code (86h)
In order to determine the entire memory map, multiple calls must be made.
For example, the first call would be:
Input:
EDX = 534D4150h
EBX = 00h
ECX = 14h
ES:DI = some buffer to store information.
Output:
EAX = 534D4150h
EBX = 01h
ECX = 14h
ES:DI = 00 00 00 00 00 00 00 00 00 FC 09 00 00 00 00 00 01 00 00 00
(indicates 0-639k is available to the OS)
Consecutive calls would continue until EBX returns with 0, indicating that the memory map is
complete.
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8.4.6 FLASH ROM FUNCTIONS
The system BIOS may be upgraded by flashing the ROM using the INT 15, AX=E822h BIOS
interface, which includes the necessary subfunctions. An upgrade utility is provided on a
ROMPAQ diskette. The upgrade procedure is described at the end of this chapter. Corrupted
BIOS code will be indicated by the keyboard LEDs during the boot sequence as described
previously in section 8.2.1.
8.4.7 POWER BUTTON FUNCTIONS
The BIOS includes an interface for controlling the system unit’s power button. The power button
can be disabled and enabled.
The INT 15, AX=E822h, BL=08h function can be invoked to disable the power button,
preventing a user from inadvertently powering down the system. This tri-modal function is
typically used in the ROM flashing procedure to reduce the chance of an accidental power down
while the BIOS is being upgraded.
Entry:
AX
BL
= E822h
= 08h
Return:
(Successful)
CF
= 0
AH
= 00
(Failure)
CF
= 1
AH
= 86, not supported
NOTE: With the Disable function invoked the system can still be powered down by
holding the power button in for four seconds or more.
The INT 15, AX=E822h, BL=09h function is used to restore the power button to the state it was
in prior to invoking the Disable (BL=08h) function.
Entry:
AX
BL
= E822h
= 09h
Return:
(Successful)
CF
= 0
AH
= 00
(Failure)
CF
= 1
AH
= 86, call not supported
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Chapter 8 BIOS ROM
8.4.8 ACCESSING CMOS
Configuration memory data can be retrieved with the BIOS call INT 15, AX=E823h. This tri-
modal function retrieves a single byte from the CMOS map described in Chapter 4. The function
is described as follows:
INPUT:
EAX
BH
= E823h
= 0, Read
= 1, Write
BL
CX
= Value to write (if a write is specified)
= Bytes number (zero-based)
OUTPUT:
(Successful)
CF
= 0
AH
= 00h
AL
= Byte value (on a read)
(Failure)
CF
= 1
AH
= 86h, Function not supported
= FFh, byte does not exist
8.4.9 ACCESSING CMOS FEATURE BITS
The BIOS function INT 15, AX=E845h is a tri-modal call for accessing areas in non-volatile
memory (CMOS) used for storing variables for various features. Note that this function differs
from the previously discussed call since data blocks of varying lengths are retrieved.
INPUT:
EAX
BL
= E845h
= 0, Read
= 1, Write
BH
CX
= Value Read/to Write
= Feature Bits Number (refer to following description box)
DS:SI = Pointer to buffer passing multiple byte features
OUTPUT:
(Successful)
CF
= 0
EAX
= Reserved
BH
= Value read (on a read)
(Failure)
CF
= 1
AH
= 86h, Function not supported
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Default
CX
0000h
Function
PCI 2.1 Mode (Enabled)
Value
1b
0001h
Erase Eaze Keyboard (off)
11b
0002h
0003h
0004h
0005h
0006h
0007h
0008h
0009h
Comm/IR Port Designation (Comm port)
No Rejection of SETs By PnP (reject SETs)
PCI VGA Snoop (snoop disabled)
PCI Bus Mastering BIOS Support (enabled)
Auto Prompt for Auto Setup (prompt for F1, F2, F10)
Mode 2 Configuration Support (enabled)
Secondary Hard Drive Controller Enabled (enabled)
Secondary Hard Drive Controller IRQ (IRQ15)
Custom Drive Type #1
0b
0b
0b
1b
00b
1b
1b
11b
000Ah
40 bits, all 0s
000Bh
Custom Drive Type #2
40 bits, all 0s
000Ch
000Dh
000Eh
000Fh
0010h
Custom Drive Type #3
Custom Drive Type #4
POST Verbose/Terse or “Silent Boot” Mode (Terse)
Drive Translation Mode (translate)
Mfg. Process Number Bytes
Administrator Password
40 bits, all 0s
40 bits, all 0s
1b
0b
30 bits, [1]
72 bits, [1]
0011h
0012h
Power-On Password
32 bits, [1]
0013h
Ownership Tag
640 bits, [1]
0014h
0015h
Warm Boot Password Mode (disabled)
Hood Lock (enabled)
0b
0b
0016h
Hood Removal (disabled)
00b
0017h
USB Security (disabled)
1b
0018h
0019h
Configurable Power Supply (legacy mode)
QuickBoot Mode (full boot always)
Onboard NIC (1A)/SCSI (1B)/Pri. IDE (1C) Enables
Ultra SCSI Mode
QuickLock/QuickBlank Enables
Serial Port 1/Port 2 Security
Parallel Port Security
1b
11111b
1b/1b/1b
1b
0b/0b
1b/1b
1b
001A-001Ch
001Dh
001E, 001Fh
0020, 0021h
0022h
0023, 0024h
0025h
Diskette Drive Bootability/Writeability
Asset Tag
0b/0b
[1]
0026h
Back-to-Back I/O Delay
00b
0027h
CMOS /10h-2Fh Backup
[1]
0028h
QuickLock after Standby Enable
Audio Enable/IRQ/DMA/Address
ECP DMA Configuration
Serial Port 1 Base I/O Address/Interrupt
Serial Port 2 Base I/O Address/Interrupt
Ultra DMA-33 Enable
0b
0029-002Ch
002Dh
002E, 002Fh
0030, 0031h
0032h
1b/01b/10b/00b
011b
3Fh/00b
1Fh/00b
1111b
0033h
0034h
Network Server Mode Enable
CIA BOM No. Bytes
0b
[1]
0035h
0036h
0037h
Copy Standard CMOS to Backup Location
AGP Monochrome Adapter Search Enable
APM Fan Throttle
[1]
1b
1b
0038h
Manufacturing Diags Mode
0b
0039h
RIPL ROM Boot Mode
0b
003Ah
Exit Clean Boot Screen
[1]
003B-003Dh
003Eh
Ethernet Speed/Mode/Connector Type
ACPI Enable
S/W BOM Serial Number of Bytes
Select ECP Mode
000b/00b/001b
1b
[1]
1b
003Fh
0040h
NOTE:
For full bit definitions refer to the Compaq BIOS Technical Reference Guide.
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[1] Determined at runtime.
8.4.10 SECURITY FUNCTIONS
The INT 15 AX=E846h BIOS function is used to control various security features of the system.
This function may be issued by a remote system (over a network). The issuing driver must build a
request buffer for each security feature prior to making the call. This system supports the
following security features:
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
QuickLock
QuickBlank
Diskette drive boot disable
Diskette drive write disable
IDE controller disable
Serial ports disable
Parallel port disable
Change administrator password
QuickLock on suspend
Ownership tag
USB disable
The write-protect function that determines diskette write control is extended to cover all drives
that use removable read/write media (i.e., if diskette write protect is invoked, then any diskette
drive, power drive (SCSI and/or ATAPI), and floptical drive installed will be inaccessible for
(protected from) writes). Client management software should check the following bytes of SIT
record 07h for the location and access method for this bit:
System Information Table, Peripheral and Input Device Record (07h) (partial listing)
Byte
1Fh
20h
Bit
7-0
Function
Removable Read/Write Media Write Protect Enable Byte Offset (0-255)
Removable Read/Write Media Write Protect Enable Bit Location:
7..4
3..0
CMOS Type:
0000 = CMOS
0001 = High CMOS
0010 = NVRAM
0011 = Flat model NVRAM
Bit Location:
0000 = Bit 0
0001 = Bit 1
0010 = Bit 2
0011 = Bit 3
0100 = Bit 4
0101 = Bit 5
0110 = Bit 6
0111 = Bit 7
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8.5
PNP SUPPORT
The BIOS includes Plug ’n Play (PnP) support for PnP version 1.0A.
NOTE: For full PnP functionality to be realized, all peripherals used in the system must
be designed as “PnP ready.” Any installed ISA peripherals that are not “PnP ready” can
still be used in the system, although configuration parameters may need to be considered
(and require intervention) by the user.
Table 8-2 shows the PnP functions supported (for detailed PnP information refer to the Compaq
BIOS Technical Reference Guide):
Table 8-2.
PnP BIOS Functions
Function Register
00h
01h
02h
03h
04h
50h
51h
Get number of system device nodes
Get system device node
Set system device node
Get event
Send message
Get SMBIOS Structure Information
Get Specific SMBIOS Structure
The BIOS call INT 15, AX=E841h, BH=01h can be used by an application to retrieve the default
settings of PnP devices for the user. The application should use the following steps for the display
function:
1. Call PnP function 01(get System Device Node) for each devnode with bit 1 of the control
flag set (get static configuration) and save the results.
2. Call INT 15, AX=E841h, BH=01h.
3. Call PnP “Get Static Configuration” for each devnode and display the defaults.
4. If the user chooses to save the configuration, no further action is required. The system board
devices will be configured at the next boot. If the user wants to abandon the changes, then
the application must call PnP function 02 (Set System Device Node) for each devnode (with
bit 1 of the control flag set for static configuration) with the results from the calls made prior
to invoking this function.
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Chapter 8 BIOS ROM
8.5.1 SMBIOS
In support of the DMI specification the PnP functions 50h and 51h are used to retrieve the
SMBIOS data. Function 50h retrieves the number of structures, size of the largest structure, and
SMBIOS version. Function 51h retrieves a specific structure. This system supports SMBIOS
version 2.1 and the following structure types:
Type
0
Data
BIOS Information
1
System Information
3
4
System Enclosure or Chassis
Processor Information
5
6
7
Memory Controller Information
Memory Module Information
Cache Information
8
9
Port Connector Information
System Slots
10
12
13
16
17
18
19
20
On Board Device Information
System Configuration Options
BIOS Language Information
Physical Memory Array
Memory Devices
Memory Error Information
Memory Array Mapped Addresses
Memory Device Mapped Addresses
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8.6
POWER MANAGEMENT FUNCTIONS
The BIOS ROM provides three types of power management support: independent PM support;
APM support, and ACPI support.
8.6.1 INDEPENDENT PM SUPPORT
The BIOS ROM can provide power management of the system independently from any software
(OS or application) that is running on the system. In this mode the BIOS uses a timer to
determine when to switch the system to a different power state. State switching is not reported to
the OS and occurs as follows:
On – The computer is running normally and is drawing full power.
Standby – The computer is in a low power state. In this state the processor and chipset are still
running and the VSYNC signal to the monitor is turned off. Returning to the On state requires
very little time and will be initiated by any of the following actions:
a. key stroke
b. mouse movement
Off – The computer is not running and drawing practically no power at all.
8.6.2 ACPI SUPPORT
This system meets the hardware and firmware requirements for being ACPI compliant. The
BIOS function INT 15 AX=E845h can be used to check or set the ACPI enable/disable status of
the system, which defaults to the “ACPI enabled” state. The setup option for ACPI should be
disabled if APM/PnP is to be used with Windows 98 or when disabling power management and
PnP support for NT5.0. A hardware redetection should be made with Windows 98 and a reinstall
of Windows NT5.0 should be performed when an ACPI switch is made.
This system supports the following ACPI functions:
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
PM timer
Power button
Power button override
RTC alarm
Sleep/Wake logic (S1, S4 (NT), S5
Legacy/ACPI select
C1 state (Halt)
C2 state (STOPGRANT)
C3 state (no clock)
PCI PME
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Chapter 8 BIOS ROM
8.6.3 APM SUPPORT
Advanced Power Management (APM) BIOS support provides interaction between the BIOS
ROM and the operating system (OS). The BIOS advises the OS when a power state transition
should occur. The OS then notifies the appropriate driver(s) and reports back to the BIOS.
For maximum energy-conservation benefit, APM functionality should be implemented using the
following three layers:
♦
♦
♦
BIOS layer (APM BIOS (ver. 1.2, 1.1, 1.0))
Operating system (OS) layer (APM driver)
Application layer (APM-aware application or device driver)
The process starts with the OS or driver making a connection with the BIOS through an APM
BIOS call. In a DOS environment POWER.EXE makes a Real mode connection. In Windows 3.1
and in Windows 95, a 32-bit connection is made. Currently Windows NT does not make an APM
connection.
With power management enabled, inactivity timers are monitored. When an inactivity timer
times out, an SMI is sent to the microprocessor to invoke the SMI handler. The SMI handler
works with the APM driver and APM BIOS to take appropriate action based on which inactivity
timer timed out.
Two I/O ports are used for APM communication with the SMI handler:
Port Address
0B2h
Name
APM Control
APM Status
0B3h
Three power states are defined under power management:
On - The computer is running, all subsystems are on and drawing full power. Any activity in the
following subsystems will reset the activity timer, which has a default setting of 15 minutes
before Standby entered:
a. Keyboard
b. Mouse
c. Serial port
d. Diskette drive
e. Hard drive
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Standby - The computer is in a low power state: video is off, some subsystems may be drawing
less power, and the microprocessor is halted except for servicing interrupts. Video graphics
controller is under driver control and/or VSYNC is off and the power supply fan is turned off.
Any of the following activities will generate a wake-up SMI and return the system to On:
a. Keyboard
b. Mouse
c. Serial port
d. Diskette drive
e. Hard drive
f. RTC Alarm
If no APM connection is present, the BIOS will set an APM timer to 45 minutes, at which
time the Suspend will be entered if no activity has occurred. This function can be defeated (so
that Suspend will not be achieved). If an APM connection is present, the BIOS APM timer is
not used and Suspend is entered only by user request either through an icon in Windows 95 or
by pressing and releasing the power button under 4 seconds.
Suspend - The computer is in a low power state: video graphics controller is under driver control
and/or HSYNC and VSYNC are off, some subsystems may be drawing less power, and the
microprocessor is halted except for servicing interrupts. Any of the following activities will
generate a wake-up SMI and return the system to On:
a. Keyboard
b. Mouse
c. Serial port
d. Diskette drive
e. Hard drive
f. RTC Alarm
g. Network interface controller
The APM BIOS for this system supports APM 1.2 as well as previous versions 1.1 and 1.0. The
APM BIOS functions are listed in Table 8-3.
Table 8-3.
APM BIOS Functions (INT15)
AX
Function
5300h
5301h
5302h
5303h
5304h
5305h
5306h
5307h
5308h
5309h
530Ah
530Bh
530Ch
530Dh
530Eh
530Fh
5380h
APM Installation Check
APM Connect (Real Mode)
APM Connect (16-bit Protected Mode)
APM Connect (32-bit Protected Mode)
Interface Disconnect
CPU Idle
CPU Busy
Set Power State [1]
Enable/Disable Power Management
Restore Power On Defaults
Get Power Status
Get PM Event
Get Power State
Enable/Disable Device Power Management
APM Driver Version
Engage/Disengage Power Management
OEM (Compaq) Specific APM Function
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Chapter 8 BIOS ROM
8.7
USB LEGACY SUPPORT
The BIOS ROM checks the USB port, during POST, for the presence of a USB keyboard. This
allows a system with only a USB keyboard to be used during ROM-based setup and also on a
system with an OS that does not include a USB driver.
On such a system a keystroke will generate an SMI and the SMI handler will retrieve the data
from the device and convert it to PS/2 data. The data will be passed to the keyboard controller
and processed as in the PS/2 interface. Changing the delay and/or typematic rate of a USB
keyboard though BIOS function INT 16 is not supported.
The system does not support hot-plugging of a USB keyboard, nor is a keyboard attached to a
USB hub supported. A PS/2 keyboard and a USB keyboard can, however, be connected and used
simultaneously.
8.8
BIOS UPGRADING
The flash ROM device can be re-written with updated BIOS code if necessary. The flashing
procedure is as follows:
FORMAT A: /S
1. Create a system (bootable) diskette using the
command in DOS.
2. Download the appropriate BIOS firmware from the Compaq web site.
3. Copy the downloaded BIOS file and the flash utility file onto the boot diskette.
4. Unzip the BIOS and flash utility files, which should result in an .exe file and a .bin file.
5. Place the boot diskette into drive A: and reboot the system.
.exe
.bin”
filename
6. At the A: prompt, type in “filename
(there is a space between the file
names) and press Enter.
7. At the Flash Memory Write menu, to the question “Do you want to save BIOS?” select Y. If
you want to save the current BIOS then type the current BIOS name and the extension after
“File name to save” (example: type in 613j900.bin). Alternately, select N if you do not want
to save the current BIOS.
8. To the question “Are you sure to program?” select Y.
9. Wait until the message “Power Off or Reset the system,” indicating the BIOS has been
loaded successfully. Then remove the boot diskette. Should power be lost or the system
reset during this time (before the message is displayed) the BIOS code in ROM will
likely be corrupted and the procedure will have to be repeated (starting at step 5).
10. Turn off (power down) the system.
11. While holding the End key down, turn on (power up) the system, making sure the End key
is held down until the Setup utility is entered.
12. Complete the Setup utility as appropriate.
13. Re-boot the system.
If the BIOS code is corrupted due to a failed ROM flash the keyboard LEDs provide an indication
of the problem during the boot process as described in section 8.2.1.
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Appendix A
ERROR MESSAGES AND CODES
A.1
A.2
INTRODUCTION
This appendix lists the error codes and a brief description of the probable cause of the error. Note
that not all errors listed in this appendix may be applicable to a particular system depending on
the model and/or configuration.
POWER-ON MESSAGES
Table A-1.
Power-On Messages
Message
CMOS Time and Date Not Set
(none)
Run Setup
Beeps
(None)
2 short
(None)
Probable Cause
Invalid time or date
Power-On successful
Any failure
A.3
BEEP/KEYBOARD LED CODES
Table A-2.
Beep/Keyboard LED Codes
Beeps
LED Blinking [1]
Probable Cause
1 short, 2 long
1 long, 2 short
2 long, 1 short
NUM Lock
CAP Lock
Scroll Lock
Base memory failure.
Video/graphics controller failure.
System failure (prior to video initialization).
NOTE:
[1] PS/2 keyboard only.
Compaq Personal Computers A-1
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Appendix A Error Messages and Codes
A.4
POWER-ON SELF TEST (POST) MESSAGES
Table A-3.
Power-On Self Test (POST) Messages
Error Message
Probable Cause
Bad PnP Serial ID Checksum
Address Lines Short!
Cache Memory Failure, Do Not Enable
Cache!
Serial ID checksum of PnP card was invalid.
Error in address decoding circuitry on system board.
Defective cache memory, CPU has failed.
CMOS Battery Failed
Low RTC/CMOS battery
CMOS Checksum Invalid
CMOS System Options Not Set
CMOS Display Type Mismatch
Previous and current checksum value mismatch.
Corrupt or non-existant CMOS values.
Graphics/video type in CMOS does not match type detected by
BIOS.
CMOS Memory Size Mismatch
CMOS Time and Date Not Set
Diskette Boot Failure
Memory amount detected does not match value stored in CMOS.
Time and date are invalid.
Boot disk in drive A: is corrupt.
DMA Bus Timeout
DMA Controller Error
Bus driven by device for more than 7.8 us
Error in one or both DMA controllers.
Drive Not Ready Error
BIOS cannot access the diskette drive.
BIOS cannot communicate with diskette drive controller.
Diskette drive controller has requested a resource already in use.
Diskette Drive Controller Failure
Diskette Drive Controller Resource
Conflict
Diskette Drive A: Failure
BIOS cannot access drive A:.
Diskette Drive B: Failure
BIOS cannot access drive B:
Gate A20 Failure
Invalid Boot Diskette
Gate A20 of keyboard controller not working.
BIOS can read but cannot boot system from drive A:.
Keyboard controller failure.
Locked keyboard.
Key pressed down.
Error exists in master DMA controller.
Master interrupt controller failure.
Amount of memory detected is less than stated value in CMOS.
ESCD data was re-initialized due to NVRAM checksum error.
Keyboard Controller Error
Keyboard is Locked…Please Unlock It
Keyboard Stuck Key Detected
Master DMA Controller Error
Master Interrupt Controller Error
Memory Size Decreased
NVRAM Checksum Error, NVRAM
Cleared
NVRAM Cleared By Jumper
NVRAM Data Invalid, NVRAM Cleared
Off Board Parity Error Addr. (HEX) = X
Parallel Port Resource Conflict
PCI Error Log is Full
NVRAM has been cleared by removal of jumper.
Invalid entry in ESCD.
Parity error occurred in expansion memory, x= address of error.
Parallel port has requested a resource already in use.
PCI conflict error limit (15) has been reached.
Two devices requested the same resource.
PCI I/O Port Conflict
PCI Memory Conflict
Two devices requested the same resource.
Primary Boot Device Not Found
Primary IDE Cntrl. Resource Conflict
Primary Input Device Not Found
Secondary IDE Controller Resource
Serial Port 1 Resource Conflict
Serial Port 2 Resource Conflict
Slave DMA Controller Error
Slave Interrupt Controller Error
Static Device Resource Conflict
System Board Device Resource
Conflict
Designated primary boot device could not be found.
Primary IDE controller requested a resource already in use.
Designated primary input device could not be found.
Secondary IDE controller has requested a resource already in use.
Serial port 1 requested a resource already in use.
Serial port 2 requested a resource already in use.
Error exists in slave DMA controller.
Slave interrupt controller failure.
A non-PnP ISA card has requested a resource already in use.
A non-PnP ISA card has requested a resource already in use.
System Memory Size Mismatch
Amount of memory detected on system board is different from
amount indicated in CMOS.
NOTE:
PCI and PnP messages are displayed with bus, device, and function information.
A-2 Compaq Personal Computers
Changed - April 1998
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Technical Reference Guide
A.5
PROCESSOR ERROR MESSAGES (1xx-xx)
Table A-4.
Processor Error Messages
Message
101-01
101-02
101-91..94
102-01
102-02
102-03
102-04
102-05
102-06
102-07
102-08
102-09
102-10
102-11
102-12
102-15
102-16
102-17
102-18
102-19
102-20
102-21
103-01
103-02
103-03
104-01
104-02
104-03
105-01
105-02
105-03
105-04
105-05
105-06
105-07
Probable Cause
CPU test failed
32-bit CPU test failed
Multiplication test failed
Message Probable Cause
105-08
105-09
105-10
105-11
105-12
105-13
105-14
106-01
107-01
108-02
108-03
109-01
109-02
109-03
110-01
Port 61 bit <1> not at one
Port 61 bit <0> not at one
Port 61 I/O test failed
Port 61 bit <7> not at zero
Port 61 bit <2> not at zero
No interrupt generated by failsafe timer
NMI not triggered by failsafe timer
Keyboard controller test failed
CMOS RAM test failed
FPU initial sts. word incorrect
FPU initial cntrl. Word incorrect
FPU tag word not all ones
FPU tag word not all zeros
FPU exchange command failed
FPU masked exception error
FPU unmasked exception error
FPU wrong mask status bit set
FPU unable to store real number
FPU real number calc test failed
FPU speed test failed
CMOS interrupt test failed
CMOS not properly initialized (interrupt test)
CMOS clock load data test failed
CMOS clock rollover test failed
CMOS not properly initialized (clock test)
Programmable timer load data test failed
Programmable timer dynamic test failed
Program timer 2 load data test failed
Refresh detect test failed
FPU pattern test failed
FPU is inoperative or not present 110-02
Weitek not responding
Weitek failed register trnsfr. Test
110-03
111-01
Weitek failed arithemetic ops test 112-01
Speed test Slow mode out of range
Speed test Mixed mode out of range
Speed test Fast mode out of range
Speed test unable to enter Slow mode
Speed test unable to enter Mixed mode
Speed test unable to enter Fast mode
Speed test system error
Unable to enter Auto mode in speed test
Unable to enter High mode in speed test
Speed test High mode out of range
Speed test Auto mode out of range
Speed test variable speed mode inoperative
Protected mode test failed
Weitek failed data conv. Test
Weitek failed interrupt test
Weitek failed speed test
112-02
112-03
112-04
112-05
112-06
112-07
112-08
112-09
112-10
112-11
112-12
113-01
114-01
116-xx
199-00
--
DMA page registers test failed
DMA byte controller test failed
DMA word controller test failed
Master int. cntlr. test fialed
Slave int. cntlr. test failed
Int. cntlr. SW RTC inoperative
Port 61 bit <6> not at zero
Port 61 bit <5> not at zero
Port 61 bit <3> not at zero
Port 61 bit <1> not at zero
Port 61 bit <0> not at zero
Port 61 bit <5> not at one
Port 61 bit <3> not at one
Speaker test failed
Way 0 read/write test failed
Installed devices test failed
--
Compaq Personal Computers A-3
Changed – April 1998
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Appendix A Error Messages and Codes
A.6
MEMORY ERROR MESSAGES (2xx-xx)
Table A-5.
Memory Error Messages
Message
200-04
200-05
200-06
200-07
200-08
201-01
202-01
202-02
202-03
203-01
203-02
203-03
204-01
204-02
204-03
204-04
204-05
205-01
205-02
205-03
206-xx
210-01
210-02
210-03
211-01
211-02
211-03
213-xx
214-xx
215-xx
Probable Cause
Real memory size changed
Extended memory size changed
Invalid memory configuration
Extended memory size changed
CLIM memory size changed
Memory machine ID test failed
Memory system ROM checksum failed
Failed RAM/ROM map test
Failed RAM/ROM protect test
Memory read/write test failed
Error while saving block in read/write test
Error while restoring block in read/write test
Memory address test failed
Error while saving block in address test
Error while restoring block in address test
A20 address test failed
Page hit address test failed
Walking I/O test failed
Error while saving block in walking I/O test
Error while restoring block in walking I/O test
Increment pattern test failed
Memory increment pattern test
Error while saving memory during increment pattern test
Error while restoring memory during increment pattern test
Memory random pattern test
Error while saving memory during random memory pattern test
Error while restoring memory during random memory pattern test
Incompatible DIMM in slot x
Noise test failed
Random address test
A.7
KEYBOARD ERROR MESSAGES (30x-xx)
Table A-6.
Keyboard Error Messages
Message
300-xx
301-01
301-02
301-03
301-04
301-05
302-xx
302-01
303-01
303-02
303-03
303-04
Probable Cause
Failed ID test
Message
303-05
303-06
303-07
303-08
303-09
304-01
304-02
304-03
304-04
304-05
304-06
--
Probable Cause
LED test, LED command test failed
LED test, LED command test failed
LED test, LED command test failed
LED test, command byte restore test failed
LED test, LEDs failed to light
Keyboard repeat key test failed
Unable to enter mode 3
Incorrect scan code from keyboard
No Make code observed
Cannot /disable repeat key feature
Unable to return to Normal mode
--
Kybd short test, 8042 self-test failed
Kybd short test, interface test failed
Kybd short test, echo test failed
Kybd short test, kybd reset failed
Kybd short test, kybd reset failed
Failed individual key test
Kybd long test failed
LED test, 8042 self-test failed
LED test, reset test failed
LED test, reset failed
LED test, LED command test failed
A-4 Compaq Personal Computers
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Technical Reference Guide
A.8
PRINTER ERROR MESSAGES (4xx-xx)
Table A-7.
Printer Error Messages
Message
401-01
402-01
402-02
402-03
402-04
402-05
402-06
402-07
402-08
402-09
Probable Cause
Message
402-10
402-11
402-12
402-13
402-14
402-15
402-16
402-01
498-00
--
Probable Cause
Printer failed or not connected
Printer data register failed
Printer control register failed
Data and control registers failed
Loopback test failed
Loopback test and data reg. failed
Loopback test and cntrl. reg. failed
Loopback tst, data/cntrl. reg. failed
Interrupt test failed
Interrupt test and control reg. failed
Interrupt test, data/cntrl. reg. failed
Interrupt test and loopback test failed
Int. test, LpBk. test., and data register failed
Int. test, LpBk. test., and cntrl. register failed
Int. test, LpBk. test., and data/cntrl. reg. failed
Unexpected interrupt received
Printer pattern test failed
Printer failed or not connected
--
Interrupt test and data reg. failed
A.9
VIDEO (GRAPHICS) ERROR MESSAGES (5xx-xx)
Table A-8.
Video (Graphics) Error Messages
Message
501-01
502-01
503-01
504-01
505-01
506-01
507-01
Probable Cause
Message
508-01
509-01
510-01
511-01
512-01
514-01
516-01
Probable Cause
Video controller test failed
Video memory test failed
Video attribute test failed
Video character set test failed
80x25 mode, 9x14 cell test failed
80x25 mode, 8x8 cell test failed
40x25 mode test failed
320x200 mode, color set 0 test failed
320x200 mode, color set 1 test failed
640x200 mode test failed
Screen memory page test failed
Gray scale test failed
White screen test failed
Noise pattern test failed
Compaq Personal Computers A-5
Changed – April 1998
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Appendix A Error Messages and Codes
A.10
DISKETTE DRIVE ERROR MESSAGES (6xx-xx)
Table A-9.
Diskette Drive Error Messages
Message
6xx-01
6xx-02
6xx-03
6xx-04
6xx-05
6xx-06
6xx-07
6xx-08
6xx-09
6xx-10
Probable Cause
Message
6xx-20
6xx-21
6xx-22
6xx-23
6xx-24
6xx-25
6xx-26
6xx-27
6xx-28
--
Probable Cause
Failed to get drive type
Exceeded maximum soft error limit
Exceeded maximum hard error limit
Previously exceeded max soft limit
Previously exceeded max hard limit
Failed to reset controller
Fatal error while reading
Fatal error while writing
Failed compare of R/W buffers
Failed to format a tract
Failed sector wrap test
Failed to get change line status
Failed to clear change line status
Failed to set drive type in ID media
Failed to read diskette media
Failed to verify diskette media
Failed to read media in speed test
Failed speed limits
Failed write-protect test
--
600-xx = Diskette drive ID test
601-xx = Diskette drive format
602-xx = Diskette read test
603-xx = Diskette drive R/W compare test
604-xx = Diskette drive random seek test
605-xx = Diskette drive ID media
606-xx = Diskette drive speed test
607-xx = Diskette drive wrap test
608-xx = Diskette drive write-protect test
609-xx = Diskette drive reset controller test
610-xx = Diskette drive change line test
694-00 = Pin 34 not cut on 360-KB drive
697-00 = Diskette type error
698-00 = Drive speed not within limits
699-00 = Drive/media ID error (run Setup)
A.11
SERIAL INTERFACE ERROR MESSAGES (11xx-xx)
Table A-10.
Serial Interface Error Messages
Message
1101-01
1101-02
1101-03
1101-04
1101-05
1101-06
1101-07
1101-08
1101-09
1101-10
1101-11
Probable Cause
Message
1101-12
1101-13
1101-14
1109-01
1109-02
1109-03
1109-04
Probable Cause
Port test, UART DLAB bit failure
Port test, line input or UART fault
Port test, address line fault
Port test, data line fault
Port test, UART cntrl. signal failure
Port test, UART THRE bit failure
Port test, UART Dta RDY bit failure
Port test, DRVR/RCVR cntrl. signal failure
Port test, UART cntrl. signal interrupt failure
Port test, DRVR/RCVR data failure
Clock register initialization failure
Clock register rollover failure
Clock reset failure
Input line or clock failure
Address line fault
Data line fault
Port test, UART TX/RX buffer failure 1109-05
Port test, interrupt circuit failure
Port test, COM1 set to invalid INT
Port test, COM2 set to invalid INT
1109-06
1150-xx
--
Comm port setup error (run Setup)
--
A-6 Compaq Personal Computers
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Technical Reference Guide
A.12
MODEM COMMUNICATIONS ERROR MESSAGES (12xx-xx)
Table A-11.
Serial Interface Error Messages
Message
1201-XX
1201-01
1201-02
1201-03
1201-04
1201-05
1201-06
1201-07
1201-08
1201-09
1201-10
1201-11
1201-12
1201-13
1201-14
1201-15
1201-16
1201-17
1202-XX
1202-01
1202-02
1202-03
1202-11
1202-12
1202-13
1202-21
1202-22
1202-23
1203-XX
1203-01
1203-02
1203-03
1204-XX
1204-01
1204-02
Probable Cause
Modem internal loopback test
UART DLAB bit failure
Line input or UART failure
Address line failure
Data line fault
UART control signal failure
UART THRE bit failure
UART DATA READY bit failure
UART TX/RX buffer failure
Interrupt circuit failure
COM1 set to invalid inturrupt
COM2 set to invalid
DRVR/RCVR control signal failure
UART control signal interrupt failure
DRVR/RCVR data failure
Modem detection failure
Message
1204-03
1204-04
1204-05
1204-06
1204-07
1204-08
1204-09
1204-10
1204-11
1205-XX
1205-01
1205-02
1205-03
1205-04
1205-05
1205-06
1205-07
1205-08
1205-09
1205-10
1205-11
1206-XX
1206-17
1210-XX
1210-01
1210-02
1210-03
1210-04
1210-05
1210-06
1210-07
1210-08
1210-09
1210-10
1210-11
Probable Cause
Data block retry limit reached [4]
RX exceeded carrier lost limit
TX exceeded carrier lost limit
Time-out waiting for dial tone
Dial number string too long
Modem time-out waiting for remote response
Modem exceeded maximum redial limit
Line quality prevented remote response
Modem time-out waiting for remote connection
Modem auto answer test
Time-out waiting for SYNC [5]
Time-out waiting for response [5]
Data block retry limit reached [5]
RX exceeded carrier lost limit
TX exceeded carrier lost limit
Time-out waiting for dial tone
Modem ROM, checksum failure
Tone detect failure
Modem internal test
Dial number string too long
Modem time-out waiting for remote response
Modem exceeded maximum redial limit
Line quality prevented remote response
Modem time-out waiting for remote connection
Dial multi-frequency tone test
Tone detection failure
Modem direct connect test
Time-out waiting for SYNC [6]
Time-out waiting for response [6]
Data block retry limit reached [6]
RX exceeded carrier lost limit
TX exceeded carrier lost limit
Time-out waiting for dial tone
Time-out waiting for SYNC [1]
Time-out waiting for response [1]
Data block retry limit reached [1]
Time-out waiting for SYNC [2]
Time-out waiting for response [2]
Data block retry limit reached [2]
Time-out waiting for SYNC [3]
Time-out waiting for response [3]
Data block retry limit reached [3]
Modem external termination test
Modem external TIP/RING failure
Modem external data TIP/RING fail
Modem line termination failure
Modem auto originate test
Time-out waiting for SYNC [4]
Time-out waiting for response [4]
Dial number string too long
Modem time-out waiting for remote response
Modem exceeded maximum redial limit
Line quality prevented remote response
Modem time-out waiting for remote connection
NOTES:
[1] Local loopback mode
[2] Analog loopback originate mode
[3] Analog loopback answer mode
[4] Modem auto originate test
[5] Modem auto answer test
[6] Modem direct connect test
Compaq Personal Computers A-7
Changed – April 1998
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Appendix A Error Messages and Codes
A.13
HARD DRIVE ERROR MESSAGES (17xx-xx)
Table A-12.
Hard Drive Error Messages
Message
17xx-01
17xx-02
17xx-03
17xx-04
17xx-05
17xx-06
17xx-07
17xx-08
17xx-09
17xx-10
17xx-19
17xx-40
17xx-41
17xx-42
17xx-43
17xx-44
17xx-45
17xx-46
17xx-47
17xx-48
17xx-49
17xx-50
Probable Cause
Exceeded max. soft error limit
Exceeded max. Hard error limit
Previously exceeded max. soft error limit 17xx-53
Previously exceeded max.hard error limit 17xx-54
Failed to reset controller
Fatal error while reading
Fatal error while writing
Failed compare of R/W buffers
Failed to format a track
Failed diskette sector wrap during read
Cntlr. failed to deallocate bad sectors
Cylinder 0 error
Message
17xx-51
17xx-52
Probable Cause
Failed I/O read test
Failed file I/O compare test
Failed drive/head register test
Failed digital input register test
Cylinder 1 error
Failed controller RAM diagnostics
Failed controller-to-drive diagnostics
Failed to write sector buffer
Failed to read sector buffer
Failed uncorrectable ECC error
Failed correctable ECC error
Failed soft error rate
Exceeded max. bad sectors per track
Failed to initialize drive parameter
Failed to write long
Failed to read long
Failed to read drive size
Failed translate mode
17xx-55
17xx-56
17xx-57
17xx-58
17xx-59
17xx-60
17xx-62
17xx-63
17xx-65
17xx-66
17xx-67
17xx-68
Drive not ready
Failed to recalibrate drive
Failed to format a bad track
Failed controller diagnostics
Failed to get drive parameters from ROM 17xx-69
Invalid drive parameters from ROM
Failed to park heads
Failed to move hard drive table to RAM
Failed to read media in file write test
Failed I/O write test
17xx-70
17xx-71
17xx-72
17xx-73
--
Failed non-translate mode
Bad track limit exceeded
Previously exceeded bad track limit
--
1700-xx = Hard drive ID test
1710-xx = Hard drive park head test
1701-xx = Hard drive format test
1702-xx = Hard drive read test
1714-xx = Hard drive file write test
1715-xx = Hard drive head select test
1716-xx = Hard drive conditional format test
1717-xx = Hard drive ECC test
1719-xx = Hard drive power mode test
1721-xx = SCSI hard drive imminent failure
1724-xx = Net work preparation test
1736-xx = Drive monitoring test
1703-xx = Hard drive read/write compare test
1704-xx = Hard drive random seek test
1705-xx = Hard drive controller test
1706-xx = Hard drive ready test
1707-xx = Hard drive recalibrate test
1708-xx = Hard drive format bad track test
1709-xx = Hard drive reset controller test
1799-xx = Invalid hard drive type
A-8 Compaq Personal Computers
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Technical Reference Guide
A.14
HARD DRIVE ERROR MESSAGES (19xx-xx)
Table A-13.
Hard Drive Error Messages
Message
19xx-01
19xx-02
19xx-03
19xx-04
19xx-05
19xx-06
19xx-07
19xx-08
19xx-09
19xx-10
19xx-11
19xx-12
19xx-13
19xx-14
19xx-15
19xx-16
19xx-17
19xx-18
19xx-19
19xx-20
Probable Cause
Drive not installed
Cartridge not installed
Tape motion error
Drive busy erro
Message
19xx-21
19xx-22
19xx-23
19xx-24
19xx-25
19xx-26
19xx-27
19xx-28
19xx-30
19xx-31
19xx-32
19xx-33
19xx-34
19xx-35
19xx-36
19xx-37
19xx-38
19xx-39
19xx-40
19xx-91
Probable Cause
Got servo pulses second time but not first
Never got to EOT after servo check
Change line unset
Write-protect error
Unable to erase cartridge
Cannot identify drive
Drive not compatible with controller
Format gap error
Exception bit not set
Unexpected drive status
Device fault
Illegal command
Track seek error
Tape write-protect error
Tape already Servo Written
Unable to Servo Write
Unable to format
Format mode error
Drive recalibration error
Tape not Servo Written
Tape not formatted
Drive time-out error
Sensor error flag
Block locate (block ID) error
Soft error limit exceeded
Hard error limit exceeded
Write (probably ID ) error
NEC fatal error
No data detected
Power-on reset occurred
Failed to set FLEX format mode
Failed to reset FLEX format mode
Data mismatch on directory track
Data mismatch on track 0
Failed self-test
Power lost during test
1900-xx = Tape ID test failed
1904-xx = Tape BOT/EOT test failed
1901-xx = Tape servo write failed
1902-xx = Tape format failed
1903-xx = Tape drive sensor test failed
1905-xx = Tape read test failed
1906-xx = Tape R/W compare test failed
1907-xx = Tape write-protect failed
A.15
VIDEO (GRAPHICS) ERROR MESSAGES (24xx-xx)
Table A-14.
Hard Drive Error Messages
Message
2402-01
2403-01
2404-01
2405-01
2406-01
2407-01
2408-01
2409-01
2410-01
2411-01
2412-01
2414-01
2416-01
2417-01
2417-02
2417-03
2417-04
2418-01
Probable Cause
Video memory test failed
Video attribute test failed
Message Probable Cause
2418-02
2419-01
2420-01
2421-01
2422-01
2423-01
2424-01
2425-01
2431-01
2432-01
2448-01
2451-01
2456-01
2458-xx
2468-xx
2477-xx
2478-xx
2480-xx
EGA shadow RAM test failed
EGA ROM checksum test failed
EGA attribute test failed
Video character set test failed
80x25 mode, 9x14 cell test failed
80x25 mode, 8x8 cell test failed
40x25 mode test failed
320x200 mode color set 0 test failed
320x200 mode color set 1 test failed
640x200 mode test failed
Screen memory page test failed
Gray scale test failed
White screen test failed
640x200 mode test failed
640x350 16-color set test failed
640x350 64-color set test failed
EGA Mono. text mode test failed
EGA Mono. graphics mode test failed
640x480 graphics mode test failed
320x200 256-color set test failed
Advanced VGA controller test failed
132-column AVGA test failed
AVGA 256-color test failed
AVGA BitBLT test failed
Noise pattern test failed
Lightpen text test failed, no response
Lightpen text test failed, invalid response
Lightpen graphics test failed, no resp.
Lightpen graphics test failed, invalid resp.
EGA memory test failed
AVGA DAC test failed
AVGA data path test failed
AVGA BitBLT test failed
AVGA linedraw test failed
Compaq Personal Computers A-9
Changed – April 1998
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Appendix A Error Messages and Codes
A.16
AUDIO ERROR MESSAGES (3206-xx)
Table A-15.
Audio Error Message
Message
Probable Cause
3206-xx
Audio subsystem internal error
A.17
NETWORK INTERFACE ERROR MESSAGES (60xx-xx)
Table A-16.
Network Interface Error Messages
Message
6000-xx
6014-xx
6016-xx
6028-xx
6029-xx
Probable Cause
Message
6054-xx
6056-xx
6068-xx
6069-xx
6089-xx
Probable Cause
Pointing device interface error
Ethernet configuration test failed
Ethernet reset test failed
Ethernet int. loopback test failed
Ethernet ext. loopback test failed
Token ring configuration test failed
Token ring reset test failed
Token ring int. loopback test failed
Token ring ext. loopback test failed
Token ring open
A-10 Compaq Personal Computers
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A.18
SCSI INTERFACE ERROR MESSAGES (65xx-xx, 66xx-xx, 67xx-xx)
Table A-17.
SCSI Interface Error Messages
Message
6nyy-02
6nyy-03
6nyy-05
6nyy-06
6nyy-07
6nyy-08
6nyy-09
6nyy-10
6nyy-11
6nyy-12
6nyy-13
6nyy-14
6nyy-15
6nyy-16
6nyy-17
6nyy-18
6nyy-21
6nyy-24
6nyy-25
6nyy-30
6nyy-31
6nyy-32
Probable Cause
Drive not installed
Media not installed
Seek failure
Drive timed out
Drive busy
Drive already reserved
Reserved
Reserved
Media soft error
Drive not ready
Media error
Drive hardware error
Illegal drive command
Media was changed
Tape write-protected
No data detected
Drive command aborted
Media hard error
Reserved
Message
6nyy-33
6nyy-34
6nyy-35
6nyy-36
6nyy-39
6nyy-40
6nyy-41
6nyy-42
6nyy-43
6nyy-44
6nyy-50
6nyy-51
6nyy-52
6nyy-53
6nyy-54
6nyy-60
6nyy-61
6nyy-65
6nyy-90
6nyy-91
6nyy-92
6nyy-99
Probable Cause
Illegal controller command
Invalid SCSI bus phase
Invalid SCSI bus phase
Invalid SCSI bus phase
Error status from drive
Drive timed out
SSI bus stayed busy
ACK/REQ lines bad
ACK did not deassert
Parity error
Data pins bad
Data line 7 bad
MSG, C/D, or I/O lines bad
BSY never went busy
BSY stayed busy
Controller CONFIG-1 register fault
Controller CONFIG-2 register fault
Media not unloaded
Fan failure
Controller timed out
Unrecoverable error
Controller/drive not connected
Over temperature condition
Side panel not installed
Autoloader reported tape not loaded properly
n = 5, Hard drive
= 6, CD-ROM drive
= 7, Tape drive.
yy = 00, ID
= 03, Power check
= 05, Read
= 06, SA/Media
= 08, Controller;
= 23, Random read
= 28, Media load/unload
A.19
POINTING DEVICE INTERFACE ERROR MESSAGES (8601-xx)
Table A-18.
Pointing Device Interface Error Messages
Message
8601-01
8601-02
8601-03
8601-04
8601-05
Probable Cause
Mouse ID fails
Left mouse button is inoperative
Left mouse button is stuck closed
Right mouse button is inoperative
Right mouse button is stuck closed
Message
8601-06
8601-07
8601-08
8601-09
8601-10
Probable Cause
Left block not selected
Right block not selected
Timeout occurred
Mouse loopback test failed
Pointing device is inoperative
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Appendix A Error Messages and Codes
A.20
CEMM PRIVILEDGED OPS ERROR MESSAGES
Table A-19.
CEMM Privileged Ops Error Messages
Message
Probable Cause
LGDT instruction
LIDT instruction
LMSW instruction
LL2 instruction
Message
Probable Cause
LL3 instruction
MOV CRx instruction
MOV DRx instruction
MOV TRx instruction
00
01
02
03
04
05
06
07
A.21
CEMM EXCEPTION ERROR MESSAGES
Table A-20.
CEMM Exception Error Messages
Message
00
01
02
03
04
05
06
07
Probable Cause
Divide
Debug
NMI or parity
INT 0 (arithmetic overflow)
INT 3
Array bounds check
Invalid opcode
Coprocessor device not available
Double fault
Message
Probable Cause
Invalid TSS
Segment not present
Stack full
General protection fault
Page fault
Coprocessor
Attempt to write to protected area
Reserved
Invalid software interrupt
--
10
11
12
13
14
16
32
33
34
--
08
09
Coprocessor segment overrun
A-12 Compaq Personal Computers
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Technical Reference Guide
Appendix B
ASCII CHARACTER SET
B.1
INTRODUCTION
This appendix lists, in Table B-1, the 256-character ASCII code set including the decimal and
hexadecimal values. All ASCII symbols may be called while in DOS or using standard text-
mode editors by using the combination keystroke of holding the Alt key and using the Numeric
Keypad to enter the decimal value of the symbol. The extended ASCII characters (decimals 128-
255) can only be called using the Alt + Numeric Keypad keys.
NOTE:
Regarding keystrokes, refer to notes at the end of the table. Applications may interpret
multiple keystroke accesses differently or ignore them completely.
Table B-1.
ASCII Character Set
Dec
0
1
2
3
4
5
6
7
Hex
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
Symbol Dec
Hex
Symbol Dec
Hex
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
Symbol Dec
Hex
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
Symbol
Blank
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
Space
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
@
A
B
C
D
E
F
G
H
I
96
97
98
99
‘
a
b
c
d
e
f
g
h
I
j
k
l
m
n
o
p
q
r
!
“
♥
♦
♣
♠
●
#
$
%
&
‘
(
)
*
+
`
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
❍
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
J
K
L
-
.
/
M
N
O
P
Q
R
S
T
U
V
W
X
Y
Z
[
0
1
2
3
4
5
6
7
8
9
:
↕
!!
¶
§
s
t
u
v
w
x
y
z
{
↕
↑
↓
→
←
;
<
=
>
?
\
]
^
_
|
}
↔
▲
▼
~
[1]
Continued
Compaq Personal Computers
B-1
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Appendix B ASCII Character Set
Table B-1. ASCII Code Set (Continued)
Dec
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
NOTES:
Hex
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
Symbol Dec
Hex
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
Symbol Dec
Hex
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
Symbol
Dec
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
Hex
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
Symbol
Ç
ü
é
â
ä
à
å
ç
ê
ë
è
ï
î
ì
Ä
Å
É
æ
Æ
ô
ö
ò
û
ù
ÿ
Ö
Ü
¢
£
¥
•
ƒ
á
í
ó
ú
ñ
Ñ
ª
º
¿
•
¬
½
¼
¡
«
»
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
ß
•
•
•
•
µ
•
•
•
•
•
•
•
•
•
•
±
•
•
•
•
÷
•
°
·
·
•
•
²
•
Blank
[1] Symbol not displayed.
Keystroke Guide:
Dec #
0
Keystroke(s)
Ctrl 2
1-26
27
Ctrl A thru Z respectively
Ctrl [
28
Ctrl
29
Ctrl ]
30
31
Ctrl 6
Ctrl -
32
Space Bar
33-43
44-47
48-57
58
Shift and key w/corresponding symbol
Key w/corresponding symbol
Key w/corresponding symbol, numerical keypad w/Num Lock active
Shift and key w/corresponding symbol
Key w/corresponding symbol
59
60
61
Shift and key w/corresponding symbol
Key w/corresponding symbol
62-64
65-90
Shift and key w/corresponding symbol
Shift and key w/corresponding symbol or key w/corresponding symbol and
Caps Lock active
91-93
94, 95
96
Key w/corresponding symbol
Shift and key w/corresponding symbol
Key w/corresponding symbol
97-126 Key w/corresponding symbol or Shift and key w/corresponding symbol
and Caps Lock active
127
Ctrl -
128-255 Alt and decimal digit(s) of desired character
B-2 Compaq Personal Computers
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Appendix C
KEYBOARD
C.1
INTRODUCTION
This appendix describes the Compaq keyboard that is included as standard with the system unit.
The keyboard complies with the industry-standard classification of an “enhanced keyboard” and
includes a separate cursor control key cluster, twelve “function” keys, and enhanced
programmability for additional functions.
This appendix covers the following keyboard types:
♦
♦
Standard enhanced keyboard.
Space-Saver Windows-version keyboard featuring three additional keys for specific support
of the Windows operating system.
Only one type of keyboard is supplied with each system. Other types may be available as an
option.
NOTE:
This appendix discusses only the keyboard unit. The keyboard interface is a
function of the system unit and is discussed in Chapter 5, Input/Output Interfaces.
Topics covered in this appendix include the following:
♦
Keystroke processing (C.2)
page C-2
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Appendix C Keyboard
C.2
KEYSTROKE PROCESSING
A functional block diagram of the keystroke processing elements is shown in Figure C-1. Power
(+5 VDC) is obtained from the system through the PS/2-type interface. The keyboard uses a
Z86C14 (or equivalent) microprocessor. The Z86C14 scans the key matrix drivers every 10 ms
for pressed keys while at the same time monitoring communications with the keyboard interface
of the system unit. When a key is pressed, a Make code is generated. A Break code is generated
when the key is released. The Make and Break codes are collectively referred to as scan codes.
All keys generate Make and Break codes with the exception of the Pause key, which generates a
Make code only.
Scroll
Lock
Num
Lock
Caps
Lock
Matrix
Drivers
Data/
CLK
Keyboard
Interface
(System Unit)
Keyswitch
Matrix
Keyboard
Processor
Matrix
Receivers
Figure C–1. Keystroke Processing Elements, Block Diagram
When the system is turned on, the keyboard processor generates a Power-On Reset (POR) signal
after a period of 150 ms to 2 seconds. The keyboard undergoes a Basic Assurance Test (BAT)
that checks for shorted keys and basic operation of the keyboard processor. The BAT takes from
300 to 500 ms to complete.
If the keyboard fails the BAT, an error code is sent to the CPU and the keyboard is disabled until
an input command is received. After successful completion of the POR and BAT, a completion
code (AAh) is sent to the CPU and the scanning process begins.
The keyboard processor includes a 16-byte FIFO buffer for holding scan codes until the system is
ready to receive them. Response and typematic codes are not buffered. If the buffer is full (16
bytes held) a 17th byte of a successive scan code results in an overrun condition and the overrun
code replaces the scan code byte and any additional scan code data (and the respective key
strokes) are lost. Multi-byte sequences must fit entirely into the buffer before the respective
keystroke can be registered.
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C.2.1 TRANSMISSIONS TO THE SYSTEM
The keyboard processor sends two main types of data to the system; commands (or responses to
system commands) and keystroke scan codes. Before the keyboard sends data to the system
(specifically, to the 8042-type logic within the system), the keyboard verifies the clock and data
lines to the system. If the clock signal is low (0), the keyboard recognizes the inhibited state and
loads the data into a buffer. Once the inhibited state is removed, the data is sent to the system.
Keyboard-to-system transfers consist of 11 bits as shown in Figure C-2.
D1
0
D2
0
D3
1
D4
1
D5
1
D6
1
Parity
0
Start
Bit
D0
(LSb)
D7
(MSb)
Stop
Bit
0
0
1
0
Data
Clock
Th
Minimum Maximum
Tcy
Tcl Tch
Parameter
Ts
Tcy (Cycle Time)
Tcl (Clock Low)
Tch (clock High)
Th (Data Hold)
Ts (Data Setup)
60 us
30 us
30 us
45 us
8 us
80 us
35 us
45 us
62 us
14 us
Figure C–2. Keyboard-To-System Transmission of Code 58h, Timing Diagram
The system can halt keyboard transmission by setting the clock signal low. The keyboard checks
the clock line every 60 us to verify the signal state. If a low is detected, the keyboard will finish
the current transmission if the rising edge of the clock pulse for the parity bit has not occurred.
The enhanced keyboard has three operating modes:
♦
♦
♦
Mode 1 - PC-XT compatible
Mode 2 - PC-AT compatible (default)
Mode 3 - Select mode (keys are programmable as to make-only, break-only, typematic)
Modes can be selected by the user or set by the system. Mode 2 is the default mode. Each mode
produces a different set of scan codes. When a key is pressed, the keyboard processor sends that
key’s make code to the 8042 logic of the system unit. The When the key is released, a release
code is transmitted as well (except for the Pause key, which produces only a make code). The
8042-type logic of the system unit responds to scan code reception by asserting IRQ1, which is
processed by the interrupt logic and serviced by the CPU with an interrupt service routine. The
service routine takes the appropriate action based on which key was pressed.
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Appendix C Keyboard
C.2.2 KEYBOARD LAYOUTS
C.2.2.1 Standard Enhanced Keyboards
6
1
2
3
4
5
7
8
9
10 11 12 13
14 15 16
36
38
58
18 19 20 21 22 23 24 25 26
40 41 42 43 44 45 46 47
60 61 62 63 64 65 66 67
28
31
30
71
86
32 33 34
52 53 54
35
37
17
27
29
50
55 56 57
72 73 74
88 89 90
39
59
75
92
48 49
68 69
51
70
76 77 78 79 80 81 82 83
93 94
87
84 85
95
91
96
100
101
97 98 99
Figure C–3. U.S. English (101-Key) Keyboard Key Positions
6
1
2
3
4
5
7
8
9
10 11 12 13
14 15 16
36
38
58
18 19 20 21 22 23 24 25 26
40 41 42 43 44 45 46 47
60 61 62 63 64 65 66 67
28
31
32 33 34
52 53 54
35
37
17
27
29
50
55 56 57
72 73 74
88 89 90
39
59
75
92
48 49
68 69
51
71
70
103
86
76 77 78 79 80 81 82 83
87
84 85
95
104
91
93
94
96
100
101
97 98 99
Figure C–4. National (102-Key) Keyboard Key Positions
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C.2.2.2 Windows Enhanced Keyboards
6
1
2
3
4
5
7
8
9
10
28
12
15
11
29
13
14
16
36
56
73
89
38
58
18
20
22
24
26
47
67
83
31
30
71
86
33
53
35
55
72
88
37
57
17
19
21
23
25
27
32
52
34
54
41
61
77
93
43
63
79
45
50
39
59
75
92
40
60
76
42
62
78
44
64
80
94
46
48 49
68 69
51
65
81
70
66
82
74
87
98
84 85
95
90
91
96
100
97
99
110
111 112
101
Figure C–5. U.S. English Windows (101W-Key) Keyboard Key Positions
6
1
2
3
4
5
7
8
9
10 11 12 13
14 15 16
36
38
58
18 19 20 21 22 23 24 25 26
40 41 42 43 44 45 46 47
60 61 62 63 64 65 66 67
28
31
32 33 34
52 53 54
35
37
17
27
29
50
55 56 57
72 73 74
88 89 90
39
59
48 49
68 69
51
71
70
103
86
75
92
76 77 78 79 80 81 82 83
87
84 85
95
104
110
91
100
101
96
97 98 99
93
94
111 112
Figure C–6. National Windows (102W-Key) Keyboard Key Positions
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C-5
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Appendix C Keyboard
C.2.3 KEYS
All keys generate a make code (when pressed) and a break code (when released) with the
exception of the Pause key (pos. 16), which produces a make code only. All keys, again, with
the exception of the Pause key, are also typematic, although the typematic action of the Shift,
Ctrl, Alt, Num Lock, Scroll Lock, Caps Lock, and Ins keys is suppressed by the BIOS.
Typematic keys, when held down, send the make code repetitively at a predetermined rate until
the key is released. If two keys are held down, the last key pressed will be typematic.
C.2.3.1 Special Single-Keystroke Functions
The following keys provide the intended function in most applications and environments.
Caps Lock - The Caps Lock key (pos. 59), when pressed and released, invokes a BIOS
routine that turns on the caps lock LED and shifts into upper case key positions 40-49, 60-68,
and 76-82. When pressed and released again, these keys revert to the lower case state and the
LED is turned off. Use of the Shift key will reverse which state these keys are in based on the
Caps Lock key.
Num Lock - The Num Lock key (pos. 32), when pressed and released, invokes a BIOS routine
that turns on the num lock LED and shifts into upper case key positions 55-57, 72-74, 88-90,
100, and 101. When pressed and released again, these keys revert to the lower case state and the
LED is turned off.
The following keys provide special functions that require specific support by the application.
Print Scrn - The Print Scrn (pos. 14) key can, when pressed, generate an interrupt that
initiates a print routine. This function may be inhibited by the application.
Scroll Lock - The Scroll Lock key (pos. 15) when pressed and released, , invokes a BIOS
routine that turns on the scroll lock LED and inhibits movement of the cursor. When pressed and
released again, the LED is turned off and the function is removed. This keystroke is always
serviced by the BIOS (as indicated by the LED) but may be inhibited or ignored by the
application.
Pause - The Pause (pos. 16) key, when pressed, can be used to cause the keyboard interrupt to
loop, i.e., wait for another key to be pressed. This can be used to momentarily suspend an
operation. The key that is pressed to resume operation is discarded. This function may be ignored
by the application.
The Esc, Fn (function), Insert, Home, Page Up/Down, Delete, and End keys operate at the
discretion of the application software.
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C.2.3.2 Multi-Keystroke Functions
Shift - The Shift key (pos. 75/86), when held down, produces a shift state (upper case) for keys
in positions 17-29, 30, 39-51, 60-70, and 76-85 as long as the Caps Lock key (pos. 59) is
toggled off. If the Caps Lock key is toggled on, then a held Shift key produces the lower
(normal) case for the identified pressed keys. The Shift key also reverses the Num Lock state of
key positions 55-57, 72, 74, 88-90, 100, and 101.
Ctrl - The Ctrl keys (pos. 92/96) can be used in conjunction with keys in positions 1-13, 16, 17-
34, 39-54, 60-71, and 76-84. The application determines the actual function. Both Ctrl key
positions provide identical functionality. The pressed combination of Ctrl and Break (pos. 16)
results in the generation of BIOS function INT 1Bh. This software interrupt provides a method of
exiting an application and generally halts execution of the current program.
Alt - The Alt keys (pos. 93/95) can be used in conjunction with the same keys available for use
with the Ctrl keys with the exception that position 14 (SysRq) is available instead of position
16 (Break). The Alt key can also be used in conjunction with the numeric keypad keys (pos. 55-
57, 72-74, and 88-90) to enter the decimal value of an ASCII character code from 1-255. The
application determines the actual function of the keystrokes. Both Alt key positions provide
identical functionality.
The combination keystroke of Alt and SysRq results in software interrupt 15h, AX=8500h
being executed. It is up to the application to use or not use this BIOS function.
The Ctrl and Alt keys can be used together in conjunction with keys in positions 1-13, 17-34, 39-
54, 60-71, and 76-84. The Ctrl and Alt key positions used and the sequence in which they are
pressed make no difference as long as they are held down at the time the third key is pressed. The
Ctrl, Alt, and Delete keystroke combination (required twice if in the Windows environment)
initiates a system reset (warm boot) that is handled by the BIOS.
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Appendix C Keyboard
C.2.3.3 Windows Keystrokes
Windows-enhanced keyboards include three additional key positions. Key positions 110 and 111
(marked with the Windows logo
) have the same functionality and are used by themselves
or in combination with other keys to perform specific “hot-key” type functions for the Windows
operating system. The defined functions of the Windows logo keys are listed as follows:
Keystroke
Function
Window Logo
Open Start menu
Window Logo + F1
Window Logo + TAB
Window Logo + E
Window Logo + F
Window Logo + CTRL + F
Window Logo + M
Shift + Window Logo + M
Window Logo + R
Window Logo + PAUSE
Window Logo + 1-0
Display pop-up menu for the selected object
Activate next task bar button
Explore my computer
Find document
Find computer
Minimize all
Undo minimize all
Display Run dialog box
Perform system function
Reserved for OEM use (see following text)
The combination keystroke of the Window Logo + 1-0 keys are reserved for OEM use for
auxiliary functions (speaker volume, monitor brightness, password, etc.).
Key position 112 (marked with an application window icon
other keys for invoking Windows application functions.
) is used in combination with
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C.2.4 KEYBOARD COMMANDS
Table C-1 lists the commands that the keyboard can send to the system (specifically, to the 8042-
type logic).
Table C-1.
Keyboard-to-System Commands
Command
Key Detection Error/Over/run
Value
00h [1]
FFh [2]
AAh
FCh
EEh
Description
Indicates to the system that a switch closure couldn’t be
identified.
Indicates to the system that the BAT has been successful.
Indicates failure of the BAT by the keyboard.
Indicates that the Echo command was received by the
keyboard.
BAT Completion
BAT Failure
Echo
Acknowledge (ACK)
FAh
Issued by the keyboard as a response to valid system
inputs (except the Echo and Resend commands).
Issued by the keyboard following an invalid input.
Upon receipt of the Read ID command from the system, the
keyboard issues the ACK command followed by the two IDS
bytes.
Resend
Keyboard ID
FEh
83ABh
Note:
[1] Modes 2 and 3.
[2] Mode 1 only.
C.2.5 SCAN CODES
The scan codes generated by the keyboard processor are determined by the mode the keyboard is
operating in.
♦
♦
Mode 1:
In Mode 1 operation, the keyboard generates scan codes compatible with 8088-
/8086-based systems. To enter Mode 1, the scan code translation function of the keyboard
controller must be disabled. Since translation is not performed, the scan codes generated in
Mode 1 are identical to the codes required by BIOS. Mode 1 is initiated by sending command
F0h with the 01h option byte. Applications can obtain system codes and status information
by using BIOS function INT 16h with AH=00h, 01h, and 02h.
Mode 2:
Mode 2 is the default mode for keyboard operation. In this mode, the 8042 logic
translates the make codes from the keyboard processor into the codes required by the BIOS.
This mode was made necessary with the development of the Enhanced III keyboard, which
includes additional functions over earlier standard keyboards. Applications should use BIOS
function INT 16h, with AH=10h, 11h, and 12h for obtaining codes and status data. In Mode
2, the keyboard generates the Break code, a two-byte sequence that consists of a Make code
immediately preceded by F0h (i.e., Break code for 0Eh is “F0h 0Eh”).
♦
Mode 3:
Mode 3 generates a different scan code set from Modes 1 and 2. Code
translation must be disabled since translation for this mode cannot be done.
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Appendix C Keyboard
Table C-2.
Keyboard Scan Codes
Make / Break Codes (Hex)
Key
Pos.
1
Legend
Esc
F1
Mode 1
01/81
3B/BB
Mode 2
76/F0 76
05/F0 05
Mode 3
08/na
07/na
0F/na
17/na
1F/na
27/na
2F/na
37/na
3F/na
47/na
4F/na
56/na
5E/na
57/na
2
3
4
5
6
7
8
9
10
11
12
13
14
F2
F3
F4
F5
F6
F7
F8
F9
F10
F11
F12
Print Scrn
3C/BC
3D/BD
3E/BE
3F/BF
40/C0
41/C1
42/C2
43/C3
06/F0 06
04/F0 04
0C/F0 0C
03/F0 03
0B/F0 0B
83/F0 83
0A/F0 0A
01/FO 01
44/C4
57/D7
58/D8
09/F0 09
78/F0 78
07/F0 07
E0 2A E0 37/E0 B7 E0 AA
E0 2A E0 7C/E0 F0 7C E0 F0 12
E0 7C/E0 F0 7C [1] [2]
84/F0 84 [3]
E0 37/E0 B7 [1] [2]
54/84 [3]
15
16
Scroll Lock
Pause
46/C6
E1 1D 45 E1 9D C5/na
E0 46 E0 C6/na [3]
7E/F0 7E
5F/na
62/na
E1 14 77 E1 F0 14 F0 77/na
E0 7E E0 F0 7E/na [3]
0E/F0 E0
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
`
1
2
3
4
5
6
7
8
9
0
-
=
\
29/A9
02/82
03/83
04/84
05/85
06/86
07/87
08/88
09/89
0A/8A
0B/8B
0C/8C
0D/8D
0E/F0 0E
46/F0 46
1E/F0 1E
26/F0 26
25/F0 25
2E/F0 2E
36/F0 36
3D/F0 3D
3E/F0 3E
46/F0 46
45/F0 45
4E/F0 4E
55/F0 55
5C/F0 5C
66/F0 66
67/na
16/F0 16
1E/F0 1E
26/F0 26
25/F0 25
2E/F0 2E
36/F0 36
3D/F0 3D
3E/F0 3E
46/F0 46
45/F0 45
4E/F0 4E
55/F0 55
5D/F0 5D
66/F0 66
2B/AB
0E/8E
Backspace
Insert
E0 52/E0 D2
E0 70/E0 F0 70
E0 F0 12 E0 70/E0 F0 70 E0 12 [5]
E0 12 E0 70/E0 F0 70 E0 F0 12 [6]
E0 6C/E0 F0 6C
E0 F0 12 E0 6C/E0 F0 6C E0 12 [5]
E0 12 E0 6C/E0 F0 6C E0 F0 12 [6]
E0 7D/E0 F0 7D
E0 F0 12 E0 7D/E0 F0 7D E0 12 [5]
E0 12 E0 7D/E0 F0 7D E0 F0 12 [6]
77/F0 77
E0 AA E0 52/E0 D2 E0 2A [4]
E0 2A E0 52/E0 D2 E0 AA [6]
E0 47/E0 D2
E0 AA E0 52/E0 D2 E0 2A [4]
E0 2A E0 47/E0 C7 E0 AA [6]
E0 49/E0 C7
E0 AA E0 49/E0 C9 E0 2A [4]
E0 2A E0 49/E0 C9 E0 AA [6]
45/C5
33
34
Home
6E/na
6F/na
Page Up
35
36
Num Lock
/
76/na
77/na
E0 35/E0 B5
E0 AA E0 35/E0 B5 E0 2A [1]
37/B7
E0 4A/E0 F0 4A
E0 F0 12 E0 4A/E0 F0 4A E0 12 [1]
7C/F0 7C
37
38
39
40
*
-
7E/na
84/na
0D/na
15/na
4A/CA
0F/8F
10/90
7B/F0 7B
0D/F0 0D
15/F0 15
Tab
Q
Continued
([x] Notes listed at end of table.)
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Technical Reference Guide
Table C-2. Keyboard Scan Codes (Continued)
Make / Break Codes (Hex)
Key
Pos
41
42
43
44
45
46
47
48
49
50
51
52
Legend
W
E
R
T
Y
U
I
O
P
[
]
Mode 1
11/91
12/92
13/93
14/94
15/95
16/96
17/97
18/98
19/99
1A/9A
1B/9B
Mode 2
1D/F0 1D
24/F0 24
2D/F0 2D
2C/F0 2C
35/F0 35
3C/F0 3C
43/F0 43
44/F0 44
Mode 3
1D/F0 1D
24/F0 24
2D/F0 2D
2C/F0 2C
35/F0 35
3C/F0 3C
43/F0 43
44/F0 44
4D/F0 4D
54/F0 54
5B/F0 5B
64/F0 64
4D/F0 4D
54/F0 54
5B/F0 5B
Delete
E0 53/E0 D3
E0 71/E0 F0 71
E0 F0 12 E0 71/E0 F0 71 E0 12 [5]
E0 12 E0 71/E0 F0 71 E0 F0 12 [6]
E0 69/E0 F0 69
E0 F0 12 E0 69/E0 F0 69 E0 12 [5]
E0 12 E0 69/E0 F0 69 E0 F0 12 [6]
E0 7A/E0 F0 7A
E0 F0 12 E0 7A/E0 F0 7A E0 12 [5]
E0 12 E0 7A/E0 F0 7A E0 F0 12 [6]
6C/F0 6C [6]
75/F0 75 [6]
E0 AA E0 53/E0 D3 E0 2A [4]
E0 2A E0 53/E0 D3 E0 AA [6]
53
54
End
E0 4F/E0 CF
65/F0 65
6D/F0 6D
E0 AA E0 4F/E0 CF E0 2A [4]
E0 2A E0 4F/E0 CF E0 AA [6]
Page Down
E0 51/E0 D1
E0 AA E0 51/E0 D1 E0 2A [4]
E0 @a E0 51/E0 D1 E0 AA [6]
47/C7 [6]
48/C8 [6]
49/C9 [6]
4E/CE [6]
3A/BA
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
7
8
9
+
6C/na [6]
75/na [6]
7D/na [6]
7C/F0 7C
14/F0 14
1C/F0 1C
1B/F0 1B
23/F0 23
2B/F0 2B
34/F0 34
33/F0 33
3B/F0 3B
42/F0 42
4B/F0 4B
4C/F0 4C
52/F0 52
5A/F0 5A
6B/na [6]
73/na [6]
74/na [6]
12/F0 12
1A/F0 1A
22/F0 22
21/F0 21
2A/F0 2A
32/F0 32
7D/F0 7D [6]
79/F0 79 [6]
58/F0 58
Caps Lock
A
S
D
F
G
H
J
K
L
;
‘
Enter
4
5
6
1E/9E
1F/9F
20/A0
21/A1
22/A2
23/A3
24/A4
25/A5
26/A6
27/A7
28/A8
1C/9C
4B/CB [6]
4C/CC [6]
4D/CD [6]
2A/AA
2C/AC
2D/AD
1C/F0 1C
1B/F0 1B
23/F0 23
2B/F0 2B
34/F0 34
33/F0 33
3B/F0 3B
42/F0 42
4B/F0 4B
4C/F0 4C
52/F0 52
5A/F0 5A
6B/F0 6B [6]
73/F0 73 [6]
74/F0 74 [6]
12/F0 12
1A/F0 1A
Shift (left)
Z
X
C
V
B
22/F0 22
21/F0 21
2A/F0 2A
32/F0 32
2E/AE
2F/AF
30/B0
Continued
([x] Notes listed at end of table.)
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Appendix C Keyboard
Table C-2. Keyboard Scan Codes (Continued)
Make / Break Codes (Hex)
Key
Pos.
81
Legend
N
Mode 1
31/B1
Mode 2
31/F0 31
Mode 3
31/F0 31
3A/F0 3A
41/F0 41
49/F0 49
4A/F0 4A
59/F0 59
63/F0 63
82
83
84
85
86
87
M
,
.
/
32/B2
33/B3
34/B4
35/B5
3A/F0 3A
41/F0 41
49/F0 49
4A/F0 4A
Shift (right)
36/B6
59/F0 59
E0 48/E0 C8
E0 75/E0 F0 75
E0 AA E0 48/E0 C8 E0 2A [4]
E0 2A E0 48/E0 C8 E0 AA [6]
4F/CF [6]
E0 F0 12 E0 75/E0 F0 75 E0 12 [5]
E0 12 E0 75/E0 F0 75 E0 F0 12 [6]
69/F0 69 [6]
88
89
90
91
92
93
94
95
96
97
1
2
3
69/na [6]
72/na [6]
7A/na [6]
79/F0 79[6]
11/F0 11
19/F0 19
29/F0 29
39/na
50/D0 [6]
51/D1 [6]
E0 1C/E0 9C
72/F0 72 [6]
7A/F0 7A [6]
E0 5A/F0 E0 5A
Enter
Ctrl (left)
Alt (left)
(Space)
Alt (right)
Ctrl (right)
1D/9D
38/B8
39/B9
14/F0 14
11/F0 11
29/F0 29
E0 38/E0 B8
E0 1D/E0 9D
E0 4B/E0 CB
E0 11/F0 E0 11
E0 14/F0 E0 14
E0 6B/Eo F0 6B
58/na
61/F0 61
E0 AA E0 4B/E0 CB E0 2A [4]
E0 2A E0 4B/E0 CB E0 AA [6]
E0 50/E0 D0
E0 AA E0 50/E0 D0 E0 2A [4]
E0 2A E0 50/E0 D0 E0 AA [6]
E0 4D/E0 CD
E0 F0 12 E0 6B/E0 F0 6B E0 12[5]
E0 12 E0 6B/E0 F0 6B E0 F0 12[6]
E0 72/E0 F0 72
E0 F0 12 E0 72/E0 F0 72 E0 12[5]
E0 12 E0 72/E0 F0 72 E0 F0 12[6]
E0 74/E0 F0 74
98
99
60/F0 60
6A/F0 6A
E0 AA E0 4D/E0 CD E0 2A [4]
E0 2A E0 4D/E0 CD E0 AA [6]
52/D2 [6]
E0 F0 12 E0 74/E0 F0 74 E0 12[5]
E0 12 E0 74/E0 F0 74 E0 F0 12[6]
70/F0 70 [6]
100
101
102
103
104
110
0
.
na
na
70/na [6]
71/na [6]
7B/F0 7B
53/F0 53
13/F0 13
8B/F0 8B
53/D3 [6]
7E/FE
2B/AB
36/D6
71/F0 71 [6]
6D/F0 6D
5D/F0 5D
61/F0 61
na
(Win95) [7]
E0 5B/E0 DB
E0 1F/E0 F0 1F
E0 AA E0 5B/E0 DB E0 2A [4]
E0 2A E0 5B/E0 DB E0 AA [6]
E0 5C/E0 DC
E0 AA E0 5C/E0 DC E0 2A [4]
E0 2A E0 5C/E0 DC E0 AA [6]
E0 5D/E0 DD
E0 F0 12 E0 1F/E0 F0 1F E0 12 [5]
E0 12 E0 1F/E0 F0 1F E0 F0 12 [6]
E0 2F/E0 F0 27
E0 F0 12 E0 27/E0 F0 27 E0 12 [5]
E0 12 E0 27/E0 F0 27 E0 F0 12 [6]
E0 2F/E0 F0 2F
111
112
(Win95) [7]
8C/F0 8C
8D/F0 8D
(Win Apps)
[7]
E0 AA E0 5D/E0 DD E0 2A [4]
E0 2A E0 5D E0 DD E0 AA [6]
E0 F0 12 E0 2F/E0 F0 2F E0 12 [5]
E0 12 E0 2F/E0 F0 2F E0 F0 12 [6
NOTES:
All codes assume Shift, Ctrl, and Alt keys inactive unless otherwise noted.
NA = Not applicable
[1] Shift (left) key active.
[2] Ctrl key active.
[3] Alt key active.
[4] Left Shift key active. For active right Shift key, substitute AA/2A make/break codes for B6/36 codes.
[5] Left Shift key active. For active right Shift key, substitute F0 12/12 make/break codes
for F0 59/59 codes.
[6] Num Lock key active.
[7] Windows keyboards only
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Technical Reference Guide
Appendix D
COMPAQ 10/100 TX PCI INTEL
WOL UTP CONTROLLER CARD
D.1
INTRODUCTION
This appendix describes the Compaq 10/100 TX PCI Intel WOL UTP Controller card (# 323550-
001). Key features of this card include:
♦
♦
♦
♦
♦
Intel 82558 Fast LAN controller with 32-bit architecture and 3-KB TX/RX buffers.
Dual-mode support with auto-switching between 10BASE-T and 100BASE-TX PHY.
Power down and Wake up support in both APM and ACPI environments (PME- and WOL).
LED indicators for link, activity, and speed status.
LanDesk Service Agent (LSA) ver 2.0 boot code contained in on-board flash memory.
The card installs into a PCI slot and provides Wake-On-LAN (WOL) support.
This appendix covers the following subjects:
♦
♦
♦
♦
Functional description (D.2) page D-2
Configuration/control (D.3) page D-5
RJ-45 connector (D.4)
Specifications (D.5)
page D-5
page D-5
WOL Header
RJ-45
Connector
82558
LAN
Controller
Link LED
Activity LED
100TX LED
Figure D–1.
Compaq 10/100 TX WOL Controller Card Layout (PCA# 323550-001)
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Appendix D Compaq 10/100 TX PCI Intel WOL UTP Controller Card
D.2
FUNCTIONAL DESCRIPTION
The Compaq 10/100 TX PCI Intel WOL UTP Controller card contains the 82558 controller (with
ROMs and support logic), three LED status indicators, a WOL header connector, a RJ-45
network connector, and power switching logic (Figure D-2).
Link
Active 100TX
(Yellow) (Green) (Green)
EEP/
Flash
ROM
RJ-45
Connector
82558
Ethernet
Controller
TX/RX
WOL
Header
PCI Bus
3
1
PCI
Connector
+5VDC
CLK
Pulse
Generator
PME-
WAKEUP
PCI CLK
+5AUX
Power/
Clock
Transition
Logic
25 MHz
Clock
Circuitry
CLK
Figure D–2. Compaq 10/100 TX PCI Intel WOL UTP Controller Card Block Diagram
D.2.1 STATUS INDICATORS
The LEDs provide the following indications:
Link LED (yellow) – Indicates reception of link pulses in 10 MB/s mode, scrambler lock in 100
MB/s mode.
Activity LED (green) – Indicates network activity.
100 TX LED (green) – Indicates connection with 100 MB/s network.
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D.2.2 CARD POWER AND CLOCK
The controller card includes on-board power logic that receives +5 VDC power from the PCI
connector or the WOL header. The PCI CLK signal provides the clock source for the controller
when the system is up and active. When the system is off or in Standby the on-board clock
generator provides the clock signal.
NOTE: Lack of a WOL header connection with the main system will result in the
controller board not receiving power at any time. Therefore the WOL header cable
should always be installed even if Wake-On-LAN functionality is not required.
D.2.3 82558 CONTROLLER
The Intel 82558 Fast Ethernet LAN controller provides most of the functionality of the card
(Figure D-3). The 82558 provides the following features:
♦
♦
♦
♦
♦
♦
Dual-mode support with auto-switching between 10BASE-T to 100BASE-TX PHY.
Digitally controlled adaptive equalization of transmission
Optimized PCI bandwidth with enhanced support of PCI commands.
ACPI support of power-down and wake-up states.
Wake On LAN (WOL) support.
LANDesk Service Agent (LSA) support.
Figure D-3 shows the internal architecture of the 82558 Ethernet controller.
82558 Ethernet Controller
AD31..0
3-KB
PCI Bus
Bus
I/F
TX FIFO
TX Data
RX Data
Micro
Machine
10BASE-TX/
100BASE-T
PHY
FIFO Cntrl
TX/RX
Filters
4-Ch
DMA
Cntlr.
3-KB
RX FIFO
Figure D–3. 82558 Controller Internal Architecture
The 82558 controller features auto-negotiation of both speed and direction (half/full duplex). The
82558 provides high-level command support for minimum Host CPU intervention and uses 3-KB
FIFOs for both transmit and receive buffers.
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Appendix D Compaq 10/100 TX PCI Intel WOL UTP Controller Card
D.2.4 POWER MANAGEMENT SUPPORT
The controller card provides system wake up using network events and supports both APM and
ACPI power management environments.
NOTE: The APM and ACPI environments use different methods to implement the
Wake-On-LAN function. The cable connection between the controller card’s WOL
header and the system’s WOL header should be complete to insure that the wake up
feature will occur for both the APM and ACPI environments.
D.2.4.1 APM Environment
The Advanced Power Management (APM) functionality of system wake up is implemented
through the system’s APM-compliant BIOS and the controller card’s Magic Packet-compliant
hardware. This environment bypasses operating system (OS) intervention allowing a plugged in
unit to be turned on remotely over the network (i.e., “remote wake up”). In APM mode the
controller, powered by the +5AUX voltage through the WOL header, will respond upon receiving
a Magic Packet, which is a packet where the node’s address is repeated 16 times. Upon Magic
packet detection, the controller card asserts the WAKEUP signal (for about 50 milliseconds) that
is routed through the WOL header and cable to the system board where power control logic turns
on the system and intitiates the boot sequence. After the boot sequence the BIOS clears the PME-
signal (from which WAKEUP is derived) so that subsequent wakeup events will be detected.
D.2.4.2 ACPI Environment
The Advanced Configuration and Power Interface (ACPI) functionality of system wake up is
implemented through an ACPI-compliant OS such as Windows NT 5.0 and hardware that is
compliant to the PCI power management specification. The following wakeup events may be
individually enabled/disabled through the supplied software driver:
♦
Magic Packet – Packet with node address repeated 16 times in data portion
NOTE: The following functions are supported in NDIS5 drivers but implemented through
remote management software applications (such as LanDesk).
♦
♦
♦
♦
Individual address match – Packet with matching user-defined byte mask
Multicast address match – Packet with matching user-defined sample frame
ARP (address resolution protocol) packet
Flexible packet filtering – Packets that match defined CRC signature
When an enabled event is received the controller card asserts the PME- signal that is used by the
system board to initiate its wakeup sequence. Note that the WAKEUP signal is also asserted but
not required in the ACPI environment.
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D.3
CONFIGURATION/CONTROL
The 82558 controller is a PCI device and configured though PCI configuration space registers
using PCI protocol described in chapter 4.
Vender ID
8086h
Device ID
1229h
Control is through I/O registers mapped in the 300h-30Fh range.
D.4
RJ-45 CONNECTOR
Pin
1
Description
Transmit
2
Receive
3
6
Receive Low
Transmit Low
8 7 6 5 4 3 2 1
Figure D–4. Ethernet TPE Connector (RJ-45, viewed from card edge)
SPECIFICATIONS
D.5
Table D-1.
Operating Specifications
Parameter
Modes Supported
Power Management Support
Power Consumption (nominal):
Standby
Half or full duplex for 10BASE-T, 100BASE-TX
APM, ACPI, PCI Power Management Spec.
2.41 watts
2.61 watts
Full On
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Appendix D Compaq 10/100 TX PCI Intel WOL UTP Controller Card
This page is intentionally blank.
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Technical Reference Guide
Appendix E
WIDE ULTRA SCSI HOST ADAPTER
E.1
INTRODUCTION
The Adaptec AHA-2940UW SCSI Host Adapter (Compaq p/n 334136-001) is a PCI peripheral
that provides high performance interfacing with compatible SCSI peripherals, specifically hard
drives. The card installs in a PCI slot and supports full bus mastering capability.
NOTE:
This appendix describes the Wide Ultra SCSI Adapter in general. For detailed
information on the Ultra SCSI Adapter card refer to Adaptec, Inc documentation.
This appendix covers the following subjects:
♦
♦
♦
♦
♦
Functional description (E.2)
SCSI adapter programming (E.3)
Specifications (E.4)
User guidelines (E.5)
SCSI connectors (E.6)
page E-2
page E-3
page E-3
page E-4
page E-5
Internal
Internal
Ultra SCSI Connector
Wide Ultra SCSI Connector
External
Wide Ultra
SCSI Connector
AIC7880
Figure E–1.
Wide Ultra SCSI Host Adapter Card Layout
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Appendix E Wide Ultra SCSI Host Adapter Card
E.2
FUNCTIONAL DESCRIPTION
A block diagram of the Wide Ultra SCSI Card is shown in Figure E-2. The card’s architecture is
based on the AIC-7880 SCSI controller. The AIC-7880 controller includes an on-board SCSI
sequencer that can process SCSI commands without intervention from the host microprocessor.
The sequencer uses micro-code that is downloaded from the host during initialization. Single-
ended SCSI drivers are built into the controller and a 256-byte FIFO in the data path allowing up
to 15-byte synchronous offsets. An LED is provided to indicate SCSI bus activity.
The AIC provides a memory interface that is used by the Serial EEPROM and the BIOS ROM.
The serial EEPROM stores non-volatile configuration data and the BIOS ROM (which is a flash
ROM) contains additional configuration data and SCSI functions. The programmable array logic
(PAL) controls the Serial EEPROM-to-AIC7880 interface.
SCSI operations include the processing of 32-byte SCSI command blocks (SCBs). The AIC-7880
can execute up to 254 SCBs by swapping the blocks in and out of 8-KB of system memory as
there is no on-board memory. The SCBs can be handled on the byte level or as an entire block.
SCSI
Activity
PAL
BIOS
ROM
40-MHz
Mem. I/F
Clock
AIC7880
SCSI
Controller
Ultra SCSI Connector (Ext)
Serial
EEPROM
Wide Ultra SCSI Connector (Int. & Ext.)
PCI Bus
Figure E–2. Adaptec AHA-2940U Ultra SCSI Adapter Card Block Diagram
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E.3
SCSI ADAPTER PROGRAMMING
E.3.1 SCSI ADAPTER CONFIGURATION
The Adaptec AHA-2940U SCSI Adapter Card is a PCI device and configured using PCI protocol
and PCI Configuration Space registers (PCI addresses 00h-FFh) as discussed in Chapter 4.
Configuration is accomplished by BIOS during POST and re-configurable with software.
E.3.2 SCSI ADAPTER CONTROL
Control of the SCSI host adapter is affected through I/O mapped registers mapped as listed in
Table E-1.
Table E-1.
Ultra SCSI Host Adapter Card
Control Register Mapping
I/O Addr.
Function
n00h-n1Fh
n20h-n5Fh
n60h-n7Fh
n80h-n9Fh
n00h-nFFh
SCSI Register Array
Scratch RAM
Phase Engine (Sequencer)
Host Registers
SCB Array
n = prefix address supplied by the BASEADR0 PCI Config. Reg.
E.4
SPECIFCATIONS
The operating specifications are listed in Table E-2.
Table E-2.
Ultra SCSI Host Adapter Card Specifications
Operating Voltage
+5 VDC
Maximum Current Draw
Operating Temperature
2 A
32°F (0°C) to 131°F (55°C)
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Appendix E Wide Ultra SCSI Host Adapter Card
E.5
USER GUIDELINES
The adapter card follows standard SCSI guidelines in supporting up to SCSI devices using SCSI
identification numbers 0-6 (ID #7 is reserved for the adapter card). Each SCSI device chain must
be terminated at both ends.
NOTE: The adapter card includes an external connector and two internal connectors.
All connectors may be in use at the same time. However, if two or more SCSI hard
drives are connected, they must all be either internal or external. Other SCSI
peripherals (tape/CD-ROM drives can be mixed (internal and external). The device
using the external connector must be terminated.
Table E-3 lists the typical parameter configuration for the SCSI adapter card installed in a system
Table E-3.
Wide Ultra SCSI Adapter Card
Typical Configuration
Paramemter
Setting
SCSI Identification Numbers
0
1-4
Hard Drive
available
5
6
CD-ROM (if installed)
available
7
Adapter Card
Enabled
Parity checking
Adapter SCSI Termination
Boot Device Options
Automatic
Boot Target ID
Boot LUN Number
0
0
SCSI Configuration Boot Device Options:
Initiate Sync Negotiation
Maximum Sync Transfer Rate
Enable Disconnection
Initiate Wide Negotiation
Send Start Unit
Yes
40.0 MB/s
Yes
Yes
Yes
Include BIOS Scan
Yes
Advanced Configuration Options:
PnP SCAM Support
Disabled
Enabled
Enabled
Disabled
Enabled
Enabled
Disabled
Disabled
Enabled
Enabled
Silent
Reset SCSI BIOS at IC Initialization
Host Adapter BIOS (Config. Utility Reserves)
Support Removable Fixed Disks Under BIOS
Extended BIOS Translation for >1GB Drives
Display <Ctlr A> Message During BIOS Init.
Multiple LUN Support
BIOS Support for Bootable CD-ROM
BIOS Support for INT 13 Extensions
Support for Ultra SCSI Speed
Silent/Verbose Mode Setting
POST Speedup Feature
Write Cache
Enabled
Enabled
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E.6
SCSI CONNECTORS
Pin 1
Figure E–3. Ultra SCSI Connector (50-pin, as seen from rear of card)
Table E-3.
SCSI Connector Pinout
Pin
1
2
3
4
5
6
7
8
Signal
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
RSVD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Function
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Reserved
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Pin
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Signal
DB0-
DB1-
DB2-
DB3-
DB4-
DB5-
DB6-
DB7-
DBP
Function
Data Bit 0
Data Bit 1
Data Bit 2
Data Bit 3
Data Bit 4
Data Bit 5
Data Bit 6
Data Bit 7
Data Bus Pulse
Ground
Ground
Ground
Termination Power
Ground
Ground
Attention
Ground
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
GND
GND
GND
TERMPWR
GND
GND
ATN-
GND
BSY-
ACK-
SBRST-
MSG-
SEL-
Busy
Acknowledge
Burst
Message Activity
Select
Control/Data Transfer Indicator
Request
C-/D
REQ-
I-/O
Input/Output Indicator
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Appendix E Wide Ultra SCSI Host Adapter Card
Pin 1
Figure E–4. Wide Ultra SCSI Connector (68-pin, as seen from top of card)
Table E-4.
Wide-Ultra SCSI Connector Pinout
Pin
1
2
3
4
5
6
7
8
Signal
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
TERMPWR
TERMPWR
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Function
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Termination Power
Termination Power
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Pin
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
Signal
DB12
DB13
DB14
DB15
DBP-
DB0-
DB1-
DB2-
DB3-
DB4-
DB5-
DB6-
DB7-
DBP-
GND
GND
TERMPWR
TERMPWR
Int_Out-
SBRST-
ATN-
GND
BSY-
ACK-
RESET-
MSG-
SEL-
C-/D
REQ-
I-/O
Function
Data Bit 12
Data Bit 13
Data Bit 14
Data Bit 15
Data Bus Parity
Data Bit 0
Data Bit 1
Data Bit 2
Data Bit 3
Data Bit 4
Data Bit 5
Data Bit 6
Data Bit 7
Data Bus Parity
Ground
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
Ground
Termination Power
Termination Power
Interrupt Out
Burst
Attention
Ground
Busy
Acknowledge
Reset
Message Activity
Select
Control/Data Transfer Indicator
Request
Input/Output Indicator
Data Bit 8
Data Bit 9
Data Bit 10
Data Bit 11
DB8-
DB9-
DB10-
DB11-
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Appendix F
ATI RAGE PRO AGP GRAPHICS CARDS
F.1
INTRODUCTION
This appendix describes ATI RAGE PRO AGP Graphics Cards used in some models. These
graphics cards are based on the ATI RAGE PRO graphics controller. This appendix covers the
following subjects:
♦
♦
♦
♦
♦
Functional description (F.2)
Display modes (F.3)
Programming (F.4)
Monitor power management (F.5)
Connectors (F.6)
page F-2
page F-4
page F-5
page F-6
page F-6
ATI Multimedia Channel
Connector (P1)
Monitor
SODIMM
Expansion
Connector
Connector
ATI
Rage Pro
Turbo
NOTES:
ATI RAGE PRO AGP Card PCA# 008061-001 (ATX) & -002 (NLX)
ATI RAGE PRO AGP 2X Card P/N 334134-001 (ATX) & -002 (NLX)
Figure F–1.
ATI RAGE PRO AGP Graphics Card Layout (NLX version shown)
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Appendix F ATI RAGE PRO AGP Graphics Cards
F.2
FUNCTIONAL DESCRIPTION
The ATI RAGE PRO AGP Graphics Cards are based on the ATI RAGE PRO controller. The
AGP design provides an economical approach to 3D processing by off-loading 3D effects such as
texturing, z-buffering and alpha blending to the system memory while the on-board SGRAM
stores the main display image. Both cards implement side band addressing for high 3D
performance. The AGP 1X card, providing a peak bandwidth of 133 MB/s, comes standard with
four megabytes of 100-MHz SGRAM installed. The AGP 2X card, providing a peak bandwidth
of 500 MB/s, includes four megabytes of 100-MHz SGRAM on the board and an optional 4-MB
SGRAM module may be added to expand the frame buffer memory to eight megabytes.
On-Board
SGRAM [1]
SGRAM
Module
Multimedia
Data
AMC
64-Bit Graphics
Memory Bus
ATI
Connector
RAGE PRO Turbo
AGP Graphics
Controller
32-Bit AGP Bus
AGP
Connector
BIOS
ROM
RGB Data,
Hsync, Vsync
Monitor
NOTES:
[1] 2 megabytes on AGP 1X card, 4 megabytes on AGP 2x card.
2-MB module installed as standard on AGP 1X card. 4-MB module optional on AGP 2X card.
Figure F–2. ATI RAGE PRO AGP Graphics Card Block diagram
The ATI RAGE PRO AGP Graphics Card includes the following software support:
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
Accelerated drive support for Windows 3.x, Win95, and WinNT
MS DirectDraw support for Win95
MS ActiveMovie support for Win95
MPEG-1 software playback for DOS, Windows 3.x, and Win95
MPEG-2 software playback Win95
MS Direct3D support for Win95
QuickDraw 3D RAVE support for Win95 and WinNT
OpenGL support for Win95 and WinNT
Heidi support for WinNT
ATI 3D CIF support for Win95
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F.2.1 ATI RAGE PRO TURBO AGP GRAPHICS CONTROLLER
The ATI RAGE PRO Turbo AGP graphics controller provides most of the functionality of the
integrated graphics subsystem and contains the features listed below:
♦
♦
230-MHz DAC
2D accelerator with:
•
•
•
•
Hardware BitBLT, line draw, polygon fill, h/w cursor
MS DirectDraw support (double buffering, virtual sprites, transparent BitBLT
8-/16-/24-/32-bpp acceleration
24-bpp true color w/1 MB memory
♦
3D accelerator with:
•
•
•
•
•
•
•
Integrated 4-KB texture cache for improved large triangle performance
3D primitive support for points, lines, triangle, lists, strips, and quadrilaterals
Full screen/window double buffering
Hidden surface removal with 16-bit Z-buffering
Single pass bi- and tri-linear filtering support
Full Direct3D texture lighting support
Dithering support in 16-bpp for near-24-bpp quality in less memory
♦
♦
VESA DDC1 and DDC2B support
Video processor/accelerator supporting the following formats:
•
•
•
•
YCrCb 4:2:2
RGB 5-5-5
RGB 5-6-5
Cirrus AcciPak 91m)
♦
♦
Power management for full VESA DPMS and EPA Energy Star compliance
Supports DDC2B+ PnP monitors
Figure F-3 shows the basic architecture of the ATI 3D RAGE PRO controller. Both the AGP and
AGP 2X cards feature the RAGE PRO Turbo controller, with the AGP 2X card using an
enhanced version of the controller that supports AGP 2X operation. The VGA core of the
controller is compatible with VGA, EGA, and CGA software. Extended graphics modes are
supported through video BIOS in flash ROM, which can be easily updated if necessary.
Graphics
3D RAGE PRO
Data
Memory
I/F
Memory
VGA
Controller
AGP Bus
VD7..0
Host
Bus
I/F
HSync
VSync
AGP
Connector
CRT
Controller
Red
Green
Blue
Video
Processor
Drawing
Display
Monitor
Coprocessor
RAM
DAC
VESA
Connector
Figure F–3. ATI 3DRage Pro Graphics Controller Internal Architecture
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Appendix F ATI RAGE PRO AGP Graphics Cards
F.3
DISPLAY MODES
The graphics modes supported by the ATI RAGE PRO AGP1X/2X card with the standard four
megabytes are listed in Tables F-1 and F-2. To expand display mode support will require memory
expansion and may also require a video BIOS upgrade.
Table F-1.
2D Graphics Display Modes (w/SGRAM)
Horizontal
Resolution
640 x 480
640 x 480
640 x 480
800 x 600
Color Depth
256
Refresh Freq.
200 Hz
200 Hz
200 Hz
200 Hz
200 Hz
160 Hz
150 Hz
150 Hz
120 Hz
120 Hz
120 Hz
85 Hz
SGRAM Used
512 KB
1 MB
65K
16.7M
256
65K
16.7M
256
65K
16.7M
256
65K
16.7M
256
65K
16.7M
256
65K
256
1 MB
512 KB
1 MB
1.5 MB
1 MB
1.5 MB
2.5 MB
3 MB
3.5 MB
4 MB
1.5 MB
2.5 MB
4 MB
800 x 600
800 x 600
1024 x 768
1024 x 768
1024 x 768
1152 x 864
1152 x 864
1152 x 864
1280 x 1024
1280 x 1024
1280 x 1024
1600 x 1200
1600 x 1200
1920 x 1080
1920 x 1080
1920 x 1200
100 Hz
100 Hz
85 Hz
85 Hz
85 Hz
75 Hz
75 Hz
75 Hz
2 MB
4 MB
2 MB
4 MB
65K
256
4 MB
NOTE:
Modes not supported with supplied driver.
Table F-2 lists the 3D graphics display modes and how the frame buffer is used.
Table F-2.
3D Graphics Display Modes
Texture Memory
Frame
Buffer
2 MB
2 MB
4 MB
4 MB
4 MB
Front
Buffer
Back
Buffer
Z
Resolution
512 x 384
640 x 480
640 x 480
640 x 480
800 x 600
Color Depth
65K
Buffer
w/Z
w/o Z
0.38 MB
0.59 MB
0.59 MB
1.17 MB
0.92 MB
0.38 MB
0.59 MB
0.59 MB
1.17 MB
0.92 MB
0.38 MB
0.59 MB
0.59 MB
0.59 MB
0.92 MB
0.88 MB
0.24 MB
2.24 MB
1.07 MB
1.25 MB
1.25 MB
0.83 MB
2.83 MB
1.66 MB
2.17 MB
65K
65K
16.7M
65K
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F.4
PROGRAMMING
F.4.1 CONFIGURATION
The graphics card works off the AGP bus and is configured through PCI configuration space
registers using PCI protocol. These registers (Table F-3) are configured by BIOS during POST
Table F-3.
ATI RAGE PRO PCI Configuration Space Registers
PCI Config.
Address
00h
04h
08h
PCI Config.
Address
14h
30h
3Ch
Function
Vender ID (1002h)/Device ID (4744h)
PCI Command
Function
Relocateable I/O Base Address
Expansion ROM Base Address
Interrupt Line / Interrupt Pin
--
Status
10h
Display Memory Base Address
--
For a discussion of accessing PCI configuration space registers refer to chapter 4. For a detailed
description of registers refer to applicable ATI Technologies, Inc. documentation.
F.4.2 CONTROL
F.4.2.1 Standard VGA Modes
Table F-4 list the control registers used for operating in standard VGA mode. No special drivers
are required for VGA, EGA, and CGA modes. For a detailed description of the registers refer to
applicable ATI Technologies, Inc. documentation.
Table F-4.
Standard VGA Mode I/O Mapping
I/O
I/O
Address
3B5.00..26h*
3BAh
3C1.00..14h*
3C2h
Function
Address
3C6h..3C9h
3CAh
3CCh
3CF.00..08h
Function
RAMDAC
Read VSYNC Status
Misc. Control, Read
Graphics Controller
CRT Controller (mono)
VSYNC Control, Display Status
Attribute Controller
Misc. Control / Status
Sequencer
3C5h.00..04h*
--
3D5.00..26h* CRT Controller (color)
3DAh VSYNC Control, Display Status (color)
--
* Index at base minus 1 (i.e., if base is 3B5h, index is at 3B4h.
F.4.2.2 Extended VGA Modes
Extended modes use the on-board video BIOS (contained in a flash ROM) and the supplied
driver (which is the same for both cards).
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Appendix F ATI RAGE PRO AGP Graphics Cards
F.5
MONITOR POWER MANAGEMENT CONTROL
This controller provides monitor power control for monitors that conform to the VESA display
power management signaling (DPMS) protocol. This protocol defines different power
consumption conditions and uses the HSYNC and VSYNC signals to select a monitor’s power
condition. Table F-5 lists the monitor power conditions.
Table F-5.
Monitor Power Management Conditions
HSYNC
VSYNC
Power Mode
Description
Active
Active
On
Monitor is completely powered up. If activated, the inactivity
counter counts down during system inactivity and if allowed to
tiemout, generates an SMI to initiate the Suspend mode.
Monitor’s high voltage section is turned off and CRT heater
(filament) voltage is reduced from 6.6 to 4.4 VDC. The Off mode
inactivity timer counts down from the preset value and if allowed to
timeout, another SMI is generated and serviced, resulting in the
monitor being placed into the Off mode. Wake up from Suspend
mode is typically a few seconds.
Active
Inactive
Inactive
Suspend
Inactive
Off
Monitor’s high voltage section and heater circuitry is turned off.
Wake up from Off mode is a little longer than from Suspend.
F.6
CONNECTORS
There are three connectors associated with the graphics subsystem; the display/monitor
connector, the ATI Multimedia Channel (AMC) connector (which includes the VESA Standard
Feature Connector (VSFC)), and a SODIMM connector for frame buffer memory expansion.
NOTE: The graphic card’s edge connector mates with the AGP connector on the system
board. This interface is described in chapter 4.
F.6.1 MEMORY EXPANSION CONNECTOR
A memory expansion connector is included allowing the expansion of frame buffer memory. This
connector accepts an industry-standard 144-pin SODIMM. The SODIMM socket on the AGP 1X
card has a 2-MB SGRAM module installed as standard. The SODIMM socket on the AGP 2X
card is not populated and can accept a 4-MB SGRAM module for expansion to eight megabytes.
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F.6.2 MONITOR CONNECTOR
9
Figure F–4. VGA Monitor Connector, (Female DB-15, as viewed from rear).
Table F-6.
DB-15 Monitor Connector Pinout
Pin
1
2
3
4
5
6
7
8
Signal
R
G
B
NC
GND
R GND
G GND
B GND
Description
Red Analog
Blue Analog
Green Analog
Not Connected
Ground
Red Analog Ground
Blue Analog Ground
Green Analog Ground
Pin
9
Signal
PWR
GND
NC
SDA
HSync
VSync
SCL
Description
+5 VDC (fused) [1]
Ground
Not Connected
DDC2-B Data
Horizontal Sync
Vertical Sync
DDC2-B Clock
--
10
11
12
13
14
15
--
--
NOTES:
[1] Fuse automatically resets when excessive load is removed.
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Appendix F ATI RAGE PRO AGP Graphics Cards
F.6.3 ATI MULTIMEDIA CHANNEL CONNECTOR
The ATI Multimedia Channel (AMC) is provided through a 40-pin header (Figure F-5) that
includes the VESA standard feature (VSFC) connector (also known as the VGA pass-through
connector) and additional signal interface. The AMC interface can operate in one of the
following three modes:
VSFC Mode – The VESA Standard Feature Connector (VFSC) mode supports an overlay
peripheral such as an MPEG or TV card. This mode, available in all VGA modes and accelerated
modes, receives video data through the VSFC I/F and overlays the data onto the graphics display
(display clock < 80 Hz).
DVS Mode – The Digital Video Stream (DVS) mode supports connection to a video decoder.
MPP Mode – The Multimedia Peripheral Port (MPP) mode supports data streaming from Host
memory out of the multimedia interface.
Multimedia Interface
VESA Standard Feature I/F
Y20
Z20
Y1
Y13
Z12
Z1
Figure F–5. AMC Connector (40-Pin Header P1)
Table F-7.
Multimedia Interface Connector Pinout
Pin
Z1
Z2
Z3
Z4
Z5
Z6
Z7
Z8
Signal
GND
GND
Description
Ground
Ground
Ground
Overlay Enable
External Sync Enable
External Clock Enable
Serial Data
Ground
Ground
Ground
Ground
Serial Clock
KEY
KEY
+5 volts DC
Reset
SA Data Bit 6
Reserved
Ground
Pin
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Signal
P0
P1
P2
P3
P4
P5
P6
Description
Pixel Data 0
Pixel Data 1
Pixel Data 2
Pixel Data 3
Pixel Data 4
Pixel Data 5
Pixel Data 6
Pixel Data 7
Pixel Data Clock
DAC Output Blanking
Horizontal Sync
Vertical Sync
Ground
GND
EVIDEO-
ESYNC-
EDCLK
SDA
GND
GND
GND
GND
SCL
--
Y8
Y9
P7
Z9
DCLK
BLANK
HSYNC
VSYNC
GND
AZY
SAD3
SAD7
SAD5
REV
+12 VDC
AUD L
Z10
Z11
Z12
Z13
Z14
Z15
Z16
Z17
Z18
Z19
Z20
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
--
+ 5 VDC
RESET-
SAD6
RESVD
A. GND
AUD R
SA Data Bit 3
SA Data Bit 7
SA Data Bit 5
+12 volt DC
Left Audio
Right Audio
NOTE: VESA standard interface is unshaded.
F-8 Compaq Personal Computers
Original - April 1998
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INDEX
3D effects, F-2
IDE interface, 5-8
87307 I/O controller, 4-49
abbreviations, 1-3
IDE/diskette drive power, 7-5
ISA bus, 4-17
Accelerated Graphics Port (AGP), 4-11
ACPI, D-4
acronyms, 1-3
keyboard/pointing device interface, 5-33
parallel interface, 5-26
PCI bus, 4-3
administrator password, 4-52, 4-53
AGP, 4-11
AGP bus, 2-10
analog-to-digital converter (ADC), 6-4
APM, D-4
APM BIOS functions, 8-23
APM BIOS support, 8-22
architecture, system, 2-10
ASCII character set, B-1
AT attachment (ATA), 5-3
audio subsystem, 2-14, 6-1
backplane, 2-6
RJ-45, D-5
serial interface (RS-232), 5-14
Ultra SCSI (50-pin), E-5
Universal Serial Bus interface, 5-35
VGA pass-through (feature), F-8
Wide Ultra SCSI (68-pin), E-6
cover lock, 4-55
Desktop management, 4-51
Desktop Management, 8-4
digital-to-analog converter (DAC), 6-5
DIMM detection, 8-3
DIMM support, 8-13
battery replacement, 4-29
BIOS ROM, 2-13
BIOS upgrading, 3-5, 8-24
BIOS, ROM, 8-1
DIP switch, D-4
DIP switch, power-on password disable, 4-52, 4-
53
disabling I/O, 4-53
Black Box logic, 4-52
boot block ROM, 8-2
cache, L1, L2, 2-13
diskette drive interface, 5-9
display modes, F-4
DMA, 4-20
cartridge, SEC, 2-12
Celeron processor, 2-12, 3-4
chipsets, support, 2-13
clock distribution, 4-28
CMOS, 4-29
CMOS, clearing, 4-30
configuration (ISA), 4-27
Configuration Cycle, 4-6
configuration memory, 4-29
Connector
DMI, 8-20
drive fault prediction, 8-13, 8-14, 8-15, 8-16
effects, 3D, F-2
EIDE interface, 5-1
Enhanced Parallel Port (EPP), 5-21
error codes, A-1
error messages, A-1
Ethernet, D-1
events, wake up, 7-4
expansion card cage, 2-6
Extended Capabilities Port (ECP), 5-21
fan control, 4-56
features, standard, 2-2
flash ROM, 4-52
AGP bus, 4-15
AMC (multimedia/VESA), F-8
Audio, CD, 6-3
Audio, Headphone Out, 6-2
Audio, Line In, 6-2
FM synthesis, 6-7
Audio, Line Out, 6-2
Audio, Mic In, 6-2
general purpose I/O, 4-47
GPIO, 3-5, 4-47
Audio, Speaker, 6-3
I/O controller, 4-50
diskette drive interface, 5-13
display (VGA monitor), F-7
south bridge, 4-47
graphics card, ATI RAGE PRO AGP, F-1
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graphics subsystem, 2-14
graphics, 3D, F-2
guidelines, SCSI user, E-4
hard drive spindown, 4-57
heat sink (processor), 2-12, 3-5
Host bus, 2-10
Plug 'n Play BIOS function, 8-19
power button, 4-56, 7-3
power distribution, 7-5
power management, 4-56
Power Management BIOS function, 8-21
power supply, 7-1
I/O controller (87307), 4-49
I/O map, 4-46
IDE interface, 5-1
index addressing, 1-2
interrupts
maskable (IRQn), 4-23
nonmaskable (NMI, SMI), 4-25
interrupts, PCI, 4-9
power-on password, 4-52, 4-53
processing speed, selecting, 3-5
processor upgrading, 3-5
processor, Celeron, 2-12, 3-4
processor, Pentium II, 2-12, 3-3
QuickBoot, 8-2
QuickLock/QuickBlank, 4-53
RAM, 2-13
interval timer, 4-27
ISA bus, 2-10
reference sources, 1-1
remote flashing, 8-2
ISA bus, overview, 4-16
key (keyboard) functions, C-6
keyboard, C-1
remote wake up, D-4
reset, 8-2
ROM BIOS, 8-1
keyboard (micro)processor, C-2
keyboard layouts, C-4
keyboard/pointing device interface, 5-27
L2 (secondary) cache, 3-3
LAN, D-1
LED indicatons, power, 7-3
low voltages, 7-6
Magic Packet, 7-4, D-4
media write protect function (BIOS), 8-18
memory detection, 8-3
memory map, 3-8
RTC, 4-29
scan codes (keyboard), C-9
SCSI adapter card, wide ultra, E-1
SCSI user guidelines, E-4
SEC cartridge, 2-12, 3-2
secondary (L2) cache, 3-3
security functions (BIOS), 8-18
security, I/O, 4-53
sensor, cover removal, 4-55
sensor, tempurature, 4-54
serial interface, 5-14
sideband addressing, 4-12
signal distribution, 7-7
SilentBoot, 8-2
memory, cache (SRAM), 2-13
memory, ROM (BIOS), 2-13
memory, system, 3-6
memory, system (RAM), 2-13
mixing, 6-2
MMX technology, 3-3
monitor power control, 4-57, F-6
mouse interface, 5-29
NIC card, D-1
single edge connector, 3-2
Smart Cover Lock, 4-55
Smart Cover removal sensor, 4-55
SMBIOS, 8-20
SMI, 4-26
spatializer, 6-2
NLX card, F-1
speaker, 6-2
notational conventions, 1-2
options, 2-3
special cycles (PCI), 4-8
specifications
parallel interface, 5-20
password, administrator, 4-52, 4-53
password, clearing, 4-30
password, power-on, 4-52, 4-53
PCI bus, 2-10, 2-13
electrical, 2-15
environmental, 2-15
physical, 2-15
power supply, 7-7
Specifications
PCI bus, overview, 4-2
PCI Configuration Space, 4-7
PCI interrupts, 4-9
PCM audio processing, 6-4
Pentium II, 2-13, 3-3
8x CD-ROM Drive, 2-16
Audio subsystem, 6-11
Diskette Drive, 2-16
Hard Drive, 2-18
SCSI Host Adapter, E-3
specifications, system, 2-15
system board, 2-9
Pentium II processor, 2-12, 3-3
Plug ’n Play, 2-2, 2-3, 2-14, 8-19
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system ID, 8-6
upgrading, Ethernet interface, D-4
upgrading, processor, 3-5
USB interface, 5-34
USB legacy support, 8-24
USB ports, 2-14
VESA connector, F-8
wake up (power), 7-4
wake up events, 7-4
system information table (SIT), 8-6
system management, 4-51
system memory, 2-13, 3-6
system ROM, 2-13, 8-1
tempurature sensor, 4-54
thermal considerations, 3-5
thermister, 4-56
timer, interval, 4-27
UART, 5-14
Universal Serial Bus (USB) interface, 5-34
upggrading BIOS, 8-24
wake up, remote, D-4
Wake-On-LAN (WOL), D-1
WOL, 7-4
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