16700 Series
Logic Analysis System
Product Overview
Debugging today's digital systems
is tougher than ever. Increased
product requirements, complex
software, and innovative hardware
technologies make it difficult to
meet your time-to-market goals.
The Agilent Technologies
16700 Series logic analysis systems
provide the simplicity and power you
need to conquer complex systems
by combining state/timing analysis,
oscilloscopes, pattern generators,
post-processing tool sets, and
emulation in one integrated system.
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System Overview
Modular Design
Module Choices
User Benefits
Modular Design Protects Your
Long-Term Investment
State/Timing
Agilent offers a wide variety of state/timing modules for a range
of applications, from high-speed glitch capture to multi-channel
bus analysis.
Modularity is the key to the Agilent
16700 Series logic analysis systems'
long term value. You purchase only
the capability you need now, then
expand as your needs evolve. All
modules are tightly integrated to
provide time-correlated, cross
domain measurements.
High-Speed Timing
Oscilloscopes
Precisely characterize setup/hold times over a wide channel
count. Capture data over many clock cycles while retaining the
highest multi-channel accuracy.
Identify signal integrity issues and characterize signals quickly
with automatic measurements of rise time, voltage, pulse width,
and frequency.
Pattern Generation
Emulation
Use stimulus to substitute for missing system components or to
provide a stimulus-response test environment.
An emulation module connects to the debug port (BDM or JTAG)
on your target. You have full access to processor execution
control features of the module through the built-in emulation
control interface or a third-party debugger.
External Ports
Target Control Port
Use the target control port to force a reset of your target or
activate a target interrupt.
Port-in/Port-out
A BNC connector allows you to trigger or arm external devices
or to receive signals that can be used to arm acquisition
modules within your logic analyzer.
Help
enables you to
access the online
user’s guide and
measurement
examples.
Figure 1.1. The system boot up screen shows you
what modules are configured into your logic
analysis system.
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System Overview
Features and Benefits
System Capability
NEW Touch Screen Interface
The Agilent 16702B mainframe supports a large, 12.1 inch LCD touch screen and redesigned front panel
controls for an easy-to-operate, self-contained unit requiring minimal bench space and offering simple
portability.
NEW Multiframe Configuration
By connecting up to eight mainframes and expanders you can simultaneously view time-correlated traces for
all buses in a large channel count, multibus system.
NEW Enhanced Mainframe Hardware
Mainframe now includes a 40X CD-ROM drive, a 9 GB hard disk drive, 100BaseT-X LAN, and 128 MB of
internal system RAM (optional 256 MB total).
Scalable System
• State/timing analyzers
• High-speed timing
• Oscilloscopes
• Select the optimum combination of performance, features, and price that you need for your specific
application today, with the flexibility to add to your system as your measurement needs change.
• View system activity from signals to source code.
• Pattern generators
• Emulation modules
Measurement Modules/Interfaces
The Agilent 16760A
State/Timing Module
With up to 1.5 Gb/s state speed, the 16760A lets you debug today’s and tomorrow’s ultra-high-speed
digital buses. NEW Eye scan gives a rapid comprehensive overview of signal integrity on hundreds of
channels simultaneously
The Agilent 16750A, 16751A,
and 16752A State/Timing Modules
With up to 400 MHz state speed and up to 32 MBytes of trace depth these modules help you address today’s
high-performance measurement requirements. (See page 19)
The Agilent 16720A
Pattern Generator
With up to 16 MVectors depth and 300 MVectors/sec operation and up to 240 channels[1] of stimulus, the
16720A provides a new level of capability that makes complex device substitution a reality. Supports TTL,
CMOS, 3.3V, 1.8V, LVDS, 3-state, ECL, PECL, and LVPECL.
High-Speed Bus Measurements
Made Simple with Eye Finder
Technology
Agilent’s eye finder technology automatically adjusts the setup and hold on every channel, eliminating the
need for manual adjustment and ensuring accurate state measurements on high-speed buses.
Timing Zoom Technology
VisiTrigger Technology
Simultaneously acquire data at up to 2 GHz timing and 400 MHz state through the same connection. Timing
Zoom is available across all channels, all the time. (See page 23)
• Use graphical views and sentence-like structure to help you define a trace event.
• Select trigger functions as individual trigger conditions or as building blocks to easily customize a trigger
for your specific task.
Processor and Bus Support
• Get control over your microprocessor’s internal and external data.
• Quickly and reliably connect to the device under test. (See page 36)
Direct Links to Industry Standard
Debuggers and High-Level
Language Tools
• Debuggers provide visibility into software execution for systems running software written in C and C++ as
well as active microprocessor execution control (run control).
• Import symbol files created by your language tool. Symbols allow you to set up trigger conditions and review
waveform and state listings in easily recognized terms that relate directly to the names used for signals on
your target and the functions and variables in your code.
Direct Links to EDA Tools
• Use captured logic analysis waveforms to generate simulation test vectors.
• Easily find problems by comparing captured waveforms with simulated waveforms.
[1] 240 channel system consists of five 16720A pattern generator modules with 48 channels per module. Full channel mode runs at 180 MVectors/s and 8 MVectors depth.
300 MVectors/s and 16 MVectors depth are offered in half channel mode.
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System Overview
Features and Benefits
Data Transfer, Documentation, and Remote Programming
Direct Link to Microsoft® Excel via
Agilent IntuiLink
• Automatically move your data from the logic analyzer into Microsoft Excel with just a click of the mouse.
(See page 12)
• Use Microsoft Excel’s powerful functions to post-process captured trace data to get the insight you need.
Transfer Data for Offline Analysis -
Data Export
• Fast binary (compressed binary) from the FileOut tool provides highest performance transfer rate.
• ASCII format provides same format as listing display, including inverse-assembled data.
Transparent File System Access
• Access, transfer, and archive files.
• Stay synchronized with your source code by mapping shared directories and file systems from your
Windows 95/98/NT-based PC directly onto the logic analyzer and vice versa.
• Move data files to and from the logic analyzer for archiving or use elsewhere.
Documentation Capability
• Save graphics in standard TIFF, PCX, and EPS formats.
• Print screen shots and trace listings to a local or networked printer.
• Save your lab notes and trace data in the same file by entering relevant information in the Comments tab of
the display.
Remote Programming with
Microsoft’s COM Using
Microsoft Visual Basic or
Visual C++
• Perform pass/fail analysis, stimulus response tests, data acquisition for offline analysis, and system
verification and characterization tests.
• Powerful-yet-efficient command set focuses on your programming tasks, resulting in a shorter learning
curve while maintaining necessary functionality.
System Software Features
Post-Processing Analysis Tools
Rapidly consolidate large amounts of data into displays that provide insight into your system’s behavior.
(See page 38)
Setup Assistant
Tabbed Interface
Quickly configure the logic analysis system for your target microprocessor. (See page 9)
• Groups like tasks together so you can quickly find and complete the task you want to perform.
• Spend your time solving problems, not setting up a measurement.
Multi-Windowed View of
Target System Activity
• View your cross-domain measurements, time-corrected on the same screen. (See page 10)
• Debug faster because you can view system activity at a glance.
Global Markers
Track a symptom in one domain (e.g., timing) to its cause in another domain (e.g., analog).
Resizable Windows and Data Views
• Magnify your view or zoom in on a boxed area of interest.
• Resize waveforms and data or quickly change colors to highlight areas of interest.
Web-Enabled System
Network Security
• Directly access the instrument’s web page from your web browser. (See page 11)
• Remotely check the instrument’s measurement status without disturbing the acquisition.
• Remotely access, monitor and control your logic analysis system.
• Protect your networked assets and comply with your company’s security requirements with individual user
logins that provide system integrity.
NEW Time Correlation with
Infiniium 54800 Series Oscilloscopes
• Make time-correlated measurements using an Agilent 16700 Series logic analyzer and an
Agilent Infiniium 54800 Series oscilloscope.
• View Infiniium oscilloscope waveforms in the 16700 logic analyzer’s waveform display.
• Use the 16700 logic analyzer’s global markers to measure time between any domain in the 16700 and voltage
waveforms acquired by the Infiniium oscilloscope.
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System Overview
Selecting the Right System
Selecting a system for your application
Select a mainframe (page 7)
Choose a system based on your needs:
•
Self-contained unit or a unit with
external mouse, keyboard, and monitor
Expander frame for large channel count
requirements
•
Determine your probing requirements (page 13)
•
•
Are you analyzing a microprocessor?
Do you need to probe a specific package type?
Select the measurement modules to meet your
application needs
•
•
•
•
State/Timing Logic Analyzers (page 17)
Oscilloscopes (page 29)
Pattern Generation (page 32)
Emulation (page 36)
Add post-processing tool sets for analysis and
insight (page 38)
•
•
•
•
•
Source correlation
Data communications
System performance analysis
Serial analysis
Tool development kit
Support, services, and assistance (page 123)
•
•
•
•
Training classes
Consulting
On-line support
Warranty extension
6
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Mainframes
Display
12.1" LCD display with touch screen on
the 16702B makes it easy to view a large
number of waveforms or states.
Select a modifiable variable by touching
it, then turn the knob to quickly step
through values for the variable.
Dedicated hot keys give instant access to
the most frequently used menus, displays,
and on-line help.
Dedicated knobs for horizontal and vertical
scaling and scrolling. Adjust the display to
get just the information you need to solve
your problem.
"Touch Off" button disables the touch
screen and allows you to point out a
nomalies to a colleague without altering
the display settings.
Dedicated knobs for global markers help
track down tough problems. A symptom
seen in one domain (e.g., timing) can be
tied to its cause in another domain
(e.g., analog).
Figure 2.1. The Agilent 16702B quickly tracks down problems in your design while saving precious bench space.
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Mainframes
Back Panel
Connection for optional monitor.
Parallel printer port
SCSI-II connection for an
(Up to 1600x1200 video
resolution with option 003)
external 18 GByte data drive or
external removable hard drive
10/100BaseT LAN - autosensing
Five slots for
measurement
modules
Option slot for an emulation module or
for a multiframe module. Multiframe
option allows up to eight mainframes
and expanders to be combined so that
you can see all the buses in a complex
target system.
Expander frame connection provides an
additional five slots for measurement
modules.
Built-in 40x CD-ROM drive makes it easy
to install or update system software,
processor support, or tool sets.
Figure 2.2. The mainframe and expander frame provide advanced capabilities for debugging complex target systems.
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Mainframes
System Screens
Figure 2.3. Icons in the power-up screen give you
quick access to common tasks.
System Admin
Demo Center
provides simple
demos of the most
commonly used
features.
Setup Assistant
is a guided menu
system that helps
you configure the
logic analysis sys-
tem for your target
microprocessor or
bus. Online infor-
mation guides you
through the setup.
(See figure 2.4)
allows you to quick-
ly set up the instru-
ment on your net-
work, configure
print servers, set up
user accounts for
security or install
software updates.
Figure 2.4. Setup Assistant gets you up and
running quickly.
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Mainframes
System Screens
See the Big Picture of Your
Prototype System's Behavior
A large external display (option 001)
with multiple, resizable windows
allows you to see at a glance more of
your target system's operation. A
built-in, flat-panel display in the
16702B fits in environments with
limited space. Color lets you highlight
critical information so you can find
it quickly.
Use one system to examine target
operation from different perspec-
tives. Multiple time-correlated views
of data let you confirm both signal
integrity and software execution
flow. These views are invaluable in
solving cross-domain problems.
Figure 2.5. You can quickly isolate the root cause of system problems by examining target operation across a wide
analysis domain, from signals to source code.
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Mainframes
System Screens
Expanding Possibilities with
Network Connectivity
Web-enabled instrumentation gives
you the freedom to access the
system—anywhere, anytime. Have
you ever needed to check on a
measurement's status while you were
in a remote location? Now you can.
With a Web Enabled Logic
Analysis System You Can...
...access Agilent's Web site for the latest
online manuals and technical information
...install Agilent IntuiLink to seamlessly
transfer data from the system to a PC
...access the logic analysis
system's Web page from
your browser by using the
instrument's hostname as
a URL
...access the system’s user
interface directly from with-
in your browser, giving you
full control of all analysis
functions
...remotely check current
measurement status to find
out if the system has
triggered
...quickly check instrument
status to determine if the
system is available for use
Figure 2.6. Your logic analyzer is its own web site. From the Home Page, you can perform multiple remote functions.
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Mainframes
IntuiLink
Agilent IntuiLink Moves Your
Data Automatically into
Microsoft® Excel for
Advanced Offline Analysis
IntuiLink is shipped with each logic
analysis system and can be down-
loaded to your PC from the system’s
own web page. Use the Agilent
IntuiLink tool bar to connect to a
logic analysis system. Select from
the available labels and specify
the destination cell location in
Microsoft Excel.
Use Microsoft Excel's powerful
functions to post-process captured
trace data for the insight you need.
Import data from a current
acquisition or data previously saved
to a file via the File Out tool.
Figure 2.7. Transfer data into Microsoft Excel with just a click of the mouse.
Programming
IntuiLink also includes an Active-X
automation server to provide
programmatic control of the logic
analysis system from an external
environment, such as LabVIEW or the
Microsoft VisualStudio environment
of Visual Basic and Visual C++ tools.
The instrument's Remote
Programming Interface (or RPI) also
allows you to write Perl or other
scripts to control the logic analyzer.
Use the sample programs provided
to assist you in creating your own
custom programs.
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Probing Solutions
Criteria for Selection
Why is Probing Important?
Your debugging tools perform three
important tasks: probing your target
system, acquiring data, and analyzing
data. Data acquisition and analysis
tools are only as effective as the
physical interface to your target
system. Use the following criteria to
see how your probing measures up.
How to Determine Your
Requirements
To determine what probing method
is best to use you need to take the
following into consideration:
• The number of signals to be
probed
Figure 3.1. A rugged connection lets you focus on debugging your target, not your probe.
• The ability to design probing
connectors on the target PC board
itself
• Mechanical probing clearance
requirements
• Signal loading effects
• Ease of attachment
• Package type to be probed
Immunity to Noise
EMF noise is everywhere and can corrupt your data. Active
attenuator probing can be particularly susceptible to noise effects.
Agilent Technologies designs probing solutions with high immunity to
transient noise.
DIP
PGA
BGA
Dual In-line Package
Pin Grid Array
Ball Grid Array
Impedance
Ruggedness
Connectivity
High input impedance will minimize the effect of probing on your
circuit. Although many probes are acceptable for lower frequencies,
capacitive loading dominates at higher frequencies.
PLCC Plastic Leaded Chip
Carrier
PQFP Plastic Quad Flat Pack
TQFP Thin Quad Flat Pack
SOP
TSOP
A flimsy probe will give you unintended open circuits. Agilent
Technologies' probes are mechanically designed to relieve strain and
ensure a rugged and reliable connection.
Small Outline Package
Thin Small Outline
Package
A multitude of device packages exist in the digital electronics industry.
Check our large selection of probing solutions designed for specific
chip packages or buses. As an alternative, we offer reliable
• Package Pin Pitch (distance
between pin centers)
termination adapters that work with standard on-target connectors.
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Probing Solutions
Technologies
Choose the Optimum Probing
Strategy for Your Application
NEW Figure 3.3. The E5382A single-ended flying lead
probe set provides connections for 17 channels of
the 16760A logic analyzer.
Connecting to individual test
points with flying leads
Figure 3.4. Surface mount IC clip.
5090-4356 (20 clips).
Figure 3.2.
Figure 3.5. 0.5 mm IC clip.
10467-68701 (4 clips).
Advantages
Limitations
Most flexible method.
Flying-lead probes are included with logic
analyzer module (except 16760A).
Can be time-consuming to connect a large
number of channels. Least space-efficient
method.
Figure 3.6. Wedge adapters connect to multiple
pins of 0.5 mm or 0.65 mm QFP ICs. Refer to
“Probing Solutions for Agilent Technologies
Logic Analysis Systems,” publication number
5968-4632E, for specific part numbers.
Connecting to all the pins of a
quad flat pack (QFP) package
Figure 3.7.
Advantages
Limitations
Refer to “Probing Solutions for
Agilent Technologies Logic Analysis
Systems,” publication number
5968-4632E, for specific solutions.
Rapid access to all pins of fine-pitch
QFP package.
Very reliable connections.
Requires minimal keepout area.
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Probing Solutions
Technologies
Designing connectors into
the target system
Figure 3.8.
Advantages
Limitations
Very reliable connections.
Saves time in making multiple connections.
Requires advance planning in the design stage.
Requires some dedicated board space.
Moderate incremental cost.
High-density probing solutions
Model
Description
Requires kit of 5 connectors
Usable with
number
and 5 shrouds
logic analyzers
E5385A
E5346A
E5351A
E5339A
100-pin probe with built-in isolation networks for the logic analyzer
16760-68701
All except 16517A,
16518A,16760A
34-channel, 38-pin probe with built-in
isolation networks for the logic analyzer.
E5346-68701
E5346-68701
E5346-68701
All except 16517A,
16518A, 16760A
34-channel 38-pin adapter cable, requires logic analyzer
isolation networks on the target.
All except 16517A,
16518A, 16760A
34-channel 38-pin low-voltage probe with
built-in isolation networks for the logic analyzer. Designed for signals
with peak-to-peak amplitude as small as 250 mV.
All except 16517A,
16518A, 16760A
E5378A
E5379A
E5380A
34-channel 100-pin single-ended probe for 16760A
17-channel 100-pin differential probe for 16760A
34-channel 38-pin single-ended probe for 16760A
16760-68701
16760-68701
E5346-68701
16760A only
16760A only
16760A only
The Agilent 01650-63203 isolation
adapter contains the termination
networks for the logic analyzer. The
01650-63203 connects to a 3M 20-pin
connector on the target PC board.
Refer to "Probing Solutions for
Agilent Technologies Logic Analysis
Systems," publication number
5968-4632E, for design guidelines
and part numbers for mating
connectors.
You may also add the isolation
Moderate-density probing solutions
networks to the target PC board and
connect the logic analyzer cable
directly to a 40-pin 3M connector on
the PC board. Refer to "Probing
Solutions for Agilent Technologies
Logic Analysis Systems," publication
number 5968-4632E, for design
guidelines in addition to part num-
bers for mating connectors and
isolation networks.
Figure 3.9. 01650-63203 termination adapter.
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Probing Solutions
Technologies
Using a processor- or bus-specific
analysis probe
Figure 3.10.
Advantages
Limitations
Refer to “Processor and Bus Support
for Agilent Technologies Logic
Analyzers,” publication number
5966-4365E, for specific solutions.
Easiest and fastest connection to supported
processors and buses.
Moderate to significant incremental cost.
Only useable for the specific processor or bus.
May require moderate clearance around
processor or bus.
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Data Acquisition and Stimulus
State/Timing Modules
performance, cost, and the amount of
Selecting the Correct Modules
to Meet Your Needs
Selecting the proper logic analyzer
modules for your needs requires a
series of choices concerning
data you will be able to capture. The
following table explains these factors
in greater detail.
Considerations for Choosing Modules
Microprocessor/
Bus Support
Will you be using an analysis probe for a particular processor or bus? If so, a good starting point is the document Processor
and Bus Support for Agilent Technologies Logic Analyzers, publication number 5966-4365E, available on the worldwide web
at www.agilent.com/find/logicanalyzer. This document provides the number of channels and state speed required for any
particular analysis probe. It also indicates which analysis modules are supported and how many are required.
State Speed
• State analysis uses a clock or strobe signal from your system under test to determine when to sample. Because state
analysis samples are synchronous with the system under test, they provide a view of how your system is executing. You can
use state analysis to capture bus cycles from a microprocessor or I/0 bus and convert the data into processor mnemonics
or bus transactions using an Agilent Technologies inverse assembler.
• Select a state acquisition system that provides the speed and headroom you need without breaking your budget. Remember
that a microprocessor will have an internal core frequency that is normally 2X-5X the speed of the external bus.
Headroom
You may realize a better return on your investment if you consider possible future needs when purchasing analysis modules.
The things to consider are primarily state speed and memory depth.
Setup/Hold
• Logic analyzers require time for the data at the inputs to become valid (setup time), and time to capture the data (hold time).
A lengthy setup and hold can make the difference between capturing valid data or data in transition.
• Your device under test will ensure that data is valid on the bus for a defined length of time. This is known as the data valid
window. Your target's data valid window must be large enough to meet the setup/hold specifications of the logic analyzer.
The data valid window of most devices is generally less than half of the clock period. Don't be fooled by "typical" setup and
hold specifications for logic analyzers.
• As bus speeds increase, the time window during which data is stable decreases. Jitter, skew, and pattern-dependent ISI
add more uncertainty and consume a greater portion of the data-valid window at high speeds. A logic analyzer with
adjustable setup/hold with fine position resolution provides unparalleled measurement accuracy at high frequencies.
Timing Resolution
Transitional Timing
Timing analysis uses the logic analyzer's internal clock to determine when to sample. Since timing analysis samples
asynchronously to the system under test, you should consider what accuracy you will need to verify your system.
Accuracy is made up of two elements: sample speed and channel-to-channel skew. Remember to evaluate both of these
elements and be careful of logic analyzers that have a fast sample speed with a large channel-to-channel skew.
If your system has bursts of activity followed by times with little activity, you can use transitional timing to capture a longer
trace. In transitional timing, the analyzer samples data at regular intervals, but only stores the data when there is a transition
on one of the signals.
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Data Acquisition and Stimulus
State/Timing Modules
Considerations for Choosing Modules (continued)
Channel Count
Determine the number of signals you want to analyze on your system under test. You will need this number of channels in
your logic analyzer. Even if you have enough channels to view all the signals in your system today, you should consider logic
analysis systems that allow you to add more channels for your future application needs.
Memory Depth
• Complex architectures and bus protocols make your debugging job increasingly challenging. Split transactions, multiple
outstanding transactions, pipelining, out-of-order execution, and deep FIFOs, all mean that the flow of data related to a
problem can be distributed over thousands or millions of bus cycles.
• The keys to useful insight are the combination of deep memory with responsive display refresh, search, rescaling, and
scrolling to help you find information and answers quickly. Hardware-assisted memory management in the Agilent
16740A, 16741A, 16742A, 16750A, 16751A, 16752A, and 16760A state and timing analysis modules makes quick work of
refreshing the display, rescaling, scrolling, and searching. It takes only a few seconds to refresh, rescale, or scroll a 32M
sample record. Agilent Technologies offers a range of state and timing analyzer modules with memory depths up to 128M
samples, at prices to meet your budget.
Triggering
• The logic analyzer memory system is similar to a circular buffer. When the acquisition is started, the analyzer continuously
gathers data samples and stores them in memory. When memory becomes full, it simply wraps around and stores each new
sample in the place of the sample that has been in memory the longest. This process will continue until the logic analyzer
finds the trigger point. The logic analyzer trigger stops the acquisition at the point you specify and provides a view into the
system under test. The primary responsibility of the trigger is to stop the acquisition, but it can also be used to control the
selective storage of data. Consider a logic analyzer with the trigger resources you need to quickly set up your
measurements.
• After memory depth, triggering is the most important aspect of a logic analyzer to consider. On the one hand, powerful
triggering resources and algorithms will allow you to focus on potential problem sources without using up valuable memory.
On the other hand, to be useful, the trigger must be easy to set up.
Other
Measurements
In addition to the measurements made with an analysis probe, consider whether you need to monitor other signals. Be sure to
allow enough channels to make those measurements. For state measurements, the state speed of the analyzer must be at least
as high as the clock speed of your circuit. You may want to test the margin in your circuit by operating it at higher than the
nominal clock speed to determine if the analyzer has sufficient clock speed. For timing measurements, the timing analyzer rate
should be from 2-10X the clock speed of your target.
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Data Acquisition and Stimulus
State/Timing Modules
Multichannel
Eye measurements
Eye scan allows you to make eye diagram measurements, quickly and easily,
on hundreds of channels simultaneously (16760A only)
Key Features of Agilent’s
State/Timing Modules
Triggering for the
most elusive
problems
VisiTrigger combines powerful trigger functionality with a user interface
that is easy to understand and use. Capturing complex sequences of
events is as simple as pointing to the function you want to use and filling in
the blanks to customize it to your specific situation.
• Memory depth up to 128M
samples at a price to meet your
budget
• State analysis up to 1.5 Gb/s
• Timing analysis up to 2 GHz
• VisiTrigger combines powerful
functionality with an intuitive
user interface
Reliable
Eye finder automatically adjusts the setup and hold on every channel,
eliminating the need for manual adjustment and ensuring the highest
confidence in accurate state measurements on high-speed buses.
measurements
on high-speed
buses
• Timing Zoom 2-GHz timing on
all channels
• Eye finder for automatic setup
and hold on all channels
High-speed
timing on
all channels
Timing Zoom provides the data acquisition speed you need for high-speed
microprocessors and buses.
Choose the Logic Analyzer and Measurement Modules that Best Fit Your Application
State/Timing General-
8/16 Bit
processor
debug
32/64 Bit
processor
debug or
channel
intensive
systems
High-
speed
bus
Timing
margin
analysis or
characterize
setup/hold
Deep trace
capture
with timing
or state
High-
speed
computer
debug
Analysis of
Modules
purpose
hardware
debug
data intensive
systems and
performance
analysis
analysis
16710A
16711A
16712A
16715A
16716A
16717A
16740A
16741A
16742A
16750A
16751A
16752A
16760A
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
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√
√
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√
√
√
√
√
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√
√
√
√
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√
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√
√
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√
√
A variety of measurement modules allow you to select the optimum combination of performance, features, and price to meet your specific needs now and in the future.
19
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Data Acquisition and Stimulus
State/Timing Modules
Improve Your Productivity with an
Intuitive User Interface
Agilent Technologies has made the
user interface easy to understand
and use. Now you can spend more
time making measurements and less
time setting up the logic analyzer.
Timing Zoom provides 2 GSa/s timing
analysis simultaneous with state or
conventional timing analysis on all
channels. Sampling rate and position
relative to trigger are adjustable
(16716A, 16717A, 16740A, 16741A
16742A, 16750A, 16751A, and
16752A only).
Format allows you to
group signals into buses.
Trigger defines what
data is acquired.
Sampling defines how the logic
analyzer will acquire the data.
Measurement configuration and
data files can be loaded directly into
the logic analyzer
Menu tabs provide a logical
progression through the setup of
your measurement.
State and timing mode selections
specify how data is sampled.
Single location for access to all state
acquisition options.
Convenient color coding helps you
identify the signals in the interface
with the physical connection to your
device under test.
Figure 4.1. Setting up your logic analyzer has never been this easy.
Clocking for state measurements
can be quickly defined using the
clock setup menu.
20
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Data Acquisition and Stimulus
State/Timing Modules
Features and Applications
VisiTrigger Quickly Locates
Your Most Elusive Problems
VisiTrigger
• Use graphical views and sentence-like structures to help you
define a trace event.
VisiTrigger technology is a break-
through in logic analysis usability. It
combines increased trigger function-
ality with a user interface that is easy
to understand and use. Now with
VisiTrigger, capturing complex events
is as simple as pointing to the trigger
function and filling-in-the-blanks.
(available in the 16715A,
16716A, 16717A, 16740A,
16741A, 16742A, 16750A
16751A, 16752A, and
16760A state/timing
modules)
• Select trigger functions as individual trigger conditions or as
building blocks to easily customize a trigger for your specific task.
• Set global counters to count events such as the number of times a
function executes, or the number of accesses to an l/O port.
• Set, clear or evaluate flags by any module in the frame. Flags allow
you to set up a trigger that is dependent on activity from more than
one bus in the system.
• Specify four-way arbitrary IF/THEN/ELSE branching.
Examples of Problems that Can be Captured Easily with VisiTrigger
Description
Typical Applications
Graphic
Min width
Max width
Pulse too narrow or too wide
•
•
•
Line hangs at wrong level (high or low).
Asynchronous input (for example, an interrupt) persists too long.
Strobe width is too narrow or too wide.
OR
Pulse too narrow
edge 1
Pulse too wide
Time between two edges is
longer than specified
•
•
Excessive delay in responding to a bus grant request.
Excessive delay in responding to a data valid with a data
acknowledged.
edge 2
time
pattern
time
Pattern lasts longer than a
specified time
•
A bus hangs up at a given value.
Pattern two exists within a
specified time after pattern
one is detected
•
•
An incorrect response to a read or write.
An incorrect output from a FIFO or bridge.
pattern 1
time
pattern 2
A pattern exists for less
than a specified time
•
A driver is not holding a bus value long enough for a receiver to
respond.
pattern
time
21
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Data Acquisition and Stimulus
State/Timing Modules
View current information on the state of
the timers, counters, flags, and the trigger
sequence level.
Save and recall up to ten of your
custom trigger setups without loading
a new configuration file.
VisiTrigger
Your most commonly used triggers are
just a mouse click away with the built-in
trigger functions. VisiTrigger’s graphical
representation shows you how the
trigger condition will be defined. You can
use trigger functions as building blocks
to easily customize a trigger for your
specific task.
Sequence levels allow you to develop a
sequence of analyzer instructions to
specify a trigger point or to qualify data
and store only the information that
interests you. Each step in the sequence
contains an "IF/THEN/ELSE" structure
that can evaluate up to four logic
events. Each event can specify a
combination of actions such as: store
sample, increment counters, reset
timers, trigger, or go to another step
in the sequence level.
Ranges provide a way to monitor
program and data accesses within a
specified area in memory.
Global counters can count events such
as the number of times a function
executes or accesses an I/O port.
Timers can be set up to evaluate when
one event happens too late or too soon
with respect to another event.
In timing mode, edge terms let you
trigger on a rising edge, falling edge,
either edge, or a glitch.
Flags can be set, cleared and evaluated by
any 16715A/16A/17A/40A/41A/42A/50A/
51A/52A/60A module in the frame. This
allows you to set up a trigger that is depend-
ent on activity from more than one bus in the
system.
Values can be easily entered directly into
the trigger description.
Patterns and their logical combinations
let you identify which states to store,
when to branch and when to trigger.
Figure 4.2. Set up your trigger in terms of the measurements you want to make.
22
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Data Acquisition and Stimulus
State/Timing Modules
Features and Applications
2 GHz Timing Zoom Provides High-
Speed Timing Analysis Across All
Channels, All the Time
Timing Zoom
• Simultaneously acquire up to 16K of data at 2 GHz timing and
400 MHz state across all channels, all the time, through the same
connection
• Vary the Timing Zoom sample rate from 250 MHz to 2 GHz
• Vary the placement of Timing Zoom data around the trigger point
• Efficiently characterize hardware with 500 ps resolution
(available in the 16716A,
16717A, 16740A, 16741A,
16742A, 16750A, 16751A
and 16752A state/timing
modules)
When you're pushing the speed
envelope, you may run into elusive
hardware problems. Capturing
glitches and verifying that your
design meets critical setup/hold
times can be difficult without the
proper tools. With Timing Zoom you
have access to the industry's most
powerful tool for high-speed
digital debug.
Now it’s easy to capture simultaneous
2 GHz timing and high-speed state
information through a single connection.
Use the global
markers to
time-correlate
events across
multiple displays.
Timing Zoom labels are automatically
created and marked with an _TZ extension.
Figure 4.3. Verifying critical edge timing in your system is easy with Agilent Technologies' 2 GHz Timing Zoom technology.
23
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Data Acquisition and Stimulus
State/Timing Modules
It takes less than a minute to run
Eye Finder
eye finder. No special setup or
additional equipment is required.
You only need to run eye finder
once, when the logic analyzer is set
up and connected to the target.
Agilent’s eye finder examines the
signals coming from the circuit under
test and automatically adjusts the
logic analyzer’s setup and hold
window on each channel. Eye finder,
combined with 100 ps adjustment
resolution (10 ps on 16760A) on
Agilent’s logic analyzer modules,
yields the highest confidence in
accurate state measurements on
high-speed buses.
Gray shading indicates
regions where
transitions are detected.
Blue bars indicate
the sampling point
selected by eye finder.
Figure 4.4. The eye finder display.
The eye finder display shows:
Times in the eye finder display are
referenced to the incoming clock
transitions. The center of the display
(labeled "0 ns") corresponds to the
clock transitions.
• Regions of transitions that were
discovered on all channels
selected
• The sampling point selected by eye
finder
If you want to select a different
sample point on any individual
channel, just drag and drop the blue
"sample" bar at the desired point.
24
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Data Acquisition and Stimulus
State/Timing Modules
Eye Finder as an Analytical Tool
Eye finder is very useful as a first-
pass screening test for data valid
windows. Because eye finder quickly
examines all channels, it is
considerably faster than examining
each channel with an oscilloscope.
After running eye finder, you may
want to use an oscilloscope to
examine only those signals that are
close to your desired specifications
for setup and hold.
Examples of When to Run Eye Finder
You should use eye finder in the
following situations:
Probing a new target, or probing
different signals in the same target
• Because eye finder examines the
actual signals in the circuit under
test, you should run it whenever
you probe a different bus or a
different target.
Significant change of target
temperature
Eye finder also can quickly provide
useful diagnostic or troubleshooting
information. If a channel has an
unexpectedly small data valid
window, or an anomalous offset
relative to clock, this could be an
indication of a problem, or could be
used to validate the cause of an
intermittent timing problem.
• The propagation delays and signal
levels in your target system may
vary with temperature. If, for
example, you place your target
system in a controlled tempera-
ture chamber to evaluate its oper-
ation over a range of temperatures
or to trouble-shoot a problem that
only occurs at high or low temper-
atures, you should run eye finder
after the target system stabilizes
at the new ambient temperature.
Differences in the position of the
stable region from one signal to
another on a bus indicate skew. An
indication of excessive skew on eye
finder can help isolate which
channels you want to check with an
oscilloscope, or with the Timing
Zoom 2 GHz timing analysis mode
in your logic analyzer.
When Do You Need Eye Finder?
Eye finder becomes critical when
the data valid window is <2.5 ns. If
you’re unsure where your clock edge
is relative to the data valid window,
you can run eye finder for maximum
confidence. If the clock in your
system runs at 100 MHz or slower,
and the clock transitions are approxi-
mately centered in the data valid
window, you may not see any transi-
tion zones indicated in the eye finder
display. This is because eye finder
only examines a time span of 10 ns
(16760A: 6 ns) centered about the
clock.
25
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Data Acquisition and Stimulus
State/Timing Modules
Features Supported in Agilent State and Timing Analysis Modules
Agilent Module Number
16710A, 16711A,
16712A
16715A
16716A, 16717A,
16740A, 16741A,
16742A, 16750A
16751A, 16752A
16760A
Eye finder
√
√
√
√
√
√
√
√
Visitrigger
Timing Zoom
Transitional timing
Context Store
Eye Scan
√
√
√
√
√
26
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Data Acquisition and Stimulus
State/Timing Modules
As state speeds go up, the data valid
• Differential signals
Agilent 16760A: Extending Logic
Analysis to New Realms
window shrinks. To make reliable
measurements, a logic analyzer’s
combined setup and hold window
must be smaller than the data valid
window of the signals it is acquiring.
Agilent’s 16760A has a combined
setup and hold time of 500 ps to
match the data valid window of
very high-speed buses.
Many high-speed designs use differen-
tial signaling to minimize simultane-
ous switching noise and to provide
immunity to crosstalk and noise. The
Agilent 16760A has differential inputs
to allow you to acquire differential
signals with complete confidence.
Single-ended probes are also available.
• Differential inputs (single-ended
probes also available).
• State analysis up to 1.5 Gb/s.
• Setup-and-hold time of 500 ps.
• Input signal amplitude as low as
200 mV p-p.
Logic analysis at state speeds up to
1.5 Gb/s imposes a stringent set of
criteria for a logic analyzer.
Agilent helps you get started in the
design stage.
To position the analyzer’s setup-and-
hold window inside the data valid
window requires very fine adjust-
ment resolution. The 16760A gives
you the ability to position the setup-
and-hold window with 10 ps resolu-
tion.
To probe high-speed signals with a
logic analyzer, you need to design the
probe in when you are designing your
PC board. The following document
from Agilent will help you design your
system to take maximum advantage
of the capabilities of the 16760A logic
analyzer:
• Probing
Agilent’s 16760A uses an innovative
probing system with only 1.5 pF of
probe tip capacitance, including the
connector. The connector is a joint
design between Agilent and Samtec,
optimized especially for logic analysis
measurements.
• Small-amplitude signals
Many high-speed designs use small
signal amplitudes to limit slew rates
and reduce power. Agilent’s 16760A
can make reliable measurements on
signals as small as 200 mV p-p.
• Logic signal standards supported
Ground pins located between every
pair of signal pins provide excellent
channel-to-channel isolation at high
speeds.
TTL
LVTTL
HSTL Class I & II HSTL CLass III & IV
SSTL2
SSTL3
AGP-2X
LVCMOS 1.8V
LVCMOS3.3V
ECL
LVCMOS 1.5V
LVCMOS 2.5V
CMOS 5V
• Setup and hold
LVPECL
PECL
User defined from -3V to +5V in 10mV
increments
Publication Title
Description
Publication Number
User’s Guide, Agilent Technologies E5378A, E5379A, and
E5380A Probes for the 16760A Logic Analyzer
Mechanical drawings, electrical models,
general information on probes for the 16760A
16760-97007
Designing High-Speed Digital Systems for
Logic Analyzer Probing
Guidelines and design examples for designing
logic analyzers probing into your target system
5988-2989EN
27
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Data Acquisition and Stimulus
State/Timing Modules
Eye scan
In the eye scan mode, the Agilent
16760A scans all incoming signals for
activity in a time range centered on
the clock and over the entire voltage
range of the signal. The results are
displayed in a graph similar to an eye
diagram as seen on an oscilloscope.
As timing and voltage margins
continue to shrink, confidence in
signal integrity becomes an
increasingly vital requirement of the
design verification process. Eye scan
lets you acquire comprehensive signal
integrity information on all the buses
in your design, under a wide variety
of operating conditions, in minimum
time.
Qualified eye scan
In the qualified eye scan mode, a
single qualifier input defines what
clock cycles are to be acquired and
what cycles are to be ignored in the
eye scan acquisition. For example,
you may wish to examine the eye
diagram for read cycles only,
ignoring write cycles.
Slope
Results can be viewed for each
individual channel. A composite
display of multiple channels and/or
multiple labels is also available.
Individual channels can be highlight-
ed in the composite view
The slope tool indicates DV/DT
between two manually - positions
cursors.
Eye scan allows the user to set the
following variables:
• The number of clock cycles to be
evaluated at each time and voltage
region
• The display mode
• Color graded
Cursors
Eye scan data can be stored and
recalled for later comparison or
analysis.
Two manually positioned cursors are
available. The readout indicates the
time and voltage coordinates of each
cursor.
• Intensity shaded
• Solid color
• Aspect ratio of the display
• Time/division
• Time offset
• Volts/division
Eye limit
The eye limit tool is a single point
cursor that can be positioned manu-
ally. The readout indicates the inner
eye limits detected at the time and
voltage coordinates of the cursor.
• Voltage offset
Histogram
• Time resolution of measurement
• Voltage resolution of
measurement
The histogram tool indicates the rela-
tive number of transitions along a
selected line. The time range and
voltage levels of the histogram are
selected by manually positioning a
pair of cursors. The cursors indicate
the voltage level and the beginning
and end times of the histogram.
Polygon
A 4-point or 6-point polygon can be
defined manually.
28
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Data Acquisition and Stimulus
State/Timing Modules
Probes are not supplied as part of the
Probing solutions to match the
measurement capabilities
standard 16760A. Probes must be
ordered separately, either as options
to the 16760A or individually by their
respective model numbers.
Three probing options are available
for the Agilent 16760A. Each probe
can be ordered by its individual
model number or as an option to the
16760A. The following table indicates
both the model number and the
option number.
Agilent Model Number
16760A Option Number
Description
Notes
E5378A
010
100-pin single-ended probe
Requires a kit of mating connectors and shrouds
(see the next table) to connect to target system.
E5379A
E5380A
E5382A
011
012
013
100-pin differential probe
Two E5379A (or two option 011 on the 16760A) are
required to support all 34 channels on a 16760A.
Requires a kit of mating connectors and shrouds
(see the next table) to connect to target system.
38-pin single-ended probe, compatible
with target systems designed for the
Agilent E5346A Mictor adapter cable
Maximum state analysis speed is 600 Mb/s.
Minimum input amplitude is 300 mV p-p.
Requires a kit of mating connectors and shrouds
(see the next table) to connect to target system.
17-channel, single-ended flying lead
probe set for the 16760A
Two E5382A are required to support all the channels
of a 16760A.
Connector and shroud kits for probes for the 16760A logic analyzer
For probe model number
For PC board thickness
Probing connector kit part number
(each contains 5 mating connectors and 5 support shrouds)
E5378A
Up to 1.57 mm (0.062")
Up to 3.05 mm (0.120")
16760-68702
16760-68703
E5379A
Up to 1.57 mm (0.062")
Up to 3.05 mm (0.120")
16760-68702
16760-68703
E5380A
Up to 1.57 mm (0.062")
Up to 3.18 mm (0.125")
E5346-68701
E5346-68700
29
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Data Acquisition and Stimulus
Oscilloscope Modules
When integrated into the 16700
Series logic analysis systems, the
oscilloscope modules make powerful
measurement and analysis more
accessible, so you can find the
answers to tough debugging problems
in less time. Oscilloscope controls are
easy to find and use.
For example, using a state analyzer
you may observe a failed bus cycle. A
timing problem caused by a reflection
on an incorrectly terminated line
may be causing the bus cycle to fail.
By triggering an oscilloscope from the
state analyzer, you can quickly identi-
fy the cause. The ability to cross-trig-
ger and time-correlate state, timing,
and analog measurements can help
you in solving these tough problems.
Multiple Views of Target Behavior
Isolate Problems Quicker
Frequently a problem is detected in
one measurement domain, while the
clues to the cause of the problem are
found in another. That’s why the abil-
ity to view your prototype's behavior
from all angles simultaneously—from
software execution to analog signals—
is essential for quickly gaining insight
into problems.
Scope controls
and waveform
display are inte-
grated into a
single window,
making interac-
tive adjustment
easy.
Trigger icon
indicates trigger
level, making it
easy for you to
adjust trigger
level.
Ground icon
always shows
you where ground
is relative
Time and voltage
markers allow you
to measure signal
details precisely.
to signal.
Figure 4.5. All primary oscilloscope control settings, including scale factors and trigger settings, are visible
simultaneously.
30
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Data Acquisition and Stimulus
Oscilloscope Modules
The global time markers of the 16700
Series logic analysis systems let you
correlate state, timing, and oscillo-
scope measurements to track prob-
lems across multiple measurement
domains.
Automatic Measurements Quickly
Characterize Signals
The Agilent Technologies 16534A
oscilloscope modules quickly charac-
terize signals with automatic meas-
urements of rise time, voltage, pulse
width, and frequency.
Markers Easily Set Up Timing and
Voltage Margin Measurements
Four independent voltage markers
and two local time markers are avail-
able to quickly set up measurements
of voltage and timing margins.
Automatic measurements
save time in characterizing
signal parameters.
Figure 4.6. Automatic measurements and markers let you make faster analysis.
31
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Data Acquisition and Stimulus
Oscilloscope Modules
More Channels When You Need Them
You can combine up to four 16534A
oscilloscope modules to provide up
to eight channels on a single time
base. When you operate in this
mode, you can use the master module
for triggering.
External trigger input and output are
used to connect up to four oscilloscope
modules, providing up to eight channels
on a single time base.
Calibrator output used
for operational accuracy
calibration
Probe power output provides power
for 1145A dual active probe or two
1141A active probes
Channel 1 input
Channel 2 input
!
CHAN 1 &
2
16534A
IN
ECL EXT
TRIG
OUT
CHAN
1
CHAN
1MW = 7pF
2
GSa /
s
250V MAX OR
2
50W 5Vrms MAX
OSCILLOSCOPE
!
SN US35021924
16534A
!
! PROBE POWER
MADE IN THE USA
AC/DC CAL
Figure 4.7. Connector panel of the 16534A oscilloscope module.
32
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Data Acquisition and Stimulus
Pattern Generation Modules
Digital Stimulus and Response in a
Single Instrument
Parallel Testing of Subsystems
Reduces Time to Market
Configure the logic analysis system to
provide both stimulus and response
in a single instrument. For example,
the pattern generator can simulate a
circuit initialization sequence and
then signal the state or timing analyz-
er to begin measurements. Use the
compare mode on the state analyzer
to determine if the circuit or subsys-
tem is functioning as expected. An
oscilloscope module can help locate
the source of timing problems or
troubleshoot signal problems due to
noise, ringing, overshoot, crosstalk,
or simultaneous switching.
By testing system subcomponents
before they are complete, you can fix
problems earlier in the development
process. Use the Agilent 16720A as a
substitute for missing boards,
integrated circuits (ICs), or buses
instead of waiting for the missing
pieces. Software engineers can create
infrequently encountered test
conditions and verify that their code
works—before complete hardware is
available. Hardware engineers can
generate the patterns necessary to
put their circuit in the desired state,
operate the circuit at full speed or
step the circuit through a series
of states.
Key Characteristics
Agilent Model 16720A
Maximum clock (full/half channel)
Number of data channels (full/half channel)
Memory depth (full/half channels)
180/300 MHz
48/24 Channels
8/16 MVectors
240/120 Bits
Maximum vector width
(5 module system, full/half channel)
Logic levels supported
TTL, 3-state TTL, 3.3V, 1.8V, 3-state CMOS, ECL,
5V PECL, 3.3V LVPECL, LVDS
Maximum binary vector set size
Editable ASCII vector set size
16 MVectors (24 channels)
1 MVectors
33
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Data Acquisition and Stimulus
Pattern Generation Modules
Vectors Up To 240 Bits Wide
Vectors are defined as a "row" of
labeled data values, with each data
value from one to 32 bits wide. Each
vector is output on the rising edge of
the clock.
Depth Up to 16 MVectors
With the 16720A pattern generator,
you can load and run up to
16 MVectors of stimulus. Depth on
this scale is most useful when cou-
pled with powerful stimulus
generated by electronic design
automation tools, such as
SynaptiCAD's WaveFormer and
VeriLogger. These tools create
stimulus using a combination of
graphically drawn signals, timing
parameters that constrain edges,
clock signals, and temporal and
Boolean equations for describing
complex signal behavior. The
stimulus also can be created from
design simulation waveforms. To take
advantage of the full depth of the
16720A pattern generator, data must
be loaded into the module in the
Pattern Generator Binary (.PGB) for-
mat. The SynaptiCAD tools allow you
to convert .VCD files into .PGB files
directly, offering you an integrated
solution that saves you time.
Initialize (INIT) Block for
Repetitive Runs
When running repetitively, the vec-
tors in the initialize (init) sequence
are output only once, while the main
sequence is output as a continually
repeating sequence. This "init"
sequence is very useful when the
circuit or subsystem needs to be
initialized. The repetitive run capabil-
ity is especially helpful when operat-
ing the stimulus module independent
of the other modules in the logic
analysis system.
Up to five, 48-channel 16720A mod-
ules can be interconnected within a
16700 Series mainframe or expansion
frame. This configuration supports
vectors of any width up to 240 bits
with excellent channel-to-channel
skew characteristics (see specific
data pod characteristics in Pattern
Generation Modules Specifications
starting on page 105). The modules
operate as one time-base with one
master clock pod. Multiple modules
also can be configured to operate
independently with individual clocks
controlling each module.
"Signal IMB" Coordinates System
Module Activity
A "Signal IMB" (intermodule bus)
instruction acts as a trigger arming
event for other logic analysis modules
to begin measurements. IMB setup
and trigger setup of the other logic
analysis modules determine the
action initiated by "Signal IMB".
"Wait" for Input Pattern
The clock pod also accepts a 3-bit
input pattern. These inputs are level-
sensed so that any number of "Wait"
instructions can be inserted into a
stimulus program. Up to four pattern
conditions can be defined from the
OR-ing of the eight possible 3-bit
input patterns. A "Wait" also can be
defined to wait for an intermodule
bus event. This intermodule bus
event signal can come from any other
module in the logic analysis system.
Synchronized Clock Output
You can output data synchronized to
either an internal or external clock.
The external clock is input via a clock
pod, and has no minimum frequency
(other than a 2 ns minimum high
time).
The internal clock is selectable
between 1 MHz and 300 MHz in
1 MHz steps. A Clock Out signal is
available from the clock pod and can
be used as an edge strobe with a
variable delay of up to 8 ns.
34
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Data Acquisition and Stimulus
Pattern Generation Modules
Figure 4.8. Stimulus vectors are defined in the
Sequence menu tab. In this example, vector output
halts until the WAIT UNTIL condition is satisfied.
Figure 4.9. To fill the 16720A pattern generator's 8 MVector
deep memory (16 MVector in half channel mode) with data,
the stimulus must be in 'pattern generator binary' format.
Stimulus files in .PGB format can be loaded directly from
the user interface.
35
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Data Acquisition and Stimulus
Pattern Generation Modules
"User Macro" and "Loop" Simplify
Creation of Stimulus Programs
ASCII Input File Format: Your Design
Tool Connection
Direct Connection to Your Target
System
User macros permit you to define a
pattern sequence once, then insert
the macro by name wherever it is
needed. Passing parameters to the
macro will allow you to create a more
generic macro. For each call to the
macro you can specify unique values
for the parameters. Each macro can
have up to 10 parameters. Up to 100
different macros can be defined for
use in a single stimulus program.
The 16720A supports an ASCII file
format to facilitate connectivity to
other tools in your design environ-
ment. Because the ASCII format does
not support the instructions listed
earlier, they cannot be edited into the
ASCII file. User macros and loops
also are not supported, so the vectors
need to be fully expanded in the
ASCII file. Many design tools will
generate ASCII files and output the
vectors in this linear sequence. Data
must be in Hex format, and each label
must represent a set of contiguous
output channels. Data in this ASCII
format is limited to 1 MVectors in
the 16720A.
The pattern generator pods can be
directly connected to a standard
connector on your target system. Use
a 3M brand #2520 Series, or similar
connector. The 16720A clock or data
pods will plug right in. Short, flat
cable jumpers can be used if the
clearance around the connector is
limited. Use a 3M #3365/20, or equiv-
alent, ribbon cable; a 3M #4620
Series, or equivalent, connector on
the 16720A pod end of the cable; and
a 3M #3421 Series, or equivalent,
connector at your target system end
of the cable.
Loops enable you to repeat a defined
block of vectors for a specified
number of times. The repeat counter
can be any value from 1 to 20,000.
Loops and macros can be nested,
except that a macro can not be nested
within another macro. When nested,
each invocation of a loop or a macro
is counted towards the 1,000 invoca-
tion limit. At compile time, loops and
macros are expanded in memory to a
linear sequence.
Probing Accessories
The probe tips of the Agilent 10474A,
10347A, and 10498A lead sets plug
directly into any 0.1 inch grid with
0.026 inch to 0.033 inch diameter
round pins or 0.025 inch square pins.
These probe tips work with the
Agilent 5090-4356 surface mount
grabbers and with the Agilent
5959-0288 through-hole grabbers.
Other compatible probing accessories
are listed in ordering information on
page 121.
Configuration
The 16720A pattern generators
require a single slot in a logic
analysis system frame. The pattern
generator operates with the clock
pods, data pods, and lead sets
described later in this section. At
least one clock pod and one data pod
must be selected to configure a func-
tional system. Users can select from a
variety of pods to provide the signal
source needed for their logic devices.
The data pods, clock pods and data
cables use standard connectors. The
electrical characteristics of the data
cables also are described for users
with specialized applications who
want to avoid the use of a data pod.
The 16720A can be configured in
systems with up to five cards for a
total of 240 channels of stimulus.
Convenient Data Entry and Editing
Feature
You can conveniently enter patterns
in hex, octal, binary, decimal, and
two's complement bases. The data
associated with an individual label
can be viewed with multiple radixes
to simplify data entry. Delete, Insert,
Copy, and Merge commands are
provided for easy editing. Fast and
convenient Pattern Fills give the
programmer useful test patterns with
a few key strokes. Fixed, Count,
Rotate, Toggle, and Random are
available to quickly create a test
pattern, such as "walking ones".
Pattern parameters, such as Step
Size and Repeat Frequency, can be
specified in the pattern setup.
36
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Data Acquisition and Stimulus
Emulation Modules
Speed Problem Solving With
Off-the-Shelf Solutions for Many
Common Microprocessors
To help you design and debug your
microprocessor-based target systems,
Agilent offers different microproces-
sor specific products that let you get
control and visibility over your
microprocessor’s internal and
external data.
An analysis probe allows you to
quickly connect an Agilent logic
analyzer to your target system. The
analysis probe provides non-intrusive
capture and disassembly of micro-
processor and bus activity
Analysis probes are available for over
200 microprocessors and microcon-
trollers. Bus probes allow probing of
popular bus architectures such as
PCI, AGP, USB, VXI, SCSI, and many
others.
Figure 4.10. Agilent analysis probes make it easy to connect a logic analyzer to your target system.
Flexible physical probing schemes
give quick and reliable connections to
almost any device on your prototype.
On-Chip Emulation Tools Make Fixing
Bugs Easier
For specific microprocessor families
that feature on-chip emulation, you
can add a processor emulation
module to your system to connect
the on-board debugging resources
of the microprocessor to the logic
analysis system.
The microprocessor’s BDM or JTAG
technology provides control over
processor operation even if there is
no software monitor on the target
system. This feature is particularly
helpful during the development of
your target system’s boot code.
37
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Data Acquisition and Stimulus
Emulation Modules
Emulation Control Interface
The emulation control interface is
accessed from the power up screen of
the Agilent 16700 Series system. The
interface is included with the Agilent
E5901A/B emulation modules.
Designed for hardware engineers,
this graphical user interface provides
the following features:
• Control over processor execution:
run/break/reset/step.
• Register display/modification.
• Memory display/modification in
various formats including disas-
sembly for code visualization.
Memory modification or memory
block fill can be done to check
processor memory access or to
reinitialize memory areas.
• Multiple breakpoint configuration:
hardware, software, and processor
internal breakpoint registers.
• Code download to the target.
• Command scripts to reproduce
test sequences.
• The ability to trigger a measure-
ment module on a processor break
or to receive a trigger from the
logic analysis system’s measure-
ment modules.
Integrated Debugger Support
When the hardware turn-on phase is
completed, the same Agilent emula-
tion module can be connected to
high-level debuggers for C or C++
software development.
Figure 4.11. Emulation control interface.
You can achieve the functionality of
a full-featured emulator by using a
third-party debugger to drive the
installed Agilent emulation module.
This gives you complete microproces-
sor execution control (run control).
38
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Post-Processing and Analysis Tool Sets
Software Tool Sets
Once the data is acquired, you can
rely on the post-processing tools to
rapidly consolidate data into displays
that provide insight into your sys-
tem's behavior. The tool sets
described in the following pages are
optional, post-processing software
packages for the 16700 Series logic
analysis systems.
Selecting the Right Tool Set
Take a look at the tool set descrip-
tions below to see if they meet your
needs. If you don't immediately see
what you need there is also the
option of writing your own analysis
application using the tool develop-
ment kit. Best of all, you can try out
any one of these tool sets with no
obligation to buy.
Application
Product Name
Model Number
Detailed Information
Debug your real-time code at the source level
Source Correlation
B4620B
Page 40
Correlate a logic analyzer trace with the high-level source
code that produced it. Set up the logic analyzer trace by
simply pointing and clicking on a line of source code.
Tool Set
Debug your parallel data communication buses
Display logic analyzer trace information at a protocol level.
Powerful trigger macros allow triggering on standard or
custom protocol fields. Data bus width is limited only by
the number of available channels.
Data Communications
Tool Set
B4640B
Page 44
Optimize your target system's performance
Profile your target system's performance to identify system
bottlenecks and to identify areas needing optimization.
System Performance
Analysis Tool Set
B4600B
B4601B
Page 53
Page 60
Solve your serial communication problems
Serial Analysis
Tool Set
Convert serial bit streams to parallel format for easy viewing
and analysis. Supports serial data with or without an external
clock reference and protocols that use bit stuffing to maintain
clock synchronization. Works at speeds up to 1 GHz.
Customize your trace for greater insight
Tool Development
Kit
B4605B
Page 66
Create custom tools using the C programming language.
Custom tools can analyze captured data and present it in
a form that makes sense to you. Analysis systems do not
require the tool development kit to run generated tools.
39
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Post-Processing and Analysis Tool Sets
Software Tool Sets
Free Tool Set Evaluation
To see which tool sets best fit your
needs, Agilent Technologies offers a
free 21-day trial period that lets you
evaluate any tool set as your work
schedule permits. Once you receive
your tool, you obtain a password that
temporarily enables the tool.
Figure 5.1. For a free, one-time, 21-day trial of any tool set, simply type “demo” in the password field for the product
you want to evaluate.
40
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Post-Processing and Analysis Tool Sets
Source Correlation
• What is the exact time between
two user-defined system events?
• What is the execution history
Product Description
Debug Your Source Code
The tool set's main advantage is its
ability to allow you to observe soft-
ware execution without halting the
system or adding instructions to the
code. The tool set uses information
provided in your compiler's object file
to build a database of source files,
line numbers and symbol information
to reference to logic analyzer traces.
The tool set can also be used to set up
the logic analyzer trace by simply
pointing and clicking on a source
line.
The Agilent B4620B source correla-
tion tool set correlates a microproces-
leading up to or occurring after an
sor execution trace window with a
area of interest?
corresponding high-level source code
window. The source correlation tool
set enhances your software develop-
ment environment by providing mul-
Data Tracking
• What is the exact history of a
variable's value over time?
tiple views of code execution and
• Which routine(s) corrupted the
variable content under severe real-
data?
time constraints.
Software-Hardware Integration
• What is the root cause of a system
Using the B4620B you can obtain
answers to many of your questions
failure—hardware or software?
• Are timing anomalies found by the
hardware engineer the cause of
software problems?
• Is the software engineer working
on the same problem as the hard-
ware engineer?
concerning software code execution,
data tracking, and software-hardware
integration.
Once the tool set is enabled on your
16700 Series system, you can support
new processors by changing analysis
probes and verifying object file com-
patibility. Multiple-processor systems
are also supported.
Obtain Answers to the Following
Questions:
• What portion of the source code
correlates to the problem the
hardware engineer reported?
Software Code Execution
• What happened just before the
target system crashed?
• What source code was executed at
a specific point in time?
Your Development Environment
Source
Analyzer
Trace
Compile
Relocatable
Object Code
Link
Absolute
Object Code
Symbol File
Download
Edit
Source File
Debug
Figure 5.2. The source correlation tool set allows you to observe software execution without halting the system or
adding instructions to the code.
41
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Post-Processing and Analysis Tool Sets
Source Correlation
When You Want
to Trace . . .
...on a variable to see what caused data
corruption.
...on a function to determine where it is being
called from in order to understand the context
of a system error.
...on a line number to determine if a
specific code segment is ever executed.
Simply Click . . .
... to trace about a variable, function, or
line number.
... to halt processor execution with an
integrated emulation module when the trace
event occurs.
...to use text search to quickly navigate
through hundreds of symbols. To recall
previous entries when rotating through debug
tests.
...to specify alignment conditions for
processors that don’t include lower address
bits on the bus. This is necessary if your
processor uses bursting or byte enables when
fetching instructions.
...to use address offsets for code that is
dynamically loaded or moved from ROM to
RAM during a boot-up sequence.
Figure 5.3.
42
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Post-Processing and Analysis Tool Sets
Source Correlation
Once You Acquire
the Trace . . .
...“step” through the
trace at the source-
code level or the
assembly level.
Locate the cause of a
problem by “stepping
backward” from the
point where you see
a problem to its root
cause.
...quickly locate a
specific function,
variable, or text
string. The system
maintains a history
of previous text
searches for quick
recall.
...click the source line
which you want to
trace about on your
next acquisition.
...set the data type to
“Symbols” to view
file and symbol
names or ”line #s” to
view file name and
line number.
...filter out unexe-
cuted code fetches
from the inverse
assembled trace to
view executed code
only, using Agilent’s
advanced inverse
assembly filtering for
popular processors.
...scroll or step through
the time-correlated
source code (left) or
inverse assembled trace
listing (right)
Also...
Analyze a function’s behavior without viewing
calls to subroutines or interrupts by using the
analyzer’s filtering capabilities to focus on a
specific part of the executed software.
Figure 5.4.
43
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Post-Processing and Analysis Tool Sets
Source Correlation
You can load multiple object files.
Address offsets are also supported,
enabling system performance meas-
Source File Access
Product Characteristics
The source correlation tool set must
be able to access source files to pro-
vide source line referencing.
Data Sources
All state and timing measurement
urements and source-code level views
of dynamically loaded software exe-
Source files can reside in multiple
directories on the hard drive of your
workstation, PC, or on the 16700
Series mainframe's internal hard
disk. You can access the files via NFS-
mounted disks or CIFS mounted
disks. To display the source file, the
tool set first looks for the source path
name in the object file, follows the
path to access the source file and, if
not found, looks for the source file in
alternate user-defined directories.
modules supported by the 16700
cution or code moved from ROM to
Series logic analysis systems (except
RAM during a boot-up sequence.
the 16517A/518A) serve as data
sources for the source correlation
tool set.
High-level language tools that pro-
duce the following file formats are
supported:
Microprocessor Support
The source correlation tool set sup-
• Agilent(HP)/MRI IEEE696
ports many of the most popular
• ELF/DWARF*
embedded microprocessors Non-
• ELF/Stabs*
intrusive analysis probes for the
• TI_COFF
16700 Series systems provide reli-
• COFF/Stabs*
able, fast and convenient connections
• Intel OMF86
The 16700 Series logic analysis
systems automatically place the
following in the directory search
path:
to your target system.
• Intel OMF96
• Intel OMF 286
New microprocessors are constantly
• Intel OMF 386 (which supports
being added to the list of supported
Intel80486 and Pentium Language)
CPUs. For the most current informa-
tion about supported microproces-
sors, please contact your Agilent
Technologies sales representative or
• NFS mounted directories
• Directory paths specified in
loaded symbol files
• Directory paths specified in
loaded source files
*Supports C++ name de-mangling
If your language system does not gen-
visit our web site: http://www.agilent.
erate output in one of the listed for-
com/find/ logic analyzer.
mats, a generic ASCII file format is
also supported.
Source Correlation Functionality
Object File Format Compatibility
The 16700 Series logic analysis sys-
tems quickly and reliably read your
specific object file format. Agilent
Technologies' extensive experience
with different file formats and sym-
bol representations ensures that your
source code files are accurately cor-
related and your system is precisely
characterized.
For the most current information
about supported compiler file for-
mats and processor support, please
contact your Agilent Technologies
sales representative.
• Source code and inverse
assembled trace listing are time-
correlated.
• User can alternate between source
viewer and browsing of other
source files.
• Trace specification can be set up
from the source viewer or file
browser.
• For multiple-processor systems,
each trace window can be
time-correlated to a source viewer.
Source correlation and system per-
formance measurements do not
require any change in your software
generation process. No modification
or recompilation of your source code
is required.
44
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Post-Processing and Analysis Tool Sets
Data Communications
Monitor Packet Information on
Parallel Data Buses
The powerful protocol trigger macro
allows easy trigger setup by eliminat-
ing the need to manually configure
the trigger sequencer for complex
measurements. All custom-defined
protocol fields or layers are support-
ed in the trigger macro.
The data communications tool set
shows parallel bus data at a protocol
level on the logic analyzer. Developers
have the capability to find complex,
system-level bus interaction problems
in applications such as a switching or
routing system.
All packets or cells are time-stamped
in the logic analyzer for time-correla-
tion measurements with other system
buses, such as a microprocessor,
memory interface, PCI bus, or other
UTOPIA bus. All state listing and
waveform displays in the logic ana-
lyzer are time-correlated with global
markers for a complete view of the
system. With this tool, it is possible
to trigger the logic analyzer with a
microprocessor event and see what is
happening on a parallel data bus with
protocol information.
Obtain Answers to the Following
Questions:
• What is the time difference
between two or more data paths
and/or a microprocessor?
• Did a packet make it through the
switch or router?
• Why did a packet take so long to
go through the switch or router?
• Where did an illegal packet come
from?
• What is the latency on packet
information?
By monitoring multiple time-correlat-
ed data buses, you can monitor a
packet entering one ASIC and see
how long it takes for the packet to
reach another part of the system. The
powerful trigger can also monitor a
packet entering one port and trigger
if the packet has not reached another
port by a designated time.
• What is corrupting packets?
Product Description
The Agilent Technologies B4640B
data communications tool set adds
protocol analysis capabilities to the
logic analyzer for viewing parallel
data buses (e.g, UTOPIA or a propri-
etary data bus) in a switching or
routing system. Each protocol layer is
displayed with a different color in the
logic analyzer lister display to allow
easy viewing of the protocol data.
Payload information is included after
the header in a raw hex format.
Filters are included to allow many
different views of the data. Protocol
layers can be collapsed or expanded
to create a custom view of the data
acquired in the logic analyzer. With
the filters, you can concentrate on
the data of interest for a particular
measurement.
45
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Post-Processing and Analysis Tool Sets
Data Communications
Theory of Operation
Use a logic analyzer to probe the
system’s parallel data buses (e.g.,
UTOPIA).
Custom/UTOPIA
PHY
UTOPIA Level 2
CPU
The analyzer needs access to:
PHY
• Data signals
• Qualifying signals
• Start of cell or packet bit
• Synchronous clock for the bus
ATM
ATM
Layer
Layer
PHY
PHY
Switch
Fabric
The synchronous bus clock samples
data into the logic analyzer.
Qualifiers such as "Data Valid" allow
the logic analyzer to sample only on
PHY
ATM
ATM
Layer
PHY
Layer
PHY
events of interest instead of all
cycles.
With access to the "Start of Cell" or
"Start of Packet" bit on the data bus,
UTOPIA Level 1
the analyzer starts looking at the
Figure 5.5. Typical ATM Switch Design.
beginning of a cell or packet. With the
protocol definition set up by the user,
the logic analyzer can sequence down
into the cell or packet to find the
desired protocol field to trigger on.
46
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Post-Processing and Analysis Tool Sets
Data Communications
Product Characteristics
Additional Information
Requires
16700 Series logic analysis system with
system software version A.01.50.00 or higher
Applications
Trigger on a processor event and see what
is happening on a parallel data bus with
protocol information or vice versa.
Supported Measurement Modules
Protocols Supported
16715A, 16716A, 16717A, 16718A, 16719A,
16750A, 16751A, 16752A
• Ethernet
• ATM
• TCP/IP Stack
• Custom
• Example files for these protocols are provided with the
product. These standard files can be edited to include
any custom protocol "wrapper" layers or fields.
• Custom protocols are supported by entering the protocol
setup information via the logic analyzer interface or a text
file. Custom protocol definitions are used in both the
trigger definition and packet display.
Trigger Macro
All custom-defined protocol fields or layers
are supported in the trigger macro
Maximum Parallel Bus Width
Display Features
Limited only by the number of available channels
• Color
• Each protocol layer is displayed with a different color in
the analyzer’s lister display to allow easy viewing of
protocol data.
• Filters and preferences
• Specific protocol layers and fields can be selected for
viewing in the trace. Provides many different views of the
data. Allows you to concentrate on the data of interest
for a particular measurement.
• Payload information
• Protocol layers
• Included after the header in a raw hex format
• Can be collapsed or expanded to create a custom view of
the acquired data
47
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Post-Processing and Analysis Tool Sets
Data Communications
Edit or create a
protocol using the
logic analyzer
user interface.
Select a known
protocol and add
proprietary fields.
Insert custom
wrapper or
field here.
Insert name, num-
ber of bits and
format for trigger
and
display.
Define any sym-
bols for both
trigger and
display of
packets.
Edit or create a
protocol using a
text file.
Start with stan-
dard protocol
definition and add
custom fields with
text file.
Insert protocol
layer name.
Define protocol
fields, number of
bits, and format
for trigger and
display.
Define any user
symbols to make
triggering and dis-
play easier to use.
Figure 5.6.
48
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Post-Processing and Analysis Tool Sets
Data Communications
New packet
trigger macros.
Choose from a list
of buses.
Trigger on simple
IP address instead
of setting up trig-
ger sequencer.
Specify what
action to perform
once a packet is
found.
Specify protocol
layer to trigger on.
Use any defined
protocol fields as
a trigger, such as
source address,
destination
address, etc.
Physical representation of bit fields to be triggered on.
This window is automatically updated when fields are edited.
Figure 5.7.
49
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Post-Processing and Analysis Tool Sets
Data Communications
Use the bus editor feature to specify
what protocol runs on your bus. This
is helpful when probing more than
one bus with a single state/timing
module.
Figure 5.8.
50
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Post-Processing and Analysis Tool Sets
Data Communications
Protocol Filters and Viewing
Preferences
Filter captured data to
only view key data for
measurement.
Choose to view payload
data with header
information.
Select which protocol
layers and fields to
view in trace.
Figure 5.9.
51
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Post-Processing and Analysis Tool Sets
Data Communications
Display of
protocol levels.
Protocol view of
data acquired in
logic analyzer.
Figure 5.10.
Time tags for system level correlation of other data
buses, memory interfaces, microprocessors, etc.
52
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Post-Processing and Analysis Tool Sets
Data Communications
Global markers measure time intervals between
packets on separate parallel interfaces or timing
between the data path and a microprocessor.
Collapsed view
of protocol infor-
mation using pref-
erences.
Raw packet
header
information.
Raw payload
information.
Figure 5.11.
53
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Post-Processing and Analysis Tool Sets
System Performance Analysis
Debug and System Parameter
Analysis
• Does this pointer address the right
memory buffer?
• How does the system react when it
receives too many simultaneous
interrupts?
• Is the stack size adequate?
• Is the cache size adequate?
Optimize System Performance
Product Description
Your design has to meet consistent
performance requirements over a
range of operating conditions and
over a specific time period. Using the
system performance analysis tool set,
you can obtain answers to many of
your questions concerning perform-
ance and responsiveness, software
execution coverage, debug and sys-
tem parameter analysis, etc.
The Agilent Technologies B4600B sys-
tem performance analysis (SPA) tool
set profiles an entire target system at
all levels of abstraction—from signals
to high-level source code. It clearly
identifies the components that affect
the behavior of your system. In addi-
tion to performance analysis, it can
be used at any time to test and docu-
ment many other characteristics,
such as memory coverage and
response time.
Analog, Timing, and Bus
Measurements
• What is the setup/hold time of this
signal or group of signals?
• Is the distribution of voltages for
this analog signal acceptable?
• Is this signal spending too much
time in the switching region?
• What bus states occur most often?
• What is the bus loading?
• How does the bus affect overall
system performance?
Obtain Answers to the Following
Questions:
The SPA tool set generates statistical
representations of the captured data.
It shows the amount and percent of
time spent in each of the targeted
functions or data locations. Data is
conveniently displayed in histograms
and bar charts, reducing the time you
spend analyzing results and identify-
ing system bottlenecks.
Performance and Responsiveness
• What functions monopolize micro-
processor bandwidth?
• What functions are never execut-
ed? What is the relative workload
of each processor in a multiple-
processor system?
• What is the minimum, maximum,
and average execution time of a
function (including calls)?
• How many interrupts does the
system receive per consecutive
time slice?
• What is the response time of the
target system to an external
event?
• How much time is spent in bus
arbitration?
• What is the histogram of bus
transfer times?
Processor/Cache Measurements
• Which microprocessor bus states
occur most often?
• Which peripherals are used most
often?
• What is the profile of load sharing
in a multiple-processor system?
• How does the cache size affect
system performance?
Software Execution Coverage
• Do test suites provide thorough
coverage of the application?
• Is this function or variable
accessed by the application?
54
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Post-Processing and Analysis Tool Sets
System Performance Analysis
Product Characteristics
SPA Tools
State Interval Display
Time Interval Display
Time Overview Display
State Overview Display
Generates
Provides
Statistical representations of the captured data
Shows the amount and percent of time spent in each of the targeted functions or data locations.
Histogram of event
activity. Display shows
the percentage of hits
for each procedure,
function, or event
Histogram of event times.
Display shows a
distribution of the
execution time of a
specific function or of
the time between two
user-defined events.
Overview of occurrence
rates over time.
Measurements of the
occurrence rate of any
event, including
Overview of bus/memory
activity. Display shows the
number of hits for each
possible bus state.
(states). Events are
defined as patterns or
ranges associated with
any set of data (labels,
symbols).
interrupts, over time.
Usage
Helps prioritize functions
that are candidates for
duration measurements
Determines a specific
routine’s execution times
and verifies signal timing
Views the frequency of
events over time.
First step of analysis or
optimization process to
identify which events occur
most frequently.
using the time interval tool. specifications
Applications
Cache hit and miss
Measures setup and hold
Isolates defects such as
invalid pointers (filtering).
Distribution of signal
voltages can tell whether a
digital signal is spending too
much time in the switching
region. Evaluates the
analysis. Bus headroom
analysis can be made by
examining ratio of active
to idle status states.
Examines workload of
each processor in a
multi-processor system
to determine if system
is balanced.
times, the jitter between
two edges, or the
variation between two
bus states.
linearity of the output of a
D/A converter.
Displays Include
Ability to be viewed simultaneously
Filtering capabilities for removing portions of a trace that are not applicable to the analysis
Maximum Number of Events
No theoretical limit.
Up to 10,000 events tested with a standard configuration
Number of events limited by size of the window
(e.g. pixels on the screen)
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Post-Processing and Analysis Tool Sets
System Performance Analysis
Product Characteristics (continued)
SPA Tools
State Interval Display
Time Interval Display
Time Overview Display
State Overview Display
Supplemental Information
Number of hits
Minimum time
Maximum time
Average time
Number of hits
Time bucket width
Number of hits
State bucket width
Standard deviation
Display Modes
Sort by number of hits
Sort alphabetically by
event name
Sort by time
Sort alphabetically by
event name
Autoscale zoom
Accumulate Mode
No theoretical limit to the number of acquisitions in accumulate mode.
Any modification of the display will cause the display to revert back to the last data acquisition.
Object File Format
Compatibility
Object file formats are identical for SPA and the source correlation tool sets. See page 43.
Off-Line Analysis and
Post-Processing
All measurements can be saved using the file out tool.
Data can be recalled at any time for later analysis using any SPA or other tool.
Performance measurements can be exported to your host computer as histograms or as tabular formatted text files.
Processor Support
Data Sources
Supports any analysis probe listed in Processor and Bus Support for Agilent Technologies Logic Analyzers
(pub no. 5966-4365E)
All measurement modules supported by the 16700 Series logic analysis systems serve without modification as data
sources for the B4600B.
The particular module determines time resolution and accuracy.
Sample rate, channel count, memory depth and triggering are controlled by the user independent of the SPA tool set.
56
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Post-Processing and Analysis Tool Sets
System Performance Analysis
State Overview Tool
Pinpoint regions of high memory activity to
determine which routines or operations are
responsible for throughput bottlenecks.
Narrow in on an area of interest
using built-in qualification and zoom
functions.
Measure memory coverage or stack
usage by observing whether memory
locations are accessed. You can also
detect which peripherals are most fre-
quently used.
Figure 5.12. Identify which events occur most frequently.
57
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Post-Processing and Analysis
System Performance Analysis
State Interval Tool
Sort and display symbols alphabetically by event
name or by the number of hits.
Display just the symbols you
want to evaluate by using the
symbol-navigation utility. The util-
ity automatically configures the
tool for the selected function and
variable names from large symbol
files created by complex software
projects.
To help simplify your display,
delete all functions below a
selected point with a single
mouse click.
Pass the mouse over a histogram bar and
bucket information gives you detailed
information for each event.
Figure 5.13. Determine which functions use the most CPU cycles.
58
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Post-Processing and Analysis
System Performance Analysis
Time Interval Tool
Because time interval measurements often
depend upon hardware-software interaction,
the event definition can be a combination
of symbolics and hardware events. Data
qualification can be used to define the
specific hardware context in which the
analysis will be made.
Data is displayed in histograms, which
can be exported to your host computer
either as histograms or as tabular
formatted text files.
Statistics such as maximum time,
minimum time, standard deviation and
mean help you document system behav-
ior. Use “accumulate mode” to analyze
the behavior of your system over a long
period of time.
Figure 5.14. Determine a specific routine's execution times.
59
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Post-Processing and Analysis Tool Sets
System Performance Analysis
Time Overview Tool
Use “Comments” to document your trace. The
“Comments” field contents are saved with the
configuration and data.
Use the markers in this window to correlate
interrupts to a state listing or timing waveform.
Elusive system crashes are often
caused by too many interrupts occur-
ring over a short period of time. If the
software cannot handle all simultane-
ous service requests, the system can
exhibit random defects while leaving
no clues as to their cause. In this situ-
ation, you need a tool that can meas-
ure and display interrupt loading.
Figure 5.15. View the frequency of events over time.
60
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Post-Processing and Analysis Tool Sets
Serial Analysis
Solve Serial Communication Problems Product Description
Your system may use serial buses to
communicate between ICs and to
transfer data to and from peripheral
devices. Sifting through thousands of
serial bits by looking at long vertical
columns of captured 1's and 0's can
be very tedious, time-consuming, and
error-prone.
The Agilent Technologies B460lB seri-
al analysis tool set is a general-pur-
pose tool that allows easy viewing
and analysis of serial data.
The tool set enables you to:
• Convert acquired serial bit
streams into readable parallel
word formats
• Time-correlate real-time serial
traces to system activity
• Remove stuffed bits from the data
block
Obtain Answers to the Following
Questions:
• Is the software sending the correct
message?
• Is the communication hardware
acting as expected?
• Process frame and data portions
separately
• Process serial data from a signal
with or without an external clock
reference
• Capture and analyze high-speed
(1 GHz) serial buses
• When multiple messages are
involved, in what order is data
being transmitted?
• How does the serial bus activity
correlate to the target system
processor?
• What is causing the data corrup-
tion in the target system?
61
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Post-Processing and Analysis Tool Sets
Serial Analysis
When You Want to Analyze Serial
Bit Streams . . .
...accept the default output
label“Parallel” or modify the
label name for easy recognition.
...specify which signal you want to
convert to parallel format by
selecting a specific bit of any
available label.
...set the output parallel word
width (up to 32 bits).
...select the specific state in
the trace where conversion
begins.
...specify the order in which
the bits occur in the serial
data stream
MSB =Most Significant
Bit first
LSB = Least Significant
Bit first.
...enable frame processing to
extract all instances of a
defined frame.
...maintain or invert the
input serial bit stream.
...capture serial data with or with-
out an external clock reference.
Enable clock recovery for an
incoming serial bit stream that has
no external clock reference.
(RS-232 is an example of a bus
with clocking embedded within the
serial bit stream).
Figure 5.16.
62
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Post-Processing and Analysis Tool Sets
Serial Analysis
To Separate Frame Information
from the Data Block . . .
...accept the default
start of frame label
“Start” or modify the
label to a name of your
choosing.
...specify the pattern
that designates the start
of a frame.
...get immediate feed-
back as you configure
the tool set for your
data. This diagram
changes as you make
your framing and data
block selections.
...remove stuffed 0s or
0/1s from the trace
before other serial
analysis functions are
performed. Some proto-
cols use bit stuffing to
maintain clock
synchronization.
...specify the portion of
the data block for the
serial-to-parallel
conversion.
...specify whether the
end of frame occurs at
the end of a data block
of X bits or on a speci-
fied pattern.
...accept the default
end of frame label
“End” or enter a
different name.
Figure 5.17.
63
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Post-Processing and Analysis Tool Sets
Serial Analysis
To Acquire a Serial Bit Stream
without an External Clock
Reference . . .
...set the sample period of
your timing analyzer to take
four or more samples for
each serial bit.
...accept the “Samples”
default label or enter a new
label name.
...specify the embedded bit
time of the serial bit
stream.
...specify the incoming
signal’s data encoding
method, normal or NRZI.
Figure 5.18.
Clock Recovery Algorithm
1. For analysis purposes the data is
captured in conventional timing
mode using the internal timing
analyzer clock as the clock refer-
ence. Set the sample period of the
timing analyzer to take four or
more samples for each serial bit.
2. The timing analyzer data is sam-
pled in the middle of each bit
according to the serial bit rate
defined in the clock recovery
window.
3. Data edges (transitions from 0 to 1
or 1 to 0 in the timing analyzer
trace) are used to resynchronize
the sampling.
How Clock Recovery Works
Embedded bit time
Resynchronize on edge
Incoming serial
bit stream
Timing analyzer samples
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
(with timing analyzer set
to take five samples for
each serial bit)
0
0
0
0
1
1
1
1
1
New “Samples”serial data
Figure 5.19.
64
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Post-Processing and Analysis Tool Sets
Serial Analysis
Once the Serial Bit Stream is
Acquired . . .
This example shows the conversion of an RS-
232 serial bit stream. The data sent to the
printer includes the column header
”MACHINE”.
...configure the
serial tool once for
your specific bus,
then save the con-
figuration for
...view the serial-to-parallel
conversion in the format that
is easiest for you — wave-
form or listing.
future uses.
...display the parallel data in binary, hex, octal, deci-
mal, ASCII or Twos Complement.
...use the global markers and time tags to correlate
real-time serial traces to other system activity.
...synchronize the start of the serial-to-parallel con-
version to the start of the frame pattern for your spe-
cific bus.
...convert the data block into parallel words, in this
case 8-bit words.
...find the Nth occurrence of specific frames or data
relative to the trigger, other markers, or the begin-
ning or end of the trace. Markers allow you to quick-
ly search from frame to frame in the data.
...view the data in the order in which the bits occur
in the serial stream, in this case LSB.
Figure 5.20.
65
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Post-Processing and Analysis Tool Sets
Serial Analysis
Because every trace is non-intrusive,
and every event captured in the trace
is time-stamped, you can correlate
activity from your serial bus with
other events in the target system.
Parallel Data Display Types
Binary, Octal, Hex, Decimal, ASCII,
Twos Complement
Product Characteristics
Data Sources
All state and timing measurement
modules supported by the 16700
Series logic analysis systems serve
Off-line Analysis and Post-Processing
All measurements can be saved using
the file out tool. Data can be recalled
at any time for later analysis using
any analysis or display tool. Serial
measurement data can be exported to
your host computer as ASCII files.
The Agilent Technologies 16720A and
without modification as data sources
16522A pattern generator modules
for the B4601B serial analysis tool
can be used to generate your own
set. The particular measurement
serial test data.
module used determines time resolu-
tion and accuracy. Sample rate, chan-
Maximum Parallel Word Width
nel count, memory depth and trigger-
32 bits
ing are controlled by the user inde-
pendent of the serial analysis tool.
Serial Measurement Characteristics
16517A/18A
16710A/11A/12A 16715A
8 Kbits/32 Kbits/ 2 Mbits
128 Kbits
16716A
16717A/18A/19A 16750A/51A/52A
Maximum serial
Mbits/
Clocked data [1]
64 Kbits
512 Mbits
256 Mbit
2 Mbits/8 Mbits/ 4 Mbits/16
trace depth
32 Mbits
32 Mbits
Unclocked data [2]
16-32 Kbits
4 Kbits/16Kbits/
64 Kbits
1 Mbit
1 Mbit/4 Mbits/
16 Mbits
2 Mbits/8 Mbits/
16 Mbits
Maximum serial
bus frequency
Clocked data [3]
Unclocked data [4]
Clocked data
1 Gbit/s
100 Mbits/s
125 Mbits/s
No limit
167 Mbits/s
167 Mbits/s
No limit
167 Mbits/s
167 Mbits/s
No limit
333 Mbits/s
167 Mbits/s
No limit
400 Mbits/s
200 Mbits/s
No limit
1 Gbit/s
Minimum serial
bus frequency
20 Mbit/s
765 Mbits/s
Unclocked data [5]
5 Kbits/s
50 bits/s
50 bits/s
50 bits/s
50 bits/s
Information in Table above calculated according to notes [1] to [5]
[1] =Maximum State Memory Depth
[2] =Maximum Timing Memory Depth/4
[3] =Maximum State Frequency
[4] =Maximum Timing Frequency/4
[5] =1/(Maximum sample period x 20)
66
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Post-Processing and Analysis Tool Sets
Tool Development Kit
The custom tools can be used on any
16700 Series logic analysis system.
This allows you to purchase just one
or two copies of the development kit
and develop custom tools to support
a large number of analyzers.
Customize Your Measurements
The ability to interpret and display
information is vital to your project.
At times the information you need
can be buried in the raw data of your
measurement. This might be due to
one of several reasons:
Enhance Data Displays
• Color-code specific states of your
trace.
• Display some of your trace data in
engineering units.
• The use of a protocol, encoded
data, or proprietary bus
• Events that happen only under
certain conditions
• Convert the raw trace of a propri-
etary bus to a transaction-level
trace of that bus.
• The need to analyze system
performance
• The need to analyze data across
a large number of repetitive
measurements
Manipulate Data
• Unravel interleaved data into two
or more columns of data.
Product Description
• Combine the traces of two differ-
ent analyzers into one trace, with
each column being combined or
separately displayed as prescribed
by you.
• Modify your scope trace using an
algorithm developed by you, such
as an analog filter, beat frequency,
or DSP algorithm.
The Agilent Technologies B4605B tool
development kit provides a complete
environment for creating custom
tools that processes data using the
powerful search and filtering capabil-
ities of the logic analysis system.
Features of the tool kit include:
• Fast, compiled and optimized C
code
Read or Write External Files
• Accumulate information from
repetitive traces taken by the ana-
lyzer in a file on your PC or UNIX
workstation.
• Write specific types of states or
trace data that have been analyzed
to an Excel consumable ASCII file
on your PC or UNIX workstation.
• Use information read from a file
on your PC or UNIX workstation
to modify the display of an
• Push button compiling, no make
files
• A rich library of functions that
speeds development
• Extensive examples of code
• The creation of installable tools
• One year of technical support for
the B4605B
Data is processed quickly by the cus-
tom tools, because they consist of
compiled, optimized C code. A C lan-
guage programming background is
highly recommended. A tutorial,
extensive examples, and a rich
library of functions are provided that
help you easily access analyzer data
and the tool's interface.
analyzer trace.
67
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Post-Processing and Analysis Tool Sets
Tool Development Kit
Custom Tool Example, Added Text in
Trace
This example shows how a custom
tool can convert data to text to pres-
ent information in an easy-to-under-
stand form.
The original trace comes from a
control unit in an automobile.
Embedded in the data is information
about the engine and transmission.
When MODE = 0, DATA represents
engine information, including RPM,
fuel level, fuel to air ratio, and mani-
fold pressure. When MODE = 1,
DATA represents transmission infor-
mation, including gear position and
temperature.
Output of Custom Tool
Original Trace
This custom tool allows the user to
specify Fahrenheit or Centigrade for
the engine temperature data.
Figure 5.21.
Parameter Interface of Custom Tool
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Post-Processing and Analysis Tool Sets
Tool Development Kit
The output of the custom tool in this
example is shown. Notice that there
is now data in the DATA column. The
custom tool was able to reconstruct
the code flow after the trace was
taken. The code was reconstructed by
using the branch trace messages and
information in the SRecord file creat-
ed when the code was compiled. The
tool took the address of the appropri-
ate states in the trace data and found
the corresponding code (data) in the
SRecord file. This created a trace that
the MPC 555 inverse assembler could
operate on properly.
Custom Tool Example, Microprocessor
Code Reconstruction
The original trace came from the bus
of a MPC 555 processor. As you can
see, no data was placed on the bus at
the time of the trace because cache
memory was turned on. Normally, it
would not be possible to inverse
assemble this trace.
Original Trace
Output of Custom Tool
By entering information here, users can direct
the tool to the correct SRecord file and control
how much of the data the tool is to operate on.
They can also indicate if the AT2 pin of the MPC
555 processor is in use.
Figure 5.22. Code reconstruction
Parameter Window of Custom Tool
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Post-Processing and Analysis Tool Sets
Tool Development Kit
Custom Tool Example, Multiplex Data
Custom tools can combine several
lines of data acquired sequentially
under one label into one line of data.
However the data to be combined
does not have to come from the same
label, it can come from different
labels. The labels can even come from
different analyzers.
Output of Custom Tool
Original Trace
At left are the parameter window and
message display created by the custom
tool in this example. Parameters allow the
user to control different aspects of what
the tool does to the acquired trace. The
user can change the parameters and hit
the execute button to change the output
of the tool. The output dialog to the
left displays information generated by
the tool.
Figure 5.23.
Parameter and Output Windows
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Post-Processing and Analysis Tool Sets
Tool Development Kit
Select this button to cause the compiled code
to operate on the acquired data.
Custom Tool Development
Environment
This is the main window for
developing code with the tool
development kit.
Select this button to compile the
code displayed in the “Source
Code” tab.
Load a file created on another
system or create your code here
using the “Source Code” editor.
Compilation status is shown
at the bottom of the tool
development kit Display window.
Runtime errors are displayed in
the “Runtime” tab.
Errors generated
during a compile
are displayed in
the “Buildtime”
tab.
Output generated
during the tool’s
execution are
displayed in the
“Output” tab.
Figure 5.24. TDK development environment
71
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Post-Processing and Analysis Tool Sets
Tool Development Kit
Product Characteristics
Provided Functions
Analyzer compatible custom tools
will run on any 16700 Series analyzer
running version A.01.40.00 or
greater. In some rare instances,
changes in the operating system can
require that your tools be recompiled
in order to run on that version of the
operating system.
Agilent Technologies provides a rich
library of functions that allow you to
copy data sets, create new data sets
with new labels, and to reorganize
the acquired data under these new
labels or to include data or text
derived from the acquired data.
The functions allow:
Analysis and Stimulus Modules
The tool development kit supports
the following Agilent Technologies
measurement modules:
• Stopping a repetitive run
• Filtering of the data
• Randomly accessing the data
• Searching the data
• Displaying the data in one of eight
colors
• Accessing the trigger point
• Accessing the acquired time or
state of the data
• 16715A, 16716A, 16717A, 16718A,
16719A, 16750A, 16751A, 16752A
• 16710A, 16711A, 16712A
• 16557D
• 16556A/D, 16555A/D
• 16554A
• Outputting text strings to the
tool's display window
• 16550A
• Outputting errors to the runtime
window
• 16534A, 16533A
• 16517A, 16518A
• 16522A, 16720A
• 16740A, 16741A, 16742A
By using two of the provided func-
tions, a simple user interface can eas-
ily be created that consists of label
strings and input fields. This allows
the input of parameters during the
tool's execution.
C Compiler
The libraries provided with the C
compiler allow you to perform stan-
dard operations such as creating
ASCII or binary files, reading from
these files, writing or appending to
these files, and IEEE 764 floating
point operations.
72
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Post-Processing and Analysis Tool Sets
Licensing Information
Licensing and Miscellaneous
Description
System Configuration Requirements
• 16700 Series logic analysis system
• Desired tool set(s)
• Supported and compatible measurement hardware
Tool Set Control
• Locally control and view tool set measurements
• Remotely access any tool set from a PC or workstation through a web browser or X-window emulation
software.
File Access
• Access source files or other development environment applications (compiler, debugger) from the logic
analyzer via Telnet, NFS, or mapped file systems, and X-Windows client/server protocols.
• Save or access files via the standard network capabilities of the logic analyzer, such as FTP, NFS, or CIFS
(Common Internet File System for Windows 95/98/NT based PCs.
Ordering and Shipment
• When a tool set is ordered with a 16700 Series mainframe, the tool set is shipped installed and ready to
run (Unless option 0D4 is ordered.)
• Tool set proof-of-receipt is provided by the entitlement certificate.
See page 121 for ordering information.
Tool Set Licensing Information
License Policy
The 16700 Series logic analysis systems’ tool set software is licensed for single-unit use only. Licenses
are valid for the life of the tool set. Software updates do not affect the license.
Nodelock Mode
• Tool set licenses are shipped or first installed as nodelocked applications. Nodelocked means that use of
the tool set license is only allowed on the single node (16700 Series analyzer on which it is installed). Tool
sets ordered with a 16700 Series mainframe will be installed with a permanent password and are ready to
run.
• For tool sets purchased as upgrades to existing 16700 Series mainframes, you must access the Agilent
password redemption web site to obtain a password. Your entitlement certificate provides the web URL
and alternate contact information. Password turnaround is generally the same business day.
Free Tool Set Evaluation
(Temporary Demo License)
A single temporary license is available for any tool set type not previously licensed on a node. The
temporary password for any node on any tool set is "demo". The temporary license is valid for 21 calendar
days from first entry of the password in the license management window of the 16700 Series logic
analysis system.
License Management
Password Backup
Licenses are managed from ‘Licensing…’ in the Admin tab of System Admin. Licenses are reserved at the
start of a measurement session. They remain in use until the measurement session is terminated.
Passwords can be backed up to a floppy disk or network file. Should the passwords on your 16700 Series
logic analysis system hard drive become corrupted, the tool set passwords can be reinstated by copying
your backed up password file to: /system/licensing/license.dat
73
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Time Correlation with Agilent Infiniium Oscilloscopes
E5850A Logic Analyzer - Oscilloscope Time Correlation Fixture
• Automatic de-skew.
• Tracking markers.
E5850A Logic Analyzer – Oscilloscope
Time Correlation Fixture
Measurements between the logic
analyzer and Infiniium oscillo-
scope are automatically de-skewed
in time. This saves you time and
gives you confidence in the meas-
urement results.
The Infiniium oscilloscope’s time
markers track the global markers
in the 16700 logic analyzer. If you
wish to view a waveform in
greater detail on the oscilloscope’s
display, or measure a voltage level
using the oscilloscope’s voltage
markers, this feature allows you to
relate information on the oscillo-
scope’s display precisely to corre-
sponding information on the logic
analyzer display.
The Agilent E5850A time correlation
fixture allows you to make time-cor-
related measurements between a
16700 logic analyzer and an Agilent
548XX Series Infiniium oscilloscope
to solve the following types of prob-
lems more effectively:
• Combined waveform display.
The Infiniium oscilloscope wave-
forms are displayed in the wave-
form display window on the 16700
logic analyzer, along with timing
analyzer waveforms. This allows
you to instantly visualize time
relationships among oscilloscope
and timing measurements.
• Verifying signal integrity
• Tracking down problems caused
by signal integrity
• Verifying correct operation of A/D
and D/A converters
• Verifying correct logical and tem-
poral relationships between the
analog and digital portions of a
design
• Global markers.
The global markers in the 16700
may be used to measure time
among all measurements made in
the logic analyzer and Infiniium
oscilloscope measurements.
Agilent’s E5850A time correlation
fixture works in conjunction with
software in the 16700 family logic
analyzers, and any Agilent Infiniium
54800 Series oscilloscope, to deliver
the following features:
Figure 5.26. E5850A time correlation fixture.
Compatibility
For Infiniium
scope
Software version
for 16700 series
Software version for oscillo-
Infiniium oscilloscope
model number
logic analyzer
54810A
54815A
54820A
54825A
54835A
54845A
54856A
54830B
54831B
54832B
A.02.20.00 or higher
A.04.00 or higher
A.02.50.00 or higher
A.01.00 or higher
The E5850A requires the versions of operating software indicated in the table
Figure 5.25. Infiniium oscilloscope waveforms are displayed in the 16700 logic
analyzer waveform display window along with logic analyzer timing wave-
forms, accurately time-correlated.
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Mainframe Specifications and
Characteristics
Mass Storage
Agilent 16700 Series Technical
Information
Hard Disk Drive
9 GB formatted disk drive
Floppy Disk Drive
• Capacity
• Media
• Formats
System Software
All features and functionality
described in this document are
available with system software
1.44 MB formatted
3.5 inch floppy
MS-D0S (Read, write, format), LIF (Read only)
version A.02.20.00
Internal System RAM
Standard
128 MB
Option 003 (Must be ordered at
256 MB total
time of frame purchase)
Supported Monitor Resolutions
Standard
640 x 480 through 1280 x 1024
(The 16702B has a built-in 800 x 600, 12.1”
(26.2mm) diagonal monitor.)
Option 003 (Must be ordered at
time of frame purchase)
Adds support for up to 1600 x 1200
LAN, IEEE 802.3
Physical Connectors
16700B Series:
10BaseT/100BaseT-X (ethertwist): RJ-45
16700A Series:
10BaseT (ethertwist): RJ-45; 10Base2: BNC
Protocols Supported
TCP/IP
NFS
CIFS (Windows® 95/98/NT) [1]
FTP
NTP
PCNFS
X-Window Support
X Window system version 11, release 6, as a client and
server
[1] User and share level control supported for Windows NT® 4.0. Share level control only supported for
Windows 95/98.
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Mainframe Specifications and
Characteristics
Web Server
Agilent 16700 Series Technical
Information (continued)
Supported from Instrument
Web Page
Measurement status check,remote display, installation
of PC application software, link to Agilent’s Test and
Measurement site
PC Requirements
Pentium® (family) PC (200 MHz, 32 MB RAM) running
Windows 95, Windows 98, or Windows NT 4.0 with
service pack 3 or higher
Supported Web Browsers
(on Your PC or Workstation)
Internet Explorer 4.0 or higher,
Netscape 4.0 or higher
IntuiLink Support
Installation of PC Application Software
MS Excel
Directly from instrument web page
Excel 97 Version 7.0 or later. Excel limits maximum trace
depth to 64K per sheet.
Available Data Formats
Fast Binary (Compressed
Binary Format)
High performance transfer rate. Includes source code to
parse data. Available via File Out.
Uncompressed Binary
ASCII
Includes utility routines. Available via RPI.
Provides same format as listing display, including
inverse-assembled data. Available via RPI and File Out.
Pattern Generator Binary
Used to load large amount of stimulus (> 1M) into the
16720A pattern generator
Intermodule Bus (IMB)
Time Correlation Resolution
2 ns
Port In/Out
Connectors
BNC
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Mainframe Specifications and
Characteristics
Port In
Agilent 16700 Series Technical
Information (continued)
Levels
TTL, ECL, or user defined
4 KΩ
Input Resistance
Input Voltage
–6V at –1.5 mA to +6V at 1.6 mA
Port Out
Levels
3V TTL compatible into 50 Ω
Functions
Latched (latch operation is module dependent)
Pulsed, width from 66 ns to 143 ns
Target Control Port
Number of signals
Levels
8
3V TTL compatible
Connector
2 rows of 5 pins, 0.1-inch centers
Operating Environment
Temperature
• Instrument
• Disk Media
• Probes/Cables
0°C to 50°C (32°F to 122°F)
10°C to 40°C (50°F to 104°F)
O°C to 65°C (32°F to 149°F)
Altitude
To 3000m (10,000 ft)
Humidity
8 to 80% relative humidity at 40°C (104°F)
Printing
Printer Interface
Printers Supported
Parallel interface for Centronics compatible printers
PostScript printers and printers which support the
HP Printer Control Language (PCL)
Graphics
Graphics can be printed directly to the printer or to a file.
Graphic files can be created in black-and-white or color
TIFF format, PostScript, PCX, or XWD formats
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Mainframe Specifications and
Characteristics
Remote Programming Interface (RPI)
RPI Overview
Typical Applications
Manufacturing Test
Data Acquisition for Offline Analysis
System Verification and Characterization
Pass/Fail Analysis
Stimulus Response Tests
Remote Programming
Steps
1.Set up the logic analyzer and save the test configuration.
2.Create a program that remotely:
Loads a test configuration
Starts the acquisition process
Checks measurement status (verifies completion)
Acts on the results of the data acquisition
• Saves configuration and captured data
• Exports data
• Executes a compare
• Modifies the trigger setup or trigger value for the next
acquisition
• Accesses the oscilloscope’s automatic measurements
Physical Connection
Remote programming is done via the LAN connection
Requirements
16700B Series
Analysis Systems
RPI is standard with system software version A.02.00.00 or
higher
PC
Programming is done via Microsoft® ActiveX/COM
automation
Pentium (family) PC with one of the following:
• Windows 95
• Windows 98
• Windows NT 4.0 with Service Pack 3 or higher
Visual Basic or Visual C++ (Version 5.0 or higher)
UNIX®
Programming is done via TCP/IP socket based
ASCII commands
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Mainframe Specifications and
Characteristics
Remote Programming Interface (RPI) (continued)
Command Set Summary - Commands available on both UNIX and PC
System
System Configuration Query
Load/Save Configuration and Data
Start/Stop Measurement
Current Run Status
Start/Stop/Query a Session
Logic Analysis Modules
Load/Save Configuration and Data
Trigger Setup
Acquisition Data and Parameters
Set/Query Acquisition Mode
Set/Query Acquisition Depth
Set/Query Pod Assignment
Add/Delete/Load/Query Labels
Set/Query Trigger Position
Modify Occurrence Count
Oscilloscope Modules
Pattern Generator
Load/Save Configuration and Data
Acquisition Data / Parameters
Query Automatic Measurements
Trigger Setup
Load/Save Configuration and Data
Load ASCII file (vectors) or PGB (pattern generator binary)
files (16720A only)
Modify Vector
Set/Query Clock Frequency
Set/Query Clock Out Delay
Insert New Vector at Specific Position
Delete Specific Vector
Emulation Module
Reset Processor
Run Processor
Break Processor
Single Step
Listing Tool
Status
Acquisition Data and Parameters
Transfer Data (includes inverse assembled information)
Compare Tool
Execute Compare
Set Compare Mask
Query Compare Result
Specify Range to Compare
Abort Compare After Specified Number of Differences
Return Labels and Values Where Differences Occur
File Out Tool
Transfer Data to File
Select Range to Expert
Additional Information
Instrument Online Help
Web Sites
Programming Information in instrument online help
Full remote programming documentation (pdf) available on
the hard drive. Sample programs are provided
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Mainframe Specifications and
Characteristics
IntuiLink
Programming Examples Provided with IntuiLink
Visual Basic
Examples have been included for use with Visual Basic 5.0
or higher. These examples perform simple functions such
as: system checks, oscilloscope measurements, pass/fail
tests using stored configuration and pattern generator
stimulus files, and stimulus/response tests. They also can
capture and retrieve data for off-line analysis.
Visual C++
LabVIEW
Examples have been included for use with Visual C++ 5.0 or
higher to perform simple functions such as: system check,
capturing and retrieving data for off-line analysis.
An instrument library has been included for use with
LabVIEW 5.1 or higher. This library contains five LabVIEW
samples that provide a starting point for creating your own
LabVIEW programs.
• Load/Run/Save - loads a configuration, runs a
measurement, then saves results to a file
• Analyzer Listing - runs the logic analyzer and displays
data in a table
• Pass/Fail - runs the logic analyzer and compares the
measurement data against a standard
• Scope Waveform - runs the oscilloscope module and
displays waveform data
• Scope Measurements - runs the oscilloscope module
and displays a number of oscilloscope measurements
HP VEE
An instrument library has been included for use with
HP VEE 5.0 or higher that provides a starting point for
creating your own application.
• Load/Run/Save - loads a configuration, runs a
measurement, then saves results to a file
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Mainframe Specifications and
Characteristics
12.1” Built-in LCD
Display with Touch
Screen
3.5 Inch Floppy
Disk Drive
Agilent 16700B Series Physical
Characteristics
Power
16700B
16701B
16702B
115/230 V, 48 to 66 Hz, 610 W max
115/230 V, 48 to 66 Hz, 545 W max
115/230 V, 48 to 66 Hz, 610 W max
On/Off
Power Switch
Touch Screen On/Off
Weight*
Figure 6.1. Agilent 16702B front panel.
Max Net
Max Shipping
16700B
lbs)
16701B
lbs)
16702B
lbs)
12.7 kg (27.0 lb) 34.2 kg (75.4
10.4 kg (23.0 lb) 32.0 kg (70.6
15.2 kg (32.4 lb) 36.7 kg (80.8
Parallel Port
LAN 10BaseT/100BaseT-X
SCSI-2 Single Ended
Monitor
RS-
Five Slots for
Measurement
Modules
A
B
C
D
E
One Slot for
Emulation or
Multiframe
Module
*
Weight of modules ordered with mainframes will add
0.9 kg (2.0 lb) per module.
Target Control Port
Port IN
40x CD-ROM
Drive
Keyboard
Mouse
Port OUT
Expansion Frame Cable Connector
Figure 6.2. Back panel for Agilent models 16700B and 16702B.
551.2 (21.7”)
425.7 (16.75”)
234.2
(9.22”)
Dimensions: mm (inches)
Figure 6.3. Exterior dimensions for the 16700B Series mainframe.
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Mainframe Specifications and
Characteristics
Built-in LCD Display
3.5 Inch Floppy
Disk Drive
Agilent 16700A Series Physical
Characteristics
Power
16700A
16701A
16702A
115/230 V, 48 to 66 Hz, 610 W max
115/230 V, 48 to 66 Hz, 545 W max
115/230 V, 48 to 66 Hz, 610 W max
On/Off
Power Switch
Screen Intensity Adjustment
Keypads for Alpha-Numeric Entry
Weight*
Figure 6.4. Agilent 16702A front panel.
Max Net
Max Shipping
16700A
lbs)
16701A
lbs)
16702A
lbs)
12.7 kg (27.0 lb) 34.2 kg (75.4
10.4 kg (23.0 lb) 32.0 kg (70.6
15.2 kg (32.4 lb) 36.7 kg (80.8
Parallel Port
LAN 10BaseT
SCSI-2 Single Ended
LAN 10Base2
Monitor
A
RS-
Five Slots for
Measurement
Modules
Two Slots for
Emulation
Modules
1
2
B
C
D
E
*
Weight of modules ordered with mainframes will add
0.9 kg (2.0 lb) per module.
Target Control Port
Port IN
Keyboard
Mouse
Port OUT
Expansion Frame Cable Connector
Figure 6.5. Back panel for Agilent models 16700A and 16702A.
548.64 (21.6”)
556.3 (21.9”)
482.6 (19.0”)
425.7 (16.76”)
234.2
(9.22”)
Dimensions: mm (inches)
Figure 6.6. Exterior dimensions for the 16700A Series mainframe.
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Probing Solutions Specifications and
Characteristics
Probing Technical Specifications
POWER GND
SIGNAL GND
SIGNAL GND
SIGNAL GND
2
4
6
8
1
3
5
7
9
+5V
CLK1
CLK2
D15
SIGNAL GND 10
SIGNAL GND 12
SIGNAL GND 14
SIGNAL GND 16
SIGNAL GND 18
SIGNAL GND 20
SIGNAL GND 22
SIGNAL GND 24
SIGNAL GND 26
SIGNAL GND 28
SIGNAL GND 30
SIGNAL GND 32
SIGNAL GND 34
SIGNAL GND 36
SIGNAL GND 38
POWER GND 40
D14
11 D13
13 D12
15 D11
17 D10
19 D9
21 D8
23 D7
25 D6
27 D5
29 D4
31 D3
33 D2
35 D1
37 D0
39 +5V
1
3
5
7
9
+5V
CLK 1
D14
D12
D10
CLK 2
D15
2
4
6
8
+5V
1
3
5
7
9
2 POWER GND
4 SIGNAL GND
6 SIGNAL GND
8 SIGNAL GND
10 SIGNAL GND
12 SIGNAL GND
14 SIGNAL GND
16 SIGNAL GND
18 SIGNAL GND
20 SIGNAL GND
22 SIGNAL GND
24 SIGNAL GND
26 SIGNAL GND
28 SIGNAL GND
30 SIGNAL GND
32 SIGNAL GND
34 SIGNAL GND
36 SIGNAL GND
38 SIGNAL GND
40 POWER GND
D13
CLK1
CLK2
D15
D11
D9 10
D7 12
D5 14
D3 16
D1 18
GND 20
11 D8
13 D6
15 D4
17 D2
19 D0
D14
D13 11
D12 13
D11 15
D10 17
D9 19
D8 21
D7 23
D6 25
D5 27
D4 29
D3 31
D2 33
D1 35
D0 37
+5V 39
Figure 6.7. Pinout for state/timing module pod cable and 100 KΩ isolation adapter. (Agilent 01650-63203)
2
4
6
8
CLK2
D15
D13
D11
+5V
CLK1 3
1
D14
D12
D10
D8 11
D6 13
D4 15
D2 17
D0 19
5
7
9
10 D9
12 D7
14 D5
16 D3
18 D1
20 GND
Figure 6.8. Pinout for 20-pin connector. (Agilent 1251-8106)
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Probing Solutions Specifications and
Characteristics
Isolation Adapter 01650-63203
Adapter RC Network
Isolation adapters that connect to
the end of the probe cable are
designed to perform two functions.
The first is to reduce the number of
pins required for the header on the
target board from 40 pins to 20
pins. This process reduces the
board area dedicated to the prob-
ing connection. The second func-
tion is to provide the proper RC
isolation networks in a very con-
venient package.
250 90.9k
ohm ohm
Signal
To Logic
Analyzer
Pod
8.2pF
Ground
Equivalent Load
370
ohm
Signal
100k
ohm
4.6pF
7.4pF
Ground
Includes logic analyzer
Figure 6.9. Termination adapter and equivalent load.
E5346A 38-pin Probe
370 ohm
Signal
100k
ohm
3pF
9pF
Ground
Figure 6.10. E5346A equivalent load.
E5339A 38-pin Low Voltage Probe
220 ohm
Signal
50.5k
ohm
3pF
18pF
Ground
Figure 6.11. E5339A equivalent load.
84
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State/Timing Modules Specifications and
Characteristics
Key Specifications* and Characteristics
Agilent Model Number
16715A, 16716A, 16717A
16740A, 16741A, 16742A
16750A, 16751A, 16752A
16760A
Maximum state acquisition rate on
each channel
16715A, 16716A: 167 Mb/s
16717A, 333 Mb/s [1]
200 Mb/s
400 Mb/s [1]
Full channel: 800 Mb/s
Half channel: 1.25 Gb/s
Maximum timing sample rate
(half/full channel)
Timing Zoom: 2 GHz (16716A,
16717A only)
Timing Zoom: 2 GHz
Timing Zoom: 2 GHz
Conventional: 800 MHz
Transitional: 400 MHz
Conventional: 800/400 MHz
Transitional: 400 MHz
Conventional: 800/400 MHz
Transitional: 400 MHz
Conventional: 667/333 MHz
Transitional: 333 MHz
Channels/module
68
68
68
34
Maximum channels on a
340 (5 modules)
340 (5 modules)
340 (5 modules)
170 (5 modules)
single time base and trigger
Memory depth
16715A, 16717A: 4/2M [2]
16716A: 1M/512K [2]
16740A: 2/1 M [2]
16741A: 8/4 M [2]
16742A 32/16 M [2]
16750A: 8/4M [2]
16751A: 32/16M [2]
16752A: 64/32M [2]
128/64M [5]
(half/full channel)
Trigger resources
16750A,
Patterns: 16
Ranges: 15
Pattern: 16
Patterns: 16
Ranges: 15
At 800 Mb/s: 4 patterns or
2 ranges, 4 flags, arm in
At 200 Mb/s: same as
Ranges: 15
Edge & Glitch: 2
Edge & Glitch: 2
Edge & Glitch: 2
Timers: (2 per module) -1
Occurrence Counter: [4]
Global Counters: 2
Flags: 4
Timers: (2 per module) –1
Occurrence Counter: 2
Global Counter: 2
Flags: 4
Timers: (2 per module) -1
Occurrence Counter: [4]
Global Counters: 2
Flags: 4
16751A, 16752A
Other speeds: refer to
synchronous state analysis
(page 98) and asynchronous
timing analysis (page 100)
Maximum trigger sequence levels
16
16
16
1.25 Gb/s: 2
800 Mb/s: 4
200 or 400 Mb/s: 16
Maximum trigger sequence speed
Trigger sequence level branching
16715A, 16716A: 167 MHz
16717A: 333 MHz
200 MHz
400 MHz
1.25 Gb/s
4-way arbitrary “IF/THEN/ELSE”
branching
4-way arbitary
“IF/THEN/ELSE”
branching
4-way arbitrary “IF/THEN/ELSE” 800 or 1.25 Gb/s: none
branching
200 Mb/s: arbitrary
“IF/THEN/ELSE” branching
400 Mb/s: dedicated next-
state branch or reset
Number of state clocks/qualifiers
Setup/hold time*
4
4
4
1 (state clock only)
2.5 ns window adjustable from
4.5/-2.0 ns to -2.0/4.5 ns in 100 ps
increments per channel [3]
2.5 ns windows adjustable from
4.5/2.0 ns to -2.0/4.5 ns in 100 ps
increments per channel [3]
2.5 ns window adjustable from
1 ns window adjustable from
4.5/-2.0 ns to -2.0/4.5 ns in 100 ps 2.5/-1.5 ns to -1.5/2.5 ns
increments per channel [3]
10 ps increments per channel
Threshold range
TTL, ECL, user-definable 6.0 V
adjustable in 10-mV increments
TTL, ECL, user-definable 6.0 V
adjustable in 10-mV increments
TTL, ECL, user-definable 6.0 V
adjustable in 10-mV increments
-3.0 V to 5.0 V adjustable in
10-mV increments
*
All specifications noted by an asterisk are the performance standards against which the product is tested.
[1] State speeds greater than 167 MHz (16717A) or 200 MHz (16750A, 16751A, 16752A, 16760A) require a trade-off in features.
Refer to “Supplemental Specifications and Characteristics” on page 93 for more information.
[2] Memory depth doubles in half-channel timing mode only.
[3] Minimum setup/hold time specified for a single clock, single edge acquisition. Multi-clock, multi-edge setup/hold window add 0.5 ns.
[4] There is one occurrence counter per trigger sequence level.
[5] Memory depth doubles in half-channel 1.25 Gb/s state mode only.
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State/Timing Modules Specifications and
Characteristics
Key Specifications* and Characteristics (continued)
Agilent Model Number
16710A, 16711A, 16712A
Maximum state acquisition rate on
each channel
100 Mb/s
Maximum timing sample rate
(half/full channel)
Conventional: 500/250 MHz
Transitional: 125 MHz
Channels/module
102
Maximum channel count on a
single time base and trigger
204 (2 modules)
Memory depth
(half/full channel)
16710A: 16/8K [1]
16711A: 64/32K [1]
16712A: 256/128k [1]
Trigger resources
Patterns: 10
Ranges: 2
Edge & Glitch: 2
Timers: 2
Maximum trigger sequence levels
State mode: 12
Timing mode: 10
Maximum trigger sequence speed
Trigger sequence level branching
125 MHz
Dedicated next state or
single arbitrary branching
Number of state clocks/qualifiers
Setup/hold time*
6
4.0 ns window adjustable from
4.0/0 ns to 0/4.0 ns in 500 ps
increments [2] per 34 channels
Threshold range
TTL, ECL, user-definable 6.0 V
adjustable in 50 mV increments
*
All specifications noted by an asterisk are the performance standards against which the product is tested.
[1] Memory depth doubles in half-channel timing mode only.
[2] Minimum setup/hold time specified for single-clock, single-edge acquisition. Single-clock, multi-edge setup/hold
add 0.5 ns. Multi-clock, multi-edge setup/hold window add 1.0 ns.
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State/Timing Modules Specifications and
Characteristics
Agilent Technologies 16710A, 16711A, 16712A
Supplemental Specifications* and Characteristics
370 ohms
Probes (general-purpose lead set)
100K
ohm
1.5pF
7.4pF
Input resistance
100 KΩ, 2%
Parasitic tip capacitance
Minimum voltage swing
Threshold accuracy*
Maximum input voltage
1.5 pF
500 mV, peak-to-peak
(100 mV + 3% of threshold setting)
40 V peak
GROUND
Figure 6.12. Equivalent probe load for the
Agilent 16710A, 16711A and 16712A, general-
purpose lead set.
State Analysis
Minimum state clock pulse width
Time tag resolution [1]
3.5 ns
8 ns
Maximum time count between states
34 seconds
9
Maximum state tag
4.29 x 10 states
count between states [1]
Minimum master to master clock time*
Minimum master to slave clock time
Minimum slave to master clock time
16710A, 16711A, 16712A: 10 ns
0.0 ns
4.0 ns
Context store block sizes
16710A/11A/12A only
16, 32, 64 states
Timing Analysis
Sample period accuracy
Channel-to-channel skew
Time interval accuracy
0.01% of sample period
2 ns, typical
(sample period + channel-to-channel
skew + 0.01% of time interval reading)
Minimum detectable glitch
3.5 ns
*
All specifications noted by an asterisk are the performance standards against which the product is tested.
[1] Time or state tags halve the acquisition memory when there are no unassigned pods.
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State/Timing Modules Specifications and
Characteristics
Agilent Technologies 16710A, 16711A, 16712A
Supplemental Specifications* and Characteristics (continued)
Triggering
Maximum trigger sequence speed
Maximum occurrence counter
Range width
125 MHz, maximum
1,048,575
32 bits each
Timer value range
400 ns to 500 seconds
16 ns or 0.1% whichever is greater
32 ns or 0.1% whichever is greater
Timer resolution
Timer accuracy
Operating Environment
Temperature
Agilent 16700 Series mainframes:
• Instrument 0˚C to 50˚C (+32˚F to 122˚F)
• Probe lead sets and cables, 0˚C to 65˚C (+32˚F to 149˚F)
Humidity
Altitude
80% relative humidity at +40˚C
Operating 4600m (15,000ft)
Nonoperating 15,300m (50,000ft)
*
All specifications noted by an asterisk are the performance standards against which the product is tested.
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State/Timing Modules Specifications and
Characteristics
Agilent Technologies 16715A, 16716A, 16717A, 16740A, 16741A,
16742A, 16750A, 16751A, 16752A Supplemental Specifications*
and Characteristics
370 ohms
100K
ohm
1.5pF
7.4pF
Probes (general-purpose lead set)
Input resistance
100 KΩ, 2%
Parasitic tip capacitance
Minimum voltage swing
Minimum input overdrive
Threshold range
1.5 pF
GROUND
500 mV, peak-to-peak
250 mV
Figure 6.13. Equivalent probe load for the
Agilent 16715A, 16716A, 16717A, 16718A,
16719A, 16750A, 16751A, 16752A general-
purpose lead set.
-6V to +6V in 10 mV increments
(65 mV + 1.5% of settings)
10V about threshold
40V peak
Threshold accuracy*
Input dynamic range
Maximum input voltage
+5V Accessory current
Channel assignment
1/3 amp maximum per pod
Each group of 34 channels can be assigned to
Analyzer 1, Analyzer 2 or remain unassigned
2 GHz Timing Zoom (Agilent 16716A, 16717A, 16740A, 16741A, 16742A, 16750A, 16751A, 16752A only)
Timing analysis sample rate
Sample period accuracy
Channel-to-channel skew
Time interval accuracy
2 GHz/1 GHz/500 MHz/250 MHz
50 ps
< 1.0 ns
(sample period + channel-to-channel skew + 0.01% of
time interval reading)
Memory depth
Trigger position
16 K
Start, center, end, or user defined
Operating Environment
Temperature
Agilent 16700 Series frame: 0˚C to 50˚C (+32˚F to 122˚F)
Probe lead sets and cables: 0˚C to 65˚C (+32˚F to 149˚F)
Humidity
Altitude
80% relative humidity at + 40˚C
Operating 4600 m (15,000 ft)
Non-operating 15,300 m (50,000 ft)
*
All specifications noted by an asterisk are the performance standards against which the product is tested.
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State/Timing Modules Specifications and
Characteristics
Agilent Technologies 16715A, 16716A, 16717A, 16740A, 16741A, 16742A,
16750A, 16751A, 16752A Supplemental Specifications* and Characteristics
State Mode
16715A, 16716A, 16717A
167 Mb/s State Mode
16740A, 16741A, 16742A
16750A, 16751A, 16752A
200 Mb/s State Mode
Maximum state acquisition rate on
each channel
167 Mb/s
200 Mb/s
Channel count
68 per module
340
68 per module
340
Maximum channels on a single
time base and trigger
Number of independent analyzers
2, can be set up in state or timing modes
5.988 ns
2, can be set up in state or timing modes
5 ns
Minimum master to
master clock time* [1]
Minimum master to slave clock time
Minimum slave to master clock time
Minimum slave to slave clock time
2 ns
2 ns
2 ns
5 ns
2 ns
5.988 ns
Setup/hold time* [1]
(single-clock, single-edge)
2.5 ns window adjustable from 4.5/-2.0 ns to
-2.0/4.5 ns in 100 ps increments per channel
2.5 ns window adjustable from 4.5/-2.0 ns to
-2.0/4.5 ns in 100 ps increments per channel
Setup/hold time* [1]
(multi-clock, multi-edge)
3.0 ns window adjustable from 5.0/-2.0 ns to
-1.5/4.5 ns in 100 ps increments per channel
3.0 ns window adjustable from 5.0/-2.0 ns to
-1.5/4.5 ns in 100 ps increments per channel
Setup/hold time (on individual channels,
after running eye finder)
1.25 ns window
1.25 ns window
Minimum state clock pulse width
Time tag resolution [2]
1.2 ns
1.2 ns
4 ns
4 ns
Maximum time count between states
17 seconds
17 seconds
32
2
32
2
Maximum state tag count
between states [2]
Number of state clocks/qualifiers
Maximum memory depth
4
4
16716A: 512K
16715A, 16717A: 2M
16740A: 1M
16741A: 4M
16742A: 16M
16750A: 4M
16751A: 16M
16752A: 32M
Maximum trigger sequence speed
Maximum trigger sequence levels
167 MHz
16
200 MHz
16
*
All specifications noted by an asterisk are the performance standards against which the product is tested.
[1] Tested at input signal VH=-0.9V, VL=-1.7V, Slew rate=1V/ns, and threshold=-1.3V.
[2] Time or state tags halve the acquisition memory when there are no unassigned pods.
90
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State/Timing Modules Specifications and
Characteristics
Agilent Technologies 16715A, 16716A, 16717A, 16740A, 16741A, 16742A,
16750A, 16751A, 16752A Supplemental Specifications* and Characteristics (continued)
State Mode
16715A, 16716A, 16717A
167 Mb/s State Mode
16740A, 16741A, 16742A
16750A, 16751A, 16752A
200 Mb/s State Mode
Trigger sequence level branching
Trigger position
4 way arbitrary “IF/THEN/ELSE” branching
Start, center, end, or user defined
4 way arbitrary “IF/THEN/ELSE” branching
Start, center, end, or user defined
Trigger resources
16 Patterns evaluated as =, ≠, >, <, ≥, ≤
15 Ranges evaluated as in range, not in range
(2 Timers per module) -1
16 Patterns evaluated as =, ≠, >, <, ≥, ≤
15 Ranges evaluated as in range, not in range
(2 Timers per module) -1
2 Global counters
2 Global counters
1 Occurrence counter per sequence level
4 Flags
1 Occurrence counter per sequence level
4 Flags
Trigger resource conditions
Trigger actions
Arbitrary Boolean combinations
Arbitrary Boolean combinations
Goto
Goto
Trigger and fill memory
Trigger and goto
Trigger and fill memory
Trigger and goto
Store/don’t store sample
Turn on/off default storing
Timer start/stop/pause/resume
Global counter increment/reset
Occurrence counter reset
Flag set/clear
Store/don’t store sample
Turn on/off default storing
Timer start/stop/pause/resume
Global counter increment/reset
Occurrence counter reset
Flag set/clear
Store qualification
Default and per sequence level
16,777,215
Default and per sequence level
16,777,215
Maximum global counter
Maximum occurrence counter
Maximum pattern/range width
Timers value range
16,777,215
16,777,215
32 bits
32 bits
100 ns to 5497 seconds
5 ns
100 ns to 5497 seconds
5 ns
Timer resolution
Timer accuracy
10 ns + .01%
70 ns
10 ns + .01%
70 ns
Timer reset latency
Data in to trigger out (BNC port)
Flag set/reset to evaluation
150 ns, typical
110 ns, typical
150 ns, typical
110 ns, typical
*
All specifications noted by an asterisk are the performance standards against which the product is tested.
91
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State/Timing Modules Specifications and
Characteristics
Agilent Technologies 16715A, 16716A, 16717A, 16740A, 16741A, 16742A,
16750A, 16751A, 16752A Supplemental Specifications* and Characteristics (continued)
State Mode
16715A, 16716A, 16717A
167 Mb/s State Mode
16750A, 16751A, 16752A
400 Mb/s State Mode
Maximum state acquisition rate
on each channel
333 Mb/s
400 Mb/s
Channel count
(Number of modules x 68) - 34
306
(Number of modules x 68) - 34
306
Maximum channels on a single
time base and trigger
Number of independent analyzers
1, when 333 MHz state mode is selected
the second analyzer is turned off
1, when 400 MHz state mode is selected
the second analyzer is turned off
Minimum master to master clock time* [1]
3.003 ns
2.5 ns
Setup/hold time* [1]
(single-clock, single-edge)
2.5 ns window adjustable from 4.5/-2.0 ns to
-2.0/4.5 ns in 100 ps increments per channel
2.5 ns window adjustable from 4.5/-2.0 ns to
-2.0/4.5 ns in 100 ps increments per channel
Setup/hold time* [1]
(single-clock, multi-edge)
3.0 ns window adjustable from 5.0/-2.0 ns to
-1.5/4.5 ns in 100 ps increments per channel
3.0 ns window adjustable from 5.0/-2.0 ns to
-1.5/4.5 ns in 100 ps increments per channel
Setup/hold time (on individual channels
after running eye finder)
1.25 ns window
1.25 ns window
Minimum state clock pulse width
Time tag resolution [2]
1.2 ns
1.2 ns
4 ns
4 ns
Maximum time count between states
Number of state clocks
17 seconds
1
17 seconds
1
Maximum memory depth
16717A: 2M
16750A: 4M
16751A: 16M
16752A: 32M
Maximum trigger sequence speed
Maximum trigger sequence levels
Trigger sequence level branching
Trigger position
333 MHz
400 MHz
15
15
Dedicated next state branch or reset
Start, center, end, or user defined
Dedicated next state branch or reset
Start, center, end, or user defined
*
All specifications noted by an asterisk are the performance standards against which the product is tested.
[1] Tested at input signal VH=-0.9V, VL=-1.7V, Slew rate=1V/ns, and threshold=-1.3V.
[2] Time or state tags halve the acquisition memory when there are no unassigned pods.
92
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State/Timing Modules Specifications and
Characteristics
Agilent Technologies 16715A, 16716A, 16717A, 16740A, 16741A, 16742A,
16750A, 16751A, 16752A Supplemental Specifications* and Characteristics (continued)
State Mode
16715A, 16716A, 16717A
167 Mb/s State Mode
16750A, 16751A, 16752A
400 Mb/s State Mode
Trigger resources
8 Patterns evaluated as =, ≠, >, <, ≥, ≤
4 Ranges evaluated as in range, not in range
2 Occurrence counters
8 Patterns evaluated as =, ≠, >, <, ≥, ≤
4 Ranges evaluated as in range, not in range
2 Occurrence counters
4 Flags
4 Flags
Trigger resource conditions
Trigger actions
Arbitrary Boolean combinations
Arbitrary Boolean combinations
Goto
Goto
Trigger and fill memory
Trigger and fill memory
Store qualification
Default
Default
Maximum occurrence counter
Maximum pattern/range width
Data in to trigger out (BNC port)
Flag set/reset to evaluation
16,777,215
32 bits
16,777,215
32 bits
150 ns, typical
110 ns, typical
150 ns, typical
110 ns, typical
Timing Mode
16715A, 16716A, 16717A
16740A, 16741A, 16742A, 16750A, 16751A, 16752A
Timing analysis sample rate
(half/full channel)
667/333 MHz
800/400 MHz
Channel count
68 per module
340
68 per module
340
Maximum channels on
a single time base and trigger
Number of independent analyzers
Sample period (full channel)
Sample period (half channel)
2, can be setup in state or timing modes
2, can be setup in state or timing modes
3 ns to 1 ms
1.5 ns
2.5 ns to 1 ms
1.25 ns
Minimum data pulse width
for data capture
Conventional timing
Transitional timing
For trigger sequencing
1.75 ns
3.9 ns
6.1 ns
1.5 ns
3.8 ns
5.1 ns
Sample period accuracy
Channel-to-channel skew
Time interval accuracy
(100 ps + .01% of sample period)
< 1.5 ns
(100 ps + .01% of sample period)
< 1.5 ns
(sample period + channel-to-channel
skew + .01% of time interval reading)
(sample period + channel-to-channel
skew + .01% of time interval reading)
Minimum detectable glitch
1.5 ns
1.5 ns
Memory depth (half/full channel)
16716A: 1M/512K
16750A: 8/4M
16715A, 16717A: 4/2M
16751A: 32/16M
16752A: 64/32M
*
All specifications noted by an asterisk are the performance standards against which the product is tested.
93
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State/Timing Modules Specifications and
Characteristics
Agilent Technologies 16715A, 16716A, 16717A, 16740A, 16741A, 16742A, 16750A,
16751A, 16752A Supplemental Specifications* and Characteristics (continued)
Timing Mode (continued)
16715A, 16716A, 16717A
16740A, 16741A, 16742A
16750A, 16751A, 16752A
Maximum trigger sequence speed
Maximum trigger sequence levels
Trigger sequence level branching
Trigger position
167 MHz
200 MHz
16
16
4 way arbitrary “IF/THEN/ELSE” branching
Start, center, end, or user defined
4 way arbitrary “IF/THEN/ELSE” branching
Start, center, end, or user defined
Trigger resources
16 Patterns evaluated as =, ≠, >, <, ≥, ≤
15 Ranges evaluated as in range, not in range
2 Edge/glitch
16 Patterns evaluated as =, ≠, >, <, ≥, ≤
15 Ranges evaluated as in range, not in range
2 Edge/glitch
(2 Timers per module) -1
(2 Timers per module) -1
2 Global counters
2 Global counters
1 Occurrence counter per sequence level
4 Flags
1 Occurrence counter per sequence level
4 Flags
Trigger resource conditions
Trigger actions
Arbitrary Boolean combinations
Arbitrary Boolean combinations
Goto
Goto
Trigger and fill memory
Trigger and goto
Trigger and fill memory
Trigger and goto
Timer start/stop/pause/resume
Global counter increment/reset
Occurrence counter reset
Flag set/clear
Timer start/stop/pause/resume
Global counter increment/reset
Occurrence counter reset
Flag set/clear
Maximum global counter
Maximum occurrence counter
Maximum pattern/range width
Timer value range
16,777,215
16,777,215
16,777,215
16,777,215
32 bits
32 bits
100 ns to 5497 seconds
5 ns
100 ns to 5497 seconds
5 ns
Timer resolution
Timer accuracy
10 ns + .01%
10 ns + .01%
Greater than duration
Less than duration
6 ns to 100 ms in 6 ns increments
12 ns to 100 ms in 6 ns increments
70 ns
6 ns to 100 ms in 6 ns increments
12 ns to 100 ms in 6 ns increments
70 ns
Timer reset latency
Data in to trigger out (BNC port)
Flag set/reset to evaluation
150 ns, typical
150 ns, typical
110 ns, typical
110 ns, typical
*
All specifications noted by an asterisk are the performance standards against which the product is tested.
94
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State/Timing Modules Specifications and
Characteristics
Agilent Technologies 16760A
Supplemental Specifications* and Characteristics
Probes
E5378A Single-ended
E5379A Differential
E5380A Mictor
E5382A Single-Ended Flying Leads
Input resistance and
capacitance
Refer to figure 6.14
Refer to figure 6.14
Refer to figure 6.14
Refer to figure 6.15
Maximum state data
rate supported
1.5 Gb/s
1.5 Gb/s
600 Mb/s
1.5 Gb/s
Mating connector
Agilent part number
1253-3620 [1]
Agilent part number
1253-3620 [1]
Amp Mictor 38 [2]
None required
+
-
Minimum voltage swing
Input dynamic range
Threshold accuracy
Threshold range
250 mV p-p
V
- V >= 200 mV p-p
in
300 mV p-p
250 mV p-p
in
-3 Vdc to +5 Vdc
-3 Vdc to +5 Vdc
-3 Vdc to +5 Vdc
-3 Vdc to +5 Vdc
+/- (30 mV + 1% of setting)* +/- (30 mV + 1% of setting) [3] +/- (30 mV + 1% of setting) +/- (30 mV + 1% of setting)
-3.0 V to +5.0 V
-3.0 V to +5.0 V
-3.0 V to +5.0 V
N/A
-3.0 V to +5.0 V
N/A
-3.0 V to +5.0 V
N/A
User-supplied threshold
input range
User-supplied threshold
input resistance
>= 100K ohms
N/A
N/A
N/A
Threshold control options • User-provided input
• Adjustable from user
If operated single-ended
(minus inputs grounded),
the threshold can be adjusted
from the user interface
Adjustable from user
interface
Adjustable from user
interface
interface
Maximum nondestructive +/-40 Vdc
input voltage
+/-40 Vdc
+/-40 Vdc
+/-40 Vdc
Maximum input slew rate 5 V/ns
5 V/ns
5 V/ns
5 V/ns
Clock input
Differential
Differential
Single-ended
Differential
Number of inputs [4]
34 (32 data and 2 clock/data) 17 (16 data and 1 clock/data)
34 (32 data and 2 clock/data) 17 (16 data and 1 clock/data)
*
All specifications noted by an asterisk are the performance standards against which the product is tested.
[1] A support shroud, Agilent part number 16760-02302 (for boards up to 0.062" thick) or 16760-02303 (for boards up to 0.120" thick) is recommended.
A kit of 5 shrouds and 5 connectors is available as Agilent part number 16760-68702 (for boards up to 0.062" thick) or 16760-68703 (for boards up to 0.120" thick).
[2] A kit of 5 Amp Mictor connectors and 5 support shrouds is available, Agilent part number E5346-68701.
A support shroud is available separately, Agilent part number E5346-44701.
[3] If operated single-ended (minus inputs grounded), the threshold can be adjusted from the user interface.
[4] Refer to specifications on specific modes of operation for details on how inputs can be used.
R1
215
121
C1
0.7pF
R2
20k
1pF
0.6pF
30
20k
+0.75 V
+0.75 V
Figure 6.15. E5382A input equivalent probe load, with
5cm damped wire (see user’s guide for load models
with other accessories).
Model Number
E5378A, E5379A
E5380A
C1
R1
R2
30
60
1.5pF
3pF
120
120
Figure 6.14. E5378A, E5379A, E5380A input
equivalent probe load.
95
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State/Timing Modules Specifications and
Characteristics
Agilent Technologies 16760A
Supplemental Specifications* and Characteristics (continued)
Synchronous Data Sampling
tWidth
Figure 6.17. Data Sampling.
Individual
Data Channel
vHeight
Data Eye
tSetup tHold
vThreshold*
—0V—
Sampling
Position
*User Adjustable
tSample*
Clock Channel
Note (1)
Specifications for Each Input
Parameter
Minimum
Description/Notes
800, 1250, 1500 Mb/s modes
200, 400 Mb/s modes
Data
to Clock tSetup
tHold
tWidth*
500 ps
250 ps
250 ps
1.25 ns
625 ps
625 ps
Eye width in system under test [2]
Data setup time required before tSample
Data hold time required after tSample
All
Inputs
vHeight [1]
100mV
250 mV
100mV
250 mV
E5379A 100-pin differential probe [3]
E5378A 100-pin single-ended probe [4],
E5382A single-ended flying-lead probe set
E5380A 38-pin single-ended probe
300mV
300mV
User Adjustable Settings for Each Input
Parameter
Adjustment Range
1500 Mb/s mode
1250 Mb/s mode
800 Mb/s mode
400 Mb/s mode
200 Mb/s mode
Data
to Clock
Adjustment Resolution
tSample [5]
10 ps
0 to +4 ns
10 ps
-2.5 to +2/5 ns
10 ps
-2.5 to +2/5 ns
100 ps
-3.2 to +3.2 ns
100 ps
-3.5 to +3 ns
All
Inputs
vThreshold [6]
10 mV resolution
-3 to +5 V
10 mV resolution
-3 to +5 V
10 mV resolution
-3 to +5 V
10 mV resolution
-3 to +5 V
10 mV resolution
-3 to +5 V
*
All specifications noted by an asterisk in the table are the performance standards against which the product is tested.
[1] The analyzer can be configured to sample on the rising edge, the falling edge, or both edges of the clock. If both edges are used with a single ended clock input, take care to set the
clock threshold accurately to avoid phase error.
[2] Eye width and height are specified at the probe tip. Eye width as measured by eye finder in the analyzer may be less, and still sample reliably.
[3] For each side of a differential signal.
vHeight
pSignal
——0V—— 2X vHeight
⌺
vHeight
nSignal
[4] The clock inputs in the E5378A and the E5382A may be connected differentially or single ended. Use the E5379A vHeight spec for clock channel(s) connected differentially.
[5] Sample positions are independently adjustable for each data channel input. A negative sample position causes the input to be synchronously sampled by that amount before each
active clock edge. A positive sample position causes the input to be synchronously sampled by that amount after each active clock edge. A sampling position of zero causes synchro-
nous sampling coincident with each active clock edge.
[6] Threshold applies to single-ended input signals. Thresholds are independently adjustable for the clock input of each pod and for each set of 16 data inputs for each pod. Threshold lim-
its apply to both the internal reference and to the external reference input on the E5378A.
96
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State/Timing Modules Specifications and
Characteristics
Agilent Technologies 16760A
Supplemental Specifications* and Characteristics (continued)
Synchronous state analysis
1.5 Gb/s mode
1.25 Gb/s mode
800 Mb/s mode
400 Mb/s mode
200 Mb/s mode
Maximum data rate
on each channel
E5378A, E5379A probes:
1.5 Gb/s
E5378A, E5379A probes:
1.25 Gb/s
E5378A, E5379A, E5382A
probes: 800 Mb/s
400 Mb/s
200 Mb/s
E5380A probe: 600 Mb/s
Minimum clock interval,
active edge to active edge*
667 ps
800 ps
E5378A, E5379A probes:
1.25 ns
2.5 ns
5 ns
E5380A probe: 1.67 ns
Minimum state clock pulse
width with clock polarity
rising or falling
N/A
N/A
E5378A, E5379A probes:
600 ps
E5380A probe: 800 ps
1.5 ns
1.5 ns
Clock periodicity
Clock must be periodic
Clock must be periodic
Periodic or aperiodic
Periodic or aperiodic
Periodic or aperiodic
Number of clocks
Clock polarity
1
1
1
1
1
Both edges
Both edges
750 ps
Rising, falling, or both
Rising, falling, or both
Rising, falling, or both
Minimum data pulse width
600 ps
E5378A, E5379A, E5382A
probes: 750 ps
1.5 ns
1.5 ns
E5380A probe: 1.5 ns
Number of channels [1]
• With time tags
16 x (number of modules) - 16 x (number of modules) -
34 x (number of modules) -
16
34 x (number of modules) - 34 x (number of modules)
16
8
8
• Without time tags
16 x (number of modules)
80 (5 modules)
16 x (number of modules)
80 (5 modules)
34 x (number of modules)
170 (5 modules)
34 x (number of modules) 34 x (number of modules)
Maximum channels on a
153 (5 modules)
170 (5 modules)
single time base and trigger
Maximum memory depth
Time tag resolution
128M samples
4 ns [2]
128M samples
4 ns [2]
64M samples
4 ns [2]
32M samples
4 ns [2]
32M samples
4 ns
Maximum time count
between states
17 seconds
17 seconds
17 seconds
17 seconds
17 seconds
Trigger resources
3 Patterns on each pod
evaluated as =, ≠, >, <,
≥, ≤ on one pod; or
evaluated as =, ≠ across
multiple pods; or
1 range on each pod
4 Flags
3 Patterns on each pod
evaluated as =, ≠, >, <,
≥, ≤ on one pod; or
evaluated as =, ≠ across
multiple pods; or
1 range on each pod
4 Flags
4 Patterns on each pod
evaluated as =, ≠, >, <,
≥, ≤ on one pod; or
evaluated as =, ≠ across
multiple pods; or
2 ranges on each pod
4 Flags
8 Patterns evaluated as 16 Patterns evaluated as
=, ≠, >, <, ≥, ≤ =, ≠, >, <, ≥, ≤
4 Ranges evaluated as 15 Ranges evaluated as
in range, not in range in range, not in range
2 Occurrence counters Timers: 2 x (number of
4 Flags
Arm in
modules) – 1
2 Global counters
1 Occurrence counter per
sequence level
4 Flags
Arm in
Arm in
Arm in
Arm in
Trigger actions
Trigger and fill memory
Trigger and fill memory
Trigger and fill memory
Goto
Goto
Trigger and fill memory Trigger and fill memory
Trigger and goto
Store/don’t store sample
Turn default storing on/off
Timer start/stop/pause/resume
Global counter increment/reset
Occurrence counter reset
Flag set/clear
*
All specifications noted by an asterisk are the performance standards against which the product is tested.
[1] In 1.25 Gb/s mode, only the even-numbered channels (0, 2, 4, etc.) are acquired.
[2] The resolution of the hardware used to assign time tags is 4 ns. Times of intermediate states are calculated.
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State/Timing Modules Specifications and
Characteristics
Agilent Technologies 16760A
Supplemental Specifications and Characteristics (continued)
Synchronous state
analysis (continued)
1.5 Gb/s mode (only
available with E5378A
and E5379A probes)
1.25 Gb/s mode (only
available with E5378A
and E5379A probes)
800 Mb/s mode
400 Mb/s mode
200 Mb/s mode
Maximum trigger
sequence levels
2
2
4
16
16
Maximum trigger
sequencer speed
1.5 Gb/s
Default
1.25 Gb/s
Default
800 MHz
Default
400 MHz
Default
200 MHz
Store qualification
Default and per
sequence level
Maximum global counter
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
16,777,215
16,777,215
Maximum occurrence
counter
Maximum pattern/range
term width
32 bits [3]
32 bits [3]
32 bits [3]
32 bits [3]
32 bits [3]
Timer value range
Timer resolution
Timer accuracy
N/A
N/A
N/A
N/A
150 ns
N/A
N/A
N/A
N/A
150 ns
N/A
N/A
N/A
N/A
150 ns
N/A
N/A
N/A
N/A
150 ns
100 ns to 4397 seconds
4 ns
(10 ns + 0.01% of value)
Timer reset latency
65 ns
Data in to BNC port out
latency
150 ns
Flag set/reset to evaluation
latency
N/A
N/A
N/A
N/A
110 ns
[1] In 1.25 Gb/s mode, only the even-numbered channels (0, 2, 4, etc.) are acquired.
[2] The resolution of the hardware used to assign time tags is 4 ns. Times of intermediate states are calculated.
[3] Maximum label width is 32 bits. Wider patterns can be created by “Anding” multiple labels together.
Asynchronous Timing Analysis
Maximum timing analysis sample rate
Number of channels
Conventional Timing Analysis
800 MHz
Transitional Timing Analysis
400 MHz
34 x (number of modules)
Sampling rates < 400 MHz: 34 x (number of modules)
Sampling rates = 400 MHz:
34 x (number of modules) - 17 [1]
Maximum channels on a
170 (5 modules)
170 (5 modules)
single time base and trigger
Sample period
Memory Depth
1.25 ns
2.5 ns to 1 ms [1]
32 M Samples [1]
64 M Samples
[1] With all pods assigned in transitional/store qualified timing, minimum sample period is 5 ns and maximum memory depth is 16 M samples.
98
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State/Timing Modules Specifications and
Characteristics
Agilent Technologies 16760A
Supplemental Specifications and Characteristics (continued)
Asynchronous Timing Analysis
(continued)
Conventional Timing Analysis
Transitional Timing Analysis
Sample period accuracy
Channel-to-channel skew
Time interval accuracy
(250 ps + 0.01% of sample period)
< 1.5 ns
(250 ps + 0.01% of sample period)
< 1.5 ns
[sample period + (channel-to-channel skew) +
(0.01% of time interval)]
[sample period + (channel-to-channel skew) +
(0.01% of time interval)]
Minimum data pulse width
1.5 ns for data capture
3.8 ns for data capture
5.1 ns for trigger sequencing
5.1 ns for trigger sequencing
Maximum trigger sequencer speed
Trigger resources
200 MHz
200 MHz
16 Patterns evaluated as =, ≠, >, <, ≥, ≤
15 Ranges evaluated as in range, not in range
2 Edge/glitch
16 Patterns evaluated as =, ≠, >, <, ≥, ≤
15 Ranges evaluated as in range, not in range
2 Edge/glitch
(2 Timers per module) -1
(2 Timers per module) -1
2 Global counters
2 Global counters
1 Occurrence counter per sequence level
4 Flags, Arm In
1 Occurrence counter per sequence level
4 Flags, Arm In
Trigger resource conditions
Trigger actions
Arbitrary Boolean combinations
Arbitrary Boolean combinations
Goto
Goto
Trigger and fill memory
Trigger and goto
Trigger and fill memory
Trigger and goto
Timer start/stop/pause/resume
Global counter increment/reset
Occurrence counter reset
Timer/start/stop/pause/resume
Global counter increment/reset
Occurrence counter reset
Maximum global counter
Maximum occurrence counter
Timer value range
16,777,215
16,777,215
16,777,215
16,777,215
100 ns to 5497 seconds
100 ns to 5497 seconds
Timer resolution
5 ns
5 ns
Timer accuracy
(10 ns + 0.01%)
(10 ns + 0.01%)
Greater than duration
Less than duration
5 ns to 83 ms in 5 ns increments
5 ns to 83 ms in 5 ns increments
10 ns to 83 ms in 5 ns increments
10 ns to 83 ms in 5 ns increments
Timer reset latency
60 ns
60 ns
Data in to BNC port out delay latency
150 ns
110 ns
150 ns
110 ns
Flag set/reset to evaluation latency
Environmental
Operating temperature
0 deg C to 45 deg C
99
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State/Timing Modules Specifications and
Characteristics
Agilent Technologies 16760A
Supplemental Specifications and Characteristics (continued)
Eye scan mode
1.5 Gb/s mode
1.5 Gb/s
800 Mb/s mode
800 Mb/s
Maximum clock rate
Sample position range relative
to clock
+5ns to 10 ns
-4 ns to +4 ns
Sample (time) position resolution
Sample position (time) accuracy
Number of channels
12 ps
12 ps
+/- (50 ps + 0.01 * sample position)
16*(number of modules)
-3.0 Vdc to +5.0 Vdc
-3.0 Vdc to +5.0 Vdc
2 mV
+/- (50 ps + 0.01 * sample position)
34*(number of modules)-1
-3.0 Vdc to +5.0 Vdc
-3.0 Vdc to +5.0 Vdc
2 mV
Input dynamic range
Threshold range
Threshold resolution
Threshold accuracy
+/-(30 mV + 1% of setting)
150 ps
+/-(30 mV + 1% of setting)
150 ps
Equivalent rise time [1]
Equivalent bandwidth [1]
2.33 GHz
2.33 GHz
Minimum detectable pulse width
at minimum signal amplitude [1]
500 ps
750 ps
Jitter
10 ps RMS
25 mV p-p
100 ps
10 ps RMS
25 mV p-p
100 ps
Noise floor
Channel-to-channel skew, maximum
between any two channels
[1] E5378A, E5379A, and E5382A probes only.
Timing
Channels available
Qualified eye scan mode
The analyzer samples the qualifica-
tion signal at the beginning of each
clock cycle (i.e. at the first of each
pair of data transfers). The analyzer
can be configured to treat either the
rising edge or the falling edge of the
clock as the first edge of each clock
cycle. The qualifier should remain
stable for the entire duration of
each burst.
The following channels are not
available for qualified eye scan
measurements.
In the qualified eye scan mode, a
single qualifier input defines what
clock cycles are to be acquired and
what cycles are to be ignored in eye
scan acquisition.
Master module, Pod 1
Master module, Pod 2, Bit 0, Bit 14,
Bit 1, Bit 15, Bit 2, K-clock
(the qualifier input itself).
All channels on all boards other than
the master board are available for
qualified eye scans.
Qualified eye scan is supported in
the 16760A in 800 Mb/s eye scan
mode only. Qualified eye scan is
only available for double-edged clock
(double-data-rate).
The qualifier must be pipelined
(delayed) by one clock cycle before
transmittal to the analyzer.
100
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Oscilloscope Modules Specifications and
Characteristics
16534A Specifications*
Bandwidth
dc to 500 MHz
dc offset accuracy
(1% of offset + 2% of full scale)
(1.5% of full scale + offset accuracy)
[(0.005% of D T) + (2E–6 x delay setting) + 100 ps]
dc voltage measurement accuracy
Time interval measurement
accuracy at maximum sampling rate,
on a single scope card, on a single
acquisition
Trigger sensitivity (See notes)
• dc to 50 MHz
• 50 MHz to 500 MHz
• 0.06 full scale
• 0.13 full scale
Input resistance
1 MΩ 1% 50 Ω 1%
*
Specifications refer to the input to the BNC connector
Notes:
•
•
Specifications apply only within 10° C of the temperature at which the most recent calibration was performed.
Specifications apply only after operational accuracy calibration is performed in the frame in which the
oscilloscope module is installed.
•
Display magnification is used below 56 mV full scale. For sensitivities from 16 mV to 56 mV full scale, full scale is
defined as 56 mV.
Characteristics
General
Maximum sampling rate
Number of channels
2 GSa/s
• 2 to 8 using the same
time base and trigger.
• Up to 10 channels may be installed in a single
16700 frame, or up to 20 in a single system using a
16701 expansion frame.
Waveform record length
32768 points
101
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Oscilloscope Modules Specifications and
Characteristics
16534A Characteristics*
Vertical (Voltage)
Vertical sensitivity range
Vertical resolution
16 mV full scale to 40 V full scale
8 bits full scale
Rise time (calculated from bandwidth)
dc gain accuracy
700 ps
(1.25% of full scale + 0.08% per °C difference from
calibration temperature)
dc offset range
Vertical sensitivity
Offset range
• 16 mV full scale to 400 mV full scale
• 400 mV full scale to 2.0 V full scale
• 2.0 V full scale to 10 V full scale
• 10 V full scale to 40 V full scale
•
•
•
•
2 V
10 V
50 V
250 V
Probe attenuation
Any ratio from 1:1E-9 to 1:1E+6
Channel-to-channel isolation (with channel sensitivities equal)
• dc–50 MHz
• 50 MHz–500 MHz
• 40 dB
• 30 dB
Maximum safe input voltage
• 1 MΩ
• 50 Ω
•
250 V dc + peak ac (<10 kHz)
• 5 Vrms
*
Characteristics refer to the input at the BNC connector
102
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Oscilloscope Modules Specifications and
Characteristics
16534A Characteristics
Horizontal (Time)
Time base ranges
0.5 ns/div to 5 s/div
10 ps
Time base resolution
Delay range
• pretrigger
• posttrigger
• -32 K x sample period
• 320 ms or 1.6E7 x sample period, whichever is greater
Time interval measurement accuracy
forsampling rates other than maximum,
for bandwidth-limited signals [signal
rise time > 1.4/(sampling rate)], on a
single card, on a single acquisition
{(0.005% of ∆ T) + (2E–6 x delay setting)
+ [0.15/(sample rate)]}
Time interval measurement accuracy
for 2, 3, or 4 Agilent 16533As or 16534As
operating on a single time base, for
measurements made between channels
on different cards, at maximum
sampling rate
[(0.005% of ∆T) + (2E–6 x delay setting) + 300 ps
Trigger
Trigger level range (See notes)
1.5 x full scale from center of screen
Trigger modes
• Immediate
• Edge
• Triggers immediately after arming condition is met
• Triggers on rising or falling edge on channel 1 or
channel 2
• Pattern
• Triggers on entering or exiting a specified pattern
across both channels
• Auto condition
• Events delay
• Intermodule
• Self-triggers if trigger is not satisfied within
approximately 50 ms after arming
• The trigger can be set to occur on the nth occurrence
of an edge or pattern, n ≤ 32000
• Arms another measurement module or activates the
port out BNC connector when the trigger condition is
met
Notes:
•
•
Specifications apply only within 10° C of the temperature at which the most recent calibration was performed.
Specifications apply only after operational accuracy calibration is performed in the frame in which the
oscilloscope module is installed.
•
Display magnification is used below 56 mV full scale. For sensitivities from 16 mV to 56 mV full scale, full scale is
defined as 56 mV.
103
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Pattern Generation Modules Specifications
and Characteristics
16720A Pattern Generator Characteristics
Maximum memory depth
16 MVectors
Number of output channels at ≤ 300 MHz clock
Number of output channels at ≤ 180 MHz clock
Number of output channels at ≤ 200 MHz clock
Number of output channels at ≤ 100 MHz clock
Number of different macros
24
48
24
48
100
Maximum number of lines in a macro
Maximum number of parameters in a macro
Maximum number of macro invocations
Maximum loop count in a repeat loop
Maximum number of repeat loop invocations
Maximum number of "Wait" event patterns
Number of input lines to define a pattern
Maximum number of modules in a system
Maximum width of a vector (in a 5 module system)
Maximum width of a label
1024
10
1000
20000
1000
4
3
5
240 bits
32 bits
126
Maximum number of labels
Maximum number of vectors in binary format
Minimum number of vectors in binary format
16 MVectors
4096
Lead Set Characteristics
Agilent 10474A 8-channel
probe lead set
Provides most cost effective lead set for the 16522A and
16720A clock and data pods. Grabbers are not included.
Lead wire length is 12 inches.
Agilent 10347A 8-channel
probe lead set
Provides 50 Ω coaxial lead set for unterminated signals,
required for 10465A ECL Data Pod (unterminated).
Grabbers are not included.
Agilent 10498A 8-channel
probe lead set
Provides most cost effective lead set for the 16522A and
16720A clock and data pods. Grabbers are not included.
Lead wire length is 6 inches.
104
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Pattern Generation Modules Specifications
and Characteristics
Data Pod Characteristics
Note: Data Pod output parametrics depend on the output driver and the impedance load of the target
system. Check the device data book for the specific drivers listed for each pod.
Agilent 10461A TTL Data Pod
Output type
10H125 with 100 Ω series
200 MHz
Maximum clock
Skew [1]
typical < 2 ns; worst case = 4 ns
Agilent 10474A
Recommended lead set
100 Ω
ECL/TTL
10H125
Agilent 10462A 3-State TTL/CMOS Data Pod
Output type
74ACT11244 with 100 Ω series; 10H125 on non 3-state channel 7 [2]
3-state enable
Maximum clock
Skew [1]
negative true, 100 KΩ to GND, enabled on no connect
100 MHz
typical < 4 ns; worst case = 12 ns
Agilent 10474A
Recommended lead set
100 Ω
74ACT11244
Agilent 10464A ECL Data Pod (terminated)
Output type
10H115 with 330 Ω pulldown, 47 Ω series
Maximum clock
Skew [1]
300 MHz
typical < 1 ns; worst case = 2 ns
Agilent 10474A
Recommended lead set
42 Ω
10H115
348 Ω
– 5.2 V
105
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Pattern Generation Modules Specifications
and Characteristics
Agilent 10465A ECL Data Pod (unterminated)
Output type
10H115 (no termination)
300 MHz
Maximum clock
Skew [1]
typical < 1 ns; worst case = 2 ns
Agilent 10347A
Recommended lead set
10H115
Agilent 10466A 3-State TTL/3.3 volt Data Pod
Output type
74LVT244 with 100 Ω series; 10H125 on non 3-state channel 7 [2]
3-state enable
Maximum clock
Skew [1]
negative true, 100 KΩ to GND, enabled on no connect
200 MHz
typical < 3 ns; worst case = 7 ns
Agilent 10474A
Recommended lead set
100 Ω
74LVT244
[1] Typical skew measurements made at pod connector with approximately 10 pF/50 KΩ load to GND; worst case
skew numbers are a calculation of worst case conditions through circuits. Both numbers apply to any channel
within a single or multiple module system.
[2] Channel 7 on the 3-state pods has been brought out in parallel as a non 3-state signal. By looping this output back
into the 3-state enable line, the channel can be used as a 3-state enable.
106
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Pattern Generation Modules Specifications
and Characteristics
Agilent 10469A 5 volt PECL Data Pod
Output type
100EL90 (5V) with 348 ohm pulldown to ground and 42 ohm in series
Maximum clock
Skew [1]
300 MHz
typical < 500 ps; worst case = 1 ns
Agilent 10498A
Recommended lead set
42 Ω
100EL90
348 Ω
Agilent 10471A 3.3 volt LVPECL Data Pod
Output type
100LVEL90 (3.3V) with 215 ohm pulldown to ground and
42 ohm in series
Maximum clock
Skew [1]
300 MHz
typical < 500 ps; worst case = 1 ns
Agilent 10498A
Recommended lead set
42 Ω
100LVEL90
215 Ω
Agilent 10473A 3-State 2.5 Volt Data Pod
Output type
74AVC16244
3-state enable
Maximum clock
Skew [1]
negative true, 38 KΩ to GND, enabled on no connect
300 MHz
typical < 1.5 ns; worst case = 2 ns
Agilent 10498A
Recommended lead set
74AVC16244
[1] Typical skew measurements made at pod connector with approximately 10 pF/50 KΩ load to GND; worst case
skew numbers are a calculation of worst case conditions through circuits. Both numbers apply to any channel
within a single or multiple module system.
[2] Channel 7 on the 3-state pods has been brought out in parallel as a non 3-state signal. By looping this output back
into the 3-state enable line, the channel can be used as a 3-state enable.
107
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Pattern Generation Modules Specifications
and Characteristics
Agilent 10476A 3-State 1.8 Volt Data Pod
Output type
74AVC16244
3-state enable
Maximum clock
Skew [1]
negative true, 38 KΩ to GND, enabled on no connect
300 MHz
typical < 1.5 ns; worst case = 2 ns
Agilent 10498A
Recommended lead set
74AVC16244
Agilent 10483A 3-State 3.3 Volt Data Pod
Output type
74AVC16244
3-state enable
Maximum clock
Skew [1]
negative true, 38 KΩ to GND, enabled on no connect
300 MHz
typical < 1.5 ns; worst case = 2 ns
Agilent 10498A
Recommended lead set
74AVC16244
Agilent E8141A LVDS Data Pod
Output type
65LVDS389 (LVDS data lines)
10H125 (TTL non-3-state channel 7)
3-state enable
positive true TTL; no connect=enabled
300 MHz
Maximum clock
Skew
typical < 1 ns; worst case = 2 ns
E8142A
Recommended lead set:
Recommended lead set
Agilent 10498A
65LVDS389
LVDS DATA OUT
ENABLE
°
10 KΩ
3.3 V
3-STATE IN TTL
[1] Typical skew measurements made at pod connector with approximately 10 pF/50 KΩ load to GND; worst case
skew numbers are a calculation of worst case conditions through circuits. Both numbers apply to any channel
within a single or multiple module system.
108
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Pattern Generation Modules Specifications
and Characteristics
Data Cable Characteristics Without a Data Pod
The Agilent 16720A and 16522A data cables without a data pod provide an ECL terminated (1 KΩ to
–5.2V) differential signal (from a type 10E156 or 10E154 driver). These are usable when received by
a differential receiver, preferably with a 100 Ω termination across the lines. These signals should
not be used single ended due to the slow fall time and shifted voltage threshold (they are not ECL
compatible).
–3.25 V
16720A
470 Ω
10E156
or
10E154
Differential
Output
470 Ω
–3.25 V
–5.2 V
16522A
1 kΩ
10E156
or
10E154
Differential
Output
1 kΩ
–5.2 V
109
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Pattern Generation Modules Specifications
and Characteristics
Clock Cable Characteristics Without a Clock Pod
The Agilent 16720A and 16522A clock cables without a clock pod provide an ECL terminated
(1 KΩ to –5.2V) differential signal (from a type 10E164 driver). These are usable when received by a
differential receiver, preferably with a 100 Ω termination across the lines. These signals should not be
used single ended due to the slow fall time and shifted voltage threshold (they are not ECL compatible).
7
10E116
100 Ω
Clock In
8
11, 13, 15
10H125
100 Ω
Wait 1, 2, 3 IN
12, 14, 16
–3.25 V
215 Ω
Clock Out
10E164
215 Ω
–3.25 V
110
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Pattern Generation Modules Specifications
and Characteristics
Clock Pod Characteristics
10460A TTL Clock Pod
Clock output type
Clock output rate
Clock out delay
10H125 with 47 Ω series; true & inverted
100 MHz maximum
approximately 8 ns total in 14 steps (16720A
only); 11 ns maximum in 9 steps (16522A
only)
Clock input type
Clock input rate
Pattern input type
Clock-in to clock-out
Pattern-in to recognition
Recommended lead set
TTL – 10H124
dc to 100 MHz
TTL – 10H124 (no connect is logic 1)
approximately 30 ns
47Ω
CLKout
10H125
10H124
approximately 15 ns + 1 clk period
Agilent 10474A
WAIT
CLKin
10463A ECL Clock Pod
Clock output type
10H116 differential unterminated; and differ-
ential with 330 Ω to –5.2V and 47 Ω series
Clock output rate
Clock out delay
only)
300 MHz maximum
approximately 8 ns total in 14 steps (16720A
only); 11 ns maximum in 9 steps (16522A
Clock input type
Clock input rate
Pattern input type
ECL – 10H116 with 50 KΩ to –5.2v
dc to 300 MHz
ECL – 10H116 with 50 KΩ (no connect is
logic 0)
CLKin
10H116
10H116
50 kΩ
VBB
Clock-in to clock-out
approximately 30 ns
–5.2 V
Pattern-in to recognition
Recommended lead set
approximately 15 ns + 1 clk period
Agilent 10474A
–5.2 V
330 Ω
47 Ω
CLKout
111
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Pattern Generation Modules Specifications
and Characteristics
10468A 5 volt PECL Clock Pod
Clock output type
100EL90 (5V) with 348 ohm pulldown to
ground and 42 ohm in series
Clock output rate
Clock out delay
only)
300 MHz maximum
approximately 8 ns total in 14 steps (16720A
only); 11 ns maximum in 9 steps (16522A
Clock input type
Clock input rate
Pattern input type
100EL91 PECL (5V), no termination
dc to 300 MHz
100EL91 PECL (5V), no termination (no
connect is logic 0)
42 Ω
CLKout
CLKin
100EL90
100EL91
Clock-in to clock-out
approximately 30 ns
348 Ω
Pattern-in to recognition
Recommended lead set
approximately 15 ns + 1 clk period
Agilent 10498A
10470A 3.3 volt LVPECL Clock Pod
Clock output type
100LVEL90 (3.3V) with 215 ohm pulldown to
ground and 42 ohm in series
Clock output rate
Clock out delay
only)
300 MHz maximum
approximately 8 ns total in 14 steps (16720A
only); 11 ns maximum in 9 steps (16522A
Clock input type
Clock input rate
Pattern input type
100LVEL91 LVPECL (3.3V), no termination
dc to 300 MHz
100LVEL91 LVPECL (3.3V), no termination
(no connect is logic 0)
42 Ω
CLKout
CLKin
100LVEL90
100LVEL91
Clock-in to clock-out
approximately 30 ns
215 Ω
Pattern-in to recognition
Recommended lead set
approximately 15 ns + 1 clk period
Agilent 10498A
112
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Pattern Generation Modules Specifications
and Characteristics
10472A 2.5 volt Clock Pod
Clock output type
Clock output rate
Clock out delay
74AVC16244
200 MHz maximum
approximately 8 ns total in 14 steps (16720A
only); 11 ns maximum in 9 steps (16522A
only)
Clock input type
Clock input rate
Pattern input type
Clock-in to clock-out
Pattern-in to recognition
Recommended lead set
74AVC16244 (3.6V max)
dc to 200 MHz
74AVC16244 (3.6V max; no connect is logic 0)
approximately 30 ns
CLKout
74AVC16244
74AVC16244
approximately 15 ns + 1 clk period
Agilent 10498A
WAIT
CLKin
10475A 1.8 volt Clock Pod
Clock output type
Clock output rate
Clock out delay
74AVC16244
200 MHz maximum
approximately 8 ns total in 14 steps (16720A
only); 11 ns maximum in 9 steps (16522A
only)
Clock input type
74AVC16244 (3.6V max)
dc to 200 MHz
Clock input rate
Pattern input type
Clock-in to clock-out
Pattern-in to recognition
Recommended lead set
74AVC16244 (3.6V max; no connect is logic 0)
approximately 30 ns
CLKout
74AVC16244
74AVC16244
approximately 15 ns + 1 clk period
Agilent 10498A
WAIT
CLKin
113
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Pattern Generation Modules Specifications
and Characteristics
10477A 3.3 volt Clock Pod
Clock output type
Clock output rate
Clock out delay
74AVC16244
200 MHz maximum
approximately 8 ns total in 14 steps (16720A
only); 11 ns maximum in 9 steps (16522A
only)
Clock input type
Clock input rate
Pattern input type
Clock-in to clock-out
Pattern-in to recognition
Recommended lead set
74AVC16244 (3.6V max)
dc to 200 MHz
CLKout
74AVC16244 (3.6V max; no connect is logic 0)
approximately 30 ns
74AVC16244
74AVC16244
approximately 15 ns + 1 clk period
Agilent 10498A
WAIT
CLKin
E8140A LVDS Clock Pod
Clock output type
65LVDS179 (LVDS) and 10H125 (TTL)
200 MHz maximum (LVDS and TTL)
approximately 8 ns total in 14 steps
65LVDS179 (LVDS with 100 ohm)
dc to 150 MHz (LVDS)
Clock output rate
Clock out delay
Clock input type
Clock input rate
Pattern input type
Clock-in to clock-out
Pattern-in to recognition
Recommended lead set
10H124 (TTL) (no connect = logic 1)
approximately 30 ns
approximately 15 ns + 1 clk period
Agilent 10498A
10H125
CLK OUT TTL
CLK OUT LVDS
65LBDS179
65LVDS179
°
°
CLK IN LVDS
CLK IN LVDS
100 Ω
10H124
WAIT IN TTL
114
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Ordering Information
Mainframes and Mainframe Accessories
Product Number
Description
Includes
16700B
Modular mainframe with five measurement
module slots and one emulation or multiframe
module slot
•
•
•
•
•
•
One DIN keyboard
One three-button DIN mouse
One ten-conductor, flying lead cable for target control port
Training kit
One internal CD ROM drive
One internal 3.5" floppy drive
16702B
Modular frame with built-in 800x600 LCD display
with touchscreen. Includes five measurement
slots and one emulation or multiframe
module slot
Same as 16700B plus:
•
•
•
12.1” touchscreen display
Display knobs
Dedicated hot keys
16701B
Expansion frame with five measurement module
slots and two emulation module slots. Requires a
16700A/B or 16702A/B
1 ft. and 3 ft. interface cables
1184A Testmobile
4 wheeled equipment cart specifically designed
to carry the 16700 Series logic analyzer,
expansion frame, and monitor
Drawer, keyboard tray, mouse tray, strap for
stabilizing monitor
Mainframe Options
Option
Number
Description
16700B or
16702B
16700A or
16702A
16701B
16701A
001
003
Add 17-inch 1280x1024 monitor
√
√
Performance option. Up to 256 MBytes total system
RAM, 4 MBytes total video RAM.
√
√
(256 MB)
(160 MB)
004*
008
Add external CD-ROM drive and cable
External, auxiliary 18 GByte hard disk drive
Removable internal hard disk
√
√
√
√
√
√
009
012
Multiframe option
0B3
1CM
AXC
ABJ
W17
W30
W50
Add service guide
√
√
Add rack-mount kit (all but 16702B)
Equipment shelf (16702B only)
√
√
√
√
Japanese localization
√
√
√
√
Convert standard warranty to one year on-site warranty
Extend standard warranty to three year return-to-Agilent warranty
Extend standard warranty to five year return-to-Agilent warranty
√
√
√
√
√
√
√
√
√
*
Built-in CD-ROM drive standard on 16700B Series
116
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Ordering Information
E5850A Logic Analyzer - Infiniium Oscilloscope Correlation Time Fixture
Product Number
Description
Includes
E5850A
Logic analyzer - Infiniium oscilloscope time
correlation fixture
All BNC cables needed to connect to logic analyzer and
oscilloscope
• Keyboard tray with adjustable tilt
Agilent 1184A Testmobile
and height
The Agilent 1184A testmobile gives
you a convenient means of organizing
and transporting your logic analysis
system mainframes and accessories.
• Mouse extension on keyboard
tray for either right or left hand
operation
• Locking casters for stability on
uneven surfaces
The testmobile includes the following:
• Strap to stabilize the monitor
• Load limits: Top tray: 68.2 kg
(150.0 lb.) Lower tray: 68.2 kg
(150.0 lb.) Total: 136.4 kg
(300.0 lb.)
• Drawer for accessories (probes,
cables, power cords)
Weight
Max Net
Max Shipping
1184A
48.0 kg (106.0 lb) 59.0 kg (130.0 lbs)
Figure 7.1. Agilent 1184A testmobile cart.
584.2
(23.0)
774.7
(30.5)
243.8
(9.6)
190.5
(7.5)
469.9
(18.5)
482.6
(19.0)
772.2
(30.4)
866.1
254
(34.1)
(10.0)
652.8
(25.7)
594.4
(23.4)
116.8
(4.6)
Dimensions: mm (inches)
Figure 7.2. Agilent 1184A testmobile cart dimensions.
117
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Ordering Information
Measurement Module Compatibility Table
Measurement
Module Category
Model
Number
Description
16700
Series
16600A
Series
16500C*
16500A/B*
State and Timing
16510A*
16510B*
25 MHz State; 100 MHz Timing; 1 K memory depth
35 MHz State; 100 MHz Timing; 1 K memory depth
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
16540A/16541A* 100 MHz State; 100 MHz Timing; 4 K memory depth
16540D/16541D* 100 MHz State; 100 MHz Timing; 16 K memory depth
16542A*
16550A*
16554A*
100 MHz State; 100 MHz Timing; 1 M memory depth
100 MHz State; 500 MHz Timing; 4/8 K memory depth
100 MHz State; 250 MHz Timing; 512 K/1 M memory depth
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
16555A/16555D* 110 MHz State; 500 MHz Timing; 2/4 M memory depth
16556A/16556D* 100 MHz State; 400 MHz Timing; 2/4 M memory depth
16557D
16710A
16711A
16712A
16715A
16716A
140 MHz State; 500 MHz Timing; 2/4 M memory depth
100 MHz State; 500 MHz Timing; 8 K memory depth
100 MHz State; 500 MHz Timing; 32 K memory depth
100 MHz State; 500 MHz Timing; 128 K memory depth
167 MHz State; 667 MHz Timing; 2/4 M memory depth
167 MHz State; 667 MHz Timing; 2 GHz Timing Zoom;
512 K/1 M memory depth
16717A
16718A*
16719A*
16740A
16741A
16742A
16750A
16751A
16752A
16760A
333 MHz State; 667 MHz Timing; 2 GHz Timing Zoom;
2/4 M memory depth
√
√
√
√
√
√
√
√
√
√
333 MHz State; 667 MHz Timing; 2 GHz Timing Zoom;
8/16 M memory depth
333 MHz State; 667 MHz Timing; 2 GHz Timing Zoom;
32/64 M memory depth
200 MHz State; 800 MHz Timing; 2 GHz Timing Zoom
2/1 M memory depth
200 MHz State; 800 MHz Timing; 2 GHz Timing Zoom
8/4 M memory depth
200 MHz State; 800 MHz Timing; 2 GHz Timing Zoom
32/16 M memory depth
400 MHz State; 800 MHz Timing; 2 GHz Timing Zoom;
4/8 M memory depth
400 MHz State; 800 MHz Timing; 2 GHz Timing Zoom;
16/32 M memory depth
400 MHz State; 800 MHz Timing; 2 GHz Timing Zoom;
32/64 M memory depth
1.25 Gb/s State; 800 MHz Timing; 34 channel;
64 M memory depth
*
Discontinued products.
118
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Ordering Information
Measurement Module Compatibility Table (continued)
Measurement
Module Category
Model
Number
Description
16700
Series
16600
Series
16500C*
16500A/B*
Oscilloscope
16530A/16531A* 2 Channel; 100 MHz Bandwidth; 400 MSa/s;
4 K memory depth
√
√
√
√
√
√
16532A*
16533A*
16534A
2 Channel; 250 MHz Bandwidth; 1 GSa/s;
8 K memory depth
2 Channel; 250 MHz Bandwidth; 1 GSa/s;
32 K memory depth
√
√
√
√
2 Channel; 500 MHz Bandwidth; 2 GSa/s;
32 K memory depth
High Speed Timing
Pattern Generator
16515A/16516A* 1 GHz Timing; 8 K memory depth
√
√
√
√
16517A/16518A 4 GHz Timing; 1GHz Synchronous State;
64 K memory depth
√
√
√
16520A/16521A* 50 MV/s; 4 K memory; 12 Channel
√
√
√
16522A*
16720A
200 MV/s; 258 K memory; 100 MHz in 40 Channel;
200 MHz in 20 Channel
√
√
300 MV/s; 180 MHz in 48 Channel, 16 MV memory;
300 MHz in 24 Channel, 8 MV memory
Emulation
E5901A
E5901B
Emulation Module Products
Emulation Module Products
√
√
√
*
Discontinued products.
Options for Agilent 16700 Series State/Timing Modules
Agilent Module Product Numbers
Option
Option Description
16517A/16518A
16710A
16711A
0B3
1BP
W17
Add service manual
MIL-STD-45662A calibration with test data
Convert standard warranty to one-year on-site warranty
16712A
16715A
16716A
16717A
16750A
16751A
16752A
16760A
010
011
012
013
0B3
A6J
W17
add one E5378A, single-ended, 34-channel probe
add one E5379A, differential, 17-channel probe
add one E5380A, Mictor-compatible probe
add one E5382A, single-ended flying lead probe set
Add service manual (available April 2001)
MIL-STD-45662A calibration with test data (available April 2001)
Convert standard warranty to one-year on-site warranty
119
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Ordering Information
Agilent Wedge Probe Adapters
IC Leg Spacing
Number of
Signals
Quantity of
Probes Shipped
Probe Model
Number
0.5 mm
0.5 mm
0.5 mm
0.5 mm
0.65 mm
0.65 mm
0.65 mm
0.65 mm
3
1
2
1
1
1
2
1
1
E2613A
E2613B
E2614A
E2643A
E2615A
E2615B
E2616A
E26144A
3
8
16
3
3
8
16
Agilent Elastomeric Probing Solutions
Package Type
IC Leg Spacing
0.5 mm
Probe Model Number
240-pin PQFP/CQFP
208-pin PQFP/CQFP
176-pin PQFP
E5363A Probe. E5371A 1/4 flexible cable
E5374A Probe. E5371A 1/4 flexible cable
E5348A Probe. E5349A 1/4 flexible cable
E5377A Probe. E5349A 1/4 flexible cable
E5373A Probe. E5349A 1/4 flexible cable
E5361A Probe. E5340A 1/4 flexible cable
E5336A Probe. E5340A 1/4 flexible cable
0.5 mm
0.5 mm
160-pin QFP
0.5 mm
160-pin PQFP/CQFP
144-pin PQFP/CQFP
144-pin TQFP
0.65 mm
0.65 mm
0.65 mm
120
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Ordering Information
Options and Accessories for Agilent 16534A Oscilloscope Modules
Agilent Option
Option Description
•
•
•
•
•
•
•
•
001
•
•
•
•
•
•
•
•
Add one Agilent 1145A, dual, active 750 MHz probe
Japanese user's reference
Delete manuals
MIL-STD 45662A calibration with test data
Add service manual
Add programming manual set for a 16500 (not required for a 16700)
Convert standard warranty to one-year-on-site warranty
Convert standard warranty to 90-day-on-site warranty
ABJ
0B0
1BP
0B3
0BF
W17
W03
Agilent Model Number
Accessory Description
1144A
800 MHz active probe (power for two Agilent 1144A active probes is provided by the
Agilent 16533A and 16534A) (requires 01144-61604 power splitter to operate two 1144As)
01144-61604
1145A
Power splitter. Allows operation of two Agilent 1144A active probes from one Agilent 16533A or 16534A
750-MHz dual, active probe (power for Agilent 1145A active probes is provided by the Agilent 16533A and 16534A)
200 MHz differential probe (requires an Agilent 1142A power supply)
Probe power supply
1141A
1142A
10442A
10443A
10:1, 500-ohm 1.2pF oscilloscope probe
20:1, 1000-ohm, 1.2pF oscilloscope probe
Options for Agilent 16720A Pattern Generator Modules
Agilent Option
Option Description
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
011
013
014
015
016
017
018
021
022
023
031
032
033
034
041
042
051
052
0B3
W17
W30
W50
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
TTL clock pod and 6” lead set (10460A and 10498A)
3-state TTL/CMOS data pod and 6” lead set (10462A and 10498A)
TTL data pod and 6” lead set (10461A and 10498A)
2.5 V clock pod and 6” lead set (10472A and 10498A)
2.5 V 3-state data pod and 6” lead set (10473A and 10498A)
3.3 V clock pod and 6” lead set (10477A and 10498A)
3-state TTL/3.3 V data pod and 6” lead set (10483A and 10498A)
ECL clock pod and 6” lead set (10463A and 10498A)
ECL terminated pod and 6” lead set (10464A and 10498A)
ECL unterminated pod and 50 Ω shield coaxial lead set (10465A and 10347A)
5 V PECL clock pod and 6” lead set (10468A and 10498A)
5 V PECL data pod and 6” lead set (10469A and 10498A)
3.3 V LVPECL clock pod and 6” lead set (10470A and 10498A)
3.3 V LVPECL data pod and 6” lead set (10471A and 10498A)
1.8 V clock pod and 6” lead set (10475 and 10498A)
1.8 V 3-state data pod and 6” lead set (10476 and 10498A)
LVDS clock pod and 6” LVDS lead set (E8140A and E8142A)
LVDS data pod and 6” LVDS lead set (E8141A and E8142A)
Add service manual
Convert to one-year on-site warranty
3 years return for repair service
5 years return for repair service
121
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Ordering Information
Accessories for Agilent 16720A Pattern Generator Modules
Accessories
Description
Accessories
Description
Model Number
Model Number
10460A
10461A
10462A
10463A
10464A
10465A
10466A
10468A
10469A
10470A
10471A
10472A
10473A
10474A
10475A
TTL clock pod
10476A
10477A
10483A
10498A
10347A
5090-4356
5959-0288
10211A
10024A
E2421A
E2422A
E8140A
E8141A
E8142A
3-state 1.8 volt data pod
TTL data pod
3.3 volt clock pod
3-state TTL/CMOS data pod
10463A ECL clock pod
ECL data pod (terminated)
ECL data pod (unterminated)
3-state TTL/3.3V data pod
5 volt PECL clock pod
5 volt PECL data pod
3-state TTL/3.3 volt data pod
8-channel probe lead set, 6" long
8-channel 50-ohm shielded coaxial probe lead set
Grabbers, surface mount, package of 20
Grabbers, through hole, package of 20
IC probe clip, 24-pin dual in-line package
IC probe clip, 16 pin dual in-line package
SOIC clip adapter test kit (Pomona 5514)
Quad clip adapter test kit (Pomona 5515)
LVDS clock pod
3.3 volt LVPECL clock pod
3.3 volt LVPECL data pod
2.5 volt clock pod
3-state 2.5 volt data pod
8-channel probe lead set, 12" long
1.8 volt clock pod
LVDS data pod
LVDS lead set
Product Numbers and Option(s) for Agilent 16700 Series
Post-Processing Tool Sets
Product or Option Number
Description
B4600B
B4601B
B4605B
B4620B
B4640B
• System Performance Analysis (SPA) Tool Set
• Serial Analysis Tool Set
• Tool Development Kit
• Source Correlation Tool Set
• Data Communications Tool Set
Available for all Tool Sets
#0D4
Do not install tool set (instructs factory to ship tool set
separately from any 16700 Series system on the order)
122
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Third-Party Solutions
Solutions Partner
Advanced Logic Design (ALD)
Aptix
Application Focus
Contact Information
Our solutions partners offer a wide
array of accessory products for the
Agilent Technologies logic analysis
systems. Agilent's solution partners
offer complementary products cover-
ing probing clips, specialized analysis
probes for over 200 microprocessors,
and software tools for ASIC emula-
tion and test system design.
Product design services (digital) www.ald.com
ASIC emulation
www.aptix.com
JM Engineering (JME)
Probing (solutions for
SMT parts)
www.jmecorp.com
American Arium
Intel emulators and probes
Microprocessor core IP
www.arium.com
www.arm.com
Advanced RISC Machines
(ARM)
See the Processor and Bus Support
For Agilent Technologies Logic
Analyzers (p/n 5966-4365) document
for contact information concerning
these vendors.
CAD-UL
Corelis
Software programming tools
www.cadul.com
www.corelis.com
Analysis probes for various
microprocessors and buses
Diagonal
Manufacturing test suite
software
www.diagonal.com
Emulation Technologies (ET)
Europe Technologies
Probing
www.emulation.com
Embedded system design
tools and services
www.europe-technologies.com
FuturePlus Systems
Analysis probes for computer
buses
www.futureplus.com
www.ghs.com
Green Hills Software, Inc
(GHS)
Debugger and compiler
software for Motorola
microprocessors
Ironwood
High-density VLSI
www.ironwoodelectronics.com
interconnect solutions
Lital Electronics, Inc.
Mil-spec computer boards
www.lital.com
Mobile Media Research
PCMCIA focused development
tools
www.mobmedres.com
Microtec (Mentor Graphics
Embedded Software Division)
Debuggers and compilers
www.mentor.com/embedded
www.pomonaelectronics.com
Pomona Electronics
Supplier of accessories for
electronic test instruments
DIAB-SDS
Skyline
Debuggers, compilers
www.diabsds.com
Probing and manufacturing
services
phone only: 719-390-9425
SynaptiCAD
WindRiver
Waveform simulation
analysis software
www.syncad.com
Embedded RTOS
www.windriver.com
development tools
123
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Support, Warranty and Related Literature
Agilent software and firmware prod-
ucts that are designated by Agilent
for use with a hardware product are
warranted for a period of one year
from date of shipment to execute
their programming instructions when
properly installed. If you send us
notice of defects in materials or
workmanship during the warranty
period, we will repair or replace
these products, so long as the defect
does not result from buyer supplied
hardware or interfacing. The
Support and Services
Warranty
Agilent's support services comple-
ment your logic analysis system to
provide a complete solution to your
digital design and debug problems.
By taking advantage of Agilent's
expertise you can concentrate on
your particular design projects and
applications, rather than your debug
tools, resulting in increased produc-
tivity.
Agilent hardware products are war-
ranted against defects in materials
and workmanship for a period of one
year from date of shipment. Some
newly manufactured Agilent products
may contain remanufactured parts,
which are equivalent to new in per-
formance. If you send us a notice of
such defects during the warranty
period, we will either repair or
replace hardware products that prove
to be defective.
warranty period is controlled by the
warranty statement included with
the product and begins on the date
of shipment.
Related Literature
Publication Title
Publication Type
Publication Number
Processor and Bus Support For
Configuration Guide
5966-4365E
Agilent Technologies Logic Analyzers
Probing Solutions for
Agilent Technologies Logic Analysis Systems
Product Overview
Product Overview
Product Overview
Product Overview
Product Overview
5968-4632E
5966-2866E
5966-2868E
5966-2867E
5968-2421E
Emulation and Analysis Solutions for
the Motorola MPC 8XX Microprocessors
Emulation and Analysis Solutions for
the Motorola/IBM PowerPC 6XX Microprocessors
Emulation and Analysis Solutions for the
Motorola/IBM Power PC 740/750 Microprocessors
Agilent E2487C Analysis Probe & Agilent E2492B/C/E
Probe Adapter for Intel Celeron Pentium II/III and
Pentium II/III Xeon Processors
Emulation and Analysis Solutions for
ARM7 and ARM9 Microprocessors
Product Overview
5966-3442E
124
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www.agilent.com
By internet, phone, or fax, get assistance with
all your test & measurement needs
Agilent Technologies’ Test and Measurement Support, Services, and Assistance
Agilent Technologies aims to maximize the value you receive, while minimizing your risk and
problems. We strive to ensure that you get the test and measurement capabilities you paid
for and obtain the support you need. Our extensive support resources and services can help
you choose the right Agilent products for your applications and apply them successfully.
Every instrument and system we sell has a global warranty. Support is available for at least
five years beyond the production life of the product. Two concepts underlie Agilent's overall
support policy: "Our Promise" and "Your Advantage."
Online assistance:
www.agilent.com/find/assist
Phone or Fax
United States:
(tel) 800 452 4844
Our Promise
Canada:
(tel) 877 894 4414
(fax) 905 282 6495
Our Promise means your Agilent test and measurement equipment will meet its advertised
performance and functionality. When you are choosing new equipment, we will help you
with product information, including realistic performance specifications and practical
recommendations from experienced test engineers. When you use Agilent equipment,
we can verify that it works properly, help with product operation, and provide basic
measurement assistance for the use of specified capabilities, at no extra cost upon request.
Many self-help tools are available.
China:
(tel) 800 810 0189
(fax) 800 820 2816
Europe:
(tel) (31 20) 547 2323
(fax) (31 20) 547 2390
Your Advantage
Your Advantage means that Agilent offers a wide range of additional expert test and
measurement services, which you can purchase according to your unique technical and
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training, as well as design, system integration, project management, and other professional
engineering services. Experienced Agilent engineers and technicians worldwide can help
you maximize your productivity, optimize the return on investment of your Agilent
instruments and systems, and obtain dependable measurement accuracy for the life of
those products.
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(tel) (81) 426 56 7832
(fax) (81) 426 56 7840
Korea:
(tel) (82 2) 2004 5004
(fax) (82 2) 2004 5115
Latin America:
(tel) (305) 269 7500
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Agilent T&M Software and Connectivity
Agilent's Test and Measurement software and connectivity products, solutions and
developer network allows you to take time out of connecting your instruments to your
computer with tools based on PC standards, so you can focus on your tasks, not on your
connections. Visit www.agilent.com/find/connectivity for more information.
Taiwan:
(tel) 0800 047 866
(fax) 0800 286 331
Other Asia Pacific Countries:
(tel) (65) 6375 8100
(fax) (65) 6836 0252
Email: tm_asia@agilent.com
Product specifications and descriptions in this
document subject to change without notice.
www.agilent.com/find/emailupdates
Get the latest information on the products and applications you select.
©
Agilent Technologies, Inc. 2002
Printed in USA June 25, 2002
5968-9661E
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