NEC PD75P0016 User Manual

USER'S MANUAL

µPD750008

4 BIT SINGLE-CHIP MICROCOMPUTER

µPD750004

µPD750006

µPD750008

µPD75P0016

Document No. U10740EJ2V0UM00 (2nd edition)

(Previous No. IEU-1421)

Date Published April 1996 P

Printed in Japan

1995

The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited

without governmental license, the need for which must be judged by the customer. The export or re-export of this product

from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales

representative.

The information in this document is subject to change without notice.

No part of this document may be copied or reproduced in any form or by any means without the prior written

consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in

this document.

NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property

rights of third parties by or arising from use of a device described herein or any other liability arising from use

of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other

intellectual property rights of NEC Corporation or others.

While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,

the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or

property arising from a defect in an NEC semiconductor device, customer must incorporate sufficient safety

measures in its design, such as redundancy, fire-containment, and anti-failure features.

NEC devices are classified into the following three quality grades:

“Standard“, “Special“, and “Specific“. The Specific quality grade applies only to devices developed based on a

customer designated “quality assurance program“ for a specific application. The recommended applications of

a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device

before using it in a particular application.

Standard:Computers, office equipment, communications equipment, test and measurement equipment, audio

and visual equipment, home electronic appliances, machine tools, personal electronic equipment

and industrial robots

Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster

systems, anti-crime systems, safety equipment and medical equipment (not specifically designed

for life support)

Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life

support systems or medical equipment for life support, etc.

The quality grade of NEC devices in “Standard“ unless otherwise specified in NEC's Data Sheets or Data Books.

If customers intend to use NEC devices for applications other than those specified for Standard quality grade,

they should contact NEC Sales Representative in advance.

Anti-radioactive design is not implemented in this product.

M7 94.11

Major Changes

Page

Description

All

The 44-pin plastic QFP package has been changed from µPD750008GB-xxx-3B4

to µPD750008GB-xxx-3BS-MTX.

The µPD75P0016 under development has been changed to the already-developed

µPD75P0016.

The input withstand voltage at ports 4 and 5 during open drain has been changed from

12 V to 13 V.

Preface

p.4

English-version document numbers have been added to "Related documents."

The format of the table in Section 1.3 has been changed.

p.45

The caution in using Mk II mode has been added in Section 4.1.1.

p.85

The description for the mask option when using the feedback resistor has been added in

(6) in Section 5.2.2.

p.187

The description for the interrupt enable flag has been added in Section 6.3.

Table 6-4 has been added in Section 6.6.

p.198

p.233

Section 9.4 has been added.

p.235

Chapter 10 has been added.

p.237–298

p.241

The operand @rpa has been changed to @rpa1 in Section 11.

@rpa1 has been added in the table in (1) in Section 11.2.

The title of Section 11.4 has been modified to conform to that of Section 11.2.

p.264

p.301

Appendix B

Supported OS versions have been upgraded.

p.321

Appendix F has been added.

The mark shows major revised points.

PREFACE

Readers

This manual is intended for engineers who want to learn the capabilities of the

µPD750004,µPD750006,µPD750008,andµPD75P0016todevelopapplicationsystems

based on them.

Purpose

The purpose of this manual is to help users understand the hardware capabilities (shown

below) of the µPD750004, µPD750006, µPD750008, and µPD75P0016.

Configuration

This manual is roughly divided as follows:

• General

• Pin functions

• Architecture feature and memory map

• Internal CPU functions

• Peripheral hardware functions

• Interrupt and test functions

• Standby function

• Reset function

• Writing to and verifying program memory (PROM)

• Mask option

• Instruction set

Guidance

Readers of this manual should have general knowledge of the electronics, logical circuit,

and microcomputer fields.

• For users who have used the µPD75008:

–> See Appendix A to check for any difference in the functions and read the

explanation of those differences.

• To check the functions of an instruction in detail when the reader knows its

mnemonics:

–> See the instruction index in Appendix D.

• To check the functions of specific internal circuits, etc.:

–> See Appendix E.

• To understand the overall functions of the µPD750004, µPD750006, µPD750008,

and µPD75P0016:

–> Read through all chapters sequentially.

Notation

Data bit significance

: Higher-order bits on the left side

Lower-order bits on the right side

Active low

: xxx (Pin and signal names are overscored.)

: Low-order address on the upper side

High-order address on the lower side

: Explanation of an indicated part of text

: Information requesting the user's special attention

: Supplementary information

Memory map address

Note

Caution

Remark

Important and emphasized matter : Described in bold face

Numeric value : Binary .................. xxxx or xxxxB

Decimal ............... xxxx

Hexadecimal ....... xxxxH

Other documents

Document Number

Japanese English

Document Name

Package Manual

IEI-635

IEI-1213

IEI-1207

IEI-1209

Semiconductor Device Mounting Technology Manual

Quality Grade on NEC Semiconductor Devices

Reliability and Quality Control of NEC Semiconductor Devices

Electrostatic Discharge (ESD) Test

IEI-616

IEI-620

IEI-5068

MEM-539

MEI-603

MEI-604

—

MEI-1202

—

Semiconductor Device Quality Guarantee Guide

Microcontroller-Related Products Guide - by third parties

Caution The above related documents are subject to change without notice. Be sure to use the

latest edition when you design your system.

[MEMO]

CONTENTS

CHAPTER 1 GENERAL .........................................................................................................................

1.1 FUNCTION OVERVIEW .........................................................................................

1.2 ORDERING INFORMATION...................................................................................

1.3 DIFFERENCES AMONG SUBSERIES PRODUCTS.............................................

1.4 BLOCK DIAGRAM ..................................................................................................

1.5 PIN CONFIGURATION (TOP VIEW) .....................................................................

CHAPTER 2 PIN FUNCTIONS ..............................................................................................................

2.1 PIN FUNCTIONS OF THE µPD750008 .................................................................

2.2 PIN FUNCTIONS .................................................................................................... 12

2.2.1 P00-P03 (PORT0)...................................................................................... 12

P10-P13 (PORT1)...................................................................................... 12

2.2.2 P20-P23 (PORT2)...................................................................................... 13

P30-P33 (PORT3)...................................................................................... 13

P40-P43 (PORT4), P50-P53 (PORT5) ..................................................... 13

P60-P63 (PORT6), P70-P73 (PORT7) ..................................................... 13

2.2.3 P80, P81 (PORT8)..................................................................................... 13

2.2.4 TI0 .............................................................................................................. 13

2.2.5 PTO0, PTO1 .............................................................................................. 13

2.2.6 PCL............................................................................................................. 14

2.2.7 BUZ ............................................................................................................ 14

2.2.8 SCK, SO/SB0, SI/SB1 ............................................................................... 14

2.2.9 INT4............................................................................................................ 14

2.2.10 INT0, INT1 ................................................................................................ 14

2.2.11 INT2 .......................................................................................................... 15

2.2.12 KR0-KR3................................................................................................... 15

KR4-KR7................................................................................................... 15

2.2.13 X1, X2 ....................................................................................................... 15

2.2.14 XT1, XT2................................................................................................... 16

2.2.15 RESET ...................................................................................................... 16

2.2.16

2.2.17

......................................................................................................................................... 16

2.2.18 IC (for the µPD750004, µPD750006, and µPD750008 only).................. 17

2.2.19 (for the µPD75P0016 only) ............................................................... 17

2.2.20 MD0-MD3 (for the µPD75P0016 only)..................................................... 17

2.3 PIN INPUT/OUTPUT CIRCUITS ............................................................................ 18

2.4 CONNECTION OF UNUSED PINS ........................................................................ 20

- i -

CHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAP ....................................... 21

3.1 DATA MEMORY BANK STRUCTURE AND ADDRESSING MODES .................. 21

3.1.1 Data Memory Bank Structure .................................................................... 21

3.1.2 Data Memory Addressing Modes .............................................................. 23

3.2 GENERAL REGISTER BANK CONFIGURATION ................................................. 34

3.3 MEMORY-MAPPED I/O .......................................................................................... 39

CHAPTER 4 INTERNAL CPU FUNCTIONS ......................................................................................... 45

4.1 Mk I MODE/Mk II MODE SWITCH FUNCTIONS................................................... 45

4.1.1 Differences between Mk I Mode and Mk II Mode..................................... 45

4.1.2 Setting of the Stack Bank Selection Register (SBS) ................................ 46

4.2 PROGRAM COUNTER (PC) ................................................................................. 47

4.3 PROGRAM MEMORY (ROM) ................................................................................ 48

4.4 DATA MEMORY (RAM) .......................................................................................... 53

4.4.1 Data Memory Configuration....................................................................... 53

4.4.2 Specification of a Data Memory Bank....................................................... 54

4.5 GENERAL REGISTER............................................................................................ 56

4.6 ACCUMULATOR..................................................................................................... 57

4.7 STACK POINTER (SP) AND STACK BANK SELECT REGISTER (SBS)............ 58

4.8 PROGRAM STATUS WORD (PSW) ...................................................................... 62

4.9 BANK SELECT REGISTER (BS) ........................................................................... 65

CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS ...................................................................... 67

5.1 DIGITAL I/O PORTS............................................................................................. 67

5.1.1 Types, Features, and Configurations of Digital I/O Ports ........................ 68

5.1.2 I/O Mode Setting........................................................................................ 74

5.1.3 Digital I/O Port Manipulation Instructions ................................................. 76

5.1.4 Digital I/O Port Operation .......................................................................... 79

5.1.5 Specification of Bilt-in Pull-Up Resistors .................................................. 81

5.1.6 I/O Timing of Digital I/O Ports ................................................................... 82

5.2 CLOCK GENERATOR ............................................................................................ 84

5.2.1 Clock Generator Configuration.................................................................. 84

5.2.2 Functions and Operations of the Clock Generator ................................... 85

5.2.3 System Clock and CPU Clock Setting ...................................................... 94

5.2.4 Clock Output Circuit................................................................................... 96

5.3 BASIC INTERVAL TIMER/WATCHDOG TIMER ................................................... 99

5.3.1 Configuration of the Basic Interval Timer/Watchdog Timer ..................... 99

5.3.2 Basic Interval Timer Mode Register (BTM) .............................................. 99

5.3.3 Watchdog Timer Enable Flag (WDTM) ..................................................... 101

5.3.4 Operation of the Basic Interval Timer ....................................................... 101

- ii -

5.3.5 Operation of the Watchdog Timer ............................................................. 102

5.3.6 Other Functions ......................................................................................... 103

5.4 CLOCK TIMER ........................................................................................................ 105

5.4.1 Configuration of the Clock Timer .............................................................. 106

5.4.2 Clock Mode Register ................................................................................. 106

5.5 TIMER/EVENT COUNTER ..................................................................................... 108

5.5.1 Configuration of Timer/Event Counter ...................................................... 108

5.5.2 8-Bit Timer/Event Counter Mode Operation ............................................. 114

5.5.3 Notes on Timer/Event Counter Applications............................................. 120

5.6 SERIAL INTERFACE .............................................................................................. 123

5.6.1 Serial Interface Functions.......................................................................... 123

5.6.2 Configuration of Serial Interface ............................................................... 124

5.6.3 Register Functions ..................................................................................... 127

5.6.4 Operation Halt Mode.................................................................................. 135

5.6.5 Three-Wire Serial I/O Mode Operations ................................................... 137

5.6.6 Two-Wire Serial I/O Mode ......................................................................... 144

5.6.7 SBI Mode Operation .................................................................................. 150

5.6.8 Manipulation of SCK Pin Output ............................................................... 179

5.7 BIT SEQUENTIAL BUFFER ................................................................................... 181

CHAPTER 6 INTERRUPT AND TEST FUNCTIONS .............................................................................. 183

6.1 CONFIGURATION OF THE INTERRUPT CONTROL CIRCUIT........................... 183

6.2 TYPES OF INTERRUPT SOURCES AND VECTOR TABLES ............................. 185

6.3 VARIOUS DEVICES TO CONTROL INTERRUPT FUNCTIONS.......................... 187

6.4 INTERRUPT SEQUENCE ...................................................................................... 195

6.5 MULTIPLE INTERRUPT PROCESSING CONTROL............................................. 196

6.6 PROCESSING OF INTERRUPTS SHARING A VECTOR ADDRESS ................. 198

6.7 MACHINE CYCLES FOR STARTING INTERRUPT PROCESSING .................... 200

6.8 EFFECTIVE USE OF INTERRUPTS ..................................................................... 202

6.9 INTERRUPT APPLICATIONS ................................................................................ 202

6.10 TEST FUNCTION ................................................................................................. 210

6.10.1 Test Sources .......................................................................................... 210

6.10.2 Hardware to Control Test Functions ..................................................... 210

CHAPTER 7 STANDBY FUNCTION ..................................................................................................... 215

7.1 SETTING OF STANDBY MODES AND OPERATION STATUS ........................... 216

7.2 RELEASE OF THE STANDBY MODES................................................................. 217

7.3 OPERATION AFTER A STANDBY MODE IS RELEASED ................................... 219

7.4 SELECTION OF A MASK OPTION........................................................................ 220

7.5 APPLICATIONS OF THE STANDBY MODES....................................................... 220

- iii -

CHAPTER 8 RESET FUNCTION ........................................................................................................... 225

CHAPTER 9 WRITING TO AND VERIFYING PROGRAM MEMORY (PROM) ................................... 229

9.1 OPERATING MODES WHEN WRITING TO AND VERIFYING

THE PROGRAM MEMORY .................................................................................... 230

9.2 WRITING TO THE PROGRAM MEMORY ............................................................. 230

9.3 READING THE PROGRAM MEMORY .................................................................. 232

9.4 SCREENING OF ONE-TIME PROM ...................................................................... 233

CHAPTER 10 MASK OPTION ............................................................................................................... 235

10.1 PIN......................................................................................................................... 235

10.2 MASK OPTION OF STANDBY FUNCTION......................................................... 235

10.3 MASK OPTION FOR FEEDBACK RESISTOR OF SUBSYSTEM CLOCK ........ 236

CHAPTER 11 INSTRUCTION SET .......................................................................................................... 237

11.1 UNIQUE INSTRUCTIONS .................................................................................... 237

11.1.1 GETI Instruction ..................................................................................... 237

11.1.2 Bit Manipulation Instructions .................................................................. 238

11.1.3 String-Effect Instructions ........................................................................ 238

11.1.4 Number System Conversion Instructions .............................................. 239

11.1.5 Skip Instructions and the Number of Machine Cycles Required

for a Skip ............................................................................................... 240

11.2 INSTRUCTION SET AND OPERATION .............................................................. 241

11.3 INSTRUCTION CODES OF EACH INSTRUCTION ............................................ 258

11.4 FUNCTIONS AND APPLICATIONS OF THE INSTRUCTIONS .......................... 264

11.4.1 Transfer Instructions .............................................................................. 264

11.4.2 Table Reference Instructions ................................................................. 270

11.4.3 Bit Transfer Instructions ......................................................................... 273

11.4.4 Arithmetic/Logical Instructions ............................................................... 273

11.4.5 Accumulator Manipulation Instructions.................................................. 279

11.4.6 Increment/Decrement Instructions ......................................................... 279

11.4.7 Compare Instructions ............................................................................. 280

11.4.8 Carry Flag Manipulation Instructions ..................................................... 281

11.4.9 Memory Bit Manipulation Instructions ................................................... 282

11.4.10 Branch Instructions .............................................................................. 284

11.4.11 Subroutine Stack Control Instructions ................................................. 289

11.4.12 Interrupt Control Instructions ............................................................... 293

11.4.13 I/O Instructions ..................................................................................... 294

11.4.14 CPU Control Instructions ..................................................................... 295

11.4.15 Special Instructions .............................................................................. 295

- iv -

APPENDIX A FUNCTIONS OF THE µPD75008, µPD750008, AND µPD75P0016 ............................ 299

APPENDIX B DEVELOPMENT TOOLS ................................................................................................ 301

APPENDIX C MASKED ROM ORDERING PROCEDURE................................................................... 309

APPENDIX D INSTRUCTION INDEX .................................................................................................... 311

D.1 INSTRUCTION INDEX (BY FUNCTION) .............................................................. 311

D.2 INSTRUCTION INDEX (ALPHABETICAL ORDER) ............................................. 314

APPENDIX E HARDWARE INDEX .......................................................................................................... 317

E.1 HARDWARE INDEX (ALPHABETICAL ORDER WITH RESPECT TO THE .......

HARDWARE NAME).............................................................................................. 317

E.2 HARDWARE INDEX (ALPHABETICAL ORDER WITH RESPECT TO THE

HARDWARE SYMBOL) ......................................................................................... 319

APPENDIX F REVISION HISTORY ......................................................................................................... 321

- v -

LIST OF FIGURES (1/4)

Figure No.

2-1

Title

Page

Pin Input/Output Circuits .................................................................................................. 18

3-1

3-2

3-3

3-4

3-5

3-6

3-7

Use of MBE = 0 Mode and MBE = 1 Mode ..................................................................... 22

Data Memory Organization and Addressing Range of Each Addressing Mode ............ 24

Updating Static RAM Addresses...................................................................................... 28

Example of Register Bank Selection ............................................................................... 35

General Register Configuration (4-bit Processing) ......................................................... 37

General Register Configuration (8-bit Processing) ......................................................... 38

µPD750008 I/O Map ......................................................................................................... 40

4-1

Stack Bank Selection Register Format ............................................................................ 46

Program Counter Organization ........................................................................................ 47

Program Memory Map (in µPD750004) ........................................................................... 49

Program Memory Map (in µPD750006) ........................................................................... 50

Program Memory Map (in µPD750008) ........................................................................... 51

Program Memory Map (in µPD75P0016)......................................................................... 52

Data Memory Map ............................................................................................................ 54

General Register Format .................................................................................................. 56

Register Pair Format ........................................................................................................ 57

Accumulator ...................................................................................................................... 57

Format of Stack Pointer and Stack Bank Select Register .............................................. 59

Data Saved to the Stack Memory (Mk I Mode) ............................................................... 59

Data Restored from the Stack Memory (Mk I Mode) ...................................................... 60

Data Saved to the Stack Memory (Mk II Mode) .............................................................. 60

Data Restored from the Stack Memory (Mk II Mode) ..................................................... 61

Program Status Word Format .......................................................................................... 62

Bank Select Register Format ........................................................................................... 65

4-2

4-3

4-4

4-5

4-6

4-7

4-8

4-9

4-10

4-11

4-12

4-13

4-14

4-15

4-16

4-17

5-1

5-2

5-3

5-4

5-5

5-6

5-7

5-8

Data Memory Addresses of Digital Ports......................................................................... 67

Configurations of Ports 0 and 1 ....................................................................................... 69

Configurations of Ports 2 and 7 ....................................................................................... 70

Configurations of Ports 3n and 6n (n = 0 to 3)................................................................ 71

Configurations of Ports 4 and 5 ....................................................................................... 72

Configuration of Port 8 ..................................................................................................... 73

Formats of Port Mode Registers ...................................................................................... 75

Pull-Up Resistor Specification Register Format .............................................................. 82

- vi -

LIST OF FIGURES (2/4)

Figure No.

Title

Page

5-9

I/O Timing Chart of Digital I/O Ports ................................................................................ 82

ON Timing Chart of Built-in Pull-Up Resistor Connected by Software.......................... 83

Block Diagram of the Clock Generator ............................................................................ 84

Format of the Processor Clock Control Register............................................................. 87

Format of the System Clock Control Register ................................................................. 88

External Circuit for the Main System Clock Oscillator .................................................... 89

External Circuit for the Subsystem Clock Oscillator........................................................ 89

Examples of Oscillator Connections Which Should Be Avoided .................................... 90

Subsystem Clock Oscillator.............................................................................................. 92

Sub-Oscillator Control Register (SOS) Format ............................................................... 93

Changing the System Clock and CPU Clock................................................................... 95

Configuration of the Clock Output Circuit ........................................................................ 96

Format of the Clock Output Mode Register ..................................................................... 97

Application to Remote Control Output ............................................................................. 98

Block Diagram of the Basic Interval Timer/Watchdog Timer .......................................... 99

Format of the Basic Interval Timer Mode Register ......................................................... 100

Format of the Watchdog Timer Enable Flag (WDTM)..................................................... 101

Block Diagram of the Clock Timer ................................................................................... 106

Clock Mode Register Format ........................................................................................... 107

Block Diagram of the Timer/Event Counter (Channel 0) ................................................ 109

Block Diagram of the Timer Counter (Channel 1) ........................................................... 110

Timer/Event Counter Mode Register (Channel 0) Format .............................................. 112

Timer Counter Mode Register (Channel 1) Format......................................................... 113

Timer/Event Counter Output Enable Flag Format ........................................................... 114

Timer/Event Counter Mode Register Setup..................................................................... 115

Timer/Event Counter Output Enable Flag Setup............................................................. 116

Configuration of Timer/Event Counter ............................................................................. 118

Count Operation Timing ................................................................................................... 119

Error at the Start of the Timer .......................................................................................... 120

Example of the SBI System Configuration ...................................................................... 124

Block Diagram of the Serial Interface .............................................................................. 125

Format of Serial Operation Mode Register (CSIM) ......................................................... 127

Format of Serial Bus Interface Control Register (SBIC) ................................................. 131

Peripheral Hardware of Shift Register ............................................................................. 134

Example of Three-Wire Serial I/O System Configuration................................................ 137

Timing of Three-Wire Serial I/O Mode ............................................................................. 140

5-10

5-11

5-12

5-13

5-14

5-15

5-16

5-17

5-18

5-19

5-20

5-21

5-22

5-23

5-24

5-25

5-26

5-27

5-28

5-29

5-30

5-31

5-32

5-33

5-34

5-35

5-36

5-37

5-38

5-39

5-40

5-41

5-42

5-43

5-44

- vii -

LIST OF FIGURES (3/4)

Figure No.

Title

Page

5-45

5-46

5-47

5-48

5-49

5-50

5-51

5-52

5-53

5-54

5-55

5-56

5-57

5-58

5-59

5-60

5-61

5-62

5-63

5-64

5-65

5-66

5-67

5-68

5-69

5-70

5-71

5-72

5-73

5-74

5-75

5-76

5-77

5-78

5-79

5-80

Operations of RELT and CMDT ....................................................................................... 141

Transfer Bit Switching Circuit ........................................................................................... 141

Example of Two-Wire Serial I/O System Configuration .................................................. 144

Timing of Two-Wire Serial I/O Mode................................................................................ 147

Operations of RELT and CMDT ....................................................................................... 148

Example of SBI System Configuration............................................................................. 150

Timing of SBI Transfer ..................................................................................................... 152

Bus Release Signal .......................................................................................................... 153

Command Signal .............................................................................................................. 153

Address ............................................................................................................................. 153

Slave Selection Using an Address................................................................................... 154

Command.......................................................................................................................... 154

Data................................................................................................................................... 154

Acknowledge Signal ......................................................................................................... 155

Busy and Ready Signals .................................................................................................. 156

Operations of RELT, CMDT, RELD, and CMDD (Master) .............................................. 161

Operations of RELT, CMDT, RELD, and CMDD (Slave) ................................................ 161

Operation of ACKT ........................................................................................................... 162

Operation of ACKE ........................................................................................................... 162

Operation of ACKD ........................................................................................................... 163

Operation of BSYE ........................................................................................................... 164

Pin Configuration .............................................................................................................. 167

Address Transfer Operation from Master Device to Slave Device (WUP = 1) .............. 169

Command Transfer Operation from Master Device to Slave Device.............................. 170

Data Transfer Operation from Master Device to Slave Device....................................... 171

Data Transfer Operation from Slave Device to Master Device....................................... 172

Example of Serial Bus Configuration ............................................................................... 174

Transfer Format of the READ Command ........................................................................ 175

Transfer Format of the WRITE and END Commands ..................................................... 176

Transfer Format of the STOP Command......................................................................... 176

Transfer Format of the STATUS Command .................................................................... 177

Status Format of the STATUS Command ....................................................................... 177

Transfer Format of the RESET Command ...................................................................... 178

Transfer Format of the CHGMST Command................................................................... 178

Master and Slave Operation in Case of Error ................................................................. 179

SCK/P01 Pin Circuit Configuration .................................................................................. 180

- viii -

LIST OF FIGURES (4/4)

Figure No.

5-81

Title

Page

Format of the Bit Sequential Buffer ................................................................................. 181

6-1

6-2

6-3

6-4

6-5

6-6

6-7

6-8

6-9

6-10

6-11

Block Diagram of Interrupt Control Circuit ....................................................................... 184

Interrupt Vector Table....................................................................................................... 185

Interrupt Priority Specification Register ........................................................................... 189

Configurations of the INT0, INT1, and INT4 Circuits ...................................................... 191

I/O Timing of a Noise Eliminator ...................................................................................... 192

Format of Edge Detection Mode Registers ..................................................................... 193

Interrupt Sequence ........................................................................................................... 195

Multiple Interrupt Processing by a High-Order Interrupt ................................................. 196

Multiple Interrupt Processing by Changing the Interrupt Status Flags ........................... 197

Block Diagram of the INT2 and KR0 to KR7 Circuits...................................................... 212

Format of INT2 Edge Detection Mode Register (IM2) .................................................... 213

7-1

7-2

Standby Mode Release Operation ................................................................................... 218

Wait Time When the STOP Mode Is Released ............................................................... 219

8-1

8-2

Configuration of Reset Functions..................................................................................... 225

Reset Operation by Generation of RESET Signal .......................................................... 225

B-1

B-2

Drawings of the EV-9200G-44 (Reference)..................................................................... 306

Recommended Pattern on Boards for the EV-9200G-44 (Reference) ........................... 307

- ix -

LIST OF TABLES (1/2)

Table No.

1-1

Title

Page

Features of the Products ..................................................................................................

2-1

2-2

2-3

Digital I/O Port Pins ..........................................................................................................

Non-Port Pin Functions .................................................................................................... 11

Connection of Unused Pins.............................................................................................. 20

3-1

3-2

3-3

Addressing Modes ............................................................................................................ 25

Recommended Use of Register Banks with Normal Routines and

Interrupt Routines ............................................................................................................. 34

Addressing Modes Applicable to Peripheral Hardware Operation.................................. 39

3-4

4-1

4-2

4-3

4-4

4-5

4-6

Differences between Mk I Mode and Mk II Mode............................................................ 45

Stack Area to Be Selected by the SBS ........................................................................... 58

PSW Flags Saved/Restored in Stack Operation ............................................................. 62

Carry Flag Manipulation Instructions ............................................................................... 63

Information Indicated by the Interrupt Status Flag .......................................................... 64

5-1

5-2

5-3

5-4

5-5

5-6

5-7

5-8

5-9

5-10

Types and Features of Digital Ports ................................................................................ 68

I/O Pin Manipulation Instructions ..................................................................................... 78

Operations by I/O Port Manipulation Instructions............................................................ 80

Specification of Built-in Pull-Up Resistors ....................................................................... 81

Maximum Time Required to Change the System Clock and CPU Clock ....................... 94

Resolution and Longest Setup Time................................................................................ 117

Serial Clock Selection and Application (In the Three-Wire Serial I/O Mode)................. 140

Serial Clock Selection and Application (In the Two-Wire Serial I/O Mode) ................... 148

Serial Clock Selection and Application (In the SBI Mode).............................................. 160

Various Signals Used in the SBI Mode............................................................................ 165

6-1

6-2

6-3

6-4

6-5

6-6

Interrupt Sources .............................................................................................................. 185

Set Signals for Interrupt Request Flags........................................................................... 188

Interrupt Processing Statuses of IST0 and IST1 ............................................................. 194

Identifying Interrupt Sharing Vector Table Address ........................................................ 198

Test Source....................................................................................................................... 210

Signals Setting Test Request Flags................................................................................. 210

- x -

LIST OF TABLES (2/2)

Table No.

Title

Page

7-1

7-2

Operation Statuses in the Standby Mode ........................................................................ 216

Selection of a Wait Time with BTM.................................................................................. 219

8-1

Status of the Hardware after a Reset .............................................................................. 226

Selecting Mask Option of Pin ........................................................................................... 235

10-1

- xi -

[MEMO]

- xii -

CHAPTER 1 GENERAL

The µPD750004, µPD750006, µPD750008, and µPD75P0016 are 75XL series 4-bit single-chip microcom-

puters. The 75XL series is a successor of the 75X series consisting of many products. These µPD750004,

µPD750006, µPD750008, and µPD75P0016 are collectively called the µPD750008 subseries.

The 75XL series takes over the CPUs of the 75X series, realizing a wide range of operating voltages and

high-speed operation. In addition to having upward compatibility with existing products, the 75XL series is

best suited for battery-driven applications.

The µPD750004, µPD750006, µPD750008, and µPD75P0016 have the following features:

• Operable on low voltage: V

= 2.2 to 5.5 V

• Switchable instruction execution times (useful for high-speed operation and power saving)

0.95 µs, 1.91 µs, 3.81 µs, 15.3 µs (at 4.19 MHz)

0.67 µs, 1.33 µs, 2.67 µs, 10.7 µs (at 6.0 MHz)

122 µs (at 32.768 kHz)

• Enhanced timers: 4 channels

• Easy replacement (The functions and instructions of the µPD75008 are taken over.)

The 75XL series comes in four models, according to the size and type of program memory (see

Table 1-1).

Table 1-1. Features of the Products

Model

Program memory (ROM)

Remarks

µPD750004

µPD750006

µPD750008

µPD75P0016

4096 x 8 bits

6144 x 8 bits

8192 x 8 bits

16384 x 8 bits

Masked ROM

One-time PROM

The µPD75P0016, having the electrically programmable one-time PROM, is pin-compatible with the

µPD750004, µPD750006, and µPD750008. It is suitable for small-scale production or prototype production

in system development.

Applications

• Consumer electronics

VCR, audio equipment (such as CD players), remote controller, etc.

• Others

Telephone, camera, etc.

Remark This manual will explain only the µPD750008 when the µPD750008, µPD750004,

µPD750006, and µPD75P0016 are functionally the same. Users of the µPD750004, µPD750006,

orµPD75P0016shouldreadµPD750008asreferringtoµPD750004,µPD750006,orµPD75P0016.

µPD750008 USER'S MANUAL

1.1 FUNCTION OVERVIEW

Item

Function

Instruction execution

time

• 0.95, 1.91, 3.81, 15.3 µs (when the main system clock operates at 4.19 MHz)

• 0.67, 1.33, 2.67, 10.7 µs (when the main system clock operates at 6.0 MHz)

• 122 µs (when the subsystem clock operates at 32.768 kHz)

Internal memory ROM 4096 x 8 bits (µPD750004)

6144 x 8 bits (µPD750006)

8192 x 8 bits (µPD750008)

16384 x 8 bits (µPD75P0016)

RAM 512 x 4 bits

General register

I/O port

• When operating in 4 bits: 8 x 4 banks

• When operating in 8 bits: 4 x 4 banks

CMOS input pins

Can incorporate 25 pull-up resistors

that are specified with the software.

CMOS I/O pins

Four pins can directly drive

the LED.

N-ch open-drain I/O pins

Eight pins can directly drive

the LED.

Can withstand 13 V.

Can incorporate pull-up resistors that

are specified with the mask option.

Note

Timer

• Timer/event counter: 1 channel

• Timer counter: 1 channel

• Basic interval timer/watchdog timer: 1 channel

• Clock timer: 1 channel

Serial interface

• Three-wire serial I/O mode (switchable between the start LSB and the start MSB)

• Two-wire serial I/O mode

• SBI mode

Bit sequential buffer

Clock output

16 bits

• F, 524 kHz, 262 kHz, 65.5 kHz (when the main system clock operates at 4.19 MHz)

• F, 750 kHz, 375 kHz, 93.7 kHz (when the main system clock operates at 6.0 MHz)

Vectored interrupt

Test input

External: 3, Internal: 4

External: 1, Internal: 1

System clock oscillator • Ceramic or crystal oscillator for the main system clock

• Crystal oscillator for the subsystem clock

Standby function

STOP/HALT mode

T =–40°C to +85°C

Operating ambient

temperature

Supply voltage

Package

= 2.2 to 5.5 V

42-pin plastic shrink DIP (600 mil)

44-pin plastic QFP (10 x 10 mm)

Note The N-ch open-drain I/O port pins of the µPD75P0016 are not connected to pull-up resistors by mask

option, and are always open.

CHAPTER 1 GENERAL

1.2 ORDERING INFORMATION

Part number

Package

On-chip ROM

µPD750004CU-xxx

42-pin plastic shrink DIP (600 mil)

44-pin plastic QFP (10 x 10 mm)

42-pin plastic shrink DIP (600 mil)

44-pin plastic QFP (10 x 10 mm)

42-pin plastic shrink DIP (600 mil)

44-pin plastic QFP (10 x 10 mm)

42-pin plastic shrink DIP (600 mil)

44-pin plastic QFP (10 x 10 mm)

Masked ROM

One-time PROM

Note

µPD750004GB-xxx-3BS-MTX

µPD750006CU-xxx

Note

µPD750006GB-xxx-3BS-MTX

µPD750008CU-xxx

Note

µPD750008GB-xxx-3BS-MTX

µPD75P0016CU

Note

µPD75P0016GB-3BS-MTX

Note Code orders on and after April 1, 1996 can be accepted.

Remark xxx is a ROM code number.

µPD750008 USER'S MANUAL

1.3 DIFFERENCES AMONG SUBSERIES PRODUCTS

Item

Program counter

µPD750004

12 bits

µPD750006

13 bits

µPD750008

µPD75P0016

14 bits

Program memory (byte)

Masked ROM

4096

Masked ROM

6144

Masked ROM

8192

One-time PROM

16384

Data memory (x 4 bits)

512

Mask

Pull-up resistors at

Incorporated

None

option

ports 4 and 5

(Whether to incorporate pull-up resistors can

be specified.)

(Cannot be

incorporated.)

Wait time during

RESET

Available

Not available

(Fixed to 2 /f .)

Note

(Can be selected from 2 /f or 2 /f .)

Selection to use

feedback resistors

for subsystem clock

Yes

(Whether to enable feedback resistors can

be specified.)

(Use of feedback

resistors is factory-set)

6-9 (CU)

23-26 (GB)

20 (CU)

P33-30

P33/MD3-P30/MD0

connection

38 (GB)

Others

Noise immunity and noise radiation vary with the circuit scale and mask

layout.

Note 2 /f (21.8 ms at 6.0 MHz, 31.3 ms at 4.19 MHz)

2 /f (5.46 ms at 6.0 MHz, 7.81 ms at 4.19 MHz)

Caution The noise immunity and noise radiation of the PROM model differ from those of the mask

ROM model. If you replace the PROM model with the ROM model of the course of

experimental production to mass production, perform thorough evaluation by using the

CS model (not ES model) of the mask ROM model.

CHAPTER 1 GENERAL

1.4 BLOCK DIAGRAM

Port 0

Port 1

Port 2

Port 3

Port 4

Port 5

Port 6

Port 7

Port 8

P00 - P03

P10 - P13

Basic interval timer/

watchdog timer

RESET

INTBT

Program

ALU

counter^{Note 1}

SBS

TI0

Timer/event

counter

P20 - P23

PTO0

BANK

TOUT0 INTT0

P30 - P33

P30/MD0 -

Note 3

General register

(

)

P33/MD3

Timer counter

INTT1

PTO1

BUZ

ROM^{Note 2}

program

memory

Decode and

control

P40 - P43

RAM

data memory

512 x 4 bits

Wach timer

INTW

P50 - P53

SI/SB1

SO/SB0

SCK

P60 - P63

P70 - P73

Clocked serial

interface

/2^N

CPU clock

TOUT0

INTCSI

Clock generator

Clock output

control

Standby

control

INT0

INT1

INT2

INT4

Clock divider

Sub

Main

P80, P81

Interrupt

control

KR0 - KR7

PCL/P22

XT1 XT2

X1 X2

Bit sequential

buffer (16)

VDD

V^SSRESET

(V^PP)^{Note 3}

Notes 1. The program counter for the µPD750004 consists of 12 bits, 13 bits for the µPD750006 and

µPD750008, and 14 bits for the µPD75P0016.

2. The ROM capacity depends on the product.

3. ( ) : µPD75P0016

µPD750008 USER'S MANUAL

1.5 PIN CONFIGURATION (TOP VIEW)

(1) 42-pin plastic shrink DIP (600 mil)

µPD750004CU-XXX

µPD750006CU-XXX

µPD750008CU-XXX

µPD75P0016CU

VSS

XT1

XT2

P40

P41

RESET

P42

P43

P50

P33 (/MD3)

P32 (/MD2)

P31 (/MD1)

P30 (/MD0)

P81

P51

P52

P53

P60/KR0

P61/KR1

P62/KR2

P63/KR3

P70/KR4

P71/KR5

P72/KR6

P73/KR7

P20/PTO0

P21/PTO1

P22/PCL

P23/BUZ

P80

SI/SB1/P03

SO/SB0/P02

SCK/P01

INT4/P00

TI0/P13

INT2/P12

INT1/P11

INT0/P10

IC (V^PP)^Note

V^DD

Note Connect IC (V ) to V , keeping the wiring as short as possible.

Remark ( ) : µPD75P0016.

CHAPTER 1 GENERAL

(2) 44-pin plastic QFP (10 x 10 mm)

µPD750004GB-XXX-3BS-MTX

µPD750006GB-XXX-3BS-MTX

µPD750008GB-XXX-3BS-MTX

µPD75P0016GB-3BS-MTX

44 43 42 41 40 39 38 37 36 35 34

P72/KR6

P71/KR5

P70/KR4

P63/KR3

P62/KR2

P61/KR1

P60/KR0

P53

P13/TI0

P00/INT4

P01/SCK

P02/SO/SB0

P03/SI/SB1

P80

P81

P30 (/MD0)

P31 (/MD1)

P32 (/MD2)

P33 (/MD3)

P52

P51

P50

12 13 14 15 16 17 18 19 20 21 22

Note Connect IC (V ) to V , keeping the wiring as short as possible.

Remark ( ) : µPD75P0016.

µPD750008 USER'S MANUAL

Pin name

P00-P03 : Port 0

P10-P13 : Port 1

P20-P23 : Port 2

P30-P33 : Port 3

P40-P43 : Port 4

P50-P53 : Port 5

P60-P63 : Port 6

P70-P73 : Port 7

P80-P81 : Port 8

KR0-KR7 : Key return

RESET

TI0

: Reset input

: Timer input 0

PTO0, 1 : Programmable timer output 0, 1

BUZ

PCL

: Buzzer clock

: Programmable clock

INT0, 1, 4 : External vectored interrupt 0, 1, 4

INT2

X1, 2

XT1, 2

: External test input 2

: Main system clock oscillation 1, 2

: Subsystem clock oscillation 1, 2

: No connection

SCK

: Serial clock

: Serial input

: Serial output

: Internally connected

: Positive power supply

: Ground

SB0, 1 : Serial bus 0, 1

: Programming power supply

MD0-MD3 : Mode selection 0 - 3

CHAPTER 2 PIN FUNCTIONS

2.1 PIN FUNCTIONS OF THE µPD750008

Table 2-1. Digital I/O Port Pins (1/2)

Also

used

I/O

Input/

output

8 bit

I/O

Upon

reset

Function

circuit

Note 1

type

P00

Input

I/O

INT4

4-bit input port (PORT0).

Input

P01

P02

P03

P10

P11

P12

P13

SCK

For P01 to P03, built-in pull-up resistors

can be connected by software in units of

3 bits.

F -A

F -B

M -C

B -C

I/O

SO/SB0

SI/SB1

INT0

I/O

Input

4-bit input port (PORT1).

Input

INT1

Built-in pull-up resistors can be connected

by software in units of 4 bits. Only the

INT2

TI0

P10/INT0 pin is provided with noise

elimination function.

P20

P21

P22

P23

P30

P31

P32

P33

I/O

PTO0

PTO1

PCL

4-bit I/O port (PORT2).

Input

E-B

Built-in pull-up resistors can be connected

by software in units of 4 bits.

BUZ

Note 2

Note 3

(MD0)

(MD1)

(MD2)

(MD3)

Programmable 4-bit I/O port (PORT3).

I/O can be specified bit by bit.

Note 3

Built-in pull-up resistors can be connected

by software in units of 4 bits.

Notes 1. I/O circuits enclosed in circles have a Schmitt-triggered input.

2. An LED can be driven directly.

3. ( ): µPD75P0016

µPD750008 USER'S MANUAL

Table 2-1. Digital I/O Port Pins (2/2)

Also

used

I/O

circuit

8 bit

I/O

Upon

reset

Input

output

Function

Note 1

type

P40-

I/O

—

N-ch open-drain 4-bit I/O port (PORT4).

Withstand voltage is 13 V in open-drain

mode.

High level (when M-D

Note 2, 4

Note 3

P43

a pull-up resistor (M-E)

is provided) or

A pull-up resistor can be provided bit

high impedance

Note 5

by bit (mask option)

Data input/output pins for writing/

verifying (lower 4 bits of program

memory (PROM).

P50-

I/O

—

N-ch open-drain 4-bit I/O port (PORT5).

Withstand voltage is 13 V in open-drain

mode.

High level (when M-D

a pull-up resistor (M-E)

is provided) or

Note 2, 4

Note 3

P53

A pull-up resistor can be provided bit

high impedance

Note 5

by bit (mask option)

Data input/output pins for writing/

verifying (higher 4 bits of program

memory (PROM).

P60

P61

P62

P63

P70

P71

P72

P73

P80

P81

I/O

KR0

KR1

KR2

KR3

KR4

KR5

KR6

KR7

—

Programmable 4-bit I/O port (PORT6).

I/O can be specified bit by bit.

Built-in pull-up resistors can be

connected by software in units of 4 bits.

4-bit I/O port (PORT7).

Input

F -A

Built-in pull-up resistors can be

connected by software in units of

4 bits.

2-bit input port (PORT8).

E-B

—

Built-in pull-up resistors can be

connected by software in units of 2 bits.

Notes 1. I/O circuits enclosed in circles have a Schmitt-triggered input.

2. An LED can be driven directly.

3. ( ): µPD75P0016

4. When pull-up resistors that can be specified with the mask option are not

incorporated (when pins are used as N-ch open-drain input ports), the input leak low

current increases when an input instruction or bit operation instruction is executed.

5. These pins of the µPD75P0016 are not provided with pull-up resistors by mask option, and are

always open.

CHAPTER 2 PIN FUNCTIONS

Table 2-2. Non-Port Pin Functions

Also

used

I/O

Upon

Input/

output

Function

circuit

reset

Note 1

type

TI0

Input

I/O

P13

Inputs external event pulse to the timer/event counter

Timer/event counter output

—

B -C

PTO0

PTO1

PCL

P20

P21

P22

P23

Input

E-B

Timer counter output

I/O

Clock output

Input

E-B

BUZ

Fixed frequency output

(for buzzer or system clock trimming)

Serial clock I/O

SCK

I/O

P01

P02

P03

P00

Input

—

F -A

F -B

M -C

SO/SB0

SI/SB1

INT4

I/O

Serial data output or serial data bus I/O

Serial data input or serial data bus I/O

Edge detection vectored interrupt input

(Either a rising or falling edge is detected.)

The INT0/P10 pin has a noise eliminating function.

I/O

Input

INT0

INT1

INT2

Input

P10

P11

P12

Edge detection vectored interrupt input

(The edge to be detected is selectable.) Asynchronous

Rising edge detection testable input Asynchronous

Synchronous

—

B -C

—

Input

—

B -C

F -A

—

KR0-KR3 I/O

KR4-KR7 I/O

P60-P63 Parallel falling edge detection testable input

P70-P73 Parallel falling edge detection testable input

X1, X2

Input

—

Connection pin to a crystal/ceramic resonator for main

system clock generation.

When external clock is used, it is input to X1,

and its inverted signal is input to X2.

Connection pin to a crystal for subsystem clock

generation.

XT1

Input

—

XT2

When external clock is used, it is input to XT1, and

XT2 is left open.

RESET

Input

—

System reset input

—

Note 2

Internally connected.

—

Connect to V , keeping the wiring as short as possible.

—

Positive power supply

GND potential

—

Note 2

P10/INT0 Program voltage application for program memory

(PROM) write/verify operation.

+12.5 V is applied for PROM write/verify operation.

Connect to V , keeping the wiring as short as

possible.

MD0-

MD3

I/O

—

P30-P33 Mode selection for program memory (PROM)

write/verify operation.

Input

—

E-B

—

Note 3

—

No connection

Notes 1. The circuits enclosed in circles have a Schmitt-triggered input.

2. Used as the V pin for the µPD75P0016.

3. Provided only in the µPD75P0016.

µPD750008 USER'S MANUAL

2.2 PIN FUNCTIONS

2.2.1 P00-P03 (PORT0) : Input Pins Used Also for INT4, SCK, SO/SB0 and SI/SB1

P10-P13 (PORT1) : Input Pins Used Also for INT0-INT2, and TI0

These are the input pins of the 4-bit input ports: Ports 0 and 1.

Ports 0 and 1 function as input ports, and also have the functions described below.

(1) Port 0 : Vectored interrupt input (INT4)

Serial interface I/O (SCK, SO/SB0, SI/SB1)

(2) Port 1 : Vectored interrupt input (INT0, INT1)

Edge detection test input (INT2)

External event pulse input (TI0) for timer/event counter

Input is always enabled for each pin of ports 0 and 1 regardless of the operation status of the other function

of the pin.

Schmitt-triggered inputs are used for the input pin of port 0 and pins of port 1 to prevent malfunction due

to noise. In addition, a noise eliminator is provided for P10. (See (3) of Section 6.3.)

Port 0 can be connected with built-in pull-up resistors in units of 3 bits (P01 to P03) by software. Port 1

can be connected with built-in pull-up resistors in units of 4 bits (P10 to P13) by software. This is done by

manipulating pull-up resistor specification register group A (POGA).

A RESET signal input places these pins in the input port mode.

CHAPTER 2 PIN FUNCTIONS

2.2.2 P20-P23 (PORT2) : I/O Pins Used Also for PTO0, PTO1, PCL, and BUZ

Note

P30-P33 (PORT3) : I/O Pins Used Also for MD0-MD3

P40-P43 (PORT4),

P50-P53 (PORT5) : N-ch Open-Drain Intermediate Withstand Voltage (13 V) Large-Current

Output

P60-P63 (PORT6),

P70-P73 (PORT7) : Tristate I/O

These pins are the I/O pins of the 4-bit I/O ports with output latches: Ports 2 to 7.

Port n (n = 2, 3, 6, and 7) functions as I/O ports, and also have the following functions:

(1) Port 2

: Timer/event counter (PTO0, PTO1)

Clock output (PCL)

Fixed frequency output (BUZ)

Note

(2) Port 3

: Mode selection for program memory (PROM) write/verify operation (MD0-MD3)

(3) Ports 6 and 7: Key interrupt input (KR0-KR3, KR4-KR7)

Note Provided only in the µPD75P0016.

Port 3 is a large-current output. Ports 4 and 5 are N-ch open-drain intermediate withstand voltage (13 V)

large-current output. These ports can directly drive the LED.

An I/O mode is selected by the port mode register. The I/O mode of port m (m = 2, 4, 5, and 7) can be

selected in units of 4 bits, and the I/O mode of ports 3 and 6 can be selected bit by bit.

Port n can be connected with built-in pull-up resistors in units of 4 bits by software. This can be done by

manipulating pull-up resistor specification register group A (POGA). For ports 4 and 5, the use of built-in pull-

up resistors can be specified bit by bit by mask option.

Ports 4 and 5, and ports 6 and 7 can be paired respectively for 8-bit I/O.

A RESET input clears the output latches in the ports, places port n in the input mode (output high-

impedance state), and drives ports 4 and 5 high if pull-up resistors are provided or causes ports 4 and 5

to go into a high-impedance state.

2.2.3 P80, P81 (PORT8)

These pins are the I/O pins of the 2-bit I/O ports with output latches: Port 8.

Port 8 can be connected with built-in pull-up resistors in units of 2 bits by software. This can be done by

manipulating pull-up resistor specification register group B (POGB).

2.2.4 TI0: Input Pin Used Also for Port 1

This is an external event pulse input pin for the programmable timer/event counter.

A Schmitt-triggered input is used for the TI0 pin.

2.2.5 PTO0, PTO1: Output Pin Used Also for Port 2

This is the output signal pin of the programmable timer/event counter and programmable timer counter.

Square-wave pulses appear on this pin. To output a signal from the programmable timer/event counter and

programmable timer counter, the output latch P20 or P21 must be cleared to 0, and the bit for port 2 in the

port mode register must be set to 1 (output mode).

The output is cleared to 0 by the timer start instruction.

µPD750008 USER'S MANUAL

2.2.6 PCL: Output Pin Used Also for Port 2

This is the programmable clock output pin. It is used to supply the clock pulse to a peripheral LSI circuit

such as a slave microcomputer or A/D converter.

A RESET signal clears the clock mode register (CLOM) to 0, disabling clock output, then the pin is placed

in the normal mode to function as a normal port.

2.2.7 BUZ: Output Pin Used Also for Port 2

An arbitrary frequency (2.048, 4.096, or 32.768 kHz) output on this pin can be used for sounding the buzzer

or trimming the system clock frequency. This pin is used also as the P23 pin, and can be used only when

bit 7 (WM.7) of the clock mode register (WM) is set to 1.

A RESET signal places this pin in the normal operation mode as a general port (see Section 5.4.2 for

details).

2.2.8 SCK, SO/SB0, SI/SB1: Tristate I/O Pins Used Also as Port 0

These are I/O pins for serial interface. They operate according to the setting of the serial operation mode

registers (CSIM).

A RESET signal stops serial interface operation and places these pins in the input port mode.

A Schmitt-triggered input is used for each pin.

2.2.9 INT4: Input Pin Used Also as Port 0

INT4 is an external vectored interrupt input pin, which is rising edge active as well as falling edge active.

When a signal applied to this pin goes from low to high or from high to low, the interrupt request flag is set.

INT4 is an asynchronous input, and can accept a signal with some high level width or low level width

regardless of what the CPU clock is.

The INT4 pin can also be used to release the STOP and HALT modes. A Schmitt-triggered input is used

for this pin.

2.2.10 INT0, INT1: Input Pins Used Also for Port 1

These are edge detection vectored interrupt input pins. INT0 has a noise eliminator. The edge to be

detected can be selected using the edge detection mode registers (IM0, IM1).

(1) INT0 (bits 0 and 1 of IM0)

(a) Rising edge active

(b) Falling edge active

(d) External interrupt signal input disabled

(2) INT1 (bit 0 of IM1)

(a) Rising edge active

(b) Falling edge active

CHAPTER 2 PIN FUNCTIONS

INT0 has a noise eliminator. Two different sampling clocks for noise elimination can be switched. The

acceptable width of a signal depends on the CPU clock.

INT1 is an asynchronous input, and can accept a signal with some high level width regardless of what the

CPU clock is.

A RESET input clears IM0 and IM1 to 0, selecting rising edge active.

The INT1 pin can also be used to release the STOP and HALT modes, but the INT0 pin cannot.

Schmitt-triggered inputs are used for the INT0 and INT1 pins.

2.2.11 INT2: Input Pin Used Also for Port 1

This is a rising edge active, external test input pin. When INT2 is selected with the edge detection mode

INT2 is an asynchronous input, and can accept a signal with some high level width regardless of the

operating clock of the CPU.

A RESET signal clears IM2 to 0. In this case, the test flag (IRQ2) is set by a rising edge on the INT2 pin.

The INT2 pin can also be used to release the STOP and HALT modes. A Schmitt-triggered input is used

for this pin.

2.2.12 KR0-KR3: Input Pins Used Also for Port 6

KR4-KR7: Input Pins Used Also for Port 7

KR0 to KR7 are key interrupt input pins. An interrupt is caused when parallel falling edges are detected

on them. The interrupt format can be specified with the edge detection mode register (IM2).

A RESET signal places these pins in the port 6 and 7 input modes.

2.2.13 X1, X2

These pins are used for connection to a crystal or ceramic resonator for main system clock generation.

An external clock can also be applied.

(a) Crystal/ceramic oscillation

(b) External clock

µPD750008

External

clock

VSS

PD74HC04

Crystal or ceramic resonator

(Standard frequency:

4.194304 or 6.0 MHz)

µPD750008 USER'S MANUAL

2.2.14 XT1, XT2

These pins are used for connection to a crystal for subsystem clock oscillation.

An external clock can also be applied.

(a) Crystal oscillation

(b) External clock

µPD750008

VSS

External

clock

XT1

XT2

Crystal

(Standard frequency:

32.768 kHz)

2.2.15 RESET

This is the pin for active-low reset input.

The RESET input is asynchronous. When a signal with certain low level width is applied to the pin, a RESET

signal is generated to cause a system reset, which has priority over any other operations.

The RESET signal is used for normal CPU initialize/start operation, and is also used to release the standby

(STOP or HALT) mode.

A Schmitt-triggered input is used for the RESET input pin.

2.2.16

This is the positive power supply pin.

2.2.17

This is the ground pin.

CHAPTER 2 PIN FUNCTIONS

2.2.18 IC (for the µPD750004, µPD750006, and µPD750008 only)

The internally connected (IC) pin is used to set the µPD750008 to test mode for inspection prior to shipping.

In normal operation, connect the IC pin to the V pin, keeping the writing as short as possible.

When the wiring between the IC pin and the V pin is too long, or noise is generated on the IC pin, a potential

difference may occur between the IC pin and the V

pin. This may cause your program to malfunction.

• Connect the IC pin to the V

pin, keeping the wiring as short as possible.

Keep the wiring

as short as possible

VDD

IC (VPP)

VDD

2.2.19

(for the µPD75P0016 only)

This is a program voltage input pin for program memory (PROM) write/verify operation.

For normal use, connect this pin to V , keeping the wiring as short as possible (shown above).

+12.5 V is applied for PROM write/verify operation.

2.2.20 MD0-MD3 (for the µPD75P0016 only): I/O Pins Used Also for Port 3

MD0 to MD3 select a mode for program memory (PROM) write/verify operation.

µPD750008 USER'S MANUAL

2.3 PIN INPUT/OUTPUT CIRCUITS

Figure 2-1 shows schematic diagrams of the I/O circuitry of the µPD750008.

Figure 2-1. Pin Input/Output Circuits (1/2)

Type B-C

Type A

V^DD

VDD

P.U.R.

P-ch

P.U.R.

enable

P-ch

N-ch

CMOS input buffer

P.U.R.: Pull-Up Resistor

Type B

Type D

VDD

Data

P-ch

N-ch

OUT

Output

disable

Schmitt trigger input with hysteresis

Push-pull output which can be set to high-impedance output

(off for both P-ch and N-ch)

CHAPTER 2 PIN FUNCTIONS

Figure 2-1. Pin Input/Output Circuits (2/2)

V^DD

Type M-C

Type E-B

VDD

P.U.R.

enable

P.U.R.

enable

P-ch

IN/OUT

Data

IN/OUT

Type D

Type A

Data

Output

disable

N-ch

Output

disable

P.U.R.: Pull-Up Resistor

Type F-A

Type M-D*

V^DD

Input instruction

P-ch

P.U.R.

P-ch

VDD

P.U.R.

(Mask option)

P.U.R ^Note

IN/OUT

P.U.R.

enable

Data

IN/OUT

N-ch

(Withstand

voltage:13 V)

Type D

Output

disable

Output

disable

Type B

Input buffer with an intermediate

withstand voltage of +13 V

P.U.R.: Pull-Up Resistor

Note Pull-up resistor that operates only when an input

instruction is excuted (valid at low voltage)

VDD

Type M-E*

Type F-B

V^DD

P.U.R.

Input instruction

P-ch

P.U.R.

enable

P-ch

Note

Output

disable

(P-ch)

VDD

IN/OUT

Data

N-ch

P-ch

(Withstand

voltage:13 V)

Output

disable

IN/OUT

Data

Output

disable

N-ch

Output

disable

(N-ch)

Input buffer with an intermediate

withstand voltage of +13 V

Note Pull-up resistor that operates only when an input

instruction is executed (valid at low voltage)

P.U.R.: Pull-Up Resistor

µPD750008 USER'S MANUAL

2.4 CONNECTION OF UNUSED PINS

Table 2-3. Connection of Unused Pins

Pin name

Recommended connection

P00/INT4

P01/SCK

To be connected to V

or V

P02/SO/SB0

P03/SI/SB1

P10/INT0-P12/INT2

P13/TI0

To be connected to V

P20/PTO0

P21/PTO1

P22/PCL

Input state:

To be connected to V

through a resistor

Output state: To be left open

P23/BUZ

Note

P30(/MD0)-P33(/MD3)

P40-P43

P50-P53

P60-P63

P70-P73

P80-P81

XT1

To be connected to V

To be left open

or V

SS DD

XT2

Note

IC (V

)

To be connected directly to V

Note ( ): µPD75P0016

CHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAP

The 75XL series architecture of the µPD750008 has the following features:

• Internal RAM of up to 4K words x 4 bits (12-bit address)

• Peripheral hardware expansibility

To provide these features, the following are used:

(1) Data memory bank structure

(2) General register bank structure

(3) Memory-mapped I/O

This chapter explains these topics.

3.1 DATA MEMORY BANK STRUCTURE AND ADDRESSING MODES

3.1.1 Data Memory Bank Structure

In the µPD750008, addresses 000H to 1FFH in data memory space are assigned to static RAM (512 words

x 4 bits), and addresses F80H to FFFH are assigned to peripheral hardware (such as I/O ports and timers).

To address a 12-bit location in this data memory space (4K x 4 bits), the µPD750008 uses such a memory

bank structure that the low-order eight bits are specified with an instruction directly or indirectly, and the high-

order four bits are used to specify a memory bank.

To specify a memory bank (MB), two hardware items are incorporated:

• Memory bank enable flag (MBE)

• Memory bank select register (MBS)

The MBS is a register used to select a memory bank, and the register can be set to 0, 1, or 15. The MBE

is a flag used to determine whether the memory bank selected using the MBS is valid. As shown in Figure

3-1, when the MBE is set to 0, a certain memory bank is always selected regardless of the setting of the MBS.

When the MBE is set to 1, memory bank selection depends on the setting of the MBS, thus enabling data

memory space expansion.

In addressing data memory space, the MBE is usually set to 1 (MBE = 1), and data memory in the memory

bank specified in the MBS is operated. However, the MBE = 0 mode or MBE = 1 mode can be selected for

each step of processing for more efficient programming.

µPD750008 USER'S MANUAL

Applicable program processing

Effect

MBE = 0 mode

MBE = 1 mode

•

Interrupt processing

MBS save/restoration becomes unnecessary.

MBS modification becomes unnecessary.

Processing that repeats internal

hardware and static RAM operations

•

Subroutine processing

MBS save/restoration becomes

Usual program processing

Figure 3-1. Use of MBE = 0 Mode and MBE = 1 Mode

SET1 MBE

MBE

= 1

CLR1 MBE

MBE = 0

CLR1 MBE

Internal hardware

and static RAM

operations are

repeated.

MBE

= 0

RET <Interrupt processing>

; MBE = 0 is to be set in the vector table.

SET1 MBE

MBE = 0

MEB

= 1

RETI

The contents of the MBE are automatically saved or restored at the time of subroutine processing, so that

the MBE can be freely modified during subroutine processing. In interrupt processing, the MBE is automatically

saved or restored, and when interrupt processing is started, the contents of the MBE can be specified for the

interrupt processing by setting the interrupt vector table. This speeds up interrupt processing.

The setting of the MBS can be modified for subroutine processing or interrupt processing by saving or

restoring the MBS with the PUSH or POP instruction.

The MBE is set using the SET1 or CLR1 instruction. The MBS is set using the SEL instruction.

Examples 1. The MBE is cleared, and a fixed memory bank is used.

CLR1

MBE

; MBE <– 0

2. Memory bank 1 is selected.

SET1

SEL

MBE

MB1

; MBE <– 1

; MBS <– 1

CHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAP

3.1.2 Data Memory Addressing Modes

With the architecture of the µPD750008, seven addressing modes summarized in Figures 3-2 and 3-3, and

Table 3-1 are available to address data memory space efficiently for each bit length of data to be processed.

These addressing modes enable more efficient programming.

(1) 1-bit direct addressing (mem.bit)

In this addressing mode, the operand of an instruction can directly specify any bit in the entire data memory

space.

A particular memory bank (MB) is always used in this addressing mode. In the MBE = 0 mode, when an

address from 00H to 7FH is specified in the operand, memory bank 0 (MB = 0) is always used. When

an address from 80H to FFH is specified, memory bank 15 (MB = 15) is always used. Accordingly, both

the data area ranging from 000H to 07FH and the peripheral hardware area ranging from F80H to FFFH

can be addressed in the MBE = 0 mode.

In the MBE = 1 mode, MB = MBS, and specifiable data memory space can be expanded.

This addressing mode can be applied to four instructions: bit set and reset instructions (SET1 and CLR1),

and bit test instructions (SKT and SKF).

Example FLAG1 is set, FLAG2 is reset, and whether FLAG3 is zero is tested.

FLAG1

FLAG2

FLAG3

EQU

03FH.1 ; Bit 1 at address 3FH

087H.2 ; Bit 2 at address 87H

0A7H.0 ; Bit 0 at address A7H

SET1

SEL

MBE

MB0

; MBE <– 1

; MBS <– 0

SET1

CLR1

SKF

FLAG1 ; FLAG1 <– 1

FLAG2 ; FLAG2 <– 0

FLAG3 ; FLAG3 = 0?

µPD750008 USER'S MANUAL

Figure 3-2. Data Memory Organization and Addressing Range of Each Addressing Mode

Stack

mem

mem.bit

@HL

@H+mem.bit

@DE

@DL

Addressing mode

address- fmem.bit pmem.@L

ing

MBE

—

Memory bank enable flag

000H

Area for

general register

01FH

020H

07FH

MBS

SBS

Data area

Static RAM

(memory bank 0)

0FFH

100H

Data area

Static RAM

(memory bank 1)

MBS

SBS

1FFH

F80H

Not provided

Peripheral hardware area

(memory bank 15)

MBS

=15

MBS

=15

FC0H

FFFH

Remark – : Don't care

CHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAP

Table 3-1. Addressing Modes

Representation

format

Addressing mode

Specified address

1-bit direct

addressing

mem.bit

Bit specified by bit at the address specified by MB and mem.

• When MBE = 0 and

mem = 00H-7FH,

mem = 80H-FFH,

MB = 0

MB = 15

• When MBE = 1,

MB = MBS

4-bit direct

addressing

mem

Address specified by MB and mem.

• When MBE = 0 and

mem = 00H-7FH,

mem = 80H-FFH,

MB = 0

MB = 15

• When MBE = 1,

MB = MBS

8-bit direct

addressing

Address specified by MB and mem (mem: even address).

• When MBE = 0 and

mem = 00H-7FH,

mem = 80H-FFH,

MB = 0

MB = 15

• When MBE = 1,

MB = MBS

4-bit register

indirect

addressing

@HL

@HL+

@HL–

Address specified by MB and HL.

In this case, MB = MBE·MBS

HL+ automatically increments the L register after addressing.

HL– automatically decrements the L register after addressing.

@DE

@DL

@HL

Address specified by DE in memory bank 0

Address specified by DL in memory bank 0

8-bit register

indirect

Address specified by MB and HL. (Contents of the L register is

an even address.)

addressing

In this case, MB = MBE·MBS

Bit

fmem.bit

Bit specified by bit at the address specified by fmem.

In this case,

fmem = FB0H-FBFH (interrupt-related hardware)

FF0H-FFFH (I/O ports)

manipulation

addressing

pmem.@L

Bit specified by the low-order two bits of the L register

at the address specified by the high-order 10 bits of pmem and the

high-order two bits of the L register.

In this case, pmem = FC0H-FFFH

@H+mem.bit

—

Bit specified by bit at the address specified by MB, H, and the low-

order four bits of mem.

In this case, MB = MBE·MBS

Stack addressing

Address specified by the SP in memory bank selected by the SBS

µPD750008 USER'S MANUAL

(2) 4-bit direct addressing (mem)

In this addressing mode, the operand of an instruction directly specifies any area in the data memory space

in units of four bits.

As with the 1-bit direct addressing mode, in the MBE = 0 mode, a fixed space consisting of the static RAM

area ranging from 000H to 07FH and the peripheral hardware area ranging from F80H to FFFH can be

addressed. In the MBE = 1 mode, MB = MBS, and specifiable data memory space can be expanded to

the entire space.

This addressing mode can be applied to the MOV, XCH, INCS, IN, and OUT instructions.

Caution Less efficient program processing results if data associated with an I/O port is stored in

the static RAM area of bank 1 as in Example 1. The modification of the MBS, as contained

in Example 2, becomes unnecessary in the programming if data associated with an I/O

port is stored at addresses 00H to 7FH of bank 0.

Examples 1. The data contained in BUFF is output on port 5.

BUFF

EQU

SET1

SEL

11AH

MBE

; BUFF located at address 11AH

; MBE <– 1

MB1

; MBS <– 1

MOV

SEL

A,BUFF

MB15

; A <– (BUFF)

; MBS <– 15

OUT

PORT5,A ; PORT5 <– A

2. Data on port 4 is entered, and is saved in DATA1.

DATA1 EQU

5FH

; DATA1 located at address 5FH

; MBE <– 0

CLR1

MBE

A,PORT4 ; A <– PORT4

DATA1,A ; (DATA1) <– A

MOV

(3) 8-bit direct addressing (mem)

In this addressing mode, the operand of an instruction directly specifies any area in the data memory space

in units of eight bits.

The operand can specify an even address. The 4-bit data at the address specified in the operand and

the 4-bit data at the address incremented by 1 are processed as a pair on an 8-bit basis with the 8-bit

accumulator (XA register pair).

A memory bank is specified in the same way as the 4-bit direct addressing.

This addressing mode can be applied to the MOV, XCH, IN, and OUT instructions.

Example 1. Eight-bit data from port 4 and port 5 is transferred to addresses 20H and 21H.

DATA

EQU

CLR1

020H

MBE

; MBE <– 0

XA,PORT4 ; X <– PORT5 , A <– PORT4

DATA,XA ; (21H) <– X, (20H) <– A

MOV

CHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAP

Example 2. Eight-bit data is latched into the serial interface shift register (SIO), and the transfer data

is set at the same time.

SEL

MB15

; MBS <– 15

XCH

XA,SIO

; XA <—> (SIO)

(4) 4-bit register indirect addressing (@rpa)

In this addressing mode, the pointer (general register pair) specified in the operand of an instruction

indirectly specifies a data memory space in units of four bits.

There are three types of data pointers. One is the HL register pair, which can specify any area in the data

memory space when MB = MBE·MBS is specified. The other two are the DE register pair and DL register

pair, with which memory bank 0 is always used regardless of how the MBE and MBS are specified. More

efficient programming is possible by selecting a data pointer according to a data memory bank to be used.

When the HL register pair is specified, the L register can be incremented or decremented by one in the

automatic increment or automatic decrement mode each time an instruction is executed, thus simplifying

the program step.

Example The data at 50H to 57H is transferred to 110H to 117H.

DATA1

DATA2

EQU

SET1

SEL

57H

117H

MBE

; MBE <– 1

MB1

; MBS <– 1

MOV

XCH

D,#DATA1 SHR4

HL,#DATA2 AND 0FFH

A,@DL

; D <– 5

; HL <– 17H

; A <– (DL)

LOOP:

A,@HL–

; A <—> (HL), L <– L – 1

LOOP

The addressing mode using the HL register pair as the data pointer finds a wide range of operations such

as data transfer, operations, comparison, and I/O. The addressing mode using the DE register pair or

DL register pair is applied to the MOV and XCH instructions.

This addressing mode, combined with an increment/decrement instruction for a general register or register

pair, enables data memory space addresses to be freely updated as shown in Figure 3-3.

Example 1. The data at 50H to 57H is compared with the data at 110H to 117H.

DATA1 EQU

DATA2 EQU

SET1

57H

117H

MBE

SEL

MB1

MOV

D,#DATA1 SHR4

HL,#DATA2 AND 0FFH

A,@DL

MOV

LOOP: MOV

SKE

A,@HL

; A = (HL)?

; NO

DECS

; YES, L <– L – 1

LOOP

µPD750008 USER'S MANUAL

Example 2. The data memory of 00H to FFH is cleared to 0.

CLR1

RBE

MBE

MOV

XA,#00H

HL,#04H

@HL,A

MOV

LOOP: MOV

INCS

; (HL) <– A

; HL <– HL + 1

LOOP

Figure 3-3. Updating Static RAM Addresses

x 0H

x FH

0 x H

DECS D

@DE

DECS E

INCS E

@DL

DECS L

INCS L

4-bit transfer

DECS DE

INCS DE

INCS D

Direct

addressing

Bit manipulation

4-bit transfer

8-bit transfer

DECS H

@HL

DECS H

Automatic

decrement

Automatic

increment

4-bit

manipulation

@H + mem.bit

DECS L

INCS L

Bit manipulation

8-bit

manipulation

DECS HL

INCS HL

INCS H

F x H

CHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAP

(5) 8-bit register indirect addressing (@HL)

In this addressing mode, the data pointer (HL register pair) indirectly specifies any area in the data memory

space in units of eight bits.

The 4-bit data at the address determined with bit 0 of the data pointer (bit 0 of the L register) set to 0 and

the 4-bit data at the address incremented by 1 are processed as a pair on an 8-bit basis with the 8-bit

accumulator (XA register pair).

A memory bank is specified in the same way as the 4-bit register indirect addressing with the HL register

specified. In this case, MB = MBE·MBS.

This addressing mode can be applied to the MOV, XCH, and SKE instructions.

Examples 1. A comparison is made to determine whether the value of the count register (T0) of timer/

event counter 0 is equal to the data at addresses 30H and 31H.

DATA

EQU

CLR1

MOV

SKE

30H

MBE

HL,#DATA

XA,T0

; XA <– Count register 0

; XA = (HL)?

XA,@HL

2. The data memory of 00H to FFH is cleared to 0.

CLR1

MOV

INCS

RBE

MBE

XA,#00H

HL,#04H

@HL,XA

LOOP:

; (HL) <– XA

LOOP

(6) Bit manipulation addressing

This addressing mode is used to perform bit manipulations (such as Boolean operations and bit transfer)

for each bit in the data memory space.

The 1-bit direct addressing mode can be applied only to the set, reset, and test instructions. On the other

hand, the bit manipulation addressing enables a wide variety of bit manipulations such as Boolean

operations using the AND1, OR1, and XOR1 instructions, bit transfers using the MOV1 instruction, and

test and reset operations using the SKTCLR instruction.

There are three types of bit manipulation addressing. The user can choose from these options according

to the data memory address used.

µPD750008 USER'S MANUAL

(a) Specific address bit direct addressing (fmem.bit)

In this addressing mode, peripheral equipment that frequently performs bit manipulations involving,

for example, I/O ports and interrupt flags, can be processed at all times regardless of memory bank

setting. Accordingly, the data memory addresses that allow this addressing mode to be used are FF0H

to FFFH where I/O ports are mapped, and FB0H to FBFH where interrupt-related hardware is mapped.

Hardware mapped to these data memory areas can freely perform bit manipulations in the direct

addressing mode at any time regardless of MBS and MBE setting.

Examples 1. Value input to P02 is inverted, and the result is output on P33.

MOV1

NOT1

MOV1

CY, PORT0.2

PORT3.3, CY

2. The timer 0 interrupt request flag (IRQT0) is tested. The request flag, if set, is cleared,

and P63 is reset.

SKTCLR

IRQT0

; IRQT0 = 1?

; NO

CLR1

PORT6.3

; YES

3. If both P30 and P41 are set to 1, P53 is reset.

P30

P53

P41

MOV1

AND1

NOT1

MOV1

CY, PORT3.0

CY, PORT4.1

; CY <– P30

; CY P41

; CY <– CY

; P53 <– CY

PORT5.3, CY

CHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAP

(b) Specific address bit register indirect addressing (pmem.@L)

In this addressing mode, the bits of peripheral hardware I/O ports are indirectly specified using a

addresses FC0H to FFFH.

In this addressing mode, the high-order 10 bits of a 12-bit data memory address is directly specified

in the operand, and the low-order two bits and bit address are indirectly specified using the L register.

Thus the use of the L register enables 16 bits (four ports) to be continuously manipulated.

This addressing mode again enables bit manipulation regardless of MBE and MBS setting.

Example Pulses are output on the bits in the order from port 4 to port 7.

P40

P41

P73

MOV

SET1

CLR1

INCS

NOP

L,#0

LOOP:

PORT4.@L

; Bits (L ) of ports 4 to 7 <– 1

1-0

; Bits (L ) of ports 4 to 7 <– 0

1-0

LOOP

µPD750008 USER'S MANUAL

This addressing mode enables any bit in the data memory space to be manipulated.

In this addressing mode, the high-order four bits of the data memory address in the memory bank

specified by MB = MBE·MBS are indirectly specified using the H register, and the low-order four bits

and bit address are directly specified in the operand. This addressing mode enables a wide variety

of manipulations for each bit in the entire data memory space.

Example Bit 2 at address 32H (FLAG3) is reset if both bit 3 at address 30H (FLAG1) and bit 0 at

address 31H (FLAG2) are set to 0 or 1.

FLAG1

FLAG3

FLAG2

FLAG1

FLAG2

FLAG3

EQU

SEL

30H.3

31H.0

32H.2

MB0

MOV

H,#FLAG1 SHR 6

MOV1 CY, @H+FLAG1

XOR1 CY, @H+FLAG2

MOV1 @H+FLAG3, CY

; CY <– FLAG1

; CY <– CY FLAG2

; FLAG3 <– CY

CHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAP

(7) Stack addressing

This addressing mode is used for save/restoration operation in interrupt processing or subroutine

processing.

In this addressing mode, the address indicated by the stack pointer (8 bits) of data memory bank 0 is

specified.

This addressing mode can be used for register save/restoration operation using the PUSH or POP

instruction as well as save/restoration operation in interrupt and subroutine processing.

Examples 1. A register is saved and restored in subroutine processing.

SUB:

PUSH

; Save MBS and RBS

POP

RET

2. The contents of the HL register pair are transferred to the DE register pair.

PUSH

POP

; DE <– HL

3. A branch is made to the address indicated by the [XABC] register.

PUSH

RET

; Branch to address XABC

µPD750008 USER'S MANUAL

3.2 GENERAL REGISTER BANK CONFIGURATION

The µPD750008 contains four register banks, each consisting of eight general registers: X, A, B, C, D,

E, H, and L. These registers are mapped to addresses 00H to 1FH in memory bank 0 of the data memory

(see Figure 3-5). To specify a general register bank, a register bank enable flag (RBE) and a register bank

select register (RBS) are contained. The RBS is a register used to select a register bank, and the RBE is

a flag used to determine whether a register bank selected using the RBS is to be enabled. The register bank

(RB) enabled at instruction execution is determined as

RB = RBE·RBS

Table 3-2. Register Bank to Be Selected with the RBE and RBS

RBS

RBE

Bank 0 is always selected.

Bank 0 is selected.

Bank 1 is selected.

Bank 2 is selected.

Bank 3 is selected.

Always 0

Remark x: Don’t care

The contents of the RBE are automatically saved or restored at the beginning or end of subroutine

processing, so that the RBE can be freely modified during subroutine processing. In interrupt processing,

the RBE is automatically saved or restored, and when interrupt processing is started, the contents of the RBE

can be specified for the interrupt processing by setting the interrupt vector table. Therefore, as indicated in

Table 3-3, by selecting a register bank depending on whether the processing is normal or interrupt, the general

be saved and restored for the level-two interrupt processing, thus speeding up interrupt processing.

Table 3-3. Recommended Use of Register Banks with Normal Routines and Interrupt Routines

Normal processing

Use register banks 2 and 3 with RBE = 1.

Use register bank 0 with RBE = 0.

Level-one interrupt processing

Level-two interrupt processing

Use register bank 1 with RBE = 1.

(In this case, the RBS needs to be saved and restored.)

Multiple (triple or more) interrupt processing

Save and restore the registers with PUSH or POP.

CHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAP

Figure 3-4. Example of Register Bank Selection

SET1 RBE

SEL RB2

<Level-one interrupt> <Level-two interrupt> <Level-three interrupt>

; RBE = 0 in the

vector table

; RBE = 0 in the

vector table

; RBE = 1 in the

vector table

PUSH BS

SEL RB1

PUSH rp

RB = 2

RB = 0

RB = 1

RB = 0

RETI

POP rp

RETI

POP BS

RETI

The setting of the RBS can be modified for subroutine processing or interrupt processing by saving or

restoring the RBS with the PUSH or POP instruction.

The RBE is set using the SET1 or CLR1 instruction. The RBS is set using the SEL instruction.

Example

SET1

CLR1

SEL

RBE ; RBE <– 1

RBE ; RBE <– 0

RB0 ; RBS <– 0

RB3 ; RBS <– 3

SEL

The general register area of the µPD750008 can be used not only on a 4-bit basis, but also on an 8-bit

basis with register pairs. This enables users to perform transfers, arithmetic/logical operations, comparisons,

and increments and decrements at a speed comparable to that of an 8-bit microcomputer, and thereby enables

to program using mainly general registers.

(1) When used as a 4-bit register

When the general register area is used on a 4-bit basis, eight general registers, the X, A, B, C, D, E, H,

and L registers, are available in the register bank specified with RB = RBE·RBS as shown in Figure 3-

5. The A register functions as a 4-bit accumulator which performs transfers, arithmetic/logical operations,

andcomparisons. Theothergeneralregistersperformtransfers, comparisons, andincrements/decrements

with the accumulator.

µPD750008 USER'S MANUAL

(2) When used as an 8-bit register

When the general register area is used on an 8-bit basis, the register pairs in the register bank specified

by RBE·RBS can be specified as XA, BC, DE, and HL as shown in Figure 3-6, and the register pairs in

the register bank that has the inverted value of bit 0 of the register bank (RB) can be specified as XA’,

BC’, DE’, and HL’, thus providing up to eight 8-bit registers. The XA register pair functions as an 8-bit

accumulator which performs transfers, arithmetic/logical operations, comparisons, and increments/

decrements of 8-bit data. The other register pairs perform transfers, arithmetic/logical operations,

comparisons, and increments/decrements with the accumulator. The HL register pair functions mainly

as a data pointer, and the DE and DL register pairs function as an auxiliary data pointer.

Examples 1.

INCS

ADDS

SUBC

MOV

; HL <– HL + 1, skip at HL = 00H

; XA <– XA + BC, skip at carry

; DE’ <– DE’ – XA – CY

; XA <– XA’

XA,BC

DE’,XA

XA,XA’

XA,@PCDE

XA, BC

MOVT

SKE

; XA <– (PC

+ DE) ROM, reference table

12-8

; Skip if XA = BC

2. The value of the count register (T0) for timer/event counter 0 is tested until it becomes

greater than the value of the BC’ register pair.

CLR1

MOV

SUBS

MBE

XA,T0

XA,BC’

YES

NO:

; Read count register

; XA • BC?

; YES

; NO

CHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAP

Figure 3-5. General Register Configuration (4-bit Processing)

01H

03H

05H

07H

09H

0BH

0DH

0FH

11H

13H

15H

17H

19H

1BH

1DH

1FH

00H

02H

04H

06H

08H

0AH

0CH

0EH

10H

12H

14H

16H

18H

1AH

1CH

1EH

(RBE·RBS = 0)

(RBE·RBS = 1)

(RBE·RBS = 2)

(RBE·RBS = 3)

µPD750008 USER'S MANUAL

Figure 3-6. General Register Configuration (8-bit Processing)

XA’

HL’

DE’

BC’

00H

02H

04H

06H

08H

0AH

0CH

0EH

00H

02H

04H

06H

08H

0AH

0CH

0EH

XA’

HL’

DE’

BC’

When RBE·RBS

= 0

When RBE·RBS

= 1

XA’

HL’

DE’

BC’

10H

12H

14H

16H

18H

1AH

1CH

1EH

10H

12H

14H

16H

18H

1AH

1CH

1EH

XA’

HL’

DE’

BC’

When RBE·RBS

= 2

When RBE·RBS

= 3

CHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAP

3.3 MEMORY-MAPPED I/O

The µPD750008 employs memory-mapped I/O, which maps peripheral hardware such as timers and I/O

ports to addresses F80H to FFFH in data memory space as shown in Figure 3-2. This means that there is

no particular instruction to control peripheral hardware, but all peripheral hardware is controlled using memory

manipulation instructions. (Some mnemonics for hardware control are available to make programs readable.)

To manipulate peripheral hardware, the addressing modes listed in Table 3-4 can be used.

Table 3-4. Addressing Modes Applicable to Peripheral Hardware Operation

Applicable addressing mode

Applicable hardware

Bit

Direct addressing mode specifying mem.bit with

MBE = 0 (MBE = 1, MBS = 15)

All hardware

allowing bit manipulation

manipulation

Direct addressing mode specifying fmem.bit regardless of

MBE and MBS setting

IST1, IST0, MBE, RBE,

IExxx, IRQxxx, PORTn.x

Indirect addressing mode specifying pmem.@L regardless of

MBE and MBS setting

BSBn.x

PORTn.x

4-bit

manipulation

Direct addressing mode specifying mem with

MBE = 0 or (MBE = 1, MBS = 15)

All hardware allowing 4-bit

manipulation

(MBE = 1, MBS = 15)

8-bit

manipulation

Direct addressing mode specifying mem (even address) with

MBE = 0 or (MBE = 1, MBS = 15)

All hardware allowing 8-bit

manipulation

(with the L register containing an even number) with

MBE = 1 and MBS = 15

Figure 3-7 summarizes the I/O map of the µPD750008.

The items in the figure have the following meanings:

• Symbol : Name representing incorporated hardware, which can be coded in the operand field of an

instruction

• R/W

: Indicates whether the hardware allows read/write operation.

R/W : Both read and write operations possible

: Read only

: Write only

• Number of manipulatable bits:

Indicates the number of bits that can be processed at a time in hardware manipulation

–

: Bit manipulation is possible in units of the indicated number of bits (1, 4, or 8 bits).

: Particular bits can be manipulated. For these bits, see Remarks.

: Bit manipulation is impossible in units of the indicated number of bits (1, 4, or 8 bits).

• Bit manipulation addressing:

Bit manipulation addressing applicable in hardware bit manipulation

µPD750008 USER'S MANUAL

Figure 3-7. µPD750008 I/O Map (1/5)

Number of bits that can be

manipulated

Hardware name (symbol)

b2 b1

Bit

manipulation

addressing

Address

R/W

Remarks

1 bit

–

4 bits

8 bits

Bit 0 is fixed

to 0.

F80H

Stack pointer (SP)

–

Bank selection register (BS)

F82H

F83H

F84H

F85H

F86H

–

Note 1

Memory bank selection register (MBS)

Stack bank selection register (SBS)

R/W

–

mem.bit

Only bit 3 can

be manipulated.

Basic interval timer mode register (BTM)

Basic interval timer (BT)

WDTM^{Note 2}

–

F8BH

F98H

–

mem.bit

Only bit 3 can

be tested.

–

mem.bit

–

(R)

–

Clock mode register (WM)

R/W

Notes 1. Can be manipulated separately as the RBS and MBS in 4-bit units.

Can also be manipulated as the BS in 8-bit units.

Use SEL MBn and SEL RBn instructions to write data to MBS and RBS respectively.

2. WDTM: Watchdog timer enable flag (W); cannot be cleared by an instruction.

CHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAP

Figure 3-7. µPD750008 I/O Map (2/5)

Number of bits that can be

manipulated

Hardware name (symbol)

b2 b1

Bit

manipulation

addressing

Address

FA0H

R/W

Remarks

1 bit

4 bits

8 bits

Bit write manipu-

lation is enabled

only for bit 3.

–

mem.bit

(W)

–

Timer/event counter mode register (TM0)

(R/W)

–

FA2H

FA4H

TOE0^{Note 1}

mem.bit

Timer/event counter count register (T0)

–

FA6H

FA8H

Timer/event counter modulo register (TMOD0)

Timer counter mode register (TM1)

R/W

–

Bit write manipu-

lation is enabled

only for bit 3.

mem.bit

(W)

–

(R/W)

–

FAAH

FACH

TOE1^{Note 2}

mem.bit

Timer counter count register (T1)

–

FAEH

Timer counter modulo register (TMOD1)

R/W

Notes 1. TOE0: Timer/event counter output enable flag (W)

2. TOE1: Timer counter output enable flag (W)

µPD750008 USER'S MANUAL

Figure 3-7. µPD750008 I/O Map (3/5)

Number of bits that can be

manipulated

Hardware name (symbol)

Bit

manipulation

addressing

Address

R/W

Remarks

1 bit

4 bits

8 bits

(R)

IST1

IST0

MBE

RBE

Manipulation in

8-bit units is

enabled only

for reading.

FB0H

(R/W)

–

(R/W)

–

Program status word (PSW)

CY SK2 SK1

SK0

fmem.bit

Note 1

Note 2

FB2H

FB3H

FB4H

FB5H

FB6H

FB7H

FB8H

FBAH

Interrupt priority select register (IPS)

Processor clock control register (PCC)

R/W

–

INT0 edge detection mode register (IM0)

INT1 edge detection mode register (IM1)

INT2 edge detection mode register (IM2)

System clock control register (SCC)

Bits 3, 2, and 1

are fixed to 0.

–

Bits 3 and 2 are

fixed to 0.

Bits 2 and 1 are

fixed to 0.

–

(R/W)

(R)

IE4

IET1

IE1

IRQ4

IRQT1

IRQ1

IEBT

IEW

IRQBT

IRQW

FBCH

IET0

IRQT0

R/W

fmem.bit

–

FBDH

FBEH

FBFH

IECSI

IE0

IRQCSI

IRQ0

R/W

IE2

IRQ2

FC0H

FC1H

FC2H

FC3H

FCFH

Bit sequential buffer 0 (BSB0)

Bit sequential buffer 1 (BSB1)

Bit sequential buffer 2 (BSB2)

Bit sequential buffer 3 (BSB3)

Sub-oscillator control register (SOS)

R/W

mem.bit

pmem.@L

–

Remarks 1. IExxx : Interrupt enable flag

2. IRQxxx : Interrupt request flag

Notes 1. Only bit 3 can be manipulated by an EI/DI instruction.

2. Bits 3 and 2 can be manipulated bit by bit by a STOP/HALT instruction.

CHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAP

Figure 3-7. µPD750008 I/O Map (4/5)

Number of bits that can be

manipulated

Hardware name (symbol)

b2 b1

Clock output mode register (CLOM)

Bit

manipulation

addressing

Address

R/W

Remarks

1 bit

–

4 bits

8 bits

–

FD0H

FDCH

–

Pull-up resistor specification register group A

(POGA)

–

FDEH

Pull-up resistor specification register group B

(POGB)

R/W

–

FE0H

FE2H

FE4H

FE6H

FE8H

FECH

FEEH

–

Serial operation mode register (CSIM)

Note

R/W

mem.bit

CSIE

COI

WUP

(R) (W)

Whether this

location is read-

or write-

accessible de-

pends on the bit.

CMDD

RELD

CMDT

RELT

ACKT

SBI control register (SBIC)

BSYE ACKD ACKE

–

mem.bit

Serial I/O shift register (SIO)

Slave address register (SVA)

–

PM33

PM32

PM31

PM30

Port mode register group A (PMGA)

PM63

–

PM62

PM2

PM61

–

PM60

–

Port mode register group B (PMGB)

PM7

–

PM5

–

PM4

PM8

Port mode register group C (PMGC)

–

Note Whether a bit can be read or written depends on the bit.

µPD750008 USER'S MANUAL

Figure 3-7. µPD750008 I/O Map (5/5)

Number of bits that can be

manipulated

Hardware name (symbol)

Bit

manipulation

addressing

Address

R/W

Remarks

1 bit

4 bits

8 bits

–

SCKP

Note 1

FF0H

FF1H

Port 0 (PORT0)

Port 1 (PORT1)

Port 2 (PORT2)

Port 3 (PORT3)

Port 4 (PORT4)

Port 5 (PORT5)

R/W

(R) (R/W) (R)

FF2H

R/W

–

FF3H

fmem.bit

pmem.@L

FF4H

FF5H

KR3

KR2

KR1

KR5

KR0

KR4

FF6H^{Note 2}

FF7H^{Note 2}

FF8H

Port 6 (PORT6)

KR7

KR6

Port 7 (PORT7)

–

Port 8 (PORT8)

Notes 1. Bit 1 can be read or written only in serial operation enable mode. It can be read when four-bit

manipulation is performed.

2. KR0 to KR7 can be read (R) bit by bit. When inputting 4 bits at a time, specify PORT6 or PORT7.

CHAPTER 4 INTERNAL CPU FUNCTIONS

4.1 Mk I MODE/Mk II MODE SWITCH FUNCTIONS

4.1.1 Differences between Mk I Mode and Mk II Mode

The CPU of the µPD750008 subseries has two modes (Mk I mode and Mk II mode) and which mode is

used is selectable. Bit 3 of the stack bank selection register (SBS) determines the mode.

• Mk I mode: This mode has the upward compatibility with the µPD75008 subseries.

It can be used in the 75XL CPUs having a ROM of up to 16KB.

• Mk II mode: This mode is not compatible with the µPD75008 subseries.

It can be used in all 75XL CPUs, including those having a ROM of 16KB or more.

Table 4-1 shows the differences between Mk I mode and Mk II mode.

Table 4-1. Differences between Mk I Mode and Mk II Mode

Mk I mode

2 bytes

Mk II mode

3 bytes

Number of stack bytes in a subroutine instruction

BRA !addr1 instruction

Undefined operation

Normal operation

CALLA !addr1 instruction

CALL !addr instruction

CALLF !faddr instruction

3 machine cycles

2 machine cycles

4 machine cycles

3 machine cycles

Caution Mk II mode is for maintaining a software compatibility with products in the 75X series or

75XL series whose program memory is more than 24K bytes.

Therefore, Mk I mode is recommended for applications with a focus on the ROM efficiency

or speed.

µPD750008 USER'S MANUAL

4.1.2 Setting of the Stack Bank Selection Register (SBS)

The Mk I mode and Mk II mode are switched by stack bank selection register. Figure 4-1 shows the register

configuration.

The stack bank selection register is set with a 4-bit memory operation instruction. To use the CPU in Mk

Note

I mode, initialize the register to 10xxB

at the beginning of the program. To use the CPU in Mk II mode,

Note

initialize it to 00xxB

Figure 4-1. Stack Bank Selection Register Format

Address

F84H

Symbol

SBS

SBS3 SBS2 SBS1 SBS0

Stack area designation

Memory bank 0

Memory bank 1

Other settings are inhibited

Bit 2 must be set to 0

Mode switching designation

Mk II mode

Mk I mode

Note Specify the desired value in xx.

Caution The CPU operates in Mk I mode after the RESET signal is issued, because bit 3 of SBS

is set to 1. Set bit 3 of SBS to 0 (Mk II mode) to use the CPU in Mk II mode.

CHAPTER 4 INTERNAL CPU FUNCTIONS

4.2 PROGRAM COUNTER (PC):

12 BITS (µPD750004)

13 BITS (µPD750006 AND µPD750008)

14 BITS (µPD75P0016)

The program counter is a binary counter which retains the address data of the program memory. The

program counter consists of 12 bits in the µPD750004 (see Figure 4-2(a)), 13 bits in the µPD750006 and

µPD750008 (see Figure 4-2(b)), and 14 bits in the µPD75P0016 (see Figure 4-2(c)).

Figure 4-2. Program Counter Organization

(a) µPD750004

PC11 PC10 PC9

PC8

PC7 PC6

PC5

PC4

PC3

PC2 PC1 PC0

(b) µPD750006 and µPD750008

PC12 PC11 PC10 PC9

PC8 PC7

PC6

PC5

PC4

PC3 PC2 PC1

PC0

PC13 PC12 PC11 PC10 PC9 PC8

PC7

PC6

PC5

PC4 PC3 PC2

PC1 PC0

Usually, each time an instruction is executed, the program counter is automatically incremented according

to the number of bytes in the instruction.

When a branch instruction (BR, BRA, BRCB) is executed, immediate data indicating the branch destination

and the contents of a register pair are set in all or some bits of the program counter.

When a subroutine call instruction (CALL, CALLA, CALLF) is executed, or a vectored interrupt occurs, the

current contents of the program counter (already incremented return address for fetching the next instruction)

are saved in the stack memory (data memory indicated by the stack pointer), then the jump destination address

is loaded.

When a return instruction (RET, RETS, RETI) is executed, the contents of the stack memory are set in the

program counter.

When the RESET signal is issued, the program counter is initialized to the contents of the program memory

at addresses 000H and 001H. The program can be started from any address according to the contents.

µPD750004 :

PC -PC <– (000H)

, PC -PC <– (001H)

3-0

7-0

µPD750006 and µPD750008 :

PC -PC <– (000H)

, PC -PC <– (001H)

4-0

µPD75P0016 :

PC -PC <– (000H)

, PC -PC <– (001H)

5-0

µPD750008 USER'S MANUAL

4.3 PROGRAM MEMORY (ROM):

4096 WORDS x 8 BITS (µPD750004: MASKED ROM)

6144 WORDS x 8 BITS (µPD750006: MASKED ROM)

8192 WORDS x 8 BITS (µPD750008: MASKED ROM)

16384 WORDS x 8 BITS (µPD75P0016: ONE-TIME PROM)

The program memory is used for storing programs, an interrupt vector table, GETI instruction reference

table, table data, and so forth. The µPD750004, µPD750006, and µPD750008 are provided with a mask-

programmable ROM as the program memory, and the µPD75P0016 is provided with a one-time PROM.

Figures 4-3 to 4-6 show the program memory maps.

Program memory is addressed by the program counter. Table data can be referenced using the table

reference instruction (MOVT).

Figures 4-3 to 4-6 also show the allowable branch address ranges for the branch instructions and subroutine

call instructions. The relative branch instruction (BR $addr) allows a branch to addresses (contents of the

PC less 15 to one, or plus two to 16) regardless of block.

The program memory is located at following addresses.

• 0000H to 0FFFH: µPD750004

• 0000H to 17FFH: µPD750006

• 0000H to 1FFFH: µPD750008

• 0000H to 3FFFH: µPD75P0016

The following addresses are assigned to special functions. All areas excluding 0000H and 0001H can be

used as normal program memory.

• 0000H to 0001H

Vector address table for holding the RBE and MBE values and program start address when a RESET

signal is issued (allowing a reset start at an arbitrary address)

• 0002H to 000DH

Vector address table for holding the RBE and MBE values and program start address for each vectored

interrupt (allowing interrupt processing to be started at an arbitrary address)

• 0020H to 007FH

Note

Table area referenced by the GETI instruction

Note The GETI instruction can represent an arbitrary two-byte or three-byte instruction or two one-byte

instructions in one byte and is used to reduce the number of program bytes. (SeeSection 11.1.1.)

CHAPTER 4 INTERNAL CPU FUNCTIONS

Figure 4-3. Program Memory Map (in µPD750004)

0000H

0002H

0004H

0006H

0008H

000AH

000CH

MBE RBE

Internal reset start address (high-order 6 bits)

Internal reset start address (low-order 8 bits)

INTBT/INT4 start address (high-order 6 bits)

INTBT/INT4 start address (low-order 8 bits)

Entry

address

specified

in CALLF

!faddr

instruc-

tion

INT0 start address

INT1 start address

INTCSI start address

INTT0 start address

INTT1 start address

(high-order 6 bits)

(low-order 8 bits)

(high-order 6 bits)

(low-order 8 bits)

(high-order 6 bits)

(low-order 8 bits)

(high-order 6 bits)

(low-order 8 bits)

(high-order 6 bits)

(low-order 8 bits)

Branch

address

specified

in BRCB

!caddr

instruc-

tion

Branch address

specified in

BR !addr, BR BCDE,

BR BCXA, BRA

!addr1^Note, CALL

!addr, or CALLA

!addr1^Note

Branch/call

address by

GETI

0020H

GETI instruction reference table

Relative

branch

address

007FH

0080H

specified in

BR $addr

instruction

(–15 to –1,

+2 to +16)

07FFH

0800H

0FFFH

Note Can be used only in the MkII mode.

Remark In addition to the above, the BR PCDE and BR PCXA instructions can cause a branch to an

address with only the 8 low-order bits of the PC changed.

µPD750008 USER'S MANUAL

Figure 4-4. Program Memory Map (in µPD750006)

0000H

0002H

0004H

0006H

0008H

000AH

000CH

MBE RBE

Internal reset start address (high-order 6 bits)

Internal reset start address (low-order 8 bits)

INTBT/INT4 start address (high-order 6 bits)

INTBT/INT4 start address (low-order 8 bits)

Entry

address

specified

in CALLF

!faddr

instruc-

tion

INT0 start address

INT1 start address

INTCSI start address

INTT0 start address

INTT1 start address

(high-order 6 bits)

(low-order 8 bits)

(high-order 6 bits)

(low-order 8 bits)

(high-order 6 bits)

(low-order 8 bits)

(high-order 6 bits)

(low-order 8 bits)

(high-order 6 bits)

(low-order 8 bits)

Branch

address

specified

in BRCB

!caddr

instruc-

tion

Branch address

specified in

BR !addr,

BR BCDE,

BR BCXA,

BRA !addr1^Note

CALL !addr,

or CALLA !addr1^Note

Branch/call

address by

GETI

0020H

GETI instruction reference table

007FH

0080H

Relative

branch

address

specified in

BR $addr

instruction

(–15 to –1,

+2 to +16)

07FFH

0800H

0FFFH

1000H

Branch address

specified in BRCB

!caddr instruction

17FFH

Note Can be used only in the MkII mode.

Remark In addition to the above, the BR PCDE and BR PCXA instructions can cause a branch to an

address with only the 8 low-order bits of the PC changed.

CHAPTER 4 INTERNAL CPU FUNCTIONS

Figure 4-5. Program Memory Map (in µPD750008)

0000H

0002H

0004H

0006H

0008H

000AH

000CH

MBE RBE

Internal reset start address (high-order 6 bits)

Internal reset start address (low-order 8 bits)

INTBT/INT4 start address (high-order 6 bits)

INTBT/INT4 start address (low-order 8 bits)

Entry

address

specified

in CALLF

!faddr

instruc-

tion

INT0 start address

INT1 start address

INTCSI start address

INTT0 start address

INTT1 start address

(high-order 6 bits)

(low-order 8 bits)

(high-order 6 bits)

(low-order 8 bits)

(high-order 6 bits)

(low-order 8 bits)

(high-order 6 bits)

(low-order 8 bits)

(high-order 6 bits)

(low-order 8 bits)

Branch

address

specified

in BRCB

!caddr

instruc-

tion

Branch address

specified in

BR !addr,

BR BCDE,

BR BCXA,

BRA !addr1^Note

CALL !addr

or CALLA !addr1^Note

Branch/call

address by

GETI

0020H

GETI instruction reference table

007FH

0080H

Relative

branch

address

specified in

BR $addr

instruction

(–15 to –1,

+2 to +16)

07FFH

0800H

0FFFH

1000H

Branch address

specified in BRCB

!caddr instruction

1FFFH

Note Can be used only in the MkII mode.

Remark In addition to the above, the BR PCDE and BR PCXA instructions can cause a branch to an

address with only the 8 low-order bits of the PC changed.

µPD750008 USER'S MANUAL

Figure 4-6. Program Memory Map (in µPD75P0016)

0000H

0002H

0004H

0006H

0008H

000AH

000CH

MBE RBE

Internal reset start address (high-order 6 bits)

Internal reset start address (low-order 8 bits)

INTBT/INT4 start address (high-order 6 bits)

INTBT/INT4 start address (low-order 8 bits)

Entry

address

specified

in CALLF

!faddr

instruc-

tion

INT0 start address

INT1 start address

INTCSI start address

INTT0 start address

INTT1 start address

(high-order 6 bits)

(low-order 8 bits)

(high-order 6 bits)

(low-order 8 bits)

(high-order 6 bits)

(low-order 8 bits)

(high-order 6 bits)

(low-order 8 bits)

(high-order 6 bits)

(low-order 8 bits)

Branch

address

specified

in BRCB

!caddr

instruc-

tion

Branch address

specified in

BR !addr,

BR BCDE

BR BCXA,

BRA !addr1^Note

CALL !addr,

or CALLA !addr1^Note

Branch/call

address by

GETI

0020H

GETI instruction reference table

007FH

0080H

Relative

branch

address

specified in

BR $addr

instruction

(–15 to –1,

+2 to +16)

07FFH

0800H

0FFFH

1000H

Branch address

specified in BRCB

!caddr instruction

1FFFH

Branch address

specified in BRCB

!caddr instruction

2FFFH

3000H

Branch address

specified in BRCB

!caddr instruction

3FFFH

Note Can be used only in the MkII mode.

Remark In addition to the above, the BR PCDE and BR PCXA instructions can cause a branch to an

address with only the 8 low-order bits of the PC changed.

CHAPTER 4 INTERNAL CPU FUNCTIONS

4.4 DATA MEMORY (RAM): 512 WORDS x 4 BITS

The data memory consists of a data area and peripheral hardware area as shown in Figure 4-7.

The data memory consists of the following memory banks with each bank made of 256 words x 4 bits.

• Memory banks 0 and 1 (data area)

• Memory bank 15 (peripheral hardware area)

4.4.1 Data Memory Configuration

(1) Data area

The data area consists of a static RAM, and is used for storing program data and as stack memory for

subroutine and interrupt execution. Battery backup enables the memory to hold data for a long time even

if the CPU is stopped in the standby mode. The data area can be manipulated with memory manipulation

instructions.

The static RAM is mapped to memory banks 0 and 1, with each made up of 256 x 4 bits. Bank 0 is used

Note

as a data area, but can also be used as a general register area (000H to 01FH) and stack area

to 1FFH).

(000H

Whole locations in memory banks 0, 1, 2, and 3 (000H to 3FFH) can be used as a stack area.

The static RAM has a configuration of four bits per address. However, the memory can be manipulated

in 8 bit units using an 8-bit memory manipulation instruction, and in bit units using a bit manipulation

instruction. Note that an even address must be specified in an 8-bit manipulation instruction.

Note Memory bank 0 or 1 can be selected as the stack area.

• General register area

The general register area can be manipulated with either general register manipulation instructions or

memory manipulation instructions. Up to eight 4-bit registers are available. Of the 8 general registers,

registers not used by the program can be used as a data area or stack area. (See Section 4.5.)

• Stack memory area

The stack memory area is set by the instruction. This area can be used as a save area for subroutine

or interrupt execution. (See Section 4.7.)

(2) Peripheral hardware area

The peripheral hardware area is mapped at addresses F80H to FFFH of memory bank 15.

Memory manipulation instructions are used to manipulate the peripheral hardware area as well as the static

RAM area. Note that, however, the number of bits to be manipulated at a time varies according to the

individual addresses. Addresses to which no peripheral hardware is assigned cannot be accessed since

such address locations contain no data memory. (See Figure 3-7.)

µPD750008 USER'S MANUAL

4.4.2 Specification of a Data Memory Bank

If the memory bank enable flag (MBE) enables bank specification (MBE = 1), a memory bank is specified

with the 4-bit memory bank select register (MBS = 0, 1, 15). If the MBE disables bank specification (MBE

= 0), memory bank 0 or 15 is automatically selected according to the addressing mode. Locations in a bank

is addressed by 8-bit immediate data or a register pair.

For details on the selection of a memory bank and addressing, see Section 3.1.

For how to use the particular data memory areas, see the following sections and chapter.

• General register area

• Stack memory area

: Section 4.5

: Section 4.7

• Peripheral hardware area: Chapter 5

Figure 4-7. Data Memory Map

Data memory

(32 x 4)

Memory bank

000H

Area for

general

01FH

020H

256 x 4

(224 x 4)

Stack

area^Note

Data area

static RAM

(512 x 4)

0FFH

100H

256 x 4

1FFH

F80H

Not contained

Peripheral

hardware area

128 x 4

FFFH

Note Memory bank 0 or 1 can be selected as the stack area.

CHAPTER 4 INTERNAL CPU FUNCTIONS

Data memory is undefined when it is reset. For this reason, it is to be initialized to zero (RAM clear) usually

at the start of a program. Remember to perform this initialization. Otherwise, unexpected bugs may occur.

Example The following program clears data at addresses 000H to 1FFH in RAM.

SET1

MBE

SEL

MB0

MOV

XA,#00H

HL,#04H

@HL,A

MOV

Note

RAMC0: MOV

; Clear 04H to FFH

; L <– L + 1

INCS

RAMC0

INCS

; H <– H + 1

SEL

RAMC0

MB1

RAMC1: MOV

INCS

@HL,A

; Clear 100H to 1FFH

; L <– L + 1

RAMC1

INCS

; H <– H + 1

Note Data memory locations at 000H to 003H are allocated to general registers XA and HL, so these are

not cleared.

µPD750008 USER'S MANUAL

4.5 GENERAL REGISTER: 8 x 4 BITS x 4 BANKS

The general registers are mapped to particular addresses in data memory. Four banks of registers are

provided, with each bank consisting of eight 4-bit registers (B, C, D, E, H, L, X, and A).

The register bank (RB) to be enabled at the time of instruction execution is determined by:

RB = RBE·RBS: (RBS = 0 to 3)

Each general register allows 4-bit manipulation. In addition, BC, DE, HL, or XA serves as a register pair

for 8-bit manipulation. DL also makes a register pair as well as DE and HL. These three register pairs can

be used as data pointers.

In 8-bit manipulation, the register pairs in the register banks (0 <—> 1, 2 <—> 3) that have the inverted

value of bit 0 of the register bank (RB) address can be specified as BC’, DE’, HL’, and XA’ in addition to the

A general register area can be addressed and accessed as normal RAM, regardless of whether it is used

as a register.

Figure 4-8. General Register Format

Data memory

Address

000H

001H

002H

003H

004H

005H

006H

007H

008H

A register

X register

L register

H register

E register

D register

C register

B register

Same as bank 0

00FH

010H

017H

018H

01FH

CHAPTER 4 INTERNAL CPU FUNCTIONS

Figure 4-9. Register Pair Format

One bank

4.6 ACCUMULATOR

In the µPD750008, the A register and XA register pair function as accumulators. The A register is mainly

used for 4-bit data processing instructions, and the XA register pair is mainly used for 8-bit data processing

instructions.

For a bit manipulation instruction, the carry flag (CY) functions as a bit accumulator.

Figure 4-10. Accumulator

Bit accumulator

4-bit accumulator

8-bit accumulator

µPD750008 USER'S MANUAL

4.7 STACK POINTER (SP) AND STACK BANK SELECT REGISTER (SBS)

The µPD750008 uses static RAM as stack memory (LIFO scheme), and the 8-bit register holding the start

address of the stack area is the stack pointer (SP).

The stack area is located at addresses 000H to 1FFH in memory banks 0 and 1. One memory bank is

selected according to the value of the 2-bit SBS. (See Table 4-2.)

Table 4-2. Stack Area to Be Selected by the SBS

SBS

Stack area

SBS1

SBS0

Memory bank 0

Memory bank 1

Not to be set

Other than above

The SP is decremented before a write (save) operation to stack memory, and is incremented after a read

(restoration) operation from stack memory.

Figures 4-12 to 4-15 show data saved to and restored from stack memory in these stack operations.

To place the stack area at a given location, the SP can be initialized with an 8-bit memory manipulation

instruction, and the SBS can be initialized with a 4-bit memory manipulation instruction. Both can be read

from as well.

When the SP is initialized to 00H, a stack operation starts at the high-order address (nFFH) of memory

bank (n) specified with the SBS.

A stack area must be within the memory bank specified with the SBS. If a stack operation exceeds address

n00H, the operation returns to address nFFH in the same bank. Linear stacking beyond memory bank

boundaries is enabled only by resetting the SBS.

A RESET signal causes the contents of the SP to be undefined, and causes the contents of the SBS to

be 1000B. Remember to initialize the SP and SBS to a desired value at the start of a program.

CHAPTER 4 INTERNAL CPU FUNCTIONS

Figure 4-11. Format of Stack Pointer and Stack Bank Select Register

Address

F80H

Symbol

SP7

SP6

SP5

SP4

SP3

SP2

SP1

Note

SBS3

F84H

SBS1

SBS

SBS0

000H

Memory bank 0

Memory bank 1

SBS

0FFH

100H

1FFH

Note The Mk I mode and Mk II mode can be switched by bit 3 of SBS. The stack bank selection function

can be used in both Mk I mode and Mk II mode. (See Section 4.1 for details.)

Example SP initialization

Specify memory bank 1 as a stack area to start stack operation at address 1FFH.

SEL

MB15

; or CLR1 MBE

MOV

A,#1

SBS,A

XA,#00H

SP,XA

; Specify memory bank 1 as a stack area

; SP <– 00H

Figure 4-12. Data Saved to the Stack Memory (Mk I Mode)

PUSH instruction

CALL or CALLF instruction

Interrupt

Stack

SP – 4

SP – 3

SP – 2

SP – 1

PC11 - PC8

SP – 6

SP – 5

SP – 4

SP – 3

PC11 - PC8

Note

MBE RBE PC13 PC12

SP – 2

SP – 1

Lower bits of pair register

Upper bits of pair register

PC3 - PC0

PC7 - PC4

SP – 2 IST1 IST0 MBE RBE

PSW

SP – 1

CY SK2 SK1 SK0

Note PC12 and PC13 are 0 in the µPD750004. PC13 is 0 in the µPD750006 and µPD750008.

µPD750008 USER'S MANUAL

Figure 4-13. Data Restored from the Stack Memory (Mk I Mode)

POP instruction

Stack

RET or RETS instruction

RETI instruction

Stack

Lower bits of pair register

Upper bits of pair register

PC11 - PC8

Note

SP + 1

SP + 2

SP + 1

SP + 2

SP + 3

SP + 4

SP + 1

SP + 2

SP + 3

MBE RBE PC13 PC12

PC3 - PC0

PC7 - PC4

SP + 4 IST1 IST0 MBE RBE

PSW

SP + 5

CY SK2 SK1 SK0

SP + 6

Note PC12 and PC13 are 0 in the µPD750004. PC13 is 0 in the µPD750006 and µPD750008.

Figure 4-14. Data Saved to the Stack Memory (Mk II Mode)

PUSH instruction

Stack

CALL, CALLA, or CALLF instruction

Stack

Interrupt

Stack

–

PC11 - PC8

–

PC11 - PC8

Note 1

PC13 PC12

–

Lower bits of pair register

Upper bits of pair register

PC3 - PC0

PC7 - PC4

PC3 - PC0

PC7 - PC4

MBE RBE

IST1 IST0 MBE RBE

Note 2

PSW

CY SK2 SK1 SK0

Notes 1. PC12 and PC13 are 0 in the µPD750004. PC13 is 0 in the µPD750006 and µPD750008.

2. PSW bits other than MBE and RBE are not saved or restored.

Remark * indicates an undefined bit.

CHAPTER 4 INTERNAL CPU FUNCTIONS

Figure 4-15. Data Restored from the Stack Memory (Mk II Mode)

POP instruction

Stack

RET or RETS instruction

Stack

RETI instruction

Stack

Lower bits of pair register

PC11 - PC8

Note 1

SP + 1 Upper bits of pair register

SP + 2

SP + 1

SP + 2

SP + 3

SP + 4

SP + 5

SP + 6

PC13 PC12

SP + 1

SP + 2

SP + 3

SP + 4

SP + 5

SP + 6

PC13 PC12

PC3 - PC0

PC7 - PC4

PC3 - PC0

PC7 - PC4

MBE RBE

IST1 IST0 MBE RBE

Note 2

PSW

CY SK2 SK1 SK0

Notes 1. PC12 and PC13 are 0 in the µPD750004. PC13 is 0 in the µPD750006 and µPD750008.

2. PSW bits other than MBE and RBE are not saved or restored.

Remark * indicates an undefined bit.

µPD750008 USER'S MANUAL

4.8 PROGRAM STATUS WORD (PSW): 8 BITS

The program status word (PSW) consists of various flags closely associated with processor operations.

The PSW is mapped to addresses FB0H and FB1H in data memory space. Four bits at address FB0H

can be manipulated with a memory manipulation instruction.

Figure 4-16. Program Status Word Format

Address

FB0H

FB1H

FB0H

Symbol

PSW

SK2

SK1

SK0

IST1

IST0

MBE

RBE

Cannot be manipulated

Can be manipulated

by an instruction

specifically provided

for controlling this flag

Table 4-3. PSW Flags Saved/Restored in Stack Operation

Saved/restored flag

Save

When a CALL, CALLA, or CALLF instruction is executed

When a hardware interrupt occurs

MBE and RBE are saved.

All PSW bits are saved.

MBE and RBE are restored.

All PSW bits are restored.

Restore

When a RET or RETS instruction is executed

When a RETI is executed

(1) Carry flag (CY)

The carry flag is a 1-bit flag used to store information about an overflow or underflow that occurs when

an arithmetic operation with a carry (ADDC, SUBC) is executed.

The carry flag functions as a bit accumulator, and therefore can be used to store the result of a Boolean

algebra operation performed on the CY and a bit at a specified data memory bit address.

The carry flag is manipulated using special instructions, independently of the other PSW bits.

A RESET signal causes the carry flag to be undefined.

CHAPTER 4 INTERNAL CPU FUNCTIONS

Table 4-4. Carry Flag Manipulation Instructions

Instruction (mnemonic)

Carry flag operation/processing

Sets CY to 1.

Clears CY to 0.

Inverts the state of CY.

Skips if CY is 1.

Instruction dedicated to carry

flag manipulation

SET1

CLR1

NOT1

SKT

Bit transfer instruction

Bit Boolean instruction

MOV1

mem*.bit, CY

CY, mem*.bit

Transfers the state of CY to a specified bit.

Transfers the state of a specified bit to CY.

AND1

OR1

XOR1

CY, mem*.bit

ANDs, ORs, or XORs CY with a specified bit,

then sets the result in CY.

Interrupt handling

Interrupt execution

RETI

Saves CY and all other PSW bits to

stack memory in parallel.

Restores CY together with the other PSW bits

from stack memory in parallel.

Remark mem*.bit represents the following bit addressing:

• fmem.bit

• pmem.@L

• @H+mem.bit

Example Bit 3 at address 3FH is ANDed with P33, then the result is set in P50.

MOV

H,#3H

; Set the high-order 4 bits of the address in H register

; CY <– bit 3 at 3FH

MOV1

AND1

MOV1

CY,@H+0FH.3

CY,PORT3.3

PORT5.0,CY

; CY <– CY P33

; P50 <– CY

(2) Skip flags (SK2, SK1, SK0)

The skip flags are used to store skip status, and are automatically set or reset when the CPU executes

an instruction.

The user cannot directly manipulate these flags by specifying an operand.

(3) Interrupt status flag (IST1, IST0)

The interrupt status flag is a 2-bit flag used to store the status of processing being performed.

See Table 6-3 for details.

µPD750008 USER'S MANUAL

Table 4-5. Information Indicated by the Interrupt Status Flag

IST1

IST0

Status of processing

Status 0

Processing and interrupt control being performed

Normal program processing is being performed.

Any interrupts are acceptable.

Status 1

Status 2

A lower- or higher-priority interrupt is being serviced.

Higher-priority interrupts are acceptable.

A higher-priority interrupt is being serviced.

No interrupts are acceptable.

—

Not to be set

The interrupt priority control circuit (Figure 6-1) checks this flag to control multiple interrupts.

The contents of the IST1 and IST0 are saved as part of the PSW to stack memory if an interrupt is accepted,

then are automatically set to a one-step higher status. The RETI instruction restores the contents present

before an interrupt occurs.

The interrupt status flag can be manipulated using a memory manipulation instruction, and the status of

processing being performed can be changed by program control.

Caution The user must always disable interrupts with the DI instruction before manipulating this

flag, and must enable interrupts with the EI instruction after manipulating this flag.

(4) Memory bank enable flag (MBE)

The memory bank enable flag is a 1-bit flag used to specify the address information generation mode for

the high-order four bits of a 12-bit data memory address.

The MBE can be set or reset any time with a bit manipulation instruction, regardless of memory bank

setting.

When the MBE is set to 1, the data memory address space is expanded, allowing all data memory space

to be addressed.

When the MBE is reset to 0, the data memory address space is fixed, regardless of MBS setting. (See

Figure 3-2.)

A RESET signal automatically initializes the MBE by setting the MBE to the content of bit 7 at program

memory address 0.

In vectored interrupt processing, the MBE is automatically set to the content of bit 7 in the vector address

table for servicing the interrupt.

Usually, the MBE is set to 0 in interrupt processing, and static RAM in memory bank 0 is used.

(5) Register bank enable flag (RBE)

The register bank enable flag is a 1-bit flag used to determine whether to expand the general register bank

configuration.

The RBE can be set or reset any time with a bit manipulation instruction, regardless of memory bank

setting.

When the RBE is set to 1, a set of general registers can be selected from register banks 0 to 3, depending

on the setting of the register bank select register (RBS).

CHAPTER 4 INTERNAL CPU FUNCTIONS

When the RBE is reset to 0, register bank 0 is always selected as general registers, regardless of the setting

of the RBS.

A RESET signal automatically initializes the RBE by setting the RBE to the state of bit 6 at program

memory address 0.

When a vectored interrupt occurs, the RBE is automatically set to the state of bit 6 in the vector address

table for servicing the interrupt. Usually, the RBE is set to 0 in interrupt processing. Register bank 0 is

used for 4-bit processing, and register banks 0 and 1 are used for 8-bit processing.

4.9 BANK SELECT REGISTER (BS)

The bank select register (BS) consists of a register bank select register (RBS) and memory bank select

The RBS and MBS are set using the SEL RBn instruction and SEL MBn instruction, respectively.

The contents of the BS can be saved to or restored from a stack memory eight bits at a time by using the

PUSH BS/POP BS instruction.

Figure 4-17. Bank Select Register Format

Address

F82H

Symbol

F83H

F82H

MBS3 MBS2 MBS1 MBS0

RBS1 RBS0

(1) Memory bank select register (MBS)

The memory bank select register is a 4-bit register used to store the high-order four bits of a 12-bit data

memory address. The contents of this register specify a memory bank to be accessed. The µPD750008

allows memory banks 0, 1, and 15 only to be specified.

The MBS is set with the SEL MBn instruction (n = 0, 1, 15).

Figure 3-2 shows the range of addressing using MBE and MBS settings.

A RESET signal initializes the MBS to 0.

(2) Register bank select register (RBS)

The register bank select register specifies a register bank to be used as general registers; a register bank

can be selected from register banks 0 to 3.

The RBS is set by the SEL RBn instruction (n = 0 to 3).

A RESET signal initializes the RBS to 0.

µPD750008 USER'S MANUAL

Table 4-6. Register Bank to Be Selected with the RBE and RBS

RBS

RBE

Bank 0 is always selected.

Bank 0 is selected.

Bank 1 is selected.

Bank 2 is selected.

Bank 3 is selected.

Always 0

x: Don’t care

CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS

5.1 DIGITAL I/O PORTS

The µPD750008 employs the memory mapped I/O method. Thus, all input/output ports are mapped on

the data memory space.

Figure 5-1. Data Memory Addresses of Digital Ports

Address

FF0H

FF1H

FF2H

FF3H

FF4H

FF5H

FF6H

P03

P13

P23

P33

P43

P53

P02

P12

P22

P32

P42

P52

P01

P11

P21

P31

P41

P51

P00

P10

P20

P30

P40

P50

PORT 0

PORT 1

PORT 2

PORT 3

PORT 4

PORT 5

PORT 6

P63

P62

P61

P60

FF7H

FF8H

P73

–

P72

–

P71

P81

P70

P80

PORT 7

PORT 8

Remark Some I/O parts can be used as static RAM.

Input/output port manipulation instructions are as listed in Table 5-2. Ports 4 to 7 can be manipulated not

only in 4-bit units, but also in 8-bit or 1-bit units so that these ports can be controlled in various ways.

Example 1. To test the condition of P13 and output different values to ports 4 and 5 according to the test

result:

SKT

PORT1. 3 ; Skips if bit 3 of port 1 is 1

MOV XA, #18H ; XA <– 18H

MOV XA, #14H ; XA <– 14H

String-effect instructions

SEL

MB15

; Or CLR1 MBE

OUT PORT4, XA ; Port 5, 4 <– XA

2. SET1 PORT4. @L; Sets the bit(s) specified by the L register, in ports 4 to 7, to 1.

µPD750008 USER'S MANUAL

5.1.1 Types, Features, and Configurations of Digital I/O Ports

Table 5-1 lists the types of digital I/O ports.

Figures 5-2 to 5-6 show the configurations of the ports.

Table 5-1. Types and Features of Digital Ports

Port name

(symbol)

Function

4-bit I/O

Operation and feature

Remarks

Allows read and test at any timeregard

less of the operation modes of another

functions assigned to these pins.

PORT0

Also used as INT4, SCK, SO/SB0,

and SI/SB1.

PORT1

Also used as INT0 to INT2 and

TI0.

Note 1

Note 2

Allows input or output mode setting bit

by bit.

PORT3

PORT6

PORT2

4-bit I/O

Also used as MD0 to MD3

Also used as KR0 to KR3.

Ports 6 and 7 can be paired, allowing

data I/O in units of 8 bits. Allows input

or output mode setting in units of 4 bits.

Also used as PTO0, PTO1, PCL,

and BUZ.

PORT7

Also used as KR4 to KR7.

Note 1

PORT4

PORT5

4-bit I/O

Allows input or output mode setting in

Whether to use pull-up resistors

(N-ch open-drain; units of 4 bits. Ports 4 and 5 can be

can withstand

13V)

can be specified bit by bit with a

Note 3

paired, allowing data I/O in units of

8 bits.

mask option

PORT8

2-bit I/O

Allows input or output mode setting in

units of 2 bits.

Notes 1. Can directly drive the LED.

2. Only for the µPD75P0016.

3. The µPD75P0016 does not have a mask option and cannot be connected with a pull-up resistor.

P10 is also used as an external vectored interrupt input pin. This input is provided with a noise eliminator.

(See Section 6.3 for details.)

When the RESET signal is generated, output latches of ports 2 to 8 are cleared to 0 and the output buffer

is turned off so that these ports are in the input mode.

CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS

Figure 5-2. Configurations of Ports 0 and 1

Internal

SCK

SCK INT4

P01

output

latch

VDD

Pull-up

resistor

Selector

CSIM

P-ch

Bit 0 of

POGA

P00/INT4

P01/SCK

P02/SO/SB0

P03/SI/SB1

Input buffer

Output buffer which can

be switched to either

push-pull output or N-ch

open-drain output

N-ch

open drain

V^DD

Pull-up

resistor

P-ch

Bit 1 of

POGA

Φ or f^X/64

Input buffer

Noise

eliminator

P10/INT0

P11/INT1

P12/INT2

P13/TI0

Input buffer with hysteresis

TI0 INT2 INT1 INT0

µPD750008 USER'S MANUAL

Figure 5-3. Configurations of Ports 2 and 7

VDD

Pull-up

resistor

P-ch

Bit m of

POGA

Key interrupt^Note

PMm = 0

Input buffer

PMm = 1

Input buffer with

hysteresis^Note

Pm0

Pm1

Pm2

Pm3

Output

latch

Output buffer

PMm

Bits 2 and 7 of port mode

Note For port 7 only

CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS

Figure 5-4. Configurations of Ports 3n and 6n (n = 0 to 3)

Key interrupt^Note

Input buffer with

hysteresis^Note

V^DD

Pull-up

PMmn = 0

Input buffer

resistor

PMmn = 1

Bit m of

POGA

P-ch

Output latch

Output buffer

Pmn

PMmn

Corresponding bits of

m = 3, 6

port mode register group A

n = 0 to 3

Note For port 6n only

µPD750008 USER'S MANUAL

Figure 5-5. Configurations of Ports 4 and 5

VDD

Pull-up resistor

(Mask option)

Input buffer

PMm = 0

MPX

PMm = 1

Pm0

Pm1

Pm2

Pm3

Output

latch

N-ch open-drain

output buffer

PMm

Corresponding bits of port mode

CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS

Figure 5-6. Configuration of Port 8

VDD

Pull-up

resistor

P-ch

Bit 0 of

POGB

Input buffer

PM8 = 0

PM8 = 1

Output buffer

P80

P81

Ouput

latch

PM8

Corresponding bit of port

mode register group C

µPD750008 USER'S MANUAL

5.1.2 I/O Mode Setting

The I/O mode of each I/O port is set by the port mode register as shown in Figure 5-7. The I/O modes

of ports 3 and 6 can be set bit by bit by port mode register group A (PMGA). The I/O modes of ports 2, 4,

5, and 7 can be set in units of four bits by port mode register group B (PMGB). The I/O mode of port 8 can

be set in units of two bits by port mode register group C (PMGC).

Each port functions as an input port when the corresponding bit of the port mode register is set to 0, and

functions as an output port when the same corresponding bit is set to 1.

When the output mode is selected by the port mode register, the contents of the output latch appear on

the output pins, and so the contents of the output latch must be changed to a desired value before the output

mode is set.

An 8-bit memory manipulation instruction is used to set port mode register group A, B, or C.

A RESET signal clears all bits of each port mode register to 0. This means that the output buffers are set

off, and all ports are placed in the input mode.

Example P30, P31, P62, and P63 are used as input pins, and P32, P33, P60, and P61 are used as output

pins.

CLR1

MOV

MBE

; or SEL MB15

XA,#3CH

PMGA,XA

CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS

Figure 5-7. Formats of Port Mode Registers

Contents of specification

Input mode (Output buffer off)

Output mode (Output buffer on)

Port mode register group A

Address

Symbol

PMGA

FE8H

PM63 PM62 PM61 PM60 PM33 PM32 PM31 PM30

P30 I/O specification

P31 I/O specification

P32 I/O specification

P33 I/O specification

P60 I/O specification

P61 I/O specification

P62 I/O specification

P63 I/O specification

Port mode register group B

Address

Symbol

PMGB

FECH

PM7

—

PM5

PM4

—

PM2

—

Port 2 (P20 - P23) I/O specification

Port 4 (P40 - P43) I/O specification

Port 5 (P50 - P53) I/O specification

Port 7 (P70 - P73) I/O specification

Port mode register group C

Address

Symbol

PMGC

FEEH

—

PM8

Port 8 (P80, P81) I/O specification

µPD750008 USER'S MANUAL

5.1.3 Digital I/O Port Manipulation Instructions

All I/O ports contained in the µPD750008 are mapped to data memory space, so that all data memory

manipulation instructions can be used. Table 5-3 lists the instructions that are particularly useful for I/O pin

manipulation and their application ranges.

(1) Bit manipulation instructions

For digital I/O ports PORT0 to PORT8, specific address bit direct addressing (fmem.bit) and specific

address bit register indirect addressing (pmem.@L) can be used. This means that bit manipulation can

be freely performed for these ports regardless of MBE and MBS settings.

Example P50 is ORed with P41, then the result is output to P61.

SET1

AND1

OR1

SKT

; CY <– 1

CY,PORT5.0 ; CY <– CY P50

CY,PORT4.1 ; CY <– CY P41

CLRP

SET1

PORT6.1

; P61 <– 1

; P61 <– 0

CLRP :

CLR1

PORT6.1

(2) 4-bit manipulation instructions

All 4-bit memory manipulation instructions including the IN, OUT, MOV, XCH, ADDS, and INCS

instructions can be used. However, before these instructions can be executed, memory bank 15 must

be selected.

Examples 1. The contents of the accumulator are output to port 3.

SEL

MB15

; or CLR1 MBE

OUT

PORT3,A

2. The value of the accumulator is added to the data output on port 5, then the result is output.

SET1

SEL

MBE

MB15

MOV

HL,#PORT5

ADDS A,@HL

NOP

; A <– A+PORT5

; PORT5 <– A

MOV

@HL,A

3. Whether the data on port 4 is greater than the value of the accumulator is tested.

SET1

SEL

MBE

MB15

MOV

HL,#PORT4

SUBS A,@HL

BR NO

; A < PORT4

; NO

; YES

CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS

(3) 8-bit manipulation instructions

The MOV, XCH, and SKE instructions as well as the IN and OUT instructions can be used for ports 4 and

5 that allow 8-bit manipulation. As with 4-bit manipulation, memory bank 15 must be selected in advance.

Example The data contained in the BC register pair is output on the output port specified by 8-bit data

applied to ports 4 and 5.

SET1

SEL

MBE

MB15

XA,PORT4

HL,XA

; XA <– ports 5,4

; HL <– XA

MOV

XA,BC

@HL,XA

; XA <– BC

; Port (L) <– XA

µPD750008 USER'S MANUAL

Table 5-2. I/O Pin Manipulation Instructions

PORT

Instruction

Note 1

A, PORTn

XA, PORTn

Note 1

—

OUT PORTn, A

OUT PORTn, XA

SET1 PORTn.bit

SET1 PORTn.@L

CLR1 PORTn.bit

CLR1 PORTn.@L

SKT PORTn.bit

SKT PORTn.@L

SKF PORTn.bit

SKF PORTn.@L

MOV1 CY, PORTn.bit

Note 2

MOV1 CY, PORTn.@L

MOV1 PORTn.bit,CY

—

Note 2

MOV1 PORTn.@L,CY

AND1 CY, PORTn.bit

AND1 CY, PORTn.@L

OR1 CY, PORTn.bit

OR1 CY, PORTn.@L

XOR1 CY, PORTn.bit

XOR1 CY, PORTn.@L

Note 2

Notes 1. MBE = 0 or (MBE = 1, MBS = 15) must be set before execution.

2. The low-order two bits of an address and bit address are indirectly specified using the L register.

CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS

5.1.4 Digital I/O Port Operation

When a data memory manipulation instruction is executed for a digital I/O port, the operation of the port

and pins depends on the I/O mode setting (Table 5-3). This is because data taken in on the internal bus is

the data input from the pins in the input mode, or the output latch data in the output mode, as obvious from

the configurations of I/O ports.

(1) Operation when the input mode is set

Data from each pin is manipulated when a test instruction such as the SKT instruction ,a bit input instruction

such as MOV1,or an instruction for taking in port data on the internal bus in units of four or eight bits (such

as an IN, OUT, arithmetic/logical or comparison instruction) is executed.

When an instruction (the OUT or MOV instruction) is executed to transfer the contents of the accumulator

to a port in units of four or eight bits, the data of the accumulator is latched in the output latch, with the

output buffers kept off.

When the XCH instruction is executed, the data on each pin is loaded into the accumulator, and the data

in the accumulator is latched in the output latch, with the output buffers kept off.

When the INCS instruction is executed, the 4-bit data existing on the pins plus 1 is latched in the output

latch, with the output buffers kept off.

When an instruction such as the SET1, CLR1, or SKTCLR instruction is executed to rewrite a data memory

bit, the output latch data of the specified bit can be rewritten according to the instruction, but the states

of the other output latch bits are undefined.

(2) Operation when the output mode is set

When a test instruction or instruction for taking in port data on the internal bus in units of four or eight

bits is executed, output latch data is manipulated.

When an instruction is executed to transfer the contents of the accumulator in units of four or eight bits,

the output latch data is rewritten, and is output on the pins.

When the XCH instruction is executed, the output latch data is transferred to the accumulator. The

contents of the accumulator are latched in the output latches, and are output on the pins.

When the INCS instruction is executed, the contents of the output latch incremented by 1 are latched in

the output latch, and are output on the pins.

When a bit output instruction is executed, the specified bit of the output latch is rewritten, and is output

on the pin.

µPD750008 USER'S MANUAL

Table 5-3. Operations by I/O Port Manipulation Instructions

Port and pin operation

Instruction

Input mode

Pin data is tested.

Output mode

SKT

SKF

<1>

Output latch data is tested.

MOV1 CY, <1>

Pin data is transferred to CY.

Output latch data is transferred to CY.

AND1 CY, <1>

An operation is performed on pin data and

CY.

An operation is performed

on output latch data and CY.

OR1

CY, <1>

XOR1 CY, <1>

A,PORTn

XA,PORTn

Pin data is transferred to the accumulator.

Output latch data is transferred to the

accumulator.

MOV A,@HL

MOV XA,@HL

ADDS A,@HL

ADDC A,@HL

SUBS A,@HL

SUBC A,@HL

An operation is performed on pin data and

the accumulator.

An operation is performed

on output latch data and the accumulator.

AND

XOR

A,@HL

SKE

A,@HL

XA,@HL

Pin data is compared with the

accumulator.

Output latch data is com-

pared with the accumulator.

OUT

PORTn,A

Accumulator data is transferred to the

output latch and is output on the pins.

PORTn,XA output latch (with the output buffers kept

MOV @HL,A

MOV @HL,XA

off).

XCH

A,PORTn

Pin data is transferred to the accumulator,

Data is exchanged between the output

latch and accumulator.

XA,PORTn and accumulator data is transferred to the

A,@HL

XA,@HL

output latch (with the output buffers kept

off).

INCS PORTn

INCS @HL

Pin data incremented by 1 is latched in

the output latch.

Output latch data is incremented by 1.

SET1 <1>

CLR1 <1>

MOV1 <1> ,CY

SKTCLR <1>

The output latch data of a specified bit is

rewritten, but the output latch data of the

other bits is undefined.

The output pin state is modified according

to the instruction.

<1> : Represents an addressing mode PORTn.bit or PORTn.@L.

CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS

5.1.5 Specification of Bilt-in Pull-Up Resistors

A pull-up resistor can be contained at each port pin of the µPD750008 (except for P00). Whether to use

the pull-up resistor can be specified by software (for some pins) or a mask option (for the other pins).

Table 5-4 shows how a built-in pull-up resistor is specified for each port pin. The built-in pull-up resistor

is connected by software in the format shown in Figure 5-8.

Table 5-4. Specification of Built-in Pull-Up Resistors

Port (pin name)

Pull-up resistor incorporation specification method

Bit of POGA

Bit of POGB

Note

Port 0 (P01-P03)

Port 1 (P10-P13)

Port 2 (P20-P23)

Port 3 (P30-P33)

Port 6 (P60-P63)

Port 7 (P70-P73)

Port 4 (P40-P43)

Port 5 (P50-P53)

Port 8 (P80, P81)

Connection specification by software in 3-bit units

Connection specification by software in 4-bit units

Bit 0

Bit 1

Bit 2

Bit 3

Bit 6

Bit 7

—

Incorporation specification by mask option in 1-bit

units

Connection specification by software in-2-bit units

—

Bit 0

Note The P00 pin cannot specify connection of a built-in pull-up resistor.

Remark The port pins of the µPD75P0016 are not connected to a pull-up resistor by mask option, and

are always open.

µPD750008 USER'S MANUAL

Figure 5-8. Pull-Up Resistor Specification Register Format

Specification contents

Built-in pull-up resistor not connected

Built-in pull-up resistor connected

Pull-up resistor specification register group A

Address

Symbol

POGA

FDCH

PO7

PO6

—

PO3

PO2

PO1

PO0

Port 0 (P01 - P03)

Port 1 (P10 - P13)

Port 2 (P20 - P23)

Port 3 (P30 - P33)

Port 6 (P60 - P63)

Port 7 (P70 - P73)

Pull-up resistor specification register group B

Address

Symbol

POGB

—

FDEH

—

PO8

Port 8 (P80, P81)

5.1.6 I/O Timing of Digital I/O Ports

Figure 5-9 shows the timing of data output to an output latch and the timing of taking in pin data or output

latch data on the internal bus.

Figure 5-10 shows an ON timing chart when a built-in pull-up resistor is connected to a port pin by software.

Figure 5-9. I/O Timing Chart of Digital I/O Ports (1/2)

(a) When data is input by a 1-machine cycle instruction

1 machine cycle

Instruction

Manipulation instruction

execution

Input timing

CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS

Figure 5-9. I/O Timing Chart of Digital I/O Ports (2/2)

(b) When data is input by a 2-machine cycle instruction

2 machine cycles

Instruction

Manipulation instruction

execution

Input timing

Instruction

execution

Manipulation instruction

Output latch

(output pin)

(d) When data is latched by a 2-machine cycle instruction

Instruction

execution

Manipulation instruction

Output latch

(output pin)

Figure 5-10. ON Timing Chart of Built-in Pull-Up Resistor Connected by Software

2 machine cycles

Instruction

execution

Built-in pull-up resistor setting instruction

Pull-up resistor

specification

µPD750008 USER'S MANUAL

5.2 CLOCK GENERATOR

The clock generator supplies various clock signals to the CPU and peripheral hardware to control the CPU

operation mode.

5.2.1 Clock Generator Configuration

Figure 5-11 shows the configuration of the clock generator.

Figure 5-11. Block Diagram of the Clock Generator

• Basic interval timer (BT)

• Timer/event counter

• Timer counter

• Serial interface

• Clock timer

XT1

fXT

Subsystem

clock generator

Clock timer

XT2

• INT0 noise eliminator

• Clock output circuit

1/1 to 1/4096

Frequency divider

Main system

clock generator

1/2 1/4 1/16

Selec-

tor

Oscillator

disable

signal

WM.3

SCC

Frequency

divider

SCC3

SCC0

Selec-

tor

1/4

•

CPU

INT0 noise eliminator

Clock output circuit

PCC

PCC0

PCC1

PCC2

PCC3

HALT flip-flop

HALT^Note

STOP^Note

PCC2, PCC3

clear signal

STOP flip-flop

Wait release signal from BT

RESET signal

Standby release signal from

interrupt control circuit

Note Instruction execution

Remarks 1. f : Main system clock frequency

2. f : Subsystem clock frequency

3. F = CPU clock

4. PCC: Processor clock control register

5. SCC: System clock control register

6. One clock cycle (t ) of the CPU clock (F) is equal to one machine cycle of an instruction.

CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS

5.2.2 Functions and Operations of the Clock Generator

The clock generator generates the following clocks, and controls the CPU operation modes such as the

standby mode.

• Main system clock f

• Subsystem clock f

• CPU clock F

• Clock to peripheral hardware

The operation of the clock generator is determined by the processor clock control register (PCC) and system

clock control register (SCC). The function and operation of the clock generator are described in (a) to (g) below.

Note 1

(a) A RESET signal selects the lowest-speed mode (10.7 µs at 6.00 MHz)

(PCC = 0, SCC = 0).

for the main system clock

(b) When the main system clock is selected, the PCC can be set to select one of four CPU clocks (0.67

Note 2

µs, 1.33 µs, 2.67 µs, and 10.7 µs at 6.00 MHz)

available.

(d) The SCC can be set to select the subsystem clock for very low-speed, low-current operation (122 µs

at 32.768 kHz). The value in the PCC does not affect the CPU clock.

(e) When the subsystem clock is selected, main system clock generation can be stopped with the SCC.

In addition, the HALT mode can be used, but the STOP mode cannot be used. (Subsystem clock

generation cannot be stopped.)

(f) The clock to be supplied to peripheral hardware is produced by frequency-dividing the main system

clock signal. The subsystem clock can directly be supplied only to the clock timer. This enables the

clock function and the buzzer output function to continue operating even in the standby state.

(g) When the subsystem clock is selected, the clock timer can continue to operate normally. The serial

interface, timer/event counter, and timer counter can continue to operate when the external clock is

selected. However, other hardware cannot be used when the main system clock is stopped because

they operate with the main system clock.

Notes 1. At f = 4.19 MHz: 15.3 µs

2. At f = 4.19 MHz: 0.95 µs, 1.91 µs, 3.81 µs, and 15.3 µs

µPD750008 USER'S MANUAL

(1) Processor clock control register (PCC)

The PCC is a 4-bit register for selecting a CPU clock F with the low-order two bits and for controlling the

CPU operation mode with the high-order two bits (see Figure 5-12).

When bit 3 or bit 2 is set to 1, the standby mode is set. When the standby mode is released by the standby

release signal, these bits are automatically cleared to return to the normal operation mode. (SeeChapter

7 for details.)

A 4-bit memory manipulation instruction is used to set the low-order two bits of the PCC. (The high-order

two bits are set to 0.)

Bit 3 and bit 2 are set to 1 using the STOP instruction and HALT instruction, respectively.

The STOP instruction and HALT instruction can always be executed regardless of MBE setting.

The CPU clock can be selected only while the processor is operated by the main system clock. When

the processor is operated by the subsystem clock, the low-order 2 bits of the PCC are invalidated, and

/4 is automatically set. The STOP instruction can be executed only when the processor is operated

by the main system clock.

Examples 1. The machine cycle is entered in highest-speed mode (0.67 µs at f = 6.00 MHz).

SEL MB15

MOV A,#0011B

MOV PCC,A

2. The machine cycle is set to 1.91 µs (at f = 4.19 MHz).

SEL MB15

MOV A,#0010B

MOV PCC,A

3. The STOP mode is set. (A STOP instruction or HALT instruction must always be followed

by an NOP instruction.)

STOP

NOP

A RESET signal clears the PCC to 0.

CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS

Figure 5-12. Format of the Processor Clock Control Register

Address

FB3H

Symbol

PCC

PCC3 PCC2 PCC1 PCC0

CPU clock selection bit

(Operation with f^X= 6.0 MHz)

SCC3, SCC0 = 00

SCC3, SCC0 = 01 or 11

( ) is actual frequency at f^X= 6.0 MHz ( ) is actual frequency at fXT = 32.768 kHz

CPU clock frequency 1 machine cycle CPU clock frequency 1 machine cycle

Φ = f^XT/4 (8.192 kHz)

122 µs

Φ = f^X/64 (93.7 kHz)

Φ = f^X/16 (375 kHz)

Φ = f^X/8 (750 kHz)

Φ = f^X/4 (1.5 MHz)

10.7 µs

2.67 µs

1.33 µs

0.67 µs

(Operation with fX = 4.19 MHz)

SCC3, SCC0 = 00

SCC3, SCC0 = 01 or 11

( ) is actual frequency at = 4.19 MHz ( ) is actual frequency at fXT = 32.768 kHz

CPU clock frequency 1 machine cycle CPU clock frequency 1 machine cycle

Φ = f^XT/4 (8.192 kHz)

122 µs

15.3 µs

3.81 µs

1.91 µs

0.95 µs

Φ = f^X/64 (65.5 kHz)

Φ = f^X/16 (262 kHz)

Φ = f^X/8 (524 kHz)

Φ = f^X/4 (1.05 MHz)

Remarks 1. fX

Output frequency from the main system clock oscillator

2. f^XT: Output frequency from the subsystem clock oscillator

CPU operation mode control bits

Normal operation mode

HALT mode

STOP mode

Not to be set

µPD750008 USER'S MANUAL

(2) System clock control register (SCC)

The SCC is a 4-bit register for selecting CPU clock F with the least significant bit and for controlling the

termination of main system clock generation with the most significant bit (see Figure 5-13).

Bits 0 and 3 of the SCC are located at the same data memory address, but both bits cannot be changed

at the same time. Accordingly, bits 0 and 3 of the SCC are set using bit manipulation instructions. Bits

0 and 3 of the SCC can be manipulated regardless of MBE setting.

Main system clock generation can be terminated by setting bit 3 of the SCC only when the subsystem

clock is used for operation. The STOP instruction must be used to terminate main system clock generation.

A RESET signal clears the SCC to 0.

Figure 5-13. Format of the System Clock Control Register

Address

FB7H

Symbol

SCC

—

SCC3

SCC0

SCC3 SCC0

CPU clock frequency

Main system clock

Main system clock operation

Can oscillate

Subsystem clock

Not to be set

Subsystem clock

Oscillation stopped

Cautions 1. A time period of up to 1/f is needed to change the system clock. This means

that to terminate main system clock generation, bit 3 of the SCC must be set to 1

when the machine cycles indicated in Table 5-4 or more have elapsed after the

clock is switched from the main system clock to the subsystem clock.

2. When the main system clock is used for operation, setting bit 3 of the SCC to

stop clock generation does not enter the normal STOP mode.

3. When the PCC is set to 0001B (F = f /16), do not set SCC.0 to 1. Before switch-

ing the main system clock to the subsystem clock, be sure to manipulate the

PCC so other than 0001B is set. When the system operates on the subsystem

clock, the PCC must also be other than 0001B.

4. When SCC.3 is set to 1, the X1 input pin is connected to V (ground electric

potential) to prevent leakage in the crystal oscillator. When an external clock is

used as the main system clock, never set SCC.3 to 1.

CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS

(3) System clock oscillator

The main system clock oscillator operates with a crystal resonator or ceramic resonator connected to the

X1 and X2 pins.

An external clock can also be input. Input the clock signal to the X1 pin and the reversed signal to the

X2 pin.

Figure 5-14. External Circuit for the Main System Clock Oscillator

(a) Crystal/ceramic oscillation

(b) External clock

µPD750008

External

clock

VSS

Crystal or ceramic resonator

(Standard frequency: 6.0 or 4.19 MHz)

The subsystem clock oscillator operates with a crystal resonator (32.768 kHz standard) connected to the

XT1 and XT2 pins.

An external clock can also be input. Input the clock signal to the XT1 pin and leave the XT2 pin open.

The state of the XT1 pin is tested by bit 3 of the clock mode register (WM).

Figure 5-15. External Circuit for the Subsystem Clock Oscillator

(a) Crystal oscillation

(b) External clock

µPD750008

XT1

µPD750008

External

clock

VSS

XT1

XT2

Open XT2

Crystal

(Standard frequency: 32.768 kHz)

Cautions 1. When the external clock is used as the main system clock or subsystem clock, the

STOP mode cannot be set. This is because the X1 pin is connected to V in the STOP

mode.

2. When the main system clock or subsystem clock oscillator is used, conform to

the following guidelines when wiring enclosed in broken lines of Figures 5-14

and 5-15 to eliminate the influence of the stray capacitance around the wiring.

• The wiring must be as short as possible.

• Other signal lines must not run in these areas.

µPD750008 USER'S MANUAL

Any line carrying a high pulsating current must be kept away as far as possible.

• The grounding point of the capacitor of the oscillator must have the same

potential as that of V . It must not be grounded to a grounding pattern carry

ing a high current.

• No signal must be taken directly from the resonator.

The subsystem clock oscillator has low amplification to minimize current con-

sumption. For this reason, more malfunctions can occur due to noise than the

main system clock oscillator. So pay special attention to wiring when using the

subsystem clock.

Figure 5-16 gives examples of oscillator connections which should be avoided.

Figure 5-16. Examples of Oscillator Connections Which Should Be Avoided (1/2)

(a) The wiring is too long.

(b) The signal lines cross.

PORTn

(n = 0 to 8)

µPD750008

VSS

Remark When wiring the subsystem clock, read X1 and X2 as XT1 and XT2 respectively. In this case,

a resistor must be added to XT2 in series.

CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS

Figure 5-16. Examples of Oscillator Connections Which Should Be Avoided (2/2)

close to the signal line.

(d) The current flows through the ground

line of the oscillator. (The potential

at points A, B, and C fluctuates.)

VDD

µPD750008

Pnm

VSS

High current

(e) A signal is taken directly from

the resonator.

(f) The signal lines of the main system

clock and subsystem clock are parallel

and adjacent to each other.

µPD750008

VSS

XT1

XT2

XT2 and XT1 are wired

in parallel.

Remark When wiring the subsystem clock, read X1 and X2 as XT1 and XT2 respectively. In this case,

a resistor must be added to XT2 in series.

µPD750008 USER'S MANUAL

(4) Frequency divider

The frequency divider divides the output (f ) of the main system clock oscillator to generate various clocks.

(5) Control functions of subsystem clock oscillator

The subsystem clock oscillator of the µPD750008 subseries has two control functions to decrease the

supply current.

• The function to select with the software whether to use the built-in feedback resistor

• The function to suppress the supply current by reducing the drive current of the built-in inverter when

the operating supply voltage is high (V

• 2.7 V)

Each function can be used by switching bits 0 and 1 in the sub-oscillator control register (SOS). (See

Figure 5-17.)

Figure 5-17. Subsystem Clock Oscillator

SOS.0

Feedback resistor

Inverter

µPD750008

SOS.1

XT1

XT2

CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS

(6) Sub-oscillator control register (SOS)

The SOS register specifies whether to use the built-in feedback register and controls the drive current

of the built-in inverter. (See Figure 5-18.)

Inputting a RESET signal clears all bits of the SOS register. The functions of each flag in the SOS register

are described below.

(a) SOS.0 (feedback resistor cut flag)

To use the feedback resistor of the subsystem clock, the mask option setup and switching SOS.0 by

software are required. Set SOS.0 to 0 to turn on the feedback circuit.

When the resonator is not used, set SOS.0 to 1. The feedback circuit is turned off, reducing the current

drain.

To use the resonator, be sure to select "Enable the feedback resistor" upon setting the mask option.

Then, set SOS.0 to 0 (feedback circuit is turned on).

(b) SOS.1 (drive capability switch flag)

The built-in inverter in the subsystem clock oscillator of the µPD750008 subseries has a large drive

current because it can be used at low supply voltage (V = 1.8 V), so that the supply current becomes

too high to use at high supply voltage (V

• 2.7 V). To reduce the supply current, set SOS.1 to 1

so as to reduce the drive current of the inverter.

However, if SOS.1 is set to 1 when V is less than 2.7 V, the oscillation may stop for insufficient

drive current. Set this flag to 0 when V

is less than 2.7 V.

Figure 5-18. Sub-Oscillator Control Register (SOS) Format

Address

FCFH

Symbol

SOS1 SOS0

SOS

Cut flag for feedback resistor of the sub-oscillator

Built-in feedback resistor is used.

Built-in feedback resistor is not used.

Cut flag for the sub-oscillator current

Drive current is high (1.8 V ≤ V^DD)

Drive current is low (2.7 V ≤ V^DD)

Bits 2 and 3 of SOS must be set to 0.

Remark If the subsystem clock is not required , the XT1 and XT2 pins and SOS register must be

treated as follows:

XT1 : Connected to V or V

XT2 : Open

SOS: 0001B

µPD750008 USER'S MANUAL

5.2.3 System Clock and CPU Clock Setting

(1) Time required to change the system clock and CPU clock

The system clock and CPU clock can be changed by using the least significant bit of the SCC and the

low-order two bits of the PCC. This switching is not performed immediately after the contents of the

registers are rewritten, but the system operates with the previous clock for some machine cycles.

Accordingly, after this time period, the STOP instruction must be executed to terminate main system clock

generation.

Table 5-5. Maximum Time Required to Change the System Clock and CPU Clock

Setting before

Setting after switching

switching

SCC0 PCC1 PCC0 SCC0 PCC1 PCC0 SCC0 PCC1 PCC0 SCC0 PCC1 PCC0 SCC0 PCC1 PCC0 SCC0 PCC1 PCC0

1 machine

cycle

1 machine

cycle

1 machine

cycle

fX/64fXT machine

cycles

(3 machine cycles)

4 machine

cycles

4 machine

cycles

4 machine

cycles

Not to be set

8 machine

cycles

8 machine

cycles

8 machine

cycles

fX/8fXT machine

cycles

(23 machine cycles)

16 machine

cycles

16 machine

cycles

16 machine

cycles

fX/4fXT machine

cycles

(46 machine cycles)

1 machine

cycle

Not to be

set

1 machine

cycle

1 machine

cycle

Remarks 1. Time indicated in parentheses is required when f = 6.00 MHz and f = 32.768 kHz.

2. X: Dont care

3. CPU clock F is supplied to the CPU of the µPD750008. The reciprocal of this frequency

is a minimum instruction time (defined as one machine cycle in this manual).

Cautions 1. When the PCC is set to 0001B (F = f /16), do not set SCC.0 to 1. Before switching

the main system clock to the subsystem clock, be sure to manipulate the PCC so

other than 0001B is set. When the system operates on the subsystem clock, the

PCC must also be other than 0001B.

2. The fluctuation of the ambient temperature around an oscillator and the performance

of a load capacity change f and f . In particular, when f is higher than the nominal

value or f is lower than the nominalvalue, the machine cycles calculated by f /64f ,

f / 8f , and f /4f in Table 5-5 are longer than the machine cycle calculated by the

nominal values of f and f . Therefore, the wait time required to change the system

clock and CPU clock should be longer than the machine cycle calculated by the

nominal values of f and f

CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS

(2) Procedure for changing the system clock and CPU clock

The procedure for changing the system clock and CPU clock is explained using Figure 5-19.

Figure 5-19. Changing the System Clock and CPU Clock

Commercial

power

line voltage

OFF

V^DDpin voltage

RESET signal

Wait ^{Note 1}

f^XT

System clock

CPU clock

10.7 µs

0.67 µs

122 µs

0.67 µs

= 6.00 MHz

Internal reset

operation

f^XT= 32.768 kHz

<1> A RESET signal starts CPU operation at the lowest speed of the main system clock (10.7 µs at

Note 1

6.00 MHz,15.3 µs at 4.19 MHz) after a wait time

for stable oscillation.

<2> The PCC is rewritten for highest-speed operation after a time elapse which is sufficient for the

voltage on the V pin to be high enough for highest-speed operation.

Note 2

<3> The removal of commercial current is detected using, for example, an interrupt input

, then bit

0 of the SCC is set to 1 to operate with the subsystem clock. (In this case, subsystem clock

generation must have been started.) After a time (46 machine cycles) required to switch to the

subsystem clock elapses, bit 3 of the SCC is set to 1 to terminate main system clock generation.

<4> After detecting the input of commercial current by using an interrupt, bit 3 of the SCC is cleared

to start main system clock generation. After a time required for stable generation, bit 0 of the SCC

is cleared to 0 to operate at the highest speed.

Notes 1. The following two wait times can be selected by a mask option:

2 /f (21.8ms at 6.00 MHz, 31.3ms at 4.19 MHz)

2 /f (5.46ms at 6.00 MHz, 7.81ms at 4.19 MHz)

However, the µPD75P0016 does not have a mask option and its wait time is fixed to 2 /f

2. INT4 is useful.

µPD750008 USER'S MANUAL

5.2.4 Clock Output Circuit

(1) Configuration of the clock output circuit

Figure 5-20 shows the configuration of the clock output circuit.

(2) Functions of the clock output circuit

The clock output circuit outputs a clock pulse signal on the P22/PCL pin to output remote control signals

or to supply clock pulses to a peripheral LSI device.

The procedure for outputting a clock pulse signal is as follows:

(a) Select a clock output frequency, and disable clock output.

(b) Write a 0 in the P22 output latch.

(d) Enable clock output.

Figure 5-20. Configuration of the Clock Output Circuit

From the clock

generator

Output

/2³

/2⁴

/2⁶

buffer

Selector

PCL/P22

PORT2.2

Bit 2 of PMGB

Port 2 input/

output mode

specification bit

P22 output

latch

CLOM3

CLOM1 CLOM0 CLOM

Internal bus

Remark The clock output circuit is designed so that pulses with short widths do not appear in enabling

or disabling clock output.

CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS

(3) Clock output mode register (CLOM)

The CLOM is a 4-bit register to control clock output.

The CLOM is set by a 4-bit memory manipulation instruction. No read operation is allowed on this register.

Example CPU clock F is output on the PCL/P22 pin.

SEL

MB15

; or CLR1 MBE

MOV

A,#1000B

CLOM,A

A RESET signal clears the CLOM to 0, disabling clock output.

Figure 5-21. Format of the Clock Output Mode Register

Address

FD0H

Symbol

CLOM

CLOM3

CLOM1 CLOM0

Clock output frequency selection bit

(f^X= 6.00 MHz)

Φ output^Note(1.5 MHz, 750 kHz, 375 kHz, 93.8 kHz)

X/2³output (750 kHz)

X/2⁴output (375 kHz)

X/2⁶output (93.8 kHz)

(fX = 4.19 MHz)

Φ output^Note(1.05 MHz, 524 kHz, 262 kHz, 65.5 kHz)

X/2³output (524 kHz)

X/2⁴output (262 kHz)

X/2⁶output (65.5 kHz)

Note

is the CPU clock selected by PCC.

Clock output enable/disable bit

Output disable

Output enable

Caution Be sure to write a 0 in bit 2 of the CLOM.

µPD750008 USER'S MANUAL

(4) Application to remote control output

The clock output function of the µPD750008 is applicable to remote control output. The frequency of the

carrier for remote control output is selected by the clock frequency select bit of the clock output mode

The clock output circuit is designed so that pulses with short widths do not appear in enabling or disabling

clock output.

Figure 5-22. Application to Remote Control Output

Bit 3 of CLOM

PCL pin output

CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS

5.3 BASIC INTERVAL TIMER/WATCHDOG TIMER

The µPD750008 contains an 8-bit basic interval timer/watchdog timer, which has the following functions:

(a) Interval timer operation which generates a reference timer interrupt

(b) Operation as a watchdog timer for detecting program crashes and resetting the CPU

(d) Reading the count value

5.3.1 Configuration of the Basic Interval Timer/Watchdog Timer

Figure 5-23 shows the configuration of the basic interval timer/watchdog timer.

Figure 5-23. Block Diagram of the Basic Interval Timer/Watchdog Timer

From the clock

generator

Clear signal

/2⁵

/2⁷

/2⁹

/2¹²

Set

signal

Basic interval timer

(8-bit frequency divider)

BT interrupt

request flag

MPX

Vectored

interrupt

request

signal

IRQBT

Internal

reset signal

Wait release

signal for standby

release

SET1^Note

BTM3

BTM2 BTM1 BTM0

BTM

WDTM

SET1^Note

Internal bus

Note Instruction execution

5.3.2 Basic Interval Timer Mode Register (BTM)

The BTM is a 4-bit register for controlling operation of the basic interval timer (BT).

A 4-bit memory manipulation instruction is used to set the BTM.

Bit 3 can be independently manipulated using a bit manipulation instruction.

Example The interrupt generation interval is set to 1.37 ms (at 6.00 MHz).

SEL

MB15

; or CLR1 MBE

MOV A,#1111B

MOV BTM,A

; BTM <– 1111B

µPD750008 USER'S MANUAL

When bit 3 is set to 1, the BT is cleared, and the basic interval ltimer/watchdog timer interrupt request flag

(IRQBT) is also cleared (to start the basic interval timer/watchdog timer).

A RESET signal clears the interval timer to 0, and the longest interrupt request signal generation interval

time is set.

Figure 5-24. Format of the Basic Interval Timer Mode Register

Address

F85H

Symbol

BTM

BTM1

BTM3 BTM2

BTM0

(f^X= 6.00 MHz)

Interrupt interval time

Input clock specification

X/2¹²(1.46 kHz)

(wait time for releasing standby)

2²⁰/fX(175 ms)

X/2⁹(11.7 kHz)

X/2⁷(46.9 kHz)

X/2⁵(188 kHz)

¹⁷/fX(21.8 ms)

2¹⁵/fX(5.46 ms)

¹³/fX(1.37 ms)

Other than

above

—

Not to be set

(f^X= 4.19 MHz)

Interrupt interval time

Input clock specification

X/2¹²(1.02 kHz)

(wait time for releasing standby)

2²⁰/fX(250 ms)

X/2⁹(8.18 kHz)

2¹⁷/fX(31.3 ms)

X/2⁷(32.768 kHz)

¹⁵/fX(7.82 ms)

X/2⁵(131 kHz)

¹³/fX(1.95 ms)

Other than

above

—

Not to be set

Basic interval timer/watchdog timer start control bit

When 1 is written to this bit, the basic interval timer/watchdog timer operation starts

(the counter and the interrupt request flag are cleared).

When the operation starts, this bit is automatically reset to 0.

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CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS

5.3.3 Watchdog Timer Enable Flag (WDTM)

WDTM, when set, is a flag for enabling the generation of the reset signal when the basic interval timer

overflows. WDTM is set by a bit manipulation instruction. It cannot be cleared by an instruction.

Example Set the watchdog timer function.

SEL

MB15

; or CLR1 MBE

SET1 WDTM

SET1 BTM.3

; Set bit 3 of BTM to 1

The generation of a RESET signal clears WDTM to 0.

Figure 5-25. Format of the Watchdog Timer Enable Flag (WDTM)

Address

F8BH.3

WDTM

BT mode

Sets IRQBT when the basic interval timer (BT)

overflows.

WT mode

Generates an internal reset signal when the basic

interval timer (BT) overflows.

5.3.4 Operation of the Basic Interval Timer

When WDTM is set to 0, the basic interval timer (BT) functions as an interval timer. An interrupt request

flag (IRQBT) is set when the timer overflows. BT is constantly incremented by the clock supplied from the

clock generator. So it is impossible to stop the timer from incrementing.

One of four interrupt generation intervals can be selected by setting BTM. (See Figure 5-24.)

BT and IRQBT can be cleared by setting bit 3 of BTM to 1 (instruction for starting as an interval timer).

The count status of BT can be read by an 8-bit manipulation instruction. No data can be loaded to the timer.

Perform the timer operation as follows (<1> and <2> can be performed with the same instruction):

<1> Set the interval in BTM.

<2> Set 1 in bit 3 of BTM.

Example Generate an interrupt at intervals of 1.37 ms (at 6.00 MHz).

SET1 MBE

SEL

MB15

MOV A,#1111B

MOV BTM,A

; Set the interval and start processing

; Enable interrupt

IEBT

; Enable BT interrupt

101

µPD750008 USER'S MANUAL

5.3.5 Operation of the Watchdog Timer

When WDTM is set to 1, the basic interval timer/watchdog timer functions as a watchdog timer. An internal

reset signal is generated when the basic interval timer (BT) overflows. No reset signal, however, is generated

during the oscillation wait time following the STOP instruction has been released (WDTM cannot be cleared

without using reset). BT is constantly incremented by the clock supplied from the clock generator. It cannot

be stopped from counting.

In the watchdog timer mode, program crashes are detected using the intervals at which BT overflows. The

interval can be selected from among four values depending on bits 2 to 0 of BTM (see Figure 5-24). Select

an interval for detecting crashes according to the user system. A large program should be divided into modules

each of which can be executed within the set interval. Include an instruction which clears BT at the end of

each module. If execution does not reach the instruction which clears BT within the set interval (in which case

a program error leading to a program crash may have occurred), BT overflows and an internal reset signal

is generated to forcibly terminate the program. The occurrence of internal reset possibly means that a program

crash has occurred. A crash can thus be detected.

Set the watchdog timer as follows (<1> and <2> can be performed with the same instruction):

<1> Set the interval in BTM.

<2> Set 1 in bit 3 of BTM.

Initial settings

<3> Set 1 in WDTM.

<4> After <1> to <3> are set, set 1 in bit 3 of BTM within each interval.

Example Use the basic interval/watchdog timer as a watchdog timer with 5.46-ms interval (at 6.00 MHz)

A program is divided into several modules each of which can be executed within the interval

set in BTM (5.46 ms). BT is cleared at the end of each module. If a program crash occurs, BT

overflows and an internal reset signal is generated because BT is not cleared within the set

interval.

Initial setting:

SET1 MBE

SEL

MB15

MOV

A, #1101B

BTM, A

; Specifies a time interval and

; starts processing.

SET1 WDTM

; Enables the watchdog timer.

(From now on, 1 is set in bit 3 of BTM at intervals of 5.46 ms.)

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CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS

Module 1:

Processing completes

within 5.46 ms.

SET1 MBE

SEL MB15

SET1 BTM.3

Module 2:

Processing completes

within 5.46 ms.

SET1 MBE

SEL MB15

SET1 BTM.3

5.3.6 Other Functions

The basic interval timer/watchdog has the following functions regardless of whether it operates as a basic

interval timer or watchdog timer:

<1> Selecting and counting the wait time after the standby mode is released

<2> Reading the count

(1) Selecting and counting the wait time after the STOP mode is released

To allow the system clock to stabilize after releasing the STOP mode, a wait function is available which

stops the operation of the CPU until the basic interval timer (BT) overflows.

The wait time after generation of a RESET signal is fixed as specified by a mask option. On the other

hand, a wait time can be selected by setting BTM when releasing the STOP mode with an interrupt

occurrence. In this case, the wait times are the same as the interval times shown in Figure 5-24. BTM

must be set before the STOP mode is set. (For details, see Chapter 7.)

Example Set the wait time 5.46 ms (at 6.00 MHz) in releasing the STOP mode with an interrupt.

SET1

SEL

MBE

MB15

MOV

STOP

NOP

A, #1101B

BTM, A

; Set wait time

; Set STOP mode

103

µPD750008 USER'S MANUAL

(2) Reading the count

The count status of the basic interval timer (BT) can be read by using an 8-bit manipulation instruction.

No data can be loaded to the timer.

Caution When reading the count value of BT, execute a read instruction twice so that unstable

data which has been counted will not be read. If the two read values are reasonable, use

the second one as the result. If the two read values are far apart, retry from the beginning.

Examples 1. Read the count value of BT.

SET1

SEL

MBE

MB15

HL, #BT

MOV

; Set the BT address in HL

LOOP: MOV

MOV

XA, @HL ; First read

BC, XA

MOV

XA, @HL ; Second read

XA, BC

SKE

LOOP

2. Set the high level width of pulses applied to the INT4 interrupt pin (both edges detected).

(The pulse width is assumed not to exceed the value (5.46 ms or longer at 6.00 MHz) set

in the BTM.)

LOOP: MOV

MOV

SKE

XA, BT

BC, XA

XA, BT

A, C

; First read

; Store data

; Second read

LOOP

A, X

MOV

SKE

A, B

LOOP

SKT

PORT0.0 ; P00 = 1?

; NO

MOV

CLR1

RETI

XA, BC

BUFF, XA

FLAG

; Store data in data memory

; Clear data presence flag

AA:

MOV

SUBC

INCS

MOV

SUBC

MOV

HL, #BUFF

A, C

A, @HL

C, A

A, B

A, @HL

B, A

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CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS

MOV

SET1

RETI

XA, BC

BUFF, XA ; Store data

FLAG ; Set data presence flag

5.4 CLOCK TIMER

The µPD750008 contains one clock timer, which has the following functions.

(a) The clock timer sets the test flag (IRQW) every 0.5 seconds.

The IRQW can release the standby mode.

(b) Either the main system clock or the subsystem clock can be used to produce 0.5-second intervals.

Use a main system clock of 4.194304 MHz.

debugging and testing.

(d) Any of the frequencies 2.048 kHz, 4.096 kHz, and 32.768 kHz can be output to the P23/BUZ pin, so

that it can be used for sounding the buzzer and for system clock frequency trimming.

(e) The frequency divider can be cleared to start the clock from zero second.

105

µPD750008 USER'S MANUAL

5.4.1 Configuration of the Clock Timer

Figure 5-26 shows the configuration of the clock timer.

Figure 5-26. Block Diagram of the Clock Timer

2⁷

(256 Hz: 3.91 ms)

INTW

IRQW

set signal

Selector

2¹⁴

128

(32.768 kHz)

From the

clock

generator

Selector

Frequency divider

2 Hz

0.5 sec

f^XT

(4 kHz) (2 kHz)

(32.768 kHz)

Clear signal

2³

2⁴

Selector

Output buffer

P23/BUZ

PORT2.3

Bit 2 of PMGB

Port 2 input/

P23 output

latch

WM7

WM5 WM4 WM3 WM2 WM1 WM0

output mode

Bit test instruction

Internal bus

The values in parentheses are for f = 4.194304 MHz and f = 32.768 kHz.

5.4.2 Clock Mode Register

The clock mode register (WM) is an 8-bit register which controls the clock timer. Figure 5-27 shows the

format of the clock mode register.

All bits except bit 3 of the clock mode register are controlled by an 8-bit manipulation instruction. Bit 3 is

for testing the XT1 pin input level. The input level of the XT1 pin can be tested by bit test operation. No data

can be written to this register.

When the RESET signal is generated, all bits except bit 3 of this register are cleared to 0.

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CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS

Example Time is set using the main system clock (4.19 MHz), and buzzer output is enabled:

CLR1 MBE

MOV XA, #84H

MOV WM, XA

; Sets WM

Figure 5-27. Clock Mode Register Format

Address

F98H

Symbol

WM7

WM5 WM4 WM3 WM2 WM1 WM0

BUZ output enable/disable bit

WM7

Disables BUZ output

Enables BUZ output

BUZ output frequency selection bit

WM4 BUZ output frequency

WM5

(2.048 kHz)

(4.096 kHz)

2⁴

2³

Not to be set

(32.768 kHz)

XT1 pin input level (bit test only)

WM3

Input to the XT1 pin is low level

Input to the XT1 pin is high level

Clock operation enable/disable bit

Disables clock operation (clears the frequency dividing circuit)

Enables clock operation

WM2

Operation mode selection bit

WM1

Normal clock mode (

: sets IRQW at 0.5 seconds)

2¹⁴

Advanced clock mode (

: sets IRQW at 3.91 ms)

2⁷

Count clock (fW) selection bit

Selects divided system clock output:

Selects subsystem clock: f^XT

WM0

128

Remark ( ) for f = 32.768 kHz

107

µPD750008 USER'S MANUAL

5.5 TIMER/EVENT COUNTER

The µPD750008 has one timer/event counter channel (channel 0) and one timer counter channel (channel

1). Figures 5-28 and 5-29 show the configuration of these channels.

In this section, the timer/event counter and timer counters are referred to as "timer/event counters." When

you read this section for description of channel 1, take "timer/event counter" as "timer counter."

The timer/event counter has the following functions.

(a) Programmable interval timer operation

(b) Square wave output of any frequency to the PTOn pin.

(d) Divides the frequency of signal input via the TI0 pin to 1-Nth of the original signal and outputs the

divided frequency to the PTO0 pin (frequency divider operation) (Channel 0 only).

(e) Supplies the serial shift clock to the serial interface circuit (Channel 0 only).

(f) Calls the counting status.

5.5.1 Configuration of timer/event counter

Figures 5-28 and 5-29 shows the configuration of the timer/event counter.

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CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS

109

µPD750008 USER'S MANUAL

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CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS

(1) Timer/event counter mode register (TM0, TM1)

The mode register (TMn) is an 8-bit register which controls the timer/event counter.

Its format is shown in Figures 5-30 and 5-31.

The timer/event counter mode register is set by an 8-bit memory manipulation instruction.

Bit 3 is a timer start bit and can be operated bit-wise. It is automatically reset to 0 when the timer operation

starts.

All the bits of the timer/event counter mode register are cleared to 0 by a RESET signal generation.

Examples 1. Start the timer in the interval timer mode of CP = 5.86 kHz (during 6.00 MHz operation).

SEL

MB15

; or CLR1 MBE

; TMn <– 4CH

MOV

XA, #01001100B

TMn, XA

2. Restart the timer according to the setting of the timer/event counter mode register.

SEL

MB15

TMn.3

; or CLR1 MBE

; TMn.bit3 <– 1

SET1

111

µPD750008 USER'S MANUAL

Figure 5-30. Timer/Event Counter Mode Register (Channel 0) Format

Address

FA0H

Symbol

TM0

TM06 TM05 TM04 TM03 TM02

Count pulse (CP) selection bit

When f^X= 6.00 MHz

TM06 TM05 TM04

Count pulse (CP)

TI0 rising edge

TI0 falling edge

X/2¹⁰(5.86 kHz)

X/2⁸(23.4 kHz)

X/2⁶(93.8 kHz)

X/2⁴(375 kHz)

Other than above

Not to be set

When fX = 4.19 MHz

TM06 TM05 TM04

Count pulse (CP)

TI0 rising edge

TI0 falling edge

X/2¹⁰(4.09 kHz)

X/2⁸(16.4 kHz)

X/2⁶(65.5 kHz)

X/2⁴(262 kHz)

Other than above

Not to be set

Timer start indication bit

TM03 When 1 is written into the bit, the counter and IRQT0 flag are cleared.

If bit 2 is set to 1, count operation is started.

Operation mode

TM02

Count operation

Stop (retention of count contents)

Count operation

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CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS

Figure 5-31. Timer Counter Mode Register (Channel 1) Format

Address

FA8H

Symbol

TM1

TM16 TM15 TM14 TM13 TM12

Count pulse (CP) select bit

When f^X= 6.00 MHz

TM16

TM14

Count pulse (CP)

TM15

X/2¹²(1.46 kHz)

X/2¹⁰(5.86 kHz)

X/2⁸(23.4 kHz)

X/2⁶(93.8 kHz)

Other than above

Not to be set

When fX = 4.19 MHz

TM16 TM15 TM14

Count pulse (CP)

X/2¹²(1.02 kHz)

X/2¹⁰(4.09 kHz)

X/2⁸(16.4 kHz)

X/2⁶(65.5 kHz)

Other than above

Not to be set

Timer start indication bit

TM13 When 1 is written into the bit, the counter and IRQT1 flag are cleared.

If bit 2 is set to 1, count operation is started.

Operation mode

TM12

Count operation

Stop (retention of count contents)

Count operation

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µPD750008 USER'S MANUAL

(2) Timer/event counter output enable flag (TOE0, TOE1)

The timer/event counter output enable flag (TOE0, TOE1) controls the output enable/disable to the PTO0

and PTO1 pins in the timer out flip-flop (TOUT flip-flop ) status.

The timer out flip-flop is inverted by the match signal sent from the comparator. When bit 3 of the timer/

event counter mode register (TM0, TM1) is set to 1, the timer out flip-flop is cleared to 0.

TOE0, TOE1, and timer out flip-flop are cleared to 0 by a RESET signal generation.

Figure 5-32. Timer/Event Counter Output Enable Flag Format

Address

FA2H

FAAH

TOE0

TOE1

Channel 0

Channel 1

Timer/event counter output enable flag (W)

Disabled.

Enabled.

5.5.2 8-bit timer/event counter mode operation

It is used as an 8-bit timer/event counter in this mode. It performs an 8-bit programmable interval timer

and event counter operation (channel 0 only).

(1) Register setting

The following three registers and one flag are used in the 8-bit timer/event counter mode.

• Timer/event counter mode register (TMn)

• Timer/event counter count register (Tn)

• Timer/event counter modulo register (TMODn)

• Timer/event counter output enable flag (TOEn)

(a) Timer/event counter mode register (TMn)

When the 8-bit timer/event counter mode is used, TMn must be set as shown in Figure 5-33 (For the

format of the TMn, see Figures 5-30 and 5-31).

The TMn is manipulated by an 8-bit manipulation instruction. Bit 3 is a timer start indication bit and

can be manipulated bit-wise and is automatically cleared to 0 when the timer starts.

The TMn is cleared to 00H when an internal reset signal is generated.

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CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS

Figure 5-33. Timer/Event Counter Mode Register Setup (1/2)

(a) In the case of timer/event counter (channel 0)

Address

FA0H

Symbol

TM0

TM06 TM05 TM04 TM03 TM02

Count pulse (CP) selection bit

TM06 TM05 TM04

Count pulse (CP)

TI0 rising edge

TI0 falling edge

/2¹⁰

/2⁸

/2⁶

/2⁴

Other than above

Not to be set

Timer start indication bit

TM03

When “1” is written into the bit, the counter and IRQT0 flag are cleared.

If bit 2 is set to “1”, count operation is started.

Operation mode

TM02

Count operation

Stop (retention of count contents)

Count operation

115

µPD750008 USER'S MANUAL

Figure 5-33. Timer/Event Counter Mode Register Setup (2/2)

(b) In the case of timer counter (channel 1)

Address

FA8H

Symbol

TM1

TM16 TM15 TM14 TM13 TM12

Count pulse (CP) selection bit

TM16 TM15 TM14

Count pulse (CP)

/2¹²

/2¹⁰

/2⁸

/2⁶

Not to be set

Other than above

Timer start indication bit

TM13

When “1” is written to the bit, the counter and IRQT1 flag are cleared.

If bit 2 is set to “1”, count operation is started.

Operation mode

TM12

Count operation

Stop (retention of count contents)

Count operation

(b) Timer/event counter output enable flag (TOEn)

The TOEn is manipulated by a bit manipulation instruction.

The TOEn is cleared to 0 by an internal reset signal.

Figure 5-34. Timer/Event Counter Output Enable Flag Setup

Address

FA2H

FAAH

TOE0

TOE1

Channel 0

Channel 1

Timer/event counter output enable flag (W)

Disabled (outputs the low-level signal).

Enabled.

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CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS

(2) Timer/event counter time setting

[Timer setup time] (cycle) is found by dividing [modulo register contents + 1] by [count pulse (CP)

frequency] selected by setting the mode register.

n+1

T (sec) =

= (n + 1) · (resolution)

T (sec) : Timer setup time (seconds)

(Hz) : Count pulse frequency (Hz)

: Modulo register content (n • 0)

Once the timer is set, interrupt request signal (IRQTn) is generated at the intervals set in the timer.

Table 5-6 lists the resolution and longest setup time (time when FFH is set in the modulo register) for each

count pulse to the timer/event counter.

Table 5-6. Resolution and Longest Setup Time

(a) When timer/event counter (channel 0)

Mode register

At 6.00 MHz

At 4.19 MHz

TM06

TM05

TM04

Resolution

Longest setup time

43.7 ms

Resolution

Longest setup time

62.5 ms

171 µs

42.7 µs

10.7 µs

2.67 µs

244 µs

61.0 µs

15.3 µs

3.82 µs

10.9 ms

2.73 ms

683 µs

15.6 ms

3.91 ms

977 µs

(b) When timer counter (channel 1)

Mode register

At 6.00 MHz

At 4.19 MHz

TM16

TM15

TM14

Resolution

685 µs

Longest setup time

175 ms

Resolution

980 µs

Longest setup time

250 ms

171 µs

42.7 µs

10.7 µs

43.7 ms

10.9 ms

2.73 ms

244 µs

61.0 µs

15.3 µs

62.5 ms

15.6 ms

3.91 ms

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µPD750008 USER'S MANUAL

(3) Timer/event counter operation

The timer/event counter operates as follows.

Figure 5-35 shows the configuration of the timer/event counter.

<1> The count pulse (CP) is selected by setting the mode register (TMn) and is input to the count register

(Tn).

<2> The Tn is compared with the modulo register (TMODn), and if they are equal, a match signal is

generated and the interrupt request flag (IRQTn) is set. At the same time, the timer out flip-flop (TOUT

flip-flop) is inverted.

Figure 5-36 is a timing chart of the timer/event counter.

The timer/event counter normally begins operation in the following procedure.

<1> Set a count in the TMODn.

<2> Set the operating mode, count pulse, and start indication in the TMn.

Caution Set a value other than 00H in the modulo register (TMODn).

When using the timer/event counter output pin (PTOn), set the dual function pin P2n as follows.

<1> Clear the output latch of P2n.

<2> Set port 2 to the output mode.

<3> Make a status wherein the internal pull-up resistor is not connected in port 2.

<4> Set the timer/event counter output enable flag (TOEn) to 1.

Figure 5-35. Configuration of Timer/Event Counter

INTTn

(IRQTn set signal)

Modulo register (TMODn)

TI0^Note

Match

TOUT flip-flop

PTOn

TOUT0

Comparator

MPX

Internal

clock

To serial interface^Note

Count register (Tn)

Clear

Note Channel 0 of the timer/event counter only.

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CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS

Figure 5-36. Count Operation Timing

Count pulse(CP)

Modulo register

(TMODn)

Count register

(Tn)

n–1

Match

Reset

TOUT F/F

Timer start indication

(4) Applications of the timer/event counter

(a) Timer/event counter is used as an interval timer that generates interrupts at intervals of 30 ms.

• The high-order four bits of the mode register are set to 0100B to select maximum set time 43.7 ms

(at f = 6.00 MHz).

• The low-order four bits of the mode register are set to 1100B.

• The modulo register is set to the following value:

30 ms/171 µs = 175.4

AFH

SEL

MOV

MB15

XA,#0AEH

TMOD0,XA

; Set the modulo register

XA,#01001100B

TM0,XA

; Set the mode register and start the timer

; Enable an interrupt

IET0

; Enable a timer interrupt

Remark In this application, the TI0 pin can be used as an input pin.

(b) An interrupt is caused when the number of pulses (active high) applied to the TI0 pin reaches

100.

• The high-order four bits of the mode register are set to 0000 to select the rising edge.

• The low-order four bits of the mode register are set to 1100B.

• The modulo register is set to 99 = 100 – 1.

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µPD750008 USER'S MANUAL

SEL

MOV

MB15

XA,#100 – 1

TMOD0,XA

XA,#00001100B

TM0,XA

; Set the modulo register

; Set the mode register

; Enable INTT0

IET0

5.5.3 Notes on Timer/Event Counter Applications

(1) Time error at the start of the timer

A maximum error of one count pulse (CP) cycle from a value calculated according to Section 5.5.2 (2)

occurs in a time period from the start of the timer (bit 3 of the TM0 is set) to the generation of a match

signal. This is because the count register T0 is cleared not in phase with the CP as shown in Figure

5-37.

Figure 5-37. Error at the Start of the Timer

Count register

Timer start

(2) Notes on the start of the timer

Usually, when the timer is started (bit 3 of the TM0 is set), the count register T0 and the interrupt request

flag (IRQT0) are cleared. However, when the timer is placed in the operation mode, and the setting of

IRQT0 and the start of the timer occur at the same time, IRQT0 may not be cleared. This causes no problem

if IRQT0 is used for a vectored interrupt. However, if IRQT0 is being tested, a problem arises because

IRQT0 is set even if the timer is started. Accordingly, in a situation where the timer is started on such

timing that IRQT0 may be set, the timer must be restarted after it is once stopped (bit 2 of the TM0 is cleared

to 0), or timer start operation must be performed twice.

Example The timer is started on such timing that IRQT0 may be set.

SEL

MB15

MOV

XA,#0

TM0,XA

XA,#4CH

TM0,XA

; Stop the timer

; Restart

SEL

MB15

TM0.3

SET1

; Restart

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CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS

(3) Error in reading the count register

The contents of the count register can be read using an 8-bit data memory manipulation instruction at

any time. During operation by such an instruction, all count pulse changes are held not to change the

count register. This means that if the count pulse signal source is applied to the TI0 input, as many count

pulses as corresponding to the time required to execute the instruction are cut. (When an internal clock

is used for the count pulse signal, this problem does not occur because of synchronization with the

instruction.)

Accordingly, in an attempt to read the contents of the count register with a count pulse signal applied to

TI0, the signal must have a pulse wide enough to avoid incorrect counting even if count pulses are cut.

That is, the contents of the count register are held by a read instruction for one machine cycle, so that

a signal applied to the TI0 pin must have a pulse wider than that.

Read instruction

External clock (TI0)

Instruction

Count register

K – 1

K + 1

K + 2

A change in a count

pulse is placed on hold

by the instruction.

A count pulse is canceled

by the instruction.

(4) Notes on changing the count pulse

When the count pulse is changed by rewriting the contents of the timer/event counter mode register, this

takes effect immediately after the rewrite instruction is executed.

Re-set instruction

Clock A specified

Clock B specified

Clock A specified

Clock A

Clock B

A combination of clocks used for changing count pulse signals can generate a spike (<1> or <2>) count

pulse as shown in the figure below. In this case, an incorrect count operation may occur, or the contents

of the count register may be destroyed. So when the count pulse is changed, bit 3 of the timer/event counter

mode register must be set to 1, and the timer must be restarted at the same time.

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µPD750008 USER'S MANUAL

Re-set instruction Re-set instruction

Clock A specified

Clock B specified

Clock A specified

Clock A

Clock B

<1>

<2>

(5) Operation after the modulo register is changed

The contents of the modulo register are changed when an 8-bit data memory manipulation instruction is

executed.

Modulo register

Re-set instruction

Count register

Match signal

If the new value of the modulo register is less than the value of the count register, the count register

continues count operation until it overflows, then it restarts count operation from 0. Accordingly, if the

new value (m) of the modulo register is less than the value (n) before it is changed, the timer must be

restarted after the contents of the modulo register are changed.

Modulo register

Count register

x – 1

255

n > x > m

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CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS

5.6 SERIAL INTERFACE

5.6.1 Serial Interface Functions

The µPD750008 contains a clock synchronous 8-bit serial interface, which has four modes.

The functions of the four modes are outlined below.

(1) Operation halt mode

This mode is used when serial transfer is not performed. This mode reduces power consumption.

(2) Three-wire serial I/O mode

In this mode, 8-bit data is transferred through three lines: Serial clock (SCK), serial output (SO), and serial

input (SI).

The three-wire serial I/O mode allows full-duplex transmission, so data transfer can be performed at higher

speed.

The user can choose 8-bit data transfer starting with the MSB or LSB, so devices starting with either the

MSB or LSB can be connected.

The three-wire serial I/O mode enables connections to be made with the 75XL series, 78K series, and

many other types of peripheral I/O devices.

(3) Two-wire serial I/O mode

In this mode, 8-bit data is transferred through two lines: Serial clock (SCK) and serial data bus (SB0 or

SB1). By controlling output levels on the two lines by software, communication with multiple devices is

enabled.

The output levels of SCK and SB0 (or SB1) can be controlled by software, so the user can match an

arbitrary transfer format. This means that a line that has been required for handshaking to connect multiple

lines can be eliminated for more efficient input/output port utilization.

(4) Serial bus interface (SBI) mode

In this mode, communication with multiple devices can be performed using two lines: Serial clock (SCK)

and serial data bus (SB0 or SB1).

This mode conforms to the NEC serial bus format.

In this mode, the transmitter can output, on the serial data bus, an address for selecting a device subject

to serial communication, commands directed to the remote device, and data.

The receiver can identify an address, commands, and data from received data by hardware. This function

enables more efficient input/output port utilization as in the case of the two-wire serial I/O mode. In

addition, this function can simplify the serial interface control portion of an application program.

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µPD750008 USER'S MANUAL

Figure 5-38. Example of the SBI System Configuration

VDD

Master CPU

Slave CPU

Serial clock

SCK

SB0, SB1

SCK

SB0, SB1

Address 1

Address

Command

Data

Slave IC

SCK

Address N

SB0, SB1

5.6.2 Configuration of Serial Interface

Figure 5-39 shows the block diagram of the serial interface.

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B S Y E

A C K E

A C K T

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µPD750008 USER'S MANUAL

(1) Serial operation mode register 0 (CSIM)

CSIM is an 8-bit register which specifies a serial interface operation mode, serial clock, wake-up function,

and so forth. (See (1) in Section 5.6.3 for details.)

(2) Serial bus interface control register (SBIC)

SBIC is an 8-bit register consisting of bits for controlling the serial bus and flags for indicating the states

of input data from the serial bus. SBIC is used mainly in the SBI mode. (See (2) in Section 5.6.3 for

details.)

(3) Shift register (SIO)

SIO is an 8-bit register which converts 8-bit serial data to parallel data, and 8-bit parallel data to serial

data. SIO performs transfer (shift) in phase with the serial clock. Transfers operations are controlled by

writing data to SIO. (See (3) in Section 5.6.3 for details.)

(4) SO latch

SO is a latch to hold the levels of pins SO and SB0, or SI and SB1, which can be controlled directly by

software. In the SBI mode, SO is set when the eighth clock of SCK has been output. (See(2) in Section

5.6.3 for details.)

(5) Serial clock selector

The serial clock selector selects the serial clock to be used.

(6) Serial clock counter

The serial clock counter counts the serial clock to be output or input during transfer, and checks whether

8-bit data has been transferred.

(7) Slave address register (SVA) and address comparator

• In the SBI mode

SVA is used when the µPD750008 is used as a slave device. A slave sets the number assigned to

it (slave address) in SVA. The master outputs a slave address to select a particular slave.

Two data values (a slave address output from the master and the value of SVA) are compared with

each other by the address comparator. If a match is found, the slave is selected.

• In the two-wire serial I/O mode or SBI mode

SVA detects an error when data is transferred with the µPD750008 operating as the master or a slave.

(See (4) in Section 5.6.3 for details.)

(8) INTCSI control circuit

The INTCSI control circuit controls interrupt request processing. The circuit issues an interrupt request

(INTCSI), and set an interrupt request flag (IRQCSI) in the following cases. (See Figure 6-1.)

• In the three-wire or two-wire serial I/O mode

An interrupt request is issued whenever eight serial clocks are counted.

• In the SBI mode

Note

When WUP7

= 0, an interrupt request is issued whenever eight serial clocks are counted. When

WUP = 1, an interrupt request is issued when values of SVA and SIO match after an address is

received.

Note WUP: Wake-up function specification bit (bit 5 of CSIM)

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CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS

(9) Serial clock control circuit

The serial clock control circuit controls the serial clock to be supplied to the shift register, or controls the

clock to be output to the SCK pin when the internal system clock is used.

(10) Busy/acknowledge output circuit and bus release/command/acknowledge detection circuit

The busy/acknowledge output circuit and bus release/command/acknowledge detection circuit output and

detect control signals generated in the SBI mode.

These circuits do not operate in the three-wire or two-wire serial I/O mode.

(11) P01 output latch

The P01 output latch generates serial clock by software after the eighth serial clock has been output.

When the RESET signal is entered, this latch is set to 1.

To select the internal system clock as the serial clock, set the P01 output latch to 1.

5.6.3 Register Functions

(1) Serial operation mode register (CSIM)

Figure 5-40 shows the format of serial operation mode register (CSIM).

CSIM is an 8-bit register which specifies a serial interface operation mode, serial clock, wake-up function,

and so forth.

CSIM is manipulated using an 8-bit memory manipulation instruction. The higher three bits can be

manipulated bit by bit. Each bit can be manipulated using its name.

Each bit may or may not allow read and/or write operation (seeFigure 5-40). Bit 6 allows bit test operation

only; any data written to this bit is invalid.

When the RESET signal is generated, all bits are cleared to 0.

Figure 5-40. Format of Serial Operation Mode Register (CSIM) (1/4)

Address

FE0H

Symbol

CSIM

CSIE

COI

WUP

CSIM4 CSIM3 CSIM2 CSIM1 CSIM0

Serial clock selection bit (W)

Serial interface operation mode selection bit (W)

Wake-up function specification bit (W)

Signal from address comparator (R)

Serial interface operation enable/disable specification bit (W)

Remarks 1. (R) : Read only

2. (W): Write only

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µPD750008 USER'S MANUAL

Figure 5-40. Format of Serial Operation Mode Register (CSIM) (2/4)

Serial interface operation enable/disable specification bit (W)

Shift register

operation

Serial clock

counter

IRQCSI

flag

SO/SB0 and

SI/SB1 pins

CSIE

Shift operation

disabled

Cleared

Held

Used only for port 0

Shift operation

enabled

Count operation

Can be set.

Used in each mode as well

as for port 0

Signal from address comparator (R)

Note

COI

Condition for being cleared (COI = 0)

Condition for being set (COI = 1)

When the data in the slave address

in the shift register

When the data in the slave address register

(SVA) matches the data in the shift

Note COI can be read only before serial transfer is started or after serial transfer is completed. An

undefined value may result during transfer.

COI data written by an 8-bit manipulation instruction is ignored.

Wake-up function specification bit (W)

WUP

Sets IRQCSI each time serial transfer is completed in each mode.

Used in the SBI mode only to set IRQCSI only when an address received after bus release

matches the data in the slave address register (wake-up state). SB0 or SB1 goes to high-

impedance state.

Caution When WUP = 1 is set during BUSY signal output, BUSY is not released. In the SBI mode,

the BUSY signal is output until the next falling edge of the serial clock (SCK) appears after

release of BUSY is directed. Before setting WUP = 1, be sure to confirm that pin SB0 (or

SB1) is high after releasing BUSY.

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CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS

Figure 5-40. Format of Serial Operation Mode Register (CSIM) (3/4)

Serial interface operation mode selection bit (W)

Operation

mode

Bit order of

shift register

SO pin

function

SI pin

function

CSIM4 CSIM3 CSIM2

3-wire

serial

I/O mode

SIO <—> XA

(Transfer start

with MSB)

SO/P02

(CMOS output)

SI/P03

(Input)

7-0

SIO

<—> XA

0-7

(Transfer starting

with LSB)

SBI mode

SIO

<—> XA

SB0/P02

P03 input

7-0

(Transfer starting (N-ch open-drain I/O)

with MSB)

P02 input

SB1/P03

(N-ch open-drain I/O)

2-wire

SIO

<—> XA

SB0/P02

P03 input

7-0

serial

I/O mode

(Transfer starting (N-ch open-drain I/O)

with MSB)

P02 input

SB1/P03

(N-ch open-drain I/O)

Remark x: Don’t care

Serial clock selection bit (W)

CSIM1 CSIM0

Serial clock

SCK pin mode

3-wire serial I/O mode

SBI mode

2-wire serial I/O mode

Input clock externally applied to SCK pin

Input

Timer/event counter output (TOUT0)

Output

f /2 (375 kHz: at 6.00 MHz,

f /2 (93.8 kHz: at 6.00 MHz,

262 kHz: at 4.19 MHz)

65.47 kHz: at 4.19 MHz)

f /2 (750 kHz: at 6.00 MHz,

524 kHz: at 4.19 MHz)

Remarks 1. Each mode can be selected using CSIE, CSIM3, and CSIM2.

CSIE

CSIM3

CSIM2

Operation mode

Operation halt mode

Three-wire serial I/O mode

SBI mode

Two-wire serial I/O mode

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µPD750008 USER'S MANUAL

Figure 5-40. Format of Serial Operation Mode Register (CSIM) (4/4)

Remarks 2. The P01/SCK pin assumes any of the following states according to the state of

CSIE, CSIM1, and CSIM0:

CSIE

CSIM1

CSIM0

P01/SCK pin state

Input port

High impedance

High level output

Serial clock output (High level output)

3. When clearing CSIE during serial transfer, use the following procedure:

<1> Disable interrupts by clearing the interrupt enable flag (IECSI).

<2> Clear CSIE.

<3> Clear the interrupt request flag (IRQCSI).

Examples 1. f /2 is selected as the serial clock, serial interrupt IRQCSI, is generated each

time serial transfer is completed, and serial transfer is performed in the SBI

mode with the SB0 pin used as the serial data bus.

SEL

MB15

; or CLR1 MBE

MOV XA,#10001010B

MOV CSIM,XA

; CSIM <– 10001010B

2. Serial transfer dependent on the contents of CSIM is enabled.

SEL MB15 ; or CLR1 MBE

SET1 CSIE

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CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS

(2) Serial bus interface control register (SBIC)

Figure 5-41 shows the format of the serial bus interface control register (SBIC).

SBIC is an 8-bit register consisting of bits for controlling the serial bus and flags for indicating the states

of input data from the serial bus. SBIC is used mainly in the SBI mode.

SBIC is manipulated using a bit manipulation instruction. SBIC cannot be manipulated using a 4-bit or

8-bit memory manipulation instruction.

Each bit may or may not allow read and/or write operation (Figure 5-41).

When the RESET signal is generated, all bits are cleared to 0.

Caution Only the following bits can be used in the three-wire and two-wire serial I/O modes:

• Bus release trigger bit (RELT): Sets the SO latch.

• Command trigger bit (CMDT): Clears the SO latch

Figure 5-41. Format of Serial Bus Interface Control Register (SBIC) (1/3)

Address

FE2H

Symbol

BSYE

ACKD

ACKE

ACKT CMDD RELD

CMDT

RELT

SBIC

Bus release trigger bit (W)

Command trigger bit (W)

Bus release detection flag (R)

Command detection flag (R)

Acknowledge trigger bit (W)

Acknowledge enable bit (R/W)

Acknowledge detection flag (R)

Busy enable bit (R/W)

Remarks 1. (R:

Read only

Write only

2. (W):

3. (R/W): Read/write

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µPD750008 USER'S MANUAL

Figure 5-41. Format of Serial Bus Interface Control Register (SBIC) (2/3)

Busy enable bit (R/W)

BSYE

<1> The busy signal is automatically disabled.

<2> Busy signal output is stopped in phase with the falling edge of SCK immediately after

clear instruction execution.

The busy signal is output after the acknowledge signal in phase with the falling edge of SCK.

Acknowledge detection flag (R)

ACKD

Condition for being cleared (ACKD = 0)

Condition for being set (ACKD = 1)

<1> The transfer operation is started.

<2> The RESET signal is generated.

The acknowledge signal (ACK) is detected

(in phase with the rising edge of SCK).

Acknowledge enable bit (R/W)

ACKE

Disables automatic output of the acknowledge signal (ACK). (Output by ACKT is possible.)

When set before transfer

When set after transfer

ACK is output in phase with the 9th clock of SCK.

ACK is output in phase with SCK immediately following

the set instruction execution.

Acknowledge trigger bit (W)

ACKT

When set after transfer, ACK is output in phase with the next SCK. After ACK signal output,

this bit is automatically cleared to 0.

Cautions 1. Never set ACKT before or during serial transfer.

2. ACKT cannot be cleared by software.

3. Before setting ACKT, set ACKE = 0.

Command detection flag (R)

CMDD

Condition for being cleared (CMDD = 0)

Condition for being set (CMDD = 1)

<1> The transfer start instruction is executed.

<2> The bus release signal (REL)

<3> The RESET signal is generated.

<4> CSIE = 0 (Figure 5-40)

The command signal (CMD) is detected.

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CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS

Figure 5-41. Format of Serial Bus Interface Control Register (SBIC) (3/3)

Bus release detection flag (R)

RELD

Condition for being cleared (RELD = 0)

Condition for being set (RELD = 1)

<1> The transfer start instruction is executed.

<2> The RESET signal is generated.

<3> CSIE = 0 (Figure 5-40)

The bus release signal (REL) is detected.

<4> SVA does not match SIO when an address is

received.

Command trigger bit (W)

CMDT

Control bit for command signal (CMD) trigger output. By setting CMDT = 1, the SO latch is

cleared. Then the CMDT bit is automatically cleared to 0.

Caution Never clear SB0 (or SB1) during serial transfer. Be sure to clear SB0 (or SB1) before or

after serial transfer

Bus release trigger bit (W)

RELT

Control bit for bus release signal (REL) trigger output.

By setting RELT = 1, the SO latch is set to 1. Then the RELT bit is automatically cleared to 0.

Caution Never clear SB0 (or SB1) during serial transfer. Be sure to clear SB0 (or SB1) before or

after serial transfer.

Examples 1. A command signal is output.

SEL

MB15

; or CLR1 MBE

SET1 CMDT

2. RELD and CMDD are tested to identify the types of received data and the types of processing

accordingly. By setting WUP = 1, this interrupt routine is processed only when an address

match is found.

SEL

SKF

MB15

RELD

!ADRS

CMDD

!DATA

!CMD

; RELD test

; CMDD test

SKT

CMD: ...................... ; Command analysis

DATA:..................... ; Data processing

ADRS: .................... ; Address decode

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µPD750008 USER'S MANUAL

(3) Shift register (SIO)

Figure 5-42 shows the configuration of peripheral hardware of shift register. SIO is an 8-bit register which

performs parallel-serial conversion and serial transfer (shift) operation in phase with the serial clock.

Serial transfer is started by writing data to SIO.

In transmission, data written to SIO is output on the serial output (SO) or serial data bus (SB0 or SB1).

In receive operation, data is read from the serial input (SI) or SB0 or SB1 into SIO.

Data can be read from or written to SIO by using an 8-bit manipulation instruction.

When the RESET signal is generated during operation, the value of SIO is undefined. When the RESET

signal is generated in the standby mode, the value of SIO is preserved.

Shift operation is stopped after 8-bit send or receive operation is completed.

Figure 5-42. Peripheral Hardware of Shift Register

Address

comparator

Internal bus

RELT

CMDT

Shift register

SO latch

SET

CLR

CLK

CSIM

Shift clock

BUSY/ACK

N-ch open-drain output

The timing for reading SIO and start of serial transfer (writing to SIO) is as follows:

• When the serial interface operation enable/disable bit (CSIE) = 1. However, the case where CSIE

is set to 1 after data is written to the shift register is excluded.

• When the serial clock is masked after 8-bit serial transfer

• SCK is high.

When reading from or writing to SIO, make sure that SCK is high.

In the two-wire serial I/O mode and SBI mode, the pins specified for the data bus are used for both input

and output. Because the configuration of output pins is N-ch open-drain, write FFH in SIO for devices

that are to receive data.

(4) Slave address register (SVA)

The slave address register (SVA) is an 8-bit register for a slave to set its slave address (number assigned

to it).

SVA is manipulated using an 8-bit manipulation instruction.

When the RESET signal is generated, the value of SVA is undefined. However, the value of SVA is

preserved when the RESET signal is generated in the standby mode.

SVA has the following two functions:

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CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS

(a) Slave address detection

[In the SBI mode]

SVA is used when the µPD750008 is connected as a slave device to the serial bus. SVA is an 8-

bit register for a slave to set its slave address (number assigned to it). The master outputs a slave

address to the connected slaves to select a particular slave. Two data values (a slave address output

from the master and the value of SVA) are compared with each other by the address comparator. If

a match is found, the slave is selected.

At this time, bit 6 (COI) of serial operation mode register (CSIM) is set to 1.

If a match with received address data is not found, the bus release detection flag (RELD) is cleared

to 0. When WUP = 1 (wake-up state detection), IRQCSI is set only when a match is found. With this

interrupt request, the µPD750008 can be informed of a communication request transmitted from the

master.

(b) Error detection

[In the two-wire serial I/O mode or SBI mode]

SVA detects an error when addresses, commands, or data is transferred with the µPD750008

operating as the master or when data is transferred with the µPD750008 operating as a slave. (For

details, see (6) in Section 5.6.6 and (8) in Section 5.6.7.)

5.6.4 Operation Halt Mode

The operation halt mode is used when serial transfer is not performed. This mode reduces power

consumption.

The shift register does not perform shift operation in this mode, so the shift register can be used as a normal

8-bit register.

When the RESET signal is entered, the operation halt mode is set. The P02/SO/SB0 pin and P03/SI/SBI

pin function as input-only port pins. The P01/SCK pin can be used as an input port pin by setting the serial

operation mode register.

(1) Register setting

To set the operation halt mode, manipulate serial operation mode register (CSIM). (For details on CSIM

format, see (1) in Section 5.6.3.)

CSIM is manipulated with an 8-bit manipulation instruction. Only the CSIE bit of CSIM can be

independently manipulated. CSIM can also be manipulated using the name of each bit.

When the RESET signal is entered, CSIM is set to 00H.

In the figure below, hatched portions indicate bits used in the operation halt mode.

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µPD750008 USER'S MANUAL

Address

FE0H

CSIE COI WUP CSIM4 CSIM3 CSIM2 CSIM1 CSIM0 CSIM

Serial clock selection bit (W)^Note

Serial interface operation mode selection bit (W)

Wake-up function specification bit (W)

Match signal from address comparator (R)

Serial interface operation enable/disable specification bit (W)

Note The status of the P01/SCK pin is selectable.

Remark (R): Read only

(W): Write only

Serial interface operation enable/disable specification bit (W)

Shift register operation

Shift operation disabled

Serial clock counter IRQCSI flag

Cleared Held

SO/SB0 and SI/SB1 pins

Used only for port 0

CSIE0

Serial clock selection bit (W)

The P01/SCK pin assumes the following state according to the setting of CSIM0 and CSIM1:

CSIM1 CSIM0

P01/SCK pin state

High impedance

High level output

When clearing CSIE during serial transfer, use the following procedure:

<1> Disable interrupts by clearing the interrupt enable flag (IECSI).

<2> Clear CSIE.

<3> Clear the interrupt request flag (IRQCSI).

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CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS

5.6.5 Three-Wire Serial I/O Mode Operations

The three-wire serial I/O mode is compatible with other modes used in the 75 XL series, 75X series,

µPD7500 series, and 87AD series.

Communication is performed using three lines:

Serial clock (SCK), serial output (SO), and serial input (SI).

Figure 5-43. Example of Three-Wire Serial I/O System Configuration

3-wire serial I/O

Master CPU

Slave CPU

µPD750008

SCK

Remark The µPD750008 can also be used as a slave CPU.

(1) Register setting

To set the three-wire serial I/O mode, manipulate the following two registers:

• Serial operation mode register (CSIM)

• Serial bus interface control register (SBIC)

(a) Serial operation mode register (CSIM)

To use the three-wire serial I/O mode, set CSIM as shown below. (For details on CSIM format, see

(1) in Section 5.6.3.)

CSIM0 is manipulated using an 8-bit manipulation instruction. Bits 7, 6, and 5 of CSIM can be

manipulated bit by bit.

When the RESET signal is input, CSIM is set to 00H.

In the figure below, hatched portions indicate the bits used in the three-wire serial I/O mode.

Address

FE0H

CSIE COI WUP CSIM4 CSIM3 CSIM2 CSIM1 CSIM0 CSIM

Serial clock selection bit (W)

Serial interface operation mode selection bit (W)

Wake-up function specification bit (W)

Match signal from address comparator (R)

Serial interface operation enable/disable specification bit (W)

Remark (R): Read only

(W): Write only

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µPD750008 USER'S MANUAL

Serial interface operation enable/disable specification bit (W)

Shift register operation

Shift operation enabled

Serial clock counter IRQCSI flag

SO/SB0 and SI/SB1 pins

CSIE

Count operation Can be set Used in each mode

as well as for port 0

Signal from address comparator (R)

Note

COI

Condition for being cleared (COI = 0)

Condition for being set (COI = 1)

When the slave address register (SVA)

does not match the data of the shift register

When the slave address register (SVA)

matches the data of the shift register

Note COI can be read only before serial transfer is started or after serial transfer is completed. An

undefined value may be read during transfer. COI data written by an 8-bit manipulation instruction

is ignored.

Wake-up function specification bit (W)

WUP

Sets IRQCSI each time serial transfer is completed.

Serial interface operation mode selection bit (W)

CSIM4 CSIM3

CSIM2

Shift register sequence

<—> XA

SO pin function

SI pin function

SI/P03

SIO

SO/P02

7-0

(Transfer starting with MSB)

(CMOS output)

(Input)

SIO <—> XA

0-7

(Transfer starting with LSB)

Remark x: Don’t care

Serial clock selection bit (W)

CSIM1 CSIM0

Serial clock

SCK pin mode

External clock applied to SCK pin

Timer/event counter output (TOUT0)

Input

Output

Note

f /2 (262 kHz)

f /2 (524 kHz)

Note ( ): fx = 4.19 MHz

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CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS

(b) Serial bus interface control register (SBIC)

To use the three-wire serial I/O mode, set SBIC as shown below. (For details on SBIC format, see

(2) in Section 5.6.3.)

SBIC is manipulated using a bit memory manipulation instruction.

When the RESET signal is input, SBIC is set to 00H.

In the figure below, hatched portions indicate the bits used in the three-wire serial I/O mode.

Address

FE2H

BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT SBIC

Do not use these bits in the

three-wire serial I/O mode.

Bus release trigger bit (W)

Command trigger bit (W)

Remark (W): Write only

Command trigger bit (W)

CMDT

Control bit for command signal (CMD) trigger output. By setting CMDT = 1, the SO latch is

cleared. Then the CMDT bit is automatically cleared.

Bus release trigger bit (W)

RELT

Control bit for bus release signal (REL) trigger output.

By setting RELT = 1, the SO latch is set to 1. Then the RELT bit automatically cleared to 0.

Caution Never use bits other than RELT and CMDT in the three-wire serial I/O mode.

(2) Communication operation

The three-wire serial I/O mode transfers data, with eight bits as one block. Data is transferred bit by bit

in phase with the serial clock.

The shift register performs shift operation on the falling edge of the serial clock (SCK). Send data is latched

on the SO latch, and is output on the SO pin. Receive data applied to the SI pin is latched in the shift

When eight bits have been transferred, shift register operation automatically terminates setting the

interrupt request flag (IRQCSI).

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µPD750008 USER'S MANUAL

Figure 5-44. Timing of Three-Wire Serial I/O Mode

SCK

DI7

DI6

DI5

DI4

DI3

DI2

DI1

DI0

DO7

DO6

DO5

DO4

DO3

DO2

DO1

DO0

IRQCSI

Completion of transfer

Transfer operation is started in phase with falling edge of SCK.

Execution of instruction that writes data to SIO (Transfer start request)

The SO pin becomes a CMOS output and outputs the state of the SO latch. So the output state of the

SO pin can be manipulated by setting the RELT bit and CMDT bit.

However, this manipulation must not be performed during serial transfer.

The output level of the SCK pin can be controlled by manipulating the P01 output latch in the output mode

(internal system clock mode). (See Section 5.6.8.)

(3) Serial clock selection

To select the serial clock, manipulate bits 0 and 1 of serial operation mode register 0 (CSIM). The serial

clock can be selected out of the following four clocks:

Table 5-7. Serial Clock Selection and Application (In the Three-Wire Serial I/O Mode)

Mode register

Serial clock

Masking of

Timing for shift register R/W and

start of serial transfer

Application

CSIM

Source

serial clock

External

SCK

Automatically

masked when

8-bit data

transfer is

completed

<1> In the operation halt mode

(CSIE = 0)

<2> When the serial clock is

masked after 8-bit transfer

<3> When SCK is high

Slave CPU

TOUT

flip-flop

Half-duplex asyn

chronous transfer

(software control)

f /2

Middle-speed

serial transfer

f /2

High-speed serial

transfer

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CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS

(4) Signals

Figure 5-45 shows operations of RELT and CMDT.

Figure 5-45. Operations of RELT and CMDT

SO latch

RELT

CMDT

(5) Switching between MSB and LSB as the first transfer bit

The three-wire serial I/O mode has a function that can switch between the MSB and LSB as the first bit

of transfer.

Figure 5-46 shows the configuration of shift register (SIO) and internal bus. As shown in Figure 5-46,

read or write operation can be performed by switching between the MSB and LSB.

This switching can be specified using bit 2 of serial operation mode register (CSIM).

Figure 5-46. Transfer Bit Switching Circuit

Internal bus

LSB first

Read/write gate

MSB first

SO latch

Shift resister (SIO)

SCK

The first bit is switched by changing the order of data bits written to shift register (SIO). The shift operation

order of SIO is always the same.

Accordingly, the first bit must be switched between the MSB and LSB before writing data to the shift

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µPD750008 USER'S MANUAL

(6) Transfer start

Serial transfer is started by writing transfer data into shift register (SIO), provided that the following two

conditions are satisfied:

• The serial interface operation enable/disable specification bit (CSIE) is set to 1.

• The internal serial clock is not operating after 8-bit serial transfer, or SCK is high.

Caution Setting CSIE after writing data to the shift register does not start transfer.

When eight bits have been transferred, serial transfer automatically terminates setting the interrupt request

flag (IRQCSI).

Example To transfer the RAM data specified with the HL register to SIO, load the SIO data to the

accumulator and start serial transfer:

MOV XA,@HL

SEL MB15

; Fetch transmit data from RAM

; or CLR1 MBE

XCH XA,SIO

; Exchange transmit data and receive data, and start transfer

(7) Application of the three-wire serial I/O mode

(a) Data is transferred starting with the MSB on a transfer clock of 262 kHz (during 4.19-MHz

operation). (Master operation)

CLR1 MBE

MOV XA,#10000010B

MOV CSIM,XA

MOV XA,TDATA

MOV SIO,XA

; Set transfer mode

; TDATA is transfer data storage address

; Set transfer data, and start transfer

Caution A second or subsequent transfer can be started by setting data in SIO (MOV SIO,XA

or XCH XA,SIO).

µPD750008

µPD7225G (LCD controller/driver), etc.

SCK

SO/SB0

In this case, the SI/SBI pin on the µPD750008 can be used as an input.

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CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS

(b) Data is transmitted and received starting with the LSB on an external clock (slave operation).

(In this case, the function of inverting the MSB/LSB is used for shift register read/write operation.)

Other microcomputers

SCK

µPD750008

P01/SCK

SI/SB1

SO/SB0

Main routine

CLR1

MOV

MBE

XA,#84H

CSIM,XA

XA,TDATA

SIO,XA

; Serial operation halt, MSB/LSB invert mode, external clock

; Set transfer data, and start transfer

IECSI

Interrupt routine (MBE = 0)

MOV

XCH

MOV

RETI

XA,TDATA

XA,SIO

; Start to transfer receive data and transmit data

; Save receive data

RDATA,XA

4.19 MHz operation).

µPD750008 (master)

SCK

µPD75206, etc.

SCK

SO/SB0

SI/SB1

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µPD750008 USER'S MANUAL

<Sample program> (master side):

CLR1

MOV

MBE

XA,#10000011B

CSIM,XA

XA,TDATA

SIO,XA

; Set transfer mode

; Set transfer data, and start transfer

LOOP : SKTCLR

IRQCSI

LOOP

; Test IRQCSI

MOV

XA,SIO

; Read in receive data

5.6.6 Two-Wire Serial I/O Mode

The two-wire serial I/O mode can be made compatible with any communication format by programming.

In this mode, communication is basically performed using two lines: Serial clock (SCK) and serial data input/

output (SB0 or SB1).

Figure 5-47. Example of Two-Wire Serial I/O System Configuration

2-wire serial I/O

Master CPU

Slave CPU

(µPD750008)

SCK

VDD

SB0, SB1

Remark The µPD750008 can also be used as a slave CPU.

(1) Register setting

To set the two-wire serial I/O mode, manipulate the following two registers:

• Serial operation mode register (CSIM)

• Serial bus interface control register (SBIC)

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CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS

(a) Serial operation mode register (CSIM)

To use the two-wire serial I/O mode, set CSIM as shown below. (For details on CSIM format, see

(1) in Section 5.6.3.)

CSIM is manipulated using an 8-bit manipulation instruction. Bits 7, 6, and 5 of CSIM can be

manipulated bit by bit.

When the RESET signal is input, CSIM is set to 00H.

In the figure below, hatched portions indicate the bits used in the two-wire serial I/O mode.

Address

FE0H

CSIE COI WUP CSIM4 CSIM3 CSIM2 CSIM1 CSIM0 CSIM

Serial clock selection bit (W)

Serial interface operation mode selection bit (W)

Wake-up function specification bit (W)

Match signal from address comparator (R)

Serial interface operation enable/disable specification bit (W)

Remark (R: Read only

(W): Write only

Serial interface operation enable/disable specification bit (W)

Shift register operation

Shift operation enabled

Serial clock counter IRQCSI flag

SO/SB0 and SI/SB1 pins

CSIE

Count operation Can be set Used in each mode

as well as for port 0

Signal from address comparator (R)

Note

COI

Condition for being cleared (COI = 0)

Condition for being set (COI = 1)

When the slave address register (SVA)

does not match the data of the shift register

When the slave address register (SVA)

matches the data of the shift register

Note COI can be read only before serial transfer is started or after serial transfer is completed. An

undefined value may be read during transfer. COI data written by an 8-bit manipulation instruction

is ignored.

Wake-up function specification bit (W)

WUP

Sets IRQCSI each time serial transfer is completed.

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µPD750008 USER'S MANUAL

Serial interface operation mode selection bit (W)

CSIM4 CSIM3

CSIM2

Shift register sequence

<—> XA

SO pin function

SI pin function

P03 input

SIO

SB0/P02 (N-ch

open-drain I/O)

7-0

(Transfer starting with MSB)

P02 input

SB1/P03 (N-ch

open-drain I/O)

Serial clock selection bit (W)

CSIM1 CSIM0

Serial clock

External clock applied to SCK pin

SCK pin mode

Input

Output

Timer/event counter output (TOUT0)

f /2 (65.5 kHz)

Remark The value at 4.19 MHz is indicated in parentheses.

(b) Serial bus interface control register (SBIC)

To use the two-wire serial I/O mode, set SBIC as shown below. (For details on SBIC format, see (2)

in Section 5.6.3.)

SBIC is manipulated using a bit manipulation instruction.

When the RESET signal is input, SBIC is set to 00H.

In the figure below, the hatched portions indicate the bits used in the two-wire serial I/O mode.

Address

FE2H

BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT SBIC

Do not use these bits in the

two-wire serial I/O mode.

Bus release trigger bit (W)

Command trigger bit (W)

Remark (W): Write only

Command trigger bit (W)

CMDT

Control bit for command signal (CMD) trigger output. By setting CMDT = 1, the SO latch is

cleared. Then the CMDT bit is automatically cleared.

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CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS

Bus release trigger bit (W)

RELT

Control bit for bus release signal (REL) trigger output.

By setting RELT = 1, the SO latch is set to 1. Then the RELT bit automatically cleared to 0.

Caution Never use bits other than RELT and CMDT in the two-wire serial I/O mode.

(2) Communication operation

The two-wire serial I/O mode transfers data, with eight bits as one block. Data is transferred bit by bit

in phase with the serial clock.

The shift register performs shift operation on the falling edge of the serial clock (SCK). Transmit data is

latched on the SO latch, and is output on the SB0/P02 pin or SB1/P03 pin starting with the MSB. Receive

data applied to the SB0 pin or SB1 pin is latched in the shift register on the rising edge of SCK.

When eight bits have been transferred, shift register operation automatically terminates setting the

interrupt request flag (IRQCSI).

Figure 5-48. Timing of Two-Wire Serial I/O Mode

SCK

SB0, SB1

IRQCSI

Completion of transfer

Transfer operation is started in phase with falling edge of SCK.

Execution of instruction that writes date to SIO (Transfer start request)

The SB0 (or SB1) pin becomes an N-ch open-drain I/O when specified as the serial data bus, so the voltage

level on that pin must be pulled up externally.

The state of the SO latch is output on the SB0 (or SB1) pin, so the SB0 (or SB1) pin output states can

be controlled by setting the RELT or CMDT bit.

However, this operation must not be performed during serial transfer.

The output state of the SCK pin can be controlled by manipulating the P01 output latch in the output mode

(internal system clock mode). (See Section 5.6.8.)

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(3) Serial clock selection

To select the serial clock, manipulate bits 0 and 1 of serial operation mode register (CSIM). The serial

clock can be selected out of the following four clocks:

Table 5-8. Serial Clock Selection and Application (In the Two-Wire Serial I/O Mode)

Mode register

Serial clock

Masking of

Timing for shift register R/W and

start of serial transfer

Application

CSIM

Source

serial clock

External

SCK

Automatically

masked when

8-bit data

transfer is

completed

<1> In the operation halt mode

(CSIE = 0)

<2> When the serial clock is

masked after 8-bit transfer

<3> When SCK is high

Slave CPU

TOUT

flip-flop

Arbitrary-speed

serial transfer

f /2

Low-speed

serial transfer

(4) Signals

Figure 5-49 shows operations of RELT and CMDT.

Figure 5-49. Operations of RELT and CMDT

SO latch

RELT

CMDT

(5) Transfer start

Serial transfer starts by writing transfer data into shift register (SIO), provided that the following two

conditions are satisfied:

• The serial interface operation enable/disable specification bit (CSIE) is set to 1.

• The internal serial clock is not operating after 8-bit serial transfer, or SCK is high.

Cautions 1. Setting CSIE to 1 after writing data to the shift register does not start transfer.

2. When data is received, the N-ch transistor must be turned off, so FFH must be

written to SIO beforehand.

When eight bits have been transferred, serial transfer automatically terminates setting the interrupt

request flag (IRQCSI).

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CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS

(6) Error detection

In the two-wire serial I/O mode, the state of serial bus SB0 or SB1 being used for communication is loaded

into the shift register (SIO) of the transmitting device. So a transmission error can be detected by the

methods described below.

(a) Comparing SIO data before start of transmission with SIO data after start of transmission

With this method, the occurrence of a transmission error is assumed when two SIO values disagree

with each other.

(b) Using the slave address register (SVA)

Transmit data is set in SVA as well before the data is transmitted. On completion of transmission,

the COI bit (match signal from the address comparator) of serial operation mode register (CSIM) is

tested. If the result is 1, the transmission is regarded as successful. If the result is 0, the occurrence

of a transmission error is assumed.

(7) Application of two-wire serial I/O mode

A serial bus is configured, and multiple devices are connected to it.

Example A system is configured with a µPD750008 as the master to which a µPD75104, µPD75402A,

and µPD7225G are connected as slaves.

VDD

µPD750008 (master)

µPD7225G

Port

SCK

SO/SB0

µPD75402A

SCK

µPD75104

SCK

To configure the bus as shown above, connect the SI pin and SO pin. Then, writes FFH to the shift register

to make the SO pin high except when serial data is output, and free the bus by setting off the output buffer.

The SO pin of the µPD75402A cannot go into a high-impedance state, so that a transistor must be

connected as shown in the figure to make open collector output appear on the pin. When data is input,

00H must be set beforehand in the shift register to set the transistor off.

The timing of data output by each microcomputer must be predetermined.

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µPD750008 USER'S MANUAL

The µPD750008, which is the master microcomputer, outputs a serial clock, and all slave microcomputers

operate with an external clock.

5.6.7 SBI Mode Operation

The SBI (serial bus interface) is a high-speed serial interface that conforms to the NEC serial bus format.

To allow communication with multiple devices on a single-master and high-speed serial bus using two signal

lines, the SBI has a bus configuration function added to the clock synchronous serial I/O method. So the SBI

can reduce ports and wires on boards when multiple microcomputers and peripheral ICs are used to configure

a serial bus.

The master can output, on the serial data bus, an address for selecting a device subject to serial

communication, commands directed to the remote device, and data. A slave can identify an address,

commands, and data from received data by hardware. This function simplifies the serial interface control

portion of an application program.

The SBI function is available with devices such as the 75X series, 75XL series, and 78K series 8-/16-bit

single chip microcomputers.

Figure 5-50 is an example of the SBI system configuration when the CPU with a serial interface conforming

to SBI or peripheral ICs are used.

Figure 5-50. Example of SBI System Configuration

VDD

Master CPU

Slave CPU

µPD750008

SB0, SB1

SCK

SB0, SB1

SCK

Address 1

Slave CPU

SB0, SB1

SCK

Address 2

Slave IC

SB0, SB1

SCK

Address N

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CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS

Cautions 1. In the SBI mode, the serial data bus pin SB0 (or SB1) is an open-drain output. So

the serial data bus line is placed in the wired OR state. A pull-up resistor is

required for the serial data bus line.

2. To switch between the master and slave, a pull-up resistor is required also for the

serial clock line (SCK) because SCK input/output switching is performed between

the master and slave asynchronously.

(1) SBI functions

Conventional serial I/O methods provide only data transfer functions. Therefore, many ports and wires

are required to identify chip select signals, commands, and data, and to detect busy states, when the serial

bus is configured with multiple devices. Also, these processes are too burdensome to be controlled by

software.

The SBI method can configure a serial bus with two signal lines: Serial clock SCK and serial data bus

(SB0 or SB1). For this reason, the number of ports on a microcomputer can be reduced and the wiring

on a circuit board can be simplified.

SBI functions are described below.

(a) Address/command/data identification function

Serial data is classified into three types: Address, command, and data.

(b) Address-based chip select function

The master selects a chip for a slave by address transfer.

A slave can easily check address reception (for chip select identification) with the wake-up function.

This function can be set or released by software.

When the wake-up function is set, an interrupt (IRQCSI) is generated when a match address is

received. For this reason, in communication with multiple devices, a CPU other than a selected slave

can operate independently of serial communication.

(d) Acknowledge signal (ACK) control function

The acknowledge signal, which is used to confirm the reception of serial data, can be controlled.

(e) Busy signal (BUSY) control function

The busy signal, which is used to post the busy state of a slave, can be controlled.

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µPD750008 USER'S MANUAL

(2) SBI definition

The format of serial data and signal used in the SBI mode are described below.

Serial data to be transferred in the SBI mode is classified into three types: Address, command, and data.

Serial data forms one frame as shown below.

Figure 5-51 is a timing chart for transferring address, command, and data.

Figure 5-51. Timing of SBI Transfer

Address transfer

SCK

SB0, SB1

ACK

BUSY

Bus release signal

Command transfer

Command signal

SCK

SB0, SB1

C0 ACK

BUSY

READY

Data transfer

SCK

D0 ACK

BUSY

READY

SB0, SB1

The bus release signal and command signal are output by the master. BUSY is output by a slave. ACK

is output by either the master or a slave. (Normally, the device which received 8-bit data outputs ACK.)

The master continues to output the serial clock from when 8-bit data transfer starts to when BUSY is

released.

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CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS

(a) Bus release signal (REL)

When the SCK line is high (the serial clock is not output), the SB0 (or SB1) line changes from low

to high. This signal is called the bus release signal, and is output by the master.

Figure 5-52. Bus Release Signal

"H"

SCK

SB0, SB1

This signal indicates that the master is to send an address to a slave. Slaves contain hardware to

detect the bus release signal.

(b) Command signal (CMD)

When the SCK line is high (the serial clock is not output), the SB0 (or SB1) line changes from high

to low. This signal is called the command signal, which is output by the master.

Figure 5-53. Command Signal

SCK

"H"

SB0, SB1

Slaves contain hardware to detect the command signal.

An address is 8-bit data and is output by the master to connected slaves to select a particular slave.

Figure 5-54. Address

SCK

SB0, SB1

A6 A5 A4 A3 A2 A1 A0

Address

Bus release signal

Command signal

The 8-bit data following the bus release signal or command signal is defined as an address. A slave

detects the condition for the addresses by hardware, and checks whether the 8-bit data matches the

number assigned to the slave (slave address). If the 8-bit data matches the slave address, that slave

is selected. The selected slave continues to communicate with the master until disconnection is

directed by the master.

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µPD750008 USER'S MANUAL

Figure 5-55. Slave Selection Using an Address

Master

Slave 1

Slave 2

Slave 3

Slave 4

Not selected

Selected

Transmits address for

slave 2

Not selected

(d) Command and data

The master sends commands to the slave selected by sending an address. The master also transfers

data to or from the slave.

Figure 5-56. Command

SCK

SB0, SB1

C7 C6 C5 C4 C3 C2 C1 C0

Command

Command signal

Figure 5-57. Data

SCK

SB0, SB1

D7 D6 D5 D4 D3 D2 D1 D0

Data

The 8-bit data following the command signal is defined as a command. The 8-bit data without the

command signal is defined as data. The usage of commands or data can be selected optionally

according to the communication specifications.

(e) Acknowledge signal (ACK)

The acknowledge signal confirms the reception of serial data between the transmitter and the receiver.

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CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS

Figure 5-58. Acknowledge Signal

[When output in phase with the 11th clock of SCK]

SCK

SB0, SB1

ACK

[When output in phase with the 9th clock of SCK]

SCK

ACK

SB0, SB1

The acknowledge signal is a one-shot pulse output in phase with the falling edge of SCK after 8-bit

data transfer. This signal may be synchronized with any clock of SCK.

The transmitter checks if the receiver returns the acknowledge signal after 8-bit data transfer. If the

acknowledge signal is not returned after a specified period of time, the transmitter can assume that

the reception failed.

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µPD750008 USER'S MANUAL

(f) Busy signal (BUSY) and ready signal (READY)

The busy signal informs the master that a slave is getting ready for data transfer.

The ready signal informs the master that a slave is ready for data transfer.

Figure 5-59. Busy and Ready Signals

SCK

ACK

SB0, SB1

BUSY

READY

In the SBI mode, a slave notifies the master of the busy state by changing SB0 (or SB1) from high

to low.

The busy signal is output following the acknowledge signal output by the master or a slave. The busy

signal is set and released in phase with the falling edge of SCK. The master automatically terminates

output of serial clock SCK when the busy signal is released.

The master can transfer the next data when the busy signal is released and a slave enters the state

in which the ready signal is to be output.

(3) Register setting

To set the SBI mode, manipulate the following two registers:

• Serial operation mode register (CSIM)

• Serial bus interface control register (SBIC)

(a) Serial operation mode register (CSIM)

To use the SBI mode, set CSIM as shown below. (For details on CSIM format, see (1) in Section

5.6.3.)

CSIM is manipulated using an 8-bit manipulation instruction. Bits 7, 6, and 5 of CSIM can be

manipulated bit by bit.

When the RESET signal is input, CSIM is set to 00H.

In the figure below, hatched portions indicate the bits used in the SBI mode.

Address

FE0H

CSIE COI WUP CSIM4 CSIM3 CSIM2 CSIM1 CSIM0 CSIM

Serial clock selection bit (W)

Serial interface operation mode selection

bit (W)

Wake-up function specification bit (W)

Match signal from address comparator (R)

Serial interface operation enable/disable specification bit (W)

Remark (R): Read only

(W): Write only

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CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS

Serial interface operation enable/disable specification bit (W)

Shift register operation

Shift operation enabled

Serial clock counter IRQCSI flag

SO/SB0 and SI/SB1 pins

as well as for port 0

CSIE

Count operation Can be set Used in each mode

Signal from address comparator (R)

Note

COI

Condition for being cleared (COI = 0)

Condition for being set (COI = 1)

When the slave address register (SVA)

does not match the data of the shift register

When the slave address register (SVA)

matches the data of the shift register

Note COI can be read only before serial transfer is started or after serial transfer is completed. An

undefined value may be read during transfer.

COI data written by an 8-bit manipulation instruction is ignored.

Wake-up function specification bit (W)

WUP

Sets IRQCSI each time serial transfer is completed in each mode.

Used in the SBI mode only to set IRQCSI only when an address received after bus release

matches the data in the slave address register (wake-up state). SB0 or SB1 goes to high-

impedance state.

Caution When WUP = 1 is set during BUSY signal output, BUSY is not released. In the SBI mode,

the BUSY signal is output until the next falling edge of the serial clock (SCK) appears after

release of BUSY is directed. Before setting WUP = 1, be sure to confirm that the SB0 (or

SB1) pin is high after releasing BUSY.

Serial interface operation mode selection bit (W)

CSIM4 CSIM3

CSIM2

Shift register sequence

<—> XA

SO pin function

SI pin function

P03 input

SIO

SB0/P02 (N-ch

open-drain I/O)

7-0

(Transfer starting with MSB)

P02 input

SB1/P03 (N-ch

open-drain I/O)

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µPD750008 USER'S MANUAL

Serial clock selection bit (W)

CSIM1 CSIM0

Serial clock

External clock applied to SCK pin

SCK pin mode

Input

Output

Timer/event counter output (TOUT0)

f /2 (262 kHz)

f /2 (524 kHz)

Remark The value at 4.19 MHz is indicated in parentheses.

(b) Serial bus interface control register (SBIC)

To use the SBI mode, set SBIC as shown below. (For details on SBIC format, see(2) inSection 5.6.3.)

SBIC is manipulated using a bit manipulation instruction.

When the RESET signal is input, SBIC is set to 00H.

In the figure below, hatched portions indicate the bits used in the SBI mode.

Address

FE2H

BSYE

ACKD

ACKE

ACKT CMDD RELD

CMDT

RELT

SBIC

Bus release trigger bit (W)

Command trigger bit (W)

Bus release detection flag (R)

Command detection flag (R)

Acknowledge trigger bit (W)

Acknowledge enable bit (R/W)

Acknowledge detection flag (R)

Busy enable bit (R/W)

Remark (R):

Read only

Write only

(W):

(R/W): Read/write

Busy enable bit (R/W)

BSYE

<1> The busy signal is automatically disabled.

<2> Busy signal output is stopped in phase with the falling edge of SCK immediately after

clear instruction execution.

The busy signal is output after the acknowledge signal in phase with the falling edge of SCK.

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CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS

Acknowledge detection flag (R)

ACKD

Condition for being cleared (ACKD = 0)

Condition for being set (ACKD = 1)

<1> The transfer operation is started.

<2> The RESET signal is entered.

The acknowledge signal (ACK) is detected

(in phase with the rising edge of SCK).

Acknowledge enable bit (R/W)

ACKE

Disables automatic output of the acknowledge signal. (Output by ACKT is possible.)

When set before transfer

When set after transfer

ACK is output in phase with the 9th clock of SCK.

ACK is output in phase with SCK immediately following

the set instruction execution.

Acknowledge trigger bit (W)

ACKT

When set after transfer, ACK is output in phase with the next SCK. After ACK signal output,

this bit is automatically cleared to 0.

Cautions 1. Never set ACKT before or during serial transfer.

2. ACKT cannot be cleared by software.

3. Before setting ACKT, set ACKE = 0.

Command detection flag (R)

CMDD

Condition for being cleared (CMDD = 0)

Condition for being set (CMDD = 1)

<1> The transfer start instruction

is executed.

The command signal (CMD) is detected.

<2> The bus release signal (REL)

<3> The RESET signal is entered.

<4> CSIE = 0 (Figure 5-40)

Bus release detection flag (R)

RELD

Condition for being cleared (RELD = 0)

Condition for being set (RELD = 1)

<1> The transfer start instruction is executed.

<2> The RESET signal is entered.

<3> CSIE = 0 (Figure 5-40)

The bus release signal (REL) is detected.

<4> SVA does not match SIO when an address is

received.

Command trigger bit (W)

CMDT

Control bit for command signal (CMD) trigger output. By setting CMDT = 1, the SO latch is

cleared. Then the CMDT bit is automatically cleared.

Caution Never clear SB0 (or SB1) during serial transfer. Be sure to clear SB0 (or SB1) before or

after serial transfer.

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Bus release trigger bit (W)

RELT

Control bit for bus release signal (REL) trigger output.

By setting RELT = 1, the SO latch is set to 1. Then the RELT bit automatically cleared to 0.

Caution Never clear SB0 (or SB1) during serial transfer. Be sure to clear SB0 (or SB1) before or

after serial transfer.

(4) Serial clock selection

To select the serial clock, manipulate bits 0 and 1 of serial operation mode register (CSIM). The serial

clock can be selected out of the following four clocks:

Table 5-9. Serial Clock Selection and Application (In the SBI Mode)

Mode register

Serial clock

Masking of

Timing for shift register R/W and

start of serial transfer

Application

CSIM

Source

serial clock

External

SCK

Automatically

masked when

8-bit data

transfer is

completed

<1> In the operation halt mode

(CSIE = 0)

<2> When the serial clock is

masked after 8-bit transfer

<3> When SCK is high

Slave CPU

TOUT

flip-flop

Arbitrary-speed

serial transfer

f /2

Middle-speed

serial transfer

f /2

High-speed

serial transfer

When the internal system clock is selected, SCK is internally terminated when the 8th clock has been

output, and is externally counted until the slave enters the ready state.

(5) Signals

Figures 5-60 to 5-65 show signals to be generated in the SBI mode and flag operations on the SBIC. Table

5-10 lists signals used in the SBI mode.

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Figure 5-60. Operations of RELT, CMDT, RELD, and CMDD (Master)

Transfer start request

SIO

SCK

SO latch

RELT

"H"

CMDT

RELD

CMDD

Figure 5-61. Operations of RELT, CMDT, RELD, and CMDD (Slave)

Transfer start request

Write to SIO.

SIO

SCK

SO latch

RELT

(Master)

CMDT

(Master)

When address match is found

RELD

When address mismatch is found

CMDD

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Figure 5-62. Operation of ACKT

When ACKT is set after transfer completion

SCK

SB0, SB1

ACKT

ACK signal is output during the first clock

cycle immediately after ACKT is set.

ACK

When set during this period

Caution Do not set the ACKT until the transfer is completed.

Figure 5-63. Operation of ACKE (1/2)

(a) When ACKE = 1 at time of transfer completion

SCK

SB0, SB1

ACKE

The ACK signal is output

during the ninth clock

cycle.

ACK

When ACKE = 1 at this point

(b) When ACKE is set after transfer completion

SCK

SB0, SB1

ACKE

The ACK signal is output

during the first clock cycle

immediately after ACKE is set.

ACK

When ACKE is set during this period and ACKE = 1 at

the falling edge of the next SCK

SCK

SB0, SB1

ACKE

The ACK signal is not

output.

When ACKE = 0 at this point

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Figure 5-63. Operation of ACKE (2/2)

(d) When ACKE = 1 period is too short

SCK

SB0, SB1

ACKE

The ACK signal is not

output.

When ACKE is set or cleared during this period

and ACKE = 0 at the falling edge of SCK

Figure 5-64. Operation of ACKD (1/2)

(a) When ACK signal is output during the ninth SCK clock

Transfer start request

SIO

SCK

Transfer start

SB0, SB1

ACKD

ACK

(b) When ACK signal is output after the ninth SCK clock

Transfer start request

SIO

Transfer start

SCK

SB0, SB1

ACKD

ACK

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Figure 5-64. Operation of ACKD (2/2)

Transfer start request

SIO

Transfer start

SCK

SB0, SB1

ACKD

ACK

BUSY

Figure 5-65. Operation of BSYE

SCK

SB0, SB1

BSYE

BUSY

ACK

When BSYE = 1 at this point

When reset operation is executed during

this period and BSYE = 0 at the falling edge

of SCK

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(6) Pin configuration

The configurations of serial clock pin SCK and serial data bus pin (SB0 or SB1) are as follows:

(a) SCK: Pin for serial clock I/O

<1> Master : CMOS, push-pull output

<2> Slave : Schmitt input

(b) SB0, SB1: Pin for serial data I/O

Output to SB0 or SB1 is an N-ch open-drain output and input is Schmitt input for both

the master and a slave.

The serial data bus line must be externally pulled up because it has originally an N-ch open-drain

output.

Figure 5-66. Pin Configuration

Slave device

Master device

(Clock output)

Clock output

(Clock input)

Clock input

Serial clock

N-ch open-drain

SB0, SB1

SB0, SB1 N-ch open-drain

Serial data bus

Caution When data is received, the N-ch transistor must be turned off, so FFH must be written to

SIO beforehand. The N-ch open-drain output can be turned off at any time during transfer.

However, when the wake-up function specification bit (WUP) is set to 1, the N-ch transistor

is always off, so there is no need to write FFH to SIO before reception.

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(7) Address match detection method

In the SBI mode, communication starts when the master selects a particular slave device by outputting

an address.

An address match is detected by hardware. The slave address register (SVA) is available. In the wake-

up state (WUP = 1), IRQCSI is set only when the address transmitted by the master and the value held

in SVA match.

Cautions 1. Whether a slave is selected is determined by detecting a match for a slave ad-

dress received after bus release (in the state of RELD = 1).

An address match is detected usually using an address match interrupt (IRQCSI)

generated when WUP is set to 1. So detect selection/nonselection state by slave

address when WUP is set to 1.

2. When determining whether a slave is selected without using an interrupt when

WUP is 0, do not use the address match detection method. Instead, use transfer

of commands set in advance in a program.

(8) Error detection

In the SBI mode, the state of serial bus SB0 (or SB1) being used for communication is loaded into the

shift register (SIO) of the transmitting device. So a transmission error can be detected by the methods

described below.

(a) Comparing SIO data before start of transmission with SIO data after start of transmission

With this method, the occurrence of a transmission error is assumed if two SIO values disagree with

each other.

(b) Using the slave address register (SVA)

Transmit data is set in SIO and SVA as well before the data is transmitted. On completion of

transmission, the COI bit (match signal from the address comparator) of serial operation mode register

(CSIM) is tested. If the result is 1, the transmission is regarded as successful. If the result is 0, the

occurrence of a transmission error is assumed.

(9) Communication operation

In the SBI mode, the master usually selects a slave device to communicate with from multiple devices

by outputting the address of the slave to the serial bus.

After selecting a device to communicate with, the master exchanges commands and data with the slave

device, thus establishing serial communication.

Figures 5-67 to 5-70 show the timing charts of data communication operations.

In the SBI mode, the shift register performs shift operation on the falling edge of the serial clock (SCK).

Transmit data is held on the SO latch, and is output on the SB0/P02 or SB1/P03pin starting with the MSB.

Receive data applied to the SB0 (or SB1) pin is latched in the shift register on the rising edge of SCK.

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(10) Transfer start

Serial transfer is started by writing transfer data in shift register (SIO), provided that the following two

conditions are satisfied:

• The serial interface operation enable/disable bit (CSIE) is set to 1.

• The internal serial clock is not operating after 8-bit serial transfer, or SCK is high.

Cautions 1. Transfer cannot be started by setting CSIE to 1 after writing data to the shift

2. The N-ch transistor needs to be turned off when data is received. So FFH must

be written to SIO beforehand. However, when the wake-up function specification

bit (WUP) is set to 1, the N-ch transistor is always off. So FFH need not be

written to SIO beforehand for reception.

3. If data is written to SIO when the slave is busy, the data is not lost. Transfer is

started when the busy state is released and input to SB0 (or SB1) goes high.

When eight bits have been transferred, serial transfer automatically terminates setting the interrupt request

flag (IRQCSI).

Example When RAM data specified by the HL register is transferred to SIO, from which data is loaded

into the accumulator at the same time, and serial transfer is started.

MOV XA,@HL ; Extracts transmit data from RAM

SEL MB15

; or CLR1 MBE

XCH XA,SIO

; Exchanges transmit data with receive data and startstransfer

(11) Notes on the SBI mode

(a) Whether a slave is selected is determined by detecting a match for a slave address received after

bus release (in the state of RELD = 1).

An address match is detected usually using, an address match interrupt (IRQCSI) generated when

WUP is 1. So detect selection/nonselection state by slave address when WUP is set to 1.

(b) When determining whether a slave is selected without using an interrupt when WUP = 0, do not use

the address match detection method. Instead, use transfer of commands set in advance in a program.

of BUSY is directed, the BUSY signal is output until the next falling edge of the serial clock (SCK)

appears. Before setting WUP to 1, be sure to confirm that the SB0 (or SB1) pin is high after releasing

BUSY.

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(12) SBI mode

This section describes an example of application which performs serial data communication in the SBI

mode. In the example, the µPD750008 can be used as either the master CPU or a slave CPU on the

serial bus.

The master can be switched to another CPU with a command.

(a) Serial bus configuration

In the serial bus configuration used for the example of this section, a µPD750008 is connected to the

bus line as a device on the serial bus.

Two pins on the µPD750008 are used: serial data bus SB0 (or SB1) and serial clock SCK (P01).

Figure 5-71 shows an example of the serial bus configuration.

Figure 5-71. Example of Serial Bus Configuration

VDD

Master CPU

Slave CPU

µPD750008

SB0, SB1

SCK

SB0, SB1

SCK

Address 1

Slave CPU

SB0, SB1

SCK

Address 2

Slave IC

SB0, SB1

SCK

Address N

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(b) Explanation of commands

(i) Types of commands

This example uses the following commands:

<1> READ command

: Transfers data from slave to master.

<2> WRITE command : Transfers data from master to slave.

<3> END command

: Informs slave of WRITE command completion.

: Informs slave of WRITE command interruption.

<4> STOP command

<5> STATUS command : Reads slave status.

<6> RESET command : Sets currently selected slave as non-selected slave.

<7> CHGMST command: Passes master authority to slave.

(ii) Protocol

The following protocol is used for communication between the master and slaves.

<1> The address of a slave with which the master intends to communicate is transmitted to select

the slave (chip select). This starts communication.

The slave that has received the address returns ACK to engage in communication with the

master (The state of the slave is changed from the non-selected state to selected state).

<2> Commands and data are transferred between the master and the slave selected in <1>.

Command and data are transferred between the master and the selected slave on a one-

to-one basis, so the other slaves must be placed in the non-selected state.

<3> Communication is completed when the selected slave is placed in the non-selected state.

This state is caused in the following cases:

• The selected slave is placed in the non-selected state when the slave receives a RESET

command from the master.

• The device that is switched from the master to a slave with a CHGMST command is placed

in the non-selected state.

(iii) Command format

The transfer format of each command is described below.

<1> READ command

The READ command reads data from a slave. One to 256 bytes of data can be read. The

data length is specified in a parameter by the master. When 00H is specified as the data

length, the 256-byte data transfer is assumed.

Figure 5-72. Transfer Format of the READ Command

READ

ACK

Data count

Data

ACK

Data 0

Data

ACK

Data N

Data

ACK

Command

Remark M: Output by the master

S: Output by the slave

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When the slave receives a transmission data count, if it has data enough for transmitting the

specified number of bytes of data, the slave returns ACK. If the slave does not have enough

data for transmission, an error occurs; ACK is not returned in this case.

The master sends ACK to the slave each time it receives one byte.

<2> WRITE command, END command, STOP command

These commands write data to a slave. One to 256 bytes of data can be written. The data

length is specified in a parameter by the master. When 00H is specified as the data length,

the 256-byte data transfer is assumed.

Figure 5-73. Transfer Format of the WRITE and END Commands

WRITE

Command

ACK

Data count

Data

ACK

Data 0

Data

ACK

Data N

Data

ACK

END

ACK

Command

Remark M: Output by the master

S: Output by the slave

If the slave has an enough area for storing receive data of the specified length, the slave

returns ACK. If the slave does not have an enough area, an error occurs; ACK is not returned

in this case.

The master transmits an END command when all data have been transferred. The END

command informs the slave that all data have been transferred correctly.

The slave accepts an END command even before data reception is uncompleted. In this case,

the data received just before the acceptance of the END command becomes valid.

The master compares the contents of SIO before transfer with the contents of SIO after

transfer to check whether the data has been output onto the bus correctly. If the contents

of SIO disagree with each other, the master interrupts data transfer by transmitting a STOP

command.

Figure 5-74. Transfer Format of the STOP Command

Data

ACK

STOP

ACK

Command

Data transfer interruption

Data check error occurs.

Remark M: Output by the master

S: Output by the slave

When the slave receives a STOP command, the slave invalidates the most recently received one byte.

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<3> STATUS command

The STATUS command reads the status of the current slave.

Figure 5-75. Transfer Format of the STATUS Command

STATUS

Data

ACK

Status

ACK

Command

Remark M: Output by the master

S: Output by the slave

The slave returns the status in the format shown in Figure 5-78.

Figure 5-76. Status Format of the STATUS Command

MSB

Status

LSB

Bit indicating whether there is data ready for transmission

All 0s

0 : No transmit data

1 : Transmit data of one byte or more

Bit indicating whether the device is ready for data reception

0 : No receive data storage area

1 : Receive data storage area not smaller than one byte is present.

Bit indicating whether an error occurred

0 : No error

1 : Error occurred during previous transfer.

Bit indicating whether master can be changed or not

0 : Master cannot be changed.

1 : Master can be changed.

When the master receives a status, it returns ACK to the current slave.

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<4> RESET command

The RESET command changes the currently selected slave to a non-selected slave. When

a RESET command is transmitted, any slave can be placed in the non-selected state.

Figure 5-77. Transfer Format of the RESET Command

RESET

Command

ACK

Remark M: Output by the master

S: Output by the slave

<5> CHGMST command

The CHGMST command passes the master authority to the currently selected slave.

Figure 5-78. Transfer Format of the CHGMST Command

CHGMST

Command

ACK

Data

ACK

Remark M: Output by the master

S: Output by the slave

When the slave receives a CHGMST command, the slave returns one of the following data

to the master after checking whether the slave can receive the master authority:

• 0FFH: Master changeable

• 00H: Master not changeable

The slave compares the contents of SIO before transfer with the contents of SIO after transfer.

If the contents of SIO disagree with each other, an error occurs; ACK is not returned in this

case.

If the master receives 0FFH, the master returns ACK to the slave, and starts to operate as

a slave. The slave which transmitted 0FFH starts to operate as the master when it receives

ACK.

(iv) Error occurrence

If a communication error occurs, the operation described below is performed.

The slave reports the occurrence of an error by not returning ACK to the master. If an error

occurs during reception of data, the slave sets the status bit for indicating error occurrence,

and cancels all command processing being performed.

When the transmission of one byte is completed, the master checks for ACK from the slave.

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CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS

If ACK is not returned from the slave within a predetermined period after transmission

completion, the occurrence of an error is assumed; the master outputs the ACK signal as a

dummy.

Figure 5-79. Master and Slave Operation in Case of Error

Reception is completed.

Processing by slave

Error is assumed, and processing is halted.

Erroneous data

ACK

SB0, SB1

ACK wait time

ACK from slave is checked.

Processing by master

Transfer is completed.

ACK check is started.

Error is assumed.

ACK is output.

The following errors may occur:

• Error that may occur on the slave side

<1> Invalid command transfer format

<2> Reception of an undefined command

<3> Insufficient number of transfer data bytes for a READ command

<4> Insufficient area to contain data for a WRITE command

<5> Change in data during transmission of a READ, STATUS, or CHGMST command

If any of the above types of errors occurs, ACK is not returned.

• Error that may occur on the master side

If data transmitted with a WRITE command changes during transmission, the master

transmits a STOP command to the slave.

5.6.8 Manipulation of SCK Pin Output

The SCK/P01 pin has a built-in output latch, so that this pin allows static output by software manipulation

in addition to normal serial clock output.

The number of SCK pulses can be software-set arbitrarily by manipulating the P01 output latch. (The SO/

SB0/P02 or SI/SB1/P03 pin is controlled by manipulating the RELT and CMDT bits of SBIC.)

The procedure for manipulating SCK/P01 pin output is explained below.

<1> Set serial operation mode register (CSIM) (SCK pin: output mode). When serial transfer is halted,

SCK from the serial clock control circuit is set to 1.

<2> Manipulate the P01 output latch by using a bit manipulation instruction.

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Example To output one SCK/P01 pin clock cycle by software

SEL

MB15

; or CLR1 MBE

MOV XA,#10000011B ; SCK (f /2 ), output mode

MOV CSIM,XA

CLR1 0FF0H.1

SET1 0FF0H.1

; SCK/P01 <- 0

; SCK/P01 <- 1

Figure 5-80. SCK/P01 Pin Circuit Configuration

Address

FF0H.1

P01

output

latch

P01/SCK

To internal circuit

From the serial clock

control circuit

SCK

SCK pin output mode

The P01 output latch is mapped to bit 1 of address FF0H. A RESET signal sets the P01 output latch to

Cautions 1. During normal serial transfer, the P01 output latch must be set to 1.

2. The P01 output latch cannot be addressed by specifying PORT0.1 (as described

below). The address of the latch (0FF0H.1) must be coded in the operand of an

instruction directly. However, MBE = 0 (or MBE = 1, MBS = 15) must be specified

before the instruction is executed.

CLR1 PORT0.1

Not allowed

SET1 PORT0.1

CLR1 0FF0H.1

Allowed

SET1 0FF0H.1

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5.7 BIT SEQUENTIAL BUFFER: 16-BIT

The bit sequential buffer (BSB) is special data memory for bit manipulations. In particular, the buffer allows

bit manipulations to be performed very easily by sequentially changing address and bit specifications. So

the buffer is useful in processing long data bit by bit.

This data memory consists of 16 bits, and allows pmem.@L addressing with a bit manipulation instruction.

This addressing uses the L register for indirect bit specification. In this case, only by incrementing or

decrementing the L register in a program loop, the bit to be manipulated can be sequentially shifted for

continued processing.

Figure 5-81. Format of the Bit Sequential Buffer

Address

Bit

FC3H

FC2H

FC1H

FC0H

Symbol

BSB3

BSB2

BSB1

BSB0

L register L = FH

L = CH L = BH

L = 8H L = 7H

L = 4H L = 3H

DECS L

L = 0H

INCS L

Remarks 1. With pmem.@L addressing, bit specification is shifted according to the L register.

2. With pmem.@L addressing, BSB can be manipulated at any time regardless of

MBE/MBS specification.

Data can also be manipulated by direct addressing. The buffer can be used for applications such as

continuous 1-bit data input or output operations by combining direct 1-bit, 4-bit, and 8-bit addressing with

pmem.@L addressing. In 8-bit manipulation, the higher eight bits or lower eight bits are manipulated by

specifying BSB0 or BSB2.

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Example To output 16-bit data of BUFF1 and BUFF2 serially from bit 0 of port 3:

CLR1

MBE

MOV

XA,BUFF1

MOV

BSB0,XA ; Set BSB0 and BSB1

XA,BUFF2

MOV

BSB2,XA ; Set BSB2 and BSB3

L,#0

MOV

LOOP0: SKT

BSB0, @L ; Tests the specification bit of BSB

LOOP1

NOP

; Dummy (For timing adjustment)

PORT3. 0 ; Sets bit 0 of port 3

LOOP2

SET1

LOOP1: CLR1

NOP

PORT3. 0 ; Clears bit 0 of port 3

; Dummy (For timing adjustment)

NOP

LOOP2: INCS

; L <- L + 1

LOOP0

RET

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CHAPTER 6 INTERRUPT AND TEST FUNCTIONS

The µPD750008 has seven vectored interrupt sources and two test inputs, allowing a wide range of

applications.

In addition, the interrupt control circuitry of the µPD750008 has the following features for very high-speed

interrupt processing.

(1) Interrupt functions

(a) Hardware controlled vectored interrupt function which can control whether or not to accept an interrupt

using the interrupt flag (IExxx) and interrupt master enable flag (IME).

(b) The interrupt start address can be set arbitrarily.

(IPS)

(d) Test function of an interrupt request flag (IRQxxx)

(The software can confirm that an interrupt occurred.)

(e) Release of the standby mode (Interrupts released by an interrupt enable flag can be selected.)

(2) Test functions

(a) Whether test request flags (IRQxxx) are issued can be checked with software.

(b) Release of the standby mode (A test source to be released can be selected with test enable flags.)

6.1 CONFIGURATION OF THE INTERRUPT CONTROL CIRCUIT

Figure 6-1 shows the configuration of the interrupt control circuit. Each hardware item is mapped to a data

memory space.

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6.2 TYPES OF INTERRUPT SOURCES AND VECTOR TABLES

Table 6-1 lists the types of interrupt sources, and Figure 6-2 shows vector tables.

Table 6-1. Interrupt Sources

Interrupt

priority

Vectored interrupt request

(vector table address)

Interrupt source signal

In/out

Note

INTBT

INT4

Reference time interval signal from

basic interval timer/wactchdog timer

VRQ1 (0002H)

Detection of both rising and falling

edges

Out

INT0

INT1

Out

VRQ2 (0004H)

VRQ3 (0006H)

Rising/falling edge

detection specification

INTCSI

INTT0

Serial data transfer completion signal

VRQ4 (0008H)

VRQ5 (000AH)

Match signal between the count

and modulo register

INTT1

Match signal between the count

and modulo register

VRQ6 (000CH)

Note The interrupt priority is used to determine the priority when two or more interrupts are

simultaneously generated.

Figure 6-2. Interrupt Vector Table

Address

0000H

0002H

0004H

0006H

0008H

000AH

000CH

(high-order 6 bits)

(low-order 8 bits)

MBE

RBE

Internal reset start address

INTBT/INT4 start address (high-order 6 bits)

INTBT/INT4 start address (low-order 8 bits)

INT0 start address

INT1 start address

INTCSI start address

INTT0 start address

INTT1 start address

(high-order 6 bits)

(low-order 8 bits)

(high-order 6 bits)

(low-order 8 bits)

(high-order 6 bits)

(low-order 8 bits)

(high-order 6 bits)

(low-order 8 bits)

(high-order 6 bits)

(low-order 8 bits)

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The column of interrupt priority in Table 6-1 indicates a priority assigned when multiple interrupt requests

occur concurrently or are held.

A vector table contains interrupt processing start addresses and MBE and RBE setting values during

interrupt processing. An assembler pseudo instruction (VENTn) is used to set a vector table.

Example A vector table is set for INTBT/INT4.

VENT1

MBE = 0, RBE = 0,

GOTOBT

Vector table at

address 0002

MBE·RBE setting value

Symbol for indicating

an interrupt service

routine start address

in interrupt service routine

Caution The vector table specified by VENTn (n = 1 to 6) is located at address 2n.

Example Vector tables are set for INTBT/INT4 and INTT0.

VENT1

VENT5

MBE = 0, RBE = 0, GOTOBT

MBE = 0, RBE = 1, GOTOT0

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6.3 VARIOUS DEVICES TO CONTROL INTERRUPT FUNCTIONS

(1) Interrupt request flags and interrupt enable flags

The following seven interrupt request flags (IRQxxx) corresponding to the interrupt sources are

provided.

INT0 interrupt request flag (IRQ0)

INT1 interrupt request flag (IRQ1)

INT4 interrupt request flag (IRQ4)

BT interrupt request flag (IRQBT)

Serial interface interrupt request flag (IRQCSI)

Timer/event counter interrupt request flag (IRQT0)

Timer counter interrupt request flag (IRQT1)

An interrupt request flag is set to 1 by an interrupt request, and is automatically cleared to 0 when interrupt

processing is performed. However, IRQBT and IRQ4 are cleared in a different way because these flags

share a vector address. (See Section 6.6.)

The following seven interrupt enable flags (IExxx) corresponding to the interrupt request flags are

provided.

INT0 interrupt enable flag (IE0)

INT1 interrupt enable flag (IE1)

INT4 interrupt enable flag (IE4)

BT interrupt enable flag (IEBT)

Serial interface interrupt enable flag (IECSI)

Timer/event counter interrupt enable flag (IET0)

Timer counter interrupt enable flag (IET1)

An interrupt enable flag set to 1 enables the corresponding interrupt, and an interrupt enable flag set to

0 disables the corresponding interrupt.

When an interrupt request flag and the interrupt enable flag are set to 1, a vectored interrupt request (VRQn)

occurs. This condition is also used to release a standby mode.

A bit manipulation instruction or 4-bit memory manipulation instruction is used to manipulate an interrupt

request flag and interrupt enable flag. A bit manipulation instruction allows direct manipulation regardless

of MBE setting. An interrupt enable flag can be manipulated using an EI IExxx instruction or DI IE instruction.

The SKTCLR instruction is usually used to test an interrupt request flag.

Example EI

IE0

IE1

; Enable INT0

; Disable INT1

SKTCLR IRQCSI

; Skip and clear IRQCSI when it is set to 1.

When an interrupt request flag is set using an instruction, even if there is no interrupt request, a vectored

interrupt is executed in the same way as when an interrupt is requested.

Inputting a RESET signal clears the interrupt request and interrupt enable flags to 0, disabling all interrupts.

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Table 6-2. Set Signals for Interrupt Request Flags

Interrupt

request flag

Interrupt

enable flag

Set signals for interrupt request flags

IRQBT

Set by a reference time interval signal from the basic interval timer/watchdog

timer.

IEBT

IRQ4

IRQ0

Set by a detected rising or falling edge of an INT4/P00 pin input signal.

IE4

IE0

Set by a detected edge of an INT0/P10 pin input signal.

The detection edge is specified by the INT0 edge detection mode register

(IM0).

IRQ1

Set by a detected edge of an INT1/P11 pin input signal.

The detection edge is specified by the INT1 edge detection mode register

(IM1).

IE1

IRQCSI

IRQT0

IRQT1

Set by a serial data transfer completion signal for the serial interface.

Set by a match signal from timer/event counter 0.

IECSI

IET0

IET1

Set by a match signal from the timer counter.

(2) Interrupt priority specification register (IPS)

The interrupt priority specification register selects an interrupt with a higher priority from multiple interrupts

using the low-order three bits.

Bit 3, interrupt master enable flag (IME), specifies whether to disable all interrupts.

The IPS is set using a 4-bit memory manipulation instruction. Bit 3 is set by an EI instruction and reset

by a DI instruction.

When changing the low-order three bits of the IPS, interrupts must be disabled (IME = 0) beforehand.

Example DI

CLR1

; Disable interrupts

MBE

MOV

A,#1011B

IPS,A

; Assign a higher priority to INT1, then enable interrupts.

A RESET signal clears all bits to 0.

Caution Disable interrupts before setting the IPS.

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Figure 6-3. Interrupt Priority Specification Register

Address

FB2H

Symbol

IPS

IPS3

IPS2

IPS1

IPS0

High-order interrupt selection

All low-order interrupt

The listed vectored

interrupts are treated

as high-order interrupts.

VRQ1

(INTBT/INT4)

VRQ2

(INT0)

VRQ3

(INT1)

VRQ4

(INTCSI)

VRQ5

(INTT0)

VRQ6

(INTT1)

Not to be set

Interrupt master enable flag (IME)

All interrupts are disabled and no vectored interrupt is

activated.

The interrupt enable flag corresponding to an interrupt

request flag controls interrupt enabling/disabling.

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(3) Configurations of the INT0, INT1, and INT4 circuits

(a) As shown in Figure 6-4 (a), the INT0 circuit accepts an external interrupt at its rising or falling edge.

The edge to be detected can be selected.

The INT0 circuit has a noise elimination function (see Figure 6-5), called a noise eliminator, using

Note

a sampling clock, which removes pulses shorter than two sampling clock cycles

as noise. The

INT0 circuit may accept pulses which are longer than one sampling clock cycle and shorter than two

cycles as interrupts depending on the sampling timing (seeFigure 6-4 (a)). The circuit is sure to accept

pulses equal to or longer than two sampling clock cycles as interrupts.

The INT0 pin is supplied with sampling clock F or f /64, whichever is selected by bit 3 (IM03) of the

INT0 edge detection mode register (IM0).

Bit 0 (IM00) and bit 1 (IM01) of the INT0 edge detection mode register (IM0) are used to select a

detection edge.

Figure 6-6 (a) shows the format of IM0. A 4-bit memory manipulation instruction is used to set IM0.

A RESET signal clears all bits to 0, and a rising edge is specified to be detected.

Note When the frequency of a sampling clock is F, these cycles are equal to 2t . When the

frequency of a sampling clock is f /64, these cycles are equal to 128/f .

Cautions 1. InputapulsewiderthantwosamplingclockcyclestotheINT0/P10pin. Otherwise,

the pulse is suppressed as noise by a noise eliminator when the pin is used as

a port.

2. When the noise eliminator is selected (IM02 is set to 0), INT0 does not operate

in standby mode because INT0 requires a clock for sampling. Do not select the

noise eliminator when using INT0 to release standby mode (set IM02 to 1).

(b) As shown in Figure 6-4 (b), the INT1 circuit accepts an external interrupt at its rising or falling edge.

The INT1 edge detection mode register (IM1) is used to select a detection edge.

Figure 6-6 (b) shows the format of IM1. A bit manipulation instruction is used to set IM1. A RESET

signal clears all bits to 0, and a rising edge is specified to be detected.

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Figure 6-4. Configurations of the INT0, INT1, and INT4 Circuits

(a) Configuration of the INT0 circuit

INT0

IRQ0

set signal

Edge detection

circuit

INT0/P10

Noise eliminator

IM02

IM03

IM00, IM01

Selector

Detection edge

specification

Sampling clock selection

IM0

X/64

Input buffer

Internal bus

(b) Configuration of the INT1 circuit

INT1

IRQ1

set signal

Edge detection circuit

INT1/P11

IM10

IM1

Detection edge specification

Input buffer

Internal bus

INT4

Both-edge

detection circuit

IRQ4

set signal

INT4/P00

Input buffer

Internal bus

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Figure 6-5. I/O Timing of a Noise Eliminator

tSMP

<1> Shorter than sampling cycle (t^SMP)

INT0

"L"

Removed as noise

Shaped output

<2> 1 to 2 times

(a)

INT0

Shaped output

(b)

INT0

"L"

Removed as noise

Shaped output

<3> Longer than 2 times

INT0

Shaped output

Remark t

= t or 64/f

CY X

SMP

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CHAPTER 6 INTERRUPT AND TEST FUNCTIONS

Figure 6-6. Format of Edge Detection Mode Registers

(a) INT0 edge detection mode register (IM0)

Address

FB4H

Symbol

IM0

IM03

IM02

IM01

IM00

IM01

IM00

Detection edge specification

Specifies rising edge.

Specifies falling edge.

Specifies both rising and falling edges.

Ignored (No interrupt request flag is set.)

IM02

Noise eliminator selection bit

Selects a noise eliminator.

Sampling

Enabled

Standby mode

Cannot be released

Can be released

Does not select a noise eliminator. Disabled

IM03

Sampling clock

Φ (0.67 µs, 1.33 µs, 2.67 µs, and 10.7 µs at 6.00 MHz)

X/64 (10.7 µs at 6.00 MHz)

(b) INT1 edge detection mode register (IM1)

Address

FB5H

Symbol

IM1

IM10

Detection edge specification

Specifies rising edge.

Specifies falling edge.

Caution Changing the edge detection mode register may set an interrupt request flag. So, disable

the interrupts before changing the edge detection mode register. Then clear the interrupt

request flag with a CLR1 instruction and enable the interrupts. When f /64 is selected

as a sampling clock pulse in changing IM0, wait for 16 machine cycles after changing the

mode register and clear the interrupt request flag.

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(4) Interrupt status flags

The interrupt status flags (IST0 and IST1), which are contained in the PSW, indicate the status of

processing currently executed by the CPU.

By using the content of these flags, the interrupt priority control circuit controls multiple interrupts as

indicated in Table 6-3.

A 4-bit manipulation instruction or bit manipulation instruction can be used to set and reset IST0 and IST1,

so that multiple interrupts are enabled by changing the current status of execution. IST0 and IST1 can

be manipulated on a single-bit basis at any time regardless of MBE setting.

Before IST0 or IST1 is manipulated, the DI instruction must be executed to disable interrupts, then the

EI instruction must be executed to enable interrupts.

IST1 and IST0 as well as the other PSW bits are saved in the stack memory when an interrupt is accepted

and the status of IST0 and IST1 changes to a status one level higher. When a RETI instruction is executed,

the former values of IST1 and IST0 are resumed.

Inputting a RESET signal clears the content of the flag to 0.

Table 6-3. Interrupt Processing Statuses of IST0 and IST1

After acceptance

Processing

status

Interrupts that

IST1 IST0

CPU operation

can be accepted

IST1

IST0

Status 0

Status 1

Is processing the normal program.

All

Is processing a low- or high-order

interrupt.

Only high-order

interrupts

Status 2

Is processing a high-order interrupt.

—

Not to be set

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6.4 INTERRUPT SEQUENCE

When an interrupt occurs, it is processed using the procedure shown in Figure 6-7.

Figure 6-7. Interrupt Sequence

Interrupt (INTxxx) occurrence

IRQxxx setting

IExxx set?

Hold until IExxx is set.

Yes

Corresponding VRQn occurrence

Hold until IME

is set.

IME = 1

Yes

VRQn high-order

interrupt?

Hold until process-

ing being executed

is finished.

Yes

Note 1

IST1, 0 = 00 or 01

IST1, 0 = 00

Yes

If two or more VRQns occur, select

one VRQn according to Table 6-1.

Selected

VRQn

Remaining

VRQns

Save contents of PC and PSW in stack memory and set data^{Note 2}in vector table

corresponding to activated VRQn to PC, RBE, and MBE.

Change contents of IST0 and IST1 from 00 to 01

or from 01 to 10.

Reset accepted IRQxxx.

See Section 6.6 when those interrupt

sources share vector address.

Jump to the start address for processing the interrupt service program.

Notes 1. IST0 and IST1 are the interrupt status flags (bits 3 and 2 of the PSW). (See Table 6-3.)

2. An interrupt service program start address and MBE and RBE setting values at the

start of interrupt are stored in each vector table.

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6.5 MULTIPLE INTERRUPT PROCESSING CONTROL

The µPD750008 can handle multiple interrupts by either of the following methods.

(1) Multiple interrupt processing by a high-order interrupt

In this method, the µPD750008 selects an interrupt source among multiple interrupt sources, enabling

double interrupt processing.

That is, the high-order interrupt specified by the interrupt priority specification register (IPS) is enabled

when the processing status is 0 or 1. Other interrupts (interrupts lower than the specified high-order

interrupt) are enabled only when the status is 0. (See Figure 6-8 and Table 6-3.)

When only one interrupt is used as a level-two interrupt, using this method saves the user the trouble of

enabling or disabling interrupts during an interrupt processing, and holds down the number of nesting

levels to two.

Figure 6-8. Multiple Interrupt Processing by a High-Order Interrupt

Normal

processing

(Status 0)

Low- or high-order

interrupt processing

(Status 1)

High-order

interrupt

processing

(Status 2)

Interrupt is disabled.

IPS setting

Interrupt is enabled.

High-order

interrupt

occurrence

Low- or high-order

interrupt occurrence

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CHAPTER 6 INTERRUPT AND TEST FUNCTIONS

(2) Multiple interrupt processing by changing the interrupt status flags

Changing the interrupt status flags with the program causes multiple interrupts to be enabled. That is,

when the interrupt processing program changes both IST1 and IST0 to 0 (status 0), multiple interrupt

processing is enabled.

This method is used when two or more interrupts are to be enabled at a time or when the processing of

three or more interrupts is to be performed.

When changing IST1 and IST0, interrupts must be disabled beforehand with a DI instruction.

Figure 6-9. Multiple Interrupt Processing by Changing the Interrupt Status Flags

Normal processing

(status 0)

Single interrupt

Dual interrupts

Interrupt is disabled.

IPS setting

Status 1

Interrupt is

disabled.

Interrupt is enabled.

Modification

of IST

Low- or high-order

interrupt occurrence

Interrupt is

enabled.

Status 0

Status 1

Low- or high-order

interrupt occurrence

Status 0

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6.6 PROCESSING OF INTERRUPTS SHARING A VECTOR ADDRESS

Interrupt sources INTBT and INT4 share a vector table, so an interrupt source is selected as described

below.

(1) Using only one interrupt

The interrupt enable flag for desired one of the two interrupt sources sharing a vector table is set to 1,

and the interrupt enable flag for the other is cleared to 0. In this case, the enabled (IExxx = 1) interrupt

source causes an interrupt request. When the interrupt request is accepted, the interrupt request flag

is reset.

(2) Using both interrupts

The interrupt enable flags corresponding to the two interrupt sources are both set to 1. In this case, the

logical sum of the interrupt request flags for the two interrupt sources is used as an interrupt request.

In this case, even if an interrupt request or interrupt requests caused by the setting of one or both of the

interrupt request flags are accepted, the interrupt request flag or flags are not reset.

Accordingly, which of the two interrupt sources caused the interrupt needs to be determined using the

interrupt service routine. For this determination, the DI instruction is to be executed at the start of the

interrupt service routine, and the interrupt request flags are checked with the SKTCLR instruction.

If both the request flags are set when this request flag is tested or cleared, the interrupt request remains

even if one of the request flags is cleared. If this interrupt is selected as having the higher priority, nesting

processing is started by the remaining interrupt request.

Consequently, the interrupt request not tested is processed first. If the selected interrupt has the lower

priority, the remaining interrupt is kept pending and therefore, the interrupt request tested is processed

first. Therefore, an interrupt sharing a vector address with another interrupt is identified differently,

depending whether it has the higher priority, as shown in Table 6-4.

Table 6-4. Identifying Interrupt Sharing Vector Table Address

With higher priority

With lower priority

Interrupt is disabled and interrupt request flag of interrupt that takes precedence is

tested

Interrupt request flag of interrupt that takes precedence is tested

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Examples 1. To use both INTBT and INT4 as having the higher priority and give priority to INT4

SKTCLR

IRQ4

;

IRQ4 = 1 ?

VSUBBT

Processing routine

of INT4

RETI

VSUBBT: CLR1

IRQBT

Processing routine

of INTBT

RETI

2. To use both INTBT and INT4 as having the lower priority and give priority to INT4

SKTCLR

IRQ4

;

IRQ4 = 1 ?

VSUBBT

Processing routine

of INT4

RETI

VSUBBT: CLR1

IRQBT

Processing routine

of INTBT

RETI

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6.7 MACHINE CYCLES FOR STARTING INTERRUPT PROCESSING

With the µPD750008 series, the following machine cycles are used to start the execution of the interrupt

service routine after an interrupt request flag (IRQn) is set.

(1) When IRQn is set during execution of an interrupt control instruction

When IRQn is set during execution of an interrupt control instruction, an instruction preceded by that

instruction is executed, and an interrupt processing of three machine cycles is executed, then the interrupt

service routine is started.

Interrupt control

instruction

A: IRQn is set.

B: The next instruction is executed (1 to 3 machine cycles according to the instruction).

C: Interrupt processing (3 machine cycles)

D: Interrupt service routine is executed.

Remarks 1. An interrupt control instruction manipulates hardware (address FBxH in data memory) which

handles interrupt processings. There are two types of interrupt control instruction, a DI

instruction and an EI instruction.

2. Three machine cycles required for the interrupt processing include the time to manipulate

the stack when an interrupt is accepted.

Cautions 1. Wheninterruptcontrolinstructionsarecontiguoustheseinterruptcontrolinstructions

are executed up to the last one. An instruction preceded by the interrupt control

instruction executed last is executed, and an interrupt processing of three machine

cycles is executed, then the interrupt service routine is started.

2. When a DI instruction is executed in the period during which IRQn is set (A in the

figure), or in the immediately following period, the interrupt request of the set IRQn

is held until an EI instruction is executed.

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CHAPTER 6 INTERRUPT AND TEST FUNCTIONS

(2) When IRQn is set during an instruction other than that described in (1)

(a) When IRQn is set at the last machine cycle of the instruction being executed

In this case, an instruction preceded by the instruction being executed is executed, and an interrupt

processing of three machine cycles is executed, then the interrupt service routine is started.

An instruction other than

interrupt control instruction

A: IRQn is set.

B: The next instruction is executed (1 to 3 machine cycles to the instruction).

C: Interrupt processing (3 machine cycles)

D: Interrupt service routine is executed.

Caution When one or more interrupt control instructions follow, an instruction preceded by the

interrupt control instructions is executed, and an interrupt processing of three machine

cycles is executed, then the interrupt service routine is started. When an instruction to

be executed after setting IRQn is a DI instruction, the interrupt request of the set IRQn

is held.

(b) When IRQn is set earlier than the last machine cycle of the instruction being executed

In this case, after executing the instruction being executed, an interrupt processing of three machine

cycles is executed, then the interrupt service routine is started.

An instruction other than

interrupt control instruction

A: IRQn is set.

C: Interrupt processing (3 machine cycles)

D: Interrupt service routine is executed.

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6.8 EFFECTIVE USE OF INTERRUPTS

The interrupt function can be used more effectively in the ways described below.

(1) MBE = 0 is set for the interrupt service routine

By allocating addresses 00H to 7FH as data memory used by the interrupt service routine and specifying

MBE = 0 in an interrupt vector table, the user can code a program without being concerned with a memory

bank.

If a program must use memory bank 1 for some reason, save the memory bank select register using the

PUSH BS instruction before selecting memory bank 1.

(2) Use different register banks for the normal routine and interrupt routine.

The normal routine uses register banks 2 and 3 with RBE = 1 and RBS = 2. If the interrupt routine is for

one nested interrupt, use register bank 0 with RBE = 0, so that you do not have to save or restore the

registers. When two or more interrupts are nested, set RBE to 1, save the register bank by using the PUSH

BS instruction, and set RBS to 1 to select register bank 1.

(3) Use of a software interrupt for debugging

Setting an interrupt request flag using an instruction has the same effect as the occurrence of an interrupt.

Debug operation for irregular interrupts or concurrently occurring interrupts can be performed more

efficiently by setting the interrupt request flags using an instruction.

6.9 INTERRUPT APPLICATIONS

To use the interrupt function, a main program must:

(a) Set a desired interrupt enable flag (using the EI IExxx instruction)

(b) Select an active edge when INT0 or INT1 is used (set IM0 or IM1)

(d) Set the interrupt master enable flag (IME) using the EI instruction

In the interrupt routine, MBE and RBE are set by the vector table. However, when the interrupt specified

as having the higher priority is processed, the register bank must be saved and set.

To return from the interrupt routine, use the RETI instruction.

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CHAPTER 6 INTERRUPT AND TEST FUNCTIONS

(1) Interrupt enable/disable

<1> Reset

•

Interrupt disabled

<2> EI IE0

EI IET0

<3> EI

•

INT0 and INTT0 enabled

INTT0 enabled

<4> DI IE0

•

<5> DI

•

Interrupt disabled

<1> A RESET signal disables all interrupts.

<2> Interrupt enable flags are set by the EI IExxx instruction. At this stage, all interrupts are disabled.

<3> The interrupt master enable flag is set by the EI instruction. At this stage, INT0 and INTT0 are

enabled.

<4> An interrupt enable flag is cleared by the DI IExxx instruction to disable INT0.

<5> The DI instruction disables all interrupts.

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(2) Example of using INTBT, INT0 (falling edge active), and INTT0 without multiple interrupt processing

<1>

Reset

; RBE = 1, MBE = 0

<2> MOV A, #1

MOV IM0, A

CLR1 IRQ0

Status 0

; RBE = 0

<3> EI IEBT

EI IE0

EI IET0

•

<4> INT0

•

Status 1

Status 0

<5> RETI

<1> A RESET signal disables all interrupts, setting status 0.

<2> INT0 is set to be falling edge active.

<3> Interrupts are enabled by the EI and EI IExxx instructions.

<4> On the falling edge of INT0, the INT0 interrupt service program is started, status is set to 1, and all

interrupts are disabled.

<5> Control is returned from the interrupts by the RETI instruction, status 0 is set again, and interrupts

are enabled.

Remark If all the interrupts are used as having the lower priority as shown in this example, saving or

restoring the register bank is not necessary if RBE = 1 and RBS = 2 for the main program and

0 and 1 are used.

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CHAPTER 6 INTERRUPT AND TEST FUNCTIONS

(3) Nesting of interrupts with higher priority (INTBT has higher priority and INTT0 and INTCSI have

lower priority)

Reset

; RBE = 1, MBE = 0

SEL RB2

IEBT

IET0

IECSI

<1> MOV A, #9

MOV IPS, A

Status 0

; RBE = 0

; RBE = 1

Status 1

<4> SEL RB1

<2> INTT0

Status 2

<3> INTBT

<5> SEL RB2

RETI

Status 1

Status 0

RETI

<1> INTBT is specified as having the higher priority by setting of IPS, and the interrupt is enabled at the

same time.

<2> INTT0 service program is started when INTT0 with the lower priority occurs. Status 1 is set and the

other interrupts with the lower priority are disabled. RBE = 0 to select register bank 0.

<3> INTBT with the higher priority occurs. The level-two interrupts occurs. The status is changed to 0

and all the interrupts are disabled.

<4> RBE = 1 and RBS = 1 to select register bank 1 (only the registers used may be saved by the PUSH

instruction).

<5> RBS is returned to 2, and execution returns to the main program. The status is returned to 1.

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(4) Execution of held interrupts (interrupt requests when interrupts are disabled)

Reset

EI IE0

•

•

<1> INT0

•

<3> INTCSI

<2> EI

•

RETI

<4> EI IECSI

•

RETI

<1> If INT0 is set when interrupts are disabled, the interrupt request flag is held.

<2> When the interrupt is enabled by the EI instruction, the INT0 interrupt service program starts.

<3> Same as <1>

<4> When the held INTCSI flag is enabled, the INTCSI interrupt service program starts.

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CHAPTER 6 INTERRUPT AND TEST FUNCTIONS

(5) Execution of held interrupts – two interrupts with lower priority occur concurrently –

Reset

EI IET0

EI IE0

•

INT0

•

<1>

•

INTT0

•

<2> RETI

•

•

RETI

•

<1> When INT0 and INTT0 with the lower priority occur concurrently (during execution of the same

instruction), INT0, with a higher priority, is executed first. (INTT0 is held.)

<2> When the INT0 interrupt service program has been executed, the RETI instruction is executed to

start the interrupt service program for INTT0, which has been held.

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(6) Executing pending interrupt – interrupt occurs during interrupt processing (INTBT has higher

priority and INTT0 and INTCSI have lower priority) –

Reset

IEBT

IET0

IECSI

MOV A, #9

MOV IPS, A

PUSH rp

<2> INTCSI

POP rp

<3> RETI

INTT0

INTBT

<1>

<4> RETI

RETI

<1> When INTBT with the higher priority and INTT0 with the lower priority occur at the same time, the

processing of the interrupt with the higher priority is started (if there is no possibility that an interrupt

with the higher priority occurs while another interrupt with the higher priority is processed, DI IExx

is not necessary).

<2> When an interrupt with the lower priority occurs while the interrupt with the higher priority is executed,

the interrupt with the lower priority is kept pending.

<3> When the interrupt with the higher priority has been processed, INTCSI with the higher priority of

the pending interrupts is executed.

<4> When the processing of INTCSI has been completed, the pending INTT0 is processed.

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CHAPTER 6 INTERRUPT AND TEST FUNCTIONS

(7) Enabling of level-two interrupts (enabling level-two INTT0 and INT0 interrupts with INTCSI and INT4

handled as level-one interrupts)

Reset

EI IET0

EI IE0

Status 0

EI IECSI

EI IE4

<2> DI

CLR1 IST0

Status 1

•

IECSI

IE4

<1> INTCSI

Status 0

Status 0

<3> INTT0

Status 1

<4> RETI

Status 0

<5> EI IECSI

EI IE4

RETI

<1> When an INTCSI interrupt not allowed to be a level-two interrupt occurs, the INTCSI service program

starts, and status 1 is set.

<2> Status 0 is set by clearing IST0. INTCSI and INT4 not allowed to be level-two interrupts are disabled.

<3> When INTT0 allowed to be a level-two interrupt occurs, the level-two interrupt is executed, and status

1 is set to disable all interrupts.

<4> When INTT0 processing is completed, status 0 is set again.

<5> INTCSI and INT4 which have been disabled are enabled, then control returns.

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6.10 TEST FUNCTION

6.10.1 Test Sources

The µPD750008 has two test sources. INT2 provides two types of edge-detection-test inputs.

Table 6-5. Test Source

Test source

Internal/external

INT2

(detection of the rising edge of the signal input to the INT2 pin or that of External

the first falling edge of the signals input to KR0 to KR7)

INTW (signal from clock timer)

Internal

6.10.2 Hardware to Control Test Functions

(1) Test request flags, test enable flags

Test request flags (IRQxxx) are set to 1 when the corresponding test requests (INTxxx) are issued. Clear

the test request flags to 0 with the software once the test processing has been executed.

Test enable flags (IExxx) correspond to test request flags. The test enable flags enable the standby

release signal when they are set to 1. They disables the standby release signal when they are set to 0.

When both a test request flag and the corresponding test enable flag are set to 1, the standby release

signal is generated.

Table 6-6 shows the signals which set test request flags.

Table 6-6. Signals Setting Test Request Flags

Test request flag

Signals setting test request flags

Signal from the clock timer.

Test enable flag

IRQW

IRQ2

IEW

IE2

Detection of the rising edge of INT2/P12 pin input signal or

the first falling edge of the signals input to the KR0/P60 to

KR7/P73 pins. The detection edge is selected with the INT2

edge detection mode register (IM2).

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CHAPTER 6 INTERRUPT AND TEST FUNCTIONS

(2) INT2 and key interrupt (KR0 to KR7) hardware

Figure 6-10 shows the configuration of INT2 and KR0 to KR7.

The IRQ2 set signal is output in either of the following edge detection modes, which is selected with the

INT2 edge detection mode register (IM2).

(a) Detection of a rising edge on the INT2 input pin

IRQ2 is set when a rising edge is detected on the INT2 input pin.

(b) Detection of a falling edge on any of the KR0 to KR7 input pins (key interrupt)

One of the pins KR0 to KR7 is selected to be used for interrupt input with the INT2 edge detection

mode register (IM2). When a falling edge of one of input signals applied to the selected pin is detected,

IRQ2 is set.

Figure 6-11 shows the format of IM2. IM2 is set using a 4-bit manipulation instruction. When the RESET

signal is generated, all bits are cleared to 0, and the rising edge on INT2 is specified.

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CHAPTER 6 INTERRUPT AND TEST FUNCTIONS

Figure 6-11. Format of INT2 Edge Detection Mode Register (IM2)

Address

FB6H

Symbol

IM2

IM21

IM20

IM21

IM20

INT2 interrupt source

Interrupt input pin

INT2 (1)

Specifies rising edge of INT2 pin input.

KR4 - KR7 (4)

KR2 - KR7 (6)

KR0 - KR7 (8)

Specifies falling edge of any of KRx pin

inputs.

Cautions 1. When the edge detection mode register is modified, test request flags may be set in

some cases. So, disable test inputs before modifying the edge detection mode

test inputs.

2. When a low-level signal is applied to any of the pins subjected to falling edge detection,

IRQ2 is not set when a falling edge is detected on another pin.

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214

CHAPTER 7 STANDBY FUNCTION

The µPD750008 provides a standby function to reduce the power consumption by the system. The standby

function is available in the two modes: the STOP mode and HALT mode.

Differences between these two modes are as follows:

(1) STOP mode

In the STOP mode, the main system clock oscillator is stopped, and the entire system stops. The current

used by the CPU is reduced to quite a low level.

In addition, the contents of data memory can be preserved with a low supply voltage of down to V

1.8V, that is, this mode is effective to retain data memory with a very low current.

The STOP mode of the µPD750008 can be released by an interrupt request to enable intermittent

operations. However, when the STOP mode is released, a wait time is needed for stable oscillation. Select

the HALT mode when processing must be started immediately after an interrupt request.

(2) HALT mode

In the HALT mode, the CPU clock is stopped, but the oscillation of the system clock oscillator continues.

In this mode, the system uses more current than in the STOP mode. However, the HALT mode is suitable

for starting processing immediately after an interrupt request or for intermittent operations such as watch

operation.

In either mode, all contents of the registers, flags, and data memory that are present immediately before

the standby mode is set are preserved. In addition, the states of the output latches of the I/O ports and the

states of the output buffers are also preserved, so that the states of the I/O ports are to be processed to minimize

the power consumption of the entire system.

Cautions 1. The STOP mode can be used only for the main system clock. (Subsystem clock

generation cannot be terminated.) The HALT mode can be used for either the main

system clock or the subsystem clock.

2. If the STOP mode is set when main system clock f is used for clock timer operation,

the clock stops operating. For continued operation, the clock must be changed to

subsystem clock f before the STOP mode is set.

3. A lower power consumption and lower-voltage operation are enabled by switching

standby modes or switching CPU and system clocks. However, a switching time as

described in Section 5.2.3 is required before operation is started with a new clock after

the clock is selected with the control register. For this reason, when the clock

switching function is used together with a standby mode, the standby mode must be

set after a time needed for switching elapses.

4. Configure I/O ports for minimum power consumption in the stand by mode. Be sure

to connect signals which are high or low to input ports.

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7.1 SETTING OF STANDBY MODES AND OPERATION STATUS

Table 7-1. Operation Statuses in the Standby Mode

Mode

STOP mode

STOP instruction

HALT mode

HALT instruction

Item

Instruction for setting

Can be set only when operating on

the main system clock

Can be set either with the main

system clock or the subsystem clock

System clock for setting

Only the main system clock stops its

operation

Only the CPU clock F stops its

operation (oscillation continues)

Clock oscillator

Operation

status

Does not operate

Can operate only at main system

clock oscillation. (IRQBT is set at

reference time intervals.)

Basic interval

timer/watchdog

timer

Can operate only when the external

SCK input is selected for the serial

clock

Can operate only when external SCK

input is selected as the serial clock or

at main system clock oscillation.

Serial interface

Can operate only when TI0 pin input

is specified as the count clock or at

main system clock oscillation.

Timer/event

counter

Can operate only when the TI0 pin

input is selected for the count clock

Note 1

Does not operate

Can operate

Timer counter

Clock timer

Can operate

Can operate when f

the count clock

is selected as

INT1, INT2, and INT4 can operate.

Only INT0 cannot operate.

External interrupt

CPU

Note 2

Does not operate

Release signal

An interrupt request signal from hardware whose operation is enabled by the

interrupt enable flag or the generation of a RESET signal

Notes 1. Operation is possible only when the main system clock operates.

2. Operation is possible only when the noise eliminator is not selected by bit 2 of the edge detection

mode register (IM0) (when IM02 = 1).

A STOP instruction is used to set the STOP mode, and a HALT instruction is used to set the HALT mode.

(A STOP instruction sets bit 3 of PCC, and a HALT instruction sets bit 2 of PCC.)

STOP instruction or HALT instruction must always be followed by an NOP instruction.

When changing a CPU operation clock pulse with the low-order two bits of PCC, a time lag may occur from

the time when PCC is rewritten as shown in Table 5-5 to the time when the CPU clock signal is changed.

When changing an operation clock pulse before the standby mode or a CPU clock signal after the standby

mode is released, it is necessary to rewrite PCC and set the standby mode after as many machine cycles

as required to change the CPU clock pulse have elapsed.

In a standby mode, the contents of all registers and data memory that are stopped during the standby mode,

including general registers, flags, mode registers, and output latches, are retained.

Caution 1. When the STOP mode is set, the X1 input is internally connected to V

(ground

potential) to suppress leakage at the crystal oscillator circuitry. This means that the

STOP mode cannot be used with a system that uses an external clock.

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CHAPTER 7 STANDBY FUNCTION

Caution 2. Reset all the interrupt request flags before setting the standby mode. If an interrupt

source whose interrupt request flag and interrupt enable flag are both set exists, the

initiated standby mode is released immediately after it is set (see Figure 6-1). When

the STOP mode is set, however, the µPD750008 enters the HALT mode immediately

after the STOP instruction is executed, then returns to the operation mode after the

wait time specified by the BTM register has elapsed.

7.2 RELEASE OF THE STANDBY MODES

The STOP mode and HALT mode are released by a RESET signal or the generation of an interrupt request

signal that is enabled with the interrupt enable flag. Figure 7-1 shows how the STOP and HALT modes are

released.

Figure 7-1. Standby Mode Release Operation (1/2)

(a) Release of the STOP mode by RESET signal

STOP instruction

Wait^Note

RESET

signal

Operating

mode

Operating

mode

STOP mode

No oscillation

HALT mode

Oscillation

Clock

(b) Release of the STOP mode by the occurrence of an interrupt

Wait

(Time set by BTM)

STOP instruction

Standby

release

signal

Operating

mode

Operating

mode

STOP mode

No oscillation

HALT mode

Oscillation

Clock

Note The following two wait times can be selected by a mask option:

2 /f (21.8 ms at 6.00 MHz, 31.3 ms at 4.19 MHz)

2 /f (5.46 ms at 6.00 MHz, 7.81 ms at 4.19 MHz)

However, the µPD75P0016 does not have a mask option and its wait time is fixed to 2 /f .

Remark The dashed line indicates the case where the interrupt request that releases the standby mode

is accepted.

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µPD750008 USER'S MANUAL

Figure 7-1. Standby Mode Release Operation (2/2)

Wait^Note

HALT instruction

RESET

signal

Operating

mode

Operating

mode

HALT mode

Oscillation

Clock

(d) Release of the HALT mode by the occurrence of an interrupt

HALT instruction

Standby

release

signal

Operating mode

HALT mode

Operating mode

Oscillation

Clock

Note The following two wait times can be selected by a mask option:

2 /f (21.8 ms at 6.00 MHz, 31.3 ms at 4.19 MHz)

2 /f (5.46 ms at 6.00 MHz, 7.81 ms at 4.19 MHz)

However, the µPD75P0016 dose not have a mask option and its wait time is fixed to 2 /f .

Remark The dashed line indicates the case where the interrupt request that releases the standby mode

is accepted.

When the STOP mode is released by the occurrence of an interrupt, a wait time is determined by the basic

interval timer mode register (BTM). (See Table 7-2.)

A time required for stable oscillation varies with the type of resonator used and the supply voltage at the

time of STOP mode release. Accordingly, a wait time is to be selected according to each application, and

BTM is to be set before the STOP mode is set.

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CHAPTER 7 STANDBY FUNCTION

Table 7-2. Selection of a Wait Time with BTM

Note

Wait time

BTM3 BTM2 BTM1 BTM0

( ) indicates the value for f

6.00 MHz

( ) indicates the value for f

4.19 MHz

–

Approx. 2 /f (Approx. 175 ms)

Approx. 2 /f (Approx. 250 ms)

Approx. 2 /f (Approx. 31.3 ms)

Approx. 2 /f (Approx. 21.8 ms)

Approx. 2 /f (Approx. 7.81 ms)

Approx. 2 /f (Approx. 5.46 ms)

Approx. 2 /f (Approx. 1.95 ms)

Approx. 2 /f (Approx. 1.37 ms)

Other than above

Not to be set

Note This time does not include the time from the release of the STOP mode to the start of oscillation.

Caution The wait times used when the STOP mode is released do not include the time (a in Figure7-

2) required before clock oscillation is started following the release of the STOP mode,

regardless of whether the STOP mode is released by a RESET signal or the generation of

an interrupt.

Figure 7-2. Wait Time When the STOP Mode Is Released

STOP mode release

Waveform

at the X1 pin

V^SS

7.3 OPERATION AFTER A STANDBY MODE IS RELEASED

(1) If a standby mode is released by a RESET signal, normal reset operation is performed.

(2) If a standby mode is released by the occurrence of an interrupt request, the contents of the interrupt master

enable flag (IME) determines whether to perform a vectored interrupt when the CPU resumes instruction

execution.

(a) When IME = 0

If a standby mode is released, execution restarts with the instruction immediately following the

instruction used to set the standby mode.

The interrupt request flag is held.

(b) When IME = 1

If a standby mode is released, a vectored interrupt is executed after the two instructions are executed.

However, if the standby mode is released by INT2 or INTW (testable input), no vectored interrupt

occurs, and the same processing as (a) above is performed.

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µPD750008 USER'S MANUAL

7.4 SELECTION OF A MASK OPTION

For the standby function of the µPD750008, either of the following two values can be selected by a mask

option as the wait time during which the start of oscillation deferred from the generation of a RESET signal:

<1> 2 /f (21.8 ms at 6.00 MHz, 31.3 ms at 4.19 MHz)

<2> 2 /f (5.46 ms at 6.00 MHz, 7.81 ms at 4.19 MHz)

However, the µPD75P0016 dose not have a mask option and its wait time is fixed to 2 /f .

7.5 APPLICATIONS OF THE STANDBY MODES

When the standby modes are used, the following steps are used.

<1> Detect a standby mode setting factor such as power removal on an interrupt input or port input. (INT4

is useful for power removal detection.)

<2> Configure I/O ports for minimum current drain.

<3> Specify interrupts for releasing a standby mode. (INT4 is useful. All interrupt enable flags not used

for release are to be cleared.)

<4> Specify an operation to be performed after release. (IME is to be manipulated according to whether

interrupt processing is performed or not.)

<5> Specify a CPU clock to be used after release. (If the CPU clock is changed, required machine cycles

must elapse before the standby mode is set.)

<6> Select a wait time to be used when a standby mode is released.

<7> Set a standby mode using a STOP or HALT instruction.

A standby mode when combined with the system clock switch function enables a lower power consumption

and lower-voltage operation.

(1) Application of the STOP mode (at f = 4.19 MHz)

• The STOP mode is set on the falling edge of INT4, and is released on the rising edge of INT4. (INTBT

is not used.)

• All I/O ports have a high impedance.

• The INT0 and INTT0 interrupts are used for the program, but are not used to release the STOP mode.

• After the STOP mode is released, interrupts are enabled.

• After the STOP mode is released, the lowest-speed CPU clock is used for operation. Then, the CPU

clock is changed to the high-speed one after 250 ms.

• A wait time used when the STOP mode is released is about 31.3 ms.

• After the STOP mode is released, another wait time of 31.3 ms is used for stable power supply operation.

The P00/INT4 pin is checked twice to remove chattering.

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CHAPTER 7 STANDBY FUNCTION

V^DD

Voltage on V^DD

0 V

P00/INT4

Low-speed High-speed

operation operation

Wait

Operating mode

STOP mode

CPU operation

31.3 ms 31.3 ms

INT4

STOP instruction

(INT4 service program, MBE = 0)

VSUB4:

SKT

PORT0.0

; P00 = 1?

PDOWN

BTM.3

; Power-down

; Power-on

SET1

SKT

WAIT:

IRQBT

WAIT

; Wait for 31.3 ms.

SKT

PORT0.0

PDOWN

A,#0011B

PCC,A

XA.#xxH

PMGm,XA

IE0

; Chattering check

MOV

; Set high-speed mode.

; Set port mode register.

IET0

RETI

MOV

PDOWN:

A,#0

; Lowest-speed mode

PCC,A

XA,#00H

PMGA,XA

PMGB,XA

IE0

; I/O port high impedance

; Disable INT0 and INTT0

IET0

MOV

STOP

NOP

RETI

A,#1011B

BTM,A

; Wait time

31.3 ms

; Set STOP mode.

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µPD750008 USER'S MANUAL

(2) Application of the HALT mode (at f = 4.19 MHz)

• The main system clock is switched to the subsystem clock on the falling edge of INT4.

• The oscillation of the main system clock is stopped, and HALT mode is set.

• In the standby mode, intermittent operation is performed at intervals of 0.5 s.

• The subsystem clock is switched back to the main system clock on the rising edge of INT4.

• INTBT is not used.

VDD

Voltage on V^DD

0 V

P00/INT4

Intermittent operation

(HALT mode + low-speed operation)

Operating mode Operating mode

(low-speed)

(high-speed)

Operating mode

CPU operation

250 ms

INT4

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CHAPTER 7 STANDBY FUNCTION

(Initialization)

MOV

A,#0011B

PCC,A

XA,#05

WM,XA

IE4

MOV

; High-speed mode

; Subsystem clock

MOV

IEW

(Main routine)

SKT

; Enable interrupt

PORT0.0

; Power normal?

; Power-down mode

; Power normal?

HALT

NOP

SKTCLR

IRQW

MAIN

; Flag set for 0.5 second?

; NO

CALL

WATCH

; Clock subroutine

MAIN:

(INT4 service routine)

VINT4:

SKT

PORT0.0

PDOWN

SCC.3

; Power normal? MBE = 0

CLR1

MOV

SKT

; Start main system clock oscillation

A,#8

BTM,A

IRQBT

WAIT1

PORT0.0

PDOWN

SCC.0

WAIT1:

; Wait for 250 ms

SKT

; Chattering check

CLR1

RETI

; Switch to main system clock

PDOWN:

WAIT2:

SET1

MOV

INCS

SCC.0

A,#6

; Switch to subsystem clock

; Wait for 32 machine cycles

; Stop main system clock oscillation

WAIT2

SCC.3

SET1

RETI

Caution Before the system clock is changed from the main system clock to the subsystem clock,

a wait time sufficient for stable subsystem clock generation is required.

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224

CHAPTER 8 RESET FUNCTION

The µPD750008 is reset with the external reset signal (RESET) or the reset signal received from the basic

interval timer/watchdog timer. When either reset signal is input, the internal reset signal is generated. Figure

8-1 shows the configuration of the reset circuit.

Figure 8-1. Configuration of Reset Functions

RESET

Internal reset signal

Reset signal from basic

interval timer/watchdog timer

WDTM

Internal bus

When the RESET signal is generated, all hardware is initialized as indicated in Table 8-1. Figure 8-2 shows

the reset operation timing.

Figure 8-2. Reset Operation by Generation of RESET Signal

Wait^Note

RESET signal is generated

Operating mode or

standby mode

HALT mode

Operating mode

Internal reset operation

Note The following two wait times can be selected by a mask option:

2 /f (21.8 ms at 6.00 MHz, 31.3 ms at 4.19 MHz)

2 /f (5.46 ms at 6.00 MHz, 7.81 ms at 4.19 MHz)

However, the µPD75P0016 dose not have a mask option and its wait time is fixed to 2 /f .

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µPD750008 USER'S MANUAL

Table 8-1. Status of the Hardware after a Reset (1/2)

Generation of a RESET signal

in a standby mode

Generation of a RESET signal

during operation

Hardware

µPD750004

4 low-order bits at address

Program counter (PC)

0000H in program memory are 0000H in program memory are

set in PC bits 11 to 8, and the set in PC bits 11 to 8, and the

data at address 0001H are set data at address 0001H are set

in PC bits 7 to 0.

µPD750006,

µPD750008

5 low-order bits at address

0000H in program memory are 0000H in program memory are

set in PC bits 12 to 8, and the set in PC bits 12 to 8, and the

data at address 0001H are set data at address 0001H are set

in PC bits 7 to 0.

µPD75P0016

5 low-order bits at address

0000H in program memory are 0000H in program memory are

set in PC bits 13 to 8, and the set in PC bits 13 to 8, and the

data at address 0001H are set data at address 0001H are set

in PC bits 7 to 0.

Carry flag (CY)

Held

Undefined

PSW

Skip flags (SK0 to SK2)

Interrupt status flags (IST0, IST1)

Bank enable flags (MBE, RBE)

Bit 6 at address 0000H in

program memory is set in RBE, program memory is set in RBE,

and bit 7 is set in MBE.

Stack pointer (SP)

Undefined

1000B

Undefined

0, 0

1000B

Stack bank selection register (SBS)

Data memory (RAM)

Note

Held

General registers (X, A, H, L, D, E, B, C)

Bank selection register (MBS, RBS)

Held

0, 0

Counter (BT)

Basic

Undefined

interval

timer/watch-

dog timer

Mode register (BTM)

Watchdog timer enable flag

(WDTM)

Counter (T0)

Timer

event

counter

Modulo register (TMOD0)

Mode register (TM0)

TOE0, TOUT flip-flop

Counter (T1)

FFH

0, 0

Timer

counter

Modulo registers (TMOD1)

Mode register (TM1)

TOE1, TOUT flip-flop

Mode register (WM)

Shift register (SIO)

FFH

0, 0

Clock timer

Held

Undefined

Serial

interface

Operation mode register

(CSIM)

SBI control register (SBIC)

Slave address register (SVA)

Held

Undefined

Note Data of address 0F8H to 0FDH of the data memory becomes undefined when the RESET signal is

generated.

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CHAPTER 8 RESET FUNCTION

Table 8-1. Statuses of the Hardware after a Reset (2/2)

Generation of a RESET

signal in a standby mode

Generation of a RESET

signal during operation

Hardware

Processor clock control register

(PCC)

Clock

generator,

clock

output

circuit

System clock control register

(SCC)

Clock output mode register

(CLOM)

Sub-oscillator control register (SOS)

Interrupt request flag (IRQxxx)

Reset (0)

Interrupt

Reset (0)

Interrupt enable flag (IExxx)

Priority selection register (IPS)

INT0, INT1 and INT2 mode

registers (IM0, IM1, IM2)

0, 0, 0

Output buffer

Output latch

Digital

ports

Off

Clear (0)

I/O mode registers (PMGA,

PMGB, PMGC)

Pull-up resistor specification

Bit sequential buffers (BSB0 to BSB3)

Held

Undefined

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228

CHAPTER 9 WRITING TO AND VERIFYING PROGRAM MEMORY (PROM)

The program memory in the µPD75P0016 consists of a one-time PROM (16384 x 8 bits).

Writing to and verifying the contents of the one-time PROM is accomplished by using the pins shown in

the table below. Note that address inputs are not used; instead, the address is updated using the clock input

from the X1 pin.

Pin name

Function

Voltage is applied to this pin when writing to the program memory or verifying its

contents (normally V

electric potential).

X1, X2

Address update clock inputs used when writing to the program memory or verifying

its contents. The X2 pin is used to input the inverted signal of the X1 pin input.

MD0-MD3

Operation mode selection pins used when writing to the program memory or

verifying its contents.

P40 to P43

(low-order four bits)

P50 to P53

I/O pins for 8-bit data used when writing to the program memory or verifying

its contents.

(high-order four bits)

Power voltage is applied to this pin. During normal operation, 2.2 to 5.5 V should

be applied; +6 V should be applied when writing to the program memory or verifying

its contents.

Cautions 1. The µPD75P0016CU/GB does not have an erasure window, so the erasing with

ultraviolet radiation cannot be performed.

2. Handle the pins not used for writing to or verifying the program memory, as follows:

• Pins other than XT2: Connect these pins to V through pull-down resistors.

• XT2 pin: Open

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µPD75008 USER'S MANUAL

9.1 OPERATING MODES WHEN WRITING TO AND VERIFYING THE PROGRAM MEMORY

If +6 V is applied to the VDD pin and +12.5 V is applied to the V pin, the µPD75P0016 enters program

memory write/verify mode. The specific operating mode is then selected by the setting of the MD0 through

MD3 pins as listed in the table below.

Operating mode specification

Operating mode

MD0

MD1

MD2

MD3

+12.5 V

+6 V

Program memory address clear mode

Write mode

Verify mode

Program inhibit mode

Remark X indicates L or H.

9.2 WRITING TO THE PROGRAM MEMORY

The procedure for writing to program memory is described below; high-speed write is possible.

(1) Pull low all unused pins to V by means of resistors.

Bring X1 to low level.

(2) Apply 5 V to V

(3) Wait 10 µs.

and to V

(4) Select program memory address clear mode.

(5) Apply 6 V to V and 12.5 V to V

(6) Select program inhibit mode.

(7) Select write mode for 1 ms duration and write data.

(8) Select program inhibit mode.

(9) Select verify mode. If write is successful, proceed to step (10). If write fails, repeat steps (7) to (9).

(10) Perform additional write for (Number of repetitions of steps (7) to (9)) x 1 ms duration.

(11) Select program inhibit mode.

(12) Increment the program memory address by inputting four pulses on the X1 pin.

(13) Repeat steps (7) to (12) until the last address is reached.

(14) Select program memory address clear mode.

(15) Apply 5 V to V

and to V

(16) Turn the power off.

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CHAPTER 9 WRITING TO AND VERIFYING PROGRAM MEMORY (PROM)

The timing for steps (2) to (12) is shown below.

Repeat x times

Address

increment

Additional write

Write

Verify

VPP

VDD

VPP

VDD

VDD +1

VDD

P40-P43

P50-P53

Data input

Data output

Data input

MD0

(P30)

MD1

(P31)

MD2

(P32)

MD3

(P33)

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µPD75008 USER'S MANUAL

9.3 READING THE PROGRAM MEMORY

The procedure for reading the contents of program memory is described below. The read is performed

in the verify mode.

(1) Pull low all unused pins to V by means of resistors. Bring X1 to low level.

(2) Apply 5 V to V

(3) Wait 10 µs.

and V

(4) Select program memory address clear mode.

(5) Apply 6 V to V and 12.5 V to V

(6) Select program inhibit mode.

(7) Select verify mode. Data is output sequentially one address at a time for each cycle of four clock pulses

appearing on the X1 pin.

(8) Select program inhibit mode.

(9) Select program memory address clear mode.

(10) Apply 5 V to V

and to V

(11) Turn the power off.

The timing for steps (2) to (9) is shown below.

VPP

VDD

VDD+1

VDD

P40-P43

Data output

P50-P53

Data output

MD0

(P30)

MD1

(P31)

“L”

MD2

(P32)

MD3

(P33)

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CHAPTER 9 WRITING TO AND VERIFYING PROGRAM MEMORY (PROM)

9.4 SCREENING OF ONE-TIME PROM

Because of its structure, it is difficult for NEC to completely test the one-time PROM product before

shipment. It is therefore recommended that screening be performed to verify the PROM contents after the

necessary data has been written to the PROM and the product has been stored under the following conditions.

Storage Temperature

125°C

Storage Time

24 hours

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234

CHAPTER 10 MASK OPTION

10.1 PIN

The pins of the µPD750008 have the following mask options:

Table 10-1. Selecting Mask Option of Pin

Mask Option

Pull-up resistor can be connected in 1-bit units.

P40-P43

P50-P53

P40 through P43 (port 4) or P50 through P53 (port 5) can be connected with pull-up resistors by mask option.

The mask option can be specified in 1-bit units.

If the pull-up resistor is connected by mask option, port 4 or 5 goes high on reset. If the pull-up resistor

is not connected, the port goes into a high-impedance state on reset.

The ports of the µPD75P0016 do not have a mask option and is always open.

10.2 MASK OPTION OF STANDBY FUNCTION

The standby function of the µPD750008 allows you to select wait time by using a mask option. The wait

time is required for the CPU to return to the normal operation mode after the standby function has been

released by the RESET signal (for details, see Section 7.2).

The following two wait times can be selected:

<1> 2 /f (21.8 ms at f = 6.00 MHz, 31.3 ms at f = 4.19 MHz)

<2> 2 /f (5.46 ms at f = 6.00 MHz, 7.81 ms at f = 4.19 MHz)

The µPD75P0016 does not have a mask option and its wait time is fixed to 2 /f .

235

µPD750008 USER'S MANUAL

10.3 MASK OPTION FOR FEEDBACK RESISTOR OF SUBSYSTEM CLOCK

For the subsystem clock of the µPD750008, whether to enable the feedback resistor is selected by the mask

option.

<1> Enable the feedback resistor (switches on or off by software).

<2> Disable the feedback resistor (cuts by hardware).

To use the feedback resistor after selecting <1>, turn the feedback resistor on by setting SOS.0 to 0 (for

details, see (6) in Section 5.2.2).

Select <1> to use the subsystem clock.

For the µPD75P0016, the mask option need not be set; use of the feedback resistor is factory-set.

236

CHAPTER 11 INSTRUCTION SET

The instruction set of the µPD750008 is an improved and extended version of the 75X series instruction

set. This instruction set takes over the instruction set of the 75X series, having the following features:

(1) Bit manipulation instructions allowing a wide variety of applications

(2) Efficient 4-bit manipulation instructions

(3) Eight-bit instructions comparable to 8-bit microcomputers

(4) GETI instruction for reducing program sizes

(5) String-effect instructions and number system conversion instructions for increased program efficiency

(6) Table reference instructions suitable for successive references

(7) 1-byte relative branch instructions

(8) NEC standard mnemonics designed for clarity and readability

SeeSection 3.2 for the addressing modes applicable to data memory manipulation and register banks used

for instruction execution.

11.1 UNIQUE INSTRUCTIONS

This section outlines the unique instructions among the µPD750008 instruction set.

11.1.1 GETI Instruction

The GETI instruction converts any of the following instructions to a 1-byte instruction:

(a) Subroutine call instruction for the entire space

(b) Branch instruction for the entire space

instructions)

(d) A combination of two 1-byte instructions

The GETI instruction references the table located at addresses 0020H to 007FH in program memory, and

executes referenced 2-byte data as an instruction of (a), (b), (c), or (d) above. This means that 48 instructions

consisting of (a) to (d) can be converted to 1-byte instructions.

Thus the GETI instruction can be used to convert frequently used instructions of (a) to (d) to 1-byte

instructions to reduce the number of program bytes significantly.

237

µPD750008 USER'S MANUAL

11.1.2 Bit Manipulation Instructions

With the µPD750008, a variety of instructions are available for bit manipulation.

(a) Bit setting:

(b) Bit clearing:

(d) Bit testing:

SET1

CLR1

SKT

mem.bit

mem.bit*

mem.bit

mem.bit*

mem.bit

mem.bit*

mem.bit

mem.bit*

SKT

SKF

(e) Bit testing and clearing: SKTCLR mem.bit*

(f) Boolean operation:

AND1

OR1

CY,mem.bit*

XOR1

mem.bit* represents a bit address addressed by using a bit manipulation addressing mode (fmem.bit,

pmem.@L, or @H+mem.bit).

Particularly, all of these bit manipulation instructions can be used for the I/O ports, so that I/O port

manipulation can be performed in a very efficient manner.

11.1.3 String-Effect Instructions

With the µPD750008, two types of string-effect instructions are available.

(a) MOV A,#n4 or MOV XA,#n8

(b) MOV HL,#n8

"String effect" means the locating of these two types of instructions at contiguous addresses.

Example A0: MOV A,#0

A1: MOV A,#1

XA7: MOV XA,#07

When string-effect instructions are arranged as in this example, if execution starts at address A0, the

following two instructions are replaced with an NOP instruction. If execution starts at address A1, the following

one instruction is replaced with an NOP instruction. That is, only the instruction first executed is valid, and

any following instructions are processed as an NOP instruction.

By using string-effect instructions, a constant can be set in an accumulator (the A register or the XA register

pair) or data pointer (the HL register pair) more efficiently.

238

CHAPTER 11 INSTRUCTION SET

11.1.4 Number System Conversion Instructions

An application may need to convert the result of a 4-bit data addition or subtraction (performed in binary)

to a decimal number. A time-related application may require sexagesimal conversion.

For this reason, the instruction set of the µPD750008 contains number system conversion instructions for

converting the result of a 4-bit data addition or subtraction to a number in an arbitrary number system.

(a) Number system conversion for addition

Let m be a desired number system after conversion. The following combination of instructions adds

the contents of an accumulator to data in memory (HL), then converts the result of the addition to

number system m.

ADDS A,#16 – m

ADDC A,@HL ; A, CY <– A + (HL) + CY

ADDS A,#m

An overflow is set in the carry flag.

If the execution of the instruction ADDC A,@HL generates a carry, the next instruction ADDS A,#n4

is skipped. If no carry is generated, ADDS A,#n4 is executed. In this case, the skip function of this

instruction (ADDS A,#n4) is disabled, so that even if this addition generates a carry, the instruction

following this instruction is not skipped. Accordingly, programs can be written after ADDS A,#n4.

Example An accumulator is added to memory data in decimal.

ADDS A,#6

ADDC A,@HL

ADDS A,#10

; A,CY <– A + (HL) + CY

(b) Number system conversion for subtraction

Let m be a desired number system after conversion. The following combination of instructions

subtracts data in memory (HL) from the contents of an accumulator, then converts the result of the

subtraction to number system m.

SUBC A,@HL

ADDS A,#m

An underflow is set in the carry flag.

If the execution of the instruction SUBC A,@HL generates no borrow, the next instruction ADDS A,#n4

is skipped. If a borrow is generated, the instruction ADDS A, #n4 is executed. In this case, the skip

function of this instruction (ADDS A,#n4) is disabled, so that even if this addition generates a carry,

the instruction following this instruction is not skipped. Accordingly, programs can be written after

ADDS A,#n4.

239

µPD750008 USER'S MANUAL

11.1.5 Skip Instructions and the Number of Machine Cycles Required for a Skip

The instruction set of the µPD750008 is designed to organize a program by testing a condition with the

skip function.

When a skip instruction satisfies the skip condition, the immediately following instruction is skipped to

execute the instruction immediately after the skipped instruction.

A skip requires the following number of machine cycles:

(a) When the instruction (to be skipped) immediately following the skip instruction is a 3-byte instruction

(that is, the BR !addr, BRA !addr1, CALL !addr, or CALLA !addr1 instruction): 2 machine cycles

(b) When the instruction (to be skipped) immediately following the skip instruction is an instruction other

than the instructions described in (a) above: 1 machine cycle

240

CHAPTER 11 INSTRUCTION SET

11.2 INSTRUCTION SET AND OPERATION

(1) Operand identifier and description

The operand field of an instruction must contain an operand coded according to the description rule for

the operand identifier of the instruction. (Refer to RA75X Assembler Package User’s Manual:

Language (EEU-1343) for detailed information.) When there are multiple descriptions for an identifier,

one item is to be selected. The uppercase letters and + and – signs are keywords, which must be coded

as they appear.

For immediate data, a proper numeric value or label must be coded.

The abbreviations for register flags shown in Figure 3-7 can be coded as labels in place of mem, fmem,

pmem, and bit. (However, not all labels can be coded for the fmem and pmem. For details, see Table

3-1 and Figure 3-7)

Representation format

Description method

reg

reg1

X, A, B, C, D, E, H, L

X, B, C, D, E, H, L

XA, BC, DE, HL

BC, DE, HL

BC, DE

XA, BC, DE, HL, XA’, BC’, DE’, HL’

BC, DE, HL, XA’, BC’, DE’, HL’

rp1

rp2

rp’

rp’1

rpa

rpa1

HL, HL+, HL–, DE, DL

DE,DL

4-bit immediate data or label

8-bit immediate data or label

Note

mem

bit

8-bit immediate data or label

2-bit immediate data or label

fmem

pmem

FB0H-FBFH and FF0H-FFFH immediate data or label

FC0H-FFFH immediate data or label

addr,

0000H-0FFFH immediate data or label (µPD750004)

0000H-17FFH immediate data or label (µPD750006)

0000H-1FFFH immediate data or label (µPD750008)

0000H-3FFFH immediate data or label (µPD75P0016)

addr1(for MkII mode only)

caddr

faddr

taddr

12-bit immediate data or label

11-bit immediate data or label

20H-7FH immediate data (bit 0 = 0) or label

PORTn

IExxx

RBn

PORT0-PORT8

IEBT, IET0, IET1, IE0-IE2, IE4, IECSI, IEW

RB0-RB3

MBn

MB0, MB1, MB15

Note For mem, only even addresses can be coded for 8-bit data processing.

241

µPD750008 USER'S MANUAL

(2) Legend

A register; 4-bit accumulator

B register

C register

D register

E register

H register

L register

X register

XA:

BC:

DE:

HL:

XA’:

BC’:

DE’:

HL’:

PC:

SP:

CY:

PSW:

MBE:

RBE:

Extended register pair (XA’)

Extended register pair (BC’)

Extended register pair (DE’)

Extended register pair (HL’)

Program counter

Stack pointer

Carry flag, bit accumulator

Program status word

Memory bank enable flag

PORTn: Port n (n = 0 to 8)

IME:

IPS:

IExxx:

RBS:

MBS:

PCC:

Interrupt master enable flag

Interrupt priority specification register

Interrupt enable flag

Memory bank select register

Processor clock control register

Address/bit delimiter

(xx):

xxH:

Contents addressed by xx

Hexadecimal data

242

CHAPTER 11 INSTRUCTION SET

(3) Explanation of symbols used for the addressing area column

MB = MBE · MBS

(MBS = 0, 1, 15)

MB = 0

MBE = 0 : MB = 0

(00H – 7FH)

Data memory

addressing

MB = 15 (F80H – FFFH)

MBE = 1 : MB = MBS (MBS =0, 1, 15)

MB = 15, fmem = FB0H – FBFH,

FF0H – FFFH

MB = 15, pmem = FC0H – FFFH

µPD750004

µPD750006

µPD750008

µPD75P0016

addr, addr1 = 0000H – 0FFFH

addr, addr1 = 0000H – 17FFH

addr, addr1 = 0000H – 1FFFH

addr, addr1 = 0000H – 3FFFH

addr , addr1 = (Current PC) – 15 to (Current PC) – 1

(Current PC) + 2 to (Current PC) + 16

µPD750004

µPD750006

caddr = 0000H – 0FFFH

caddr = 0000H – 0FFFH (PC¹²= 0) or

1000H – 17FFH (PC¹²= 1)

µPD750008

caddr = 0000H – 0FFFH (PC¹²= 0) or

1000H – 1FFFH (PC¹²= 1)

Program memory

addressing

µPD75P0016

caddr = 0000H – 0FFFH (PC¹³, PC12 = 00B) or

1000H – 1FFFH (PC¹³, PC12 = 01B) or

2000H – 2FFFH (PC¹³, PC12 = 10B) or

3000H – 3FFFH (PC¹³, PC12 = 11B)

faddr = 0000H – 07FFH

10 taddr = 0020H – 007FH

11 For MkII mode only

addr1 = 0000H – 0FFFH (µPD750004)

0000H – 17FFH (µPD750006)

0000H – 1FFFH (µPD750008)

0000H – 3FFFH (µPD75P0016)

Remarks 1. MB represents an accessible memory bank.

2. For 2, MB = 0 regardless of the setting of MBE and MBS.

3. For 4 and 5, MB = 15 regardless of the setting of MBE and MBS.

4. Each of 6 to 10 indicates an addressable area.

243

µPD750008 USER'S MANUAL

(4) Explanation of the machine cycle column

S represents the number of machine cycles required when a skip instruction with the skip function performs

a skip operation. S assumes one of the following values:

• When no skip operation is performed: S = 0

• When a 1-byte instruction or 2-byte instruction is skipped: S = 1

Note

• When a 3-byte instruction

is skipped: S = 2

Note 3-byte instruction: BR !addr, BRA !addr1, CALL !addr, and CALLA !addr1 instructions

Caution The GETI instruction is skipped in one machine cycle.

One machine cycle is equal to one cycle (t ) of the CPU clock (F), and four different machine cycles are

available for selection according to the PCC setting. (See Figure 5-12.)

244

CHAPTER 11 INSTRUCTION SET

struc-

tion

Number

bytes

Address-

ing

area

Mne-

monic

Machine

cycle

Operation

Skip condition

String-effect A

MOV

A,#n4

A <– n4

reg1,#n4

XA,#n8

HL,#n8

rp2,#n8

A,@HL

A,@HL+

A,@HL–

A,@rpa1

XA,@HL

@HL,A

@HL,XA

A,mem

XA,mem

mem,A

mem,XA

A,reg

reg1 <– n4

XA <– n8

String-effect A

String-effect B

HL <– n8

rp2 <– n8

A <– (HL)

2+S

A <– (HL), then L <– L+1

A <– (HL), then L <– L–1

A <– (rpa1)

L=0

L=FH

XA <– (HL)

(HL) <– A

(HL) <– XA

A <– (mem)

XA <– (mem)

(mem) <– A

(mem) <– XA

A <– reg

XA,rp’

XA <– rp’

reg1,A

reg1 <– A

rp’1,XA

A,@HL

A,@HL+

A,@HL–

A,@rpa1

XA,@HL

A,mem

XA,mem

A,reg1

rp’1 <– XA

XCH

A <–> (HL)

2+S

A <–> (HL), then L <- L+1

A <–> (HL), then L <- L–1

A <–> (rpa1)

XA <–> (HL)

A <–> (mem)

XA <–> (mem)

A <–> reg1

L=0

L=FH

XA,rp’

XA <–> rp’

245

µPD750008 USER'S MANUAL

In-

struc-

tion

Number

bytes

Address-

ing

area

Mne-

monic

Machine

cycle

Operand

Operation

Skip condition

MOVT

XA,@PCDE

• µPD750004

XA <– (PC

+DE)

11-8

ROM

• µPD750006, µPD750008

XA <– (PC

+DE)

12-8

ROM

• µPD75P0016

XA <– (PC

+DE)

+XA)

13-8

XA,@PCXA

• µPD750004

XA <– (PC

11-8

• µPD750006, µPD750008

XA <– (PC

+XA)

12-8

ROM

• µPD75P0016

XA <– (PC +XA)

13-8

ROM

Note

XA,@BCDE

XA,@BCXA

CY,fmem.bit

CY,pmem.@L

CY,@H+mem.bit

fmem.bit,CY

pmem.@L,CY

@H+mem.bit,CY

A,#n4

XA <– (BCDE)

XA <– (BCXA)

ROM

Note

MOV1

CY <– (fmem.bit)

CY <– (pmem +L .bit(L ))

7-2 3-2

1-0

CY <– (H+mem .bit)

3-0

(fmem.bit) <– CY

(pmem +L .bit(L )) <– CY

7-2 3-2 1-0

(H+mem .bit) <– CY

3-0

ADDS

1+S

2+S

1+S

2+S

A <– A+n4

carry

XA,#n8

XA <– XA+n8

carry

A,@HL

A <– A+(HL)

XA,rp’

XA <– XA+rp’

rp’1,XA

rp’1 <– rp’1+XA

A,CY <– A+(HL)+CY

XA,CY <– XA+rp’+CY

rp’1,CY <– rp’1+XA+CY

A <– A–(HL)

ADDC

SUBS

SUBC

A,@HL

XA,rp’

rp’1,XA

A,@HL

1+S

2+S

borrow

XA,rp’

XA <– XA–rp’

rp’1,XA

rp’1 <– rp’1–XA

A,CY <– A–(HL)–CY

XA,CY <– XA–rp’–CY

rp’1,CY <– rp’1–XA–CY

A,@HL

XA,rp’

rp’1,XA

Note Set register B to 0 in the µPD750004. Only the LSB is valid in register B in the µPD750006 and

µPD750008. Only the low-order two bits are valid in the µPD75P0016.

246

CHAPTER 11 INSTRUCTION SET

In-

struc-

tion

Number

bytes

Address-

ing

area

Mne-

monic

Machine

cycle

Operand

Operation

Skip condition

AND

A,#n4

A <– A n4

A,@HL

XA,rp’

rp’1,XA

A,#n4

A,@HL

XA,rp’

rp’1,XA

A,#n4

A,@HL

XA,rp’

rp’1,XA

A <– A (HL)

XA <– XA rp’

rp’1 <– rp’1 XA

A <– A n4

A <– A (HL)

XA <– X A rp’

rp’1 <- rp’1 XA

A <– A n4

XOR

A <– A (HL)

XA <– XA rp’

rp’1 <– rp’1 XA

RORC

NOT

CY <– A , A <– CY, A

<– A

n-1 n

A <– A

INCS

reg

1+S

2+S

1+S

2+S

1+S

2+S

reg <– reg+1

rp1 <– rp1+1

(HL) <– (HL)+1

(mem) <– (mem)+1

reg <– reg–1

rp’ <– rp’–1

reg=0

rp1

rp1=00H

(HL)=0

@HL

mem

reg

(mem)=0

reg=FH

rp’=FFH

reg=n4

(HL)=n4

A=(HL)

XA=(HL)

A=reg

DECS

SKE

rp’

reg,#n4

@HL,#n4

A,@HL

XA,@HL

A,reg

XA,rp’

Skip if reg=n4

Skip if (HL)=n4

Skip if A=(HL)

Skip if XA=(HL)

Skip if A=reg

Skip if XA=rp’

CY <– 1

XA=rp’

SET1

CLR1

SKT

CY <– 0

1+S

Skip if CY=1

CY <– CY

CY=1

NOT1

247

µPD750008 USER'S MANUAL

struc-

tion

Number

bytes

Address-

ing

area

Mne-

monic

Machine

cycle

Operand

Operation

Skip condition

SET1

mem.bit

(mem.bit) <– 1

(fmem.bit) <– 1

(pmem +L .bit(L )) <– 1

fmem.bit

pmem.@L

@H+mem.bit

mem.bit

7-2

3-2

1-0

(H+mem .bit) <– 1

3-0

CLR1

SKT

(mem.bit) <– 0

(fmem.bit) <– 0

fmem.bit

pmem.@L

@H+mem.bit

mem.bit

(pmem +L .bit(L )) <– 0

7-2 3-2 1-0

(H+mem .bit) <– 0

3-0

2+S

Skip if (mem.bit)=1

Skip if (fmem.bit)=1

(mem.bit)=1

fmem.bit

(fmem.bit)=1

(pmem.@L)=1

(@H+mem.bit)=1

(mem.bit)=0

pmem.@L

@H+mem.bit

mem.bit

Skip if (pmem +L .bit(L ))=1

7-2 3-2 1-0

Skip if (H+mem .bit)=1

3-0

SKF

Skip if (mem.bit)=0

Skip if (fmem.bit)=0

fmem.bit

(fmem.bit)=0

(pmem.@L)=0

(@H+mem.bit)=0

(fmem.bit)=1

(pmem.@L)=1

pmem.@L

@H+mem.bit

Skip if (pmem +L .bit(L ))=0

7-2 3-2 1-0

Skip if (H+mem .bit)=0

3-0

SKTCLR fmem.bit

Skip if (fmem.bit)=1 and clear

pmem.@L

Skip if (pmem +L .bit(L ))

7-2 3-2 1-0

=1 and clear

@H+mem.bit

2+S

Skip if (H+mem .bit)=1

(@H+mem.bit)=1

3-0

and clear

AND1

OR1

CY,fmem.bit

CY <– CY (fmem.bit)

CY <– CY

CY,pmem.@L

(pmem +L .bit(L ))

7-2

3-2

1-0

CY,@H+mem.bit

CY,fmem.bit

CY <– CY Y (H+mem .bit)

3-0

CY <– CY (fmem.bit)

CY <– CY

CY,pmem.@L

(pmem +L .bit(L ))

7-2

3-2

1-0

CY,@H+mem.bit

CY,fmem.bit

CY <– CY (H+mem .bit)

3-0

XOR1

CY <– CY (fmem.bit)

CY <– CY

CY,pmem.@L

(pmem +L .bit(L ))

7-2

3-2

1-0

CY,@H+mem.bit

CY <– CY (H+mem .bit)

3-0

248

CHAPTER 11 INSTRUCTION SET

struc-

tion

Number

bytes

Address-

ing

area

Mne-

monic

Machine

cycle

Operand

Operation

Skip condition

addr

—

• µPD750004

PC <– addr

11-0

The assembler selects the most

adequate instruction from

instructions below.

• BR !addr

• BR $addr

• BRCB !caddr

• µPD750006, µPD750008

<– addr

12-0

The assembler selects the most

adequate instruction from

instructions below.

• BR !addr

• BRCB !caddr

• BR $addr

• µPD75P0016

<– addr

13-0

The assembler selects the most

adequate instruction from

instructions below.

• BR !addr

• BRCB !caddr

• BR $addr

Note

addr1

—

• µPD750004

<– addr1

11-0

The assembler selects the most

adequate instruction from

instructions below.

• BRA !addr1

• BR !addr

• BRCB !caddr

• BR $addr1

• µPD750006, µPD750008

<– addr1

12-0

The assembler selects the most

adequate instruction from

instructions below.

• BRA !addr1

• BR !addr

• BRCB !caddr

• BR $addr1

• µPD75P0016

<– addr1

13-0

The assembler selects the most

adequate instruction from

instructions below.

• BRA !addr1

• BR !addr

• BRCB !caddr

• BR $addr1

Note The shaded portion is supported in Mk II mode only.

249

µPD750008 USER'S MANUAL

struc-

tion

Number

bytes

Address-

ing

area

Mne-

monic

Machine

cycle

Operand

!addr

Operation

Skip condition

• µPD750004

PC <– addr

11-0

• µPD750006, µPD750008

PC <– addr

12-0

• µPD75P0016

PC <– addr

13-0

$addr

$addr1

PCDE

PCXA

BCDE

• µPD750004

PC <– addr

11-0

• µPD750006, µPD750008

PC <– addr

12-0

• µPD75P0016

PC <– addr

13-0

• µPD750004

PC <– addr1

11-0

• µPD750006, µPD750008

PC <– addr1

12-0

• µPD75P0016

PC <– addr1

13-0

• µPD750004

PC <– PC

+DE

11-8

11-0

• µPD750006, µPD750008

<– PC

+DE

+XA

12-0

12-8

• µPD75P0016

<– PC

13-0

13-8

11-8

• µPD750004

PC <– PC

11-0

• µPD750006, µPD750008

<– PC

+XA

12-0

12-8

• µPD75P0016

PC <– PC

13-0

13-8

• µPD750004

PC <– BCDE

Note 1

11-0

• µPD750006, µPD750008

Note 2

<– BCDE

12-0

• µPD75P0016

PC <– BCDE

Note 3

13-0

Note 1. Set register B to 0.

2. Only the LSB is valid in register B.

3. Only the low-order two bits are valid in register B.

250

CHAPTER 11 INSTRUCTION SET

struc-

tion

Number

bytes

Address-

ing

area

Mne-

monic

Machine

cycle

Operand

BCXA

Operation

Skip condition

• µPD750004

PC <– BCXA

Note 1

11-0

• µPD750006, µPD750008

Note 2

<– BCXA

12-0

• µPD75P0016

Note 3

<– BCXA

13-0

Note 1

BRA

!addr1

!caddr

!addr1

• µPD750004

PC <– addr

11-0

• µPD750006, µPD750008

PC <– addr

12-0

• µPD75P0016

PC <– addr1

13-0

BRCB

• µPD750004

PC <– caddr

11-0

• µPD750006, µPD750008

PC <– PC +caddr

12-0

11-0

• µPD75P0016

PC <– PC

+caddr

11-0

13-0

13, 12

Note 2

CALLA

• µPD750004

(SP–2) <– x, x, MBE,RBE

(SP–6)(SP–3)(SP–4) <– PC

(SP–5) <– 0, 0, 0, 0

11-0

<– addr, SP <– SP–6

11-0

• µPD750006, µPD750008

(SP–2) <– x, x, MBE,RBE

(SP–6)(SP–3)(SP–4) <– PC

11-0

(SP–5) <– 0, 0, 0, PC

<– addr, SP <– SP–6

12-0

• µPD75P0016

(SP–2) <– x, x, MBE,RBE

(SP–6)(SP–3)(SP–4) <– PC

11-0

(SP–5) <– 0, 0, PC , PC

<– addr1, SP <– SP–6

13-0

Note 1. The shaded portion is supported in Mk II mode only.

2. The shaded portion is supported in Mk II mode only. The other portions are supported in Mk

I mode only.

251

µPD750008 USER'S MANUAL

struc-

tion

Number

bytes

Address-

ing

area

Mne-

monic

Machine

cycle

Operand

!addr

Operation

Skip condition

CALL^Note

• µPD750004

(SP–3) <– MBE,RBE, 0, 0

(SP–4)(SP–1)(SP–2) <– PC

11-0

<– addr, SP <– SP–4

11-0

• µPD750006, µPD750008

(SP–3) <– MBE,RBE, 0, PC

(SP–4)(SP–1)(SP–2) <– PC

11-0

<– addr, SP <– SP–4

12-0

• µPD75P0016

(SP–3) <– MBE,RBE, PC , PC

11-0

(SP–4)(SP–1)(SP–2) <– PC

PC <– addr1, SP <– SP–4

13-0

• µPD750004

(SP–2) <– x, x, MBE,RBE

(SP–6)(SP–3)(SP–4) <– PC

(SP–5) <– 0, 0, 0, 0

11-0

<– addr, SP <– SP–6

11-0

• µPD750006, µPD750008

(SP–2) <– x, x, MBE,RBE

(SP–6)(SP–3)(SP–4) <– PC

(SP–5) <– 0, 0, 0, PC

<– addr, SP <– SP–6

12-0

• µPD75P0016

(SP–2) <– x, x, MBE,RBE

(SP–6)(SP–3)(SP–4) <– PC

11-0

(SP–5) <– 0, 0, PC , PC

<– addr, SP <– SP–6

13-0

Note

CALLF

!faddr

• µPD750004

(SP–3) <– MBE,RBE, 0, 0

(SP–4)(SP–1)(SP–2) <– PC

<– 0+faddr, SP <– SP–4

11-0

• µPD750006, µPD750008

(SP–3) <– MBE,RBE, 0, PC

(SP–4)(SP–1)(SP–2) <– PC

11-0

<– 00+faddr, SP <– SP–4

12-0

• µPD75P0016

(SP–3) <– MBE,RBE, PC , PC

11-0

(SP–4)(SP–1)(SP–2) <– PC

PC <– 000+faddr, SP <– SP–4

13-0

Note The shaded portion is supported in Mk II mode only. The other portions are supported in Mk I mode

only.

252

CHAPTER 11 INSTRUCTION SET

struc-

tion

Number

bytes

Address-

ing

area

Mne-

monic

Machine

cycle

Operand

!faddr

Operation

Skip condition

Note

CALLF

• µPD750004

(SP–2) –> x, x, MBE,RBE

(SP–6)(SP–3)(SP–4) <– PC

(SP–5) <– 0, 0, 0, 0

11-0

<– 0+faddr, SP <– SP–6

11-0

• µPD750006, µPD750008

(SP–2) –> x, x, MBE,RBE

(SP–6)(SP–3)(SP–4) <– PC

11-0

(SP–5) <– 0, 0, 0, PC

<– 00+faddr, SP <– SP–6

12-0

• µPD75P0016

(SP–2) <– x, x, MBE,RBE

(SP–6)(SP–3)(SP–4) <– PC

11-0

(SP–5) <– 0, 0, PC , PC

<– 000+faddr, SP <– SP–6

13-0

Note

RET

• µPD750004

PC <– (SP)(SP+3)(SP+2)

11-0

MBE,RBE, 0, 0 <– (SP+1), SP <– SP+4

• µPD750006, µPD750008

<– (SP)(SP+3)(SP+2)

11-0

MBE,RBE, 0, PC <– (SP+1)

SP <– SP+4

• µPD75P0016

<– (SP)(SP+3)(SP+2)

11-0

MBE,RBE, PC , PC <– (SP+1)

SP <– SP+4

• µPD750004

x, x, MBE, RBE <– (SP+4)

0, 0, 0, 0 <– (SP+1)

<– (SP)(SP+3)(SP+2)

11-0

SP <– SP+6

• µPD750006, µPD750008

x, x, MBE, RBE <– (SP+4)

MBE,0, 0, PC <– (SP+1)

<– (SP)(SP+3)(SP+2)

11-0

SP <– SP+6

• µPD75P0016

x, x, MBE, RBE <– (SP+4)

0,0, PC , PC <– (SP+1)

<– (SP)(SP+3)(SP+2)

11-0

SP <– SP+6

Note The shaded portion is supported in Mk II mode only. The other portions are supported in Mk I mode

only.

253

µPD750008 USER'S MANUAL

struc-

tion

Number

bytes

Address-

ing

area

Mne-

monic

Machine

cycle

Operand

Operation

Skip condition

Unconditionally

Note

RETS

3+S

• µPD750004

MBE, RBE, 0, 0 <– (SP+1)

PC <– (SP)(SP+3)(SP+2)

11-0

SP <– SP+4

Then skip unconditionally

• µPD750006, µPD750008

MBE, 0, 0, PC <– (SP+1)

<– (SP)(SP+3)(SP+2)

11-0

SP <– SP+4

Then skip unconditionally

• µPD75P0016

MBE, RBE, PC , PC <– (SP+1)

<– (SP)(SP+3)(SP+2)

11-0

SP <– SP+4

Then skip unconditionally

3+S

• µPD750004

0, 0, 0, 0 <– (SP+1)

<– (SP)(SP+3)(SP+2)

11-0

x, x, MBE, RBE <– (SP+4)

SP <– SP+6

Then skip unconditionally

• µPD750006, µPD750008

0, 0, 0, PC <– (SP+1)

<– (SP)(SP+3)(SP+2)

11-0

x, x, MBE, RBE <– (SP+4)

SP <– SP+6

Then skip unconditionally

• µPD75P0016

0, 0, PC , PC <– (SP+1)

<– (SP)(SP+3)(SP+2)

11-0

x, x, MBE, RBE <– (SP+4)

SP <– SP+6

Then skip unconditionally

Note

RETI

• µPD750004

Unconditionally

MBE, RBE, 0, 0 <– (SP+1)

<– (SP)(SP+3)(SP+2)

11-0

PSW <– (SP+4)(SP+5), SP <– SP+6

• µPD750006, µPD750008

MBE, RBE, 0, PC <– (SP+1)

<– (SP)(SP+3)(SP+2)

11-0

PSW <– (SP+4)(SP+5), SP <– SP+6

• µPD75P0016

MBE, RBE, PC , PC <– (SP+1)

<– (SP)(SP+3)(SP+2)

11-0

PSW <– (SP+4)(SP+5), SP <– SP+6

Note The shaded portion is supported in Mk II mode only. The other portions are supported in Mk I mode

only.

254

CHAPTER 11 INSTRUCTION SET

struc-

tion

Number

bytes

Address-

ing

area

Mne-

monic

Machine

cycle

Operand

Operation

Skip condition

Note 1

RETI

• µPD750004

0, 0, 0, 0 <– (SP+1)

PC <– (SP)(SP+3)(SP+2)

11-0

PSW <– (SP+4)(SP+5), SP <– SP+6

• µPD750006, µPD750008

0, 0, 0, PC <– (SP+1)

<– (SP)(SP+3)(SP+2)

11-0

PSW <– (SP+4)(SP+5), SP <– SP+6

• µPD75P0016

0, 0, PC , PC <– (SP+1)

<– (SP)(SP+3)(SP+2)

11-0

PSW <– (SP+4)(SP+5), SP <– SP+6

PUSH

POP

(SP–1)(SP–2) <– rp, SP <– SP–2

(SP–1) <– MBS, (SP–2) <– RBS,

SP <– SP–2

rp <– (SP+1)(SP), SP <– SP+2

MBS <– (SP+1), RBS <– (SP),

SP <– SP+2

IME(IPS.3) <– 1

IExxx <– 1

IExxx

IME(IPS.3) <– 0

IExxx <– 0

Note 2

A,PORT

A <– PORT (n=0 – 8)

XA,PORT

XA <– PORT , PORT (n=4, 6)

n+1

OUT^{Note 2}

PORT ,A

PORT <- A (n=2 - 8)

PORT ,XA

PORT ,PORT <– XA (n=4, 6)

n+1

HALT

STOP

NOP

Set HALT Mode (PCC.2 <– 1)

Set STOP Mode (PCC.3 <– 1)

No Operation

Note 1. The shaded portion is supported in Mk II mode only. The other portions are

supported in Mk I mode only.

2. MBE = 0, or MBE = 1 and MBS = 15 must be set when an IN/OUT instruction is

executed.

255

µPD750008 USER'S MANUAL

struc-

tion

Number

bytes

Address-

ing

area

Mne-

monic

Machine

cycle

Operand

Operation

Skip condition

SEL

RBn

RBS <– n (n=0 - 3)

MBn

MBS <– n (n=0, 1, 15)

Note

GETI

taddr

• µPD750004

When the TBR instruction is used

<– (taddr) +(taddr+1)

11-0

3-0

When the TCALL instruction is used

(SP–4)(SP–1)(SP–2) <– PC

(SP–3) <– MBE, RBE, 0, 0

11-0

<– (taddr) +(taddr+1)

11-0

3-0

SP <– SP–4

When an instruction other than

the TBR or TCALL instruction is

used

Depends on the

referenced

instruction

Execution of (taddr)(taddr+1)

instruction

• µPD750006, µPD750008

When the TBR instruction is used

<– (taddr) +(taddr+1)

12-0

4-0

When the TCALL instruction is used

(SP–4)(SP–1)(SP–2) <- PC

11-0

(SP–3) <– MBE, RBE, 0, PC

<– (taddr) +(taddr+1)

12-0

4-0

SP <– SP–4

When an instruction other than

the TBR or TCALL instruction is

used

Depends on the

referenced

instruction

Execution of (taddr)(taddr+1)

instruction

• µPD75P0016

When the TBR instruction is used

<– (taddr) +(taddr+1)

13-0

5-0

When the TCALL instruction is used

(SP–4)(SP–1)(SP–2) <- PC

11-0

(SP–3) <– MBE, RBE, PC , PC

<– (taddr) +(taddr+1)

13-0

5-0

SP <– SP–4

When an instruction other than

the TBR or TCALL instruction is

used

Depends on the

referenced

instruction

Execution of (taddr)(taddr+1)

instruction

Note The TBR and TCALL instructions are assembler pseudo instructions to define tables used for GETI

instructions.

256

CHAPTER 11 INSTRUCTION SET

struc-

tion

Number

bytes

Address-

ing

area

Mne-

monic

Machine

cycle

Operand

Operation

Skip condition

Notes1, 2

GETI

taddr

• µPD750004

When the TBR instruction is used

PC <– (taddr) +(taddr+1)

11-0

3-0

When the TCALL instruction is used

(SP–6)(SP–3)(SP–4) <– PC

(SP–5) <– 0, 0, 0, 0

11-0

(SP–2) <– x, x, MBE, RBE

<– (taddr) +(taddr+1)

11-0

3-0

SP <– SP–6

When an instruction other than

the TBR or TCALL instruction is

used

Depends on the

referenced

instruction

Execution of (taddr)(taddr+1)

instruction

• µPD750006, µPD750008

When the TBR instruction is used

<– (taddr) +(taddr+1)

12-0

4-0

When the TCALL instruction is used

(SP–6)(SP–3)(SP–4) <– PC

11-0

(SP–5) <– 0, 0, 0, PC

(SP–2) <– x, x, MBE, RBE

PC <– (taddr) +(taddr+1)

12-0

4-0

SP <– SP–6

When an instruction other than

the TBR or TCALL instruction is

used

Depends on the

referenced

instruction

Execution of (taddr)(taddr+1)

instruction

• µPD75P0016

When the TBR instruction is used

<– (taddr) +(taddr+1)

13-0

5-0

When the TCALL instruction is used

(SP–6)(SP–3)(SP–4) <– PC

11-0

(SP–5) <– 0, 0, PC , PC

(SP–2) <– x, x, MBE, RBE

PC <– (taddr) +(taddr+1)

13-0

5-0

SP <– SP–6

When an instruction other than

the TBR or TCALL instruction is

used

Depends on the

referenced

instruction

Execution of (taddr)(taddr+1)

instruction

Notes 1. The shaded portion is supported in Mk II mode only. The other portions are

supported in Mk I mode only.

2. The TBR and TCALL instructions are assembler pseudo instructions to define tables used for

GETI instructions.

257

µPD750008 USER'S MANUAL

11.3 INSTRUCTION CODES OF EACH INSTRUCTION

(1) Explanations of the symbols for the instruction codes

R2 R1 R0 reg

P2 P1 P0

reg-pair

XA'

HL'

reg

rp'

reg1

rp'1

DE'

BC'

Q2 Q1 Q0 addressing

P2 P1

reg-pair

@HL

@HL+

@HL–

@DE

@DL

rp1

@rpa

@rpa1

rp2

N5 N2 N1 N⁰

IExxx

IEBT

IEW

IET0

IECSI

IE0

IE2

IE4

IET1

IE1

: Immediate data for n4 or n8

D : Immediate data for mem

B : Immediate data for bit

N : Immediate data for n or IExxx

T : Immediate data for taddr x 1/2

A : Immediate data for the address (2 to 16) relative to branch destination address minus one

S : Immediate data for the one’s complement of the address (15 to 1) relative to the branch destination

address

258

CHAPTER 11 INSTRUCTION SET

(2) Bit manipulation addressing instruction codes

in the operand field indicates that there are three types of bit manipulation addressing, fmem.bit,

pmem.@L, and @H+mem.bit.

The table below lists the second byte

of an instruction code corresponding to the above addressing.

Second byte of instruction code

Accessible bits

FB0H-FBFH manipulatable bits

fmem.bit

FF0H-FFFH manipulatable bits

pmem.@L

FC0H-FFFH manipulatable bits

@H+mem.bit

Manipulatable bits of accessible memory bank

B : Immediate data for bit

F : Immediate data for fmem (Low-order four bits of address)

G : Immediate data for pmem (Bits 2 to 5 of address)

D : Immediate data for mem (Low-order four bits of address)

259

µPD750008 USER'S MANUAL

Instruction code

Mne-

monic

Instruction

Transfer

Operand

MOV

A,#n4

reg1,#n4

rp,#n8

R R R

A,@rpa1

XA,@HL

@HL,A

Q Q Q

@HL,XA

A,mem

D D D D D D D D

XA,mem

mem,A

D D D D D D D 0

D D D D D D D D

mem,XA

A,reg

D D D D D D D 0

R R R

XA,rp’

reg1,A

R R R

rp’1,XA

XCH

A,@rpa1

XA,@HL

A,mem

Q Q Q

D D D D D D D D

XA,mem

A,reg1

D D D D D D D 0

R R R

XA,rp’

MOVT

MOV1

XA,@PCDE

XA,@PCXA

XA,@BCXA

XA,@BCDE

Table

reference

CY,

Bit

transfer

,CY

260

CHAPTER 11 INSTRUCTION SET

Instruction code

Mne-

monic

Instruction

Operand

Arithmetic/ ADDS

logical

A,#n4

XA,#n8

A,@HL

XA,rp’

rp’1,XA

A,@HL

XA,rp’

rp’1,XA

A,@HL

XA,rp’

rp’1,XA

A,@HL

XA,rp’

rp’1,XA

A,#n4

ADDC

SUBS

SUBC

AND

A,@HL

XA,rp’

rp’1,XA

A,#n4

A,@HL

XA,rp’

rp’1,XA

A,#n4

XOR

A,@HL

XA,rp’

rp’1,XA

Accumulator RORC

manipulation

NOT

261

µPD750008 USER'S MANUAL

Instruction code

Mne-

monic

Instruction

Operand

Increment/ INCS

reg

R R R

decrement

rp1

@HL

mem

reg

D D D D D D D D

DECS

R R R

rp’

Comparison SKE

reg,#n4

@HL,#n4

A,@HL

XA,@HL

A,reg

XA,rp’

R R R

Carry flag SET1

manipu-

CLR1

lation

SKT

NOT1

Memory

bit

SET1

CLR1

SKT

mem.bit

D D D D D D D D

manipu-

lation

mem.bit

D D D D D D D D

mem.bit

D D D D D D D D

SKF

mem.bit

D D D D D D D D

SKTCLR

AND1

OR1

CY,

XOR1

262

CHAPTER 11 INSTRUCTION SET

Instruction code

Mne-

monic

Instruction

Branch

Operand

!addr

addr

$addr1

(+16) to (+2)

(–1) to (–15)

PCDE

PCXA

BCDE

BCXA

BRA

!addr1

!caddr

!addr

addr1

BRCB

CALL

caddr

Sub-

addr

routine

stack

CALLA !addr1

CALLF !faddr

RET

addr1

faddr

control

RETS

RETI

PUSH

POP

I/O

A,PORTn

XA,PORTn

PORTn,A

PORTn,XA

N N N

OUT

N N N

Interrupt

control

IExxx

N 1

N N N

N 1

N N N

CPU

HALT

STOP

NOP

control

Special

SEL

RBn

MBn

taddr

N N

N N N

GETI

263

µPD750008 USER'S MANUAL

11.4 FUNCTIONS AND APPLICATIONS OF THE INSTRUCTIONS

This section explains functions and applications of the instructions. For the µPD750004, µPD750006,

µPD750008, and µPD75P0016, usable instructions and their functions in Mk I mode are different from those

in Mk II mode. Read the following explanation.

How to read

Can be used in both Mk I mode and Mk II mode for the µPD750004, µPD750006, µPD750008, and

µPD75P0016

Can be used in only Mk I mode for the µPD750004, µPD750006, µPD750008, and µPD75P0016

Can be used in only Mk II mode for the µPD750004, µPD750006, µPD750008, and µPD75P0016

I/II

Can be used in both Mk I mode and Mk II mode for the µPD750004, µPD750006, µPD750008, and

µPD75P0016. However, Mk I mode is different from Mk II mode in the functions. Read the

explanation of [Mk I mode] for Mk I mode and the explanation of [Mk II mode] for Mk II mode, as

required.

Remark "Function" in this section is applicable to the µPD750006 and µPD750008 whose program

counters consist of 13 bits each. This is also applicable to the µPD750004 whose program

counter consists of 12 bits and the µPD75P0016 whose program counter consists of 14 bits,

however.

11.4.1 Transfer Instructions

MOV A,#n4

Function: A <– n4 n4 = I : 0-FH

3-0

Transfers the 4-bit immediate data n4 to the A register (4-bit accumulator).

The string effect (group A) can be utilized. When MOV A, #n4 and/or MOV XA, #n8 instructions are located

contiguously, the string instructions following an executed instruction are processed as NOP instructions.

Examples 1. The data 0BH is set in the accumulator.

MOV A,#0BH

2. Data to be output to port 3 is selected from 0 to 2.

A0: MOV A,#0

A1: MOV A,#1

A2: MOV A,#2

OUT PORT3,A

264

CHAPTER 11 INSTRUCTION SET

MOV reg1,#n4

Function: reg1 <– n4

n4 = I : 0-FH

3-0

Transfers the 4-bit immediate data n4 to A register reg1 (X, H, L, D, E, B, C).

MOV XA,#n8

Function: XA <– n8

n8 = I : 00H-FFH

7-0

Transfers the 8-bit immediate data n8 to register pair XA. The string effect can be utilized. When two

or more of this instruction are executed in succession or when MOV A,#n4 instruction is located

continguously, the string instructions following an executed instruction are processed as NOP instructions.

MOV HL,#n8

Function: HL <– n8

n8 = I : 00H-FFH

7-0

Transfers the 8-bit immediate data n8 to register pair HL. The string effect can be utilized. When two or

more of this instruction are executed in succession, the string instructions following an executed instruction

are processed as NOP instructions.

MOV rp2,#n8

Function: rp2 <– n8

n8 = I : 00H-FFH

7-0

Transfers the 8-bit immediate data n8 to register pair rp2 (BC, DE).

MOV A,@HL

MOV A,@HL+

MOV A,@HL–

MOV A,@rpa1

Function: A <– (Register pair specified by the operand)

When HL+ is specified for the register pair: Skip if L = 0

When HL– is specified for the register pair: Skip if L = FH

Transfers the data at the data memory location addressed by the specified register pair (HL, HL+, HL–,

DE, DL) to the A register.

When HL+ (automatic increment) is specified for the register pair, automatically increments the contents

of the L register by one after the data transfer, and continues the operation until the contents are set to 0.

265

µPD750008 USER'S MANUAL

Then skips the immediately following instruction.

When HL– (automatic decrement) is specified for the register pair, automatically decrements the contents

of the L register by one after the data transfer, and continues the operation until the contents are set to FH.

Then skips the immediately following instruction.

MOV XA,@HL

Function: A <– (HL), X <– (HL+1)

Transfers the data at the data memory location addressed by the HL register pair to the A register, and

transfers the data at the next data memory address to the X register.

However, if the contents of the L register are odd- numbered, an address with the low-order bit ignored

is specified.

Example The data at addresses 3EH and 3FH are transferred to the XA register pair.

MOV HL, #3EH

MOV XA, @HL

MOV @HL,A

Function: (HL) <– A

Transfers the contents of the A register to the data memory location addressed by the HL register pair.

MOV @HL,XA

Function: (HL) <– A, (HL+1) <– X

Transfers the contents of the A register to the data memory location addressed by the HL register pair, and

transfers the contents of the X register to the next memory address.

However, if the contents of the L register are odd- numbered, an address with the low-order bit ignored

is specified

MOV A,mem

Function: A <– (mem)

mem = D : 00H-FFH

7-0

Transfers the data at the data memory location addressed by the 8-bit immediate data mem to the A register.

266

CHAPTER 11 INSTRUCTION SET

MOV XA,mem

Function: A <– (mem), X <– (mem+1)

mem = D : 00H-FEH

7-0

Transfers the data at the data memory location addressed by the 8-bit immediate data mem to the A register,

and transfers the data at the next address to the X register.

An even address can be specified with mem.

Example The data at addresses 40H and 41H are transferred to the XA register pair.

MOV XA,40H

MOV mem,A

Function: (mem) <– A

mem = D : 00H-FFH

7-0

Transfers the contents of the A register to the data memory location addressed by the 8-bit immediate data

mem.

MOV mem,XA

Function: (mem) <– A, (mem+1) <– X

mem = D : 00H-FEH

7-0

Transfers the contents of the A register to the data memory location addressed by the 8-bit immediate data

mem, and transfers the contents of the X register to the next memory address.

An even address can be specified with mem.

MOV A,reg

Function: A <– reg

Transfers the contents of register reg (X, A, H, L, D, E, B, C) to the A register.

MOV XA,rp’

Function: XA <– rp’

Transfers the contents of register pair rp’ (XA, HL, DE, BC, XA’, HL’, DE’, BC’) to the XA register pair.

Example The contents of the XA’ register pair are transferred to the XA register pair.

MOV XA, XA’

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µPD750008 USER'S MANUAL

MOV reg1,A

Function: reg1 <– A

Transfers the contents of the A register to register reg1 (X, H, L, D, E, B, C).

MOV rp’1,XA

Function: rp’1 <– XA

Transfers the contents of the XA register pair to register pair rp’1 (HL, DE, BC, XA’, HL’, DE’, BC’).

XCH A,@HL

XCH A,@HL+

XCH A,@HL–

XCH A,@rpa1

Function: A <–> (Register pair specified by the operand)

When HL+ is specified for the register pair: Skip if L = 0

When HL– is specified for the register pair: Skip if L = FH

Exchanges the contents of the A register with the data at the data memory location addressed by the

specified register pair (HL, HL+, HL– , DE, DL).

When HL+ (automatic increment) is specified for the register pair, automatically increments the contents

of the L register by one after the data exchange, and continues the operation until the contents are set to 0.

Then skips the immediately following instruction.

When HL– (automatic decrement) is specified for the register pair, automatically decrements the contents

of the L register by one after the data exchange, and continues the operation until the contents are set to FH.

Then skips the immediately following instruction.

Example The data at addresses 20H-2FH are exchanged with the data at addresses 30H-3FH.

SEL

MOV

XCH

MB0

D,#2

HL,#30H

A,@HL

A,@DL

A,@HL+

LOOP

LOOP:

; A <–> (3x)

; A <–> (2x)

; A <–> (3x)

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XCH XA,@HL

Function: A <–> (HL), X <–> (HL+1)

Exchanges the contents of the A register with the data at the data memory location addressed by the HL

However, if the contents of the L register are odd- numbered, an address with the low-order bit ignored

is specified.

XCH A,mem

Function: A <–> (mem)

mem = D : 00H-FEH

7-0

Exchanges the contents of the A register with the data at the data memory location addressed by the 8-

bit immediate data mem.

XCH XA,mem

Function: A <–> (mem), X <–> (mem+1)

mem = D : 00H-FEH

7-0

Exchanges the contents of the A register with the data at the data memory location addressed by the 8-

bit immediate data mem, and exchanges the contents of the X register 1 with the data at the next memory

address.

An even address can be specified with mem.

XCH A,reg1

Function: A <–> reg1

Exchanges the contents of the A register with register reg1 (X, H, L, D, E, B, C).

XCH XA,rp’

Function: XA <–> rp’

Exchanges the contents of the XA register pair with the contents of register pair rp’ (XA, HL, DE, BC, XA’,

HL’, DE’, BC’).

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11.4.2 Table Reference Instructions

MOVT XA,@PCDE

Function: For the µPD750006 and µPD750008

XA <– ROM (PC

+DE)

12-8

Transfers the low-order four bits of the table data in program memory to the A register, and the high-order

four bits to the X register. The table data is addressed by the program counter (PC) with its low-order eight

bits (PC ) exchanged with the contents of the DE register pair.

7-0

The table address is determined by the contents of the program counter (PC) present when this instruction

is executed.

The table area must have necessary data loaded by an assembler pseudo instruction (DB instruction).

The program counter is not affected by the execution of the pseudo instruction.

This instruction is useful for consecutive table data references.

Example For the µPD750006 and µPD750008

Program memory

8 7

4 3

Table

address

Table

data H

Table

data L

PC12-8

D3-0

E3-0

0 3

Remark "Function" in this section is applicable to the µPD750006 and µPD750008 whose program

counters consist of 13 bits each. This is also applicable to the µPD750004 whose program

counter consists of 12 bits and the µPD75P0016 whose program counter consists of 14 bits,

however.

Caution The MOVT XA,@PCDE instruction usually references table data in the page containing that

instruction. However, when the instruction is located at address xxFFH, table data in the

next page is referenced instead of table data in the page containing that instruction.

Program memory

Page 2

02FFH

0300H

Page 3

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CHAPTER 11 INSTRUCTION SET

For example, if MOVT XA,@PCDE is located at a as shown above, the table data in page 3 specified by

the contents of the DE register pair is transferred to the XA register pair instead of that in page 2.

Example The 16-byte data at addresses xxF0H-xxFFH in program memory is transferred to addresses

30H-4FH in data memory.

SUB:

SEL

MB0

MOV

HL,#30H

DE,#0F0H

; HL <– 30H

; DE <– F0H

LOOP:

MOVT XA,@PCDE

; XA <– table data

; (HL) <– XA

MOV

INCS

@HL, XA

; HL <– HL + 2

; E <– E + 1

LOOP

RET

ORG

xxF0H

xxH, xxH, ....... ; Table data

MOVT XA, @PCXA

Function: For the µPD750006 and µPD750008

XA <– ROM (PC +XA)

12-8

Transfers the low-order four bits of the table data in program memory to the A register, and the high-order

four bits to the X register. The table data is addressed by the program counter (PC) with its low-order eight

bits (PC ) exchanged with the contents of the XA register pair.

7-0

The table address is determined by the contents of the program counter present when this instruction is

executed.

The table area must have necessary data loaded by an assembler pseudo instruction (DB instruction).

The program counter is not affected by the execution of this instruction.

Caution As with MOVT XA,@PCDE, when the instruction is located at address xxFFH, table data

in the next page is transferred.

Remark "Function" in this section is applicable to the µPD750006 and µPD750008 whose program

counters consist of 13 bits each. This is also applicable to the µPD750004 whose program

counter consists of 12 bits and the µPD75P0016 whose program counter consists of 14 bits,

however.

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µPD750008 USER'S MANUAL

MOVT XA,@BCXA

Function: For the µPD750006 and µPD750008

XA <– (BCXA)

ROM

Transfers the low-order four bits of the table data (eight bits) in program memory to the A register, and the

high-order four bits to the X register. The table data is addressed by the low-order one bit of the B register

and the contents of the C, X, and A registers.

The table area must have necessary data loaded by an assembler pseudo instruction (DB instruction). The

program counter is not affected by the execution of this instruction.

8 7

4 3

Table data H

Table data L

MOVT XA,@BCDE

Function: For the µPD750006 and µPD750008

XA <– (BCDE)

ROM

Transfers the low-order four bits of the table data (eight bits) in program memory to the A register, and the

high-order four bits to the X register. The table data is addressed by the low-order three bits of the B register

and the contents of the C, D, and E registers.

The table area must have necessary data loaded by an assembler pseudo instruction (DB instruction). The

program counter is not affected by the execution of this instruction.

8 7

4 3

Table data H

Table data L

Remark "Function" in this section is applicable to the µPD750006 and µPD750008 whose program

counters consist of 13 bits each. This is also applicable to the µPD750004 whose program

counter consists of 12 bits and the µPD75P0016 whose program counter consists of 14 bits,

however.

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CHAPTER 11 INSTRUCTION SET

11.4.3 Bit Transfer Instructions

MOV1 CY,fmem.bit

MOV1 CY,pmem.@l

MOV1 CY,@H+mem.bit

Function: CY <– (bit specified in operand)

Transfersthedatamemorybitspecifiedbybitmanipulationaddressing(fmem.bit, pmem.@L, @H+mem.bit)

to the carry flag (CY).

MOV1 fmem.bit,CY

MOV1 pmem.@L,CY

MOV1 @H+mem.bit,CY

Function: (bit specified in operand) <– CY

Transfers the carry flag (CY) bit to the data memory bit specified by bit manipulation addressing (fmem.bit,

pmem.@L,@H+mem.bit)

Example The flag (bit 3 at address 3FH) in data memory is set in bit 2 of port 3.

FLAG EQU 3FH.3

SEL

MB0

MOV H,#FLAG SHR6 ; H <– high-order 4 bits of FLAG

MOV1 CY,@H+FLAG

MOV1 PORT3.2,CY

; CY <– FLAG

; P32 <– CY

11.4.4 Arithmetic/Logical Instructions

ADDS A,#n4

Function: A <– A+n4 ; Skip if carry.

n4 = I : 0-FH

3-0

Adds the 4-bit immediate data n4 to the contents of the A register in binary, then skips the next instruction

if the addition generates a carry. The carry flag is not affected.

This instruction, when combined with the ADDC A,@HL or SUBC A,@HL instruction, functions as a number

system conversion instruction. (See Section 11.1.)

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µPD750008 USER'S MANUAL

ADDS XA,#n8

Function: XA <– XA+n8 ; Skip if carry.

n8 = I : 00H-FFH

7-0

Adds the 8-bit immediate data n8 to the contents of the XA register pair in binary, then skips the next

instruction if the addition generates a carry. The carry flag is not affected.

ADDS A,@HL

Function: A <– A+(HL) ; Skip if carry.

Adds the data at the data memory location addressed by the HL register pair to the contents of the A register

in binary, then skips the next instruction if the addition generates a carry. The carry flag is not affected.

ADDS XA,rp’

Function: XA <– XA+rp’ ; Skip if carry.

Adds the contents of register pair rp’ (XA, HL, DE, BC, XA’, HL’, DE’, BC’) to the contents of the XA register

pair in binary, then skips the next instruction if the addition generates a carry. The carry flag is not affected.

ADDS rp’1,XA

Function: rp’ <– rp’1+XA ; Skip if carry.

Adds the contents of the XA register pair to the contents of register pair rp’1 (HL, DE, BC, XA’, HL’, DE’,

BC’) in binary, then skips the next instruction if the addition generates a carry. The carry flag is not affected.

Example The register pair is left-shifted.

MOV XA, rp’1

ADDS rp’1, XA

NOP

ADDC A,@HL

Function: A,CY <– A+(HL)+CY

Adds the data at the data memory location addressed by the HL register pair together with the carry flag

to the contents of the A register in binary. If the addition generates a carry, the carry flag is set. If no carry

is generated, the carry flag is reset.

If the execution of this instruction generates a carry when this instruction is immediately followed by the

ADDS A,#n4 instruction, the ADDS A,#n4 instruction is skipped. If no carry is generated, the ADDS A,#n4

instruction is executed, and the skip function of the ADDS A,#n4 instruction is disabled. Accordingly, a

combination of these instructions can be used for number system conversion. (See Section 11.1.)

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CHAPTER 11 INSTRUCTION SET

ADDC XA,rp’

Function: XA, CY <– XA+rp’+CY

Adds the contents of register pair rp’ (XA, HL, DE, BC, XA’, HL’, DE’, BC’) together with the carry flag to

the contents of the XA register pair in binary. If the addition generates a carry, the carry flag is set. If no carry

is generated, the carry flag is reset.

ADDC rp’1,XA

Function: rp’1, CY <– rp’1+XA+CY

Adds the contents of the XA register pair together with the carry flag to the contents of register pair rp’1

(HL, DE, BC, XA’, HL’, DE’, BC’) in binary. If the addition generates a carry, the carry flag is set. If no carry

is generated, the carry flag is reset.

SUBS A,@HL

Function: A <– A–(HL) ; Skip if borrow

Subtracts the data at the data memory location addressed by the HL register pair from the contents of the

A register, then sets the result in the A register. If the subtraction generates a borrow, the immediately following

instruction is skipped.

The carry flag is not affected.

SUBS XA,rp’

Function: XA <– XA–rp’ ; Skip if borrow

Subtracts the contents of register pair rp’ (XA, HL, DE, BC, XA’, HL’, DE’, BC’) from the contents of the

XA register pair, then sets the result in the XA register pair. If the subtraction generates a borrow, the

immediately following instruction is skipped.

The carry flag is not affected.

Example Data memory is compared with register pair rp’.

MOV XA, mem

SUBS XA, rp’

; (mem) • rp’

; (mem) < rp’

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µPD750008 USER'S MANUAL

SUBS rp’1,XA

Function: rp’1 <– rp’1+XA ; Skip if borrow

Subtracts the contents of the XA register pair from the contents of register pair rp’1 (HL, DE, BC, XA’, HL’,

DE’, BC’), then sets the result in register pair rp’1. If the subtraction generates a borrow, the immediately

following instruction is skipped.

The carry flag is not affected.

SUBC A,@HL

Function: A, CY <– A–(HL)–CY

Subtracts the data at the data memory location addressed by the HL register pair together with the carry

flag from the contents of the A register, then sets the result in the A register. If the subtraction generates a

borrow, the carry flag is set. If no borrow is generated, the carry flag is reset.

If the execution of this instruction generates no borrow when this instruction is followed by the ADDS A,

#n4 instruction, the ADDS A, #n4 instruction is skipped. If a borrow is generated, the ADDS A, #n4 instruction

is executed, and the skip function of the ADDS A, #n4 instruction is disabled. Accordingly, a combination of

these instructions can be used for number system conversion. (See Section 11.1.)

SUBC XA,rp’

Function: XA, CY <– XA–rp’–CY

Subtracts the contents of register pair rp’ (XA, HL, DE, BC, XA’, HL’, DE’, BC’) together with the carry flag

from the contents of the XA register pair, then sets the result in the XA register pair. If the subtraction generates

a borrow, the carry flag is set. If no borrow is generated, the carry flag is reset.

SUBC rp’1,XA

Function: rp’1, CY <– rp’1–XA–CY

Subtracts the contents of the XA register pair together with the carry flag from the contents of register pair

rp’1 (HL, DE, BC, XA’, HL’, DE’, BC’), then sets the result in register pair rp’1. If the subtraction generates

a borrow, the carry flag is set. If no borrow is generated, the carry flag is reset.

AND A,#n4

Function: A <– A n4

n4 = I : 0-FH

3-0

ANDs the contents of the A register with the 4-bit immediate data n4, then sets the result in the A register.

Example The high-order two bits of an accumulator are set to 0.

AND A,#0011B

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CHAPTER 11 INSTRUCTION SET

AND A,@HL

Function: A <– A (HL)

ANDs the contents of the A register with the data at the data memory location addressed by the HL register

pair, then sets the result in the A register.

AND XA,rp’

Function: XA <– XA rp’

ANDs the contents of the XA register pair with the contents of register pair rp’ (XA, HL, DE, BC, XA’, HL’,

DE’, BC’), then sets the result in the XA register pair.

AND rp’1,XA

Function: rp’1 <– rp’1 XA

ANDs the contents of register pair rp’1 (HL, DE, BC, XA’, HL’, DE’, BC’) with the contents of the XA register

pair, then sets the result in the specified register pair.

OR A,#n4

Function: A <– A 4

n4 = I : 0-FH

3-0

ORs the contents of the A register with the 4-bit immediate data n4, then sets the result in the A register.

Example The low-order three bits of an accumulator are set to 1.

OR A,#0111B

OR A,@HL

Function: A <– A (HL)

ORs the contents of the A register with the data at the data memory location addressed by the HL register

pair, then sets the result in the A register.

OR XA,rp’

Function: XA <– XA rp’

ORs the contents of the XA register pair with the contents of register pair rp’ (XA, HL, DE, BC, XA’, HL’,

DE’, BC’), then sets the result in the XA register pair.

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µPD750008 USER'S MANUAL

OR rp’1,XA

Function: rp’1 <– rp’ XA

ORs the contents of register pair rp’1 (HL, DE, BC, XA’, HL’, DE’, BC’) with the contents of the XA register

pair, then sets the result in register pair rp’1.

XOR A,#n4

Function: A <– A n4

n4 = I : 0-FH

3-0

Exclusive-ORs the contents of the A register with the 4-bit immediate data n4, then sets the result in the

A register.

Example The high-order four bits of an accumulator is inverted.

XOR A,#1000B

XOR A,@HL

Function: A <– A (HL)

Exclusive-ORs the contents of the A register with the data at the data memory location addressed by the

HL register pair, then sets the result in the A register.

XOR XA,rp’

Function: XA <– XA rp’

Exclusive-ORs the contents of the XA register pair with the contents of register pair rp’ (XA, HL, DE, BC,

XA’, HL’, DE’, BC’), then sets the result in the XA register pair.

XOR rp’1,XA

Function: rp’1 <– rp’1 XA

Exclusive-ORs the contents of register pair rp’1 (HL, DE, BC, XA’, HL’, DE’, BC’) with the contents of the

XA register pair, then sets the result in register pair rp’1.

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CHAPTER 11 INSTRUCTION SET

11.4.5 Accumulator Manipulation Instructions

RORC A

Function: CY <- A , A

<- A , A <- CY (n = 1–3)

n-1

Rotates the contents of the A register (4-bit accumulator) through the carry flag one bit position to the right.

•

Before

execution

RORC A

After

execution

NOT A

Function: A <– A

Obtains the one’s complement of the A register (4-bit accumulator), that is, inverts each bit of the A register.

11.4.6 Increment/Decrement Instructions

INCS reg

Function: reg <– reg+1 ; Skip if reg = 0

Increments the contents of register reg (X, A, H, L, D, E, B, C). If the result of increment produces reg =

0, the immediately following instruction is skipped.

INCS rp1

Function: rp1 <– rp1+1 ; Skip if rp1 = 00H

Increments the contents of register pair rp1 (HL, DE, BC). If the result of increment produces rp1 = 00H,

the immediately following instruction is skipped.

INCS @HL

Function: (HL) <– (HL)+1 ; Skip if (HL) = 0

Increments the data at the data memory location addressed by the HL register pair. If the result of increment

produces data that is 0, the immediately following instruction is skipped.

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µPD750008 USER'S MANUAL

INCS mem

Function: (mem) <– (mem)+1 ; Skip if (mem) = 0, mem = D : 00H-FFH

7-0

Increments the data at the data memory location addressed by the 8-bit immediate data mem. If the result

of increment produces data that is 0, the immediately following instruction is skipped.

DECS reg

Function: reg <– reg–1 ; Skip if reg = FH

Decrements the contents of register reg (X, A, H, L, D, E, B, C). If the result of decrement produces reg

= FH, the immediately following instruction is skipped.

DECS rp’

Function: rp’ <– rp’–1 ; Skip if rp’ = FFH

Decrements the contents of register pair rp’ (XA, HL, DE, BC, XA’, HL’, DE’, BC’). If the result of decrement

produces rp’ = FFH, the immediately following instruction is skipped.

11.4.7 Compare Instructions

SKE reg,#n4

Function: Skip if reg = n4

n4 = I : 0-FH

3-0

Skips the immediately following instruction if the contents of register reg (X, A, H, L, D, E, B, C) match the

4-bit immediate data n4.

SKE @HL,#n4

Function: Skip if (HL) = n4

n4 = I : 0-FH

3-0

Skips the immediately following instruction if the data at the data memory location addressed by the HL

SKE A,@HL

Function: Skip if A = (HL)

Skips the immediately following instruction if the contents of the A register match the data at the data memory

location addressed by the HL register pair.

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CHAPTER 11 INSTRUCTION SET

SKE XA,@HL

Function: Skip if A = (HL) and X = (HL+1)

Skips the immediately following instruction if the contents of the A register match the data at the data memory

location addressed by the HL register pair, and the contents of the X register match the data at the next address

in data memory.

However, if the contents of the L register are odd- numbered, an address with the lowest-order bit ignored

is specified.

SKE A,reg

Function: Skip if A = reg

Skips the immediately following instruction if the contents of the A register match the contents of register

reg (X, A, H, L, D, E, B, C).

SKE XA,rp’

Function: Skip if XA = rp’

Skips the immediately following instruction if the contents of the XA register pair match the contents of

11.4.8 Carry Flag Manipulation Instructions

SET1 CY

Function: CY <– 1

Sets the carry flag.

CLR1 CY

Function: CY <– 0

Clears the carry flag.

SKT CY

Function: Skip if CY = 1

Skips the immediately following instruction if the carry flag is set to 1.

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µPD750008 USER'S MANUAL

NOT1 CY

Function: CY <– CY

Inverts the carry flag. If it is 0, it is set to 1, or vice versa.

11.4.9 Memory Bit Manipulation Instructions

SET1 mem.bit

Function: (mem.bit) <– 1

mem = D : 00H-FFH, bit = B : 0–3

7-0 1-0

Sets the bit specified by the 2-bit immediate data bit at the address specified by the 8-bit immediate data

mem.

SET1 fmem.bit

SET1 pmem.@L

SET1 @H+mem.bit

Function: (Bit specified in operand) <– 1

Sets the bit in data memory specified by bit manipulation addressing (fmem.bit, pmem.@L, @H+mem.bit).

CLR1 mem.bit

Function: (mem.bit) <– 0

mem = D : 00H-FFH, bit = B : 0–3

7-0 1-0

Clears the bit specified by the 2-bit immediate data bit at the address specified by the 8-bit immediate data

mem.

CLR1 fmem.bit

CLR1 pmem.@L

CLR1 @H+mem.bit

Function: (Bit specified in operand) <– 0

Clears the bit in data memory specified by bit manipulation addressing (fmem.bit, pmem.@L, @H+mem.bit).

SKT mem.bit

Function: Skip if (mem.bit) = 1

mem = D : 00H-FFH, bit = B : 0–3

7-0

1-0

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CHAPTER 11 INSTRUCTION SET

Skips the immediately following instruction if the bit specified by the 2-bit immediate data bit at the address

specified by the 8-bit immediate data mem is 1.

SKT fmem.bit

SKT pmem.@L

SKT @H+mem.bit

Function: Skip if (bit specified in operand) = 1

Skips the immediately following instruction if the bit in data memory specified by bit manipulation addressing

(fmem.bit, pmem.@L, @H+mem.bit) is set to 1.

SKF mem.bit

Function: Skip if (mem.bit) = 0

mem = D : 00H-FFH, bit = B : 0–3

7-0

1-0

Skips the immediately following instruction if the bit specified by the 2-bit immediate data bit at the address

specified by the 8-bit immediate data mem is 0.

SKF fmem.bit

SKF pmem.@L

SKF @H+mem.bit

Function: Skip if (bit specified in operand) = 0

Skips the immediately following instruction if the bit in data memory specified by bit manipulation addressing

(fmem.bit, pmem.@L, @H+mem.bit) is 0.

SKTCLR fmem.bit

SKTCLR pmem.@L

SKTCLR @H+mem.bit

Function: Skip if (bit specified in operand) = 1 then clear

Skips the immediately following instruction if the bit in data memory specified by bit manipulation addressing

(fmem.bit, pmem.@L, @H+mem.bit) is 1, then clears the bit to 0.

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µPD750008 USER'S MANUAL

AND1 CY, fmem.bit

AND1 CY, pmem.@L

AND1 CY, @H+mem.bit

Function: CY <– CY (bit specified in operand)

ANDs the content of the carry flag with the bit in data memory specified by bit manipulation addressing

(fmem.bit, pmem.@L, @H+mem.bit), then sets the result in the carry flag.

OR1 CY, fmem.bit

OR1 CY, pmem.@L

OR1 CY, @H+mem.bit

Function: CY <– CY¦ (bit specified in operand)

ORs the content of the carry flag with the bit in data memory specified by bit manipulation addressing

(fmem.bit, pmem.@L, @H+mem.bit), then sets the result in the carry flag.

XOR1 CY, fmem.bit

XOR1 CY, pmem.@L

XOR1 CY, @H+mem.bit

Function: CY <– CY¦ (bit specified in operand)

Exclusive-ORs the content of the carry flag with the bit in data memory specified by bit manipulation

addressing (fmem.bit, pmem.@L, @H+mem.bit), then sets the result in the carry flag.

11.4.10 Branch Instructions

BR addr

Function: For the µPD750008 PC

<– addr

12-0

addr = 0000H-1FFFH

Branches to the address specified by the immediate data addr.

This instruction is an assembler pseudo instruction, and the assembler automatically replaces this

instruction with the BR !addr instruction, BRCB !caddr instruction, or BR $addr instruction as required at

assembly time.

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CHAPTER 11 INSTRUCTION SET

BR addr1

Function: For the µPD750008 PC

<– addr1

12-0

addr1 = 0000H-1FFFH

Branches to the address specified by the immediate data addr1.

This instruction is an assembler pseudo instruction, and the assembler automatically replaces this

instruction with the BRA !addr1 instruction, BR !addr instruction, BRCB !caddr instruction, or BR $addr1

instruction as required at assembly time.

Remark "Function" in this section is applicable to the µPD750008 whose program counter consists of

13 bits (addr = 0000H to 1FFFH).

However, this is also applicable to the µPD750004 whose program counter consists of

12 bits (addr = 0000H to 0FFFH), the µPD750006 whose program counter consists of 13

bits (addr = 0000H to 17FFH), and the µPD75P0016 whose program counter consists of

14 bits (addr = 0000H to 3FFFH).

BRA !addr1

Function: For the µPD750008 PC

<– addr1

<– addr

12-0

BR !addr

Function: For the µPD750008 PC

addr = 0000H-1FFFH

Transfers the immediate data addr to the program counter (PC), then branches to the location addressed

by the program counter.

BR $addr

Function: For the µPD750008 PC

<– addr

12-0

addr = (PC–15) to (PC–1), (PC+2) to (PC+16)

Relative branch instruction with branch ranges of (–15 to –1) and (+2 to +16) from the current address.

The instruction is not affected by page or block boundaries.

BR $addr1

Function: For the µPD750008 PC

<– addr1

12-0

addr = (PC–15) to (PC–1), (PC+2) to (PC+16)

Relative branch instruction with branch ranges of (–15 to –1) and (+2 to +16) from the current address.

The instruction is not affected by page or block boundaries.

285

µPD750008 USER'S MANUAL

Remark "Function" in this section is applicable to the µPD750008 whose program counter consists of

13 bits (addr = 0000H to 1FFFH).

However, this is also applicable to the µPD750004 whose program counter consists of 12 bits

(addr = 0000H to 0FFFH), the µPD750006 whose program counter consists of 13 bits (addr =

0000H to 17FFH), and the µPD75P0016 whose program counter consists of 14 bits (addr = 0000H

to 3FFFH).

BRCB !caddr

Function: For the µPD750008 PC

<– PC + caddr

12 11-0

12-0

caddr = n000H-nFFFH

n = PC = 0, 1

Branches to the address specified by the program counter whose low-order 12 bits

(PC ) have been replaced with the 12-bit immediate data caddr (A ).

11-0

Since the program counter of the µPD750004 consists of 11 bits, this instruction enables a branch to any

location in the program memory space.

In the µPD750006 and µPD750008, PC cannot be changed, so no branch occurs beyond the block.

Similarly, in the µPD75P0016, PC and PC cannot be changed, so no branch occurs beyond the block.

Caution The BRCB !caddr instruction usually causes a branch within the block containing the

instruction. However, if the first byte is located at address 0FFEH or 0FFFH, a branch to

block 1 instead of block 0 occurs.

Program memory

Block 0

Block 1

0FFEH

0FFFH

1000H

If the BRCB !caddr instruction is located at a or b in the figure above, a branch to block 1 instead of block

0 occurs.

Remark "Function" in this section is applicable to the µPD750008 whose program counter consists of

13 bits (addr = 0000H to 1FFFH).

However, this is also applicable to the µPD750004 whose program counter consists of 12

bits (addr = 0000H to 0FFFH), the µPD750006 whose program counter consists of 13 bits

(addr = 0000H to 17FFH), and the µPD75P0016 whose program counter consists of 14 bits

(addr = 0000H to 3FFFH).

286

CHAPTER 11 INSTRUCTION SET

BR PCDE

Function: For the µPD750008 PC

<– PC

+ DE

12-8

12-0

7- 4

<– D, PC <– E

3-0

Branches to the address specified by the program counter whose low-order 8 bits (PC ) have been

7-0

replaced with the contents of the DE register pair. The high-order bits of the program counter are not affected.

Caution TheBRPCDEinstructionusuallycausesabranchwithinthepagecontainingtheinstruction.

However, if the first byte of the instruction code is located at address xxFEH or xxFFH,

a branch to the next page instead of that page occurs.

Program memory

Page 2

Page 3

02FEH

02FFH

0300H

If the BR PCDE instruction is located at a or b in the figure above, a branch to page 3 instead of page 2

occurs, jumping to the low-order 8 bits of the address specified by the contents of the DE register pair.

BR PCXA

Function: For the µPD750008 PC

<– PC

+ XA

12-8

12-0

7- 4

<– X, PC <– A

3-0

Branches to the address specified by the program counter whose low-order 8 bits (PC ) have been

7-0

replaced with the contents of the XA register pair. The high-order bits of the program counter are not affected.

Caution As with the BR PCDE instruction, if the first byte is located at address xxFEH or xxFFH,

a branch to the next page instead of the page containing the instruction occurs.

Remark "Function" in this section is applicable to the µPD750008 whose program counter consists of

13 bits (addr = 0000H to 1FFFH).

However, this is also applicable to the µPD750004 whose program counter consists of 12

bits (addr = 0000H to 0FFFH), the µPD750006 whose program counter consists of 13 bits

(addr = 0000H to 17FFH), and the µPD75P0016 whose program counter consists of 14 bits

(addr = 0000H to 3FFFH).

287

µPD750008 USER'S MANUAL

BR BCDE

Function: For the µPD750008 PC

<– BCDE

12-0

Branches to the address specified by the program counter whose bits have been replaced with the contents

of the B , C, D, and E registers.

8 7

4 3

BR BCXA

Function: For the µPD750008 PC

<– BCXA

12-0

Branches to the address specified by the program counter whose bits have been replaced with the contents

of the B , C, X, and A registers.

8 7

4 3

TBR addr

Function: Assembler pseudo instruction of the GETI instruction for table definition. This instruction is

used to replace a 3-byte BR instruction with a 1-byte GETI instruction. The 12-bit address data

must be coded in addr. For detailed information, refer to RA75X Assembler Package User’s

Manual: Language (EEU-1363).

Remark "Function" in this section is applicable to the µPD750008 whose program counter consists of

13 bits (addr = 0000H to 1FFFH).

However, this is also applicable to the µPD750004 whose program counter consists of 12

bits (addr = 0000H to 0FFFH), the µPD750006 whose program counter consists of 13 bits

(addr = 0000H to 17FFH), and the µPD75P0016 whose program counter consists of 14 bits

(addr = 0000H to 3FFFH).

288

CHAPTER 11 INSTRUCTION SET

11.4.11 Subroutine Stack Control Instructions

CALLA !addr1

Function: For the µPD750008

(SP–2) <– x, x, MBE, RBE, (SP–3) <– PC

7-4

(SP–4) <– PC

(SP–6) <– PC

(SP–5) <– 0, 0, 0, PC

3-0,

11-8

<– addr1, SP <– SP–6

12-0

CALL !addr

I/II

Function: For the µPD750008

[Mk I mode]

(SP–1) <– PC , (SP–2) <– PC

7-4

3-0

(SP–3) <– MBE, RBE, 0, PC

(SP–4) <– PC

, PC

11-8

<– addr, SP <– SP–4

12-0

addr = 0000H – 1FFFH

[Mk II mode]

(SP–2) <– x, x, MBE, RBE

(SP–3) <– PC , (SP–4) <– PC

7-4

3-0

(SP–5) <– 0, 0, 0, PC , (SP–6) <– PC

11-8

<– addr, SP <– SP–6

12-0

addr = 0000H – 1FFFH

Saves the contents of the program counter (return address), memory bank enable flag (MBE), and register

bank enable flag (RBE) to the data memory location (stack) addressed by the stack pointer (SP), then branches

to the location addressed by the 14-bit immediate data addr after decrementing SP.

Remark "Function" in this section is applicable to the µPD750008 whose program counter consists of

13 bits (addr = 0000H to 1FFFH).

However, this is also applicable to the µPD750004 whose program counter consists of 12

bits (addr = 0000H to 0FFFH), the µPD750006 whose program counter consists of 13 bits

(addr = 0000H to 17FFH), and the µPD75P0016 whose program counter consists of 14 bits

(addr = 0000H to 3FFFH).

289

µPD750008 USER'S MANUAL

CALLF !faddr

I/II

Function: For the µPD750008

[Mk I mode]

(SP–1) <– PC , (SP–2) <– PC

7-4

3-0

(SP–3) <– MBE, RBE, 0, PC

(SP–4) <– PC

, SP <– SP – 4

11-8

<– 00 + faddr

12-0

faddr = 0000H – 07FFH

[Mk II mode]

(SP–2) <– x, x, MBE, RBE

(SP–3) <– PC , (SP–4) <– PC

7-4

3-0

(SP–5) <– 0, 0, 0, PC , (SP–6) <– PC

11-8

SP <– SP–6

<– 00 + faddr

12-0

faddr = 0000H – 07FFH

Saves the contents of the program counter (PC; Return address), memory bank enable flag (MBE), and

branches to the location addressed by the 11-bit immediate data faddr after decrementing SP. Only the

address range 0000H-07FFH (0-2047) can be called.

TCALL !addr

Function: Assembler pseudo instruction of the GETI instruction for table definition. This instruction is

used to replace a 3-byte CALL !addr instruction with a 1-byte GETI instruction. The 12-bit

address data must be coded in addr. For detailed information, refer to RA75X Assembler

Package User’s Manual: Language (EEU-1363).

Remark "Function" in this section is applicable to the µPD750008 whose program counter consists of

13 bits (addr = 0000H to 1FFFH).

However, this is also applicable to the µPD750004 whose program counter consists of 12

bits (addr = 0000H to 0FFFH), the µPD750006 whose program counter consists of 13 bits

(addr = 0000H to 17FFH), and the µPD75P0016 whose program counter consists of 14 bits

(addr = 0000H to 3FFFH).

290

CHAPTER 11 INSTRUCTION SET

RET

Function: For the µPD750008

I/II

[Mk I mode]

<– (SP)

11-8

MBE, RBE, 0, PC <– (SP+1)

<– (SP+2)

3-0

<– (SP+3), SP <– SP+4

7-4

[Mk II mode]

<– (SP), x, x, x, PC <– (SP+1)

11-8

<– (SP+2), PC

<– (SP+3)

7-4

3-0

x, x, MBE, RBE <– (SP+4)

SP <– SP+6

Restores the program counter (PC), memory bank enable flag (MBE), and register bank enable flag (RBE)

with the data at the data memory location (stack) addressed by the stack pointer (SP), then increments the

contents of SP.

Caution The program status word (PSW) is not restored except MBE and RBE.

Remark "Function" in this section is applicable to the µPD750008 whose program counter consists of

13 bits (addr = 0000H to 1FFFH).

However, this is also applicable to the µPD750004 whose program counter consists of 12

bits (addr = 0000H to 0FFFH), the µPD750006 whose program counter consists of 13 bits

(addr = 0000H to 17FFH), and the µPD75P0016 whose program counter consists of 14 bits

(addr = 0000H to 3FFFH).

RETS

Function: For the µPD750008

I/II

[Mk I mode]

<– (SP)

11-8

MBE, 0, 0, PC <– (SP+1)

<– (SP+2), PC

<– (SP+3), SP <– SP+4

7-4

3-0

Then skip unconditionally

[Mk II mode]

<– (SP), 0, 0, 0, PC <– (SP+1)

11-8

<– (SP+2), PC

<– (SP+3)

7-4

3-0

x, x, MBE, RBE <– (SP+4)

SP <– SP+6

Then skip unconditionally

Restores the program counter (PC), memory bank enable flag (MBE), and register bank enable flag (RBE)

withthedataatthedatamemorylocation(stack)addressedbythestackpointer(SP), thenskipsunconditionally

after incrementing the contents of SP.

Caution The program status word (PSW) is not restored except MBE and RBE.

291

µPD750008 USER'S MANUAL

Remark "Function" in this section is applicable to the µPD750008 whose program counter consists of

13 bits (addr = 0000H to 1FFFH).

However, this is also applicable to the µPD750004 whose program counter consists of 12

bits (addr = 0000H to 0FFFH),the µPD750006 whose program counter consists of 13 bits

(addr = 0000H to 17FFH),and the µPD75P0016 whose program counter consists of 14 bits

(addr = 0000H to 3FFFH).

RETI

Function: For the µPD750008

I/II

[Mk I mode]

<– (SP), MBE, RBE, 0, PC <– (SP+1)

11-8 12

<– (SP+2)

<– (SP+3)

3-0

7-4

PSW <– (SP+4), PSW <– (SP+5)

SP <– SP+6

[Mk II mode]

<– (SP), 0, 0, 0, PC <– (SP+1)

11-8

<– (SP+2)

<– (SP+3),

3-0

7-4

PSW <– (SP+4), PSW <– (SP+5)

SP <– SP+6

Restores the program counter (PC) and program status word with the data at the data memory location

(stack) addressed by the stack pointer (SP), then increments the contents of SP.

This instruction is used when control is returned from an interrupt service routine.

Remark "Function" in this section is applicable to the µPD750008 whose program counter consists of

13 bits (addr = 0000H to 1FFFH).

However, this is also applicable to the µPD750004 whose program counter consists of 12

bits (addr = 0000H to 0FFFH), the µPD750006 whose program counter consists of 13 bits

(addr = 0000H to 17FFH), and the µPD75P0016 whose program counter consists of 14 bits

(addr = 0000H to 3FFFH).

PUSH rp

Function: (SP–1) <– rp , (SP–2) <– rp , SP <– SP–2

Saves the contents of register pair rp (XA, HL, DE, BC) to the data memory location (stack) addressed by

the stack pointer (SP), then decrements SP.

The high-order part of a register pair (rp : X, H, D, B) is saved to the stack location addressed by (SP–

1), and the low-order part (rp : A, L, E, C) is saved to the stack location addressed by (SP–2).

292

CHAPTER 11 INSTRUCTION SET

PUSH BS

Function: (SP–1) <– MBS, (SP–2) <– RBS, SP <– SP–2

Saves the contents of the memory bank select register (MBS) and the register bank select register (RBS)

to the data memory location (stack) addressed by the stack pointer (SP), then decrements SP.

POP rp

Function: rp <– (SP), rp <– (SP+1), SP <– SP+2

Restores register pair rp (XA, HL, DE, BC) with the data at the data memory location (stack) addressed

by the stack pointer (SP), then increments SP.

The low-order part of a register pair (rp : A, L, E, C) is restored from the contents of (SP), and the high-

order part (rp : X, H, D, B) is restored with the contents of (SP+ ).

POP BS

Function: RBS <– (SP), MBS <– (SP+1), SP <– SP+2

Restores the register bank select register (RBS) and the memory bank select register (MBS) with the data

at the data memory location (stack) addressed by the stack pointer (SP), then increments SP.

11.4.12 Interrupt Control Instructions

Function: IME (IPS.3) <– 1

Sets the interrupt master enable flag (bit 3 of the interrupt priority specification register) to 1 to enable

interrupts. Whether to accept an interrupt is controlled with the corresponding interrupt enable flag.

EI IExxx

Function: IExxx <– 1

xxx = N , N

2-0

Sets an interrupt enable flag (IExxx) to 1 to enable an interrupt. (xxx = BT, CSI, T0, T1, W, 0, 1, 2, 4)

Function: IME (IPS.3) <– 0

Resets the interrupt master enable flag (bit 3 of the interrupt priority specification register) to 0 to disable

all interrupts regardless of the states of the interrupt enable flags.

293

µPD750008 USER'S MANUAL

DI IExxx

Function: IExxx <– 0 xxx = N , N

2-0

Resets an interrupt enable flag (IExxx) to 0 to disable an interrupt. (xxx = BT, CSI, T0, T1, W, 0, 1, 2, 4)

11.4.13 I/O Instructions

IN A,PORTn

Function: A <– PORTn

n = N : 0–8

3-0

Transfers the contents of the port specified by PORTn (n = 0-8) to the A register.

Caution Before this instruction can be executed, MBE = 0 or (MBE = 1, MBS = 15) must be set. A

number from 0 to 8 can be specified as n. Depending on I/O mode specification, output

latch data (in the output mode) or pin data (in the input mode) are transferred.

IN XA,PORTn

Function: A <– PORTn, X <– PORT

n = N : 4, 6

3-0

n+1

Transfers the contents of the port specified by PORTn (n = 4 or 6) to the A register, then transfers the

contents of the next port to the X register.

Caution Only the number 4 or 6 can be specified as n. Before this instruction can be executed,

MBE = 0 or (MBE = 1, MBS = 15) must be set. Depending on I/O mode specification, output

latch data (in the output mode) or pin data (in the input mode) are transferred.

OUT PORTn, A

Function: PORTn <– A

n = N : 2–8

3-0

Transfers the contents of the A register to the output latch of the port specified by PORTn (n = 2–8).

Caution Before this instruction can be executed, MBE = 0 or (MBE = 1, MBS = 15) must be set.

A number from 2 to 8 can be specified as n.

OUT PORTn, XA

Function: PORTn <– A, PORT

<– X

n = N : 4, 6

3-0

n+1

Transfers the contents of the A register to the output latch of the port specified by PORTn (n = 4, 6), then

transfers the contents of the X register to the output latch of the next port.

294

CHAPTER 11 INSTRUCTION SET

Caution Before this instruction can be executed, MBE = 0 or (MBE = 1, MBS = 15) must be set.

Only 4 or 6 can be specified as n.

11.4.14 CPU Control Instructions

HALT

Function: PCC.2 <– 1

Sets the HALT mode. (This instruction is used to set bit 2 of the processor clock control register.)

Caution The instruction immediately following a HALT instruction must be a NOP instruction.

STOP

Function: PCC.3 <– 1

Sets the STOP mode. (This instruction is used to set bit 3 of the processor clock control register.)

Caution The instruction immediately following a STOP instruction must be a NOP instruction.

NOP

Function: Uses one machine cycle without performing an action.

11.4.15 Special Instructions

SEL RBn

Function: RBS <– n

n = N : 0 to 3

1-0

Sets the 2-bit immediate data n in the register bank select register (RBS).

SEL MBn

Function: MBS <– n

n = N : 0, 1, 15

3-0

Transfers the 4-bit immediate data n to the memory bank select register (MBS).

Only 0, 1, or 15 can be specified as n.

295

µPD750008 USER'S MANUAL

GETI taddr

I/II

Function: taddr = T , 0 : 20H-7FH

5-0

For the µPD750008

[Mk I mode]

• When a table defined by the TBR instruction is referenced

PC <– (taddr) + (taddr+1)

12-0

4-0

• When a table defined by the TCALL instruction is referenced

(SP–1) <– PC , (SP–2) <– PC

7-4

3-0

(SP–3) <– MBE, RBE, 0, PC

(SP–4) <– PC

11-8

<– (taddr)

+ (taddr+1)

4-0

12-0

SP <– SP–4

• When a table defined by an instruction other than the TBR or TCALL instruction is

referenced

An instruction using (taddr) (taddr+1) as its operation code is executed.

[Mk II mode]

• When a table defined by the TBR instruction is referenced

<– (taddr)

+ (taddr+1)

4-0

12-0

• When a table defined by the TCALL instruction is referenced

(SP–2) <– x, x, MBE, RBE

(SP–3) <– PC , (SP–4) <– PC

7-4

3-0

(SP–5) <– 0, 0, 0, PC , (SP–6) <– PC

11-8

<– (taddr)

+ (taddr+1)

4-0

12-0

SP <– SP–6

• When a table defined by an instruction other than the TBR or TCALL instruction is

referenced

An instruction using (taddr) (taddr+1) as its operation code is executed.

Remark "Function" in this section is applicable to the µPD750008 whose program counter consists of

13 bits (addr = 0000H to 1FFFH).

However, this is also applicable to the µPD750004 whose program counter consists of 12

bits (addr = 0000H to 0FFFH), the µPD750006 whose program counter consists of 13 bits

(addr = 0000H to 17FFH), and the µPD75P0016 whose program counter consists of 14 bits

(addr = 0000H to 3FFFH).

The 2-byte data at the program memory addresses specified by (taddr) and (taddr+1) is referenced and

executed as an instruction.

Addresses 0020H to 007FH are used as a reference table area. Data must be written to this area

beforehand. When a 1-byte instruction or 2-byte instruction is written, its mnemonic can be used directly.

For a 3-byte call instruction or 3-byte branch instruction, an assembler pseudo instruction (TCALL, TBR)

is used.

Only an even address can be specified as taddr.

296

CHAPTER 11 INSTRUCTION SET

Caution All 2-byte instructions (except the BRCB instruction and CALLF instruction) set in the

reference table must be 2-machine-cycle instructions. Pairs of 1-byte instructions can be

set as indicated in the table below.

First byte instruction

Second byte instruction

INCS

DECS

INCS

DECS

INCS

MOV A,@HL

MOV @HL,A

XCH A,@HL

INCS

DECS

INCS

DECS

INCS

MOV A,@DE

XCH A,@DE

MOV A,@DL

XCH A,@DL

INCS

DECS

INCS

DECS

The PC is not incremented during execution of a GETI instruction, so that after a reference instruction is

executed, execution is resumed starting at the address immediately after the GETI instruction.

If the instruction immediately preceding a GETI instruction has the skip function, the GETI instruction is

skipped as with other 1-byte instructions. If an instruction referenced with a GETI instruction has the skip

function, the instruction immediately following the GETI instruction is skipped.

If a GETI instruction references an instruction having a string effect, the following processing is performed:

• If the instruction immediately preceding the GETI instruction also has the string effect in the same group,

the execution of the GETI instruction cancels the string effect, and the referenced instruction is not

skipped.

• If the instruction immediately following the GETI instruction also has the string effect of the same group,

the string effect of the referenced instruction remains valid, and the next instruction is skipped.

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µPD750008 USER'S MANUAL

Example

MOV HL, #00H

MOV XA, #FFH

CALL SUB1

are replaced with GETI instructions.

BR SUB2

ORG

20H

HL00:

MOV

TCALL

TBR

HL, #00H

XA, #FFH

SUB1

XAFF:

CSUB1:

BSUB2:

SUB2

GET HL00

; MOV HL,#00H

GETI BSUB2

; BR SUB2

GETI CSUB1

; CALL SUB1

GETI XAFF

; MOV XA,#FFH

298

APPENDIX A FUNCTIONS OF THE µPD75008, µPD750008, AND µPD75P0016

(1/2)

Item

Program memory

µPD75008

µPD750008

µPD75P0016

Masked ROM

0000H - 1F7FH

(8064 x 8 bits)

Masked ROM

0000H - 1FFFH

(8192 x 8 bits)

One-time PROM

0000H - 3FFFH

(16384 x 8 bits)

000H - 1FFH

(512 x 4 bits)

Data memory

CPU

75X standard CPU

31.3 ms

75XL CPU

(equivalent to the 75X high-end CPU)

Oscillation settling time

/f , 2 /f (select-

Fixed to

able by a mask option)

0.95, 1.91, 15.3 µs

(when operating at

4.19 MHz)

When selecting the main

system clock

• 0.95, 1.91, 3.81, 15.3 µs (when operating at 4.19

MHz)

• 0.67, 1.33, 2.67, 10.7 µs (when operating at 6.0 MHz)

122 µs (when operating at 32.768 kHz)

When selecting the subsys-

tem clock

20 (CU)

38 (GB)

24 (CU)

P21

P21/PTO1

42 (GB)

P33 - P30

Not provided

P33/MD3 - P30/MD0

6 - 9 (CU)

23-26 (GB)

SBS register

Provided SBS.3 = 1 : Mk I mode selection

SBS.3 = 0 : Mk II mode selection

000H - 0FFH

2-byte stack

Stack area

n00H - nFFH (n = 0, 1)

Stack operation for a

subroutine call instruction

Mk II mode: 3-byte stack

Mk mode: Not available

mode: 2-byte stack

Not available

BRA !addr1

CALLA !addr1

Mk II mode: Available

MOVT XA, @BCDE

MOVT XA, @BCXA

BR BCDE

Available

BR BCXA

CALL !addr

3 machine cycles

2 machine cycles

machine cycles

Mk mode: 2 machine cycles, Mk II mode: 3

machine cycles

mode: 3 machine cycles, Mk II mode: 4

CALLF !faddr

299

µPD750008 USER'S MANUAL

(2/2)

Item

µPD75008

3 channels

µPD750008

4 channels

µPD75P0016

Timer

• Basic interval timer: 1

• Timer/event counter: 1

• Clock timer: 1

• Basic interval timer/watchdog timer: 1

• Timer/event counter: 1

• Timer/counter: 1

• Clock timer: 1

F, 524, 262, 65.5 kHz

(when the main system

clock operates at 4.19

MHz)

Clock output (PCL)

BUZ output (BUZ)

•

, 524, 262, 65.5 kHz

(when the main system clock operates at 4.19 MHz)

, 750, 375, 93.7 kHz

(when the main system clock operates at 6.0 MHz)

•

2 kHz

• 2, 4, 32 kHz

(when the main system clock operates at 4.19 MHz)

• 2.86, 5.72, 45.8 kHz

(when the main system clock operates at 6.0 MHz)

3 modes supported

Serial interface

• Three-wire serial I/O mode: First transferred bit switchable between the

LSB and MSB

• Two-wire serial I/O mode

• SBI mode

Can incorporate feedback

resistors that are specified

with the mask option.

Feedback resistor cut

flag (SOS.0)

Incorporated

Not provided

Sub-oscillator current cut

flag (SOS.1)

Incorporated

Provided

Not provided

(RBS)

Disable

Standby release with INT0

Enable

External: 3, internal: 3

Number of vectored interrupts

Processor clock control register

External: 3, internal: 4

Available when PCC is 0 to 3

Available when PCC is 0,

2, or 3

V^DD= 2.7 to 6.0 V

Power supply voltage

Operating ambient temperature

Package

V^DD= 2.2 to 5.5 V

= –40 to +85 °C

• 42-pin plastic shrink DIP (600 mil)

• 44-pin plastic QFP (10 x 10 mm)

300

APPENDIX B DEVELOPMENT TOOLS

The following development tools are provided for the development of a system which employs the

µPD750008. In the 75XL series, use the common relocatable assembler together with a device file of each

model.

RA75X relocatable assembler

Host machine

Part number

Distribution media

3.5-inch 2HD

PC-9800 series

MS-DOS

Ver. 3.30

µS5A13RA75X

5.25-inch 2HD

µS5A10RA75X

Note

Ver. 6.2

IBM PC/AT and See "OS for IBM

3.5-inch 2HC

5.25-inch 2HC

µS7B13RA75X

µS7B10RA75X

compatibles

PC."

Device file

Host machine

Part number

Distribution media

3.5-inch 2HD

PC-9800 series

MS-DOS

Ver. 3.30

µS5A13DF750008

5.25-inch 2HD

µS5A10DF750008

Note

Ver. 6.2

IBM PC/AT and See "OS for IBM

compatibles PC."

3.5-inch 2HC

5.25-inch 2HC

µS7B13DF750008

µS7B10DF750008

Note These software products cannot use the task swap function, which is available in MS-DOS Ver. 5.00

or later.

Remark The operations of the assembler and device file are guaranteed only on the above host machines

and OSs.

301

µPD750008 USER'S MANUAL

PROM programming tools

Hardware PG-1500

The PG-1500 PROM programmer is used together with an accessory board and optional

program adapter. It allows the user to program a single chip microcomputer containing

PROM from a standalone terminal or a host machine. The PG-1500 can be used to

program typical 256K-bit to 4M-bit PROMs.

PA-75P008CU

The PA-75P008CU is a PROM programmer adapter provided for the µPD75P008CU/

GB and µPD75P0016CU/GB. It is used in conjunction with the PG-1500.

Software PG-1500

controller

This program enables the host machine to control the PG-1500 through the serial and

parallel interfaces.

Host machine

PC-9800 series

Part number

Distribution media

3.5-inch 2HD

MS-DOS

Ver. 3.30

µS5A13PG1500

5.25-inch 2HD

µS5A10PG1500

Note

Ver. 6.2

IBM PC/AT and

compatibles

See "OS for IBM

PC."

3.5-inch 2HD

5.25-inch 2HC

µS7B13PG1500

µS7B10PG1500

Note These software products cannot use the task swap function, which is available in MS-DOS Ver. 5.00

or later.

Remark Operation of the PG-1500 controller is guaranteed only on the above host machines and OSs.

302

APPENDIX B DEVELOPMENT TOOLS

Debugging Tools

The in-circuit emulators (IE-75000-R and IE-75001-R) are provided to debug programs used for the

µPD750008.

The following system is shown below.

Note 1

IE-75000-R

The IE-75000-R is an in-circuit emulator used to debug hardware and software

when developing an application system using the 75X series and 75XL series.

Use this emulator together with optional emulation board IE-75300-R-EM and

emulation probe to develop application systems of the µPD750008 subseries.

For efficient debugging, connect the emulator to the host machine and a

PROM programmer.

The IE-75000-R contains emulation board IE-75000-R-EM. The board is

connected to the IE-75000-R.

IE-75001-R

The IE-75001-R is an in-circuit emulator used to debug hardware and software

when developing an application system using the 75X series and 75XL series.

Use this emulator together with optional emulation board IE-75300-R-EM and

emulation probe.

For efficient debugging, connect the emulator to the host machine and a

PROM programmer.

Note 2

IE-75300-R-EM

The IE-75300-R-EM is an emulation board used to evaluate an application

system using the µPD750008 subseries.

Use this board together with the IE-75000-R or IE-75001-R.

EP-75008GB-R

The EP-75008GB-R is an emulation probe for the µPD75008GB and

µPD750008GB.

Connect this emulation probe to the IE-75000-R or IE-75001-R, and the IE-

75300-R-EM.

A 44-pin conversion socket, the EV-9200G-44, supplied with this probe facili-

tates the connection of the probe to the target system.

EV-9200G-44

EP-75008CU-R

The EP-75008CU-R is an emulation probe for the µPD75008CU and

µPD750008CU.

Connect this emulation probe to the IE-75000-R or IE-75001-R, and the IE-

75300-R-EM.

This program enables the host machine to control the IE-75000-R or IE-75001-

R through the RS-232-C and Centronics interface.

IE control program

Part number

Host machine

Distribution media

3.5-inch 2HD

MS-DOS

µS5A13IE75X

µS5A10IE75X

Ver. 3.30 to

5.25-inch 2HD

PC-9800 series

Note 3

Ver. 6.2

µS7B13IE75X

µS7B10IE75X

See “OS for

IBM PC.”

3.5-inch 2HC

5.25-inch 2HC

IBM PC/AT and

compatibles

Notes 1. Maintenance service only

2. To be ordered.

3. These software products cannot use the task swap function, which is available in

MS DOS Ver. 5.00 or later.

Remark Operation of the IE control program is guaranteed only on the above host machines and OSs.

303

µPD750008 USER'S MANUAL

OS for IBM PC

The following IBM PC OSs are supported.

Version

PC DOS

Ver. 3.1 to Ver. 6.3

Note

J6.1/V

to J6.3/V

MS-DOS

IBM DOS

Ver. 5.0 to Ver. 6.22

Note

5.0/V

to J6.2/V

Note

J5.02/V

Note

Only English version is supported.

Caution These software products cannot use the task swap function, which is available in MS-DOS

Ver. 5.00 or later.

304

APPENDIX B DEVELOPMENT TOOLS

305

µPD750008 USER'S MANUAL

Drawings of the Conversion Socket (EV-9200G-44) and Recommended Pattern on Boards

Figure B-1. Drawings of the EV-9200G-44 (Reference)

EV-9200G-44-G0

306

APPENDIX B DEVELOPMENT TOOLS

Figure B-2. Recommended Pattern on Boards for the EV-9200G-44 (Reference)

EV-9200G-44-P0

Caution Dimensions of mount pad for EV-9200 and that for target device (QFP) may be different

in some parts. For the recommended mount pad dimensions for QFP, refer to

"SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL" (IEI-1207).

307

µPD750008 USER'S MANUAL

[MEMO]

308

APPENDIX C MASKED ROM ORDERING PROCEDURE

After program development is completed, the masked ROM is ordered by the following procedure:

<1> Advance notice of an order for masked ROM

Give advance notice of masked ROM ordering to a special agent or NEC’s Sales Department,

otherwise the ordered products may be delivered with delay.

<2> Preparation of media for ordering

Use three UV-EPROMs having the same contents, or 3.5- or 5.25-inch IBM format floppy disk in

ordering a masked ROM. (Prepare a mask option information sheet describing the mask option data.)

<3> Preparation of the required documents

Prepare the following documents when ordering a masked ROM:

• Masked ROM order sheet

• Masked ROM order check sheet

• Mask option information sheet

<4> Ordering

Send a set of the media created in<2> and the documents created in<3> to a special agent or NEC’s

Sales Department by the date indicated in the advance notice.

309

µPD750008 USER'S MANUAL

[MEMO]

310

APPENDIX D INSTRUCTION INDEX

D.1 INSTRUCTION INDEX (BY FUNCTION)

[Transfer instructions]

A,#n4 ... 245, 264

MOVT

XA,@PCXA ... 246, 271

XA,@BCDE ... 246, 272

XA,@BCXA ... 246, 272

MOV

XCH

reg1,#n4 ... 245, 265

XA,#n8 ... 245, 265

HL,#n8 ... 245, 265

rp2,#n8 ... 245, 265

A,@HL ... 245, 265

A,@HL+ ... 245, 265

A,@HL– ... 245, 265

A,@rpa1 ... 245, 265

XA,@HL ... 245, 266

@HL,A ... 245, 266

@HL,XA ... 245, 266

A,mem ... 245, 266

XA,mem ... 245, 267

mem,A ... 245, 267

mem,XA ... 245, 267

A,reg ... 245, 267

[Bit transfer instructions]

MOV1

CY,fmem.bit ... 246, 273

CY,pmem.@L ... 246, 273

CY,@H+mem.bit ... 246, 273

fmem.bit,CY ... 246, 273

pmem.@L,CY ... 246, 273

@H+mem.bit,CY ... 246, 273

[Arithmetic/logical instructions]

ADDS

ADDC

SUBS

SUBC

AND

A,#n4 ... 246, 273

XA,#n8 ... 246, 274

A,@HL ... 246, 274

XA,rp’ ... 246, 274

rp’1,XA ... 246, 274

A,@HL ... 246, 274

XA,rp’ ... 246, 275

rp’1,XA ... 246, 275

A,@HL ... 246, 275

XA,rp’ ... 246, 275

rp’1,XA ... 246, 276

A,@HL ... 246, 276

XA,rp’ ... 246, 276

rp’1,XA ... 246, 276

A,#n4 ... 247, 276

A,@HL ... 247, 277

XA,rp’ ... 247, 277

rp’1,XA ... 247, 277

XA,rp’ ... 245, 267

reg1,A ... 245, 268

rp’1,XA ... 245, 268

A,@HL ... 245, 268

A,@HL+ ... 245, 268

A,@HL– ... 245, 268

A,@rpa1 ... 245, 268

XA,@HL ... 245, 269

A,mem ... 245, 269

XA,mem ... 245, 269

A,reg1 ... 245, 269

XA,rp’ ... 245, 269

AND

[Table reference instructions]

MOVT XA,@PCDE ... 246, 270

A,#n4 ... 247, 277

311

µPD750008 USER'S MANUAL

A,@HL ... 247, 277

XA,rp’ ... 247, 277

rp’1,XA ... 247, 278

A,#n4 ... 247, 278

A,@HL ... 247, 278

XA,rp’ ... 247, 278

rp’1,XA ... 247, 278

SET1

CLR1

SKT

pmem.@L ... 248, 282

@H+mem.bit ... 248, 282

mem.bit ... 248, 282

XOR

fmem.bit ... 248, 282

pmem.@L ... 248 282

@H+mem.bit ... 248, 282

mem.bit ... 248, 283

SKT

fmem.bit ... 248, 283

[Accumulator manipulation instructions]

SKT

pmem.@L ... 248, 283

@H+mem.bit ... 248, 283

mem.bit ... 248, 283

RORC

NOT

A ... 247, 279

SKT

SKF

fmem.bit ... 248, 283

[Increment/decrement instructions]

SKF

pmem.@L ... 248, 283

@H+mem.bit ... 248, 283

fmem.bit ... 248, 283

INCS

DECS

reg ... 247, 279

rp1 ... 247, 279

@HL ... 247, 279

mem ... 247, 280

reg ... 247, 280

rp’ ... 247, 280

SKF

SKTCLR

AND1

OR1

pmem.@L ... 248, 283

@H+mem.bit ... 248, 283

CY,fmem.bit ... 248, 284

CY,pmem.@L ... 248, 284

CY,@H+mem.bit ... 248, 284

CY,fmem.bit ... 248, 284

CY,pmem.@L ... 248, 284

CY,@H+mem.bit ... 248, 284

CY,fmem.bit ... 248, 284

CY,pmem,@L ... 248, 284

CY,@H+mem.bit ... 248, 284

[Compare instructions]

SKE

reg,#n4 ... 247, 280

OR1

@HL,#n4 ... 247, 280

A,@HL ... 247, 280

XA,@HL ... 247, 281

A,reg ... 247, 281

OR1

XOR1

XA,rp’ ... 247, 281

[Branch instructions]

[Carry flag manipulation instructions]

addr ... 249, 284

SET1

CLR1

SKT

CY ... 247, 281

CY ... 247, 282

addr1 ... 249, 285

!addr ... 250, 285

$addr ... 250, 285

$addr1 ... 250, 285

PCDE ... 250, 287

PCXA ... 250, 287

BCDE ... 250, 288

BCXA ... 251, 288

NOT1

[Memory bit manipulation instructions]

SET1

mem.bit ... 248, 282

fmem.bit ... 248, 282

312

APPENDIX D INSTRUCTION INDEX

BRA

!addr1 ... 251, 285

!caddr ... 251, 286

addr ... 256, 288

BRCB

TBR

[Subroutine stack control instructions]

CALLA

CALL

!addr1 ... 251, 289

!addr ... 252, 289

!faddr ... 252, 290

!addr ... 256, 290

CALLF

TCALL

RET ... 253, 291

RETS ... 254, 291

RETI ... 254, 292

PUSH

POP

rp ... 255, 292

BS ... 255, 293

rp ... 255, 293

BS ... 255, 293

POP

[Interrupt control instructions]

EI ... 255, 293

IExxx ... 255, 293

DI ... 255, 293

IExxx ... 255, 294

[I/O instructions]

A,PORTn ... 255, 294

XA,PORTn ... 255, 294

PORTn,A ... 255, 294

PORTn,XA ... 255, 294

OUT

[CPU control instructions]

HALT ... 255, 295

STOP ... 255, 295

NOP ... 255, 295

[Special instructions]

SEL

GETI

RBn ... 256, 295

MBn ... 256, 295

taddr ... 256, 296

313

µPD750008 USER'S MANUAL

D.2 INSTRUCTION INDEX (ALPHABETICAL ORDER)

[A]

CLR1

mem.bit ... 248, 282

ADDC

A,@HL ... 246, 274

rp’1,XA .. 246, 275

XA,rp’ ... 246, 275

CLR1

pmem.@L ... 248 282

@H+mem.bit ... 248, 282

ADDC

ADDS

AND

A,#n4 ... 246, 273

[D]

A,@HL ... 246, 274

rp’1,XA ... 246, 274

XA,rp’ ... 246, 274

DECS

reg ... 247, 280

rp’ ... 247, 280

DECS

DI ... 255, 293

XA,#n8 ... 246, 274

A,#n4 ... 247, 276

IExxx ... 255, 294

AND

A,@HL ... 247, 277

rp’1,XA ... 247, 277

XA,rp’ ... 247, 277

[E]

EI ... 255, 293

AND

IExxx ... 255, 293

AND

AND1

CY,fmem.bit ... 248, 284

CY,pmem.@L ... 248, 284

CY,@H+mem.bit ... 248, 284

[G]

GETI

taddr ... 256, 296

[H]

[B]

HALT ... 255, 295

addr ... 249, 284

addr1 ... 249, 285

BCDE ... 250, 288

BCXA ... 251, 288

PCDE ... 250, 287

PCXA ... 250, 287

!addr ... 250, 285

$addr ... 250, 285

$addr1 ... 250, 285

!addr1 ... 251, 285

!caddr ... 251, 286

[I]

A,PORTn ... 255, 294

XA,PORTn ... 255, 294

mem ... 247, 280

reg ... 247, 279

INCS

rp1 ... 247, 279

@HL ... 247, 279

BRA

BRCB

[M]

MOV

A,mem ... 245, 266

A,reg ... 245, 267

A,#n4 ... 245, 264

A,@HL ... 245, 265

A,@HL+ ... 245, 265

A,@HL– ... 245, 265

MOV

[C]

CALL

!addr ... 252, 289

!addr1 ... 251, 289

!faddr ... 252, 290

CY ... 247, 281

CALLA

CALLF

CLR1

fmem.bit ... 248, 282

314

APPENDIX D INSTRUCTION INDEX

MOV

A,@rpa1 ... 245, 265

HL,#n8 ... 245, 265

OR1

OUT

CY,@H+mem.bit ... 248, 284

PORTn,A ... 255, 294

MOV

mem,A ... 245, 267

PORTn,XA ... 255, 294

MOV

mem,XA ... 245, 267

reg1,A ... 245, 268

MOV

[P]

POP

BS ... 255, 293

rp ... 255, 293

BS ... 255, 293

MOV

reg1,#n4 ... 245, 265

rp’1,XA ... 245, 268

POP

MOV

PUSH

MOV

rp2,#n8 ... 245, 265

MOV

XA,mem ... 245, 267

XA,rp’ ... 245, 267

PUSH

rp ... 255, 292

MOV

XA,#n8 ... 245, 265

[R]

MOV

XA,@HL ... 245, 266

@HL,A ... 245, 266

RET ... 253, 291

RETI ... 254, 292

RETS ... 254, 291

MOV

@HL,XA ... 245, 266

XA,@BCDE ... 246, 272

XA,@BCXA ... 246, 272

XA,@PCDE ... 246, 270

XA,@PCXA ... 246, 271

CY,fmem.bit ... 246, 273

CY,pmem.@L ... 246, 273

CY,@H+mem.bit ... 246, 273

fmem.bit,CY ... 246, 273

pmem.@L,CY ... 246, 273

@H+mem.bit,CY ... 246, 273

MOVT

MOV1

RORC

A ... 247, 279

[S]

SEL

MBn ... 256, 295

SEL

RBn ... 256, 295

SET1

SKE

SKF

SKT

CY ... 247, 281

fmem.bit ... 248, 282

mem.bit ... 248, 282

pmem.@L ... 248, 282

@H+mem.bit ... 248, 282

A,reg ... 247, 281

A,@HL ... 247, 280

reg,#n4 ... 247, 280

XA,rp’ ... 247, 281

XA,@HL ... 247, 281

@HL,#n4 ... 247, 280

fmem.bit ... 248, 283

mem.bit ... 248, 283

pmem.@L ... 248, 283

@H+mem.bit ... 248, 283

CY ... 247, 281

[N]

NOP ... 255, 295

NOT

A ... 247, 279

NOT1

CY ... 247, 282

[O]

A,#n4 ... 247, 277

A,@HL ... 247, 277

rp’1,XA ... 247, 278

XA,rp’ ... 247, 277

OR1

CY,fmem.bit ... 248, 284

CY,pmem.@L ... 248, 284

fmem.bit ... 248, 283

mem.bit ... 248, 283

315

µPD750008 USER'S MANUAL

SKT

pmem.@L ... 248, 283

@H+mem.bit ... 248, 283

fmem.bit ... 248, 283

SKT

SKTCLR

pmem.@L ... 248, 283

@H+mem.bit ... 248, 283

STOP ... 255, 295

SUBC

SUBS

A,@HL ... 246, 276

rp’1,XA ... 246, 276

XA,rp’ ... 246, 276

A,@HL ... 246, 275

rp’1,XA ... 246, 276

XA,rp’ ... 246, 275

[T]

TBR

addr ... 256, 288

!addr ... 256, 290

TCALL

[X]

XCH

A,mem ... 245, 269

A,reg1 ... 245, 269

XCH

XOR

XOR1

A,@HL ... 245, 268

A,@HL+ ... 245, 268

A,@HL– ... 245, 268

A,@rpa1 ... 245, 268

XA,mem ... 245, 269

XA,rp’ ... 245, 269

XA,@HL ... 245, 269

A,#n4 ... 247, 278

A,@HL ... 247, 278

rp’1,XA ... 247, 278

XA,rp’ ... 247, 278

CY,fmem.bit ... 248, 284

CY,pmem,@L ... 248, 284

CY,@H+mem.bit ... 248, 284

316

APPENDIX E HARDWARE INDEX

E.1 HARDWARE INDEX (ALPHABETICAL ORDER WITH RESPECT TO THE HARDWARE NAME)

[A]

INT0 interrupt enable flag ... 187

INT0 interrupt request flag ... 187

INT1 edge detection mode register ... 193

INT1 interrupt enable flag ... 187

INT1 interrupt request flag ... 187

INT2 edge detection mode register ... 213

INT2 interrupt enable flag ... 210

INT2 interrupt request flag ... 210

INT4 interrupt enable flag ... 187

INT4 interrupt request flag ... 187

Acknowledge detection flag ... 132

Acknowledge enable bit ... 132

Acknowledge trigger bit ... 132

[B]

Bank select register ... 65

Basic interval timer ... 99

Basic interval timer mode register ... 99

Bit sequential buffer ... 181

BT interrupt enable flag ... 187

BT interrupt request flag ... 187

Bus release detection flag ... 133

Bus release trigger bit ... 133

Busy enable bit ... 132

[K]

Key interrupt input ... 211

[M]

[C]

Memory bank enable flag ... 21, 64

Memory bank select register ... 21, 65

Carry flag ... 62

Clock mode register ... 106

Clock output mode register ... 97

Command detection flag ... 132

Command trigger bit ... 133

[P]

Port 0 to port 8 ... 68

Port mode register group A ... 75

Port mode register group B ... 75

Port mode register group C ... 75

Processor clock control register ... 86

Program counter ... 47

[E]

Edge detection mode register ... 193, 213

[I]

Interrupt enable flag for clock timer ... 210

Interrupt master enable flag ... 189

Interrupt request flag for clock timer ... 210

Interrupt status flag ... 63, 194

INT0 edge detection mode register ... 193

Program status word ... 62

Pull-up resistor specification register

group A ... 82

Pull-up resistor specification register

group B ... 82

317

µPD750008 USER'S MANUAL

[R]

[W]

Wake-up function specification bit ... 128

Watchdog timer enable flag ... 101

[S]

Serial bus interface control register ... 131

Serial interface interrupt enable flag ... 187

Serial interface interrupt request flag ... 187

Serial interface operation enable/disable

specification bit ... 128

Serial operation mode register ... 127

Shift register ... 134

Signal from address comparator ... 128

Skip flag ... 63

Slave address register ... 134

Stack bank select register ... 46, 58

Stack pointer ... 58

Sub-oscillator control register ... 93

System clock control register ... 88

[T]

Timer/counter 1 interrupt enable

flag ... 187

Timer/counter 1 interrupt request

flag ... 187

Timer/counter 1 mode register ... 111

Timer/counter 1 modulo register ... 110

Timer/counter 1 output enable flag ... 114

Timer/counter count 1 register ... 110

Timer/event counter 0 count register ... 109

Timer/event counter 0 interrupt enable

flag ... 187

Timer/event counter 0 interrupt request

flag ... 187

Timer/event counter 0 mode register ... 111

Timer/event counter 0 modulo register ... 109

Timer/event counter 0 output enable

flag ... 114

318

APPENDIX E HARDWARE INDEX

E.2 HARDWARE INDEX (ALPHABETICAL ORDER WITH RESPECT TO THE HARDWARE SYMBOL)

[A]

IRQ1 ... 187

ACKD ... 132

ACKE ... 132

ACKT ... 132

IRQ2 ... 210

IRQ4 ... 187

IRQBT ... 187

IRQCSI ... 187

IRQT0 ... 187

IRQT1 ... 187

IRQW ... 210

IST0 ... 63, 194

IST1 ... 63, 194

[B]

BS ... 65

BSB0-BSB3 ... 181

BSYE ... 132

BT ... 99

BTM ... 99

[K]

[C]

KR0-KR7 ... 211

CLOM ... 97

CMDD ... 132

CMDT ... 133

COI ... 128

CSIE ... 128

CSIM .. 127

CY ... 62

[M]

MBE ... 21, 64

MBS ... 21, 65

[P]

PC ... 47

PCC ... 86

[I]

PMGA ... 75

PMGB ... 75

PMGC ... 75

POGA ... 82

POGB ... 82

PORT0-PORT8 ... 68

PSW ... 62

IE0 ... 187

IE1 ... 187

IE2 ... 210

IE4 ... 187

IEBT ... 187

IECSI ... 187

IET0 ... 187

IET1 ... 187

IEW ... 210

IM0, IM1 ... 193

IM2 ... 213

IME ... 189

IRQ0 ... 187

[R]

RBE ... 34, 64

RBS ... 34, 65

RELD ... 133

RELT ... 133

319

µPD750008 USER'S MANUAL

[S]

SBIC ... 131

SBS ... 46, 58

SCC ... 88

SIO ... 134

SK0, SK1, SK2 ... 63

SOS ... 93

SP ... 58

SVA ... 134

[T]

T0 ... 109

T1 ... 110

TOE0 ... 114

TOE1 ... 114

TM0 ... 112

TM1 ... 113

TMOD0 ... 109

TMOD1 ... 110

[W]

WDTM ... 101

WM ... 106

WUP ... 128

320

APPENDIX F REVISION HISTORY

Major revisions in this edition are shown below. The revised chapters refer to this edition.

Edition

Second

Major revisions from previous edition

Revised chapters

The 44-pin plastic QFP package was changed from

All

µPD750008GB-xxx-3B4 to µPD750008GB-xxx-3BS-MTX.

The µPD75P0016 under development has been changed to the

already-developed µPD75P0016.

The input withstand voltage at ports 4 and 5 during open drain was

changed from 12 V to 13 V.

English-version document numbers was added to "Related

documents."

Preface

The format of the table in Section 1.3 was changed.

Chapter 1

Chapter 4

The caution in using Mk II mode was added in Table 4-1

"Differences between Mk I Mode and Mk II Mode."

The description for the mask option when using the feedback resistor Chapter 5

was added in the section "Sub-oscillator control register."

The description for the interrupt enable flag was added in Section 6.3 Chapter 6

"VARIOUS DEVICES TO CONTROL INTERRUPT FUNCTIONS."

Table 6-4 "Identifying Interrupt Sharing Vector Table Address" was

added in Section 6.6 "PROCESSING OF INTERRUPTS SHARING

A VECTOR ADDRESS."

The description for the screening of one-time PROM was added.

The description for the mask option was added.

Chapter 9

Chapter 10

Chapter 11

The operand @rpa was changed to @rpa1 in Chapter 11

"INSTRUCTION SET."

@rpa1 was added in the table in item (1) "Operand identifier and

description" in Section 11.2 "INSTRUCTION SET AND OPERATION."

The title of Section 11.4 "FUNCTIONS AND APPLICATIONS OF

THE INSTRUCTIONS" was changed to conform to that of Section

11.2 "INSTRUCTION SET AND OPERATION."

Supported OS versions were upgraded

Appendix B

321

µPD750008 USER'S MANUAL

[MEMO]

322

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